[Pkg-clamav-commits] [SCM] Debian repository for ClamAV branch, debian/unstable, updated. debian/0.95+dfsg-1-6156-g094ec9b
Török Edvin
edwin at clamav.net
Sun Apr 4 01:23:46 UTC 2010
The following commit has been merged in the debian/unstable branch:
commit 5d2a1c488f8b44b39d5111957114d4d623af1b3b
Author: Török Edvin <edwin at clamav.net>
Date: Mon Mar 22 11:42:27 2010 +0200
Update autogenerated files.
diff --git a/libclamav/c++/ARMGenAsmWriter.inc b/libclamav/c++/ARMGenAsmWriter.inc
index 7a289a3..9eef864 100644
--- a/libclamav/c++/ARMGenAsmWriter.inc
+++ b/libclamav/c++/ARMGenAsmWriter.inc
@@ -76,1943 +76,1948 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
337150054U, // BL_pred
402653277U, // BLr9
337150054U, // BLr9_pred
- 69206121U, // BRIND
- 67108973U, // BR_JTadd
- 485007478U, // BR_JTm
- 82362495U, // BR_JTr
- 69206152U, // BX
- 337141912U, // BXJ
- 552599708U, // BX_RET
- 69206152U, // BXr9
- 337141919U, // Bcc
- 620290209U, // CDP
- 687866021U, // CDP2
- 172U, // CLREX
- 739795122U, // CLZ
- 739795126U, // CMNzri
- 739795126U, // CMNzrr
- 806903990U, // CMNzrs
- 739795130U, // CMPri
- 739795130U, // CMPrr
- 806903994U, // CMPrs
- 739795130U, // CMPzri
- 739795130U, // CMPzrr
- 806903994U, // CMPzrs
+ 69206121U, // BMOVPCRX
+ 69206121U, // BMOVPCRXr9
+ 69206142U, // BRIND
+ 67108994U, // BR_JTadd
+ 485007499U, // BR_JTm
+ 82362516U, // BR_JTr
+ 69206173U, // BX
+ 337141933U, // BXJ
+ 552599729U, // BX_RET
+ 69206173U, // BXr9
+ 337141940U, // Bcc
+ 620290230U, // CDP
+ 687866042U, // CDP2
+ 193U, // CLREX
+ 739795143U, // CLZ
+ 739795147U, // CMNzri
+ 739795147U, // CMNzrr
+ 806904011U, // CMNzrs
+ 739795151U, // CMPri
+ 739795151U, // CMPrr
+ 806904015U, // CMPrs
+ 739795151U, // CMPzri
+ 739795151U, // CMPzrr
+ 806904015U, // CMPzrs
872415304U, // CONSTPOOL_ENTRY
- 939524286U, // CPS
- 337141954U, // DBG
- 198U, // DMBish
- 206U, // DMBishst
- 216U, // DMBnsh
- 224U, // DMBnshst
- 234U, // DMBosh
- 242U, // DMBoshst
- 252U, // DMBst
- 259U, // DSBish
- 267U, // DSBishst
- 277U, // DSBnsh
- 285U, // DSBnshst
- 295U, // DSBosh
- 303U, // DSBoshst
- 313U, // DSBst
- 134750528U, // EORri
- 134758720U, // EORrr
- 202375488U, // EORrs
- 755556676U, // FCONSTD
- 756080964U, // FCONSTS
- 555221321U, // FMSTAT
- 334U, // ISBsy
- 85983570U, // Int_MemBarrierV6
- 351U, // Int_MemBarrierV7
- 86507858U, // Int_SyncBarrierV6
- 355U, // Int_SyncBarrierV7
- 87032167U, // Int_eh_sjlj_setjmp
- 221831537U, // LDC2L_OFFSET
- 825819505U, // LDC2L_OPTION
- 221839729U, // LDC2L_POST
- 221831537U, // LDC2L_PRE
- 217653617U, // LDC2_OFFSET
- 821633393U, // LDC2_OPTION
- 217653617U, // LDC2_POST
- 217653617U, // LDC2_PRE
- 221831542U, // LDCL_OFFSET
- 825819510U, // LDCL_OPTION
- 221839734U, // LDCL_POST
- 221831542U, // LDCL_PRE
- 217653622U, // LDC_OFFSET
- 821633398U, // LDC_OPTION
- 217653622U, // LDC_POST
- 217653622U, // LDC_PRE
- 1027686778U, // LDM
- 1027686778U, // LDM_RET
- 806904190U, // LDR
- 806904194U, // LDRB
- 202924423U, // LDRBT
- 202924418U, // LDRB_POST
- 202924418U, // LDRB_PRE
- 202924429U, // LDRD
- 605577613U, // LDRD_POST
- 605577613U, // LDRD_PRE
- 739795346U, // LDREX
- 739795352U, // LDREXB
- 135815583U, // LDREXD
- 739795366U, // LDREXH
- 806904237U, // LDRH
- 202924466U, // LDRHT
- 202924461U, // LDRH_POST
- 202924461U, // LDRH_PRE
- 806904248U, // LDRSB
- 202924478U, // LDRSBT
- 202924472U, // LDRSB_POST
- 202924472U, // LDRSB_PRE
- 806904261U, // LDRSH
- 202924491U, // LDRSHT
- 202924485U, // LDRSH_POST
- 202924485U, // LDRSH_PRE
- 202924498U, // LDRT
- 202924414U, // LDR_POST
- 202924414U, // LDR_PRE
- 806904190U, // LDRcp
- 1095238103U, // LEApcrel
- 1095762391U, // LEApcrelJT
- 620290525U, // MCR
- 671105505U, // MCR2
- 217637352U, // MCRR
- 671105517U, // MCRR2
- 827851253U, // MLA
- 806904313U, // MLS
- 135815677U, // MOVCCi
- 135815677U, // MOVCCr
- 202924541U, // MOVCCs
- 135815681U, // MOVTi16
- 761356797U, // MOVi
- 739795462U, // MOVi16
- 739795453U, // MOVi2pieces
- 739795462U, // MOVi32imm
- 761266685U, // MOVr
- 761266685U, // MOVrx
- 827949565U, // MOVs
- 739795467U, // MOVsra_flag
- 739795467U, // MOVsrl_flag
- 620290576U, // MRC
- 671105556U, // MRC2
- 217637403U, // MRRC
- 671105568U, // MRRC2
- 337142312U, // MRS
- 337142312U, // MRSsys
- 359162412U, // MSR
- 359244332U, // MSRi
- 359686700U, // MSRsys
- 359768620U, // MSRsysi
- 134758960U, // MUL
- 761356852U, // MVNi
- 761266740U, // MVNr
- 827949620U, // MVNs
- 538968632U, // NOP
- 134750780U, // ORRri
- 134758972U, // ORRrr
- 202375740U, // ORRrs
- 1165492800U, // PICADD
- 1233125952U, // PICLDR
- 1233650240U, // PICLDRB
- 1234174528U, // PICLDRH
- 1234698816U, // PICLDRSB
- 1235223104U, // PICLDRSH
- 1235747392U, // PICSTR
- 1236271680U, // PICSTRB
- 1236795968U, // PICSTRH
- 806904386U, // PKHBT
- 806904392U, // PKHTB
- 67109454U, // PLDWi
- 471859797U, // PLDWr
- 67109467U, // PLDi
- 471859809U, // PLDr
- 67109478U, // PLIi
- 471859820U, // PLIr
- 135815793U, // QADD
- 135815798U, // QADD16
- 135815805U, // QADD8
- 135815811U, // QASX
- 135815816U, // QDADD
- 135815822U, // QDSUB
- 135815828U, // QSAX
- 135815833U, // QSUB
- 135815838U, // QSUB16
- 135815845U, // QSUB8
- 739795627U, // RBIT
- 739795632U, // REV
- 739795636U, // REV16
- 739795642U, // REVSH
- 1008222912U, // RFE
- 1008222912U, // RFEW
- 135815876U, // RSBSri
- 202924740U, // RSBSrs
- 134750921U, // RSBri
- 202375881U, // RSBrs
- 67109581U, // RSCSri
- 67109581U, // RSCSrs
- 134750931U, // RSCri
- 202375891U, // RSCrs
- 135815895U, // SADD16
- 135815902U, // SADD8
- 135815908U, // SASX
- 67109609U, // SBCSSri
- 67109609U, // SBCSSrr
- 67109609U, // SBCSSrs
- 134750959U, // SBCri
- 134759151U, // SBCrr
- 202375919U, // SBCrs
- 806904563U, // SBFX
- 135815928U, // SEL
- 764U, // SETENDBE
- 774U, // SETENDLE
- 538968848U, // SEV
- 135815956U, // SHADD16
- 135815964U, // SHADD8
- 135815971U, // SHASX
- 135815977U, // SHSAX
- 135815983U, // SHSUB16
- 135815991U, // SHSUB8
- 337142590U, // SMC
- 806904642U, // SMLABB
- 806904649U, // SMLABT
- 806904656U, // SMLAD
- 806904662U, // SMLADX
- 827851613U, // SMLAL
- 806904675U, // SMLALBB
- 806904683U, // SMLALBT
- 806904691U, // SMLALD
- 806904698U, // SMLALDX
- 806904706U, // SMLALTB
- 806904714U, // SMLALTT
- 806904722U, // SMLATB
- 806904729U, // SMLATT
- 806904736U, // SMLAWB
- 806904743U, // SMLAWT
- 806904750U, // SMLSD
- 806904756U, // SMLSDX
- 806904763U, // SMLSLD
- 806904770U, // SMLSLDX
- 806904778U, // SMMLA
- 806904784U, // SMMLAR
- 806904791U, // SMMLS
- 806904797U, // SMMLSR
- 135816164U, // SMMUL
- 135816170U, // SMMULR
- 135816177U, // SMUAD
- 135816183U, // SMUADX
- 135816190U, // SMULBB
- 135816197U, // SMULBT
- 827851788U, // SMULL
- 135816210U, // SMULTB
- 135816217U, // SMULTT
- 135816224U, // SMULWB
- 135816231U, // SMULWT
- 135816238U, // SMUSD
- 135816244U, // SMUSDX
- 1036010555U, // SRS
- 1036534843U, // SRSW
- 135816255U, // SSAT16
- 806904902U, // SSATasr
- 806904902U, // SSATlsl
- 135816267U, // SSAX
- 135816272U, // SSUB16
- 135816279U, // SSUB8
- 221832285U, // STC2L_OFFSET
- 825820253U, // STC2L_OPTION
- 221840477U, // STC2L_POST
- 221832285U, // STC2L_PRE
- 217654365U, // STC2_OFFSET
- 821634141U, // STC2_OPTION
- 217654365U, // STC2_POST
- 217654365U, // STC2_PRE
- 221832290U, // STCL_OFFSET
- 825820258U, // STCL_OPTION
- 221840482U, // STCL_POST
- 221832290U, // STCL_PRE
- 217654370U, // STC_OFFSET
- 821634146U, // STC_OPTION
- 217654370U, // STC_POST
- 217654370U, // STC_PRE
- 1027687526U, // STM
- 806904938U, // STR
- 806904942U, // STRB
- 202900595U, // STRBT
- 202900590U, // STRB_POST
- 202900590U, // STRB_PRE
- 202925177U, // STRD
- 605553785U, // STRD_POST
- 605553785U, // STRD_PRE
- 135816318U, // STREX
- 135816324U, // STREXB
- 806904971U, // STREXD
- 135816338U, // STREXH
- 806904985U, // STRH
- 202900638U, // STRHT
- 202900633U, // STRH_POST
- 202900633U, // STRH_PRE
- 202900644U, // STRT
- 202900586U, // STR_POST
- 202900586U, // STR_PRE
- 135816361U, // SUBSri
- 135816361U, // SUBSrr
- 202925225U, // SUBSrs
- 134751406U, // SUBri
- 134759598U, // SUBrr
- 202376366U, // SUBrs
- 337142962U, // SVC
- 135816374U, // SWP
- 135816378U, // SWPB
- 135816383U, // SXTAB16rr
- 806905023U, // SXTAB16rr_rot
- 135816391U, // SXTABrr
- 806905031U, // SXTABrr_rot
- 135816397U, // SXTAHrr
- 806905037U, // SXTAHrr_rot
- 739796179U, // SXTB16r
- 135816403U, // SXTB16r_rot
- 739796186U, // SXTBr
- 135816410U, // SXTBr_rot
- 739796191U, // SXTHr
- 135816415U, // SXTHr_rot
- 739796196U, // TEQri
- 739796196U, // TEQrr
- 806905060U, // TEQrs
- 1256U, // TPsoft
- 538969339U, // TRAP
- 739796224U, // TSTri
- 739796224U, // TSTrr
- 806905088U, // TSTrs
- 135816452U, // UADD16
- 135816459U, // UADD8
- 135816465U, // UASX
- 806905110U, // UBFX
- 135816475U, // UHADD16
- 135816483U, // UHADD8
- 135816490U, // UHASX
- 135816496U, // UHSAX
- 135816502U, // UHSUB16
- 135816510U, // UHSUB8
- 806905157U, // UMAAL
- 827852107U, // UMLAL
- 827852113U, // UMULL
- 135816535U, // UQADD16
- 135816543U, // UQADD8
- 135816550U, // UQASX
- 135816556U, // UQSAX
- 135816562U, // UQSUB16
- 135816570U, // UQSUB8
- 135816577U, // USAD8
- 806905223U, // USADA8
- 135816590U, // USAT16
- 806905237U, // USATasr
- 806905237U, // USATlsl
- 135816602U, // USAX
- 135816607U, // USUB16
- 135816614U, // USUB8
- 135816620U, // UXTAB16rr
- 806905260U, // UXTAB16rr_rot
- 135816628U, // UXTABrr
- 806905268U, // UXTABrr_rot
- 135816634U, // UXTAHrr
- 806905274U, // UXTAHrr_rot
- 739796416U, // UXTB16r
- 135816640U, // UXTB16r_rot
- 739796423U, // UXTBr
- 135816647U, // UXTBr_rot
- 739796428U, // UXTHr
- 135816652U, // UXTHr_rot
- 835732945U, // VABALsv2i64
- 836257233U, // VABALsv4i32
- 836781521U, // VABALsv8i16
- 837305809U, // VABALuv2i64
- 837830097U, // VABALuv4i32
- 838354385U, // VABALuv8i16
- 836781527U, // VABAsv16i8
- 835732951U, // VABAsv2i32
- 836257239U, // VABAsv4i16
- 835732951U, // VABAsv4i32
- 836257239U, // VABAsv8i16
- 836781527U, // VABAsv8i8
- 838354391U, // VABAuv16i8
- 837305815U, // VABAuv2i32
- 837830103U, // VABAuv4i16
- 837305815U, // VABAuv4i32
- 837830103U, // VABAuv8i16
- 838354391U, // VABAuv8i8
- 164627932U, // VABDLsv2i64
- 165152220U, // VABDLsv4i32
- 165676508U, // VABDLsv8i16
- 166200796U, // VABDLuv2i64
- 166725084U, // VABDLuv4i32
- 167249372U, // VABDLuv8i16
- 152102370U, // VABDfd
- 152102370U, // VABDfq
- 165676514U, // VABDsv16i8
- 164627938U, // VABDsv2i32
- 165152226U, // VABDsv4i16
- 164627938U, // VABDsv4i32
- 165152226U, // VABDsv8i16
- 165676514U, // VABDsv8i8
- 167249378U, // VABDuv16i8
- 166200802U, // VABDuv2i32
- 166725090U, // VABDuv4i16
- 166200802U, // VABDuv4i32
- 166725090U, // VABDuv8i16
- 167249378U, // VABDuv8i8
- 755557863U, // VABSD
- 756082151U, // VABSS
- 756082151U, // VABSfd
- 756082151U, // VABSfd_sfp
- 756082151U, // VABSfq
- 769656295U, // VABSv16i8
- 768607719U, // VABSv2i32
- 769132007U, // VABSv4i16
- 768607719U, // VABSv4i32
- 769132007U, // VABSv8i16
- 769656295U, // VABSv8i8
- 152102380U, // VACGEd
- 152102380U, // VACGEq
- 152102386U, // VACGTd
- 152102386U, // VACGTq
- 151578104U, // VADDD
- 167773693U, // VADDHNv2i32
- 168297981U, // VADDHNv4i16
- 168822269U, // VADDHNv8i8
- 164627972U, // VADDLsv2i64
- 165152260U, // VADDLsv4i32
- 165676548U, // VADDLsv8i16
- 166200836U, // VADDLuv2i64
- 166725124U, // VADDLuv4i32
- 167249412U, // VADDLuv8i16
- 152102392U, // VADDS
- 164627978U, // VADDWsv2i64
- 165152266U, // VADDWsv4i32
- 165676554U, // VADDWsv8i16
- 166200842U, // VADDWuv2i64
- 166725130U, // VADDWuv4i32
- 167249418U, // VADDWuv8i16
- 152102392U, // VADDfd
- 152102392U, // VADDfd_sfp
- 152102392U, // VADDfq
- 169346552U, // VADDv16i8
- 167773688U, // VADDv1i64
- 168297976U, // VADDv2i32
- 167773688U, // VADDv2i64
- 168822264U, // VADDv4i16
- 168297976U, // VADDv4i32
- 168822264U, // VADDv8i16
- 169346552U, // VADDv8i8
- 135816720U, // VANDd
- 135816720U, // VANDq
- 135816725U, // VBICd
- 135816725U, // VBICq
- 806905370U, // VBIFd
- 806905370U, // VBIFq
- 806905375U, // VBITd
- 806905375U, // VBITq
- 806905380U, // VBSLd
- 806905380U, // VBSLq
- 152102441U, // VCEQfd
- 152102441U, // VCEQfq
- 169346601U, // VCEQv16i8
- 168298025U, // VCEQv2i32
- 168822313U, // VCEQv4i16
- 168298025U, // VCEQv4i32
- 168822313U, // VCEQv8i16
- 169346601U, // VCEQv8i8
- 773326377U, // VCEQzv16i8
- 756082217U, // VCEQzv2f32
- 772277801U, // VCEQzv2i32
- 756082217U, // VCEQzv4f32
- 772802089U, // VCEQzv4i16
- 772277801U, // VCEQzv4i32
- 772802089U, // VCEQzv8i16
- 773326377U, // VCEQzv8i8
- 152102446U, // VCGEfd
- 152102446U, // VCGEfq
- 165676590U, // VCGEsv16i8
- 164628014U, // VCGEsv2i32
- 165152302U, // VCGEsv4i16
- 164628014U, // VCGEsv4i32
- 165152302U, // VCGEsv8i16
- 165676590U, // VCGEsv8i8
- 167249454U, // VCGEuv16i8
- 166200878U, // VCGEuv2i32
- 166725166U, // VCGEuv4i16
- 166200878U, // VCGEuv4i32
- 166725166U, // VCGEuv8i16
- 167249454U, // VCGEuv8i8
- 769656366U, // VCGEzv16i8
- 756082222U, // VCGEzv2f32
- 768607790U, // VCGEzv2i32
- 756082222U, // VCGEzv4f32
- 769132078U, // VCGEzv4i16
- 768607790U, // VCGEzv4i32
- 769132078U, // VCGEzv8i16
- 769656366U, // VCGEzv8i8
- 152102451U, // VCGTfd
- 152102451U, // VCGTfq
- 165676595U, // VCGTsv16i8
- 164628019U, // VCGTsv2i32
- 165152307U, // VCGTsv4i16
- 164628019U, // VCGTsv4i32
- 165152307U, // VCGTsv8i16
- 165676595U, // VCGTsv8i8
- 167249459U, // VCGTuv16i8
- 166200883U, // VCGTuv2i32
- 166725171U, // VCGTuv4i16
- 166200883U, // VCGTuv4i32
- 166725171U, // VCGTuv8i16
- 167249459U, // VCGTuv8i8
- 769656371U, // VCGTzv16i8
- 756082227U, // VCGTzv2f32
- 768607795U, // VCGTzv2i32
- 756082227U, // VCGTzv4f32
- 769132083U, // VCGTzv4i16
- 768607795U, // VCGTzv4i32
- 769132083U, // VCGTzv8i16
- 769656371U, // VCGTzv8i8
- 769656376U, // VCLEzv16i8
- 756082232U, // VCLEzv2f32
- 768607800U, // VCLEzv2i32
- 756082232U, // VCLEzv4f32
- 769132088U, // VCLEzv4i16
- 768607800U, // VCLEzv4i32
- 769132088U, // VCLEzv8i16
- 769656376U, // VCLEzv8i8
- 769656381U, // VCLSv16i8
- 768607805U, // VCLSv2i32
- 769132093U, // VCLSv4i16
- 768607805U, // VCLSv4i32
- 769132093U, // VCLSv8i16
- 769656381U, // VCLSv8i8
- 769656386U, // VCLTzv16i8
- 756082242U, // VCLTzv2f32
- 768607810U, // VCLTzv2i32
- 756082242U, // VCLTzv4f32
- 769132098U, // VCLTzv4i16
- 768607810U, // VCLTzv4i32
- 769132098U, // VCLTzv8i16
- 769656386U, // VCLTzv8i8
- 773326407U, // VCLZv16i8
- 772277831U, // VCLZv2i32
- 772802119U, // VCLZv4i16
- 772277831U, // VCLZv4i32
- 772802119U, // VCLZv8i16
- 773326407U, // VCLZv8i8
- 755557964U, // VCMPD
- 755557969U, // VCMPED
- 756082257U, // VCMPES
- 352962129U, // VCMPEZD
- 353486417U, // VCMPEZS
- 756082252U, // VCMPS
- 352962124U, // VCMPZD
- 353486412U, // VCMPZS
- 773875287U, // VCNTd
- 773875287U, // VCNTq
- 774375004U, // VCVTBHS
- 774899292U, // VCVTBSH
- 775423586U, // VCVTDS
- 775947874U, // VCVTSD
- 774375015U, // VCVTTHS
- 774899303U, // VCVTTSH
- 776595042U, // VCVTf2sd
- 776595042U, // VCVTf2sd_sfp
- 776595042U, // VCVTf2sq
- 777119330U, // VCVTf2ud
- 777119330U, // VCVTf2ud_sfp
- 777119330U, // VCVTf2uq
- 172549730U, // VCVTf2xsd
- 172549730U, // VCVTf2xsq
- 173074018U, // VCVTf2xud
- 173074018U, // VCVTf2xuq
- 777643618U, // VCVTs2fd
- 777643618U, // VCVTs2fd_sfp
- 777643618U, // VCVTs2fq
- 778167906U, // VCVTu2fd
- 778167906U, // VCVTu2fd_sfp
- 778167906U, // VCVTu2fq
- 173598306U, // VCVTxs2fd
- 173598306U, // VCVTxs2fq
- 174122594U, // VCVTxu2fd
- 174122594U, // VCVTxu2fq
- 151578221U, // VDIVD
- 152102509U, // VDIVS
- 778593906U, // VDUP16d
- 778593906U, // VDUP16q
- 779118194U, // VDUP32d
- 779118194U, // VDUP32q
- 773875314U, // VDUP8d
- 773875314U, // VDUP8q
- 174614130U, // VDUPLN16d
- 174614130U, // VDUPLN16q
- 175138418U, // VDUPLN32d
- 175138418U, // VDUPLN32q
- 169895538U, // VDUPLN8d
- 169895538U, // VDUPLN8q
- 175138418U, // VDUPLNfd
- 175138418U, // VDUPLNfq
- 779118194U, // VDUPfd
- 779118194U, // VDUPfdf
- 779118194U, // VDUPfq
- 779118194U, // VDUPfqf
- 135816823U, // VEORd
- 135816823U, // VEORq
- 845702780U, // VEXTd16
- 846227068U, // VEXTd32
- 840984188U, // VEXTd8
- 846227068U, // VEXTdf
- 845702780U, // VEXTq16
- 846227068U, // VEXTq32
- 840984188U, // VEXTq8
- 846227068U, // VEXTqf
- 175137092U, // VGETLNi32
- 165151044U, // VGETLNs16
- 165675332U, // VGETLNs8
- 166723908U, // VGETLNu16
- 167248196U, // VGETLNu8
- 165676673U, // VHADDsv16i8
- 164628097U, // VHADDsv2i32
- 165152385U, // VHADDsv4i16
- 164628097U, // VHADDsv4i32
- 165152385U, // VHADDsv8i16
- 165676673U, // VHADDsv8i8
- 167249537U, // VHADDuv16i8
- 166200961U, // VHADDuv2i32
- 166725249U, // VHADDuv4i16
- 166200961U, // VHADDuv4i32
- 166725249U, // VHADDuv8i16
- 167249537U, // VHADDuv8i8
- 165676679U, // VHSUBsv16i8
- 164628103U, // VHSUBsv2i32
- 165152391U, // VHSUBsv4i16
- 164628103U, // VHSUBsv4i32
- 165152391U, // VHSUBsv8i16
- 165676679U, // VHSUBsv8i8
- 167249543U, // VHSUBuv16i8
- 166200967U, // VHSUBuv2i32
- 166725255U, // VHSUBuv4i16
- 166200967U, // VHSUBuv4i32
- 166725255U, // VHSUBuv8i16
- 167249543U, // VHSUBuv8i8
- 242771597U, // VLD1d16
- 1316513421U, // VLD1d16Q
- 1383622285U, // VLD1d16T
- 243295885U, // VLD1d32
- 1317037709U, // VLD1d32Q
- 1384146573U, // VLD1d32T
- 243820173U, // VLD1d64
- 244344461U, // VLD1d8
- 1318086285U, // VLD1d8Q
- 1385195149U, // VLD1d8T
- 243295885U, // VLD1df
- 241829517U, // VLD1q16
- 242353805U, // VLD1q32
- 244975245U, // VLD1q64
- 237110925U, // VLD1q8
- 242353805U, // VLD1qf
- 1450731154U, // VLD2LNd16
- 1451255442U, // VLD2LNd32
- 1452304018U, // VLD2LNd8
- 1450731154U, // VLD2LNq16a
- 1450731154U, // VLD2LNq16b
- 1451255442U, // VLD2LNq32a
- 1451255442U, // VLD2LNq32b
- 645424786U, // VLD2d16
- 645424786U, // VLD2d16D
- 645949074U, // VLD2d32
- 645949074U, // VLD2d32D
- 646473357U, // VLD2d64
- 646997650U, // VLD2d8
- 646997650U, // VLD2d8D
- 1316513426U, // VLD2q16
- 1317037714U, // VLD2q32
- 1318086290U, // VLD2q8
- 1517840023U, // VLD3LNd16
- 1518364311U, // VLD3LNd32
- 1519412887U, // VLD3LNd8
- 1517840023U, // VLD3LNq16a
- 1517840023U, // VLD3LNq16b
- 1518364311U, // VLD3LNq32a
- 1518364311U, // VLD3LNq32b
- 1383622295U, // VLD3d16
- 1384146583U, // VLD3d32
- 1384670861U, // VLD3d64
- 1385195159U, // VLD3d8
- 1316513431U, // VLD3q16a
- 1316513431U, // VLD3q16b
- 1317037719U, // VLD3q32a
- 1317037719U, // VLD3q32b
- 1318086295U, // VLD3q8a
- 1318086295U, // VLD3q8b
- 1584948892U, // VLD4LNd16
- 1585473180U, // VLD4LNd32
- 1586521756U, // VLD4LNd8
- 1584948892U, // VLD4LNq16a
- 1584948892U, // VLD4LNq16b
- 1585473180U, // VLD4LNq32a
- 1585473180U, // VLD4LNq32b
- 1316513436U, // VLD4d16
- 1317037724U, // VLD4d32
- 1317561997U, // VLD4d64
- 1318086300U, // VLD4d8
- 1450731164U, // VLD4q16a
- 1450731164U, // VLD4q16b
- 1451255452U, // VLD4q32a
- 1451255452U, // VLD4q32b
- 1452304028U, // VLD4q8a
- 1452304028U, // VLD4q8b
- 1610614433U, // VLDMD
- 1610614433U, // VLDMS
- 177759910U, // VLDRD
- 135931563U, // VLDRQ
- 175138470U, // VLDRS
- 152102578U, // VMAXfd
- 152102578U, // VMAXfd_sfp
- 152102578U, // VMAXfq
- 165676722U, // VMAXsv16i8
- 164628146U, // VMAXsv2i32
- 165152434U, // VMAXsv4i16
- 164628146U, // VMAXsv4i32
- 165152434U, // VMAXsv8i16
- 165676722U, // VMAXsv8i8
- 167249586U, // VMAXuv16i8
- 166201010U, // VMAXuv2i32
- 166725298U, // VMAXuv4i16
- 166201010U, // VMAXuv4i32
- 166725298U, // VMAXuv8i16
- 167249586U, // VMAXuv8i8
- 152102583U, // VMINfd
- 152102583U, // VMINfd_sfp
- 152102583U, // VMINfq
- 165676727U, // VMINsv16i8
- 164628151U, // VMINsv2i32
- 165152439U, // VMINsv4i16
- 164628151U, // VMINsv4i32
- 165152439U, // VMINsv8i16
- 165676727U, // VMINsv8i8
- 167249591U, // VMINuv16i8
- 166201015U, // VMINuv2i32
- 166725303U, // VMINuv4i16
- 166201015U, // VMINuv4i32
- 166725303U, // VMINuv8i16
- 167249591U, // VMINuv8i8
- 822666940U, // VMLAD
- 231753409U, // VMLALslsv2i32
- 232277697U, // VMLALslsv4i16
- 233326273U, // VMLALsluv2i32
- 233850561U, // VMLALsluv4i16
- 835733185U, // VMLALsv2i64
- 836257473U, // VMLALsv4i32
- 836781761U, // VMLALsv8i16
- 837306049U, // VMLALuv2i64
- 837830337U, // VMLALuv4i32
- 838354625U, // VMLALuv8i16
- 823191228U, // VMLAS
- 823191228U, // VMLAfd
- 823191228U, // VMLAfq
- 219211452U, // VMLAslfd
- 219211452U, // VMLAslfq
- 235423420U, // VMLAslv2i32
- 235947708U, // VMLAslv4i16
- 235423420U, // VMLAslv4i32
- 235947708U, // VMLAslv8i16
- 840451772U, // VMLAv16i8
- 839403196U, // VMLAv2i32
- 839927484U, // VMLAv4i16
- 839403196U, // VMLAv4i32
- 839927484U, // VMLAv8i16
- 840451772U, // VMLAv8i8
- 822666951U, // VMLSD
- 231753420U, // VMLSLslsv2i32
- 232277708U, // VMLSLslsv4i16
- 233326284U, // VMLSLsluv2i32
- 233850572U, // VMLSLsluv4i16
- 835733196U, // VMLSLsv2i64
- 836257484U, // VMLSLsv4i32
- 836781772U, // VMLSLsv8i16
- 837306060U, // VMLSLuv2i64
- 837830348U, // VMLSLuv4i32
- 838354636U, // VMLSLuv8i16
- 823191239U, // VMLSS
- 823191239U, // VMLSfd
- 823191239U, // VMLSfq
- 219211463U, // VMLSslfd
- 219211463U, // VMLSslfq
- 235423431U, // VMLSslv2i32
- 235947719U, // VMLSslv4i16
- 235423431U, // VMLSslv4i32
- 235947719U, // VMLSslv8i16
- 840451783U, // VMLSv16i8
- 839403207U, // VMLSv2i32
- 839927495U, // VMLSv4i16
- 839403207U, // VMLSv4i32
- 839927495U, // VMLSv8i16
- 840451783U, // VMLSv8i8
- 755556676U, // VMOVD
- 135815492U, // VMOVDRR
- 151576900U, // VMOVDcc
- 739795268U, // VMOVDneon
- 768607954U, // VMOVLsv2i64
- 769132242U, // VMOVLsv4i32
- 769656530U, // VMOVLsv8i16
- 770180818U, // VMOVLuv2i64
- 770705106U, // VMOVLuv4i32
- 771229394U, // VMOVLuv8i16
- 771753688U, // VMOVNv2i32
- 772277976U, // VMOVNv4i16
- 772802264U, // VMOVNv8i8
- 739795268U, // VMOVQ
- 135815492U, // VMOVRRD
- 806904132U, // VMOVRRS
- 739795268U, // VMOVRS
- 756080964U, // VMOVS
- 739795268U, // VMOVSR
- 806904132U, // VMOVSRR
- 152101188U, // VMOVScc
- 773472580U, // VMOVv16i8
- 771907908U, // VMOVv1i64
- 772440388U, // VMOVv2i32
- 771907908U, // VMOVv2i64
- 772972868U, // VMOVv4i16
- 772440388U, // VMOVv4i32
- 772972868U, // VMOVv8i16
- 773472580U, // VMOVv8i8
- 337142089U, // VMRS
- 379586270U, // VMSR
- 151578339U, // VMULD
- 178783976U, // VMULLp
- 835716840U, // VMULLslsv2i32
- 836241128U, // VMULLslsv4i16
- 837289704U, // VMULLsluv2i32
- 837813992U, // VMULLsluv4i16
- 164628200U, // VMULLsv2i64
- 165152488U, // VMULLsv4i32
- 165676776U, // VMULLsv8i16
- 166201064U, // VMULLuv2i64
- 166725352U, // VMULLuv4i32
- 167249640U, // VMULLuv8i16
- 152102627U, // VMULS
- 152102627U, // VMULfd
- 152102627U, // VMULfd_sfp
- 152102627U, // VMULfq
- 178783971U, // VMULpd
- 178783971U, // VMULpq
- 823191267U, // VMULslfd
- 823191267U, // VMULslfq
- 839386851U, // VMULslv2i32
- 839911139U, // VMULslv4i16
- 839386851U, // VMULslv4i32
- 839911139U, // VMULslv8i16
- 169346787U, // VMULv16i8
- 168298211U, // VMULv2i32
- 168822499U, // VMULv4i16
- 168298211U, // VMULv4i32
- 168822499U, // VMULv8i16
- 169346787U, // VMULv8i8
- 739796718U, // VMVNd
- 739796718U, // VMVNq
- 755558131U, // VNEGD
- 151578355U, // VNEGDcc
- 756082419U, // VNEGS
- 152102643U, // VNEGScc
- 756082419U, // VNEGf32q
- 756082419U, // VNEGfd
- 756082419U, // VNEGfd_sfp
- 769132275U, // VNEGs16d
- 769132275U, // VNEGs16q
- 768607987U, // VNEGs32d
- 768607987U, // VNEGs32q
- 769656563U, // VNEGs8d
- 769656563U, // VNEGs8q
- 822667000U, // VNMLAD
- 823191288U, // VNMLAS
- 822667006U, // VNMLSD
- 823191294U, // VNMLSS
- 151578372U, // VNMULD
- 152102660U, // VNMULS
- 135816970U, // VORNd
- 135816970U, // VORNq
- 135816975U, // VORRd
- 135816975U, // VORRq
- 165693204U, // VPADALsv16i8
- 164644628U, // VPADALsv2i32
- 165168916U, // VPADALsv4i16
- 164644628U, // VPADALsv4i32
- 165168916U, // VPADALsv8i16
- 165693204U, // VPADALsv8i8
- 167266068U, // VPADALuv16i8
- 166217492U, // VPADALuv2i32
- 166741780U, // VPADALuv4i16
- 166217492U, // VPADALuv4i32
- 166741780U, // VPADALuv8i16
- 167266068U, // VPADALuv8i8
- 769656603U, // VPADDLsv16i8
- 768608027U, // VPADDLsv2i32
- 769132315U, // VPADDLsv4i16
- 768608027U, // VPADDLsv4i32
- 769132315U, // VPADDLsv8i16
- 769656603U, // VPADDLsv8i8
- 771229467U, // VPADDLuv16i8
- 770180891U, // VPADDLuv2i32
- 770705179U, // VPADDLuv4i16
- 770180891U, // VPADDLuv4i32
- 770705179U, // VPADDLuv8i16
- 771229467U, // VPADDLuv8i8
- 152102690U, // VPADDf
- 168822562U, // VPADDi16
- 168298274U, // VPADDi32
- 169346850U, // VPADDi8
- 152102696U, // VPMAXf
- 165152552U, // VPMAXs16
- 164628264U, // VPMAXs32
- 165676840U, // VPMAXs8
- 166725416U, // VPMAXu16
- 166201128U, // VPMAXu32
- 167249704U, // VPMAXu8
- 152102702U, // VPMINf
- 165152558U, // VPMINs16
- 164628270U, // VPMINs32
- 165676846U, // VPMINs8
- 166725422U, // VPMINu16
- 166201134U, // VPMINu32
- 167249710U, // VPMINu8
- 769656628U, // VQABSv16i8
- 768608052U, // VQABSv2i32
- 769132340U, // VQABSv4i16
- 768608052U, // VQABSv4i32
- 769132340U, // VQABSv8i16
- 769656628U, // VQABSv8i8
- 165676858U, // VQADDsv16i8
- 179308346U, // VQADDsv1i64
- 164628282U, // VQADDsv2i32
- 179308346U, // VQADDsv2i64
- 165152570U, // VQADDsv4i16
- 164628282U, // VQADDsv4i32
- 165152570U, // VQADDsv8i16
- 165676858U, // VQADDsv8i8
- 167249722U, // VQADDuv16i8
- 179832634U, // VQADDuv1i64
- 166201146U, // VQADDuv2i32
- 179832634U, // VQADDuv2i64
- 166725434U, // VQADDuv4i16
- 166201146U, // VQADDuv4i32
- 166725434U, // VQADDuv8i16
- 167249722U, // VQADDuv8i8
- 231753536U, // VQDMLALslv2i32
- 232277824U, // VQDMLALslv4i16
- 835733312U, // VQDMLALv2i64
- 836257600U, // VQDMLALv4i32
- 231753544U, // VQDMLSLslv2i32
- 232277832U, // VQDMLSLslv4i16
- 835733320U, // VQDMLSLv2i64
- 836257608U, // VQDMLSLv4i32
- 835716944U, // VQDMULHslv2i32
- 836241232U, // VQDMULHslv4i16
- 835716944U, // VQDMULHslv4i32
- 836241232U, // VQDMULHslv8i16
- 164628304U, // VQDMULHv2i32
- 165152592U, // VQDMULHv4i16
- 164628304U, // VQDMULHv4i32
- 165152592U, // VQDMULHv8i16
- 835716952U, // VQDMULLslv2i32
- 836241240U, // VQDMULLslv4i16
- 164628312U, // VQDMULLv2i64
- 165152600U, // VQDMULLv4i32
- 783288160U, // VQMOVNsuv2i32
- 768608096U, // VQMOVNsuv4i16
- 769132384U, // VQMOVNsuv8i8
- 783288168U, // VQMOVNsv2i32
- 768608104U, // VQMOVNsv4i16
- 769132392U, // VQMOVNsv8i8
- 783812456U, // VQMOVNuv2i32
- 770180968U, // VQMOVNuv4i16
- 770705256U, // VQMOVNuv8i8
- 769656687U, // VQNEGv16i8
- 768608111U, // VQNEGv2i32
- 769132399U, // VQNEGv4i16
- 768608111U, // VQNEGv4i32
- 769132399U, // VQNEGv8i16
- 769656687U, // VQNEGv8i8
- 835716981U, // VQRDMULHslv2i32
- 836241269U, // VQRDMULHslv4i16
- 835716981U, // VQRDMULHslv4i32
- 836241269U, // VQRDMULHslv8i16
- 164628341U, // VQRDMULHv2i32
- 165152629U, // VQRDMULHv4i16
- 164628341U, // VQRDMULHv4i32
- 165152629U, // VQRDMULHv8i16
- 165676926U, // VQRSHLsv16i8
- 179308414U, // VQRSHLsv1i64
- 164628350U, // VQRSHLsv2i32
- 179308414U, // VQRSHLsv2i64
- 165152638U, // VQRSHLsv4i16
- 164628350U, // VQRSHLsv4i32
- 165152638U, // VQRSHLsv8i16
- 165676926U, // VQRSHLsv8i8
- 167249790U, // VQRSHLuv16i8
- 179832702U, // VQRSHLuv1i64
- 166201214U, // VQRSHLuv2i32
- 179832702U, // VQRSHLuv2i64
- 166725502U, // VQRSHLuv4i16
- 166201214U, // VQRSHLuv4i32
- 166725502U, // VQRSHLuv8i16
- 167249790U, // VQRSHLuv8i8
- 179308421U, // VQRSHRNsv2i32
- 164628357U, // VQRSHRNsv4i16
- 165152645U, // VQRSHRNsv8i8
- 179832709U, // VQRSHRNuv2i32
- 166201221U, // VQRSHRNuv4i16
- 166725509U, // VQRSHRNuv8i8
- 179308429U, // VQRSHRUNv2i32
- 164628365U, // VQRSHRUNv4i16
- 165152653U, // VQRSHRUNv8i8
- 165676950U, // VQSHLsiv16i8
- 179308438U, // VQSHLsiv1i64
- 164628374U, // VQSHLsiv2i32
- 179308438U, // VQSHLsiv2i64
- 165152662U, // VQSHLsiv4i16
- 164628374U, // VQSHLsiv4i32
- 165152662U, // VQSHLsiv8i16
- 165676950U, // VQSHLsiv8i8
- 165676956U, // VQSHLsuv16i8
- 179308444U, // VQSHLsuv1i64
- 164628380U, // VQSHLsuv2i32
- 179308444U, // VQSHLsuv2i64
- 165152668U, // VQSHLsuv4i16
- 164628380U, // VQSHLsuv4i32
- 165152668U, // VQSHLsuv8i16
- 165676956U, // VQSHLsuv8i8
- 165676950U, // VQSHLsv16i8
- 179308438U, // VQSHLsv1i64
- 164628374U, // VQSHLsv2i32
- 179308438U, // VQSHLsv2i64
- 165152662U, // VQSHLsv4i16
- 164628374U, // VQSHLsv4i32
- 165152662U, // VQSHLsv8i16
- 165676950U, // VQSHLsv8i8
- 167249814U, // VQSHLuiv16i8
- 179832726U, // VQSHLuiv1i64
- 166201238U, // VQSHLuiv2i32
- 179832726U, // VQSHLuiv2i64
- 166725526U, // VQSHLuiv4i16
- 166201238U, // VQSHLuiv4i32
- 166725526U, // VQSHLuiv8i16
- 167249814U, // VQSHLuiv8i8
- 167249814U, // VQSHLuv16i8
- 179832726U, // VQSHLuv1i64
- 166201238U, // VQSHLuv2i32
- 179832726U, // VQSHLuv2i64
- 166725526U, // VQSHLuv4i16
- 166201238U, // VQSHLuv4i32
- 166725526U, // VQSHLuv8i16
- 167249814U, // VQSHLuv8i8
- 179308451U, // VQSHRNsv2i32
- 164628387U, // VQSHRNsv4i16
- 165152675U, // VQSHRNsv8i8
- 179832739U, // VQSHRNuv2i32
- 166201251U, // VQSHRNuv4i16
- 166725539U, // VQSHRNuv8i8
- 179308458U, // VQSHRUNv2i32
- 164628394U, // VQSHRUNv4i16
- 165152682U, // VQSHRUNv8i8
- 165676978U, // VQSUBsv16i8
- 179308466U, // VQSUBsv1i64
- 164628402U, // VQSUBsv2i32
- 179308466U, // VQSUBsv2i64
- 165152690U, // VQSUBsv4i16
- 164628402U, // VQSUBsv4i32
- 165152690U, // VQSUBsv8i16
- 165676978U, // VQSUBsv8i8
- 167249842U, // VQSUBuv16i8
- 179832754U, // VQSUBuv1i64
- 166201266U, // VQSUBuv2i32
- 179832754U, // VQSUBuv2i64
- 166725554U, // VQSUBuv4i16
- 166201266U, // VQSUBuv4i32
- 166725554U, // VQSUBuv8i16
- 167249842U, // VQSUBuv8i8
- 167774136U, // VRADDHNv2i32
- 168298424U, // VRADDHNv4i16
- 168822712U, // VRADDHNv8i8
- 770181056U, // VRECPEd
- 756082624U, // VRECPEfd
- 756082624U, // VRECPEfq
- 770181056U, // VRECPEq
- 152102855U, // VRECPSfd
- 152102855U, // VRECPSfq
- 773875662U, // VREV16d8
- 773875662U, // VREV16q8
- 778594261U, // VREV32d16
- 773875669U, // VREV32d8
- 778594261U, // VREV32q16
- 773875669U, // VREV32q8
- 778594268U, // VREV64d16
- 779118556U, // VREV64d32
- 773875676U, // VREV64d8
- 779118556U, // VREV64df
- 778594268U, // VREV64q16
- 779118556U, // VREV64q32
- 773875676U, // VREV64q8
- 779118556U, // VREV64qf
- 165677027U, // VRHADDsv16i8
- 164628451U, // VRHADDsv2i32
- 165152739U, // VRHADDsv4i16
- 164628451U, // VRHADDsv4i32
- 165152739U, // VRHADDsv8i16
- 165677027U, // VRHADDsv8i8
- 167249891U, // VRHADDuv16i8
- 166201315U, // VRHADDuv2i32
- 166725603U, // VRHADDuv4i16
- 166201315U, // VRHADDuv4i32
- 166725603U, // VRHADDuv8i16
- 167249891U, // VRHADDuv8i8
- 165677034U, // VRSHLsv16i8
- 179308522U, // VRSHLsv1i64
- 164628458U, // VRSHLsv2i32
- 179308522U, // VRSHLsv2i64
- 165152746U, // VRSHLsv4i16
- 164628458U, // VRSHLsv4i32
- 165152746U, // VRSHLsv8i16
- 165677034U, // VRSHLsv8i8
- 167249898U, // VRSHLuv16i8
- 179832810U, // VRSHLuv1i64
- 166201322U, // VRSHLuv2i32
- 179832810U, // VRSHLuv2i64
- 166725610U, // VRSHLuv4i16
- 166201322U, // VRSHLuv4i32
- 166725610U, // VRSHLuv8i16
- 167249898U, // VRSHLuv8i8
- 167774192U, // VRSHRNv2i32
- 168298480U, // VRSHRNv4i16
- 168822768U, // VRSHRNv8i8
- 165677047U, // VRSHRsv16i8
- 179308535U, // VRSHRsv1i64
- 164628471U, // VRSHRsv2i32
- 179308535U, // VRSHRsv2i64
- 165152759U, // VRSHRsv4i16
- 164628471U, // VRSHRsv4i32
- 165152759U, // VRSHRsv8i16
- 165677047U, // VRSHRsv8i8
- 167249911U, // VRSHRuv16i8
- 179832823U, // VRSHRuv1i64
- 166201335U, // VRSHRuv2i32
- 179832823U, // VRSHRuv2i64
- 166725623U, // VRSHRuv4i16
- 166201335U, // VRSHRuv4i32
- 166725623U, // VRSHRuv8i16
- 167249911U, // VRSHRuv8i8
- 770181117U, // VRSQRTEd
- 756082685U, // VRSQRTEfd
- 756082685U, // VRSQRTEfq
- 770181117U, // VRSQRTEq
- 152102917U, // VRSQRTSfd
- 152102917U, // VRSQRTSfq
- 836782093U, // VRSRAsv16i8
- 850413581U, // VRSRAsv1i64
- 835733517U, // VRSRAsv2i32
- 850413581U, // VRSRAsv2i64
- 836257805U, // VRSRAsv4i16
- 835733517U, // VRSRAsv4i32
- 836257805U, // VRSRAsv8i16
- 836782093U, // VRSRAsv8i8
- 838354957U, // VRSRAuv16i8
- 850937869U, // VRSRAuv1i64
- 837306381U, // VRSRAuv2i32
- 850937869U, // VRSRAuv2i64
- 837830669U, // VRSRAuv4i16
- 837306381U, // VRSRAuv4i32
- 837830669U, // VRSRAuv8i16
- 838354957U, // VRSRAuv8i8
- 167774227U, // VRSUBHNv2i32
- 168298515U, // VRSUBHNv4i16
- 168822803U, // VRSUBHNv8i8
- 845701444U, // VSETLNi16
- 846225732U, // VSETLNi32
- 840982852U, // VSETLNi8
- 168822811U, // VSHLLi16
- 168298523U, // VSHLLi32
- 169347099U, // VSHLLi8
- 164628507U, // VSHLLsv2i64
- 165152795U, // VSHLLsv4i32
- 165677083U, // VSHLLsv8i16
- 166201371U, // VSHLLuv2i64
- 166725659U, // VSHLLuv4i32
- 167249947U, // VSHLLuv8i16
- 169347105U, // VSHLiv16i8
- 167774241U, // VSHLiv1i64
- 168298529U, // VSHLiv2i32
- 167774241U, // VSHLiv2i64
- 168822817U, // VSHLiv4i16
- 168298529U, // VSHLiv4i32
- 168822817U, // VSHLiv8i16
- 169347105U, // VSHLiv8i8
- 165677089U, // VSHLsv16i8
- 179308577U, // VSHLsv1i64
- 164628513U, // VSHLsv2i32
- 179308577U, // VSHLsv2i64
- 165152801U, // VSHLsv4i16
- 164628513U, // VSHLsv4i32
- 165152801U, // VSHLsv8i16
- 165677089U, // VSHLsv8i8
- 167249953U, // VSHLuv16i8
- 179832865U, // VSHLuv1i64
- 166201377U, // VSHLuv2i32
- 179832865U, // VSHLuv2i64
- 166725665U, // VSHLuv4i16
- 166201377U, // VSHLuv4i32
- 166725665U, // VSHLuv8i16
- 167249953U, // VSHLuv8i8
- 167774246U, // VSHRNv2i32
- 168298534U, // VSHRNv4i16
- 168822822U, // VSHRNv8i8
- 165677100U, // VSHRsv16i8
- 179308588U, // VSHRsv1i64
- 164628524U, // VSHRsv2i32
- 179308588U, // VSHRsv2i64
- 165152812U, // VSHRsv4i16
- 164628524U, // VSHRsv4i32
- 165152812U, // VSHRsv8i16
- 165677100U, // VSHRsv8i8
- 167249964U, // VSHRuv16i8
- 179832876U, // VSHRuv1i64
- 166201388U, // VSHRuv2i32
- 179832876U, // VSHRuv2i64
- 166725676U, // VSHRuv4i16
- 166201388U, // VSHRuv4i32
- 166725676U, // VSHRuv8i16
- 167249964U, // VSHRuv8i8
- 180356706U, // VSHTOD
- 180880994U, // VSHTOS
- 785507938U, // VSITOD
- 777643618U, // VSITOS
- 840984625U, // VSLIv16i8
- 848848945U, // VSLIv1i64
- 846227505U, // VSLIv2i32
- 848848945U, // VSLIv2i64
- 845703217U, // VSLIv4i16
- 846227505U, // VSLIv4i32
- 845703217U, // VSLIv8i16
- 840984625U, // VSLIv8i8
- 181462626U, // VSLTOD
- 173598306U, // VSLTOS
- 755558454U, // VSQRTD
- 756082742U, // VSQRTS
- 836782140U, // VSRAsv16i8
- 850413628U, // VSRAsv1i64
- 835733564U, // VSRAsv2i32
- 850413628U, // VSRAsv2i64
- 836257852U, // VSRAsv4i16
- 835733564U, // VSRAsv4i32
- 836257852U, // VSRAsv8i16
- 836782140U, // VSRAsv8i8
- 838355004U, // VSRAuv16i8
- 850937916U, // VSRAuv1i64
- 837306428U, // VSRAuv2i32
- 850937916U, // VSRAuv2i64
- 837830716U, // VSRAuv4i16
- 837306428U, // VSRAuv4i32
- 837830716U, // VSRAuv8i16
- 838355004U, // VSRAuv8i8
- 840984641U, // VSRIv16i8
- 848848961U, // VSRIv1i64
- 846227521U, // VSRIv2i32
- 848848961U, // VSRIv2i64
- 845703233U, // VSRIv4i16
- 846227521U, // VSRIv4i32
- 845703233U, // VSRIv8i16
- 840984641U, // VSRIv8i8
- 242927686U, // VST1d16
- 1316669510U, // VST1d16Q
- 1383778374U, // VST1d16T
- 243451974U, // VST1d32
- 1317193798U, // VST1d32Q
- 1384302662U, // VST1d32T
- 243976262U, // VST1d64
- 244500550U, // VST1d8
- 1318242374U, // VST1d8Q
- 1385351238U, // VST1d8T
- 243451974U, // VST1df
- 241887302U, // VST1q16
- 242411590U, // VST1q32
- 245033030U, // VST1q64
- 237168710U, // VST1q8
- 242411590U, // VST1qf
- 1383778379U, // VST2LNd16
- 1384302667U, // VST2LNd32
- 1385351243U, // VST2LNd8
- 1383778379U, // VST2LNq16a
- 1383778379U, // VST2LNq16b
- 1384302667U, // VST2LNq32a
- 1384302667U, // VST2LNq32b
- 645580875U, // VST2d16
- 645580875U, // VST2d16D
- 646105163U, // VST2d32
- 646105163U, // VST2d32D
- 646629446U, // VST2d64
- 647153739U, // VST2d8
- 647153739U, // VST2d8D
- 1316669515U, // VST2q16
- 1317193803U, // VST2q32
- 1318242379U, // VST2q8
- 1316669520U, // VST3LNd16
- 1317193808U, // VST3LNd32
- 1318242384U, // VST3LNd8
- 1316669520U, // VST3LNq16a
- 1316669520U, // VST3LNq16b
- 1317193808U, // VST3LNq32a
- 1317193808U, // VST3LNq32b
- 1383778384U, // VST3d16
- 1384302672U, // VST3d32
- 1384826950U, // VST3d64
- 1385351248U, // VST3d8
- 1316685904U, // VST3q16a
- 1316685904U, // VST3q16b
- 1317210192U, // VST3q32a
- 1317210192U, // VST3q32b
- 1318258768U, // VST3q8a
- 1318258768U, // VST3q8b
- 1450887253U, // VST4LNd16
- 1451411541U, // VST4LNd32
- 1452460117U, // VST4LNd8
- 1450887253U, // VST4LNq16a
- 1450887253U, // VST4LNq16b
- 1451411541U, // VST4LNq32a
- 1451411541U, // VST4LNq32b
- 1316669525U, // VST4d16
- 1317193813U, // VST4d32
- 1317718086U, // VST4d64
- 1318242389U, // VST4d8
- 1450903637U, // VST4q16a
- 1450903637U, // VST4q16b
- 1451427925U, // VST4q32a
- 1451427925U, // VST4q32b
- 1452476501U, // VST4q8a
- 1452476501U, // VST4q8b
- 1610614874U, // VSTMD
- 1610614874U, // VSTMS
- 177760351U, // VSTRD
- 135932004U, // VSTRQ
- 175138911U, // VSTRS
- 151578731U, // VSUBD
- 167774320U, // VSUBHNv2i32
- 168298608U, // VSUBHNv4i16
- 168822896U, // VSUBHNv8i8
- 164628599U, // VSUBLsv2i64
- 165152887U, // VSUBLsv4i32
- 165677175U, // VSUBLsv8i16
- 166201463U, // VSUBLuv2i64
- 166725751U, // VSUBLuv4i32
- 167250039U, // VSUBLuv8i16
- 152103019U, // VSUBS
- 164628605U, // VSUBWsv2i64
- 165152893U, // VSUBWsv4i32
- 165677181U, // VSUBWsv8i16
- 166201469U, // VSUBWuv2i64
- 166725757U, // VSUBWuv4i32
- 167250045U, // VSUBWuv8i16
- 152103019U, // VSUBfd
- 152103019U, // VSUBfd_sfp
- 152103019U, // VSUBfq
- 169347179U, // VSUBv16i8
- 167774315U, // VSUBv1i64
- 168298603U, // VSUBv2i32
- 167774315U, // VSUBv2i64
- 168822891U, // VSUBv4i16
- 168298603U, // VSUBv4i32
- 168822891U, // VSUBv8i16
- 169347179U, // VSUBv8i8
- 739797123U, // VSWPd
- 739797123U, // VSWPq
- 169896072U, // VTBL1
- 840984712U, // VTBL2
- 237004936U, // VTBL3
- 639658120U, // VTBL4
- 840984717U, // VTBX1
- 237004941U, // VTBX2
- 639658125U, // VTBX3
- 1377855629U, // VTBX4
- 181929570U, // VTOSHD
- 182453858U, // VTOSHS
- 787081362U, // VTOSIRD
- 776595602U, // VTOSIRS
- 787080802U, // VTOSIZD
- 776595042U, // VTOSIZS
- 183035490U, // VTOSLD
- 172549730U, // VTOSLS
- 183502434U, // VTOUHD
- 184026722U, // VTOUHS
- 788654226U, // VTOUIRD
- 777119890U, // VTOUIRS
- 788653666U, // VTOUIZD
- 777119330U, // VTOUIZS
- 184608354U, // VTOULD
- 173074018U, // VTOULS
- 845703320U, // VTRNd16
- 846227608U, // VTRNd32
- 840984728U, // VTRNd8
- 845703320U, // VTRNq16
- 846227608U, // VTRNq32
- 840984728U, // VTRNq8
- 169896093U, // VTSTv16i8
- 175138973U, // VTSTv2i32
- 174614685U, // VTSTv4i16
- 175138973U, // VTSTv4i32
- 174614685U, // VTSTv8i16
- 169896093U, // VTSTv8i8
- 185075298U, // VUHTOD
- 185599586U, // VUHTOS
- 790226530U, // VUITOD
- 778167906U, // VUITOS
- 186181218U, // VULTOD
- 174122594U, // VULTOS
- 845703330U, // VUZPd16
- 846227618U, // VUZPd32
- 840984738U, // VUZPd8
- 845703330U, // VUZPq16
- 846227618U, // VUZPq32
- 840984738U, // VUZPq8
- 845703335U, // VZIPd16
- 846227623U, // VZIPd32
- 840984743U, // VZIPd8
- 845703335U, // VZIPq16
- 846227623U, // VZIPq32
- 840984743U, // VZIPq8
- 538970284U, // WFE
- 538970288U, // WFI
- 538970292U, // YIELD
+ 939524307U, // CPS
+ 337141975U, // DBG
+ 219U, // DMBish
+ 227U, // DMBishst
+ 237U, // DMBnsh
+ 245U, // DMBnshst
+ 255U, // DMBosh
+ 263U, // DMBoshst
+ 273U, // DMBst
+ 280U, // DSBish
+ 288U, // DSBishst
+ 298U, // DSBnsh
+ 306U, // DSBnshst
+ 316U, // DSBosh
+ 324U, // DSBoshst
+ 334U, // DSBst
+ 134750549U, // EORri
+ 134758741U, // EORrr
+ 202375509U, // EORrs
+ 755556697U, // FCONSTD
+ 756080985U, // FCONSTS
+ 555221342U, // FMSTAT
+ 355U, // ISBsy
+ 85983591U, // Int_MemBarrierV6
+ 372U, // Int_MemBarrierV7
+ 86507879U, // Int_SyncBarrierV6
+ 376U, // Int_SyncBarrierV7
+ 87032188U, // Int_eh_sjlj_setjmp
+ 221831558U, // LDC2L_OFFSET
+ 825819526U, // LDC2L_OPTION
+ 221839750U, // LDC2L_POST
+ 221831558U, // LDC2L_PRE
+ 217653638U, // LDC2_OFFSET
+ 821633414U, // LDC2_OPTION
+ 217653638U, // LDC2_POST
+ 217653638U, // LDC2_PRE
+ 221831563U, // LDCL_OFFSET
+ 825819531U, // LDCL_OPTION
+ 221839755U, // LDCL_POST
+ 221831563U, // LDCL_PRE
+ 217653643U, // LDC_OFFSET
+ 821633419U, // LDC_OPTION
+ 217653643U, // LDC_POST
+ 217653643U, // LDC_PRE
+ 1027686799U, // LDM
+ 1027686799U, // LDM_RET
+ 806904211U, // LDR
+ 806904215U, // LDRB
+ 202924444U, // LDRBT
+ 202924439U, // LDRB_POST
+ 202924439U, // LDRB_PRE
+ 202924450U, // LDRD
+ 605577634U, // LDRD_POST
+ 605577634U, // LDRD_PRE
+ 739795367U, // LDREX
+ 739795373U, // LDREXB
+ 135815604U, // LDREXD
+ 739795387U, // LDREXH
+ 806904258U, // LDRH
+ 202924487U, // LDRHT
+ 202924482U, // LDRH_POST
+ 202924482U, // LDRH_PRE
+ 806904269U, // LDRSB
+ 202924499U, // LDRSBT
+ 202924493U, // LDRSB_POST
+ 202924493U, // LDRSB_PRE
+ 806904282U, // LDRSH
+ 202924512U, // LDRSHT
+ 202924506U, // LDRSH_POST
+ 202924506U, // LDRSH_PRE
+ 202924519U, // LDRT
+ 202924435U, // LDR_POST
+ 202924435U, // LDR_PRE
+ 806904211U, // LDRcp
+ 1095238124U, // LEApcrel
+ 1095762412U, // LEApcrelJT
+ 620290546U, // MCR
+ 671105526U, // MCR2
+ 217637373U, // MCRR
+ 671105538U, // MCRR2
+ 827851274U, // MLA
+ 806904334U, // MLS
+ 135815698U, // MOVCCi
+ 135815698U, // MOVCCr
+ 202924562U, // MOVCCs
+ 559940114U, // MOVPCLR
+ 69206164U, // MOVPCRX
+ 135815702U, // MOVTi16
+ 761881106U, // MOVi
+ 739795483U, // MOVi16
+ 739795474U, // MOVi2pieces
+ 739795483U, // MOVi32imm
+ 761790994U, // MOVr
+ 761790994U, // MOVrx
+ 827949586U, // MOVs
+ 739795488U, // MOVsra_flag
+ 739795488U, // MOVsrl_flag
+ 620290597U, // MRC
+ 671105577U, // MRC2
+ 217637424U, // MRRC
+ 671105589U, // MRRC2
+ 337142333U, // MRS
+ 337142333U, // MRSsys
+ 359686721U, // MSR
+ 359768641U, // MSRi
+ 360211009U, // MSRsys
+ 360292929U, // MSRsysi
+ 134758981U, // MUL
+ 761881161U, // MVNi
+ 761791049U, // MVNr
+ 827949641U, // MVNs
+ 538968653U, // NOP
+ 134750801U, // ORRri
+ 134758993U, // ORRrr
+ 202375761U, // ORRrs
+ 1166017109U, // PICADD
+ 1233650261U, // PICLDR
+ 1234174549U, // PICLDRB
+ 1234698837U, // PICLDRH
+ 1235223125U, // PICLDRSB
+ 1235747413U, // PICLDRSH
+ 1236271701U, // PICSTR
+ 1236795989U, // PICSTRB
+ 1237320277U, // PICSTRH
+ 806904407U, // PKHBT
+ 806904413U, // PKHTB
+ 67109475U, // PLDWi
+ 471859818U, // PLDWr
+ 67109488U, // PLDi
+ 471859830U, // PLDr
+ 67109499U, // PLIi
+ 471859841U, // PLIr
+ 135815814U, // QADD
+ 135815819U, // QADD16
+ 135815826U, // QADD8
+ 135815832U, // QASX
+ 135815837U, // QDADD
+ 135815843U, // QDSUB
+ 135815849U, // QSAX
+ 135815854U, // QSUB
+ 135815859U, // QSUB16
+ 135815866U, // QSUB8
+ 739795648U, // RBIT
+ 739795653U, // REV
+ 739795657U, // REV16
+ 739795663U, // REVSH
+ 1008222933U, // RFE
+ 1008222933U, // RFEW
+ 135815897U, // RSBSri
+ 202924761U, // RSBSrs
+ 134750942U, // RSBri
+ 202375902U, // RSBrs
+ 67109602U, // RSCSri
+ 67109602U, // RSCSrs
+ 134750952U, // RSCri
+ 202375912U, // RSCrs
+ 135815916U, // SADD16
+ 135815923U, // SADD8
+ 135815929U, // SASX
+ 67109630U, // SBCSSri
+ 67109630U, // SBCSSrr
+ 67109630U, // SBCSSrs
+ 134750980U, // SBCri
+ 134759172U, // SBCrr
+ 202375940U, // SBCrs
+ 806904584U, // SBFX
+ 135815949U, // SEL
+ 785U, // SETENDBE
+ 795U, // SETENDLE
+ 538968869U, // SEV
+ 135815977U, // SHADD16
+ 135815985U, // SHADD8
+ 135815992U, // SHASX
+ 135815998U, // SHSAX
+ 135816004U, // SHSUB16
+ 135816012U, // SHSUB8
+ 337142611U, // SMC
+ 806904663U, // SMLABB
+ 806904670U, // SMLABT
+ 806904677U, // SMLAD
+ 806904683U, // SMLADX
+ 827851634U, // SMLAL
+ 806904696U, // SMLALBB
+ 806904704U, // SMLALBT
+ 806904712U, // SMLALD
+ 806904719U, // SMLALDX
+ 806904727U, // SMLALTB
+ 806904735U, // SMLALTT
+ 806904743U, // SMLATB
+ 806904750U, // SMLATT
+ 806904757U, // SMLAWB
+ 806904764U, // SMLAWT
+ 806904771U, // SMLSD
+ 806904777U, // SMLSDX
+ 806904784U, // SMLSLD
+ 806904791U, // SMLSLDX
+ 806904799U, // SMMLA
+ 806904805U, // SMMLAR
+ 806904812U, // SMMLS
+ 806904818U, // SMMLSR
+ 135816185U, // SMMUL
+ 135816191U, // SMMULR
+ 135816198U, // SMUAD
+ 135816204U, // SMUADX
+ 135816211U, // SMULBB
+ 135816218U, // SMULBT
+ 827851809U, // SMULL
+ 135816231U, // SMULTB
+ 135816238U, // SMULTT
+ 135816245U, // SMULWB
+ 135816252U, // SMULWT
+ 135816259U, // SMUSD
+ 135816265U, // SMUSDX
+ 1036534864U, // SRS
+ 1037059152U, // SRSW
+ 135816276U, // SSAT16
+ 806904923U, // SSATasr
+ 806904923U, // SSATlsl
+ 135816288U, // SSAX
+ 135816293U, // SSUB16
+ 135816300U, // SSUB8
+ 221832306U, // STC2L_OFFSET
+ 825820274U, // STC2L_OPTION
+ 221840498U, // STC2L_POST
+ 221832306U, // STC2L_PRE
+ 217654386U, // STC2_OFFSET
+ 821634162U, // STC2_OPTION
+ 217654386U, // STC2_POST
+ 217654386U, // STC2_PRE
+ 221832311U, // STCL_OFFSET
+ 825820279U, // STCL_OPTION
+ 221840503U, // STCL_POST
+ 221832311U, // STCL_PRE
+ 217654391U, // STC_OFFSET
+ 821634167U, // STC_OPTION
+ 217654391U, // STC_POST
+ 217654391U, // STC_PRE
+ 1027687547U, // STM
+ 806904959U, // STR
+ 806904963U, // STRB
+ 202900616U, // STRBT
+ 202900611U, // STRB_POST
+ 202900611U, // STRB_PRE
+ 202925198U, // STRD
+ 605553806U, // STRD_POST
+ 605553806U, // STRD_PRE
+ 135816339U, // STREX
+ 135816345U, // STREXB
+ 806904992U, // STREXD
+ 135816359U, // STREXH
+ 806905006U, // STRH
+ 202900659U, // STRHT
+ 202900654U, // STRH_POST
+ 202900654U, // STRH_PRE
+ 202900665U, // STRT
+ 202900607U, // STR_POST
+ 202900607U, // STR_PRE
+ 135816382U, // SUBSri
+ 135816382U, // SUBSrr
+ 202925246U, // SUBSrs
+ 134751427U, // SUBri
+ 134759619U, // SUBrr
+ 202376387U, // SUBrs
+ 337142983U, // SVC
+ 135816395U, // SWP
+ 135816399U, // SWPB
+ 135816404U, // SXTAB16rr
+ 806905044U, // SXTAB16rr_rot
+ 135816412U, // SXTABrr
+ 806905052U, // SXTABrr_rot
+ 135816418U, // SXTAHrr
+ 806905058U, // SXTAHrr_rot
+ 739796200U, // SXTB16r
+ 135816424U, // SXTB16r_rot
+ 739796207U, // SXTBr
+ 135816431U, // SXTBr_rot
+ 739796212U, // SXTHr
+ 135816436U, // SXTHr_rot
+ 739796217U, // TEQri
+ 739796217U, // TEQrr
+ 806905081U, // TEQrs
+ 1277U, // TPsoft
+ 538969360U, // TRAP
+ 739796245U, // TSTri
+ 739796245U, // TSTrr
+ 806905109U, // TSTrs
+ 135816473U, // UADD16
+ 135816480U, // UADD8
+ 135816486U, // UASX
+ 806905131U, // UBFX
+ 135816496U, // UHADD16
+ 135816504U, // UHADD8
+ 135816511U, // UHASX
+ 135816517U, // UHSAX
+ 135816523U, // UHSUB16
+ 135816531U, // UHSUB8
+ 806905178U, // UMAAL
+ 827852128U, // UMLAL
+ 827852134U, // UMULL
+ 135816556U, // UQADD16
+ 135816564U, // UQADD8
+ 135816571U, // UQASX
+ 135816577U, // UQSAX
+ 135816583U, // UQSUB16
+ 135816591U, // UQSUB8
+ 135816598U, // USAD8
+ 806905244U, // USADA8
+ 135816611U, // USAT16
+ 806905258U, // USATasr
+ 806905258U, // USATlsl
+ 135816623U, // USAX
+ 135816628U, // USUB16
+ 135816635U, // USUB8
+ 135816641U, // UXTAB16rr
+ 806905281U, // UXTAB16rr_rot
+ 135816649U, // UXTABrr
+ 806905289U, // UXTABrr_rot
+ 135816655U, // UXTAHrr
+ 806905295U, // UXTAHrr_rot
+ 739796437U, // UXTB16r
+ 135816661U, // UXTB16r_rot
+ 739796444U, // UXTBr
+ 135816668U, // UXTBr_rot
+ 739796449U, // UXTHr
+ 135816673U, // UXTHr_rot
+ 836257254U, // VABALsv2i64
+ 836781542U, // VABALsv4i32
+ 837305830U, // VABALsv8i16
+ 837830118U, // VABALuv2i64
+ 838354406U, // VABALuv4i32
+ 838878694U, // VABALuv8i16
+ 837305836U, // VABAsv16i8
+ 836257260U, // VABAsv2i32
+ 836781548U, // VABAsv4i16
+ 836257260U, // VABAsv4i32
+ 836781548U, // VABAsv8i16
+ 837305836U, // VABAsv8i8
+ 838878700U, // VABAuv16i8
+ 837830124U, // VABAuv2i32
+ 838354412U, // VABAuv4i16
+ 837830124U, // VABAuv4i32
+ 838354412U, // VABAuv8i16
+ 838878700U, // VABAuv8i8
+ 165152241U, // VABDLsv2i64
+ 165676529U, // VABDLsv4i32
+ 166200817U, // VABDLsv8i16
+ 166725105U, // VABDLuv2i64
+ 167249393U, // VABDLuv4i32
+ 167773681U, // VABDLuv8i16
+ 152102391U, // VABDfd
+ 152102391U, // VABDfq
+ 166200823U, // VABDsv16i8
+ 165152247U, // VABDsv2i32
+ 165676535U, // VABDsv4i16
+ 165152247U, // VABDsv4i32
+ 165676535U, // VABDsv8i16
+ 166200823U, // VABDsv8i8
+ 167773687U, // VABDuv16i8
+ 166725111U, // VABDuv2i32
+ 167249399U, // VABDuv4i16
+ 166725111U, // VABDuv4i32
+ 167249399U, // VABDuv8i16
+ 167773687U, // VABDuv8i8
+ 755557884U, // VABSD
+ 756082172U, // VABSS
+ 756082172U, // VABSfd
+ 756082172U, // VABSfd_sfp
+ 756082172U, // VABSfq
+ 770180604U, // VABSv16i8
+ 769132028U, // VABSv2i32
+ 769656316U, // VABSv4i16
+ 769132028U, // VABSv4i32
+ 769656316U, // VABSv8i16
+ 770180604U, // VABSv8i8
+ 152102401U, // VACGEd
+ 152102401U, // VACGEq
+ 152102407U, // VACGTd
+ 152102407U, // VACGTq
+ 151578125U, // VADDD
+ 168298002U, // VADDHNv2i32
+ 168822290U, // VADDHNv4i16
+ 169346578U, // VADDHNv8i8
+ 165152281U, // VADDLsv2i64
+ 165676569U, // VADDLsv4i32
+ 166200857U, // VADDLsv8i16
+ 166725145U, // VADDLuv2i64
+ 167249433U, // VADDLuv4i32
+ 167773721U, // VADDLuv8i16
+ 152102413U, // VADDS
+ 165152287U, // VADDWsv2i64
+ 165676575U, // VADDWsv4i32
+ 166200863U, // VADDWsv8i16
+ 166725151U, // VADDWuv2i64
+ 167249439U, // VADDWuv4i32
+ 167773727U, // VADDWuv8i16
+ 152102413U, // VADDfd
+ 152102413U, // VADDfd_sfp
+ 152102413U, // VADDfq
+ 169870861U, // VADDv16i8
+ 168297997U, // VADDv1i64
+ 168822285U, // VADDv2i32
+ 168297997U, // VADDv2i64
+ 169346573U, // VADDv4i16
+ 168822285U, // VADDv4i32
+ 169346573U, // VADDv8i16
+ 169870861U, // VADDv8i8
+ 135816741U, // VANDd
+ 135816741U, // VANDq
+ 135816746U, // VBICd
+ 135816746U, // VBICq
+ 806905391U, // VBIFd
+ 806905391U, // VBIFq
+ 806905396U, // VBITd
+ 806905396U, // VBITq
+ 806905401U, // VBSLd
+ 806905401U, // VBSLq
+ 152102462U, // VCEQfd
+ 152102462U, // VCEQfq
+ 169870910U, // VCEQv16i8
+ 168822334U, // VCEQv2i32
+ 169346622U, // VCEQv4i16
+ 168822334U, // VCEQv4i32
+ 169346622U, // VCEQv8i16
+ 169870910U, // VCEQv8i8
+ 773850686U, // VCEQzv16i8
+ 756082238U, // VCEQzv2f32
+ 772802110U, // VCEQzv2i32
+ 756082238U, // VCEQzv4f32
+ 773326398U, // VCEQzv4i16
+ 772802110U, // VCEQzv4i32
+ 773326398U, // VCEQzv8i16
+ 773850686U, // VCEQzv8i8
+ 152102467U, // VCGEfd
+ 152102467U, // VCGEfq
+ 166200899U, // VCGEsv16i8
+ 165152323U, // VCGEsv2i32
+ 165676611U, // VCGEsv4i16
+ 165152323U, // VCGEsv4i32
+ 165676611U, // VCGEsv8i16
+ 166200899U, // VCGEsv8i8
+ 167773763U, // VCGEuv16i8
+ 166725187U, // VCGEuv2i32
+ 167249475U, // VCGEuv4i16
+ 166725187U, // VCGEuv4i32
+ 167249475U, // VCGEuv8i16
+ 167773763U, // VCGEuv8i8
+ 770180675U, // VCGEzv16i8
+ 756082243U, // VCGEzv2f32
+ 769132099U, // VCGEzv2i32
+ 756082243U, // VCGEzv4f32
+ 769656387U, // VCGEzv4i16
+ 769132099U, // VCGEzv4i32
+ 769656387U, // VCGEzv8i16
+ 770180675U, // VCGEzv8i8
+ 152102472U, // VCGTfd
+ 152102472U, // VCGTfq
+ 166200904U, // VCGTsv16i8
+ 165152328U, // VCGTsv2i32
+ 165676616U, // VCGTsv4i16
+ 165152328U, // VCGTsv4i32
+ 165676616U, // VCGTsv8i16
+ 166200904U, // VCGTsv8i8
+ 167773768U, // VCGTuv16i8
+ 166725192U, // VCGTuv2i32
+ 167249480U, // VCGTuv4i16
+ 166725192U, // VCGTuv4i32
+ 167249480U, // VCGTuv8i16
+ 167773768U, // VCGTuv8i8
+ 770180680U, // VCGTzv16i8
+ 756082248U, // VCGTzv2f32
+ 769132104U, // VCGTzv2i32
+ 756082248U, // VCGTzv4f32
+ 769656392U, // VCGTzv4i16
+ 769132104U, // VCGTzv4i32
+ 769656392U, // VCGTzv8i16
+ 770180680U, // VCGTzv8i8
+ 770180685U, // VCLEzv16i8
+ 756082253U, // VCLEzv2f32
+ 769132109U, // VCLEzv2i32
+ 756082253U, // VCLEzv4f32
+ 769656397U, // VCLEzv4i16
+ 769132109U, // VCLEzv4i32
+ 769656397U, // VCLEzv8i16
+ 770180685U, // VCLEzv8i8
+ 770180690U, // VCLSv16i8
+ 769132114U, // VCLSv2i32
+ 769656402U, // VCLSv4i16
+ 769132114U, // VCLSv4i32
+ 769656402U, // VCLSv8i16
+ 770180690U, // VCLSv8i8
+ 770180695U, // VCLTzv16i8
+ 756082263U, // VCLTzv2f32
+ 769132119U, // VCLTzv2i32
+ 756082263U, // VCLTzv4f32
+ 769656407U, // VCLTzv4i16
+ 769132119U, // VCLTzv4i32
+ 769656407U, // VCLTzv8i16
+ 770180695U, // VCLTzv8i8
+ 773850716U, // VCLZv16i8
+ 772802140U, // VCLZv2i32
+ 773326428U, // VCLZv4i16
+ 772802140U, // VCLZv4i32
+ 773326428U, // VCLZv8i16
+ 773850716U, // VCLZv8i8
+ 755557985U, // VCMPD
+ 755557990U, // VCMPED
+ 756082278U, // VCMPES
+ 352962150U, // VCMPEZD
+ 353486438U, // VCMPEZS
+ 756082273U, // VCMPS
+ 352962145U, // VCMPZD
+ 353486433U, // VCMPZS
+ 774399596U, // VCNTd
+ 774399596U, // VCNTq
+ 774899313U, // VCVTBHS
+ 775423601U, // VCVTBSH
+ 775947895U, // VCVTDS
+ 776472183U, // VCVTSD
+ 774899324U, // VCVTTHS
+ 775423612U, // VCVTTSH
+ 777119351U, // VCVTf2sd
+ 777119351U, // VCVTf2sd_sfp
+ 777119351U, // VCVTf2sq
+ 777643639U, // VCVTf2ud
+ 777643639U, // VCVTf2ud_sfp
+ 777643639U, // VCVTf2uq
+ 173074039U, // VCVTf2xsd
+ 173074039U, // VCVTf2xsq
+ 173598327U, // VCVTf2xud
+ 173598327U, // VCVTf2xuq
+ 778167927U, // VCVTs2fd
+ 778167927U, // VCVTs2fd_sfp
+ 778167927U, // VCVTs2fq
+ 778692215U, // VCVTu2fd
+ 778692215U, // VCVTu2fd_sfp
+ 778692215U, // VCVTu2fq
+ 174122615U, // VCVTxs2fd
+ 174122615U, // VCVTxs2fq
+ 174646903U, // VCVTxu2fd
+ 174646903U, // VCVTxu2fq
+ 151578242U, // VDIVD
+ 152102530U, // VDIVS
+ 779118215U, // VDUP16d
+ 779118215U, // VDUP16q
+ 779642503U, // VDUP32d
+ 779642503U, // VDUP32q
+ 774399623U, // VDUP8d
+ 774399623U, // VDUP8q
+ 175138439U, // VDUPLN16d
+ 175138439U, // VDUPLN16q
+ 175662727U, // VDUPLN32d
+ 175662727U, // VDUPLN32q
+ 170419847U, // VDUPLN8d
+ 170419847U, // VDUPLN8q
+ 175662727U, // VDUPLNfd
+ 175662727U, // VDUPLNfq
+ 779642503U, // VDUPfd
+ 779642503U, // VDUPfdf
+ 779642503U, // VDUPfq
+ 779642503U, // VDUPfqf
+ 135816844U, // VEORd
+ 135816844U, // VEORq
+ 846227089U, // VEXTd16
+ 846751377U, // VEXTd32
+ 841508497U, // VEXTd8
+ 846751377U, // VEXTdf
+ 846227089U, // VEXTq16
+ 846751377U, // VEXTq32
+ 841508497U, // VEXTq8
+ 846751377U, // VEXTqf
+ 175661401U, // VGETLNi32
+ 165675353U, // VGETLNs16
+ 166199641U, // VGETLNs8
+ 167248217U, // VGETLNu16
+ 167772505U, // VGETLNu8
+ 166200982U, // VHADDsv16i8
+ 165152406U, // VHADDsv2i32
+ 165676694U, // VHADDsv4i16
+ 165152406U, // VHADDsv4i32
+ 165676694U, // VHADDsv8i16
+ 166200982U, // VHADDsv8i8
+ 167773846U, // VHADDuv16i8
+ 166725270U, // VHADDuv2i32
+ 167249558U, // VHADDuv4i16
+ 166725270U, // VHADDuv4i32
+ 167249558U, // VHADDuv8i16
+ 167773846U, // VHADDuv8i8
+ 166200988U, // VHSUBsv16i8
+ 165152412U, // VHSUBsv2i32
+ 165676700U, // VHSUBsv4i16
+ 165152412U, // VHSUBsv4i32
+ 165676700U, // VHSUBsv8i16
+ 166200988U, // VHSUBsv8i8
+ 167773852U, // VHSUBuv16i8
+ 166725276U, // VHSUBuv2i32
+ 167249564U, // VHSUBuv4i16
+ 166725276U, // VHSUBuv4i32
+ 167249564U, // VHSUBuv8i16
+ 167773852U, // VHSUBuv8i8
+ 243295906U, // VLD1d16
+ 1317037730U, // VLD1d16Q
+ 1384146594U, // VLD1d16T
+ 243820194U, // VLD1d32
+ 1317562018U, // VLD1d32Q
+ 1384670882U, // VLD1d32T
+ 244344482U, // VLD1d64
+ 244868770U, // VLD1d8
+ 1318610594U, // VLD1d8Q
+ 1385719458U, // VLD1d8T
+ 243820194U, // VLD1df
+ 242353826U, // VLD1q16
+ 242878114U, // VLD1q32
+ 245499554U, // VLD1q64
+ 237635234U, // VLD1q8
+ 242878114U, // VLD1qf
+ 1451255463U, // VLD2LNd16
+ 1451779751U, // VLD2LNd32
+ 1452828327U, // VLD2LNd8
+ 1451255463U, // VLD2LNq16a
+ 1451255463U, // VLD2LNq16b
+ 1451779751U, // VLD2LNq32a
+ 1451779751U, // VLD2LNq32b
+ 645949095U, // VLD2d16
+ 645949095U, // VLD2d16D
+ 646473383U, // VLD2d32
+ 646473383U, // VLD2d32D
+ 646997666U, // VLD2d64
+ 647521959U, // VLD2d8
+ 647521959U, // VLD2d8D
+ 1317037735U, // VLD2q16
+ 1317562023U, // VLD2q32
+ 1318610599U, // VLD2q8
+ 1518364332U, // VLD3LNd16
+ 1518888620U, // VLD3LNd32
+ 1519937196U, // VLD3LNd8
+ 1518364332U, // VLD3LNq16a
+ 1518364332U, // VLD3LNq16b
+ 1518888620U, // VLD3LNq32a
+ 1518888620U, // VLD3LNq32b
+ 1384146604U, // VLD3d16
+ 1384670892U, // VLD3d32
+ 1385195170U, // VLD3d64
+ 1385719468U, // VLD3d8
+ 1317037740U, // VLD3q16a
+ 1317037740U, // VLD3q16b
+ 1317562028U, // VLD3q32a
+ 1317562028U, // VLD3q32b
+ 1318610604U, // VLD3q8a
+ 1318610604U, // VLD3q8b
+ 1585473201U, // VLD4LNd16
+ 1585997489U, // VLD4LNd32
+ 1587046065U, // VLD4LNd8
+ 1585473201U, // VLD4LNq16a
+ 1585473201U, // VLD4LNq16b
+ 1585997489U, // VLD4LNq32a
+ 1585997489U, // VLD4LNq32b
+ 1317037745U, // VLD4d16
+ 1317562033U, // VLD4d32
+ 1318086306U, // VLD4d64
+ 1318610609U, // VLD4d8
+ 1451255473U, // VLD4q16a
+ 1451255473U, // VLD4q16b
+ 1451779761U, // VLD4q32a
+ 1451779761U, // VLD4q32b
+ 1452828337U, // VLD4q8a
+ 1452828337U, // VLD4q8b
+ 1610614454U, // VLDMD
+ 1610614454U, // VLDMS
+ 178284219U, // VLDRD
+ 135931584U, // VLDRQ
+ 175662779U, // VLDRS
+ 152102599U, // VMAXfd
+ 152102599U, // VMAXfd_sfp
+ 152102599U, // VMAXfq
+ 166201031U, // VMAXsv16i8
+ 165152455U, // VMAXsv2i32
+ 165676743U, // VMAXsv4i16
+ 165152455U, // VMAXsv4i32
+ 165676743U, // VMAXsv8i16
+ 166201031U, // VMAXsv8i8
+ 167773895U, // VMAXuv16i8
+ 166725319U, // VMAXuv2i32
+ 167249607U, // VMAXuv4i16
+ 166725319U, // VMAXuv4i32
+ 167249607U, // VMAXuv8i16
+ 167773895U, // VMAXuv8i8
+ 152102604U, // VMINfd
+ 152102604U, // VMINfd_sfp
+ 152102604U, // VMINfq
+ 166201036U, // VMINsv16i8
+ 165152460U, // VMINsv2i32
+ 165676748U, // VMINsv4i16
+ 165152460U, // VMINsv4i32
+ 165676748U, // VMINsv8i16
+ 166201036U, // VMINsv8i8
+ 167773900U, // VMINuv16i8
+ 166725324U, // VMINuv2i32
+ 167249612U, // VMINuv4i16
+ 166725324U, // VMINuv4i32
+ 167249612U, // VMINuv8i16
+ 167773900U, // VMINuv8i8
+ 822666961U, // VMLAD
+ 232277718U, // VMLALslsv2i32
+ 232802006U, // VMLALslsv4i16
+ 233850582U, // VMLALsluv2i32
+ 234374870U, // VMLALsluv4i16
+ 836257494U, // VMLALsv2i64
+ 836781782U, // VMLALsv4i32
+ 837306070U, // VMLALsv8i16
+ 837830358U, // VMLALuv2i64
+ 838354646U, // VMLALuv4i32
+ 838878934U, // VMLALuv8i16
+ 823191249U, // VMLAS
+ 823191249U, // VMLAfd
+ 823191249U, // VMLAfq
+ 219211473U, // VMLAslfd
+ 219211473U, // VMLAslfq
+ 235947729U, // VMLAslv2i32
+ 236472017U, // VMLAslv4i16
+ 235947729U, // VMLAslv4i32
+ 236472017U, // VMLAslv8i16
+ 840976081U, // VMLAv16i8
+ 839927505U, // VMLAv2i32
+ 840451793U, // VMLAv4i16
+ 839927505U, // VMLAv4i32
+ 840451793U, // VMLAv8i16
+ 840976081U, // VMLAv8i8
+ 822666972U, // VMLSD
+ 232277729U, // VMLSLslsv2i32
+ 232802017U, // VMLSLslsv4i16
+ 233850593U, // VMLSLsluv2i32
+ 234374881U, // VMLSLsluv4i16
+ 836257505U, // VMLSLsv2i64
+ 836781793U, // VMLSLsv4i32
+ 837306081U, // VMLSLsv8i16
+ 837830369U, // VMLSLuv2i64
+ 838354657U, // VMLSLuv4i32
+ 838878945U, // VMLSLuv8i16
+ 823191260U, // VMLSS
+ 823191260U, // VMLSfd
+ 823191260U, // VMLSfq
+ 219211484U, // VMLSslfd
+ 219211484U, // VMLSslfq
+ 235947740U, // VMLSslv2i32
+ 236472028U, // VMLSslv4i16
+ 235947740U, // VMLSslv4i32
+ 236472028U, // VMLSslv8i16
+ 840976092U, // VMLSv16i8
+ 839927516U, // VMLSv2i32
+ 840451804U, // VMLSv4i16
+ 839927516U, // VMLSv4i32
+ 840451804U, // VMLSv8i16
+ 840976092U, // VMLSv8i8
+ 755556697U, // VMOVD
+ 135815513U, // VMOVDRR
+ 151576921U, // VMOVDcc
+ 739795289U, // VMOVDneon
+ 769132263U, // VMOVLsv2i64
+ 769656551U, // VMOVLsv4i32
+ 770180839U, // VMOVLsv8i16
+ 770705127U, // VMOVLuv2i64
+ 771229415U, // VMOVLuv4i32
+ 771753703U, // VMOVLuv8i16
+ 772277997U, // VMOVNv2i32
+ 772802285U, // VMOVNv4i16
+ 773326573U, // VMOVNv8i8
+ 739795289U, // VMOVQ
+ 135815513U, // VMOVRRD
+ 806904153U, // VMOVRRS
+ 739795289U, // VMOVRS
+ 756080985U, // VMOVS
+ 739795289U, // VMOVSR
+ 806904153U, // VMOVSRR
+ 152101209U, // VMOVScc
+ 773996889U, // VMOVv16i8
+ 772432217U, // VMOVv1i64
+ 772964697U, // VMOVv2i32
+ 772432217U, // VMOVv2i64
+ 773497177U, // VMOVv4i16
+ 772964697U, // VMOVv4i32
+ 773497177U, // VMOVv8i16
+ 773996889U, // VMOVv8i8
+ 337142110U, // VMRS
+ 380110579U, // VMSR
+ 151578360U, // VMULD
+ 179308285U, // VMULLp
+ 836241149U, // VMULLslsv2i32
+ 836765437U, // VMULLslsv4i16
+ 837814013U, // VMULLsluv2i32
+ 838338301U, // VMULLsluv4i16
+ 165152509U, // VMULLsv2i64
+ 165676797U, // VMULLsv4i32
+ 166201085U, // VMULLsv8i16
+ 166725373U, // VMULLuv2i64
+ 167249661U, // VMULLuv4i32
+ 167773949U, // VMULLuv8i16
+ 152102648U, // VMULS
+ 152102648U, // VMULfd
+ 152102648U, // VMULfd_sfp
+ 152102648U, // VMULfq
+ 179308280U, // VMULpd
+ 179308280U, // VMULpq
+ 823191288U, // VMULslfd
+ 823191288U, // VMULslfq
+ 839911160U, // VMULslv2i32
+ 840435448U, // VMULslv4i16
+ 839911160U, // VMULslv4i32
+ 840435448U, // VMULslv8i16
+ 169871096U, // VMULv16i8
+ 168822520U, // VMULv2i32
+ 169346808U, // VMULv4i16
+ 168822520U, // VMULv4i32
+ 169346808U, // VMULv8i16
+ 169871096U, // VMULv8i8
+ 739796739U, // VMVNd
+ 739796739U, // VMVNq
+ 755558152U, // VNEGD
+ 151578376U, // VNEGDcc
+ 756082440U, // VNEGS
+ 152102664U, // VNEGScc
+ 756082440U, // VNEGf32q
+ 756082440U, // VNEGfd
+ 756082440U, // VNEGfd_sfp
+ 769656584U, // VNEGs16d
+ 769656584U, // VNEGs16q
+ 769132296U, // VNEGs32d
+ 769132296U, // VNEGs32q
+ 770180872U, // VNEGs8d
+ 770180872U, // VNEGs8q
+ 822667021U, // VNMLAD
+ 823191309U, // VNMLAS
+ 822667027U, // VNMLSD
+ 823191315U, // VNMLSS
+ 151578393U, // VNMULD
+ 152102681U, // VNMULS
+ 135816991U, // VORNd
+ 135816991U, // VORNq
+ 135816996U, // VORRd
+ 135816996U, // VORRq
+ 166217513U, // VPADALsv16i8
+ 165168937U, // VPADALsv2i32
+ 165693225U, // VPADALsv4i16
+ 165168937U, // VPADALsv4i32
+ 165693225U, // VPADALsv8i16
+ 166217513U, // VPADALsv8i8
+ 167790377U, // VPADALuv16i8
+ 166741801U, // VPADALuv2i32
+ 167266089U, // VPADALuv4i16
+ 166741801U, // VPADALuv4i32
+ 167266089U, // VPADALuv8i16
+ 167790377U, // VPADALuv8i8
+ 770180912U, // VPADDLsv16i8
+ 769132336U, // VPADDLsv2i32
+ 769656624U, // VPADDLsv4i16
+ 769132336U, // VPADDLsv4i32
+ 769656624U, // VPADDLsv8i16
+ 770180912U, // VPADDLsv8i8
+ 771753776U, // VPADDLuv16i8
+ 770705200U, // VPADDLuv2i32
+ 771229488U, // VPADDLuv4i16
+ 770705200U, // VPADDLuv4i32
+ 771229488U, // VPADDLuv8i16
+ 771753776U, // VPADDLuv8i8
+ 152102711U, // VPADDf
+ 169346871U, // VPADDi16
+ 168822583U, // VPADDi32
+ 169871159U, // VPADDi8
+ 152102717U, // VPMAXf
+ 165676861U, // VPMAXs16
+ 165152573U, // VPMAXs32
+ 166201149U, // VPMAXs8
+ 167249725U, // VPMAXu16
+ 166725437U, // VPMAXu32
+ 167774013U, // VPMAXu8
+ 152102723U, // VPMINf
+ 165676867U, // VPMINs16
+ 165152579U, // VPMINs32
+ 166201155U, // VPMINs8
+ 167249731U, // VPMINu16
+ 166725443U, // VPMINu32
+ 167774019U, // VPMINu8
+ 770180937U, // VQABSv16i8
+ 769132361U, // VQABSv2i32
+ 769656649U, // VQABSv4i16
+ 769132361U, // VQABSv4i32
+ 769656649U, // VQABSv8i16
+ 770180937U, // VQABSv8i8
+ 166201167U, // VQADDsv16i8
+ 179832655U, // VQADDsv1i64
+ 165152591U, // VQADDsv2i32
+ 179832655U, // VQADDsv2i64
+ 165676879U, // VQADDsv4i16
+ 165152591U, // VQADDsv4i32
+ 165676879U, // VQADDsv8i16
+ 166201167U, // VQADDsv8i8
+ 167774031U, // VQADDuv16i8
+ 180356943U, // VQADDuv1i64
+ 166725455U, // VQADDuv2i32
+ 180356943U, // VQADDuv2i64
+ 167249743U, // VQADDuv4i16
+ 166725455U, // VQADDuv4i32
+ 167249743U, // VQADDuv8i16
+ 167774031U, // VQADDuv8i8
+ 232277845U, // VQDMLALslv2i32
+ 232802133U, // VQDMLALslv4i16
+ 836257621U, // VQDMLALv2i64
+ 836781909U, // VQDMLALv4i32
+ 232277853U, // VQDMLSLslv2i32
+ 232802141U, // VQDMLSLslv4i16
+ 836257629U, // VQDMLSLv2i64
+ 836781917U, // VQDMLSLv4i32
+ 836241253U, // VQDMULHslv2i32
+ 836765541U, // VQDMULHslv4i16
+ 836241253U, // VQDMULHslv4i32
+ 836765541U, // VQDMULHslv8i16
+ 165152613U, // VQDMULHv2i32
+ 165676901U, // VQDMULHv4i16
+ 165152613U, // VQDMULHv4i32
+ 165676901U, // VQDMULHv8i16
+ 836241261U, // VQDMULLslv2i32
+ 836765549U, // VQDMULLslv4i16
+ 165152621U, // VQDMULLv2i64
+ 165676909U, // VQDMULLv4i32
+ 783812469U, // VQMOVNsuv2i32
+ 769132405U, // VQMOVNsuv4i16
+ 769656693U, // VQMOVNsuv8i8
+ 783812477U, // VQMOVNsv2i32
+ 769132413U, // VQMOVNsv4i16
+ 769656701U, // VQMOVNsv8i8
+ 784336765U, // VQMOVNuv2i32
+ 770705277U, // VQMOVNuv4i16
+ 771229565U, // VQMOVNuv8i8
+ 770180996U, // VQNEGv16i8
+ 769132420U, // VQNEGv2i32
+ 769656708U, // VQNEGv4i16
+ 769132420U, // VQNEGv4i32
+ 769656708U, // VQNEGv8i16
+ 770180996U, // VQNEGv8i8
+ 836241290U, // VQRDMULHslv2i32
+ 836765578U, // VQRDMULHslv4i16
+ 836241290U, // VQRDMULHslv4i32
+ 836765578U, // VQRDMULHslv8i16
+ 165152650U, // VQRDMULHv2i32
+ 165676938U, // VQRDMULHv4i16
+ 165152650U, // VQRDMULHv4i32
+ 165676938U, // VQRDMULHv8i16
+ 166201235U, // VQRSHLsv16i8
+ 179832723U, // VQRSHLsv1i64
+ 165152659U, // VQRSHLsv2i32
+ 179832723U, // VQRSHLsv2i64
+ 165676947U, // VQRSHLsv4i16
+ 165152659U, // VQRSHLsv4i32
+ 165676947U, // VQRSHLsv8i16
+ 166201235U, // VQRSHLsv8i8
+ 167774099U, // VQRSHLuv16i8
+ 180357011U, // VQRSHLuv1i64
+ 166725523U, // VQRSHLuv2i32
+ 180357011U, // VQRSHLuv2i64
+ 167249811U, // VQRSHLuv4i16
+ 166725523U, // VQRSHLuv4i32
+ 167249811U, // VQRSHLuv8i16
+ 167774099U, // VQRSHLuv8i8
+ 179832730U, // VQRSHRNsv2i32
+ 165152666U, // VQRSHRNsv4i16
+ 165676954U, // VQRSHRNsv8i8
+ 180357018U, // VQRSHRNuv2i32
+ 166725530U, // VQRSHRNuv4i16
+ 167249818U, // VQRSHRNuv8i8
+ 179832738U, // VQRSHRUNv2i32
+ 165152674U, // VQRSHRUNv4i16
+ 165676962U, // VQRSHRUNv8i8
+ 166201259U, // VQSHLsiv16i8
+ 179832747U, // VQSHLsiv1i64
+ 165152683U, // VQSHLsiv2i32
+ 179832747U, // VQSHLsiv2i64
+ 165676971U, // VQSHLsiv4i16
+ 165152683U, // VQSHLsiv4i32
+ 165676971U, // VQSHLsiv8i16
+ 166201259U, // VQSHLsiv8i8
+ 166201265U, // VQSHLsuv16i8
+ 179832753U, // VQSHLsuv1i64
+ 165152689U, // VQSHLsuv2i32
+ 179832753U, // VQSHLsuv2i64
+ 165676977U, // VQSHLsuv4i16
+ 165152689U, // VQSHLsuv4i32
+ 165676977U, // VQSHLsuv8i16
+ 166201265U, // VQSHLsuv8i8
+ 166201259U, // VQSHLsv16i8
+ 179832747U, // VQSHLsv1i64
+ 165152683U, // VQSHLsv2i32
+ 179832747U, // VQSHLsv2i64
+ 165676971U, // VQSHLsv4i16
+ 165152683U, // VQSHLsv4i32
+ 165676971U, // VQSHLsv8i16
+ 166201259U, // VQSHLsv8i8
+ 167774123U, // VQSHLuiv16i8
+ 180357035U, // VQSHLuiv1i64
+ 166725547U, // VQSHLuiv2i32
+ 180357035U, // VQSHLuiv2i64
+ 167249835U, // VQSHLuiv4i16
+ 166725547U, // VQSHLuiv4i32
+ 167249835U, // VQSHLuiv8i16
+ 167774123U, // VQSHLuiv8i8
+ 167774123U, // VQSHLuv16i8
+ 180357035U, // VQSHLuv1i64
+ 166725547U, // VQSHLuv2i32
+ 180357035U, // VQSHLuv2i64
+ 167249835U, // VQSHLuv4i16
+ 166725547U, // VQSHLuv4i32
+ 167249835U, // VQSHLuv8i16
+ 167774123U, // VQSHLuv8i8
+ 179832760U, // VQSHRNsv2i32
+ 165152696U, // VQSHRNsv4i16
+ 165676984U, // VQSHRNsv8i8
+ 180357048U, // VQSHRNuv2i32
+ 166725560U, // VQSHRNuv4i16
+ 167249848U, // VQSHRNuv8i8
+ 179832767U, // VQSHRUNv2i32
+ 165152703U, // VQSHRUNv4i16
+ 165676991U, // VQSHRUNv8i8
+ 166201287U, // VQSUBsv16i8
+ 179832775U, // VQSUBsv1i64
+ 165152711U, // VQSUBsv2i32
+ 179832775U, // VQSUBsv2i64
+ 165676999U, // VQSUBsv4i16
+ 165152711U, // VQSUBsv4i32
+ 165676999U, // VQSUBsv8i16
+ 166201287U, // VQSUBsv8i8
+ 167774151U, // VQSUBuv16i8
+ 180357063U, // VQSUBuv1i64
+ 166725575U, // VQSUBuv2i32
+ 180357063U, // VQSUBuv2i64
+ 167249863U, // VQSUBuv4i16
+ 166725575U, // VQSUBuv4i32
+ 167249863U, // VQSUBuv8i16
+ 167774151U, // VQSUBuv8i8
+ 168298445U, // VRADDHNv2i32
+ 168822733U, // VRADDHNv4i16
+ 169347021U, // VRADDHNv8i8
+ 770705365U, // VRECPEd
+ 756082645U, // VRECPEfd
+ 756082645U, // VRECPEfq
+ 770705365U, // VRECPEq
+ 152102876U, // VRECPSfd
+ 152102876U, // VRECPSfq
+ 774399971U, // VREV16d8
+ 774399971U, // VREV16q8
+ 779118570U, // VREV32d16
+ 774399978U, // VREV32d8
+ 779118570U, // VREV32q16
+ 774399978U, // VREV32q8
+ 779118577U, // VREV64d16
+ 779642865U, // VREV64d32
+ 774399985U, // VREV64d8
+ 779642865U, // VREV64df
+ 779118577U, // VREV64q16
+ 779642865U, // VREV64q32
+ 774399985U, // VREV64q8
+ 779642865U, // VREV64qf
+ 166201336U, // VRHADDsv16i8
+ 165152760U, // VRHADDsv2i32
+ 165677048U, // VRHADDsv4i16
+ 165152760U, // VRHADDsv4i32
+ 165677048U, // VRHADDsv8i16
+ 166201336U, // VRHADDsv8i8
+ 167774200U, // VRHADDuv16i8
+ 166725624U, // VRHADDuv2i32
+ 167249912U, // VRHADDuv4i16
+ 166725624U, // VRHADDuv4i32
+ 167249912U, // VRHADDuv8i16
+ 167774200U, // VRHADDuv8i8
+ 166201343U, // VRSHLsv16i8
+ 179832831U, // VRSHLsv1i64
+ 165152767U, // VRSHLsv2i32
+ 179832831U, // VRSHLsv2i64
+ 165677055U, // VRSHLsv4i16
+ 165152767U, // VRSHLsv4i32
+ 165677055U, // VRSHLsv8i16
+ 166201343U, // VRSHLsv8i8
+ 167774207U, // VRSHLuv16i8
+ 180357119U, // VRSHLuv1i64
+ 166725631U, // VRSHLuv2i32
+ 180357119U, // VRSHLuv2i64
+ 167249919U, // VRSHLuv4i16
+ 166725631U, // VRSHLuv4i32
+ 167249919U, // VRSHLuv8i16
+ 167774207U, // VRSHLuv8i8
+ 168298501U, // VRSHRNv2i32
+ 168822789U, // VRSHRNv4i16
+ 169347077U, // VRSHRNv8i8
+ 166201356U, // VRSHRsv16i8
+ 179832844U, // VRSHRsv1i64
+ 165152780U, // VRSHRsv2i32
+ 179832844U, // VRSHRsv2i64
+ 165677068U, // VRSHRsv4i16
+ 165152780U, // VRSHRsv4i32
+ 165677068U, // VRSHRsv8i16
+ 166201356U, // VRSHRsv8i8
+ 167774220U, // VRSHRuv16i8
+ 180357132U, // VRSHRuv1i64
+ 166725644U, // VRSHRuv2i32
+ 180357132U, // VRSHRuv2i64
+ 167249932U, // VRSHRuv4i16
+ 166725644U, // VRSHRuv4i32
+ 167249932U, // VRSHRuv8i16
+ 167774220U, // VRSHRuv8i8
+ 770705426U, // VRSQRTEd
+ 756082706U, // VRSQRTEfd
+ 756082706U, // VRSQRTEfq
+ 770705426U, // VRSQRTEq
+ 152102938U, // VRSQRTSfd
+ 152102938U, // VRSQRTSfq
+ 837306402U, // VRSRAsv16i8
+ 850937890U, // VRSRAsv1i64
+ 836257826U, // VRSRAsv2i32
+ 850937890U, // VRSRAsv2i64
+ 836782114U, // VRSRAsv4i16
+ 836257826U, // VRSRAsv4i32
+ 836782114U, // VRSRAsv8i16
+ 837306402U, // VRSRAsv8i8
+ 838879266U, // VRSRAuv16i8
+ 851462178U, // VRSRAuv1i64
+ 837830690U, // VRSRAuv2i32
+ 851462178U, // VRSRAuv2i64
+ 838354978U, // VRSRAuv4i16
+ 837830690U, // VRSRAuv4i32
+ 838354978U, // VRSRAuv8i16
+ 838879266U, // VRSRAuv8i8
+ 168298536U, // VRSUBHNv2i32
+ 168822824U, // VRSUBHNv4i16
+ 169347112U, // VRSUBHNv8i8
+ 846225753U, // VSETLNi16
+ 846750041U, // VSETLNi32
+ 841507161U, // VSETLNi8
+ 169347120U, // VSHLLi16
+ 168822832U, // VSHLLi32
+ 169871408U, // VSHLLi8
+ 165152816U, // VSHLLsv2i64
+ 165677104U, // VSHLLsv4i32
+ 166201392U, // VSHLLsv8i16
+ 166725680U, // VSHLLuv2i64
+ 167249968U, // VSHLLuv4i32
+ 167774256U, // VSHLLuv8i16
+ 169871414U, // VSHLiv16i8
+ 168298550U, // VSHLiv1i64
+ 168822838U, // VSHLiv2i32
+ 168298550U, // VSHLiv2i64
+ 169347126U, // VSHLiv4i16
+ 168822838U, // VSHLiv4i32
+ 169347126U, // VSHLiv8i16
+ 169871414U, // VSHLiv8i8
+ 166201398U, // VSHLsv16i8
+ 179832886U, // VSHLsv1i64
+ 165152822U, // VSHLsv2i32
+ 179832886U, // VSHLsv2i64
+ 165677110U, // VSHLsv4i16
+ 165152822U, // VSHLsv4i32
+ 165677110U, // VSHLsv8i16
+ 166201398U, // VSHLsv8i8
+ 167774262U, // VSHLuv16i8
+ 180357174U, // VSHLuv1i64
+ 166725686U, // VSHLuv2i32
+ 180357174U, // VSHLuv2i64
+ 167249974U, // VSHLuv4i16
+ 166725686U, // VSHLuv4i32
+ 167249974U, // VSHLuv8i16
+ 167774262U, // VSHLuv8i8
+ 168298555U, // VSHRNv2i32
+ 168822843U, // VSHRNv4i16
+ 169347131U, // VSHRNv8i8
+ 166201409U, // VSHRsv16i8
+ 179832897U, // VSHRsv1i64
+ 165152833U, // VSHRsv2i32
+ 179832897U, // VSHRsv2i64
+ 165677121U, // VSHRsv4i16
+ 165152833U, // VSHRsv4i32
+ 165677121U, // VSHRsv8i16
+ 166201409U, // VSHRsv8i8
+ 167774273U, // VSHRuv16i8
+ 180357185U, // VSHRuv1i64
+ 166725697U, // VSHRuv2i32
+ 180357185U, // VSHRuv2i64
+ 167249985U, // VSHRuv4i16
+ 166725697U, // VSHRuv4i32
+ 167249985U, // VSHRuv8i16
+ 167774273U, // VSHRuv8i8
+ 180881015U, // VSHTOD
+ 181405303U, // VSHTOS
+ 786032247U, // VSITOD
+ 778167927U, // VSITOS
+ 841508934U, // VSLIv16i8
+ 849373254U, // VSLIv1i64
+ 846751814U, // VSLIv2i32
+ 849373254U, // VSLIv2i64
+ 846227526U, // VSLIv4i16
+ 846751814U, // VSLIv4i32
+ 846227526U, // VSLIv8i16
+ 841508934U, // VSLIv8i8
+ 181986935U, // VSLTOD
+ 174122615U, // VSLTOS
+ 755558475U, // VSQRTD
+ 756082763U, // VSQRTS
+ 837306449U, // VSRAsv16i8
+ 850937937U, // VSRAsv1i64
+ 836257873U, // VSRAsv2i32
+ 850937937U, // VSRAsv2i64
+ 836782161U, // VSRAsv4i16
+ 836257873U, // VSRAsv4i32
+ 836782161U, // VSRAsv8i16
+ 837306449U, // VSRAsv8i8
+ 838879313U, // VSRAuv16i8
+ 851462225U, // VSRAuv1i64
+ 837830737U, // VSRAuv2i32
+ 851462225U, // VSRAuv2i64
+ 838355025U, // VSRAuv4i16
+ 837830737U, // VSRAuv4i32
+ 838355025U, // VSRAuv8i16
+ 838879313U, // VSRAuv8i8
+ 841508950U, // VSRIv16i8
+ 849373270U, // VSRIv1i64
+ 846751830U, // VSRIv2i32
+ 849373270U, // VSRIv2i64
+ 846227542U, // VSRIv4i16
+ 846751830U, // VSRIv4i32
+ 846227542U, // VSRIv8i16
+ 841508950U, // VSRIv8i8
+ 243451995U, // VST1d16
+ 1317193819U, // VST1d16Q
+ 1384302683U, // VST1d16T
+ 243976283U, // VST1d32
+ 1317718107U, // VST1d32Q
+ 1384826971U, // VST1d32T
+ 244500571U, // VST1d64
+ 245024859U, // VST1d8
+ 1318766683U, // VST1d8Q
+ 1385875547U, // VST1d8T
+ 243976283U, // VST1df
+ 242411611U, // VST1q16
+ 242935899U, // VST1q32
+ 245557339U, // VST1q64
+ 237693019U, // VST1q8
+ 242935899U, // VST1qf
+ 1384302688U, // VST2LNd16
+ 1384826976U, // VST2LNd32
+ 1385875552U, // VST2LNd8
+ 1384302688U, // VST2LNq16a
+ 1384302688U, // VST2LNq16b
+ 1384826976U, // VST2LNq32a
+ 1384826976U, // VST2LNq32b
+ 646105184U, // VST2d16
+ 646105184U, // VST2d16D
+ 646629472U, // VST2d32
+ 646629472U, // VST2d32D
+ 647153755U, // VST2d64
+ 647678048U, // VST2d8
+ 647678048U, // VST2d8D
+ 1317193824U, // VST2q16
+ 1317718112U, // VST2q32
+ 1318766688U, // VST2q8
+ 1317193829U, // VST3LNd16
+ 1317718117U, // VST3LNd32
+ 1318766693U, // VST3LNd8
+ 1317193829U, // VST3LNq16a
+ 1317193829U, // VST3LNq16b
+ 1317718117U, // VST3LNq32a
+ 1317718117U, // VST3LNq32b
+ 1384302693U, // VST3d16
+ 1384826981U, // VST3d32
+ 1385351259U, // VST3d64
+ 1385875557U, // VST3d8
+ 1317210213U, // VST3q16a
+ 1317210213U, // VST3q16b
+ 1317734501U, // VST3q32a
+ 1317734501U, // VST3q32b
+ 1318783077U, // VST3q8a
+ 1318783077U, // VST3q8b
+ 1451411562U, // VST4LNd16
+ 1451935850U, // VST4LNd32
+ 1452984426U, // VST4LNd8
+ 1451411562U, // VST4LNq16a
+ 1451411562U, // VST4LNq16b
+ 1451935850U, // VST4LNq32a
+ 1451935850U, // VST4LNq32b
+ 1317193834U, // VST4d16
+ 1317718122U, // VST4d32
+ 1318242395U, // VST4d64
+ 1318766698U, // VST4d8
+ 1451427946U, // VST4q16a
+ 1451427946U, // VST4q16b
+ 1451952234U, // VST4q32a
+ 1451952234U, // VST4q32b
+ 1453000810U, // VST4q8a
+ 1453000810U, // VST4q8b
+ 1610614895U, // VSTMD
+ 1610614895U, // VSTMS
+ 178284660U, // VSTRD
+ 135932025U, // VSTRQ
+ 175663220U, // VSTRS
+ 151578752U, // VSUBD
+ 168298629U, // VSUBHNv2i32
+ 168822917U, // VSUBHNv4i16
+ 169347205U, // VSUBHNv8i8
+ 165152908U, // VSUBLsv2i64
+ 165677196U, // VSUBLsv4i32
+ 166201484U, // VSUBLsv8i16
+ 166725772U, // VSUBLuv2i64
+ 167250060U, // VSUBLuv4i32
+ 167774348U, // VSUBLuv8i16
+ 152103040U, // VSUBS
+ 165152914U, // VSUBWsv2i64
+ 165677202U, // VSUBWsv4i32
+ 166201490U, // VSUBWsv8i16
+ 166725778U, // VSUBWuv2i64
+ 167250066U, // VSUBWuv4i32
+ 167774354U, // VSUBWuv8i16
+ 152103040U, // VSUBfd
+ 152103040U, // VSUBfd_sfp
+ 152103040U, // VSUBfq
+ 169871488U, // VSUBv16i8
+ 168298624U, // VSUBv1i64
+ 168822912U, // VSUBv2i32
+ 168298624U, // VSUBv2i64
+ 169347200U, // VSUBv4i16
+ 168822912U, // VSUBv4i32
+ 169347200U, // VSUBv8i16
+ 169871488U, // VSUBv8i8
+ 739797144U, // VSWPd
+ 739797144U, // VSWPq
+ 170420381U, // VTBL1
+ 841509021U, // VTBL2
+ 237529245U, // VTBL3
+ 640182429U, // VTBL4
+ 841509026U, // VTBX1
+ 237529250U, // VTBX2
+ 640182434U, // VTBX3
+ 1378379938U, // VTBX4
+ 182453879U, // VTOSHD
+ 182978167U, // VTOSHS
+ 787605671U, // VTOSIRD
+ 777119911U, // VTOSIRS
+ 787605111U, // VTOSIZD
+ 777119351U, // VTOSIZS
+ 183559799U, // VTOSLD
+ 173074039U, // VTOSLS
+ 184026743U, // VTOUHD
+ 184551031U, // VTOUHS
+ 789178535U, // VTOUIRD
+ 777644199U, // VTOUIRS
+ 789177975U, // VTOUIZD
+ 777643639U, // VTOUIZS
+ 185132663U, // VTOULD
+ 173598327U, // VTOULS
+ 846227629U, // VTRNd16
+ 846751917U, // VTRNd32
+ 841509037U, // VTRNd8
+ 846227629U, // VTRNq16
+ 846751917U, // VTRNq32
+ 841509037U, // VTRNq8
+ 170420402U, // VTSTv16i8
+ 175663282U, // VTSTv2i32
+ 175138994U, // VTSTv4i16
+ 175663282U, // VTSTv4i32
+ 175138994U, // VTSTv8i16
+ 170420402U, // VTSTv8i8
+ 185599607U, // VUHTOD
+ 186123895U, // VUHTOS
+ 790750839U, // VUITOD
+ 778692215U, // VUITOS
+ 186705527U, // VULTOD
+ 174646903U, // VULTOS
+ 846227639U, // VUZPd16
+ 846751927U, // VUZPd32
+ 841509047U, // VUZPd8
+ 846227639U, // VUZPq16
+ 846751927U, // VUZPq32
+ 841509047U, // VUZPq8
+ 846227644U, // VZIPd16
+ 846751932U, // VZIPd32
+ 841509052U, // VZIPd8
+ 846227644U, // VZIPq16
+ 846751932U, // VZIPq32
+ 841509052U, // VZIPq8
+ 538970305U, // WFE
+ 538970309U, // WFI
+ 538970313U, // YIELD
1679319057U, // t2ADCSri
- 1730207761U, // t2ADCSrr
- 1797316625U, // t2ADCSrs
+ 1730732049U, // t2ADCSrr
+ 1797840913U, // t2ADCSrs
1679319057U, // t2ADCri
- 1730207761U, // t2ADCrr
- 1797316625U, // t2ADCrs
- 186703893U, // t2ADDSri
- 186703893U, // t2ADDSrr
- 857792533U, // t2ADDSrs
- 1730207770U, // t2ADDrSPi
- 135817402U, // t2ADDrSPi12
- 1797316634U, // t2ADDrSPs
- 1730207770U, // t2ADDri
- 1679321274U, // t2ADDri12
- 1730207770U, // t2ADDrr
- 1797316634U, // t2ADDrs
+ 1730732049U, // t2ADCrr
+ 1797840913U, // t2ADCrs
+ 187228181U, // t2ADDSri
+ 187228181U, // t2ADDSrr
+ 858316821U, // t2ADDSrs
+ 1730732058U, // t2ADDrSPi
+ 135817423U, // t2ADDrSPi12
+ 1797840922U, // t2ADDrSPs
+ 1730732058U, // t2ADDri
+ 1679321295U, // t2ADDri12
+ 1730732058U, // t2ADDrr
+ 1797840922U, // t2ADDrs
1679319108U, // t2ANDri
- 1730207812U, // t2ANDrr
- 1797316676U, // t2ANDrs
- 1730209983U, // t2ASRri
- 1730209983U, // t2ASRrr
- 69208259U, // t2B
+ 1730732100U, // t2ANDrr
+ 1797840964U, // t2ANDrs
+ 1730734292U, // t2ASRri
+ 1730734292U, // t2ASRrr
+ 69208280U, // t2B
135815244U, // t2BFC
806903888U, // t2BFI
1679319124U, // t2BICri
- 1730207828U, // t2BICrr
- 1797316692U, // t2BICrs
- 120062079U, // t2BR_JT
- 337141912U, // t2BXJ
- 388096159U, // t2Bcc
- 538968236U, // t2CLREX
- 739795122U, // t2CLZ
- 790683830U, // t2CMNzri
- 790683830U, // t2CMNzrr
- 186704054U, // t2CMNzrs
- 790683834U, // t2CMPri
- 790683834U, // t2CMPrr
- 186704058U, // t2CMPrs
- 790683834U, // t2CMPzri
- 790683834U, // t2CMPzrr
- 186704058U, // t2CMPzrs
- 939524286U, // t2CPS
- 337141954U, // t2DBG
- 590348639U, // t2DMBish
- 590872927U, // t2DMBishst
- 591397215U, // t2DMBnsh
- 591921503U, // t2DMBnshst
- 592445791U, // t2DMBosh
- 592970079U, // t2DMBoshst
- 593494367U, // t2DMBst
- 590348643U, // t2DSBish
- 590872931U, // t2DSBishst
- 591397219U, // t2DSBnsh
- 591921507U, // t2DSBnshst
- 592445795U, // t2DSBosh
- 592970083U, // t2DSBoshst
- 593494371U, // t2DSBst
- 1679319360U, // t2EORri
- 1730208064U, // t2EORrr
- 1797316928U, // t2EORrs
- 538968398U, // t2ISBsy
- 1811941576U, // t2IT
- 351U, // t2Int_MemBarrierV7
- 355U, // t2Int_SyncBarrierV7
- 1879050443U, // t2Int_eh_sjlj_setjmp
- 1027809658U, // t2LDM
- 1027809658U, // t2LDM_RET
- 135815559U, // t2LDRBT
- 806904194U, // t2LDRB_POST
- 806904194U, // t2LDRB_PRE
- 186704258U, // t2LDRBi12
- 135815554U, // t2LDRBi8
- 790684034U, // t2LDRBpci
- 857792898U, // t2LDRBs
- 806904205U, // t2LDRDi8
- 135815565U, // t2LDRDpci
- 739795346U, // t2LDREX
- 739795352U, // t2LDREXB
- 135815583U, // t2LDREXD
- 739795366U, // t2LDREXH
- 135815602U, // t2LDRHT
- 806904237U, // t2LDRH_POST
- 806904237U, // t2LDRH_PRE
- 186704301U, // t2LDRHi12
- 135815597U, // t2LDRHi8
- 790684077U, // t2LDRHpci
- 857792941U, // t2LDRHs
- 135815614U, // t2LDRSBT
- 806904248U, // t2LDRSB_POST
- 806904248U, // t2LDRSB_PRE
- 186704312U, // t2LDRSBi12
- 135815608U, // t2LDRSBi8
- 790684088U, // t2LDRSBpci
- 857792952U, // t2LDRSBs
- 135815627U, // t2LDRSHT
- 806904261U, // t2LDRSH_POST
- 806904261U, // t2LDRSH_PRE
- 186704325U, // t2LDRSHi12
- 135815621U, // t2LDRSHi8
- 790684101U, // t2LDRSHpci
- 857792965U, // t2LDRSHs
- 135815634U, // t2LDRT
- 806904190U, // t2LDR_POST
- 806904190U, // t2LDR_PRE
- 186704254U, // t2LDRi12
- 135815550U, // t2LDRi8
- 790684030U, // t2LDRpci
- 67111120U, // t2LDRpci_pic
- 857792894U, // t2LDRs
- 790841561U, // t2LEApcrel
- 186861785U, // t2LEApcrelJT
- 1730210013U, // t2LSLri
- 1730210013U, // t2LSLrr
- 1730210017U, // t2LSRri
- 1730210017U, // t2LSRrr
- 806904309U, // t2MLA
- 806904313U, // t2MLS
- 857794751U, // t2MOVCCasr
- 186704381U, // t2MOVCCi
- 857794781U, // t2MOVCClsl
- 857794785U, // t2MOVCClsr
- 186704381U, // t2MOVCCr
- 857794789U, // t2MOVCCror
- 135815681U, // t2MOVTi16
- 1967350269U, // t2MOVi
- 739795462U, // t2MOVi16
- 739795462U, // t2MOVi32imm
- 1967350269U, // t2MOVr
- 1967212777U, // t2MOVrx
- 67111149U, // t2MOVsra_flag
- 67111157U, // t2MOVsrl_flag
- 337142312U, // t2MRS
- 337142312U, // t2MRSsys
- 359162412U, // t2MSR
- 359686700U, // t2MSRsys
- 135815728U, // t2MUL
- 1967211060U, // t2MVNi
- 790684212U, // t2MVNr
- 186704436U, // t2MVNs
- 594018872U, // t2NOP
- 1679321341U, // t2ORNri
- 1679321341U, // t2ORNrr
- 1746430205U, // t2ORNrs
- 1679319612U, // t2ORRri
- 1730208316U, // t2ORRrr
- 1797317180U, // t2ORRrs
- 806904386U, // t2PKHBT
- 806904392U, // t2PKHTB
- 740002049U, // t2PLDWi12
- 740010241U, // t2PLDWi8
- 795871489U, // t2PLDWpci
- 796641537U, // t2PLDWr
- 192669953U, // t2PLDWs
- 740002054U, // t2PLDi12
- 740010246U, // t2PLDi8
- 795871494U, // t2PLDpci
- 796641542U, // t2PLDr
- 192669958U, // t2PLDs
- 740002058U, // t2PLIi12
- 740010250U, // t2PLIi8
- 795871498U, // t2PLIpci
- 796641546U, // t2PLIr
- 192669962U, // t2PLIs
- 135815793U, // t2QADD
- 135815798U, // t2QADD16
- 135815805U, // t2QADD8
- 135815811U, // t2QASX
- 135815816U, // t2QDADD
- 135815822U, // t2QDSUB
- 135815828U, // t2QSAX
- 135815833U, // t2QSUB
- 135815838U, // t2QSUB16
- 135815845U, // t2QSUB8
- 739795627U, // t2RBIT
- 790684336U, // t2REV
- 790684340U, // t2REV16
- 790684346U, // t2REVSH
- 337144078U, // t2RFEDB
- 337144084U, // t2RFEDBW
- 337144090U, // t2RFEIA
- 337144090U, // t2RFEIAW
- 1730210021U, // t2RORri
- 1730210021U, // t2RORrr
- 2013266633U, // t2RSBSri
- 1947755209U, // t2RSBSrs
- 186704585U, // t2RSBri
- 806904521U, // t2RSBrs
- 135815895U, // t2SADD16
- 135815902U, // t2SADD8
- 135815908U, // t2SASX
- 1679319791U, // t2SBCSri
- 1730208495U, // t2SBCSrr
- 1797317359U, // t2SBCSrs
- 1679319791U, // t2SBCri
- 1730208495U, // t2SBCrr
- 1797317359U, // t2SBCrs
- 806904563U, // t2SBFX
- 135817504U, // t2SDIV
- 135815928U, // t2SEL
- 594019088U, // t2SEV
- 135815956U, // t2SHADD16
- 135815964U, // t2SHADD8
- 135815971U, // t2SHASX
- 135815977U, // t2SHSAX
- 135815983U, // t2SHSUB16
- 135815991U, // t2SHSUB8
- 337142590U, // t2SMC
- 806904642U, // t2SMLABB
- 806904649U, // t2SMLABT
- 806904656U, // t2SMLAD
- 806904662U, // t2SMLADX
- 806904669U, // t2SMLAL
- 806904675U, // t2SMLALBB
- 806904683U, // t2SMLALBT
- 806904691U, // t2SMLALD
- 806904698U, // t2SMLALDX
- 806904706U, // t2SMLALTB
- 806904714U, // t2SMLALTT
- 806904722U, // t2SMLATB
- 806904729U, // t2SMLATT
- 806904736U, // t2SMLAWB
- 806904743U, // t2SMLAWT
- 806904750U, // t2SMLSD
- 806904756U, // t2SMLSDX
- 806904763U, // t2SMLSLD
- 806904770U, // t2SMLSLDX
- 806904778U, // t2SMMLA
- 806904784U, // t2SMMLAR
- 806904791U, // t2SMMLS
- 806904797U, // t2SMMLSR
- 135816164U, // t2SMMUL
- 135816170U, // t2SMMULR
- 135816177U, // t2SMUAD
- 135816183U, // t2SMUADX
- 135816190U, // t2SMULBB
- 135816197U, // t2SMULBT
- 806904844U, // t2SMULL
- 135816210U, // t2SMULTB
- 135816217U, // t2SMULTT
- 135816224U, // t2SMULWB
- 135816231U, // t2SMULWT
- 135816238U, // t2SMUSD
- 135816244U, // t2SMUSDX
- 364931365U, // t2SRSDB
- 365455653U, // t2SRSDBW
- 364931371U, // t2SRSIA
- 365455659U, // t2SRSIAW
- 135816255U, // t2SSAT16
- 806904902U, // t2SSATasr
- 806904902U, // t2SSATlsl
- 135816267U, // t2SSAX
- 135816272U, // t2SSUB16
- 135816279U, // t2SSUB8
- 1027810406U, // t2STM
- 135816307U, // t2STRBT
- 806880366U, // t2STRB_POST
- 806880366U, // t2STRB_PRE
- 186705006U, // t2STRBi12
- 135816302U, // t2STRBi8
- 857793646U, // t2STRBs
- 806904953U, // t2STRDi8
- 135816318U, // t2STREX
- 135816324U, // t2STREXB
- 806904971U, // t2STREXD
- 135816338U, // t2STREXH
- 135816350U, // t2STRHT
- 806880409U, // t2STRH_POST
- 806880409U, // t2STRH_PRE
- 186705049U, // t2STRHi12
- 135816345U, // t2STRHi8
- 857793689U, // t2STRHs
- 135816356U, // t2STRT
- 806880362U, // t2STR_POST
- 806880362U, // t2STR_PRE
- 186705002U, // t2STRi12
- 135816298U, // t2STRi8
- 857793642U, // t2STRs
- 186705065U, // t2SUBSri
- 186705065U, // t2SUBSrr
- 857793705U, // t2SUBSrs
- 1730208942U, // t2SUBrSPi
- 135817521U, // t2SUBrSPi12
- 67111222U, // t2SUBrSPi12_
- 67111230U, // t2SUBrSPi_
- 1746429102U, // t2SUBrSPs
- 67111239U, // t2SUBrSPs_
- 1730208942U, // t2SUBri
- 1679321393U, // t2SUBri12
- 1730208942U, // t2SUBrr
- 1797317806U, // t2SUBrs
- 135816383U, // t2SXTAB16rr
- 806905023U, // t2SXTAB16rr_rot
- 135816391U, // t2SXTABrr
- 806905031U, // t2SXTABrr_rot
- 135816397U, // t2SXTAHrr
- 806905037U, // t2SXTAHrr_rot
- 739796179U, // t2SXTB16r
- 135816403U, // t2SXTB16r_rot
- 790684890U, // t2SXTBr
- 186705114U, // t2SXTBr_rot
- 790684895U, // t2SXTHr
- 186705119U, // t2SXTHr_rot
- 2080377166U, // t2TBB
- 796641619U, // t2TBBgen
- 2080377175U, // t2TBH
- 796658012U, // t2TBHgen
- 790684900U, // t2TEQri
- 790684900U, // t2TEQrr
- 186705124U, // t2TEQrs
- 1256U, // t2TPsoft
- 790684928U, // t2TSTri
- 790684928U, // t2TSTrr
- 186705152U, // t2TSTrs
- 135816452U, // t2UADD16
- 135816459U, // t2UADD8
- 135816465U, // t2UASX
- 806905110U, // t2UBFX
- 135817568U, // t2UDIV
- 135816475U, // t2UHADD16
- 135816483U, // t2UHADD8
- 135816490U, // t2UHASX
- 135816496U, // t2UHSAX
- 135816502U, // t2UHSUB16
- 135816510U, // t2UHSUB8
- 806905157U, // t2UMAAL
- 806905163U, // t2UMLAL
- 806905169U, // t2UMULL
- 135816535U, // t2UQADD16
- 135816543U, // t2UQADD8
- 135816550U, // t2UQASX
- 135816556U, // t2UQSAX
- 135816562U, // t2UQSUB16
- 135816570U, // t2UQSUB8
- 135816577U, // t2USAD8
- 806905223U, // t2USADA8
- 135816590U, // t2USAT16
- 806905237U, // t2USATasr
- 806905237U, // t2USATlsl
- 135816602U, // t2USAX
- 135816607U, // t2USUB16
- 135816614U, // t2USUB8
- 135816620U, // t2UXTAB16rr
- 806905260U, // t2UXTAB16rr_rot
- 135816628U, // t2UXTABrr
- 806905268U, // t2UXTABrr_rot
- 135816634U, // t2UXTAHrr
- 806905274U, // t2UXTAHrr_rot
- 739796416U, // t2UXTB16r
- 135816640U, // t2UXTB16r_rot
- 790685127U, // t2UXTBr
- 186705351U, // t2UXTBr_rot
- 790685132U, // t2UXTHr
- 186705356U, // t2UXTHr_rot
- 594020524U, // t2WFE
- 594020528U, // t2WFI
- 594020532U, // t2YIELD
- 2206474257U, // tADC
+ 1730732116U, // t2BICrr
+ 1797840980U, // t2BICrs
+ 120586388U, // t2BR_JT
+ 337141933U, // t2BXJ
+ 388620468U, // t2Bcc
+ 538968257U, // t2CLREX
+ 739795143U, // t2CLZ
+ 791208139U, // t2CMNzri
+ 791208139U, // t2CMNzrr
+ 187228363U, // t2CMNzrs
+ 791208143U, // t2CMPri
+ 791208143U, // t2CMPrr
+ 187228367U, // t2CMPrs
+ 791208143U, // t2CMPzri
+ 791208143U, // t2CMPzrr
+ 187228367U, // t2CMPzrs
+ 939524307U, // t2CPS
+ 337141975U, // t2DBG
+ 590872948U, // t2DMBish
+ 591397236U, // t2DMBishst
+ 591921524U, // t2DMBnsh
+ 592445812U, // t2DMBnshst
+ 592970100U, // t2DMBosh
+ 593494388U, // t2DMBoshst
+ 594018676U, // t2DMBst
+ 590872952U, // t2DSBish
+ 591397240U, // t2DSBishst
+ 591921528U, // t2DSBnsh
+ 592445816U, // t2DSBnshst
+ 592970104U, // t2DSBosh
+ 593494392U, // t2DSBoshst
+ 594018680U, // t2DSBst
+ 1679319381U, // t2EORri
+ 1730732373U, // t2EORrr
+ 1797841237U, // t2EORrs
+ 538968419U, // t2ISBsy
+ 1811941597U, // t2IT
+ 372U, // t2Int_MemBarrierV7
+ 376U, // t2Int_SyncBarrierV7
+ 1879050464U, // t2Int_eh_sjlj_setjmp
+ 1027809679U, // t2LDM
+ 1027809679U, // t2LDM_RET
+ 135815580U, // t2LDRBT
+ 806904215U, // t2LDRB_POST
+ 806904215U, // t2LDRB_PRE
+ 187228567U, // t2LDRBi12
+ 135815575U, // t2LDRBi8
+ 791208343U, // t2LDRBpci
+ 858317207U, // t2LDRBs
+ 806904226U, // t2LDRDi8
+ 135815586U, // t2LDRDpci
+ 739795367U, // t2LDREX
+ 739795373U, // t2LDREXB
+ 135815604U, // t2LDREXD
+ 739795387U, // t2LDREXH
+ 135815623U, // t2LDRHT
+ 806904258U, // t2LDRH_POST
+ 806904258U, // t2LDRH_PRE
+ 187228610U, // t2LDRHi12
+ 135815618U, // t2LDRHi8
+ 791208386U, // t2LDRHpci
+ 858317250U, // t2LDRHs
+ 135815635U, // t2LDRSBT
+ 806904269U, // t2LDRSB_POST
+ 806904269U, // t2LDRSB_PRE
+ 187228621U, // t2LDRSBi12
+ 135815629U, // t2LDRSBi8
+ 791208397U, // t2LDRSBpci
+ 858317261U, // t2LDRSBs
+ 135815648U, // t2LDRSHT
+ 806904282U, // t2LDRSH_POST
+ 806904282U, // t2LDRSH_PRE
+ 187228634U, // t2LDRSHi12
+ 135815642U, // t2LDRSHi8
+ 791208410U, // t2LDRSHpci
+ 858317274U, // t2LDRSHs
+ 135815655U, // t2LDRT
+ 806904211U, // t2LDR_POST
+ 806904211U, // t2LDR_PRE
+ 187228563U, // t2LDRi12
+ 135815571U, // t2LDRi8
+ 791208339U, // t2LDRpci
+ 67111141U, // t2LDRpci_pic
+ 858317203U, // t2LDRs
+ 791365870U, // t2LEApcrel
+ 187386094U, // t2LEApcrelJT
+ 1730734322U, // t2LSLri
+ 1730734322U, // t2LSLrr
+ 1730734326U, // t2LSRri
+ 1730734326U, // t2LSRrr
+ 806904330U, // t2MLA
+ 806904334U, // t2MLS
+ 858319060U, // t2MOVCCasr
+ 187228690U, // t2MOVCCi
+ 858319090U, // t2MOVCClsl
+ 858319094U, // t2MOVCClsr
+ 187228690U, // t2MOVCCr
+ 858319098U, // t2MOVCCror
+ 135815702U, // t2MOVTi16
+ 1967350290U, // t2MOVi
+ 739795483U, // t2MOVi16
+ 739795483U, // t2MOVi32imm
+ 1967350290U, // t2MOVr
+ 1967212798U, // t2MOVrx
+ 67111170U, // t2MOVsra_flag
+ 67111178U, // t2MOVsrl_flag
+ 337142333U, // t2MRS
+ 337142333U, // t2MRSsys
+ 359686721U, // t2MSR
+ 360211009U, // t2MSRsys
+ 135815749U, // t2MUL
+ 1967211081U, // t2MVNi
+ 791208521U, // t2MVNr
+ 187228745U, // t2MVNs
+ 594543181U, // t2NOP
+ 1679321362U, // t2ORNri
+ 1679321362U, // t2ORNrr
+ 1746430226U, // t2ORNrs
+ 1679319633U, // t2ORRri
+ 1730732625U, // t2ORRrr
+ 1797841489U, // t2ORRrs
+ 806904407U, // t2PKHBT
+ 806904413U, // t2PKHTB
+ 740002070U, // t2PLDWi12
+ 740010262U, // t2PLDWi8
+ 796395798U, // t2PLDWpci
+ 797165846U, // t2PLDWr
+ 193194262U, // t2PLDWs
+ 740002075U, // t2PLDi12
+ 740010267U, // t2PLDi8
+ 796395803U, // t2PLDpci
+ 797165851U, // t2PLDr
+ 193194267U, // t2PLDs
+ 740002079U, // t2PLIi12
+ 740010271U, // t2PLIi8
+ 796395807U, // t2PLIpci
+ 797165855U, // t2PLIr
+ 193194271U, // t2PLIs
+ 135815814U, // t2QADD
+ 135815819U, // t2QADD16
+ 135815826U, // t2QADD8
+ 135815832U, // t2QASX
+ 135815837U, // t2QDADD
+ 135815843U, // t2QDSUB
+ 135815849U, // t2QSAX
+ 135815854U, // t2QSUB
+ 135815859U, // t2QSUB16
+ 135815866U, // t2QSUB8
+ 739795648U, // t2RBIT
+ 791208645U, // t2REV
+ 791208649U, // t2REV16
+ 791208655U, // t2REVSH
+ 337144099U, // t2RFEDB
+ 337144105U, // t2RFEDBW
+ 337144111U, // t2RFEIA
+ 337144111U, // t2RFEIAW
+ 1730734330U, // t2RORri
+ 1730734330U, // t2RORrr
+ 2013266654U, // t2RSBSri
+ 1947755230U, // t2RSBSrs
+ 187228894U, // t2RSBri
+ 806904542U, // t2RSBrs
+ 135815916U, // t2SADD16
+ 135815923U, // t2SADD8
+ 135815929U, // t2SASX
+ 1679319812U, // t2SBCSri
+ 1730732804U, // t2SBCSrr
+ 1797841668U, // t2SBCSrs
+ 1679319812U, // t2SBCri
+ 1730732804U, // t2SBCrr
+ 1797841668U, // t2SBCrs
+ 806904584U, // t2SBFX
+ 135817525U, // t2SDIV
+ 135815949U, // t2SEL
+ 594543397U, // t2SEV
+ 135815977U, // t2SHADD16
+ 135815985U, // t2SHADD8
+ 135815992U, // t2SHASX
+ 135815998U, // t2SHSAX
+ 135816004U, // t2SHSUB16
+ 135816012U, // t2SHSUB8
+ 337142611U, // t2SMC
+ 806904663U, // t2SMLABB
+ 806904670U, // t2SMLABT
+ 806904677U, // t2SMLAD
+ 806904683U, // t2SMLADX
+ 806904690U, // t2SMLAL
+ 806904696U, // t2SMLALBB
+ 806904704U, // t2SMLALBT
+ 806904712U, // t2SMLALD
+ 806904719U, // t2SMLALDX
+ 806904727U, // t2SMLALTB
+ 806904735U, // t2SMLALTT
+ 806904743U, // t2SMLATB
+ 806904750U, // t2SMLATT
+ 806904757U, // t2SMLAWB
+ 806904764U, // t2SMLAWT
+ 806904771U, // t2SMLSD
+ 806904777U, // t2SMLSDX
+ 806904784U, // t2SMLSLD
+ 806904791U, // t2SMLSLDX
+ 806904799U, // t2SMMLA
+ 806904805U, // t2SMMLAR
+ 806904812U, // t2SMMLS
+ 806904818U, // t2SMMLSR
+ 135816185U, // t2SMMUL
+ 135816191U, // t2SMMULR
+ 135816198U, // t2SMUAD
+ 135816204U, // t2SMUADX
+ 135816211U, // t2SMULBB
+ 135816218U, // t2SMULBT
+ 806904865U, // t2SMULL
+ 135816231U, // t2SMULTB
+ 135816238U, // t2SMULTT
+ 135816245U, // t2SMULWB
+ 135816252U, // t2SMULWT
+ 135816259U, // t2SMUSD
+ 135816265U, // t2SMUSDX
+ 365455674U, // t2SRSDB
+ 365979962U, // t2SRSDBW
+ 365455680U, // t2SRSIA
+ 365979968U, // t2SRSIAW
+ 135816276U, // t2SSAT16
+ 806904923U, // t2SSATasr
+ 806904923U, // t2SSATlsl
+ 135816288U, // t2SSAX
+ 135816293U, // t2SSUB16
+ 135816300U, // t2SSUB8
+ 1027810427U, // t2STM
+ 135816328U, // t2STRBT
+ 806880387U, // t2STRB_POST
+ 806880387U, // t2STRB_PRE
+ 187229315U, // t2STRBi12
+ 135816323U, // t2STRBi8
+ 858317955U, // t2STRBs
+ 806904974U, // t2STRDi8
+ 135816339U, // t2STREX
+ 135816345U, // t2STREXB
+ 806904992U, // t2STREXD
+ 135816359U, // t2STREXH
+ 135816371U, // t2STRHT
+ 806880430U, // t2STRH_POST
+ 806880430U, // t2STRH_PRE
+ 187229358U, // t2STRHi12
+ 135816366U, // t2STRHi8
+ 858317998U, // t2STRHs
+ 135816377U, // t2STRT
+ 806880383U, // t2STR_POST
+ 806880383U, // t2STR_PRE
+ 187229311U, // t2STRi12
+ 135816319U, // t2STRi8
+ 858317951U, // t2STRs
+ 187229374U, // t2SUBSri
+ 187229374U, // t2SUBSrr
+ 858318014U, // t2SUBSrs
+ 1730733251U, // t2SUBrSPi
+ 135817542U, // t2SUBrSPi12
+ 67111243U, // t2SUBrSPi12_
+ 67111251U, // t2SUBrSPi_
+ 1746429123U, // t2SUBrSPs
+ 67111260U, // t2SUBrSPs_
+ 1730733251U, // t2SUBri
+ 1679321414U, // t2SUBri12
+ 1730733251U, // t2SUBrr
+ 1797842115U, // t2SUBrs
+ 135816404U, // t2SXTAB16rr
+ 806905044U, // t2SXTAB16rr_rot
+ 135816412U, // t2SXTABrr
+ 806905052U, // t2SXTABrr_rot
+ 135816418U, // t2SXTAHrr
+ 806905058U, // t2SXTAHrr_rot
+ 739796200U, // t2SXTB16r
+ 135816424U, // t2SXTB16r_rot
+ 791209199U, // t2SXTBr
+ 187229423U, // t2SXTBr_rot
+ 791209204U, // t2SXTHr
+ 187229428U, // t2SXTHr_rot
+ 2080377187U, // t2TBB
+ 797165928U, // t2TBBgen
+ 2080377196U, // t2TBH
+ 797182321U, // t2TBHgen
+ 791209209U, // t2TEQri
+ 791209209U, // t2TEQrr
+ 187229433U, // t2TEQrs
+ 1277U, // t2TPsoft
+ 791209237U, // t2TSTri
+ 791209237U, // t2TSTrr
+ 187229461U, // t2TSTrs
+ 135816473U, // t2UADD16
+ 135816480U, // t2UADD8
+ 135816486U, // t2UASX
+ 806905131U, // t2UBFX
+ 135817589U, // t2UDIV
+ 135816496U, // t2UHADD16
+ 135816504U, // t2UHADD8
+ 135816511U, // t2UHASX
+ 135816517U, // t2UHSAX
+ 135816523U, // t2UHSUB16
+ 135816531U, // t2UHSUB8
+ 806905178U, // t2UMAAL
+ 806905184U, // t2UMLAL
+ 806905190U, // t2UMULL
+ 135816556U, // t2UQADD16
+ 135816564U, // t2UQADD8
+ 135816571U, // t2UQASX
+ 135816577U, // t2UQSAX
+ 135816583U, // t2UQSUB16
+ 135816591U, // t2UQSUB8
+ 135816598U, // t2USAD8
+ 806905244U, // t2USADA8
+ 135816611U, // t2USAT16
+ 806905258U, // t2USATasr
+ 806905258U, // t2USATlsl
+ 135816623U, // t2USAX
+ 135816628U, // t2USUB16
+ 135816635U, // t2USUB8
+ 135816641U, // t2UXTAB16rr
+ 806905281U, // t2UXTAB16rr_rot
+ 135816649U, // t2UXTABrr
+ 806905289U, // t2UXTABrr_rot
+ 135816655U, // t2UXTAHrr
+ 806905295U, // t2UXTAHrr_rot
+ 739796437U, // t2UXTB16r
+ 135816661U, // t2UXTB16r_rot
+ 791209436U, // t2UXTBr
+ 187229660U, // t2UXTBr_rot
+ 791209441U, // t2UXTHr
+ 187229665U, // t2UXTHr_rot
+ 594544833U, // t2WFE
+ 594544837U, // t2WFI
+ 594544841U, // t2YIELD
+ 2206998545U, // tADC
135815194U, // tADDhirr
- 2206220314U, // tADDi3
- 2206474266U, // tADDi8
- 126355813U, // tADDrPCi
- 67127653U, // tADDrSP
- 67111269U, // tADDrSPi
- 2206220314U, // tADDrr
- 67389797U, // tADDspi
- 67127653U, // tADDspr
- 67127658U, // tADDspr_
- 69208433U, // tADJCALLSTACKDOWN
- 69208454U, // tADJCALLSTACKUP
- 2206474308U, // tAND
- 67127705U, // tANDsp
- 2206222527U, // tASRri
- 2206476479U, // tASRrr
+ 2206744602U, // tADDi3
+ 2206998554U, // tADDi8
+ 126880122U, // tADDrPCi
+ 67127674U, // tADDrSP
+ 67111290U, // tADDrSPi
+ 2206744602U, // tADDrr
+ 67389818U, // tADDspi
+ 67127674U, // tADDspr
+ 67127679U, // tADDspr_
+ 69208454U, // tADJCALLSTACKDOWN
+ 69208475U, // tADJCALLSTACKUP
+ 2206998596U, // tAND
+ 67127726U, // tANDsp
+ 2206746836U, // tASRri
+ 2207000788U, // tASRrr
69206089U, // tB
- 2206474324U, // tBIC
- 69208480U, // tBKPT
+ 2206998612U, // tBIC
+ 69208501U, // tBKPT
402653277U, // tBL
402653281U, // tBLXi
402653281U, // tBLXi_r9
69206113U, // tBLXr
69206113U, // tBLXr_r9
402653277U, // tBLr9
- 69206143U, // tBRIND
- 126877823U, // tBR_JTr
- 69206152U, // tBX
- 2470U, // tBX_RET
- 69206121U, // tBX_RET_vararg
- 69206152U, // tBXr9
- 337141919U, // tBcc
- 127402077U, // tBfar
- 67111340U, // tCBNZ
- 67111346U, // tCBZ
- 739795126U, // tCMNz
- 739795130U, // tCMPhir
- 739795130U, // tCMPi8
- 739795130U, // tCMPr
- 739795130U, // tCMPzhir
- 739795130U, // tCMPzi8
- 739795130U, // tCMPzr
- 939524286U, // tCPS
- 2206474560U, // tEOR
- 1879050443U, // tInt_eh_sjlj_setjmp
- 1027686778U, // tLDM
- 806904190U, // tLDR
- 806904194U, // tLDRB
- 806904194U, // tLDRBi
- 806904237U, // tLDRH
- 806904237U, // tLDRHi
- 135815608U, // tLDRSB
- 135815621U, // tLDRSH
- 739795326U, // tLDRcp
- 806904190U, // tLDRi
- 799015294U, // tLDRpci
- 67111351U, // tLDRpci_pic
- 135815550U, // tLDRspi
- 739797209U, // tLEApcrel
- 135817433U, // tLEApcrelJT
- 2206222557U, // tLSLri
- 2206476509U, // tLSLrr
- 2206222561U, // tLSRri
- 2206476513U, // tLSRrr
- 135815677U, // tMOVCCi
- 135815677U, // tMOVCCr
- 136317376U, // tMOVCCr_pseudo
- 67111371U, // tMOVSr
- 67111377U, // tMOVgpr2gpr
- 67111377U, // tMOVgpr2tgpr
- 2208948733U, // tMOVi8
- 67111377U, // tMOVr
- 67111377U, // tMOVtgpr2gpr
- 2206474800U, // tMUL
- 2208948788U, // tMVN
- 538968632U, // tNOP
- 2206474812U, // tORR
- 1202717248U, // tPICADD
- 538733014U, // tPOP
- 538733014U, // tPOP_RET
- 538733018U, // tPUSH
- 739795632U, // tREV
- 739795636U, // tREV16
- 739795642U, // tREVSH
- 2206476517U, // tROR
- 2208940745U, // tRSB
- 135815550U, // tRestore
- 2206474991U, // tSBC
- 764U, // tSETENDBE
- 774U, // tSETENDLE
- 538968848U, // tSEV
- 1027687526U, // tSTM
- 806904938U, // tSTR
- 806904942U, // tSTRB
- 806904942U, // tSTRBi
- 806904985U, // tSTRH
- 806904985U, // tSTRHi
- 806904938U, // tSTRi
- 135816298U, // tSTRspi
- 2206221486U, // tSUBi3
- 2206475438U, // tSUBi8
- 2206221486U, // tSUBrr
- 67389919U, // tSUBspi
- 67389767U, // tSUBspi_
- 337142962U, // tSVC
- 739796186U, // tSXTB
- 739796191U, // tSXTH
- 135816298U, // tSpill
- 1256U, // tTPsoft
- 1275U, // tTRAP
- 739796224U, // tTST
- 739796423U, // tUXTB
- 739796428U, // tUXTH
- 538970284U, // tWFE
- 538970288U, // tWFI
- 538970292U, // tYIELD
+ 69206164U, // tBRIND
+ 127402132U, // tBR_JTr
+ 69206173U, // tBX
+ 2491U, // tBX_RET
+ 69206142U, // tBX_RET_vararg
+ 69206173U, // tBXr9
+ 337141940U, // tBcc
+ 127926365U, // tBfar
+ 67111361U, // tCBNZ
+ 67111367U, // tCBZ
+ 739795147U, // tCMNz
+ 739795151U, // tCMPhir
+ 739795151U, // tCMPi8
+ 739795151U, // tCMPr
+ 739795151U, // tCMPzhir
+ 739795151U, // tCMPzi8
+ 739795151U, // tCMPzr
+ 939524307U, // tCPS
+ 2206998869U, // tEOR
+ 1879050464U, // tInt_eh_sjlj_setjmp
+ 1027686799U, // tLDM
+ 806904211U, // tLDR
+ 806904215U, // tLDRB
+ 806904215U, // tLDRBi
+ 806904258U, // tLDRH
+ 806904258U, // tLDRHi
+ 135815629U, // tLDRSB
+ 135815642U, // tLDRSH
+ 739795347U, // tLDRcp
+ 806904211U, // tLDRi
+ 799539603U, // tLDRpci
+ 67111372U, // tLDRpci_pic
+ 135815571U, // tLDRspi
+ 739797230U, // tLEApcrel
+ 135817454U, // tLEApcrelJT
+ 2206746866U, // tLSLri
+ 2207000818U, // tLSLrr
+ 2206746870U, // tLSRri
+ 2207000822U, // tLSRrr
+ 135815698U, // tMOVCCi
+ 135815698U, // tMOVCCr
+ 136317397U, // tMOVCCr_pseudo
+ 67111392U, // tMOVSr
+ 67111398U, // tMOVgpr2gpr
+ 67111398U, // tMOVgpr2tgpr
+ 2209473042U, // tMOVi8
+ 67111398U, // tMOVr
+ 67111398U, // tMOVtgpr2gpr
+ 2206999109U, // tMUL
+ 2209473097U, // tMVN
+ 538968653U, // tNOP
+ 2206999121U, // tORR
+ 1203241557U, // tPICADD
+ 538733035U, // tPOP
+ 538733035U, // tPOP_RET
+ 538733039U, // tPUSH
+ 739795653U, // tREV
+ 739795657U, // tREV16
+ 739795663U, // tREVSH
+ 2207000826U, // tROR
+ 2209465054U, // tRSB
+ 135815571U, // tRestore
+ 2206999300U, // tSBC
+ 785U, // tSETENDBE
+ 795U, // tSETENDLE
+ 538968869U, // tSEV
+ 1027687547U, // tSTM
+ 806904959U, // tSTR
+ 806904963U, // tSTRB
+ 806904963U, // tSTRBi
+ 806905006U, // tSTRH
+ 806905006U, // tSTRHi
+ 806904959U, // tSTRi
+ 135816319U, // tSTRspi
+ 2206745795U, // tSUBi3
+ 2206999747U, // tSUBi8
+ 2206745795U, // tSUBrr
+ 67389940U, // tSUBspi
+ 67389788U, // tSUBspi_
+ 337142983U, // tSVC
+ 739796207U, // tSXTB
+ 739796212U, // tSXTH
+ 135816319U, // tSpill
+ 1277U, // tTPsoft
+ 1296U, // tTRAP
+ 739796245U, // tTST
+ 739796444U, // tUXTB
+ 739796449U, // tUXTH
+ 538970305U, // tWFE
+ 538970309U, // tWFI
+ 538970313U, // tYIELD
0U
};
const char *AsmStrs =
"DBG_VALUE\000adcs\t\000adc\000adds\000add\000@ ADJCALLSTACKDOWN \000@ A"
"DJCALLSTACKUP \000and\000\000b\t\000bfc\000bfi\000bic\000bkpt\000bl\t\000"
- "blx\t\000bl\000bx\t\000add\tpc, \000ldr\tpc, \000mov\tpc, \000mov\tlr, "
- "pc\n\tbx\t\000bxj\000bx\000b\000cdp\000cdp2\tp\000clrex\000clz\000cmn\000"
- "cmp\000cps\000dbg\000dmb\tish\000dmb\tishst\000dmb\tnsh\000dmb\tnshst\000"
- "dmb\tosh\000dmb\toshst\000dmb\tst\000dsb\tish\000dsb\tishst\000dsb\tnsh"
- "\000dsb\tnshst\000dsb\tosh\000dsb\toshst\000dsb\tst\000eor\000vmov\000v"
- "mrs\000isb\000mcr\tp15, 0, \000dmb\000dsb\000str\tsp, [\000ldc2\000ldc\000"
- "ldm\000ldr\000ldrb\000ldrbt\000ldrd\000ldrex\000ldrexb\000ldrexd\000ldr"
- "exh\000ldrh\000ldrht\000ldrsb\000ldrsbt\000ldrsh\000ldrsht\000ldrt\000."
- "set \000mcr\000mcr2\tp\000mcrr\000mcrr2\tp\000mla\000mls\000mov\000movt"
- "\000movw\000movs\000mrc\000mrc2\tp\000mrrc\000mrrc2\tp\000mrs\000msr\000"
- "mul\000mvn\000nop\000orr\000\n\000pkhbt\000pkhtb\000pldw\t[\000pldw\t\000"
- "pld\t[\000pld\t\000pli\t[\000pli\t\000qadd\000qadd16\000qadd8\000qasx\000"
- "qdadd\000qdsub\000qsax\000qsub\000qsub16\000qsub8\000rbit\000rev\000rev"
- "16\000revsh\000rfe\000rsbs\000rsb\000rscs\t\000rsc\000sadd16\000sadd8\000"
- "sasx\000sbcs\t\000sbc\000sbfx\000sel\000setend\tbe\000setend\tle\000sev"
- "\000shadd16\000shadd8\000shasx\000shsax\000shsub16\000shsub8\000smc\000"
- "smlabb\000smlabt\000smlad\000smladx\000smlal\000smlalbb\000smlalbt\000s"
- "mlald\000smlaldx\000smlaltb\000smlaltt\000smlatb\000smlatt\000smlawb\000"
- "smlawt\000smlsd\000smlsdx\000smlsld\000smlsldx\000smmla\000smmlar\000sm"
- "mls\000smmlsr\000smmul\000smmulr\000smuad\000smuadx\000smulbb\000smulbt"
- "\000smull\000smultb\000smultt\000smulwb\000smulwt\000smusd\000smusdx\000"
- "srs\000ssat16\000ssat\000ssax\000ssub16\000ssub8\000stc2\000stc\000stm\000"
- "str\000strb\000strbt\000strd\000strex\000strexb\000strexd\000strexh\000"
- "strh\000strht\000strt\000subs\000sub\000svc\000swp\000swpb\000sxtab16\000"
- "sxtab\000sxtah\000sxtb16\000sxtb\000sxth\000teq\000bl\t__aeabi_read_tp\000"
- "trap\000tst\000uadd16\000uadd8\000uasx\000ubfx\000uhadd16\000uhadd8\000"
- "uhasx\000uhsax\000uhsub16\000uhsub8\000umaal\000umlal\000umull\000uqadd"
- "16\000uqadd8\000uqasx\000uqsax\000uqsub16\000uqsub8\000usad8\000usada8\000"
- "usat16\000usat\000usax\000usub16\000usub8\000uxtab16\000uxtab\000uxtah\000"
- "uxtb16\000uxtb\000uxth\000vabal\000vaba\000vabdl\000vabd\000vabs\000vac"
- "ge\000vacgt\000vadd\000vaddhn\000vaddl\000vaddw\000vand\000vbic\000vbif"
- "\000vbit\000vbsl\000vceq\000vcge\000vcgt\000vcle\000vcls\000vclt\000vcl"
- "z\000vcmp\000vcmpe\000vcnt\000vcvtb\000vcvt\000vcvtt\000vdiv\000vdup\000"
- "veor\000vext\000vhadd\000vhsub\000vld1\000vld2\000vld3\000vld4\000vldm\000"
- "vldr\000vldmia\000vmax\000vmin\000vmla\000vmlal\000vmls\000vmlsl\000vmo"
- "vl\000vmovn\000vmsr\000vmul\000vmull\000vmvn\000vneg\000vnmla\000vnmls\000"
- "vnmul\000vorn\000vorr\000vpadal\000vpaddl\000vpadd\000vpmax\000vpmin\000"
- "vqabs\000vqadd\000vqdmlal\000vqdmlsl\000vqdmulh\000vqdmull\000vqmovun\000"
- "vqmovn\000vqneg\000vqrdmulh\000vqrshl\000vqrshrn\000vqrshrun\000vqshl\000"
- "vqshlu\000vqshrn\000vqshrun\000vqsub\000vraddhn\000vrecpe\000vrecps\000"
- "vrev16\000vrev32\000vrev64\000vrhadd\000vrshl\000vrshrn\000vrshr\000vrs"
- "qrte\000vrsqrts\000vrsra\000vrsubhn\000vshll\000vshl\000vshrn\000vshr\000"
- "vsli\000vsqrt\000vsra\000vsri\000vst1\000vst2\000vst3\000vst4\000vstm\000"
- "vstr\000vstmia\000vsub\000vsubhn\000vsubl\000vsubw\000vswp\000vtbl\000v"
- "tbx\000vcvtr\000vtrn\000vtst\000vuzp\000vzip\000wfe\000wfi\000yield\000"
- "addw\000asr\000b.w\t\000it\000str\t\000@ ldr.w\t\000adr\000lsl\000lsr\000"
- "ror\000rrx\000asrs.w\t\000lsrs.w\t\000orn\000pldw\000pld\000pli\000rfea"
- "b\000rfedb\000rfeia\000sdiv\000srsdb\000srsia\000subw\000@ subw\t\000@ "
- "sub.w\t\000@ sub\t\000tbb\t\000tbb\000tbh\t\000tbh\000udiv\000add\t\000"
- "@ add\t\000@ tADJCALLSTACKDOWN \000@ tADJCALLSTACKUP \000@ and\t\000bkp"
- "t\t\000bx\tlr\000cbnz\t\000cbz\t\000@ ldr.n\t\000@ tMOVCCr \000movs\t\000"
- "mov\t\000pop\000push\000sub\t\000";
+ "blx\t\000bl\000mov\tlr, pc\n\tmov\tpc, \000bx\t\000add\tpc, \000ldr\tpc"
+ ", \000mov\tpc, \000mov\tlr, pc\n\tbx\t\000bxj\000bx\000b\000cdp\000cdp2"
+ "\tp\000clrex\000clz\000cmn\000cmp\000cps\000dbg\000dmb\tish\000dmb\tish"
+ "st\000dmb\tnsh\000dmb\tnshst\000dmb\tosh\000dmb\toshst\000dmb\tst\000ds"
+ "b\tish\000dsb\tishst\000dsb\tnsh\000dsb\tnshst\000dsb\tosh\000dsb\toshs"
+ "t\000dsb\tst\000eor\000vmov\000vmrs\000isb\000mcr\tp15, 0, \000dmb\000d"
+ "sb\000str\tsp, [\000ldc2\000ldc\000ldm\000ldr\000ldrb\000ldrbt\000ldrd\000"
+ "ldrex\000ldrexb\000ldrexd\000ldrexh\000ldrh\000ldrht\000ldrsb\000ldrsbt"
+ "\000ldrsh\000ldrsht\000ldrt\000.set \000mcr\000mcr2\tp\000mcrr\000mcrr2"
+ "\tp\000mla\000mls\000mov\000movt\000movw\000movs\000mrc\000mrc2\tp\000m"
+ "rrc\000mrrc2\tp\000mrs\000msr\000mul\000mvn\000nop\000orr\000\n\000pkhb"
+ "t\000pkhtb\000pldw\t[\000pldw\t\000pld\t[\000pld\t\000pli\t[\000pli\t\000"
+ "qadd\000qadd16\000qadd8\000qasx\000qdadd\000qdsub\000qsax\000qsub\000qs"
+ "ub16\000qsub8\000rbit\000rev\000rev16\000revsh\000rfe\000rsbs\000rsb\000"
+ "rscs\t\000rsc\000sadd16\000sadd8\000sasx\000sbcs\t\000sbc\000sbfx\000se"
+ "l\000setend\tbe\000setend\tle\000sev\000shadd16\000shadd8\000shasx\000s"
+ "hsax\000shsub16\000shsub8\000smc\000smlabb\000smlabt\000smlad\000smladx"
+ "\000smlal\000smlalbb\000smlalbt\000smlald\000smlaldx\000smlaltb\000smla"
+ "ltt\000smlatb\000smlatt\000smlawb\000smlawt\000smlsd\000smlsdx\000smlsl"
+ "d\000smlsldx\000smmla\000smmlar\000smmls\000smmlsr\000smmul\000smmulr\000"
+ "smuad\000smuadx\000smulbb\000smulbt\000smull\000smultb\000smultt\000smu"
+ "lwb\000smulwt\000smusd\000smusdx\000srs\000ssat16\000ssat\000ssax\000ss"
+ "ub16\000ssub8\000stc2\000stc\000stm\000str\000strb\000strbt\000strd\000"
+ "strex\000strexb\000strexd\000strexh\000strh\000strht\000strt\000subs\000"
+ "sub\000svc\000swp\000swpb\000sxtab16\000sxtab\000sxtah\000sxtb16\000sxt"
+ "b\000sxth\000teq\000bl\t__aeabi_read_tp\000trap\000tst\000uadd16\000uad"
+ "d8\000uasx\000ubfx\000uhadd16\000uhadd8\000uhasx\000uhsax\000uhsub16\000"
+ "uhsub8\000umaal\000umlal\000umull\000uqadd16\000uqadd8\000uqasx\000uqsa"
+ "x\000uqsub16\000uqsub8\000usad8\000usada8\000usat16\000usat\000usax\000"
+ "usub16\000usub8\000uxtab16\000uxtab\000uxtah\000uxtb16\000uxtb\000uxth\000"
+ "vabal\000vaba\000vabdl\000vabd\000vabs\000vacge\000vacgt\000vadd\000vad"
+ "dhn\000vaddl\000vaddw\000vand\000vbic\000vbif\000vbit\000vbsl\000vceq\000"
+ "vcge\000vcgt\000vcle\000vcls\000vclt\000vclz\000vcmp\000vcmpe\000vcnt\000"
+ "vcvtb\000vcvt\000vcvtt\000vdiv\000vdup\000veor\000vext\000vhadd\000vhsu"
+ "b\000vld1\000vld2\000vld3\000vld4\000vldm\000vldr\000vldmia\000vmax\000"
+ "vmin\000vmla\000vmlal\000vmls\000vmlsl\000vmovl\000vmovn\000vmsr\000vmu"
+ "l\000vmull\000vmvn\000vneg\000vnmla\000vnmls\000vnmul\000vorn\000vorr\000"
+ "vpadal\000vpaddl\000vpadd\000vpmax\000vpmin\000vqabs\000vqadd\000vqdmla"
+ "l\000vqdmlsl\000vqdmulh\000vqdmull\000vqmovun\000vqmovn\000vqneg\000vqr"
+ "dmulh\000vqrshl\000vqrshrn\000vqrshrun\000vqshl\000vqshlu\000vqshrn\000"
+ "vqshrun\000vqsub\000vraddhn\000vrecpe\000vrecps\000vrev16\000vrev32\000"
+ "vrev64\000vrhadd\000vrshl\000vrshrn\000vrshr\000vrsqrte\000vrsqrts\000v"
+ "rsra\000vrsubhn\000vshll\000vshl\000vshrn\000vshr\000vsli\000vsqrt\000v"
+ "sra\000vsri\000vst1\000vst2\000vst3\000vst4\000vstm\000vstr\000vstmia\000"
+ "vsub\000vsubhn\000vsubl\000vsubw\000vswp\000vtbl\000vtbx\000vcvtr\000vt"
+ "rn\000vtst\000vuzp\000vzip\000wfe\000wfi\000yield\000addw\000asr\000b.w"
+ "\t\000it\000str\t\000@ ldr.w\t\000adr\000lsl\000lsr\000ror\000rrx\000as"
+ "rs.w\t\000lsrs.w\t\000orn\000pldw\000pld\000pli\000rfeab\000rfedb\000rf"
+ "eia\000sdiv\000srsdb\000srsia\000subw\000@ subw\t\000@ sub.w\t\000@ sub"
+ "\t\000tbb\t\000tbb\000tbh\t\000tbh\000udiv\000add\t\000@ add\t\000@ tAD"
+ "JCALLSTACKDOWN \000@ tADJCALLSTACKUP \000@ and\t\000bkpt\t\000bx\tlr\000"
+ "cbnz\t\000cbz\t\000@ ldr.n\t\000@ tMOVCCr \000movs\t\000mov\t\000pop\000"
+ "push\000sub\t\000";
O << "\t";
@@ -2059,7 +2064,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printAddrMode2Operand(MI, 0);
break;
case 8:
- // BX_RET, FMSTAT, NOP, SEV, TRAP, WFE, WFI, YIELD, t2CLREX, t2DMBish, t2...
+ // BX_RET, FMSTAT, MOVPCLR, NOP, SEV, TRAP, WFE, WFI, YIELD, t2CLREX, t2D...
printPredicateOperand(MI, 0);
break;
case 9:
@@ -2204,7 +2209,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
}
- // Fragment 1 encoded into 7 bits for 119 unique commands.
+ // Fragment 1 encoded into 7 bits for 120 unique commands.
switch ((Bits >> 19) & 127) {
default: // unreachable.
case 0:
@@ -2236,7 +2241,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
O << "\t";
break;
case 4:
- // ADJCALLSTACKDOWN, ADJCALLSTACKUP, B, BLX, BLXr9, BRIND, BX, BXr9, NOP,...
+ // ADJCALLSTACKDOWN, ADJCALLSTACKUP, B, BLX, BLXr9, BMOVPCRX, BMOVPCRXr9,...
return;
break;
case 5:
@@ -2482,21 +2487,26 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
O << ", ";
break;
case 44:
+ // MOVPCLR
+ O << "\tpc, lr";
+ return;
+ break;
+ case 45:
// MOVi, MOVr, MOVrx, MVNi, MVNr
printSBitModifierOperand(MI, 4);
O << "\t";
printOperand(MI, 0);
O << ", ";
break;
- case 45:
+ case 46:
// MSR, MSRi, t2MSR
O << "\tcpsr, ";
break;
- case 46:
+ case 47:
// MSRsys, MSRsysi, t2MSRsys
O << "\tspsr, ";
break;
- case 47:
+ case 48:
// PICADD
O << ":\n\tadd";
printPredicateOperand(MI, 3);
@@ -2506,7 +2516,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 1);
return;
break;
- case 48:
+ case 49:
// PICLDR
O << ":\n\tldr";
printPredicateOperand(MI, 3);
@@ -2516,7 +2526,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printAddrModePCOperand(MI, 1);
return;
break;
- case 49:
+ case 50:
// PICLDRB
O << ":\n\tldrb";
printPredicateOperand(MI, 3);
@@ -2526,7 +2536,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printAddrModePCOperand(MI, 1);
return;
break;
- case 50:
+ case 51:
// PICLDRH
O << ":\n\tldrh";
printPredicateOperand(MI, 3);
@@ -2536,7 +2546,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printAddrModePCOperand(MI, 1);
return;
break;
- case 51:
+ case 52:
// PICLDRSB
O << ":\n\tldrsb";
printPredicateOperand(MI, 3);
@@ -2546,7 +2556,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printAddrModePCOperand(MI, 1);
return;
break;
- case 52:
+ case 53:
// PICLDRSH
O << ":\n\tldrsh";
printPredicateOperand(MI, 3);
@@ -2556,7 +2566,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printAddrModePCOperand(MI, 1);
return;
break;
- case 53:
+ case 54:
// PICSTR
O << ":\n\tstr";
printPredicateOperand(MI, 3);
@@ -2566,7 +2576,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printAddrModePCOperand(MI, 1);
return;
break;
- case 54:
+ case 55:
// PICSTRB
O << ":\n\tstrb";
printPredicateOperand(MI, 3);
@@ -2576,7 +2586,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printAddrModePCOperand(MI, 1);
return;
break;
- case 55:
+ case 56:
// PICSTRH
O << ":\n\tstrh";
printPredicateOperand(MI, 3);
@@ -2586,79 +2596,79 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printAddrModePCOperand(MI, 1);
return;
break;
- case 56:
+ case 57:
// SRS, t2SRSDB, t2SRSIA
O << "\tsp, ";
break;
- case 57:
+ case 58:
// SRSW, t2SRSDBW, t2SRSIAW
O << "\tsp!, ";
break;
- case 58:
+ case 59:
// VABALsv2i64, VABAsv2i32, VABAsv4i32, VABDLsv2i64, VABDsv2i32, VABDsv4i...
O << ".s32\t";
printOperand(MI, 0);
O << ", ";
break;
- case 59:
+ case 60:
// VABALsv4i32, VABAsv4i16, VABAsv8i16, VABDLsv4i32, VABDsv4i16, VABDsv8i...
O << ".s16\t";
printOperand(MI, 0);
O << ", ";
break;
- case 60:
+ case 61:
// VABALsv8i16, VABAsv16i8, VABAsv8i8, VABDLsv8i16, VABDsv16i8, VABDsv8i8...
O << ".s8\t";
printOperand(MI, 0);
O << ", ";
break;
- case 61:
+ case 62:
// VABALuv2i64, VABAuv2i32, VABAuv4i32, VABDLuv2i64, VABDuv2i32, VABDuv4i...
O << ".u32\t";
printOperand(MI, 0);
O << ", ";
break;
- case 62:
+ case 63:
// VABALuv4i32, VABAuv4i16, VABAuv8i16, VABDLuv4i32, VABDuv4i16, VABDuv8i...
O << ".u16\t";
printOperand(MI, 0);
O << ", ";
break;
- case 63:
+ case 64:
// VABALuv8i16, VABAuv16i8, VABAuv8i8, VABDLuv8i16, VABDuv16i8, VABDuv8i8...
O << ".u8\t";
printOperand(MI, 0);
O << ", ";
break;
- case 64:
+ case 65:
// VADDHNv2i32, VADDv1i64, VADDv2i64, VMOVNv2i32, VMOVv1i64, VMOVv2i64, V...
O << ".i64\t";
printOperand(MI, 0);
O << ", ";
break;
- case 65:
+ case 66:
// VADDHNv4i16, VADDv2i32, VADDv4i32, VCEQv2i32, VCEQv4i32, VCEQzv2i32, V...
O << ".i32\t";
printOperand(MI, 0);
O << ", ";
break;
- case 66:
+ case 67:
// VADDHNv8i8, VADDv4i16, VADDv8i16, VCEQv4i16, VCEQv8i16, VCEQzv4i16, VC...
O << ".i16\t";
printOperand(MI, 0);
O << ", ";
break;
- case 67:
+ case 68:
// VADDv16i8, VADDv8i8, VCEQv16i8, VCEQv8i8, VCEQzv16i8, VCEQzv8i8, VCLZv...
O << ".i8\t";
printOperand(MI, 0);
O << ", ";
break;
- case 68:
+ case 69:
// VCNTd, VCNTq, VDUP8d, VDUP8q, VDUPLN8d, VDUPLN8q, VEXTd8, VEXTq8, VLD1...
O << ".8\t";
break;
- case 69:
+ case 70:
// VCVTBHS, VCVTTHS
O << ".f16.f32\t";
printOperand(MI, 0);
@@ -2666,7 +2676,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 1);
return;
break;
- case 70:
+ case 71:
// VCVTBSH, VCVTTSH
O << ".f32.f16\t";
printOperand(MI, 0);
@@ -2674,7 +2684,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 1);
return;
break;
- case 71:
+ case 72:
// VCVTDS
O << ".f64.f32\t";
printOperand(MI, 0);
@@ -2682,7 +2692,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 1);
return;
break;
- case 72:
+ case 73:
// VCVTSD
O << ".f32.f64\t";
printOperand(MI, 0);
@@ -2690,69 +2700,69 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 1);
return;
break;
- case 73:
+ case 74:
// VCVTf2sd, VCVTf2sd_sfp, VCVTf2sq, VCVTf2xsd, VCVTf2xsq, VTOSIRS, VTOSI...
O << ".s32.f32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
- case 74:
+ case 75:
// VCVTf2ud, VCVTf2ud_sfp, VCVTf2uq, VCVTf2xud, VCVTf2xuq, VTOUIRS, VTOUI...
O << ".u32.f32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
- case 75:
+ case 76:
// VCVTs2fd, VCVTs2fd_sfp, VCVTs2fq, VCVTxs2fd, VCVTxs2fq, VSITOS, VSLTOS
O << ".f32.s32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
- case 76:
+ case 77:
// VCVTu2fd, VCVTu2fd_sfp, VCVTu2fq, VCVTxu2fd, VCVTxu2fq, VUITOS, VULTOS
O << ".f32.u32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
- case 77:
+ case 78:
// VDUP16d, VDUP16q, VDUPLN16d, VDUPLN16q, VEXTd16, VEXTq16, VLD1q16, VRE...
O << ".16\t";
break;
- case 78:
+ case 79:
// VDUP32d, VDUP32q, VDUPLN32d, VDUPLN32q, VDUPLNfd, VDUPLNfq, VDUPfd, VD...
O << ".32\t";
break;
- case 79:
+ case 80:
// VLD1d16, VLD1d16Q, VLD1d16T, VLD2LNd16, VLD2LNq16a, VLD2LNq16b, VLD2d1...
O << ".16\t{";
break;
- case 80:
+ case 81:
// VLD1d32, VLD1d32Q, VLD1d32T, VLD1df, VLD2LNd32, VLD2LNq32a, VLD2LNq32b...
O << ".32\t{";
break;
- case 81:
+ case 82:
// VLD1d64, VLD2d64, VLD3d64, VLD4d64, VST1d64, VST2d64, VST3d64, VST4d64
O << ".64\t{";
break;
- case 82:
+ case 83:
// VLD1d8, VLD1d8Q, VLD1d8T, VLD2LNd8, VLD2d8, VLD2d8D, VLD2q8, VLD3LNd8,...
O << ".8\t{";
break;
- case 83:
+ case 84:
// VLD1q64, VLDRD, VSLIv1i64, VSLIv2i64, VSRIv1i64, VSRIv2i64, VST1q64, V...
O << ".64\t";
break;
- case 84:
+ case 85:
// VMSR
O << "\tfpscr, ";
printOperand(MI, 0);
return;
break;
- case 85:
+ case 86:
// VMULLp, VMULpd, VMULpq
O << ".p8\t";
printOperand(MI, 0);
@@ -2762,19 +2772,19 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 2);
return;
break;
- case 86:
+ case 87:
// VQADDsv1i64, VQADDsv2i64, VQMOVNsuv2i32, VQMOVNsv2i32, VQRSHLsv1i64, V...
O << ".s64\t";
printOperand(MI, 0);
O << ", ";
break;
- case 87:
+ case 88:
// VQADDuv1i64, VQADDuv2i64, VQMOVNuv2i32, VQRSHLuv1i64, VQRSHLuv2i64, VQ...
O << ".u64\t";
printOperand(MI, 0);
O << ", ";
break;
- case 88:
+ case 89:
// VSHTOD
O << ".f64.s16\t";
printOperand(MI, 0);
@@ -2784,7 +2794,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 2);
return;
break;
- case 89:
+ case 90:
// VSHTOS
O << ".f32.s16\t";
printOperand(MI, 0);
@@ -2794,14 +2804,14 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 2);
return;
break;
- case 90:
+ case 91:
// VSITOD, VSLTOD
O << ".f64.s32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
- case 91:
+ case 92:
// VTOSHD
O << ".s16.f64\t";
printOperand(MI, 0);
@@ -2811,7 +2821,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 2);
return;
break;
- case 92:
+ case 93:
// VTOSHS
O << ".s16.f32\t";
printOperand(MI, 0);
@@ -2821,14 +2831,14 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 2);
return;
break;
- case 93:
+ case 94:
// VTOSIRD, VTOSIZD, VTOSLD
O << ".s32.f64\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
- case 94:
+ case 95:
// VTOUHD
O << ".u16.f64\t";
printOperand(MI, 0);
@@ -2838,7 +2848,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 2);
return;
break;
- case 95:
+ case 96:
// VTOUHS
O << ".u16.f32\t";
printOperand(MI, 0);
@@ -2848,14 +2858,14 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 2);
return;
break;
- case 96:
+ case 97:
// VTOUIRD, VTOUIZD, VTOULD
O << ".u32.f64\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
- case 97:
+ case 98:
// VUHTOD
O << ".f64.u16\t";
printOperand(MI, 0);
@@ -2865,7 +2875,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 2);
return;
break;
- case 98:
+ case 99:
// VUHTOS
O << ".f32.u16\t";
printOperand(MI, 0);
@@ -2875,103 +2885,103 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 2);
return;
break;
- case 99:
+ case 100:
// VUITOD, VULTOD
O << ".f64.u32\t";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
- case 100:
+ case 101:
// t2ADCSrr, t2ADCSrs, t2ADCrr, t2ADCrs, t2ADDSri, t2ADDSrr, t2ADDSrs, t2...
O << ".w\t";
printOperand(MI, 0);
break;
- case 101:
+ case 102:
// t2BR_JT
O << "\n";
printJT2BlockOperand(MI, 2);
return;
break;
- case 102:
+ case 103:
// t2DMBish, t2DSBish
O << "\tish";
return;
break;
- case 103:
+ case 104:
// t2DMBishst, t2DSBishst
O << "\tishst";
return;
break;
- case 104:
+ case 105:
// t2DMBnsh, t2DSBnsh
O << "\tnsh";
return;
break;
- case 105:
+ case 106:
// t2DMBnshst, t2DSBnshst
O << "\tnshst";
return;
break;
- case 106:
+ case 107:
// t2DMBosh, t2DSBosh
O << "\tosh";
return;
break;
- case 107:
+ case 108:
// t2DMBoshst, t2DSBoshst
O << "\toshst";
return;
break;
- case 108:
+ case 109:
// t2DMBst, t2DSBst
O << "\tst";
return;
break;
- case 109:
+ case 110:
// t2NOP, t2SEV, t2WFE, t2WFI, t2YIELD
O << ".w";
return;
break;
- case 110:
+ case 111:
// t2PLDWpci, t2PLDpci, t2PLIpci
O << "\t[pc, ";
printOperand(MI, 1, "negzero");
O << ']';
return;
break;
- case 111:
+ case 112:
// t2PLDWr, t2PLDWs, t2PLDr, t2PLDs, t2PLIr, t2PLIs, t2TBBgen, t2TBHgen
O << "\t[";
printOperand(MI, 0);
O << ", ";
printOperand(MI, 1);
break;
- case 112:
+ case 113:
// tADC, tADDi3, tADDi8, tADDrr, tAND, tASRri, tASRrr, tBIC, tEOR, tLSLri...
printPredicateOperand(MI, 4);
O << "\t";
printOperand(MI, 0);
O << ", ";
break;
- case 113:
+ case 114:
// tADDrPCi
O << ", pc, ";
printThumbS4ImmOperand(MI, 1);
return;
break;
- case 114:
+ case 115:
// tBR_JTr
O << "\n\t.align\t2\n";
printJTBlockOperand(MI, 1);
return;
break;
- case 115:
+ case 116:
// tBfar
O << "\t@ far jump";
return;
break;
- case 116:
+ case 117:
// tLDRpci
O << ".n\t";
printOperand(MI, 0);
@@ -2979,7 +2989,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
printOperand(MI, 1);
return;
break;
- case 117:
+ case 118:
// tMOVi8, tMVN, tRSB
printPredicateOperand(MI, 3);
O << "\t";
@@ -2987,7 +2997,7 @@ void ARMAsmPrinter::printInstruction(const MachineInstr *MI) {
O << ", ";
printOperand(MI, 2);
break;
- case 118:
+ case 119:
// tPICADD
O << ":\n\tadd\t";
printOperand(MI, 0);
@@ -6636,148 +6646,149 @@ const char *ARMAsmPrinter::getRegisterName(unsigned RegNo) {
/// from the instruction set description. This returns the enum name of the
/// specified instruction.
const char *ARMAsmPrinter::getInstructionName(unsigned Opcode) {
- assert(Opcode < 1945 && "Invalid instruction number!");
+ assert(Opcode < 1949 && "Invalid instruction number!");
static const unsigned InstAsmOffset[] = {
0, 4, 14, 24, 33, 42, 47, 62, 76, 89, 103, 120, 130, 138,
146, 154, 160, 166, 172, 179, 186, 193, 199, 205, 211, 228, 243, 249,
255, 261, 281, 301, 320, 340, 360, 379, 399, 419, 438, 459, 480, 500,
519, 538, 556, 576, 596, 615, 635, 655, 674, 690, 706, 721, 723, 727,
- 731, 737, 743, 749, 754, 757, 761, 767, 775, 780, 790, 796, 805, 812,
- 819, 822, 826, 833, 838, 842, 846, 851, 857, 861, 868, 875, 882, 888,
- 894, 900, 907, 914, 921, 937, 941, 945, 952, 961, 968, 977, 984, 993,
- 999, 1006, 1015, 1022, 1031, 1038, 1047, 1053, 1059, 1065, 1071, 1079, 1087, 1094,
- 1100, 1117, 1134, 1152, 1170, 1189, 1202, 1215, 1226, 1236, 1248, 1260, 1270, 1279,
- 1291, 1303, 1313, 1322, 1333, 1344, 1353, 1361, 1365, 1373, 1377, 1382, 1388, 1398,
- 1407, 1412, 1422, 1431, 1437, 1444, 1451, 1458, 1463, 1469, 1479, 1488, 1494, 1501,
- 1512, 1522, 1528, 1535, 1546, 1556, 1561, 1570, 1578, 1584, 1593, 1604, 1608, 1613,
- 1618, 1624, 1628, 1632, 1639, 1646, 1653, 1661, 1666, 1673, 1685, 1695, 1700, 1706,
- 1711, 1723, 1735, 1739, 1744, 1749, 1755, 1759, 1766, 1770, 1775, 1782, 1790, 1794,
- 1799, 1804, 1809, 1813, 1819, 1825, 1831, 1838, 1845, 1853, 1861, 1870, 1879, 1886,
- 1894, 1902, 1908, 1914, 1920, 1926, 1931, 1936, 1941, 1946, 1951, 1958, 1964, 1969,
- 1975, 1981, 1986, 1991, 1998, 2004, 2009, 2013, 2019, 2025, 2029, 2034, 2041, 2048,
- 2054, 2060, 2067, 2074, 2080, 2086, 2093, 2099, 2104, 2112, 2120, 2128, 2134, 2140,
- 2146, 2151, 2155, 2164, 2173, 2177, 2185, 2192, 2198, 2204, 2212, 2219, 2223, 2230,
- 2237, 2243, 2250, 2256, 2264, 2272, 2279, 2287, 2295, 2303, 2310, 2317, 2324, 2331,
- 2337, 2344, 2351, 2359, 2365, 2372, 2378, 2385, 2391, 2398, 2404, 2411, 2418, 2425,
- 2431, 2438, 2445, 2452, 2459, 2465, 2472, 2476, 2481, 2488, 2496, 2504, 2509, 2516,
- 2522, 2535, 2548, 2559, 2569, 2581, 2593, 2603, 2612, 2624, 2636, 2646, 2655, 2666,
- 2677, 2686, 2694, 2698, 2702, 2707, 2713, 2723, 2732, 2737, 2747, 2756, 2762, 2769,
- 2776, 2783, 2788, 2794, 2804, 2813, 2818, 2827, 2835, 2842, 2849, 2856, 2862, 2868,
- 2874, 2878, 2882, 2887, 2897, 2911, 2919, 2931, 2939, 2951, 2959, 2971, 2977, 2987,
- 2993, 3003, 3009, 3015, 3021, 3028, 3033, 3039, 3045, 3051, 3058, 3064, 3069, 3074,
- 3082, 3089, 3095, 3101, 3109, 3116, 3122, 3128, 3134, 3142, 3149, 3155, 3161, 3169,
- 3176, 3182, 3189, 3196, 3204, 3212, 3217, 3224, 3230, 3240, 3254, 3262, 3274, 3282,
- 3294, 3302, 3314, 3320, 3330, 3336, 3346, 3358, 3370, 3382, 3394, 3406, 3418, 3429,
- 3440, 3451, 3462, 3473, 3483, 3494, 3505, 3516, 3527, 3538, 3548, 3560, 3572, 3584,
- 3596, 3608, 3620, 3627, 3634, 3645, 3656, 3667, 3678, 3689, 3699, 3710, 3721, 3732,
- 3743, 3754, 3764, 3770, 3776, 3783, 3794, 3801, 3811, 3821, 3831, 3841, 3851, 3860,
- 3867, 3874, 3881, 3888, 3894, 3906, 3918, 3929, 3941, 3953, 3965, 3977, 3989, 4001,
- 4007, 4019, 4031, 4043, 4055, 4067, 4079, 4086, 4097, 4104, 4114, 4124, 4134, 4144,
- 4154, 4164, 4174, 4183, 4189, 4195, 4201, 4207, 4213, 4219, 4225, 4231, 4237, 4243,
- 4250, 4257, 4267, 4277, 4287, 4297, 4307, 4316, 4327, 4338, 4349, 4360, 4371, 4382,
- 4393, 4403, 4410, 4417, 4428, 4439, 4450, 4461, 4472, 4482, 4493, 4504, 4515, 4526,
- 4537, 4547, 4558, 4569, 4580, 4591, 4602, 4613, 4624, 4634, 4641, 4648, 4659, 4670,
- 4681, 4692, 4703, 4713, 4724, 4735, 4746, 4757, 4768, 4778, 4789, 4800, 4811, 4822,
- 4833, 4844, 4855, 4865, 4876, 4887, 4898, 4909, 4920, 4931, 4942, 4952, 4962, 4972,
- 4982, 4992, 5002, 5011, 5022, 5033, 5044, 5055, 5066, 5077, 5088, 5098, 5108, 5118,
- 5128, 5138, 5148, 5157, 5163, 5170, 5177, 5185, 5193, 5199, 5206, 5213, 5219, 5225,
- 5233, 5241, 5248, 5255, 5263, 5271, 5280, 5293, 5302, 5311, 5324, 5333, 5343, 5353,
- 5363, 5373, 5382, 5395, 5404, 5413, 5426, 5435, 5445, 5455, 5465, 5475, 5481, 5487,
- 5495, 5503, 5511, 5519, 5526, 5533, 5543, 5553, 5563, 5573, 5582, 5591, 5600, 5609,
- 5616, 5624, 5631, 5639, 5645, 5651, 5659, 5667, 5674, 5681, 5689, 5697, 5704, 5711,
- 5721, 5731, 5740, 5750, 5759, 5771, 5783, 5795, 5807, 5819, 5830, 5842, 5854, 5866,
- 5878, 5890, 5901, 5913, 5925, 5937, 5949, 5961, 5972, 5984, 5996, 6008, 6020, 6032,
- 6043, 6051, 6060, 6069, 6077, 6086, 6095, 6103, 6110, 6118, 6126, 6133, 6141, 6149,
- 6157, 6164, 6171, 6181, 6191, 6200, 6211, 6222, 6233, 6244, 6252, 6261, 6269, 6278,
- 6286, 6293, 6301, 6309, 6317, 6324, 6334, 6344, 6353, 6364, 6375, 6386, 6397, 6405,
- 6413, 6421, 6428, 6437, 6446, 6455, 6464, 6472, 6480, 6490, 6500, 6509, 6520, 6531,
- 6542, 6553, 6561, 6569, 6577, 6584, 6593, 6602, 6611, 6620, 6628, 6636, 6642, 6648,
- 6654, 6660, 6666, 6673, 6684, 6691, 6702, 6713, 6724, 6735, 6746, 6756, 6767, 6778,
- 6789, 6800, 6811, 6821, 6828, 6839, 6846, 6857, 6868, 6879, 6890, 6901, 6911, 6922,
- 6933, 6944, 6955, 6966, 6976, 6982, 6996, 7010, 7024, 7038, 7050, 7062, 7074, 7086,
- 7098, 7110, 7116, 7123, 7130, 7139, 7148, 7160, 7172, 7184, 7196, 7206, 7216, 7226,
- 7236, 7246, 7255, 7261, 7275, 7289, 7303, 7317, 7329, 7341, 7353, 7365, 7377, 7389,
- 7395, 7402, 7409, 7418, 7427, 7439, 7451, 7463, 7475, 7485, 7495, 7505, 7515, 7525,
- 7534, 7540, 7548, 7556, 7566, 7578, 7590, 7602, 7614, 7626, 7638, 7649, 7660, 7670,
- 7676, 7684, 7692, 7699, 7705, 7712, 7720, 7728, 7738, 7748, 7758, 7768, 7778, 7788,
- 7798, 7807, 7812, 7817, 7823, 7830, 7844, 7858, 7872, 7886, 7898, 7910, 7922, 7934,
- 7946, 7958, 7964, 7971, 7982, 7989, 7996, 8003, 8012, 8021, 8033, 8045, 8057, 8069,
- 8079, 8089, 8099, 8109, 8119, 8128, 8134, 8140, 8146, 8154, 8160, 8168, 8177, 8184,
- 8195, 8204, 8213, 8222, 8231, 8239, 8247, 8254, 8261, 8268, 8275, 8282, 8289, 8295,
- 8301, 8307, 8313, 8326, 8339, 8352, 8365, 8378, 8390, 8403, 8416, 8429, 8442, 8455,
- 8467, 8480, 8493, 8506, 8519, 8532, 8544, 8557, 8570, 8583, 8596, 8609, 8621, 8628,
- 8637, 8646, 8654, 8661, 8670, 8679, 8687, 8696, 8705, 8713, 8720, 8729, 8738, 8746,
- 8755, 8764, 8772, 8783, 8794, 8805, 8816, 8827, 8837, 8849, 8861, 8873, 8885, 8897,
- 8909, 8921, 8932, 8944, 8956, 8968, 8980, 8992, 9004, 9016, 9027, 9042, 9057, 9070,
- 9083, 9098, 9113, 9126, 9139, 9154, 9169, 9184, 9199, 9212, 9225, 9238, 9251, 9266,
- 9281, 9294, 9307, 9321, 9335, 9348, 9361, 9374, 9386, 9399, 9412, 9424, 9435, 9446,
- 9457, 9468, 9479, 9489, 9505, 9521, 9537, 9553, 9567, 9581, 9595, 9609, 9622, 9635,
- 9648, 9661, 9674, 9687, 9700, 9712, 9725, 9738, 9751, 9764, 9777, 9790, 9803, 9815,
- 9829, 9843, 9856, 9870, 9884, 9897, 9911, 9925, 9938, 9951, 9964, 9977, 9990, 10003,
- 10016, 10029, 10041, 10054, 10067, 10080, 10093, 10106, 10119, 10132, 10144, 10156, 10168, 10180,
- 10192, 10204, 10216, 10228, 10239, 10252, 10265, 10278, 10291, 10304, 10317, 10330, 10342, 10354,
- 10366, 10378, 10390, 10402, 10414, 10426, 10437, 10450, 10463, 10475, 10488, 10501, 10513, 10526,
- 10539, 10551, 10563, 10575, 10587, 10599, 10611, 10623, 10635, 10646, 10658, 10670, 10682, 10694,
- 10706, 10718, 10730, 10741, 10754, 10767, 10779, 10787, 10796, 10805, 10813, 10822, 10831, 10840,
- 10849, 10859, 10868, 10878, 10887, 10897, 10907, 10916, 10925, 10935, 10945, 10954, 10963, 10976,
- 10989, 11002, 11015, 11028, 11040, 11053, 11066, 11079, 11092, 11105, 11117, 11129, 11141, 11153,
- 11165, 11177, 11189, 11201, 11212, 11224, 11236, 11248, 11260, 11272, 11284, 11296, 11307, 11319,
- 11331, 11342, 11354, 11366, 11378, 11390, 11402, 11414, 11426, 11437, 11449, 11461, 11473, 11485,
- 11497, 11509, 11521, 11532, 11541, 11551, 11561, 11570, 11580, 11590, 11602, 11614, 11626, 11638,
- 11650, 11662, 11674, 11685, 11697, 11709, 11721, 11733, 11745, 11757, 11769, 11780, 11793, 11806,
- 11818, 11828, 11838, 11847, 11856, 11865, 11873, 11885, 11897, 11909, 11921, 11933, 11945, 11956,
- 11967, 11978, 11989, 12000, 12011, 12022, 12032, 12043, 12054, 12065, 12076, 12087, 12098, 12109,
- 12119, 12130, 12141, 12152, 12163, 12174, 12185, 12196, 12206, 12217, 12228, 12238, 12249, 12260,
- 12271, 12282, 12293, 12304, 12315, 12325, 12336, 12347, 12358, 12369, 12380, 12391, 12402, 12412,
- 12419, 12426, 12433, 12440, 12450, 12460, 12470, 12480, 12490, 12500, 12510, 12519, 12526, 12533,
- 12540, 12547, 12558, 12569, 12580, 12591, 12602, 12613, 12624, 12634, 12645, 12656, 12667, 12678,
- 12689, 12700, 12711, 12721, 12731, 12741, 12751, 12761, 12771, 12781, 12791, 12800, 12808, 12817,
- 12826, 12834, 12843, 12852, 12860, 12867, 12875, 12883, 12890, 12898, 12906, 12914, 12921, 12928,
- 12938, 12948, 12957, 12968, 12979, 12990, 13001, 13009, 13018, 13026, 13035, 13043, 13050, 13058,
- 13066, 13074, 13081, 13091, 13101, 13110, 13121, 13132, 13143, 13154, 13162, 13170, 13178, 13185,
- 13194, 13203, 13212, 13221, 13229, 13237, 13247, 13257, 13266, 13277, 13288, 13299, 13310, 13318,
- 13326, 13334, 13341, 13350, 13359, 13368, 13377, 13385, 13393, 13399, 13405, 13411, 13417, 13423,
- 13429, 13441, 13453, 13464, 13476, 13488, 13500, 13512, 13524, 13536, 13542, 13554, 13566, 13578,
- 13590, 13602, 13614, 13621, 13632, 13639, 13649, 13659, 13669, 13679, 13689, 13699, 13709, 13718,
- 13724, 13730, 13736, 13742, 13748, 13754, 13760, 13766, 13772, 13778, 13785, 13792, 13800, 13808,
- 13816, 13824, 13831, 13838, 13845, 13852, 13860, 13868, 13876, 13884, 13891, 13898, 13906, 13914,
- 13921, 13929, 13937, 13944, 13954, 13964, 13974, 13984, 13994, 14003, 14010, 14017, 14024, 14031,
- 14038, 14045, 14053, 14061, 14068, 14076, 14084, 14091, 14099, 14107, 14114, 14122, 14130, 14137,
- 14141, 14145, 14151, 14160, 14169, 14178, 14186, 14194, 14202, 14211, 14220, 14229, 14239, 14251,
- 14261, 14269, 14279, 14287, 14295, 14303, 14311, 14319, 14327, 14335, 14339, 14345, 14351, 14359,
- 14367, 14375, 14383, 14389, 14395, 14403, 14409, 14418, 14427, 14436, 14444, 14452, 14460, 14469,
- 14478, 14487, 14493, 14499, 14508, 14519, 14528, 14539, 14548, 14559, 14567, 14576, 14587, 14596,
- 14607, 14616, 14627, 14635, 14643, 14651, 14659, 14667, 14672, 14691, 14711, 14732, 14738, 14748,
- 14756, 14768, 14779, 14789, 14798, 14808, 14816, 14825, 14835, 14843, 14852, 14861, 14870, 14878,
- 14890, 14901, 14911, 14920, 14930, 14938, 14947, 14960, 14972, 14983, 14993, 15004, 15013, 15022,
- 15035, 15047, 15058, 15068, 15079, 15088, 15095, 15106, 15116, 15125, 15133, 15142, 15155, 15162,
- 15173, 15186, 15194, 15202, 15210, 15218, 15224, 15230, 15241, 15250, 15261, 15272, 15281, 15292,
- 15302, 15309, 15318, 15330, 15337, 15345, 15359, 15373, 15379, 15388, 15394, 15403, 15409, 15416,
- 15423, 15430, 15436, 15444, 15452, 15460, 15468, 15476, 15484, 15492, 15500, 15510, 15519, 15529,
- 15537, 15545, 15554, 15562, 15571, 15578, 15585, 15594, 15602, 15611, 15618, 15625, 15632, 15641,
- 15649, 15656, 15664, 15672, 15679, 15686, 15695, 15703, 15710, 15716, 15724, 15732, 15740, 15749,
- 15757, 15766, 15774, 15782, 15791, 15800, 15808, 15816, 15825, 15833, 15840, 15849, 15858, 15867,
- 15875, 15883, 15891, 15898, 15905, 15911, 15917, 15927, 15936, 15944, 15952, 15962, 15971, 15977,
- 15986, 15995, 16003, 16012, 16020, 16030, 16040, 16049, 16059, 16069, 16079, 16088, 16097, 16106,
- 16115, 16123, 16132, 16141, 16151, 16159, 16168, 16176, 16185, 16193, 16202, 16210, 16219, 16228,
- 16237, 16245, 16254, 16263, 16272, 16281, 16289, 16298, 16306, 16315, 16323, 16332, 16341, 16351,
- 16361, 16368, 16377, 16385, 16391, 16399, 16411, 16422, 16432, 16441, 16449, 16458, 16466, 16475,
- 16484, 16493, 16501, 16513, 16524, 16534, 16543, 16551, 16558, 16569, 16579, 16588, 16596, 16603,
- 16612, 16621, 16630, 16640, 16652, 16665, 16676, 16686, 16697, 16705, 16715, 16723, 16731, 16743,
- 16759, 16769, 16783, 16793, 16807, 16817, 16831, 16839, 16851, 16859, 16871, 16877, 16886, 16892,
- 16901, 16909, 16917, 16925, 16934, 16942, 16950, 16958, 16967, 16975, 16982, 16989, 16996, 17006,
- 17015, 17023, 17031, 17041, 17050, 17058, 17066, 17074, 17084, 17093, 17101, 17109, 17119, 17128,
- 17136, 17145, 17154, 17164, 17174, 17181, 17190, 17198, 17210, 17226, 17236, 17250, 17260, 17274,
- 17284, 17298, 17306, 17318, 17326, 17338, 17344, 17350, 17358, 17363, 17372, 17379, 17386, 17395,
- 17403, 17412, 17419, 17427, 17435, 17444, 17462, 17478, 17483, 17490, 17497, 17504, 17507, 17512,
- 17518, 17522, 17528, 17537, 17543, 17552, 17558, 17565, 17573, 17577, 17585, 17600, 17606, 17611,
- 17617, 17623, 17628, 17634, 17642, 17649, 17655, 17664, 17672, 17679, 17684, 17689, 17709, 17714,
- 17719, 17725, 17732, 17738, 17745, 17752, 17759, 17766, 17772, 17780, 17792, 17800, 17810, 17822,
- 17829, 17836, 17843, 17850, 17858, 17866, 17881, 17888, 17900, 17913, 17920, 17926, 17939, 17944,
- 17949, 17954, 17959, 17967, 17972, 17981, 17987, 17992, 17999, 18006, 18011, 18016, 18025, 18030,
- 18040, 18050, 18055, 18060, 18065, 18071, 18078, 18084, 18091, 18097, 18105, 18112, 18119, 18126,
- 18134, 18143, 18148, 18154, 18160, 18167, 18175, 18181, 18186, 18192, 18198, 18203, 18208, 0
+ 731, 737, 743, 749, 754, 757, 761, 767, 775, 780, 790, 799, 810, 816,
+ 825, 832, 839, 842, 846, 853, 858, 862, 866, 871, 877, 881, 888, 895,
+ 902, 908, 914, 920, 927, 934, 941, 957, 961, 965, 972, 981, 988, 997,
+ 1004, 1013, 1019, 1026, 1035, 1042, 1051, 1058, 1067, 1073, 1079, 1085, 1091, 1099,
+ 1107, 1114, 1120, 1137, 1154, 1172, 1190, 1209, 1222, 1235, 1246, 1256, 1268, 1280,
+ 1290, 1299, 1311, 1323, 1333, 1342, 1353, 1364, 1373, 1381, 1385, 1393, 1397, 1402,
+ 1408, 1418, 1427, 1432, 1442, 1451, 1457, 1464, 1471, 1478, 1483, 1489, 1499, 1508,
+ 1514, 1521, 1532, 1542, 1548, 1555, 1566, 1576, 1581, 1590, 1598, 1604, 1613, 1624,
+ 1628, 1633, 1638, 1644, 1648, 1652, 1659, 1666, 1673, 1681, 1689, 1697, 1702, 1709,
+ 1721, 1731, 1736, 1742, 1747, 1759, 1771, 1775, 1780, 1785, 1791, 1795, 1802, 1806,
+ 1811, 1818, 1826, 1830, 1835, 1840, 1845, 1849, 1855, 1861, 1867, 1874, 1881, 1889,
+ 1897, 1906, 1915, 1922, 1930, 1938, 1944, 1950, 1956, 1962, 1967, 1972, 1977, 1982,
+ 1987, 1994, 2000, 2005, 2011, 2017, 2022, 2027, 2034, 2040, 2045, 2049, 2055, 2061,
+ 2065, 2070, 2077, 2084, 2090, 2096, 2103, 2110, 2116, 2122, 2129, 2135, 2140, 2148,
+ 2156, 2164, 2170, 2176, 2182, 2187, 2191, 2200, 2209, 2213, 2221, 2228, 2234, 2240,
+ 2248, 2255, 2259, 2266, 2273, 2279, 2286, 2292, 2300, 2308, 2315, 2323, 2331, 2339,
+ 2346, 2353, 2360, 2367, 2373, 2380, 2387, 2395, 2401, 2408, 2414, 2421, 2427, 2434,
+ 2440, 2447, 2454, 2461, 2467, 2474, 2481, 2488, 2495, 2501, 2508, 2512, 2517, 2524,
+ 2532, 2540, 2545, 2552, 2558, 2571, 2584, 2595, 2605, 2617, 2629, 2639, 2648, 2660,
+ 2672, 2682, 2691, 2702, 2713, 2722, 2730, 2734, 2738, 2743, 2749, 2759, 2768, 2773,
+ 2783, 2792, 2798, 2805, 2812, 2819, 2824, 2830, 2840, 2849, 2854, 2863, 2871, 2878,
+ 2885, 2892, 2898, 2904, 2910, 2914, 2918, 2923, 2933, 2947, 2955, 2967, 2975, 2987,
+ 2995, 3007, 3013, 3023, 3029, 3039, 3045, 3051, 3057, 3064, 3069, 3075, 3081, 3087,
+ 3094, 3100, 3105, 3110, 3118, 3125, 3131, 3137, 3145, 3152, 3158, 3164, 3170, 3178,
+ 3185, 3191, 3197, 3205, 3212, 3218, 3225, 3232, 3240, 3248, 3253, 3260, 3266, 3276,
+ 3290, 3298, 3310, 3318, 3330, 3338, 3350, 3356, 3366, 3372, 3382, 3394, 3406, 3418,
+ 3430, 3442, 3454, 3465, 3476, 3487, 3498, 3509, 3519, 3530, 3541, 3552, 3563, 3574,
+ 3584, 3596, 3608, 3620, 3632, 3644, 3656, 3663, 3670, 3681, 3692, 3703, 3714, 3725,
+ 3735, 3746, 3757, 3768, 3779, 3790, 3800, 3806, 3812, 3819, 3830, 3837, 3847, 3857,
+ 3867, 3877, 3887, 3896, 3903, 3910, 3917, 3924, 3930, 3942, 3954, 3965, 3977, 3989,
+ 4001, 4013, 4025, 4037, 4043, 4055, 4067, 4079, 4091, 4103, 4115, 4122, 4133, 4140,
+ 4150, 4160, 4170, 4180, 4190, 4200, 4210, 4219, 4225, 4231, 4237, 4243, 4249, 4255,
+ 4261, 4267, 4273, 4279, 4286, 4293, 4303, 4313, 4323, 4333, 4343, 4352, 4363, 4374,
+ 4385, 4396, 4407, 4418, 4429, 4439, 4446, 4453, 4464, 4475, 4486, 4497, 4508, 4518,
+ 4529, 4540, 4551, 4562, 4573, 4583, 4594, 4605, 4616, 4627, 4638, 4649, 4660, 4670,
+ 4677, 4684, 4695, 4706, 4717, 4728, 4739, 4749, 4760, 4771, 4782, 4793, 4804, 4814,
+ 4825, 4836, 4847, 4858, 4869, 4880, 4891, 4901, 4912, 4923, 4934, 4945, 4956, 4967,
+ 4978, 4988, 4998, 5008, 5018, 5028, 5038, 5047, 5058, 5069, 5080, 5091, 5102, 5113,
+ 5124, 5134, 5144, 5154, 5164, 5174, 5184, 5193, 5199, 5206, 5213, 5221, 5229, 5235,
+ 5242, 5249, 5255, 5261, 5269, 5277, 5284, 5291, 5299, 5307, 5316, 5329, 5338, 5347,
+ 5360, 5369, 5379, 5389, 5399, 5409, 5418, 5431, 5440, 5449, 5462, 5471, 5481, 5491,
+ 5501, 5511, 5517, 5523, 5531, 5539, 5547, 5555, 5562, 5569, 5579, 5589, 5599, 5609,
+ 5618, 5627, 5636, 5645, 5652, 5660, 5667, 5675, 5681, 5687, 5695, 5703, 5710, 5717,
+ 5725, 5733, 5740, 5747, 5757, 5767, 5776, 5786, 5795, 5807, 5819, 5831, 5843, 5855,
+ 5866, 5878, 5890, 5902, 5914, 5926, 5937, 5949, 5961, 5973, 5985, 5997, 6008, 6020,
+ 6032, 6044, 6056, 6068, 6079, 6087, 6096, 6105, 6113, 6122, 6131, 6139, 6146, 6154,
+ 6162, 6169, 6177, 6185, 6193, 6200, 6207, 6217, 6227, 6236, 6247, 6258, 6269, 6280,
+ 6288, 6297, 6305, 6314, 6322, 6329, 6337, 6345, 6353, 6360, 6370, 6380, 6389, 6400,
+ 6411, 6422, 6433, 6441, 6449, 6457, 6464, 6473, 6482, 6491, 6500, 6508, 6516, 6526,
+ 6536, 6545, 6556, 6567, 6578, 6589, 6597, 6605, 6613, 6620, 6629, 6638, 6647, 6656,
+ 6664, 6672, 6678, 6684, 6690, 6696, 6702, 6709, 6720, 6727, 6738, 6749, 6760, 6771,
+ 6782, 6792, 6803, 6814, 6825, 6836, 6847, 6857, 6864, 6875, 6882, 6893, 6904, 6915,
+ 6926, 6937, 6947, 6958, 6969, 6980, 6991, 7002, 7012, 7018, 7032, 7046, 7060, 7074,
+ 7086, 7098, 7110, 7122, 7134, 7146, 7152, 7159, 7166, 7175, 7184, 7196, 7208, 7220,
+ 7232, 7242, 7252, 7262, 7272, 7282, 7291, 7297, 7311, 7325, 7339, 7353, 7365, 7377,
+ 7389, 7401, 7413, 7425, 7431, 7438, 7445, 7454, 7463, 7475, 7487, 7499, 7511, 7521,
+ 7531, 7541, 7551, 7561, 7570, 7576, 7584, 7592, 7602, 7614, 7626, 7638, 7650, 7662,
+ 7674, 7685, 7696, 7706, 7712, 7720, 7728, 7735, 7741, 7748, 7756, 7764, 7774, 7784,
+ 7794, 7804, 7814, 7824, 7834, 7843, 7848, 7853, 7859, 7866, 7880, 7894, 7908, 7922,
+ 7934, 7946, 7958, 7970, 7982, 7994, 8000, 8007, 8018, 8025, 8032, 8039, 8048, 8057,
+ 8069, 8081, 8093, 8105, 8115, 8125, 8135, 8145, 8155, 8164, 8170, 8176, 8182, 8190,
+ 8196, 8204, 8213, 8220, 8231, 8240, 8249, 8258, 8267, 8275, 8283, 8290, 8297, 8304,
+ 8311, 8318, 8325, 8331, 8337, 8343, 8349, 8362, 8375, 8388, 8401, 8414, 8426, 8439,
+ 8452, 8465, 8478, 8491, 8503, 8516, 8529, 8542, 8555, 8568, 8580, 8593, 8606, 8619,
+ 8632, 8645, 8657, 8664, 8673, 8682, 8690, 8697, 8706, 8715, 8723, 8732, 8741, 8749,
+ 8756, 8765, 8774, 8782, 8791, 8800, 8808, 8819, 8830, 8841, 8852, 8863, 8873, 8885,
+ 8897, 8909, 8921, 8933, 8945, 8957, 8968, 8980, 8992, 9004, 9016, 9028, 9040, 9052,
+ 9063, 9078, 9093, 9106, 9119, 9134, 9149, 9162, 9175, 9190, 9205, 9220, 9235, 9248,
+ 9261, 9274, 9287, 9302, 9317, 9330, 9343, 9357, 9371, 9384, 9397, 9410, 9422, 9435,
+ 9448, 9460, 9471, 9482, 9493, 9504, 9515, 9525, 9541, 9557, 9573, 9589, 9603, 9617,
+ 9631, 9645, 9658, 9671, 9684, 9697, 9710, 9723, 9736, 9748, 9761, 9774, 9787, 9800,
+ 9813, 9826, 9839, 9851, 9865, 9879, 9892, 9906, 9920, 9933, 9947, 9961, 9974, 9987,
+ 10000, 10013, 10026, 10039, 10052, 10065, 10077, 10090, 10103, 10116, 10129, 10142, 10155, 10168,
+ 10180, 10192, 10204, 10216, 10228, 10240, 10252, 10264, 10275, 10288, 10301, 10314, 10327, 10340,
+ 10353, 10366, 10378, 10390, 10402, 10414, 10426, 10438, 10450, 10462, 10473, 10486, 10499, 10511,
+ 10524, 10537, 10549, 10562, 10575, 10587, 10599, 10611, 10623, 10635, 10647, 10659, 10671, 10682,
+ 10694, 10706, 10718, 10730, 10742, 10754, 10766, 10777, 10790, 10803, 10815, 10823, 10832, 10841,
+ 10849, 10858, 10867, 10876, 10885, 10895, 10904, 10914, 10923, 10933, 10943, 10952, 10961, 10971,
+ 10981, 10990, 10999, 11012, 11025, 11038, 11051, 11064, 11076, 11089, 11102, 11115, 11128, 11141,
+ 11153, 11165, 11177, 11189, 11201, 11213, 11225, 11237, 11248, 11260, 11272, 11284, 11296, 11308,
+ 11320, 11332, 11343, 11355, 11367, 11378, 11390, 11402, 11414, 11426, 11438, 11450, 11462, 11473,
+ 11485, 11497, 11509, 11521, 11533, 11545, 11557, 11568, 11577, 11587, 11597, 11606, 11616, 11626,
+ 11638, 11650, 11662, 11674, 11686, 11698, 11710, 11721, 11733, 11745, 11757, 11769, 11781, 11793,
+ 11805, 11816, 11829, 11842, 11854, 11864, 11874, 11883, 11892, 11901, 11909, 11921, 11933, 11945,
+ 11957, 11969, 11981, 11992, 12003, 12014, 12025, 12036, 12047, 12058, 12068, 12079, 12090, 12101,
+ 12112, 12123, 12134, 12145, 12155, 12166, 12177, 12188, 12199, 12210, 12221, 12232, 12242, 12253,
+ 12264, 12274, 12285, 12296, 12307, 12318, 12329, 12340, 12351, 12361, 12372, 12383, 12394, 12405,
+ 12416, 12427, 12438, 12448, 12455, 12462, 12469, 12476, 12486, 12496, 12506, 12516, 12526, 12536,
+ 12546, 12555, 12562, 12569, 12576, 12583, 12594, 12605, 12616, 12627, 12638, 12649, 12660, 12670,
+ 12681, 12692, 12703, 12714, 12725, 12736, 12747, 12757, 12767, 12777, 12787, 12797, 12807, 12817,
+ 12827, 12836, 12844, 12853, 12862, 12870, 12879, 12888, 12896, 12903, 12911, 12919, 12926, 12934,
+ 12942, 12950, 12957, 12964, 12974, 12984, 12993, 13004, 13015, 13026, 13037, 13045, 13054, 13062,
+ 13071, 13079, 13086, 13094, 13102, 13110, 13117, 13127, 13137, 13146, 13157, 13168, 13179, 13190,
+ 13198, 13206, 13214, 13221, 13230, 13239, 13248, 13257, 13265, 13273, 13283, 13293, 13302, 13313,
+ 13324, 13335, 13346, 13354, 13362, 13370, 13377, 13386, 13395, 13404, 13413, 13421, 13429, 13435,
+ 13441, 13447, 13453, 13459, 13465, 13477, 13489, 13500, 13512, 13524, 13536, 13548, 13560, 13572,
+ 13578, 13590, 13602, 13614, 13626, 13638, 13650, 13657, 13668, 13675, 13685, 13695, 13705, 13715,
+ 13725, 13735, 13745, 13754, 13760, 13766, 13772, 13778, 13784, 13790, 13796, 13802, 13808, 13814,
+ 13821, 13828, 13836, 13844, 13852, 13860, 13867, 13874, 13881, 13888, 13896, 13904, 13912, 13920,
+ 13927, 13934, 13942, 13950, 13957, 13965, 13973, 13980, 13990, 14000, 14010, 14020, 14030, 14039,
+ 14046, 14053, 14060, 14067, 14074, 14081, 14089, 14097, 14104, 14112, 14120, 14127, 14135, 14143,
+ 14150, 14158, 14166, 14173, 14177, 14181, 14187, 14196, 14205, 14214, 14222, 14230, 14238, 14247,
+ 14256, 14265, 14275, 14287, 14297, 14305, 14315, 14323, 14331, 14339, 14347, 14355, 14363, 14371,
+ 14375, 14381, 14387, 14395, 14403, 14411, 14419, 14425, 14431, 14439, 14445, 14454, 14463, 14472,
+ 14480, 14488, 14496, 14505, 14514, 14523, 14529, 14535, 14544, 14555, 14564, 14575, 14584, 14595,
+ 14603, 14612, 14623, 14632, 14643, 14652, 14663, 14671, 14679, 14687, 14695, 14703, 14708, 14727,
+ 14747, 14768, 14774, 14784, 14792, 14804, 14815, 14825, 14834, 14844, 14852, 14861, 14871, 14879,
+ 14888, 14897, 14906, 14914, 14926, 14937, 14947, 14956, 14966, 14974, 14983, 14996, 15008, 15019,
+ 15029, 15040, 15049, 15058, 15071, 15083, 15094, 15104, 15115, 15124, 15131, 15142, 15152, 15161,
+ 15169, 15178, 15191, 15198, 15209, 15222, 15230, 15238, 15246, 15254, 15260, 15266, 15277, 15286,
+ 15297, 15308, 15317, 15328, 15338, 15345, 15354, 15366, 15373, 15381, 15395, 15409, 15415, 15424,
+ 15430, 15439, 15445, 15452, 15459, 15466, 15472, 15480, 15488, 15496, 15504, 15512, 15520, 15528,
+ 15536, 15546, 15555, 15565, 15573, 15581, 15590, 15598, 15607, 15614, 15621, 15630, 15638, 15647,
+ 15654, 15661, 15668, 15677, 15685, 15692, 15700, 15708, 15715, 15722, 15731, 15739, 15746, 15752,
+ 15760, 15768, 15776, 15785, 15793, 15802, 15810, 15818, 15827, 15836, 15844, 15852, 15861, 15869,
+ 15876, 15885, 15894, 15903, 15911, 15919, 15927, 15934, 15941, 15947, 15953, 15963, 15972, 15980,
+ 15988, 15998, 16007, 16013, 16022, 16031, 16039, 16048, 16056, 16066, 16076, 16085, 16095, 16105,
+ 16115, 16124, 16133, 16142, 16151, 16159, 16168, 16177, 16187, 16195, 16204, 16212, 16221, 16229,
+ 16238, 16246, 16255, 16264, 16273, 16281, 16290, 16299, 16308, 16317, 16325, 16334, 16342, 16351,
+ 16359, 16368, 16377, 16387, 16397, 16404, 16413, 16421, 16427, 16435, 16447, 16458, 16468, 16477,
+ 16485, 16494, 16502, 16511, 16520, 16529, 16537, 16549, 16560, 16570, 16579, 16587, 16594, 16605,
+ 16615, 16624, 16632, 16639, 16648, 16657, 16666, 16676, 16688, 16701, 16712, 16722, 16733, 16741,
+ 16751, 16759, 16767, 16779, 16795, 16805, 16819, 16829, 16843, 16853, 16867, 16875, 16887, 16895,
+ 16907, 16913, 16922, 16928, 16937, 16945, 16953, 16961, 16970, 16978, 16986, 16994, 17003, 17011,
+ 17018, 17025, 17032, 17042, 17051, 17059, 17067, 17077, 17086, 17094, 17102, 17110, 17120, 17129,
+ 17137, 17145, 17155, 17164, 17172, 17181, 17190, 17200, 17210, 17217, 17226, 17234, 17246, 17262,
+ 17272, 17286, 17296, 17310, 17320, 17334, 17342, 17354, 17362, 17374, 17380, 17386, 17394, 17399,
+ 17408, 17415, 17422, 17431, 17439, 17448, 17455, 17463, 17471, 17480, 17498, 17514, 17519, 17526,
+ 17533, 17540, 17543, 17548, 17554, 17558, 17564, 17573, 17579, 17588, 17594, 17601, 17609, 17613,
+ 17621, 17636, 17642, 17647, 17653, 17659, 17664, 17670, 17678, 17685, 17691, 17700, 17708, 17715,
+ 17720, 17725, 17745, 17750, 17755, 17761, 17768, 17774, 17781, 17788, 17795, 17802, 17808, 17816,
+ 17828, 17836, 17846, 17858, 17865, 17872, 17879, 17886, 17894, 17902, 17917, 17924, 17936, 17949,
+ 17956, 17962, 17975, 17980, 17985, 17990, 17995, 18003, 18008, 18017, 18023, 18028, 18035, 18042,
+ 18047, 18052, 18061, 18066, 18076, 18086, 18091, 18096, 18101, 18107, 18114, 18120, 18127, 18133,
+ 18141, 18148, 18155, 18162, 18170, 18179, 18184, 18190, 18196, 18203, 18211, 18217, 18222, 18228,
+ 18234, 18239, 18244, 0
};
const char *Strs =
@@ -6794,330 +6805,330 @@ const char *ARMAsmPrinter::getInstructionName(unsigned Opcode) {
"ATOMIC_LOAD_SUB_I32\000ATOMIC_LOAD_SUB_I8\000ATOMIC_LOAD_XOR_I16\000ATO"
"MIC_LOAD_XOR_I32\000ATOMIC_LOAD_XOR_I8\000ATOMIC_SWAP_I16\000ATOMIC_SWA"
"P_I32\000ATOMIC_SWAP_I8\000B\000BFC\000BFI\000BICri\000BICrr\000BICrs\000"
- "BKPT\000BL\000BLX\000BLXr9\000BL_pred\000BLr9\000BLr9_pred\000BRIND\000"
- "BR_JTadd\000BR_JTm\000BR_JTr\000BX\000BXJ\000BX_RET\000BXr9\000Bcc\000C"
- "DP\000CDP2\000CLREX\000CLZ\000CMNzri\000CMNzrr\000CMNzrs\000CMPri\000CM"
- "Prr\000CMPrs\000CMPzri\000CMPzrr\000CMPzrs\000CONSTPOOL_ENTRY\000CPS\000"
- "DBG\000DMBish\000DMBishst\000DMBnsh\000DMBnshst\000DMBosh\000DMBoshst\000"
- "DMBst\000DSBish\000DSBishst\000DSBnsh\000DSBnshst\000DSBosh\000DSBoshst"
- "\000DSBst\000EORri\000EORrr\000EORrs\000FCONSTD\000FCONSTS\000FMSTAT\000"
- "ISBsy\000Int_MemBarrierV6\000Int_MemBarrierV7\000Int_SyncBarrierV6\000I"
- "nt_SyncBarrierV7\000Int_eh_sjlj_setjmp\000LDC2L_OFFSET\000LDC2L_OPTION\000"
- "LDC2L_POST\000LDC2L_PRE\000LDC2_OFFSET\000LDC2_OPTION\000LDC2_POST\000L"
- "DC2_PRE\000LDCL_OFFSET\000LDCL_OPTION\000LDCL_POST\000LDCL_PRE\000LDC_O"
- "FFSET\000LDC_OPTION\000LDC_POST\000LDC_PRE\000LDM\000LDM_RET\000LDR\000"
- "LDRB\000LDRBT\000LDRB_POST\000LDRB_PRE\000LDRD\000LDRD_POST\000LDRD_PRE"
- "\000LDREX\000LDREXB\000LDREXD\000LDREXH\000LDRH\000LDRHT\000LDRH_POST\000"
- "LDRH_PRE\000LDRSB\000LDRSBT\000LDRSB_POST\000LDRSB_PRE\000LDRSH\000LDRS"
- "HT\000LDRSH_POST\000LDRSH_PRE\000LDRT\000LDR_POST\000LDR_PRE\000LDRcp\000"
- "LEApcrel\000LEApcrelJT\000MCR\000MCR2\000MCRR\000MCRR2\000MLA\000MLS\000"
- "MOVCCi\000MOVCCr\000MOVCCs\000MOVTi16\000MOVi\000MOVi16\000MOVi2pieces\000"
- "MOVi32imm\000MOVr\000MOVrx\000MOVs\000MOVsra_flag\000MOVsrl_flag\000MRC"
- "\000MRC2\000MRRC\000MRRC2\000MRS\000MRSsys\000MSR\000MSRi\000MSRsys\000"
- "MSRsysi\000MUL\000MVNi\000MVNr\000MVNs\000NOP\000ORRri\000ORRrr\000ORRr"
- "s\000PICADD\000PICLDR\000PICLDRB\000PICLDRH\000PICLDRSB\000PICLDRSH\000"
- "PICSTR\000PICSTRB\000PICSTRH\000PKHBT\000PKHTB\000PLDWi\000PLDWr\000PLD"
- "i\000PLDr\000PLIi\000PLIr\000QADD\000QADD16\000QADD8\000QASX\000QDADD\000"
- "QDSUB\000QSAX\000QSUB\000QSUB16\000QSUB8\000RBIT\000REV\000REV16\000REV"
- "SH\000RFE\000RFEW\000RSBSri\000RSBSrs\000RSBri\000RSBrs\000RSCSri\000RS"
- "CSrs\000RSCri\000RSCrs\000SADD16\000SADD8\000SASX\000SBCSSri\000SBCSSrr"
- "\000SBCSSrs\000SBCri\000SBCrr\000SBCrs\000SBFX\000SEL\000SETENDBE\000SE"
- "TENDLE\000SEV\000SHADD16\000SHADD8\000SHASX\000SHSAX\000SHSUB16\000SHSU"
- "B8\000SMC\000SMLABB\000SMLABT\000SMLAD\000SMLADX\000SMLAL\000SMLALBB\000"
- "SMLALBT\000SMLALD\000SMLALDX\000SMLALTB\000SMLALTT\000SMLATB\000SMLATT\000"
- "SMLAWB\000SMLAWT\000SMLSD\000SMLSDX\000SMLSLD\000SMLSLDX\000SMMLA\000SM"
- "MLAR\000SMMLS\000SMMLSR\000SMMUL\000SMMULR\000SMUAD\000SMUADX\000SMULBB"
- "\000SMULBT\000SMULL\000SMULTB\000SMULTT\000SMULWB\000SMULWT\000SMUSD\000"
- "SMUSDX\000SRS\000SRSW\000SSAT16\000SSATasr\000SSATlsl\000SSAX\000SSUB16"
- "\000SSUB8\000STC2L_OFFSET\000STC2L_OPTION\000STC2L_POST\000STC2L_PRE\000"
- "STC2_OFFSET\000STC2_OPTION\000STC2_POST\000STC2_PRE\000STCL_OFFSET\000S"
- "TCL_OPTION\000STCL_POST\000STCL_PRE\000STC_OFFSET\000STC_OPTION\000STC_"
- "POST\000STC_PRE\000STM\000STR\000STRB\000STRBT\000STRB_POST\000STRB_PRE"
- "\000STRD\000STRD_POST\000STRD_PRE\000STREX\000STREXB\000STREXD\000STREX"
- "H\000STRH\000STRHT\000STRH_POST\000STRH_PRE\000STRT\000STR_POST\000STR_"
- "PRE\000SUBSri\000SUBSrr\000SUBSrs\000SUBri\000SUBrr\000SUBrs\000SVC\000"
- "SWP\000SWPB\000SXTAB16rr\000SXTAB16rr_rot\000SXTABrr\000SXTABrr_rot\000"
- "SXTAHrr\000SXTAHrr_rot\000SXTB16r\000SXTB16r_rot\000SXTBr\000SXTBr_rot\000"
- "SXTHr\000SXTHr_rot\000TEQri\000TEQrr\000TEQrs\000TPsoft\000TRAP\000TSTr"
- "i\000TSTrr\000TSTrs\000UADD16\000UADD8\000UASX\000UBFX\000UHADD16\000UH"
- "ADD8\000UHASX\000UHSAX\000UHSUB16\000UHSUB8\000UMAAL\000UMLAL\000UMULL\000"
- "UQADD16\000UQADD8\000UQASX\000UQSAX\000UQSUB16\000UQSUB8\000USAD8\000US"
- "ADA8\000USAT16\000USATasr\000USATlsl\000USAX\000USUB16\000USUB8\000UXTA"
- "B16rr\000UXTAB16rr_rot\000UXTABrr\000UXTABrr_rot\000UXTAHrr\000UXTAHrr_"
- "rot\000UXTB16r\000UXTB16r_rot\000UXTBr\000UXTBr_rot\000UXTHr\000UXTHr_r"
- "ot\000VABALsv2i64\000VABALsv4i32\000VABALsv8i16\000VABALuv2i64\000VABAL"
- "uv4i32\000VABALuv8i16\000VABAsv16i8\000VABAsv2i32\000VABAsv4i16\000VABA"
- "sv4i32\000VABAsv8i16\000VABAsv8i8\000VABAuv16i8\000VABAuv2i32\000VABAuv"
- "4i16\000VABAuv4i32\000VABAuv8i16\000VABAuv8i8\000VABDLsv2i64\000VABDLsv"
- "4i32\000VABDLsv8i16\000VABDLuv2i64\000VABDLuv4i32\000VABDLuv8i16\000VAB"
- "Dfd\000VABDfq\000VABDsv16i8\000VABDsv2i32\000VABDsv4i16\000VABDsv4i32\000"
- "VABDsv8i16\000VABDsv8i8\000VABDuv16i8\000VABDuv2i32\000VABDuv4i16\000VA"
- "BDuv4i32\000VABDuv8i16\000VABDuv8i8\000VABSD\000VABSS\000VABSfd\000VABS"
- "fd_sfp\000VABSfq\000VABSv16i8\000VABSv2i32\000VABSv4i16\000VABSv4i32\000"
- "VABSv8i16\000VABSv8i8\000VACGEd\000VACGEq\000VACGTd\000VACGTq\000VADDD\000"
- "VADDHNv2i32\000VADDHNv4i16\000VADDHNv8i8\000VADDLsv2i64\000VADDLsv4i32\000"
- "VADDLsv8i16\000VADDLuv2i64\000VADDLuv4i32\000VADDLuv8i16\000VADDS\000VA"
- "DDWsv2i64\000VADDWsv4i32\000VADDWsv8i16\000VADDWuv2i64\000VADDWuv4i32\000"
- "VADDWuv8i16\000VADDfd\000VADDfd_sfp\000VADDfq\000VADDv16i8\000VADDv1i64"
- "\000VADDv2i32\000VADDv2i64\000VADDv4i16\000VADDv4i32\000VADDv8i16\000VA"
- "DDv8i8\000VANDd\000VANDq\000VBICd\000VBICq\000VBIFd\000VBIFq\000VBITd\000"
- "VBITq\000VBSLd\000VBSLq\000VCEQfd\000VCEQfq\000VCEQv16i8\000VCEQv2i32\000"
- "VCEQv4i16\000VCEQv4i32\000VCEQv8i16\000VCEQv8i8\000VCEQzv16i8\000VCEQzv"
- "2f32\000VCEQzv2i32\000VCEQzv4f32\000VCEQzv4i16\000VCEQzv4i32\000VCEQzv8"
- "i16\000VCEQzv8i8\000VCGEfd\000VCGEfq\000VCGEsv16i8\000VCGEsv2i32\000VCG"
- "Esv4i16\000VCGEsv4i32\000VCGEsv8i16\000VCGEsv8i8\000VCGEuv16i8\000VCGEu"
- "v2i32\000VCGEuv4i16\000VCGEuv4i32\000VCGEuv8i16\000VCGEuv8i8\000VCGEzv1"
- "6i8\000VCGEzv2f32\000VCGEzv2i32\000VCGEzv4f32\000VCGEzv4i16\000VCGEzv4i"
- "32\000VCGEzv8i16\000VCGEzv8i8\000VCGTfd\000VCGTfq\000VCGTsv16i8\000VCGT"
- "sv2i32\000VCGTsv4i16\000VCGTsv4i32\000VCGTsv8i16\000VCGTsv8i8\000VCGTuv"
- "16i8\000VCGTuv2i32\000VCGTuv4i16\000VCGTuv4i32\000VCGTuv8i16\000VCGTuv8"
- "i8\000VCGTzv16i8\000VCGTzv2f32\000VCGTzv2i32\000VCGTzv4f32\000VCGTzv4i1"
- "6\000VCGTzv4i32\000VCGTzv8i16\000VCGTzv8i8\000VCLEzv16i8\000VCLEzv2f32\000"
- "VCLEzv2i32\000VCLEzv4f32\000VCLEzv4i16\000VCLEzv4i32\000VCLEzv8i16\000V"
- "CLEzv8i8\000VCLSv16i8\000VCLSv2i32\000VCLSv4i16\000VCLSv4i32\000VCLSv8i"
- "16\000VCLSv8i8\000VCLTzv16i8\000VCLTzv2f32\000VCLTzv2i32\000VCLTzv4f32\000"
- "VCLTzv4i16\000VCLTzv4i32\000VCLTzv8i16\000VCLTzv8i8\000VCLZv16i8\000VCL"
- "Zv2i32\000VCLZv4i16\000VCLZv4i32\000VCLZv8i16\000VCLZv8i8\000VCMPD\000V"
- "CMPED\000VCMPES\000VCMPEZD\000VCMPEZS\000VCMPS\000VCMPZD\000VCMPZS\000V"
- "CNTd\000VCNTq\000VCVTBHS\000VCVTBSH\000VCVTDS\000VCVTSD\000VCVTTHS\000V"
- "CVTTSH\000VCVTf2sd\000VCVTf2sd_sfp\000VCVTf2sq\000VCVTf2ud\000VCVTf2ud_"
- "sfp\000VCVTf2uq\000VCVTf2xsd\000VCVTf2xsq\000VCVTf2xud\000VCVTf2xuq\000"
- "VCVTs2fd\000VCVTs2fd_sfp\000VCVTs2fq\000VCVTu2fd\000VCVTu2fd_sfp\000VCV"
- "Tu2fq\000VCVTxs2fd\000VCVTxs2fq\000VCVTxu2fd\000VCVTxu2fq\000VDIVD\000V"
- "DIVS\000VDUP16d\000VDUP16q\000VDUP32d\000VDUP32q\000VDUP8d\000VDUP8q\000"
- "VDUPLN16d\000VDUPLN16q\000VDUPLN32d\000VDUPLN32q\000VDUPLN8d\000VDUPLN8"
- "q\000VDUPLNfd\000VDUPLNfq\000VDUPfd\000VDUPfdf\000VDUPfq\000VDUPfqf\000"
- "VEORd\000VEORq\000VEXTd16\000VEXTd32\000VEXTd8\000VEXTdf\000VEXTq16\000"
- "VEXTq32\000VEXTq8\000VEXTqf\000VGETLNi32\000VGETLNs16\000VGETLNs8\000VG"
- "ETLNu16\000VGETLNu8\000VHADDsv16i8\000VHADDsv2i32\000VHADDsv4i16\000VHA"
- "DDsv4i32\000VHADDsv8i16\000VHADDsv8i8\000VHADDuv16i8\000VHADDuv2i32\000"
- "VHADDuv4i16\000VHADDuv4i32\000VHADDuv8i16\000VHADDuv8i8\000VHSUBsv16i8\000"
- "VHSUBsv2i32\000VHSUBsv4i16\000VHSUBsv4i32\000VHSUBsv8i16\000VHSUBsv8i8\000"
- "VHSUBuv16i8\000VHSUBuv2i32\000VHSUBuv4i16\000VHSUBuv4i32\000VHSUBuv8i16"
- "\000VHSUBuv8i8\000VLD1d16\000VLD1d16Q\000VLD1d16T\000VLD1d32\000VLD1d32"
- "Q\000VLD1d32T\000VLD1d64\000VLD1d8\000VLD1d8Q\000VLD1d8T\000VLD1df\000V"
- "LD1q16\000VLD1q32\000VLD1q64\000VLD1q8\000VLD1qf\000VLD2LNd16\000VLD2LN"
- "d32\000VLD2LNd8\000VLD2LNq16a\000VLD2LNq16b\000VLD2LNq32a\000VLD2LNq32b"
- "\000VLD2d16\000VLD2d16D\000VLD2d32\000VLD2d32D\000VLD2d64\000VLD2d8\000"
- "VLD2d8D\000VLD2q16\000VLD2q32\000VLD2q8\000VLD3LNd16\000VLD3LNd32\000VL"
- "D3LNd8\000VLD3LNq16a\000VLD3LNq16b\000VLD3LNq32a\000VLD3LNq32b\000VLD3d"
- "16\000VLD3d32\000VLD3d64\000VLD3d8\000VLD3q16a\000VLD3q16b\000VLD3q32a\000"
- "VLD3q32b\000VLD3q8a\000VLD3q8b\000VLD4LNd16\000VLD4LNd32\000VLD4LNd8\000"
- "VLD4LNq16a\000VLD4LNq16b\000VLD4LNq32a\000VLD4LNq32b\000VLD4d16\000VLD4"
- "d32\000VLD4d64\000VLD4d8\000VLD4q16a\000VLD4q16b\000VLD4q32a\000VLD4q32"
- "b\000VLD4q8a\000VLD4q8b\000VLDMD\000VLDMS\000VLDRD\000VLDRQ\000VLDRS\000"
- "VMAXfd\000VMAXfd_sfp\000VMAXfq\000VMAXsv16i8\000VMAXsv2i32\000VMAXsv4i1"
- "6\000VMAXsv4i32\000VMAXsv8i16\000VMAXsv8i8\000VMAXuv16i8\000VMAXuv2i32\000"
- "VMAXuv4i16\000VMAXuv4i32\000VMAXuv8i16\000VMAXuv8i8\000VMINfd\000VMINfd"
- "_sfp\000VMINfq\000VMINsv16i8\000VMINsv2i32\000VMINsv4i16\000VMINsv4i32\000"
- "VMINsv8i16\000VMINsv8i8\000VMINuv16i8\000VMINuv2i32\000VMINuv4i16\000VM"
- "INuv4i32\000VMINuv8i16\000VMINuv8i8\000VMLAD\000VMLALslsv2i32\000VMLALs"
- "lsv4i16\000VMLALsluv2i32\000VMLALsluv4i16\000VMLALsv2i64\000VMLALsv4i32"
- "\000VMLALsv8i16\000VMLALuv2i64\000VMLALuv4i32\000VMLALuv8i16\000VMLAS\000"
- "VMLAfd\000VMLAfq\000VMLAslfd\000VMLAslfq\000VMLAslv2i32\000VMLAslv4i16\000"
- "VMLAslv4i32\000VMLAslv8i16\000VMLAv16i8\000VMLAv2i32\000VMLAv4i16\000VM"
- "LAv4i32\000VMLAv8i16\000VMLAv8i8\000VMLSD\000VMLSLslsv2i32\000VMLSLslsv"
- "4i16\000VMLSLsluv2i32\000VMLSLsluv4i16\000VMLSLsv2i64\000VMLSLsv4i32\000"
- "VMLSLsv8i16\000VMLSLuv2i64\000VMLSLuv4i32\000VMLSLuv8i16\000VMLSS\000VM"
- "LSfd\000VMLSfq\000VMLSslfd\000VMLSslfq\000VMLSslv2i32\000VMLSslv4i16\000"
- "VMLSslv4i32\000VMLSslv8i16\000VMLSv16i8\000VMLSv2i32\000VMLSv4i16\000VM"
- "LSv4i32\000VMLSv8i16\000VMLSv8i8\000VMOVD\000VMOVDRR\000VMOVDcc\000VMOV"
- "Dneon\000VMOVLsv2i64\000VMOVLsv4i32\000VMOVLsv8i16\000VMOVLuv2i64\000VM"
- "OVLuv4i32\000VMOVLuv8i16\000VMOVNv2i32\000VMOVNv4i16\000VMOVNv8i8\000VM"
- "OVQ\000VMOVRRD\000VMOVRRS\000VMOVRS\000VMOVS\000VMOVSR\000VMOVSRR\000VM"
- "OVScc\000VMOVv16i8\000VMOVv1i64\000VMOVv2i32\000VMOVv2i64\000VMOVv4i16\000"
- "VMOVv4i32\000VMOVv8i16\000VMOVv8i8\000VMRS\000VMSR\000VMULD\000VMULLp\000"
- "VMULLslsv2i32\000VMULLslsv4i16\000VMULLsluv2i32\000VMULLsluv4i16\000VMU"
- "LLsv2i64\000VMULLsv4i32\000VMULLsv8i16\000VMULLuv2i64\000VMULLuv4i32\000"
- "VMULLuv8i16\000VMULS\000VMULfd\000VMULfd_sfp\000VMULfq\000VMULpd\000VMU"
- "Lpq\000VMULslfd\000VMULslfq\000VMULslv2i32\000VMULslv4i16\000VMULslv4i3"
- "2\000VMULslv8i16\000VMULv16i8\000VMULv2i32\000VMULv4i16\000VMULv4i32\000"
- "VMULv8i16\000VMULv8i8\000VMVNd\000VMVNq\000VNEGD\000VNEGDcc\000VNEGS\000"
- "VNEGScc\000VNEGf32q\000VNEGfd\000VNEGfd_sfp\000VNEGs16d\000VNEGs16q\000"
- "VNEGs32d\000VNEGs32q\000VNEGs8d\000VNEGs8q\000VNMLAD\000VNMLAS\000VNMLS"
- "D\000VNMLSS\000VNMULD\000VNMULS\000VORNd\000VORNq\000VORRd\000VORRq\000"
- "VPADALsv16i8\000VPADALsv2i32\000VPADALsv4i16\000VPADALsv4i32\000VPADALs"
- "v8i16\000VPADALsv8i8\000VPADALuv16i8\000VPADALuv2i32\000VPADALuv4i16\000"
- "VPADALuv4i32\000VPADALuv8i16\000VPADALuv8i8\000VPADDLsv16i8\000VPADDLsv"
- "2i32\000VPADDLsv4i16\000VPADDLsv4i32\000VPADDLsv8i16\000VPADDLsv8i8\000"
- "VPADDLuv16i8\000VPADDLuv2i32\000VPADDLuv4i16\000VPADDLuv4i32\000VPADDLu"
- "v8i16\000VPADDLuv8i8\000VPADDf\000VPADDi16\000VPADDi32\000VPADDi8\000VP"
- "MAXf\000VPMAXs16\000VPMAXs32\000VPMAXs8\000VPMAXu16\000VPMAXu32\000VPMA"
- "Xu8\000VPMINf\000VPMINs16\000VPMINs32\000VPMINs8\000VPMINu16\000VPMINu3"
- "2\000VPMINu8\000VQABSv16i8\000VQABSv2i32\000VQABSv4i16\000VQABSv4i32\000"
- "VQABSv8i16\000VQABSv8i8\000VQADDsv16i8\000VQADDsv1i64\000VQADDsv2i32\000"
- "VQADDsv2i64\000VQADDsv4i16\000VQADDsv4i32\000VQADDsv8i16\000VQADDsv8i8\000"
- "VQADDuv16i8\000VQADDuv1i64\000VQADDuv2i32\000VQADDuv2i64\000VQADDuv4i16"
- "\000VQADDuv4i32\000VQADDuv8i16\000VQADDuv8i8\000VQDMLALslv2i32\000VQDML"
- "ALslv4i16\000VQDMLALv2i64\000VQDMLALv4i32\000VQDMLSLslv2i32\000VQDMLSLs"
- "lv4i16\000VQDMLSLv2i64\000VQDMLSLv4i32\000VQDMULHslv2i32\000VQDMULHslv4"
- "i16\000VQDMULHslv4i32\000VQDMULHslv8i16\000VQDMULHv2i32\000VQDMULHv4i16"
- "\000VQDMULHv4i32\000VQDMULHv8i16\000VQDMULLslv2i32\000VQDMULLslv4i16\000"
- "VQDMULLv2i64\000VQDMULLv4i32\000VQMOVNsuv2i32\000VQMOVNsuv4i16\000VQMOV"
- "Nsuv8i8\000VQMOVNsv2i32\000VQMOVNsv4i16\000VQMOVNsv8i8\000VQMOVNuv2i32\000"
- "VQMOVNuv4i16\000VQMOVNuv8i8\000VQNEGv16i8\000VQNEGv2i32\000VQNEGv4i16\000"
- "VQNEGv4i32\000VQNEGv8i16\000VQNEGv8i8\000VQRDMULHslv2i32\000VQRDMULHslv"
- "4i16\000VQRDMULHslv4i32\000VQRDMULHslv8i16\000VQRDMULHv2i32\000VQRDMULH"
- "v4i16\000VQRDMULHv4i32\000VQRDMULHv8i16\000VQRSHLsv16i8\000VQRSHLsv1i64"
- "\000VQRSHLsv2i32\000VQRSHLsv2i64\000VQRSHLsv4i16\000VQRSHLsv4i32\000VQR"
- "SHLsv8i16\000VQRSHLsv8i8\000VQRSHLuv16i8\000VQRSHLuv1i64\000VQRSHLuv2i3"
- "2\000VQRSHLuv2i64\000VQRSHLuv4i16\000VQRSHLuv4i32\000VQRSHLuv8i16\000VQ"
- "RSHLuv8i8\000VQRSHRNsv2i32\000VQRSHRNsv4i16\000VQRSHRNsv8i8\000VQRSHRNu"
- "v2i32\000VQRSHRNuv4i16\000VQRSHRNuv8i8\000VQRSHRUNv2i32\000VQRSHRUNv4i1"
- "6\000VQRSHRUNv8i8\000VQSHLsiv16i8\000VQSHLsiv1i64\000VQSHLsiv2i32\000VQ"
- "SHLsiv2i64\000VQSHLsiv4i16\000VQSHLsiv4i32\000VQSHLsiv8i16\000VQSHLsiv8"
- "i8\000VQSHLsuv16i8\000VQSHLsuv1i64\000VQSHLsuv2i32\000VQSHLsuv2i64\000V"
- "QSHLsuv4i16\000VQSHLsuv4i32\000VQSHLsuv8i16\000VQSHLsuv8i8\000VQSHLsv16"
- "i8\000VQSHLsv1i64\000VQSHLsv2i32\000VQSHLsv2i64\000VQSHLsv4i16\000VQSHL"
- "sv4i32\000VQSHLsv8i16\000VQSHLsv8i8\000VQSHLuiv16i8\000VQSHLuiv1i64\000"
- "VQSHLuiv2i32\000VQSHLuiv2i64\000VQSHLuiv4i16\000VQSHLuiv4i32\000VQSHLui"
- "v8i16\000VQSHLuiv8i8\000VQSHLuv16i8\000VQSHLuv1i64\000VQSHLuv2i32\000VQ"
- "SHLuv2i64\000VQSHLuv4i16\000VQSHLuv4i32\000VQSHLuv8i16\000VQSHLuv8i8\000"
- "VQSHRNsv2i32\000VQSHRNsv4i16\000VQSHRNsv8i8\000VQSHRNuv2i32\000VQSHRNuv"
- "4i16\000VQSHRNuv8i8\000VQSHRUNv2i32\000VQSHRUNv4i16\000VQSHRUNv8i8\000V"
- "QSUBsv16i8\000VQSUBsv1i64\000VQSUBsv2i32\000VQSUBsv2i64\000VQSUBsv4i16\000"
- "VQSUBsv4i32\000VQSUBsv8i16\000VQSUBsv8i8\000VQSUBuv16i8\000VQSUBuv1i64\000"
- "VQSUBuv2i32\000VQSUBuv2i64\000VQSUBuv4i16\000VQSUBuv4i32\000VQSUBuv8i16"
- "\000VQSUBuv8i8\000VRADDHNv2i32\000VRADDHNv4i16\000VRADDHNv8i8\000VRECPE"
- "d\000VRECPEfd\000VRECPEfq\000VRECPEq\000VRECPSfd\000VRECPSfq\000VREV16d"
- "8\000VREV16q8\000VREV32d16\000VREV32d8\000VREV32q16\000VREV32q8\000VREV"
- "64d16\000VREV64d32\000VREV64d8\000VREV64df\000VREV64q16\000VREV64q32\000"
- "VREV64q8\000VREV64qf\000VRHADDsv16i8\000VRHADDsv2i32\000VRHADDsv4i16\000"
- "VRHADDsv4i32\000VRHADDsv8i16\000VRHADDsv8i8\000VRHADDuv16i8\000VRHADDuv"
- "2i32\000VRHADDuv4i16\000VRHADDuv4i32\000VRHADDuv8i16\000VRHADDuv8i8\000"
- "VRSHLsv16i8\000VRSHLsv1i64\000VRSHLsv2i32\000VRSHLsv2i64\000VRSHLsv4i16"
- "\000VRSHLsv4i32\000VRSHLsv8i16\000VRSHLsv8i8\000VRSHLuv16i8\000VRSHLuv1"
- "i64\000VRSHLuv2i32\000VRSHLuv2i64\000VRSHLuv4i16\000VRSHLuv4i32\000VRSH"
- "Luv8i16\000VRSHLuv8i8\000VRSHRNv2i32\000VRSHRNv4i16\000VRSHRNv8i8\000VR"
- "SHRsv16i8\000VRSHRsv1i64\000VRSHRsv2i32\000VRSHRsv2i64\000VRSHRsv4i16\000"
- "VRSHRsv4i32\000VRSHRsv8i16\000VRSHRsv8i8\000VRSHRuv16i8\000VRSHRuv1i64\000"
- "VRSHRuv2i32\000VRSHRuv2i64\000VRSHRuv4i16\000VRSHRuv4i32\000VRSHRuv8i16"
- "\000VRSHRuv8i8\000VRSQRTEd\000VRSQRTEfd\000VRSQRTEfq\000VRSQRTEq\000VRS"
- "QRTSfd\000VRSQRTSfq\000VRSRAsv16i8\000VRSRAsv1i64\000VRSRAsv2i32\000VRS"
- "RAsv2i64\000VRSRAsv4i16\000VRSRAsv4i32\000VRSRAsv8i16\000VRSRAsv8i8\000"
- "VRSRAuv16i8\000VRSRAuv1i64\000VRSRAuv2i32\000VRSRAuv2i64\000VRSRAuv4i16"
- "\000VRSRAuv4i32\000VRSRAuv8i16\000VRSRAuv8i8\000VRSUBHNv2i32\000VRSUBHN"
- "v4i16\000VRSUBHNv8i8\000VSETLNi16\000VSETLNi32\000VSETLNi8\000VSHLLi16\000"
- "VSHLLi32\000VSHLLi8\000VSHLLsv2i64\000VSHLLsv4i32\000VSHLLsv8i16\000VSH"
- "LLuv2i64\000VSHLLuv4i32\000VSHLLuv8i16\000VSHLiv16i8\000VSHLiv1i64\000V"
- "SHLiv2i32\000VSHLiv2i64\000VSHLiv4i16\000VSHLiv4i32\000VSHLiv8i16\000VS"
- "HLiv8i8\000VSHLsv16i8\000VSHLsv1i64\000VSHLsv2i32\000VSHLsv2i64\000VSHL"
- "sv4i16\000VSHLsv4i32\000VSHLsv8i16\000VSHLsv8i8\000VSHLuv16i8\000VSHLuv"
- "1i64\000VSHLuv2i32\000VSHLuv2i64\000VSHLuv4i16\000VSHLuv4i32\000VSHLuv8"
- "i16\000VSHLuv8i8\000VSHRNv2i32\000VSHRNv4i16\000VSHRNv8i8\000VSHRsv16i8"
- "\000VSHRsv1i64\000VSHRsv2i32\000VSHRsv2i64\000VSHRsv4i16\000VSHRsv4i32\000"
- "VSHRsv8i16\000VSHRsv8i8\000VSHRuv16i8\000VSHRuv1i64\000VSHRuv2i32\000VS"
- "HRuv2i64\000VSHRuv4i16\000VSHRuv4i32\000VSHRuv8i16\000VSHRuv8i8\000VSHT"
- "OD\000VSHTOS\000VSITOD\000VSITOS\000VSLIv16i8\000VSLIv1i64\000VSLIv2i32"
- "\000VSLIv2i64\000VSLIv4i16\000VSLIv4i32\000VSLIv8i16\000VSLIv8i8\000VSL"
- "TOD\000VSLTOS\000VSQRTD\000VSQRTS\000VSRAsv16i8\000VSRAsv1i64\000VSRAsv"
- "2i32\000VSRAsv2i64\000VSRAsv4i16\000VSRAsv4i32\000VSRAsv8i16\000VSRAsv8"
- "i8\000VSRAuv16i8\000VSRAuv1i64\000VSRAuv2i32\000VSRAuv2i64\000VSRAuv4i1"
- "6\000VSRAuv4i32\000VSRAuv8i16\000VSRAuv8i8\000VSRIv16i8\000VSRIv1i64\000"
- "VSRIv2i32\000VSRIv2i64\000VSRIv4i16\000VSRIv4i32\000VSRIv8i16\000VSRIv8"
- "i8\000VST1d16\000VST1d16Q\000VST1d16T\000VST1d32\000VST1d32Q\000VST1d32"
- "T\000VST1d64\000VST1d8\000VST1d8Q\000VST1d8T\000VST1df\000VST1q16\000VS"
- "T1q32\000VST1q64\000VST1q8\000VST1qf\000VST2LNd16\000VST2LNd32\000VST2L"
- "Nd8\000VST2LNq16a\000VST2LNq16b\000VST2LNq32a\000VST2LNq32b\000VST2d16\000"
- "VST2d16D\000VST2d32\000VST2d32D\000VST2d64\000VST2d8\000VST2d8D\000VST2"
- "q16\000VST2q32\000VST2q8\000VST3LNd16\000VST3LNd32\000VST3LNd8\000VST3L"
- "Nq16a\000VST3LNq16b\000VST3LNq32a\000VST3LNq32b\000VST3d16\000VST3d32\000"
- "VST3d64\000VST3d8\000VST3q16a\000VST3q16b\000VST3q32a\000VST3q32b\000VS"
- "T3q8a\000VST3q8b\000VST4LNd16\000VST4LNd32\000VST4LNd8\000VST4LNq16a\000"
- "VST4LNq16b\000VST4LNq32a\000VST4LNq32b\000VST4d16\000VST4d32\000VST4d64"
- "\000VST4d8\000VST4q16a\000VST4q16b\000VST4q32a\000VST4q32b\000VST4q8a\000"
- "VST4q8b\000VSTMD\000VSTMS\000VSTRD\000VSTRQ\000VSTRS\000VSUBD\000VSUBHN"
- "v2i32\000VSUBHNv4i16\000VSUBHNv8i8\000VSUBLsv2i64\000VSUBLsv4i32\000VSU"
- "BLsv8i16\000VSUBLuv2i64\000VSUBLuv4i32\000VSUBLuv8i16\000VSUBS\000VSUBW"
- "sv2i64\000VSUBWsv4i32\000VSUBWsv8i16\000VSUBWuv2i64\000VSUBWuv4i32\000V"
- "SUBWuv8i16\000VSUBfd\000VSUBfd_sfp\000VSUBfq\000VSUBv16i8\000VSUBv1i64\000"
- "VSUBv2i32\000VSUBv2i64\000VSUBv4i16\000VSUBv4i32\000VSUBv8i16\000VSUBv8"
- "i8\000VSWPd\000VSWPq\000VTBL1\000VTBL2\000VTBL3\000VTBL4\000VTBX1\000VT"
- "BX2\000VTBX3\000VTBX4\000VTOSHD\000VTOSHS\000VTOSIRD\000VTOSIRS\000VTOS"
- "IZD\000VTOSIZS\000VTOSLD\000VTOSLS\000VTOUHD\000VTOUHS\000VTOUIRD\000VT"
- "OUIRS\000VTOUIZD\000VTOUIZS\000VTOULD\000VTOULS\000VTRNd16\000VTRNd32\000"
- "VTRNd8\000VTRNq16\000VTRNq32\000VTRNq8\000VTSTv16i8\000VTSTv2i32\000VTS"
- "Tv4i16\000VTSTv4i32\000VTSTv8i16\000VTSTv8i8\000VUHTOD\000VUHTOS\000VUI"
- "TOD\000VUITOS\000VULTOD\000VULTOS\000VUZPd16\000VUZPd32\000VUZPd8\000VU"
- "ZPq16\000VUZPq32\000VUZPq8\000VZIPd16\000VZIPd32\000VZIPd8\000VZIPq16\000"
- "VZIPq32\000VZIPq8\000WFE\000WFI\000YIELD\000t2ADCSri\000t2ADCSrr\000t2A"
- "DCSrs\000t2ADCri\000t2ADCrr\000t2ADCrs\000t2ADDSri\000t2ADDSrr\000t2ADD"
- "Srs\000t2ADDrSPi\000t2ADDrSPi12\000t2ADDrSPs\000t2ADDri\000t2ADDri12\000"
- "t2ADDrr\000t2ADDrs\000t2ANDri\000t2ANDrr\000t2ANDrs\000t2ASRri\000t2ASR"
- "rr\000t2B\000t2BFC\000t2BFI\000t2BICri\000t2BICrr\000t2BICrs\000t2BR_JT"
- "\000t2BXJ\000t2Bcc\000t2CLREX\000t2CLZ\000t2CMNzri\000t2CMNzrr\000t2CMN"
- "zrs\000t2CMPri\000t2CMPrr\000t2CMPrs\000t2CMPzri\000t2CMPzrr\000t2CMPzr"
- "s\000t2CPS\000t2DBG\000t2DMBish\000t2DMBishst\000t2DMBnsh\000t2DMBnshst"
- "\000t2DMBosh\000t2DMBoshst\000t2DMBst\000t2DSBish\000t2DSBishst\000t2DS"
- "Bnsh\000t2DSBnshst\000t2DSBosh\000t2DSBoshst\000t2DSBst\000t2EORri\000t"
- "2EORrr\000t2EORrs\000t2ISBsy\000t2IT\000t2Int_MemBarrierV7\000t2Int_Syn"
- "cBarrierV7\000t2Int_eh_sjlj_setjmp\000t2LDM\000t2LDM_RET\000t2LDRBT\000"
- "t2LDRB_POST\000t2LDRB_PRE\000t2LDRBi12\000t2LDRBi8\000t2LDRBpci\000t2LD"
- "RBs\000t2LDRDi8\000t2LDRDpci\000t2LDREX\000t2LDREXB\000t2LDREXD\000t2LD"
- "REXH\000t2LDRHT\000t2LDRH_POST\000t2LDRH_PRE\000t2LDRHi12\000t2LDRHi8\000"
- "t2LDRHpci\000t2LDRHs\000t2LDRSBT\000t2LDRSB_POST\000t2LDRSB_PRE\000t2LD"
- "RSBi12\000t2LDRSBi8\000t2LDRSBpci\000t2LDRSBs\000t2LDRSHT\000t2LDRSH_PO"
- "ST\000t2LDRSH_PRE\000t2LDRSHi12\000t2LDRSHi8\000t2LDRSHpci\000t2LDRSHs\000"
- "t2LDRT\000t2LDR_POST\000t2LDR_PRE\000t2LDRi12\000t2LDRi8\000t2LDRpci\000"
- "t2LDRpci_pic\000t2LDRs\000t2LEApcrel\000t2LEApcrelJT\000t2LSLri\000t2LS"
- "Lrr\000t2LSRri\000t2LSRrr\000t2MLA\000t2MLS\000t2MOVCCasr\000t2MOVCCi\000"
- "t2MOVCClsl\000t2MOVCClsr\000t2MOVCCr\000t2MOVCCror\000t2MOVTi16\000t2MO"
- "Vi\000t2MOVi16\000t2MOVi32imm\000t2MOVr\000t2MOVrx\000t2MOVsra_flag\000"
- "t2MOVsrl_flag\000t2MRS\000t2MRSsys\000t2MSR\000t2MSRsys\000t2MUL\000t2M"
- "VNi\000t2MVNr\000t2MVNs\000t2NOP\000t2ORNri\000t2ORNrr\000t2ORNrs\000t2"
- "ORRri\000t2ORRrr\000t2ORRrs\000t2PKHBT\000t2PKHTB\000t2PLDWi12\000t2PLD"
- "Wi8\000t2PLDWpci\000t2PLDWr\000t2PLDWs\000t2PLDi12\000t2PLDi8\000t2PLDp"
- "ci\000t2PLDr\000t2PLDs\000t2PLIi12\000t2PLIi8\000t2PLIpci\000t2PLIr\000"
- "t2PLIs\000t2QADD\000t2QADD16\000t2QADD8\000t2QASX\000t2QDADD\000t2QDSUB"
- "\000t2QSAX\000t2QSUB\000t2QSUB16\000t2QSUB8\000t2RBIT\000t2REV\000t2REV"
- "16\000t2REVSH\000t2RFEDB\000t2RFEDBW\000t2RFEIA\000t2RFEIAW\000t2RORri\000"
- "t2RORrr\000t2RSBSri\000t2RSBSrs\000t2RSBri\000t2RSBrs\000t2SADD16\000t2"
- "SADD8\000t2SASX\000t2SBCSri\000t2SBCSrr\000t2SBCSrs\000t2SBCri\000t2SBC"
- "rr\000t2SBCrs\000t2SBFX\000t2SDIV\000t2SEL\000t2SEV\000t2SHADD16\000t2S"
- "HADD8\000t2SHASX\000t2SHSAX\000t2SHSUB16\000t2SHSUB8\000t2SMC\000t2SMLA"
- "BB\000t2SMLABT\000t2SMLAD\000t2SMLADX\000t2SMLAL\000t2SMLALBB\000t2SMLA"
- "LBT\000t2SMLALD\000t2SMLALDX\000t2SMLALTB\000t2SMLALTT\000t2SMLATB\000t"
- "2SMLATT\000t2SMLAWB\000t2SMLAWT\000t2SMLSD\000t2SMLSDX\000t2SMLSLD\000t"
- "2SMLSLDX\000t2SMMLA\000t2SMMLAR\000t2SMMLS\000t2SMMLSR\000t2SMMUL\000t2"
- "SMMULR\000t2SMUAD\000t2SMUADX\000t2SMULBB\000t2SMULBT\000t2SMULL\000t2S"
- "MULTB\000t2SMULTT\000t2SMULWB\000t2SMULWT\000t2SMUSD\000t2SMUSDX\000t2S"
- "RSDB\000t2SRSDBW\000t2SRSIA\000t2SRSIAW\000t2SSAT16\000t2SSATasr\000t2S"
- "SATlsl\000t2SSAX\000t2SSUB16\000t2SSUB8\000t2STM\000t2STRBT\000t2STRB_P"
- "OST\000t2STRB_PRE\000t2STRBi12\000t2STRBi8\000t2STRBs\000t2STRDi8\000t2"
- "STREX\000t2STREXB\000t2STREXD\000t2STREXH\000t2STRHT\000t2STRH_POST\000"
- "t2STRH_PRE\000t2STRHi12\000t2STRHi8\000t2STRHs\000t2STRT\000t2STR_POST\000"
- "t2STR_PRE\000t2STRi12\000t2STRi8\000t2STRs\000t2SUBSri\000t2SUBSrr\000t"
- "2SUBSrs\000t2SUBrSPi\000t2SUBrSPi12\000t2SUBrSPi12_\000t2SUBrSPi_\000t2"
- "SUBrSPs\000t2SUBrSPs_\000t2SUBri\000t2SUBri12\000t2SUBrr\000t2SUBrs\000"
- "t2SXTAB16rr\000t2SXTAB16rr_rot\000t2SXTABrr\000t2SXTABrr_rot\000t2SXTAH"
- "rr\000t2SXTAHrr_rot\000t2SXTB16r\000t2SXTB16r_rot\000t2SXTBr\000t2SXTBr"
- "_rot\000t2SXTHr\000t2SXTHr_rot\000t2TBB\000t2TBBgen\000t2TBH\000t2TBHge"
- "n\000t2TEQri\000t2TEQrr\000t2TEQrs\000t2TPsoft\000t2TSTri\000t2TSTrr\000"
- "t2TSTrs\000t2UADD16\000t2UADD8\000t2UASX\000t2UBFX\000t2UDIV\000t2UHADD"
- "16\000t2UHADD8\000t2UHASX\000t2UHSAX\000t2UHSUB16\000t2UHSUB8\000t2UMAA"
- "L\000t2UMLAL\000t2UMULL\000t2UQADD16\000t2UQADD8\000t2UQASX\000t2UQSAX\000"
- "t2UQSUB16\000t2UQSUB8\000t2USAD8\000t2USADA8\000t2USAT16\000t2USATasr\000"
- "t2USATlsl\000t2USAX\000t2USUB16\000t2USUB8\000t2UXTAB16rr\000t2UXTAB16r"
- "r_rot\000t2UXTABrr\000t2UXTABrr_rot\000t2UXTAHrr\000t2UXTAHrr_rot\000t2"
- "UXTB16r\000t2UXTB16r_rot\000t2UXTBr\000t2UXTBr_rot\000t2UXTHr\000t2UXTH"
- "r_rot\000t2WFE\000t2WFI\000t2YIELD\000tADC\000tADDhirr\000tADDi3\000tAD"
- "Di8\000tADDrPCi\000tADDrSP\000tADDrSPi\000tADDrr\000tADDspi\000tADDspr\000"
- "tADDspr_\000tADJCALLSTACKDOWN\000tADJCALLSTACKUP\000tAND\000tANDsp\000t"
- "ASRri\000tASRrr\000tB\000tBIC\000tBKPT\000tBL\000tBLXi\000tBLXi_r9\000t"
- "BLXr\000tBLXr_r9\000tBLr9\000tBRIND\000tBR_JTr\000tBX\000tBX_RET\000tBX"
- "_RET_vararg\000tBXr9\000tBcc\000tBfar\000tCBNZ\000tCBZ\000tCMNz\000tCMP"
- "hir\000tCMPi8\000tCMPr\000tCMPzhir\000tCMPzi8\000tCMPzr\000tCPS\000tEOR"
- "\000tInt_eh_sjlj_setjmp\000tLDM\000tLDR\000tLDRB\000tLDRBi\000tLDRH\000"
- "tLDRHi\000tLDRSB\000tLDRSH\000tLDRcp\000tLDRi\000tLDRpci\000tLDRpci_pic"
- "\000tLDRspi\000tLEApcrel\000tLEApcrelJT\000tLSLri\000tLSLrr\000tLSRri\000"
- "tLSRrr\000tMOVCCi\000tMOVCCr\000tMOVCCr_pseudo\000tMOVSr\000tMOVgpr2gpr"
- "\000tMOVgpr2tgpr\000tMOVi8\000tMOVr\000tMOVtgpr2gpr\000tMUL\000tMVN\000"
- "tNOP\000tORR\000tPICADD\000tPOP\000tPOP_RET\000tPUSH\000tREV\000tREV16\000"
- "tREVSH\000tROR\000tRSB\000tRestore\000tSBC\000tSETENDBE\000tSETENDLE\000"
- "tSEV\000tSTM\000tSTR\000tSTRB\000tSTRBi\000tSTRH\000tSTRHi\000tSTRi\000"
- "tSTRspi\000tSUBi3\000tSUBi8\000tSUBrr\000tSUBspi\000tSUBspi_\000tSVC\000"
- "tSXTB\000tSXTH\000tSpill\000tTPsoft\000tTRAP\000tTST\000tUXTB\000tUXTH\000"
- "tWFE\000tWFI\000tYIELD\000";
+ "BKPT\000BL\000BLX\000BLXr9\000BL_pred\000BLr9\000BLr9_pred\000BMOVPCRX\000"
+ "BMOVPCRXr9\000BRIND\000BR_JTadd\000BR_JTm\000BR_JTr\000BX\000BXJ\000BX_"
+ "RET\000BXr9\000Bcc\000CDP\000CDP2\000CLREX\000CLZ\000CMNzri\000CMNzrr\000"
+ "CMNzrs\000CMPri\000CMPrr\000CMPrs\000CMPzri\000CMPzrr\000CMPzrs\000CONS"
+ "TPOOL_ENTRY\000CPS\000DBG\000DMBish\000DMBishst\000DMBnsh\000DMBnshst\000"
+ "DMBosh\000DMBoshst\000DMBst\000DSBish\000DSBishst\000DSBnsh\000DSBnshst"
+ "\000DSBosh\000DSBoshst\000DSBst\000EORri\000EORrr\000EORrs\000FCONSTD\000"
+ "FCONSTS\000FMSTAT\000ISBsy\000Int_MemBarrierV6\000Int_MemBarrierV7\000I"
+ "nt_SyncBarrierV6\000Int_SyncBarrierV7\000Int_eh_sjlj_setjmp\000LDC2L_OF"
+ "FSET\000LDC2L_OPTION\000LDC2L_POST\000LDC2L_PRE\000LDC2_OFFSET\000LDC2_"
+ "OPTION\000LDC2_POST\000LDC2_PRE\000LDCL_OFFSET\000LDCL_OPTION\000LDCL_P"
+ "OST\000LDCL_PRE\000LDC_OFFSET\000LDC_OPTION\000LDC_POST\000LDC_PRE\000L"
+ "DM\000LDM_RET\000LDR\000LDRB\000LDRBT\000LDRB_POST\000LDRB_PRE\000LDRD\000"
+ "LDRD_POST\000LDRD_PRE\000LDREX\000LDREXB\000LDREXD\000LDREXH\000LDRH\000"
+ "LDRHT\000LDRH_POST\000LDRH_PRE\000LDRSB\000LDRSBT\000LDRSB_POST\000LDRS"
+ "B_PRE\000LDRSH\000LDRSHT\000LDRSH_POST\000LDRSH_PRE\000LDRT\000LDR_POST"
+ "\000LDR_PRE\000LDRcp\000LEApcrel\000LEApcrelJT\000MCR\000MCR2\000MCRR\000"
+ "MCRR2\000MLA\000MLS\000MOVCCi\000MOVCCr\000MOVCCs\000MOVPCLR\000MOVPCRX"
+ "\000MOVTi16\000MOVi\000MOVi16\000MOVi2pieces\000MOVi32imm\000MOVr\000MO"
+ "Vrx\000MOVs\000MOVsra_flag\000MOVsrl_flag\000MRC\000MRC2\000MRRC\000MRR"
+ "C2\000MRS\000MRSsys\000MSR\000MSRi\000MSRsys\000MSRsysi\000MUL\000MVNi\000"
+ "MVNr\000MVNs\000NOP\000ORRri\000ORRrr\000ORRrs\000PICADD\000PICLDR\000P"
+ "ICLDRB\000PICLDRH\000PICLDRSB\000PICLDRSH\000PICSTR\000PICSTRB\000PICST"
+ "RH\000PKHBT\000PKHTB\000PLDWi\000PLDWr\000PLDi\000PLDr\000PLIi\000PLIr\000"
+ "QADD\000QADD16\000QADD8\000QASX\000QDADD\000QDSUB\000QSAX\000QSUB\000QS"
+ "UB16\000QSUB8\000RBIT\000REV\000REV16\000REVSH\000RFE\000RFEW\000RSBSri"
+ "\000RSBSrs\000RSBri\000RSBrs\000RSCSri\000RSCSrs\000RSCri\000RSCrs\000S"
+ "ADD16\000SADD8\000SASX\000SBCSSri\000SBCSSrr\000SBCSSrs\000SBCri\000SBC"
+ "rr\000SBCrs\000SBFX\000SEL\000SETENDBE\000SETENDLE\000SEV\000SHADD16\000"
+ "SHADD8\000SHASX\000SHSAX\000SHSUB16\000SHSUB8\000SMC\000SMLABB\000SMLAB"
+ "T\000SMLAD\000SMLADX\000SMLAL\000SMLALBB\000SMLALBT\000SMLALD\000SMLALD"
+ "X\000SMLALTB\000SMLALTT\000SMLATB\000SMLATT\000SMLAWB\000SMLAWT\000SMLS"
+ "D\000SMLSDX\000SMLSLD\000SMLSLDX\000SMMLA\000SMMLAR\000SMMLS\000SMMLSR\000"
+ "SMMUL\000SMMULR\000SMUAD\000SMUADX\000SMULBB\000SMULBT\000SMULL\000SMUL"
+ "TB\000SMULTT\000SMULWB\000SMULWT\000SMUSD\000SMUSDX\000SRS\000SRSW\000S"
+ "SAT16\000SSATasr\000SSATlsl\000SSAX\000SSUB16\000SSUB8\000STC2L_OFFSET\000"
+ "STC2L_OPTION\000STC2L_POST\000STC2L_PRE\000STC2_OFFSET\000STC2_OPTION\000"
+ "STC2_POST\000STC2_PRE\000STCL_OFFSET\000STCL_OPTION\000STCL_POST\000STC"
+ "L_PRE\000STC_OFFSET\000STC_OPTION\000STC_POST\000STC_PRE\000STM\000STR\000"
+ "STRB\000STRBT\000STRB_POST\000STRB_PRE\000STRD\000STRD_POST\000STRD_PRE"
+ "\000STREX\000STREXB\000STREXD\000STREXH\000STRH\000STRHT\000STRH_POST\000"
+ "STRH_PRE\000STRT\000STR_POST\000STR_PRE\000SUBSri\000SUBSrr\000SUBSrs\000"
+ "SUBri\000SUBrr\000SUBrs\000SVC\000SWP\000SWPB\000SXTAB16rr\000SXTAB16rr"
+ "_rot\000SXTABrr\000SXTABrr_rot\000SXTAHrr\000SXTAHrr_rot\000SXTB16r\000"
+ "SXTB16r_rot\000SXTBr\000SXTBr_rot\000SXTHr\000SXTHr_rot\000TEQri\000TEQ"
+ "rr\000TEQrs\000TPsoft\000TRAP\000TSTri\000TSTrr\000TSTrs\000UADD16\000U"
+ "ADD8\000UASX\000UBFX\000UHADD16\000UHADD8\000UHASX\000UHSAX\000UHSUB16\000"
+ "UHSUB8\000UMAAL\000UMLAL\000UMULL\000UQADD16\000UQADD8\000UQASX\000UQSA"
+ "X\000UQSUB16\000UQSUB8\000USAD8\000USADA8\000USAT16\000USATasr\000USATl"
+ "sl\000USAX\000USUB16\000USUB8\000UXTAB16rr\000UXTAB16rr_rot\000UXTABrr\000"
+ "UXTABrr_rot\000UXTAHrr\000UXTAHrr_rot\000UXTB16r\000UXTB16r_rot\000UXTB"
+ "r\000UXTBr_rot\000UXTHr\000UXTHr_rot\000VABALsv2i64\000VABALsv4i32\000V"
+ "ABALsv8i16\000VABALuv2i64\000VABALuv4i32\000VABALuv8i16\000VABAsv16i8\000"
+ "VABAsv2i32\000VABAsv4i16\000VABAsv4i32\000VABAsv8i16\000VABAsv8i8\000VA"
+ "BAuv16i8\000VABAuv2i32\000VABAuv4i16\000VABAuv4i32\000VABAuv8i16\000VAB"
+ "Auv8i8\000VABDLsv2i64\000VABDLsv4i32\000VABDLsv8i16\000VABDLuv2i64\000V"
+ "ABDLuv4i32\000VABDLuv8i16\000VABDfd\000VABDfq\000VABDsv16i8\000VABDsv2i"
+ "32\000VABDsv4i16\000VABDsv4i32\000VABDsv8i16\000VABDsv8i8\000VABDuv16i8"
+ "\000VABDuv2i32\000VABDuv4i16\000VABDuv4i32\000VABDuv8i16\000VABDuv8i8\000"
+ "VABSD\000VABSS\000VABSfd\000VABSfd_sfp\000VABSfq\000VABSv16i8\000VABSv2"
+ "i32\000VABSv4i16\000VABSv4i32\000VABSv8i16\000VABSv8i8\000VACGEd\000VAC"
+ "GEq\000VACGTd\000VACGTq\000VADDD\000VADDHNv2i32\000VADDHNv4i16\000VADDH"
+ "Nv8i8\000VADDLsv2i64\000VADDLsv4i32\000VADDLsv8i16\000VADDLuv2i64\000VA"
+ "DDLuv4i32\000VADDLuv8i16\000VADDS\000VADDWsv2i64\000VADDWsv4i32\000VADD"
+ "Wsv8i16\000VADDWuv2i64\000VADDWuv4i32\000VADDWuv8i16\000VADDfd\000VADDf"
+ "d_sfp\000VADDfq\000VADDv16i8\000VADDv1i64\000VADDv2i32\000VADDv2i64\000"
+ "VADDv4i16\000VADDv4i32\000VADDv8i16\000VADDv8i8\000VANDd\000VANDq\000VB"
+ "ICd\000VBICq\000VBIFd\000VBIFq\000VBITd\000VBITq\000VBSLd\000VBSLq\000V"
+ "CEQfd\000VCEQfq\000VCEQv16i8\000VCEQv2i32\000VCEQv4i16\000VCEQv4i32\000"
+ "VCEQv8i16\000VCEQv8i8\000VCEQzv16i8\000VCEQzv2f32\000VCEQzv2i32\000VCEQ"
+ "zv4f32\000VCEQzv4i16\000VCEQzv4i32\000VCEQzv8i16\000VCEQzv8i8\000VCGEfd"
+ "\000VCGEfq\000VCGEsv16i8\000VCGEsv2i32\000VCGEsv4i16\000VCGEsv4i32\000V"
+ "CGEsv8i16\000VCGEsv8i8\000VCGEuv16i8\000VCGEuv2i32\000VCGEuv4i16\000VCG"
+ "Euv4i32\000VCGEuv8i16\000VCGEuv8i8\000VCGEzv16i8\000VCGEzv2f32\000VCGEz"
+ "v2i32\000VCGEzv4f32\000VCGEzv4i16\000VCGEzv4i32\000VCGEzv8i16\000VCGEzv"
+ "8i8\000VCGTfd\000VCGTfq\000VCGTsv16i8\000VCGTsv2i32\000VCGTsv4i16\000VC"
+ "GTsv4i32\000VCGTsv8i16\000VCGTsv8i8\000VCGTuv16i8\000VCGTuv2i32\000VCGT"
+ "uv4i16\000VCGTuv4i32\000VCGTuv8i16\000VCGTuv8i8\000VCGTzv16i8\000VCGTzv"
+ "2f32\000VCGTzv2i32\000VCGTzv4f32\000VCGTzv4i16\000VCGTzv4i32\000VCGTzv8"
+ "i16\000VCGTzv8i8\000VCLEzv16i8\000VCLEzv2f32\000VCLEzv2i32\000VCLEzv4f3"
+ "2\000VCLEzv4i16\000VCLEzv4i32\000VCLEzv8i16\000VCLEzv8i8\000VCLSv16i8\000"
+ "VCLSv2i32\000VCLSv4i16\000VCLSv4i32\000VCLSv8i16\000VCLSv8i8\000VCLTzv1"
+ "6i8\000VCLTzv2f32\000VCLTzv2i32\000VCLTzv4f32\000VCLTzv4i16\000VCLTzv4i"
+ "32\000VCLTzv8i16\000VCLTzv8i8\000VCLZv16i8\000VCLZv2i32\000VCLZv4i16\000"
+ "VCLZv4i32\000VCLZv8i16\000VCLZv8i8\000VCMPD\000VCMPED\000VCMPES\000VCMP"
+ "EZD\000VCMPEZS\000VCMPS\000VCMPZD\000VCMPZS\000VCNTd\000VCNTq\000VCVTBH"
+ "S\000VCVTBSH\000VCVTDS\000VCVTSD\000VCVTTHS\000VCVTTSH\000VCVTf2sd\000V"
+ "CVTf2sd_sfp\000VCVTf2sq\000VCVTf2ud\000VCVTf2ud_sfp\000VCVTf2uq\000VCVT"
+ "f2xsd\000VCVTf2xsq\000VCVTf2xud\000VCVTf2xuq\000VCVTs2fd\000VCVTs2fd_sf"
+ "p\000VCVTs2fq\000VCVTu2fd\000VCVTu2fd_sfp\000VCVTu2fq\000VCVTxs2fd\000V"
+ "CVTxs2fq\000VCVTxu2fd\000VCVTxu2fq\000VDIVD\000VDIVS\000VDUP16d\000VDUP"
+ "16q\000VDUP32d\000VDUP32q\000VDUP8d\000VDUP8q\000VDUPLN16d\000VDUPLN16q"
+ "\000VDUPLN32d\000VDUPLN32q\000VDUPLN8d\000VDUPLN8q\000VDUPLNfd\000VDUPL"
+ "Nfq\000VDUPfd\000VDUPfdf\000VDUPfq\000VDUPfqf\000VEORd\000VEORq\000VEXT"
+ "d16\000VEXTd32\000VEXTd8\000VEXTdf\000VEXTq16\000VEXTq32\000VEXTq8\000V"
+ "EXTqf\000VGETLNi32\000VGETLNs16\000VGETLNs8\000VGETLNu16\000VGETLNu8\000"
+ "VHADDsv16i8\000VHADDsv2i32\000VHADDsv4i16\000VHADDsv4i32\000VHADDsv8i16"
+ "\000VHADDsv8i8\000VHADDuv16i8\000VHADDuv2i32\000VHADDuv4i16\000VHADDuv4"
+ "i32\000VHADDuv8i16\000VHADDuv8i8\000VHSUBsv16i8\000VHSUBsv2i32\000VHSUB"
+ "sv4i16\000VHSUBsv4i32\000VHSUBsv8i16\000VHSUBsv8i8\000VHSUBuv16i8\000VH"
+ "SUBuv2i32\000VHSUBuv4i16\000VHSUBuv4i32\000VHSUBuv8i16\000VHSUBuv8i8\000"
+ "VLD1d16\000VLD1d16Q\000VLD1d16T\000VLD1d32\000VLD1d32Q\000VLD1d32T\000V"
+ "LD1d64\000VLD1d8\000VLD1d8Q\000VLD1d8T\000VLD1df\000VLD1q16\000VLD1q32\000"
+ "VLD1q64\000VLD1q8\000VLD1qf\000VLD2LNd16\000VLD2LNd32\000VLD2LNd8\000VL"
+ "D2LNq16a\000VLD2LNq16b\000VLD2LNq32a\000VLD2LNq32b\000VLD2d16\000VLD2d1"
+ "6D\000VLD2d32\000VLD2d32D\000VLD2d64\000VLD2d8\000VLD2d8D\000VLD2q16\000"
+ "VLD2q32\000VLD2q8\000VLD3LNd16\000VLD3LNd32\000VLD3LNd8\000VLD3LNq16a\000"
+ "VLD3LNq16b\000VLD3LNq32a\000VLD3LNq32b\000VLD3d16\000VLD3d32\000VLD3d64"
+ "\000VLD3d8\000VLD3q16a\000VLD3q16b\000VLD3q32a\000VLD3q32b\000VLD3q8a\000"
+ "VLD3q8b\000VLD4LNd16\000VLD4LNd32\000VLD4LNd8\000VLD4LNq16a\000VLD4LNq1"
+ "6b\000VLD4LNq32a\000VLD4LNq32b\000VLD4d16\000VLD4d32\000VLD4d64\000VLD4"
+ "d8\000VLD4q16a\000VLD4q16b\000VLD4q32a\000VLD4q32b\000VLD4q8a\000VLD4q8"
+ "b\000VLDMD\000VLDMS\000VLDRD\000VLDRQ\000VLDRS\000VMAXfd\000VMAXfd_sfp\000"
+ "VMAXfq\000VMAXsv16i8\000VMAXsv2i32\000VMAXsv4i16\000VMAXsv4i32\000VMAXs"
+ "v8i16\000VMAXsv8i8\000VMAXuv16i8\000VMAXuv2i32\000VMAXuv4i16\000VMAXuv4"
+ "i32\000VMAXuv8i16\000VMAXuv8i8\000VMINfd\000VMINfd_sfp\000VMINfq\000VMI"
+ "Nsv16i8\000VMINsv2i32\000VMINsv4i16\000VMINsv4i32\000VMINsv8i16\000VMIN"
+ "sv8i8\000VMINuv16i8\000VMINuv2i32\000VMINuv4i16\000VMINuv4i32\000VMINuv"
+ "8i16\000VMINuv8i8\000VMLAD\000VMLALslsv2i32\000VMLALslsv4i16\000VMLALsl"
+ "uv2i32\000VMLALsluv4i16\000VMLALsv2i64\000VMLALsv4i32\000VMLALsv8i16\000"
+ "VMLALuv2i64\000VMLALuv4i32\000VMLALuv8i16\000VMLAS\000VMLAfd\000VMLAfq\000"
+ "VMLAslfd\000VMLAslfq\000VMLAslv2i32\000VMLAslv4i16\000VMLAslv4i32\000VM"
+ "LAslv8i16\000VMLAv16i8\000VMLAv2i32\000VMLAv4i16\000VMLAv4i32\000VMLAv8"
+ "i16\000VMLAv8i8\000VMLSD\000VMLSLslsv2i32\000VMLSLslsv4i16\000VMLSLsluv"
+ "2i32\000VMLSLsluv4i16\000VMLSLsv2i64\000VMLSLsv4i32\000VMLSLsv8i16\000V"
+ "MLSLuv2i64\000VMLSLuv4i32\000VMLSLuv8i16\000VMLSS\000VMLSfd\000VMLSfq\000"
+ "VMLSslfd\000VMLSslfq\000VMLSslv2i32\000VMLSslv4i16\000VMLSslv4i32\000VM"
+ "LSslv8i16\000VMLSv16i8\000VMLSv2i32\000VMLSv4i16\000VMLSv4i32\000VMLSv8"
+ "i16\000VMLSv8i8\000VMOVD\000VMOVDRR\000VMOVDcc\000VMOVDneon\000VMOVLsv2"
+ "i64\000VMOVLsv4i32\000VMOVLsv8i16\000VMOVLuv2i64\000VMOVLuv4i32\000VMOV"
+ "Luv8i16\000VMOVNv2i32\000VMOVNv4i16\000VMOVNv8i8\000VMOVQ\000VMOVRRD\000"
+ "VMOVRRS\000VMOVRS\000VMOVS\000VMOVSR\000VMOVSRR\000VMOVScc\000VMOVv16i8"
+ "\000VMOVv1i64\000VMOVv2i32\000VMOVv2i64\000VMOVv4i16\000VMOVv4i32\000VM"
+ "OVv8i16\000VMOVv8i8\000VMRS\000VMSR\000VMULD\000VMULLp\000VMULLslsv2i32"
+ "\000VMULLslsv4i16\000VMULLsluv2i32\000VMULLsluv4i16\000VMULLsv2i64\000V"
+ "MULLsv4i32\000VMULLsv8i16\000VMULLuv2i64\000VMULLuv4i32\000VMULLuv8i16\000"
+ "VMULS\000VMULfd\000VMULfd_sfp\000VMULfq\000VMULpd\000VMULpq\000VMULslfd"
+ "\000VMULslfq\000VMULslv2i32\000VMULslv4i16\000VMULslv4i32\000VMULslv8i1"
+ "6\000VMULv16i8\000VMULv2i32\000VMULv4i16\000VMULv4i32\000VMULv8i16\000V"
+ "MULv8i8\000VMVNd\000VMVNq\000VNEGD\000VNEGDcc\000VNEGS\000VNEGScc\000VN"
+ "EGf32q\000VNEGfd\000VNEGfd_sfp\000VNEGs16d\000VNEGs16q\000VNEGs32d\000V"
+ "NEGs32q\000VNEGs8d\000VNEGs8q\000VNMLAD\000VNMLAS\000VNMLSD\000VNMLSS\000"
+ "VNMULD\000VNMULS\000VORNd\000VORNq\000VORRd\000VORRq\000VPADALsv16i8\000"
+ "VPADALsv2i32\000VPADALsv4i16\000VPADALsv4i32\000VPADALsv8i16\000VPADALs"
+ "v8i8\000VPADALuv16i8\000VPADALuv2i32\000VPADALuv4i16\000VPADALuv4i32\000"
+ "VPADALuv8i16\000VPADALuv8i8\000VPADDLsv16i8\000VPADDLsv2i32\000VPADDLsv"
+ "4i16\000VPADDLsv4i32\000VPADDLsv8i16\000VPADDLsv8i8\000VPADDLuv16i8\000"
+ "VPADDLuv2i32\000VPADDLuv4i16\000VPADDLuv4i32\000VPADDLuv8i16\000VPADDLu"
+ "v8i8\000VPADDf\000VPADDi16\000VPADDi32\000VPADDi8\000VPMAXf\000VPMAXs16"
+ "\000VPMAXs32\000VPMAXs8\000VPMAXu16\000VPMAXu32\000VPMAXu8\000VPMINf\000"
+ "VPMINs16\000VPMINs32\000VPMINs8\000VPMINu16\000VPMINu32\000VPMINu8\000V"
+ "QABSv16i8\000VQABSv2i32\000VQABSv4i16\000VQABSv4i32\000VQABSv8i16\000VQ"
+ "ABSv8i8\000VQADDsv16i8\000VQADDsv1i64\000VQADDsv2i32\000VQADDsv2i64\000"
+ "VQADDsv4i16\000VQADDsv4i32\000VQADDsv8i16\000VQADDsv8i8\000VQADDuv16i8\000"
+ "VQADDuv1i64\000VQADDuv2i32\000VQADDuv2i64\000VQADDuv4i16\000VQADDuv4i32"
+ "\000VQADDuv8i16\000VQADDuv8i8\000VQDMLALslv2i32\000VQDMLALslv4i16\000VQ"
+ "DMLALv2i64\000VQDMLALv4i32\000VQDMLSLslv2i32\000VQDMLSLslv4i16\000VQDML"
+ "SLv2i64\000VQDMLSLv4i32\000VQDMULHslv2i32\000VQDMULHslv4i16\000VQDMULHs"
+ "lv4i32\000VQDMULHslv8i16\000VQDMULHv2i32\000VQDMULHv4i16\000VQDMULHv4i3"
+ "2\000VQDMULHv8i16\000VQDMULLslv2i32\000VQDMULLslv4i16\000VQDMULLv2i64\000"
+ "VQDMULLv4i32\000VQMOVNsuv2i32\000VQMOVNsuv4i16\000VQMOVNsuv8i8\000VQMOV"
+ "Nsv2i32\000VQMOVNsv4i16\000VQMOVNsv8i8\000VQMOVNuv2i32\000VQMOVNuv4i16\000"
+ "VQMOVNuv8i8\000VQNEGv16i8\000VQNEGv2i32\000VQNEGv4i16\000VQNEGv4i32\000"
+ "VQNEGv8i16\000VQNEGv8i8\000VQRDMULHslv2i32\000VQRDMULHslv4i16\000VQRDMU"
+ "LHslv4i32\000VQRDMULHslv8i16\000VQRDMULHv2i32\000VQRDMULHv4i16\000VQRDM"
+ "ULHv4i32\000VQRDMULHv8i16\000VQRSHLsv16i8\000VQRSHLsv1i64\000VQRSHLsv2i"
+ "32\000VQRSHLsv2i64\000VQRSHLsv4i16\000VQRSHLsv4i32\000VQRSHLsv8i16\000V"
+ "QRSHLsv8i8\000VQRSHLuv16i8\000VQRSHLuv1i64\000VQRSHLuv2i32\000VQRSHLuv2"
+ "i64\000VQRSHLuv4i16\000VQRSHLuv4i32\000VQRSHLuv8i16\000VQRSHLuv8i8\000V"
+ "QRSHRNsv2i32\000VQRSHRNsv4i16\000VQRSHRNsv8i8\000VQRSHRNuv2i32\000VQRSH"
+ "RNuv4i16\000VQRSHRNuv8i8\000VQRSHRUNv2i32\000VQRSHRUNv4i16\000VQRSHRUNv"
+ "8i8\000VQSHLsiv16i8\000VQSHLsiv1i64\000VQSHLsiv2i32\000VQSHLsiv2i64\000"
+ "VQSHLsiv4i16\000VQSHLsiv4i32\000VQSHLsiv8i16\000VQSHLsiv8i8\000VQSHLsuv"
+ "16i8\000VQSHLsuv1i64\000VQSHLsuv2i32\000VQSHLsuv2i64\000VQSHLsuv4i16\000"
+ "VQSHLsuv4i32\000VQSHLsuv8i16\000VQSHLsuv8i8\000VQSHLsv16i8\000VQSHLsv1i"
+ "64\000VQSHLsv2i32\000VQSHLsv2i64\000VQSHLsv4i16\000VQSHLsv4i32\000VQSHL"
+ "sv8i16\000VQSHLsv8i8\000VQSHLuiv16i8\000VQSHLuiv1i64\000VQSHLuiv2i32\000"
+ "VQSHLuiv2i64\000VQSHLuiv4i16\000VQSHLuiv4i32\000VQSHLuiv8i16\000VQSHLui"
+ "v8i8\000VQSHLuv16i8\000VQSHLuv1i64\000VQSHLuv2i32\000VQSHLuv2i64\000VQS"
+ "HLuv4i16\000VQSHLuv4i32\000VQSHLuv8i16\000VQSHLuv8i8\000VQSHRNsv2i32\000"
+ "VQSHRNsv4i16\000VQSHRNsv8i8\000VQSHRNuv2i32\000VQSHRNuv4i16\000VQSHRNuv"
+ "8i8\000VQSHRUNv2i32\000VQSHRUNv4i16\000VQSHRUNv8i8\000VQSUBsv16i8\000VQ"
+ "SUBsv1i64\000VQSUBsv2i32\000VQSUBsv2i64\000VQSUBsv4i16\000VQSUBsv4i32\000"
+ "VQSUBsv8i16\000VQSUBsv8i8\000VQSUBuv16i8\000VQSUBuv1i64\000VQSUBuv2i32\000"
+ "VQSUBuv2i64\000VQSUBuv4i16\000VQSUBuv4i32\000VQSUBuv8i16\000VQSUBuv8i8\000"
+ "VRADDHNv2i32\000VRADDHNv4i16\000VRADDHNv8i8\000VRECPEd\000VRECPEfd\000V"
+ "RECPEfq\000VRECPEq\000VRECPSfd\000VRECPSfq\000VREV16d8\000VREV16q8\000V"
+ "REV32d16\000VREV32d8\000VREV32q16\000VREV32q8\000VREV64d16\000VREV64d32"
+ "\000VREV64d8\000VREV64df\000VREV64q16\000VREV64q32\000VREV64q8\000VREV6"
+ "4qf\000VRHADDsv16i8\000VRHADDsv2i32\000VRHADDsv4i16\000VRHADDsv4i32\000"
+ "VRHADDsv8i16\000VRHADDsv8i8\000VRHADDuv16i8\000VRHADDuv2i32\000VRHADDuv"
+ "4i16\000VRHADDuv4i32\000VRHADDuv8i16\000VRHADDuv8i8\000VRSHLsv16i8\000V"
+ "RSHLsv1i64\000VRSHLsv2i32\000VRSHLsv2i64\000VRSHLsv4i16\000VRSHLsv4i32\000"
+ "VRSHLsv8i16\000VRSHLsv8i8\000VRSHLuv16i8\000VRSHLuv1i64\000VRSHLuv2i32\000"
+ "VRSHLuv2i64\000VRSHLuv4i16\000VRSHLuv4i32\000VRSHLuv8i16\000VRSHLuv8i8\000"
+ "VRSHRNv2i32\000VRSHRNv4i16\000VRSHRNv8i8\000VRSHRsv16i8\000VRSHRsv1i64\000"
+ "VRSHRsv2i32\000VRSHRsv2i64\000VRSHRsv4i16\000VRSHRsv4i32\000VRSHRsv8i16"
+ "\000VRSHRsv8i8\000VRSHRuv16i8\000VRSHRuv1i64\000VRSHRuv2i32\000VRSHRuv2"
+ "i64\000VRSHRuv4i16\000VRSHRuv4i32\000VRSHRuv8i16\000VRSHRuv8i8\000VRSQR"
+ "TEd\000VRSQRTEfd\000VRSQRTEfq\000VRSQRTEq\000VRSQRTSfd\000VRSQRTSfq\000"
+ "VRSRAsv16i8\000VRSRAsv1i64\000VRSRAsv2i32\000VRSRAsv2i64\000VRSRAsv4i16"
+ "\000VRSRAsv4i32\000VRSRAsv8i16\000VRSRAsv8i8\000VRSRAuv16i8\000VRSRAuv1"
+ "i64\000VRSRAuv2i32\000VRSRAuv2i64\000VRSRAuv4i16\000VRSRAuv4i32\000VRSR"
+ "Auv8i16\000VRSRAuv8i8\000VRSUBHNv2i32\000VRSUBHNv4i16\000VRSUBHNv8i8\000"
+ "VSETLNi16\000VSETLNi32\000VSETLNi8\000VSHLLi16\000VSHLLi32\000VSHLLi8\000"
+ "VSHLLsv2i64\000VSHLLsv4i32\000VSHLLsv8i16\000VSHLLuv2i64\000VSHLLuv4i32"
+ "\000VSHLLuv8i16\000VSHLiv16i8\000VSHLiv1i64\000VSHLiv2i32\000VSHLiv2i64"
+ "\000VSHLiv4i16\000VSHLiv4i32\000VSHLiv8i16\000VSHLiv8i8\000VSHLsv16i8\000"
+ "VSHLsv1i64\000VSHLsv2i32\000VSHLsv2i64\000VSHLsv4i16\000VSHLsv4i32\000V"
+ "SHLsv8i16\000VSHLsv8i8\000VSHLuv16i8\000VSHLuv1i64\000VSHLuv2i32\000VSH"
+ "Luv2i64\000VSHLuv4i16\000VSHLuv4i32\000VSHLuv8i16\000VSHLuv8i8\000VSHRN"
+ "v2i32\000VSHRNv4i16\000VSHRNv8i8\000VSHRsv16i8\000VSHRsv1i64\000VSHRsv2"
+ "i32\000VSHRsv2i64\000VSHRsv4i16\000VSHRsv4i32\000VSHRsv8i16\000VSHRsv8i"
+ "8\000VSHRuv16i8\000VSHRuv1i64\000VSHRuv2i32\000VSHRuv2i64\000VSHRuv4i16"
+ "\000VSHRuv4i32\000VSHRuv8i16\000VSHRuv8i8\000VSHTOD\000VSHTOS\000VSITOD"
+ "\000VSITOS\000VSLIv16i8\000VSLIv1i64\000VSLIv2i32\000VSLIv2i64\000VSLIv"
+ "4i16\000VSLIv4i32\000VSLIv8i16\000VSLIv8i8\000VSLTOD\000VSLTOS\000VSQRT"
+ "D\000VSQRTS\000VSRAsv16i8\000VSRAsv1i64\000VSRAsv2i32\000VSRAsv2i64\000"
+ "VSRAsv4i16\000VSRAsv4i32\000VSRAsv8i16\000VSRAsv8i8\000VSRAuv16i8\000VS"
+ "RAuv1i64\000VSRAuv2i32\000VSRAuv2i64\000VSRAuv4i16\000VSRAuv4i32\000VSR"
+ "Auv8i16\000VSRAuv8i8\000VSRIv16i8\000VSRIv1i64\000VSRIv2i32\000VSRIv2i6"
+ "4\000VSRIv4i16\000VSRIv4i32\000VSRIv8i16\000VSRIv8i8\000VST1d16\000VST1"
+ "d16Q\000VST1d16T\000VST1d32\000VST1d32Q\000VST1d32T\000VST1d64\000VST1d"
+ "8\000VST1d8Q\000VST1d8T\000VST1df\000VST1q16\000VST1q32\000VST1q64\000V"
+ "ST1q8\000VST1qf\000VST2LNd16\000VST2LNd32\000VST2LNd8\000VST2LNq16a\000"
+ "VST2LNq16b\000VST2LNq32a\000VST2LNq32b\000VST2d16\000VST2d16D\000VST2d3"
+ "2\000VST2d32D\000VST2d64\000VST2d8\000VST2d8D\000VST2q16\000VST2q32\000"
+ "VST2q8\000VST3LNd16\000VST3LNd32\000VST3LNd8\000VST3LNq16a\000VST3LNq16"
+ "b\000VST3LNq32a\000VST3LNq32b\000VST3d16\000VST3d32\000VST3d64\000VST3d"
+ "8\000VST3q16a\000VST3q16b\000VST3q32a\000VST3q32b\000VST3q8a\000VST3q8b"
+ "\000VST4LNd16\000VST4LNd32\000VST4LNd8\000VST4LNq16a\000VST4LNq16b\000V"
+ "ST4LNq32a\000VST4LNq32b\000VST4d16\000VST4d32\000VST4d64\000VST4d8\000V"
+ "ST4q16a\000VST4q16b\000VST4q32a\000VST4q32b\000VST4q8a\000VST4q8b\000VS"
+ "TMD\000VSTMS\000VSTRD\000VSTRQ\000VSTRS\000VSUBD\000VSUBHNv2i32\000VSUB"
+ "HNv4i16\000VSUBHNv8i8\000VSUBLsv2i64\000VSUBLsv4i32\000VSUBLsv8i16\000V"
+ "SUBLuv2i64\000VSUBLuv4i32\000VSUBLuv8i16\000VSUBS\000VSUBWsv2i64\000VSU"
+ "BWsv4i32\000VSUBWsv8i16\000VSUBWuv2i64\000VSUBWuv4i32\000VSUBWuv8i16\000"
+ "VSUBfd\000VSUBfd_sfp\000VSUBfq\000VSUBv16i8\000VSUBv1i64\000VSUBv2i32\000"
+ "VSUBv2i64\000VSUBv4i16\000VSUBv4i32\000VSUBv8i16\000VSUBv8i8\000VSWPd\000"
+ "VSWPq\000VTBL1\000VTBL2\000VTBL3\000VTBL4\000VTBX1\000VTBX2\000VTBX3\000"
+ "VTBX4\000VTOSHD\000VTOSHS\000VTOSIRD\000VTOSIRS\000VTOSIZD\000VTOSIZS\000"
+ "VTOSLD\000VTOSLS\000VTOUHD\000VTOUHS\000VTOUIRD\000VTOUIRS\000VTOUIZD\000"
+ "VTOUIZS\000VTOULD\000VTOULS\000VTRNd16\000VTRNd32\000VTRNd8\000VTRNq16\000"
+ "VTRNq32\000VTRNq8\000VTSTv16i8\000VTSTv2i32\000VTSTv4i16\000VTSTv4i32\000"
+ "VTSTv8i16\000VTSTv8i8\000VUHTOD\000VUHTOS\000VUITOD\000VUITOS\000VULTOD"
+ "\000VULTOS\000VUZPd16\000VUZPd32\000VUZPd8\000VUZPq16\000VUZPq32\000VUZ"
+ "Pq8\000VZIPd16\000VZIPd32\000VZIPd8\000VZIPq16\000VZIPq32\000VZIPq8\000"
+ "WFE\000WFI\000YIELD\000t2ADCSri\000t2ADCSrr\000t2ADCSrs\000t2ADCri\000t"
+ "2ADCrr\000t2ADCrs\000t2ADDSri\000t2ADDSrr\000t2ADDSrs\000t2ADDrSPi\000t"
+ "2ADDrSPi12\000t2ADDrSPs\000t2ADDri\000t2ADDri12\000t2ADDrr\000t2ADDrs\000"
+ "t2ANDri\000t2ANDrr\000t2ANDrs\000t2ASRri\000t2ASRrr\000t2B\000t2BFC\000"
+ "t2BFI\000t2BICri\000t2BICrr\000t2BICrs\000t2BR_JT\000t2BXJ\000t2Bcc\000"
+ "t2CLREX\000t2CLZ\000t2CMNzri\000t2CMNzrr\000t2CMNzrs\000t2CMPri\000t2CM"
+ "Prr\000t2CMPrs\000t2CMPzri\000t2CMPzrr\000t2CMPzrs\000t2CPS\000t2DBG\000"
+ "t2DMBish\000t2DMBishst\000t2DMBnsh\000t2DMBnshst\000t2DMBosh\000t2DMBos"
+ "hst\000t2DMBst\000t2DSBish\000t2DSBishst\000t2DSBnsh\000t2DSBnshst\000t"
+ "2DSBosh\000t2DSBoshst\000t2DSBst\000t2EORri\000t2EORrr\000t2EORrs\000t2"
+ "ISBsy\000t2IT\000t2Int_MemBarrierV7\000t2Int_SyncBarrierV7\000t2Int_eh_"
+ "sjlj_setjmp\000t2LDM\000t2LDM_RET\000t2LDRBT\000t2LDRB_POST\000t2LDRB_P"
+ "RE\000t2LDRBi12\000t2LDRBi8\000t2LDRBpci\000t2LDRBs\000t2LDRDi8\000t2LD"
+ "RDpci\000t2LDREX\000t2LDREXB\000t2LDREXD\000t2LDREXH\000t2LDRHT\000t2LD"
+ "RH_POST\000t2LDRH_PRE\000t2LDRHi12\000t2LDRHi8\000t2LDRHpci\000t2LDRHs\000"
+ "t2LDRSBT\000t2LDRSB_POST\000t2LDRSB_PRE\000t2LDRSBi12\000t2LDRSBi8\000t"
+ "2LDRSBpci\000t2LDRSBs\000t2LDRSHT\000t2LDRSH_POST\000t2LDRSH_PRE\000t2L"
+ "DRSHi12\000t2LDRSHi8\000t2LDRSHpci\000t2LDRSHs\000t2LDRT\000t2LDR_POST\000"
+ "t2LDR_PRE\000t2LDRi12\000t2LDRi8\000t2LDRpci\000t2LDRpci_pic\000t2LDRs\000"
+ "t2LEApcrel\000t2LEApcrelJT\000t2LSLri\000t2LSLrr\000t2LSRri\000t2LSRrr\000"
+ "t2MLA\000t2MLS\000t2MOVCCasr\000t2MOVCCi\000t2MOVCClsl\000t2MOVCClsr\000"
+ "t2MOVCCr\000t2MOVCCror\000t2MOVTi16\000t2MOVi\000t2MOVi16\000t2MOVi32im"
+ "m\000t2MOVr\000t2MOVrx\000t2MOVsra_flag\000t2MOVsrl_flag\000t2MRS\000t2"
+ "MRSsys\000t2MSR\000t2MSRsys\000t2MUL\000t2MVNi\000t2MVNr\000t2MVNs\000t"
+ "2NOP\000t2ORNri\000t2ORNrr\000t2ORNrs\000t2ORRri\000t2ORRrr\000t2ORRrs\000"
+ "t2PKHBT\000t2PKHTB\000t2PLDWi12\000t2PLDWi8\000t2PLDWpci\000t2PLDWr\000"
+ "t2PLDWs\000t2PLDi12\000t2PLDi8\000t2PLDpci\000t2PLDr\000t2PLDs\000t2PLI"
+ "i12\000t2PLIi8\000t2PLIpci\000t2PLIr\000t2PLIs\000t2QADD\000t2QADD16\000"
+ "t2QADD8\000t2QASX\000t2QDADD\000t2QDSUB\000t2QSAX\000t2QSUB\000t2QSUB16"
+ "\000t2QSUB8\000t2RBIT\000t2REV\000t2REV16\000t2REVSH\000t2RFEDB\000t2RF"
+ "EDBW\000t2RFEIA\000t2RFEIAW\000t2RORri\000t2RORrr\000t2RSBSri\000t2RSBS"
+ "rs\000t2RSBri\000t2RSBrs\000t2SADD16\000t2SADD8\000t2SASX\000t2SBCSri\000"
+ "t2SBCSrr\000t2SBCSrs\000t2SBCri\000t2SBCrr\000t2SBCrs\000t2SBFX\000t2SD"
+ "IV\000t2SEL\000t2SEV\000t2SHADD16\000t2SHADD8\000t2SHASX\000t2SHSAX\000"
+ "t2SHSUB16\000t2SHSUB8\000t2SMC\000t2SMLABB\000t2SMLABT\000t2SMLAD\000t2"
+ "SMLADX\000t2SMLAL\000t2SMLALBB\000t2SMLALBT\000t2SMLALD\000t2SMLALDX\000"
+ "t2SMLALTB\000t2SMLALTT\000t2SMLATB\000t2SMLATT\000t2SMLAWB\000t2SMLAWT\000"
+ "t2SMLSD\000t2SMLSDX\000t2SMLSLD\000t2SMLSLDX\000t2SMMLA\000t2SMMLAR\000"
+ "t2SMMLS\000t2SMMLSR\000t2SMMUL\000t2SMMULR\000t2SMUAD\000t2SMUADX\000t2"
+ "SMULBB\000t2SMULBT\000t2SMULL\000t2SMULTB\000t2SMULTT\000t2SMULWB\000t2"
+ "SMULWT\000t2SMUSD\000t2SMUSDX\000t2SRSDB\000t2SRSDBW\000t2SRSIA\000t2SR"
+ "SIAW\000t2SSAT16\000t2SSATasr\000t2SSATlsl\000t2SSAX\000t2SSUB16\000t2S"
+ "SUB8\000t2STM\000t2STRBT\000t2STRB_POST\000t2STRB_PRE\000t2STRBi12\000t"
+ "2STRBi8\000t2STRBs\000t2STRDi8\000t2STREX\000t2STREXB\000t2STREXD\000t2"
+ "STREXH\000t2STRHT\000t2STRH_POST\000t2STRH_PRE\000t2STRHi12\000t2STRHi8"
+ "\000t2STRHs\000t2STRT\000t2STR_POST\000t2STR_PRE\000t2STRi12\000t2STRi8"
+ "\000t2STRs\000t2SUBSri\000t2SUBSrr\000t2SUBSrs\000t2SUBrSPi\000t2SUBrSP"
+ "i12\000t2SUBrSPi12_\000t2SUBrSPi_\000t2SUBrSPs\000t2SUBrSPs_\000t2SUBri"
+ "\000t2SUBri12\000t2SUBrr\000t2SUBrs\000t2SXTAB16rr\000t2SXTAB16rr_rot\000"
+ "t2SXTABrr\000t2SXTABrr_rot\000t2SXTAHrr\000t2SXTAHrr_rot\000t2SXTB16r\000"
+ "t2SXTB16r_rot\000t2SXTBr\000t2SXTBr_rot\000t2SXTHr\000t2SXTHr_rot\000t2"
+ "TBB\000t2TBBgen\000t2TBH\000t2TBHgen\000t2TEQri\000t2TEQrr\000t2TEQrs\000"
+ "t2TPsoft\000t2TSTri\000t2TSTrr\000t2TSTrs\000t2UADD16\000t2UADD8\000t2U"
+ "ASX\000t2UBFX\000t2UDIV\000t2UHADD16\000t2UHADD8\000t2UHASX\000t2UHSAX\000"
+ "t2UHSUB16\000t2UHSUB8\000t2UMAAL\000t2UMLAL\000t2UMULL\000t2UQADD16\000"
+ "t2UQADD8\000t2UQASX\000t2UQSAX\000t2UQSUB16\000t2UQSUB8\000t2USAD8\000t"
+ "2USADA8\000t2USAT16\000t2USATasr\000t2USATlsl\000t2USAX\000t2USUB16\000"
+ "t2USUB8\000t2UXTAB16rr\000t2UXTAB16rr_rot\000t2UXTABrr\000t2UXTABrr_rot"
+ "\000t2UXTAHrr\000t2UXTAHrr_rot\000t2UXTB16r\000t2UXTB16r_rot\000t2UXTBr"
+ "\000t2UXTBr_rot\000t2UXTHr\000t2UXTHr_rot\000t2WFE\000t2WFI\000t2YIELD\000"
+ "tADC\000tADDhirr\000tADDi3\000tADDi8\000tADDrPCi\000tADDrSP\000tADDrSPi"
+ "\000tADDrr\000tADDspi\000tADDspr\000tADDspr_\000tADJCALLSTACKDOWN\000tA"
+ "DJCALLSTACKUP\000tAND\000tANDsp\000tASRri\000tASRrr\000tB\000tBIC\000tB"
+ "KPT\000tBL\000tBLXi\000tBLXi_r9\000tBLXr\000tBLXr_r9\000tBLr9\000tBRIND"
+ "\000tBR_JTr\000tBX\000tBX_RET\000tBX_RET_vararg\000tBXr9\000tBcc\000tBf"
+ "ar\000tCBNZ\000tCBZ\000tCMNz\000tCMPhir\000tCMPi8\000tCMPr\000tCMPzhir\000"
+ "tCMPzi8\000tCMPzr\000tCPS\000tEOR\000tInt_eh_sjlj_setjmp\000tLDM\000tLD"
+ "R\000tLDRB\000tLDRBi\000tLDRH\000tLDRHi\000tLDRSB\000tLDRSH\000tLDRcp\000"
+ "tLDRi\000tLDRpci\000tLDRpci_pic\000tLDRspi\000tLEApcrel\000tLEApcrelJT\000"
+ "tLSLri\000tLSLrr\000tLSRri\000tLSRrr\000tMOVCCi\000tMOVCCr\000tMOVCCr_p"
+ "seudo\000tMOVSr\000tMOVgpr2gpr\000tMOVgpr2tgpr\000tMOVi8\000tMOVr\000tM"
+ "OVtgpr2gpr\000tMUL\000tMVN\000tNOP\000tORR\000tPICADD\000tPOP\000tPOP_R"
+ "ET\000tPUSH\000tREV\000tREV16\000tREVSH\000tROR\000tRSB\000tRestore\000"
+ "tSBC\000tSETENDBE\000tSETENDLE\000tSEV\000tSTM\000tSTR\000tSTRB\000tSTR"
+ "Bi\000tSTRH\000tSTRHi\000tSTRi\000tSTRspi\000tSUBi3\000tSUBi8\000tSUBrr"
+ "\000tSUBspi\000tSUBspi_\000tSVC\000tSXTB\000tSXTH\000tSpill\000tTPsoft\000"
+ "tTRAP\000tTST\000tUXTB\000tUXTH\000tWFE\000tWFI\000tYIELD\000";
return Strs+InstAsmOffset[Opcode];
}
diff --git a/libclamav/c++/ARMGenCodeEmitter.inc b/libclamav/c++/ARMGenCodeEmitter.inc
index 616f024..8ce1986 100644
--- a/libclamav/c++/ARMGenCodeEmitter.inc
+++ b/libclamav/c++/ARMGenCodeEmitter.inc
@@ -74,6 +74,8 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
184549376U, // BL_pred
3942645760U, // BLr9
184549376U, // BLr9_pred
+ 27324416U, // BMOVPCRX
+ 27324416U, // BMOVPCRXr9
3778019088U, // BRIND
8450048U, // BR_JTadd
118550528U, // BR_JTm
@@ -182,6 +184,8 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
60817408U, // MOVCCi
27262976U, // MOVCCr
27262976U, // MOVCCs
+ 27324430U, // MOVPCLR
+ 3785420800U, // MOVPCRX
54525952U, // MOVTi16
60817408U, // MOVi
50331648U, // MOVi16
@@ -2014,6 +2018,8 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::BL_pred:
case ARM::BLr9:
case ARM::BLr9_pred:
+ case ARM::BMOVPCRX:
+ case ARM::BMOVPCRXr9:
case ARM::BRIND:
case ARM::BR_JTadd:
case ARM::BR_JTm:
@@ -2122,6 +2128,8 @@ unsigned ARMCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) {
case ARM::MOVCCi:
case ARM::MOVCCr:
case ARM::MOVCCs:
+ case ARM::MOVPCLR:
+ case ARM::MOVPCRX:
case ARM::MOVTi16:
case ARM::MOVi:
case ARM::MOVi16:
diff --git a/libclamav/c++/ARMGenDAGISel.inc b/libclamav/c++/ARMGenDAGISel.inc
index 7dbce8a..275c63e 100644
--- a/libclamav/c++/ARMGenDAGISel.inc
+++ b/libclamav/c++/ARMGenDAGISel.inc
@@ -5789,7 +5789,7 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v4i32, 4, 0, 1, 2, 3,
0,
0,
- 44|128,71, ISD::ADD,
+ 30|128,71, ISD::ADD,
OPC_Scope, 94,
OPC_RecordChild0,
OPC_MoveChild, 1,
@@ -7654,7 +7654,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMLAWB), 0,
1, MVT::i32, 5, 1, 0, 2, 3, 4,
0,
- 13|128,1,
+ 7|128,1,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
@@ -7669,52 +7669,48 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveParent,
OPC_MoveParent,
OPC_MoveChild, 1,
- OPC_Scope, 28,
- OPC_CheckValueType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 0,
- OPC_EmitConvertToTarget, 2,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::SXTABrr_rot), 0,
- 1, MVT::i32, 5, 0, 1, 3, 4, 5,
- 28,
- OPC_CheckValueType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 0,
- OPC_EmitConvertToTarget, 2,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::SXTAHrr_rot), 0,
- 1, MVT::i32, 5, 0, 1, 3, 4, 5,
- 28,
+ OPC_Scope, 54,
OPC_CheckValueType, MVT::i8,
OPC_MoveParent,
OPC_MoveParent,
OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_EmitConvertToTarget, 2,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SXTABrr_rot), 0,
- 1, MVT::i32, 5, 0, 1, 3, 4, 5,
- 28,
+ OPC_Scope, 22,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SXTABrr_rot), 0,
+ 1, MVT::i32, 5, 0, 1, 3, 4, 5,
+ 22,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SXTABrr_rot), 0,
+ 1, MVT::i32, 5, 0, 1, 3, 4, 5,
+ 0,
+ 54,
OPC_CheckValueType, MVT::i16,
OPC_MoveParent,
OPC_MoveParent,
OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_EmitConvertToTarget, 2,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SXTAHrr_rot), 0,
- 1, MVT::i32, 5, 0, 1, 3, 4, 5,
+ OPC_Scope, 22,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SXTAHrr_rot), 0,
+ 1, MVT::i32, 5, 0, 1, 3, 4, 5,
+ 22,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SXTAHrr_rot), 0,
+ 1, MVT::i32, 5, 0, 1, 3, 4, 5,
+ 0,
0,
- 16|128,1,
+ 8|128,1,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::SIGN_EXTEND_INREG,
OPC_MoveChild, 0,
@@ -7728,54 +7724,48 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveParent,
OPC_MoveParent,
OPC_MoveChild, 1,
- OPC_Scope, 29,
- OPC_CheckValueType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 0,
- OPC_EmitConvertToTarget, 1,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::SXTABrr_rot), 0,
- 1, MVT::i32, 5, 2, 0, 3, 4, 5,
- 29,
- OPC_CheckValueType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 0,
- OPC_EmitConvertToTarget, 1,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::SXTAHrr_rot), 0,
- 1, MVT::i32, 5, 2, 0, 3, 4, 5,
- 29,
+ OPC_Scope, 55,
OPC_CheckValueType, MVT::i8,
OPC_MoveParent,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_EmitConvertToTarget, 1,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SXTABrr_rot), 0,
- 1, MVT::i32, 5, 2, 0, 3, 4, 5,
- 29,
+ OPC_Scope, 22,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SXTABrr_rot), 0,
+ 1, MVT::i32, 5, 2, 0, 3, 4, 5,
+ 22,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SXTABrr_rot), 0,
+ 1, MVT::i32, 5, 2, 0, 3, 4, 5,
+ 0,
+ 55,
OPC_CheckValueType, MVT::i16,
OPC_MoveParent,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_EmitConvertToTarget, 1,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SXTAHrr_rot), 0,
- 1, MVT::i32, 5, 2, 0, 3, 4, 5,
+ OPC_Scope, 22,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SXTAHrr_rot), 0,
+ 1, MVT::i32, 5, 2, 0, 3, 4, 5,
+ 22,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SXTAHrr_rot), 0,
+ 1, MVT::i32, 5, 2, 0, 3, 4, 5,
+ 0,
0,
18|128,2,
OPC_RecordChild0,
@@ -10967,8 +10957,8 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v4i32, 4, 0, 1, 2, 3,
0,
0,
- 112|128,3, ISD::SIGN_EXTEND_INREG,
- OPC_Scope, 85|128,2,
+ 94|128,3, ISD::SIGN_EXTEND_INREG,
+ OPC_Scope, 81|128,2,
OPC_MoveChild, 0,
OPC_SwitchOpcode , 80|128,1, ISD::OR,
OPC_MoveChild, 0,
@@ -11061,7 +11051,7 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::i32, 3, 0, 1, 2,
0,
0,
- 124, ISD::ROTR,
+ 120, ISD::ROTR,
OPC_RecordChild0,
OPC_RecordChild1,
OPC_MoveChild, 1,
@@ -11071,108 +11061,98 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveParent,
OPC_MoveParent,
OPC_MoveChild, 1,
- OPC_Scope, 26,
+ OPC_Scope, 51,
OPC_CheckValueType, MVT::i8,
OPC_MoveParent,
OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 0,
- OPC_EmitConvertToTarget, 1,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::SXTBr_rot), 0,
- 1, MVT::i32, 4, 0, 2, 3, 4,
- 26,
+ OPC_Scope, 21,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SXTBr_rot), 0,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 21,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SXTBr_rot), 0,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 0,
+ 51,
OPC_CheckValueType, MVT::i16,
OPC_MoveParent,
OPC_CheckType, MVT::i32,
+ OPC_Scope, 21,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SXTHr_rot), 0,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 21,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SXTHr_rot), 0,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 0,
+ 0,
+ 0,
+ 7|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_Scope, 64,
+ OPC_CheckValueType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 18,
OPC_CheckPatternPredicate, 0,
- OPC_EmitConvertToTarget, 1,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::SXTHr_rot), 0,
- 1, MVT::i32, 4, 0, 2, 3, 4,
- 26,
- OPC_CheckValueType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SXTBr), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 18,
+ OPC_CheckPatternPredicate, 1,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SXTBr_rot), 0,
- 1, MVT::i32, 4, 0, 2, 3, 4,
- 26,
- OPC_CheckValueType, MVT::i16,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tSXTB), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 18,
OPC_CheckPatternPredicate, 2,
- OPC_EmitConvertToTarget, 1,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SXTHr_rot), 0,
- 1, MVT::i32, 4, 0, 2, 3, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SXTBr), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
0,
- 0,
- 21|128,1,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_Scope, 23,
- OPC_CheckValueType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::SXTBr), 0,
- 1, MVT::i32, 3, 0, 1, 2,
- 23,
- OPC_CheckValueType, MVT::i16,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::SXTHr), 0,
- 1, MVT::i32, 3, 0, 1, 2,
- 23,
- OPC_CheckValueType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 1,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::tSXTB), 0,
- 1, MVT::i32, 3, 0, 1, 2,
- 23,
- OPC_CheckValueType, MVT::i16,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 1,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::tSXTH), 0,
- 1, MVT::i32, 3, 0, 1, 2,
- 23,
- OPC_CheckValueType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SXTBr), 0,
- 1, MVT::i32, 3, 0, 1, 2,
- 23,
+ 64,
OPC_CheckValueType, MVT::i16,
OPC_MoveParent,
OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SXTHr), 0,
- 1, MVT::i32, 3, 0, 1, 2,
+ OPC_Scope, 18,
+ OPC_CheckPatternPredicate, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SXTHr), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 18,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tSXTH), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 18,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SXTHr), 0,
+ 1, MVT::i32, 3, 0, 1, 2,
+ 0,
0,
0,
- 117|128,4, ISD::SRA,
+ 115|128,4, ISD::SRA,
OPC_Scope, 126|128,2,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::MUL,
@@ -11394,15 +11374,15 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(ARM::SMULWB), 0,
1, MVT::i32, 4, 1, 0, 2, 3,
0,
- 2|128,1,
+ 0|128,1,
OPC_RecordChild0,
OPC_RecordChild1,
- OPC_Scope, 70,
+ OPC_Scope, 68,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::Constant,
- OPC_Scope, 32,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 30,
OPC_CheckPredicate, 24,
- OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 2,
@@ -11412,8 +11392,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ASRri), 0,
1, MVT::i32, 5, 0, 2, 3, 4, 5,
- 30,
- OPC_CheckType, MVT::i32,
+ 28,
OPC_MoveParent,
OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 6,
@@ -11449,13 +11428,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 89,
OPC_MoveChild, 1,
OPC_SwitchOpcode , 47, ISD::LOAD,
- OPC_CheckPredicate, 25,
- OPC_CheckPredicate, 26,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckPredicate, 25,
+ OPC_CheckPredicate, 26,
OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_RecordChild2,
@@ -11516,221 +11495,143 @@ SDNode *SelectCode(SDNode *N) {
0, 3, 1, 2, 4,
0,
0,
- 94|128,20, ISD::LOAD,
- OPC_CheckPredicate, 25,
- OPC_Scope, 34,
- OPC_CheckPredicate, 26,
- OPC_RecordMemRef,
- OPC_RecordNode,
+ 87|128,17, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_Scope, 60|128,15,
OPC_RecordChild1,
OPC_CheckChild1Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/3, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICLDR), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 4, 2, 3, 4, 5,
- 74,
- OPC_CheckPredicate, 27,
- OPC_Scope, 34,
- OPC_CheckPredicate, 28,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/3, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICLDRH), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 4, 2, 3, 4, 5,
- 34,
- OPC_CheckPredicate, 29,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
+ OPC_CheckPredicate, 25,
+ OPC_Scope, 29,
+ OPC_CheckPredicate, 26,
OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 5,
OPC_CheckComplexPat, /*CP*/3, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICLDRB), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICLDR), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 4, 2, 3, 4, 5,
- 0,
- 10|128,1,
- OPC_CheckPredicate, 30,
- OPC_Scope, 34,
- OPC_CheckPredicate, 31,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
+ 62,
+ OPC_CheckPredicate, 27,
OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/3, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICLDRSH), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 4, 2, 3, 4, 5,
- 63,
- OPC_CheckPredicate, 32,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 28,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICLDRH), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 27,
+ OPC_CheckPredicate, 29,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICLDRB), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 0,
+ 119,
+ OPC_CheckPredicate, 30,
OPC_CheckType, MVT::i32,
- OPC_Scope, 25,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 31,
OPC_CheckPatternPredicate, 5,
OPC_CheckComplexPat, /*CP*/3, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICLDRSB), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICLDRSH), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 4, 2, 3, 4, 5,
- 25,
+ 56,
+ OPC_CheckPredicate, 32,
+ OPC_Scope, 25,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICLDRSB), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 25,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/4, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDRSB), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 0,
+ 27,
+ OPC_CheckPredicate, 31,
OPC_CheckPatternPredicate, 6,
OPC_CheckComplexPat, /*CP*/4, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDRSB), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDRSH), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 4, 2, 3, 4, 5,
0,
- 34,
- OPC_CheckPredicate, 31,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/4, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDRSH), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 4, 2, 3, 4, 5,
- 0,
- 35,
- OPC_CheckPredicate, 26,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/2, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::LDR), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 76,
- OPC_CheckPredicate, 27,
- OPC_Scope, 35,
- OPC_CheckPredicate, 28,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/5, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::LDRH), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 35,
- OPC_CheckPredicate, 29,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
+ 30,
+ OPC_CheckPredicate, 26,
OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 5,
OPC_CheckComplexPat, /*CP*/2, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::LDRB), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::LDR), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 0,
- 76,
- OPC_CheckPredicate, 30,
- OPC_Scope, 35,
- OPC_CheckPredicate, 31,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/5, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::LDRSH), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 35,
- OPC_CheckPredicate, 32,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
+ 64,
+ OPC_CheckPredicate, 27,
OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/5, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::LDRSB), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 0,
- 37,
- OPC_CheckPredicate, 27,
- OPC_CheckPredicate, 33,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/2, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::LDRB), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 112,
- OPC_CheckPredicate, 34,
- OPC_Scope, 35,
- OPC_CheckPredicate, 35,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
+ OPC_Scope, 28,
+ OPC_CheckPredicate, 28,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/5, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::LDRH), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 28,
+ OPC_CheckPredicate, 29,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::LDRB), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 64,
+ OPC_CheckPredicate, 30,
OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/2, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::LDRB), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 35,
- OPC_CheckPredicate, 36,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
+ OPC_Scope, 28,
+ OPC_CheckPredicate, 31,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/5, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::LDRSH), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 28,
+ OPC_CheckPredicate, 32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/5, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::LDRSB), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 32,
+ OPC_CheckPredicate, 27,
+ OPC_CheckPredicate, 33,
OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 5,
OPC_CheckComplexPat, /*CP*/2, /*#*/1,
@@ -11739,238 +11640,166 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::LDRB), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 35,
- OPC_CheckPredicate, 37,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/5, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::LDRH), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 0,
- 35,
- OPC_CheckPredicate, 26,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/6, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDR), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 112,
- OPC_CheckPredicate, 27,
- OPC_Scope, 35,
- OPC_CheckPredicate, 29,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/7, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDRB), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 35,
- OPC_CheckPredicate, 28,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/8, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDRH), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 35,
- OPC_CheckPredicate, 33,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
+ 93,
+ OPC_CheckPredicate, 34,
OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/7, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDRB), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 0,
- 112,
- OPC_CheckPredicate, 34,
- OPC_Scope, 35,
- OPC_CheckPredicate, 35,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/7, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDRB), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 35,
- OPC_CheckPredicate, 36,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
+ OPC_Scope, 28,
+ OPC_CheckPredicate, 35,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::LDRB), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 28,
+ OPC_CheckPredicate, 36,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::LDRB), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 28,
+ OPC_CheckPredicate, 37,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/5, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::LDRH), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 30,
+ OPC_CheckPredicate, 26,
OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/7, /*#*/1,
+ OPC_CheckComplexPat, /*CP*/6, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDRB), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDR), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 35,
- OPC_CheckPredicate, 37,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
+ 93,
+ OPC_CheckPredicate, 27,
OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/8, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDRH), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 0,
- 35,
- OPC_CheckPredicate, 26,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_CheckComplexPat, /*CP*/9, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRs), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 76,
- OPC_CheckPredicate, 27,
- OPC_Scope, 35,
- OPC_CheckPredicate, 28,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_CheckComplexPat, /*CP*/9, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRHs), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 35,
- OPC_CheckPredicate, 29,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
+ OPC_Scope, 28,
+ OPC_CheckPredicate, 29,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/7, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDRB), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 28,
+ OPC_CheckPredicate, 28,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/8, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDRH), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 28,
+ OPC_CheckPredicate, 33,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/7, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDRB), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 93,
+ OPC_CheckPredicate, 34,
OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_CheckComplexPat, /*CP*/9, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBs), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 0,
- 76,
- OPC_CheckPredicate, 30,
- OPC_Scope, 35,
- OPC_CheckPredicate, 31,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
+ OPC_Scope, 28,
+ OPC_CheckPredicate, 35,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/7, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDRB), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 28,
+ OPC_CheckPredicate, 36,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/7, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDRB), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 28,
+ OPC_CheckPredicate, 37,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/8, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDRH), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 30,
+ OPC_CheckPredicate, 26,
OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 2,
OPC_CheckComplexPat, /*CP*/9, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRSHs), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRs), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 35,
- OPC_CheckPredicate, 32,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
+ 64,
+ OPC_CheckPredicate, 27,
OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_CheckComplexPat, /*CP*/9, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRSBs), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 0,
- 37,
- OPC_CheckPredicate, 27,
- OPC_CheckPredicate, 33,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_CheckComplexPat, /*CP*/9, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBs), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 112,
- OPC_CheckPredicate, 34,
- OPC_Scope, 35,
- OPC_CheckPredicate, 35,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
+ OPC_Scope, 28,
+ OPC_CheckPredicate, 28,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/9, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRHs), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 28,
+ OPC_CheckPredicate, 29,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/9, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBs), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 64,
+ OPC_CheckPredicate, 30,
OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_CheckComplexPat, /*CP*/9, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBs), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 35,
- OPC_CheckPredicate, 36,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
+ OPC_Scope, 28,
+ OPC_CheckPredicate, 31,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/9, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRSHs), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 28,
+ OPC_CheckPredicate, 32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/9, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRSBs), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 32,
+ OPC_CheckPredicate, 27,
+ OPC_CheckPredicate, 33,
OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 2,
OPC_CheckComplexPat, /*CP*/9, /*#*/1,
@@ -11979,360 +11808,251 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBs), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 35,
- OPC_CheckPredicate, 37,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
+ 93,
+ OPC_CheckPredicate, 34,
OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_CheckComplexPat, /*CP*/9, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRHs), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 0,
- 32|128,2,
- OPC_CheckPredicate, 30,
- OPC_Scope, 54,
- OPC_CheckPredicate, 32,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 1,
- OPC_CheckComplexPat, /*CP*/7, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_EmitNode, TARGET_OPCODE(ARM::tLDRB), 0|OPFL_Chain,
- 1, MVT::i32, 5, 2, 3, 4, 5, 6,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_EmitNode, TARGET_OPCODE(ARM::tSXTB), 0|OPFL_MemRefs,
- 1, MVT::i32, 3, 7, 8, 9,
- OPC_CompleteMatch, 1, 10,
-
- 54,
- OPC_CheckPredicate, 31,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 1,
- OPC_CheckComplexPat, /*CP*/8, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_EmitNode, TARGET_OPCODE(ARM::tLDRH), 0|OPFL_Chain,
- 1, MVT::i32, 5, 2, 3, 4, 5, 6,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_EmitNode, TARGET_OPCODE(ARM::tSXTH), 0|OPFL_MemRefs,
- 1, MVT::i32, 3, 7, 8, 9,
- OPC_CompleteMatch, 1, 10,
-
- 86,
- OPC_CheckPredicate, 32,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/7, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitRegister, MVT::i32, ARM::CPSR,
- OPC_EmitRegister, MVT::i32, ARM::CPSR,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_EmitNode, TARGET_OPCODE(ARM::tLDRB), 0|OPFL_Chain,
- 1, MVT::i32, 5, 2, 3, 4, 7, 8,
- OPC_EmitInteger, MVT::i32, 24,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_EmitNode, TARGET_OPCODE(ARM::tLSLri), 0,
- 1, MVT::i32, 5, 6, 9, 10, 11, 12,
- OPC_EmitInteger, MVT::i32, 24,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_EmitNode, TARGET_OPCODE(ARM::tASRri), 0|OPFL_MemRefs,
- 1, MVT::i32, 5, 5, 13, 14, 15, 16,
- OPC_CompleteMatch, 1, 17,
-
- 86,
- OPC_CheckPredicate, 31,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/7, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitRegister, MVT::i32, ARM::CPSR,
- OPC_EmitRegister, MVT::i32, ARM::CPSR,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_EmitNode, TARGET_OPCODE(ARM::tLDRH), 0|OPFL_Chain,
- 1, MVT::i32, 5, 2, 3, 4, 7, 8,
- OPC_EmitInteger, MVT::i32, 16,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_EmitNode, TARGET_OPCODE(ARM::tLSLri), 0,
- 1, MVT::i32, 5, 6, 9, 10, 11, 12,
- OPC_EmitInteger, MVT::i32, 16,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_EmitNode, TARGET_OPCODE(ARM::tASRri), 0|OPFL_MemRefs,
- 1, MVT::i32, 5, 5, 13, 14, 15, 16,
- OPC_CompleteMatch, 1, 17,
-
- 0,
- 74,
- OPC_CheckPredicate, 34,
- OPC_Scope, 34,
- OPC_CheckPredicate, 36,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/3, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICLDRB), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 4, 2, 3, 4, 5,
- 34,
- OPC_CheckPredicate, 37,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/3, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICLDRH), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 4, 2, 3, 4, 5,
- 0,
- 90,
- OPC_CheckPredicate, 26,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_Scope, 25,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/10, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDRspi), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 4, 2, 3, 4, 5,
- 52,
- OPC_CheckPatternPredicate, 2,
- OPC_Scope, 23,
- OPC_CheckComplexPat, /*CP*/11, /*#*/1,
+ OPC_Scope, 28,
+ OPC_CheckPredicate, 35,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/9, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRi12), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 4, 2, 3, 4, 5,
- 23,
- OPC_CheckComplexPat, /*CP*/12, /*#*/1,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBs), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 28,
+ OPC_CheckPredicate, 36,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/9, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 4, 2, 3, 4, 5,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBs), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
+ 28,
+ OPC_CheckPredicate, 37,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/9, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRHs), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
0,
- 0,
- 0|128,1,
- OPC_CheckPredicate, 27,
- OPC_Scope, 61,
- OPC_CheckPredicate, 28,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
+ 6|128,2,
+ OPC_CheckPredicate, 30,
OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_Scope, 23,
- OPC_CheckComplexPat, /*CP*/11, /*#*/1,
+ OPC_Scope, 47,
+ OPC_CheckPredicate, 32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/7, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRHi12), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 4, 2, 3, 4, 5,
- 23,
- OPC_CheckComplexPat, /*CP*/12, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitNode, TARGET_OPCODE(ARM::tLDRB), 0|OPFL_Chain,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRHi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 4, 2, 3, 4, 5,
- 0,
- 61,
- OPC_CheckPredicate, 29,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_Scope, 23,
- OPC_CheckComplexPat, /*CP*/11, /*#*/1,
+ OPC_EmitNode, TARGET_OPCODE(ARM::tSXTB), 0|OPFL_MemRefs,
+ 1, MVT::i32, 3, 7, 8, 9,
+ OPC_CompleteMatch, 1, 10,
+
+ 47,
+ OPC_CheckPredicate, 31,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/8, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBi12), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 4, 2, 3, 4, 5,
- 23,
- OPC_CheckComplexPat, /*CP*/12, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitNode, TARGET_OPCODE(ARM::tLDRH), 0|OPFL_Chain,
+ 1, MVT::i32, 5, 2, 3, 4, 5, 6,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 4, 2, 3, 4, 5,
- 0,
- 0,
- 0|128,1,
- OPC_CheckPredicate, 30,
- OPC_Scope, 61,
- OPC_CheckPredicate, 31,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_Scope, 23,
- OPC_CheckComplexPat, /*CP*/11, /*#*/1,
+ OPC_EmitNode, TARGET_OPCODE(ARM::tSXTH), 0|OPFL_MemRefs,
+ 1, MVT::i32, 3, 7, 8, 9,
+ OPC_CompleteMatch, 1, 10,
+
+ 79,
+ OPC_CheckPredicate, 32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/7, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRSHi12), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 4, 2, 3, 4, 5,
- 23,
- OPC_CheckComplexPat, /*CP*/12, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitNode, TARGET_OPCODE(ARM::tLDRB), 0|OPFL_Chain,
+ 1, MVT::i32, 5, 2, 3, 4, 7, 8,
+ OPC_EmitInteger, MVT::i32, 24,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRSHi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 4, 2, 3, 4, 5,
- 0,
- 61,
- OPC_CheckPredicate, 32,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_Scope, 23,
- OPC_CheckComplexPat, /*CP*/11, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitNode, TARGET_OPCODE(ARM::tLSLri), 0,
+ 1, MVT::i32, 5, 6, 9, 10, 11, 12,
+ OPC_EmitInteger, MVT::i32, 24,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRSBi12), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 4, 2, 3, 4, 5,
- 23,
- OPC_CheckComplexPat, /*CP*/12, /*#*/1,
+ OPC_EmitNode, TARGET_OPCODE(ARM::tASRri), 0|OPFL_MemRefs,
+ 1, MVT::i32, 5, 5, 13, 14, 15, 16,
+ OPC_CompleteMatch, 1, 17,
+
+ 79,
+ OPC_CheckPredicate, 31,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/7, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRSBi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 4, 2, 3, 4, 5,
+ OPC_EmitNode, TARGET_OPCODE(ARM::tLDRH), 0|OPFL_Chain,
+ 1, MVT::i32, 5, 2, 3, 4, 7, 8,
+ OPC_EmitInteger, MVT::i32, 16,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::tLSLri), 0,
+ 1, MVT::i32, 5, 6, 9, 10, 11, 12,
+ OPC_EmitInteger, MVT::i32, 16,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitNode, TARGET_OPCODE(ARM::tASRri), 0|OPFL_MemRefs,
+ 1, MVT::i32, 5, 5, 13, 14, 15, 16,
+ OPC_CompleteMatch, 1, 17,
+
0,
- 0,
- 63,
- OPC_CheckPredicate, 27,
- OPC_CheckPredicate, 33,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_Scope, 23,
- OPC_CheckComplexPat, /*CP*/11, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBi12), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 4, 2, 3, 4, 5,
- 23,
- OPC_CheckComplexPat, /*CP*/12, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 4, 2, 3, 4, 5,
- 0,
- 62|128,1,
- OPC_CheckPredicate, 34,
- OPC_Scope, 61,
- OPC_CheckPredicate, 35,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
+ 62,
+ OPC_CheckPredicate, 34,
OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_Scope, 23,
- OPC_CheckComplexPat, /*CP*/11, /*#*/1,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 36,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBi12), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICLDRB), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 4, 2, 3, 4, 5,
- 23,
- OPC_CheckComplexPat, /*CP*/12, /*#*/1,
+ 27,
+ OPC_CheckPredicate, 37,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBi8), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICLDRH), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 4, 2, 3, 4, 5,
0,
- 61,
- OPC_CheckPredicate, 36,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
+ 85,
+ OPC_CheckPredicate, 26,
OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_Scope, 23,
- OPC_CheckComplexPat, /*CP*/11, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBi12), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 4, 2, 3, 4, 5,
- 23,
- OPC_CheckComplexPat, /*CP*/12, /*#*/1,
+ OPC_Scope, 25,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/10, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBi8), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLDRspi), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 4, 2, 3, 4, 5,
+ 52,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 23,
+ OPC_CheckComplexPat, /*CP*/11, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRi12), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 23,
+ OPC_CheckComplexPat, /*CP*/12, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 0,
0,
- 61,
- OPC_CheckPredicate, 37,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
+ 116,
+ OPC_CheckPredicate, 27,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 54,
+ OPC_CheckPredicate, 28,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 23,
+ OPC_CheckComplexPat, /*CP*/11, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRHi12), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 23,
+ OPC_CheckComplexPat, /*CP*/12, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRHi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 0,
+ 54,
+ OPC_CheckPredicate, 29,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 23,
+ OPC_CheckComplexPat, /*CP*/11, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBi12), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 23,
+ OPC_CheckComplexPat, /*CP*/12, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 0,
+ 0,
+ 116,
+ OPC_CheckPredicate, 30,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 54,
+ OPC_CheckPredicate, 31,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 23,
+ OPC_CheckComplexPat, /*CP*/11, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRSHi12), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 23,
+ OPC_CheckComplexPat, /*CP*/12, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRSHi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 0,
+ 54,
+ OPC_CheckPredicate, 32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 23,
+ OPC_CheckComplexPat, /*CP*/11, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRSBi12), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 23,
+ OPC_CheckComplexPat, /*CP*/12, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRSBi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 0,
+ 0,
+ 58,
+ OPC_CheckPredicate, 27,
+ OPC_CheckPredicate, 33,
OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 2,
OPC_Scope, 23,
@@ -12340,24 +12060,76 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRHi12), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBi12), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 4, 2, 3, 4, 5,
23,
OPC_CheckComplexPat, /*CP*/12, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRHi8), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBi8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 4, 2, 3, 4, 5,
0,
- 0,
- 25|128,1,
- OPC_CheckPredicate, 26,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_Scope, 86,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
+ 43|128,1,
+ OPC_CheckPredicate, 34,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 54,
+ OPC_CheckPredicate, 35,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 23,
+ OPC_CheckComplexPat, /*CP*/11, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBi12), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 23,
+ OPC_CheckComplexPat, /*CP*/12, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 0,
+ 54,
+ OPC_CheckPredicate, 36,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 23,
+ OPC_CheckComplexPat, /*CP*/11, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBi12), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 23,
+ OPC_CheckComplexPat, /*CP*/12, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 0,
+ 54,
+ OPC_CheckPredicate, 37,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 23,
+ OPC_CheckComplexPat, /*CP*/11, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRHi12), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 23,
+ OPC_CheckComplexPat, /*CP*/12, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRHi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 2, 3, 4, 5,
+ 0,
+ 0,
+ 85,
+ OPC_CheckPredicate, 26,
OPC_SwitchType , 25, MVT::f64,
OPC_CheckPatternPredicate, 8,
OPC_CheckComplexPat, /*CP*/13, /*#*/1,
@@ -12383,15 +12155,19 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VLDRQ), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2f64, 4, 2, 3, 4, 5,
0,
- 59,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ARMISD::Wrapper,
- OPC_RecordChild0,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::TargetConstantPool,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
+ 0,
+ 19|128,2,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ARMISD::Wrapper,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::TargetConstantPool,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 25,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 48,
+ OPC_CheckPredicate, 26,
OPC_Scope, 21,
OPC_CheckPatternPredicate, 6,
OPC_EmitMergeInputChains, 1, 0,
@@ -12407,709 +12183,462 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRpci), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 3, 1, 2, 3,
0,
- 0,
- 82,
- OPC_CheckPredicate, 27,
- OPC_Scope, 38,
- OPC_CheckPredicate, 28,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ARMISD::Wrapper,
- OPC_RecordChild0,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::TargetConstantPool,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRHpci), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 3, 1, 2, 3,
- 38,
- OPC_CheckPredicate, 29,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ARMISD::Wrapper,
- OPC_RecordChild0,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::TargetConstantPool,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBpci), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 3, 1, 2, 3,
- 0,
- 82,
- OPC_CheckPredicate, 30,
- OPC_Scope, 38,
- OPC_CheckPredicate, 31,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ARMISD::Wrapper,
- OPC_RecordChild0,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::TargetConstantPool,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRSHpci), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 3, 1, 2, 3,
- 38,
- OPC_CheckPredicate, 32,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ARMISD::Wrapper,
- OPC_RecordChild0,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::TargetConstantPool,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRSBpci), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 3, 1, 2, 3,
- 0,
- 40,
- OPC_CheckPredicate, 27,
- OPC_CheckPredicate, 33,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ARMISD::Wrapper,
- OPC_RecordChild0,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::TargetConstantPool,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBpci), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 3, 1, 2, 3,
- 121,
- OPC_CheckPredicate, 34,
- OPC_Scope, 38,
- OPC_CheckPredicate, 35,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ARMISD::Wrapper,
- OPC_RecordChild0,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::TargetConstantPool,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBpci), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 3, 1, 2, 3,
- 38,
- OPC_CheckPredicate, 36,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ARMISD::Wrapper,
- OPC_RecordChild0,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::TargetConstantPool,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBpci), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 3, 1, 2, 3,
- 38,
- OPC_CheckPredicate, 37,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ARMISD::Wrapper,
- OPC_RecordChild0,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::TargetConstantPool,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRHpci), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 3, 1, 2, 3,
- 0,
- 0,
- 44|128,10, ISD::STORE,
- OPC_Scope, 81|128,3,
- OPC_CheckPredicate, 38,
- OPC_Scope, 35,
- OPC_CheckPredicate, 39,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/3, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICSTR), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 1, 3, 4, 5, 6,
- 76,
- OPC_CheckPredicate, 40,
- OPC_Scope, 35,
- OPC_CheckPredicate, 41,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/3, /*#*/2,
+ 52,
+ OPC_CheckPredicate, 27,
+ OPC_Scope, 23,
+ OPC_CheckPredicate, 28,
+ OPC_CheckPatternPredicate, 2,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICSTRH), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 1, 3, 4, 5, 6,
- 35,
- OPC_CheckPredicate, 42,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/3, /*#*/2,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRHpci), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 1, 2, 3,
+ 23,
+ OPC_CheckPredicate, 29,
+ OPC_CheckPatternPredicate, 2,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICSTRB), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 1, 3, 4, 5, 6,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBpci), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 1, 2, 3,
0,
- 36,
- OPC_CheckPredicate, 39,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/2, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::STR), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 1, 3, 4, 5, 6, 7,
- 78,
- OPC_CheckPredicate, 40,
- OPC_Scope, 36,
- OPC_CheckPredicate, 41,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/5, /*#*/2,
+ 52,
+ OPC_CheckPredicate, 30,
+ OPC_Scope, 23,
+ OPC_CheckPredicate, 31,
+ OPC_CheckPatternPredicate, 2,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::STRH), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 1, 3, 4, 5, 6, 7,
- 36,
- OPC_CheckPredicate, 42,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/2, /*#*/2,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRSHpci), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 1, 2, 3,
+ 23,
+ OPC_CheckPredicate, 32,
+ OPC_CheckPatternPredicate, 2,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::STRB), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 1, 3, 4, 5, 6, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRSBpci), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 1, 2, 3,
0,
- 36,
- OPC_CheckPredicate, 39,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::i32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/6, /*#*/2,
+ 25,
+ OPC_CheckPredicate, 27,
+ OPC_CheckPredicate, 33,
+ OPC_CheckPatternPredicate, 2,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::tSTR), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 1, 3, 4, 5, 6, 7,
- 78,
- OPC_CheckPredicate, 40,
- OPC_Scope, 36,
- OPC_CheckPredicate, 42,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::i32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/7, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::tSTRB), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 1, 3, 4, 5, 6, 7,
- 36,
- OPC_CheckPredicate, 41,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::i32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/8, /*#*/2,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBpci), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 1, 2, 3,
+ 76,
+ OPC_CheckPredicate, 34,
+ OPC_Scope, 23,
+ OPC_CheckPredicate, 35,
+ OPC_CheckPatternPredicate, 2,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::tSTRH), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 1, 3, 4, 5, 6, 7,
- 0,
- 36,
- OPC_CheckPredicate, 39,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_CheckComplexPat, /*CP*/9, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRs), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 1, 3, 4, 5, 6, 7,
- 78,
- OPC_CheckPredicate, 40,
- OPC_Scope, 36,
- OPC_CheckPredicate, 42,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBpci), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 1, 2, 3,
+ 23,
+ OPC_CheckPredicate, 36,
OPC_CheckPatternPredicate, 2,
- OPC_CheckComplexPat, /*CP*/9, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRBs), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 1, 3, 4, 5, 6, 7,
- 36,
- OPC_CheckPredicate, 41,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRBpci), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 1, 2, 3,
+ 23,
+ OPC_CheckPredicate, 37,
OPC_CheckPatternPredicate, 2,
- OPC_CheckComplexPat, /*CP*/9, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRHs), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 1, 3, 4, 5, 6, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LDRHpci), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 1, 2, 3,
0,
0,
- 86,
- OPC_CheckPredicate, 43,
- OPC_Scope, 40,
- OPC_CheckPredicate, 44,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_RecordChild3,
- OPC_CheckChild3Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/15, /*#*/3,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::STR_PRE), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 1, 2, 4, 5, 6, 7,
- 40,
- OPC_CheckPredicate, 45,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_RecordChild3,
- OPC_CheckChild3Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/15, /*#*/3,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::STR_POST), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 1, 2, 4, 5, 6, 7,
- 0,
- 48|128,1,
- OPC_CheckPredicate, 46,
- OPC_Scope, 42,
- OPC_CheckPredicate, 47,
- OPC_CheckPredicate, 48,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_RecordChild3,
- OPC_CheckChild3Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/16, /*#*/3,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::STRH_PRE), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 1, 2, 4, 5, 6, 7,
- 42,
- OPC_CheckPredicate, 49,
- OPC_CheckPredicate, 50,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_RecordChild3,
- OPC_CheckChild3Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/16, /*#*/3,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::STRH_POST), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 1, 2, 4, 5, 6, 7,
- 42,
- OPC_CheckPredicate, 47,
- OPC_CheckPredicate, 51,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_RecordChild3,
- OPC_CheckChild3Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/15, /*#*/3,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::STRB_PRE), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 1, 2, 4, 5, 6, 7,
- 42,
- OPC_CheckPredicate, 49,
- OPC_CheckPredicate, 52,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_RecordChild3,
- OPC_CheckChild3Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/15, /*#*/3,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::STRB_POST), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 1, 2, 4, 5, 6, 7,
- 0,
- 73|128,2,
- OPC_CheckPredicate, 38,
- OPC_Scope, 91,
- OPC_CheckPredicate, 39,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
+ 0,
+ 83|128,8, ISD::STORE,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_Scope, 99|128,7,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_Scope, 115|128,2,
OPC_CheckChild2Type, MVT::i32,
- OPC_Scope, 25,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/10, /*#*/2,
+ OPC_CheckPredicate, 38,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 39,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::tSTRspi), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICSTR), 0|OPFL_Chain|OPFL_MemRefs,
0, 5, 1, 3, 4, 5, 6,
- 52,
- OPC_CheckPatternPredicate, 2,
- OPC_Scope, 23,
- OPC_CheckComplexPat, /*CP*/11, /*#*/2,
+ 60,
+ OPC_CheckPredicate, 40,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 41,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRi12), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICSTRH), 0|OPFL_Chain|OPFL_MemRefs,
0, 5, 1, 3, 4, 5, 6,
- 23,
- OPC_CheckComplexPat, /*CP*/12, /*#*/2,
+ 27,
+ OPC_CheckPredicate, 42,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRi8), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::PICSTRB), 0|OPFL_Chain|OPFL_MemRefs,
0, 5, 1, 3, 4, 5, 6,
0,
- 0,
- 2|128,1,
- OPC_CheckPredicate, 40,
- OPC_Scope, 62,
- OPC_CheckPredicate, 42,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_Scope, 23,
- OPC_CheckComplexPat, /*CP*/11, /*#*/2,
+ 28,
+ OPC_CheckPredicate, 39,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::STR), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 1, 3, 4, 5, 6, 7,
+ 62,
+ OPC_CheckPredicate, 40,
+ OPC_Scope, 28,
+ OPC_CheckPredicate, 41,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/5, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRBi12), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 1, 3, 4, 5, 6,
- 23,
- OPC_CheckComplexPat, /*CP*/12, /*#*/2,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::STRH), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 1, 3, 4, 5, 6, 7,
+ 28,
+ OPC_CheckPredicate, 42,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRBi8), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 1, 3, 4, 5, 6,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::STRB), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 1, 3, 4, 5, 6, 7,
0,
+ 28,
+ OPC_CheckPredicate, 39,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/6, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tSTR), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 1, 3, 4, 5, 6, 7,
62,
- OPC_CheckPredicate, 41,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_Scope, 23,
- OPC_CheckComplexPat, /*CP*/11, /*#*/2,
+ OPC_CheckPredicate, 40,
+ OPC_Scope, 28,
+ OPC_CheckPredicate, 42,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/7, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRHi12), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 1, 3, 4, 5, 6,
- 23,
- OPC_CheckComplexPat, /*CP*/12, /*#*/2,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tSTRB), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 1, 3, 4, 5, 6, 7,
+ 28,
+ OPC_CheckPredicate, 41,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/8, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRHi8), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 1, 3, 4, 5, 6,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tSTRH), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 1, 3, 4, 5, 6, 7,
0,
- 0,
- 100,
- OPC_CheckPredicate, 39,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_Scope, 30,
- OPC_CheckChild1Type, MVT::f64,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::i32,
- OPC_CheckPatternPredicate, 8,
- OPC_CheckComplexPat, /*CP*/13, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSTRD), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 1, 3, 4, 5, 6,
- 30,
- OPC_CheckChild1Type, MVT::f32,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::i32,
- OPC_CheckPatternPredicate, 8,
- OPC_CheckComplexPat, /*CP*/13, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSTRS), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 1, 3, 4, 5, 6,
- 30,
- OPC_CheckChild1Type, MVT::v2f64,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::i32,
- OPC_CheckPatternPredicate, 3,
- OPC_CheckComplexPat, /*CP*/14, /*#*/2,
+ 28,
+ OPC_CheckPredicate, 39,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/9, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSTRQ), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 1, 3, 4, 5, 6,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRs), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 1, 3, 4, 5, 6, 7,
+ 62,
+ OPC_CheckPredicate, 40,
+ OPC_Scope, 28,
+ OPC_CheckPredicate, 42,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/9, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRBs), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 1, 3, 4, 5, 6, 7,
+ 28,
+ OPC_CheckPredicate, 41,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/9, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRHs), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 1, 3, 4, 5, 6, 7,
+ 0,
0,
- 0,
- 84,
- OPC_CheckPredicate, 43,
- OPC_Scope, 39,
- OPC_CheckPredicate, 44,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_RecordChild3,
- OPC_CheckChild3Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_CheckComplexPat, /*CP*/17, /*#*/3,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STR_PRE), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 1, 2, 4, 5, 6,
- 39,
- OPC_CheckPredicate, 45,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_RecordChild3,
- OPC_CheckChild3Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_CheckComplexPat, /*CP*/17, /*#*/3,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STR_POST), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 1, 2, 4, 5, 6,
- 0,
- 44|128,1,
- OPC_CheckPredicate, 46,
- OPC_Scope, 41,
- OPC_CheckPredicate, 47,
- OPC_CheckPredicate, 48,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
+ 78|128,1,
OPC_RecordChild3,
OPC_CheckChild3Type, MVT::i32,
OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_CheckComplexPat, /*CP*/17, /*#*/3,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRH_PRE), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 1, 2, 4, 5, 6,
- 41,
- OPC_CheckPredicate, 49,
- OPC_CheckPredicate, 50,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_RecordChild3,
- OPC_CheckChild3Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_CheckComplexPat, /*CP*/17, /*#*/3,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRH_POST), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 1, 2, 4, 5, 6,
- 41,
- OPC_CheckPredicate, 47,
- OPC_CheckPredicate, 51,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_RecordChild3,
- OPC_CheckChild3Type, MVT::i32,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_CheckComplexPat, /*CP*/17, /*#*/3,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRB_PRE), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 1, 2, 4, 5, 6,
- 41,
- OPC_CheckPredicate, 49,
- OPC_CheckPredicate, 52,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
+ OPC_Scope, 64,
+ OPC_CheckPredicate, 43,
+ OPC_Scope, 29,
+ OPC_CheckPredicate, 44,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/15, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::STR_PRE), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 1, 2, 4, 5, 6, 7,
+ 29,
+ OPC_CheckPredicate, 45,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/15, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::STR_POST), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 1, 2, 4, 5, 6, 7,
+ 0,
+ 4|128,1,
+ OPC_CheckPredicate, 46,
+ OPC_Scope, 31,
+ OPC_CheckPredicate, 47,
+ OPC_CheckPredicate, 48,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/16, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::STRH_PRE), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 1, 2, 4, 5, 6, 7,
+ 31,
+ OPC_CheckPredicate, 49,
+ OPC_CheckPredicate, 50,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/16, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::STRH_POST), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 1, 2, 4, 5, 6, 7,
+ 31,
+ OPC_CheckPredicate, 47,
+ OPC_CheckPredicate, 51,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/15, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::STRB_PRE), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 1, 2, 4, 5, 6, 7,
+ 31,
+ OPC_CheckPredicate, 49,
+ OPC_CheckPredicate, 52,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/15, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::STRB_POST), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 1, 2, 4, 5, 6, 7,
+ 0,
+ 0,
+ 77|128,1,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_CheckPredicate, 38,
+ OPC_Scope, 83,
+ OPC_CheckPredicate, 39,
+ OPC_Scope, 25,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/10, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tSTRspi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 1, 3, 4, 5, 6,
+ 52,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 23,
+ OPC_CheckComplexPat, /*CP*/11, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRi12), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 1, 3, 4, 5, 6,
+ 23,
+ OPC_CheckComplexPat, /*CP*/12, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 1, 3, 4, 5, 6,
+ 0,
+ 0,
+ 114,
+ OPC_CheckPredicate, 40,
+ OPC_Scope, 54,
+ OPC_CheckPredicate, 42,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 23,
+ OPC_CheckComplexPat, /*CP*/11, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRBi12), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 1, 3, 4, 5, 6,
+ 23,
+ OPC_CheckComplexPat, /*CP*/12, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRBi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 1, 3, 4, 5, 6,
+ 0,
+ 54,
+ OPC_CheckPredicate, 41,
+ OPC_CheckPatternPredicate, 2,
+ OPC_Scope, 23,
+ OPC_CheckComplexPat, /*CP*/11, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRHi12), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 1, 3, 4, 5, 6,
+ 23,
+ OPC_CheckComplexPat, /*CP*/12, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRHi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 1, 3, 4, 5, 6,
+ 0,
+ 0,
+ 0,
+ 72|128,1,
OPC_RecordChild3,
OPC_CheckChild3Type, MVT::i32,
OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_CheckComplexPat, /*CP*/17, /*#*/3,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRB_POST), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 1, 2, 4, 5, 6,
+ OPC_Scope, 62,
+ OPC_CheckPredicate, 43,
+ OPC_Scope, 28,
+ OPC_CheckPredicate, 44,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/17, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STR_PRE), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 1, 2, 4, 5, 6,
+ 28,
+ OPC_CheckPredicate, 45,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/17, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STR_POST), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 1, 2, 4, 5, 6,
+ 0,
+ 0|128,1,
+ OPC_CheckPredicate, 46,
+ OPC_Scope, 30,
+ OPC_CheckPredicate, 47,
+ OPC_CheckPredicate, 48,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/17, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRH_PRE), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 1, 2, 4, 5, 6,
+ 30,
+ OPC_CheckPredicate, 49,
+ OPC_CheckPredicate, 50,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/17, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRH_POST), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 1, 2, 4, 5, 6,
+ 30,
+ OPC_CheckPredicate, 47,
+ OPC_CheckPredicate, 51,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/17, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRB_PRE), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 1, 2, 4, 5, 6,
+ 30,
+ OPC_CheckPredicate, 49,
+ OPC_CheckPredicate, 52,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/17, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2STRB_POST), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 1, 2, 4, 5, 6,
+ 0,
+ 0,
0,
+ 34,
+ OPC_CheckChild1Type, MVT::f64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_CheckPredicate, 38,
+ OPC_CheckPredicate, 39,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/13, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSTRD), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 1, 3, 4, 5, 6,
+ 34,
+ OPC_CheckChild1Type, MVT::f32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_CheckPredicate, 38,
+ OPC_CheckPredicate, 39,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/13, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSTRS), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 1, 3, 4, 5, 6,
+ 34,
+ OPC_CheckChild1Type, MVT::v2f64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i32,
+ OPC_CheckPredicate, 38,
+ OPC_CheckPredicate, 39,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/14, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSTRQ), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 1, 3, 4, 5, 6,
0,
71|128,10, ARMISD::CMPZ,
OPC_Scope, 74,
@@ -14165,12 +13694,12 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v4i32, 4, 0, 1, 2, 3,
0,
0,
- 39|128,4, ISD::ADDE,
- OPC_Scope, 35,
+ 106|128,3, ISD::ADDE,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 32,
OPC_CheckPredicate, 55,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
- OPC_RecordChild1,
OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 5,
OPC_CheckComplexPat, /*CP*/1, /*#*/1,
@@ -14179,21 +13708,15 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ADCrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
1, MVT::i32, 7, 0, 2, 3, 4, 5, 6, 7,
- 23,
+ 20,
OPC_CheckPredicate, 56,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
- OPC_RecordChild1,
OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 5,
OPC_CheckComplexPat, /*CP*/1, /*#*/1,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ADCSSrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
1, MVT::i32, 4, 0, 2, 3, 4,
- 35,
+ 32,
OPC_CheckPredicate, 55,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
- OPC_RecordChild1,
OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 5,
OPC_CheckComplexPat, /*CP*/1, /*#*/0,
@@ -14202,21 +13725,15 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ADCrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
1, MVT::i32, 7, 1, 2, 3, 4, 5, 6, 7,
- 23,
+ 20,
OPC_CheckPredicate, 56,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
- OPC_RecordChild1,
OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 5,
OPC_CheckComplexPat, /*CP*/1, /*#*/0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ADCSSrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
1, MVT::i32, 4, 1, 2, 3, 4,
- 34,
+ 31,
OPC_CheckPredicate, 55,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
- OPC_RecordChild1,
OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 2,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -14225,11 +13742,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ADCrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
1, MVT::i32, 6, 0, 2, 3, 4, 5, 6,
- 34,
+ 31,
OPC_CheckPredicate, 56,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
- OPC_RecordChild1,
OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 2,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -14238,11 +13752,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ADCSrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
1, MVT::i32, 6, 0, 2, 3, 4, 5, 6,
- 34,
+ 31,
OPC_CheckPredicate, 55,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
- OPC_RecordChild1,
OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 2,
OPC_CheckComplexPat, /*CP*/0, /*#*/0,
@@ -14251,11 +13762,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ADCrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
1, MVT::i32, 6, 1, 2, 3, 4, 5, 6,
- 34,
+ 31,
OPC_CheckPredicate, 56,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
- OPC_RecordChild1,
OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 2,
OPC_CheckComplexPat, /*CP*/0, /*#*/0,
@@ -14264,76 +13772,55 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ADCSrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
1, MVT::i32, 6, 1, 2, 3, 4, 5, 6,
- 39,
- OPC_CheckPredicate, 55,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
- OPC_RecordChild1,
+ 122,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::Constant,
- OPC_CheckPredicate, 5,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_EmitConvertToTarget, 1,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::ADCri), 0|OPFL_FlagInput|OPFL_FlagOutput,
- 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ OPC_Scope, 51,
+ OPC_CheckPredicate, 5,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 55,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ADCri), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 15,
+ OPC_CheckPredicate, 56,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::ADCSSri), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 2, 0, 2,
+ 0,
+ 63,
+ OPC_CheckPredicate, 4,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 55,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ADCri), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 27,
+ OPC_CheckPredicate, 56,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ADCSri), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 0,
+ 0,
27,
- OPC_CheckPredicate, 56,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckPredicate, 5,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_EmitConvertToTarget, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::ADCSSri), 0|OPFL_FlagInput|OPFL_FlagOutput,
- 1, MVT::i32, 2, 0, 2,
- 39,
- OPC_CheckPredicate, 55,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckPredicate, 4,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_EmitConvertToTarget, 1,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ADCri), 0|OPFL_FlagInput|OPFL_FlagOutput,
- 1, MVT::i32, 5, 0, 2, 3, 4, 5,
- 39,
- OPC_CheckPredicate, 56,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckPredicate, 4,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_EmitConvertToTarget, 1,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ADCSri), 0|OPFL_FlagInput|OPFL_FlagOutput,
- 1, MVT::i32, 5, 0, 2, 3, 4, 5,
- 30,
OPC_CheckPredicate, 55,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
- OPC_RecordChild1,
OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 5,
OPC_EmitInteger, MVT::i32, 14,
@@ -14341,20 +13828,14 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ADCrr), 0|OPFL_FlagInput|OPFL_FlagOutput,
1, MVT::i32, 5, 0, 1, 2, 3, 4,
- 18,
+ 15,
OPC_CheckPredicate, 56,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
- OPC_RecordChild1,
OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 5,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ADCSSrr), 0|OPFL_FlagInput|OPFL_FlagOutput,
1, MVT::i32, 2, 0, 1,
- 30,
+ 27,
OPC_CheckPredicate, 55,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
- OPC_RecordChild1,
OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 2,
OPC_EmitInteger, MVT::i32, 14,
@@ -14362,11 +13843,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ADCrr), 0|OPFL_FlagInput|OPFL_FlagOutput,
1, MVT::i32, 5, 0, 1, 2, 3, 4,
- 30,
+ 27,
OPC_CheckPredicate, 56,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
- OPC_RecordChild1,
OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 2,
OPC_EmitInteger, MVT::i32, 14,
@@ -14374,10 +13852,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2ADCSrr), 0|OPFL_FlagInput|OPFL_FlagOutput,
1, MVT::i32, 5, 0, 1, 2, 3, 4,
- 28,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
- OPC_RecordChild1,
+ 25,
OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 6,
OPC_EmitRegister, MVT::i32, ARM::CPSR,
@@ -14386,220 +13861,180 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(ARM::tADC), 0|OPFL_FlagInput|OPFL_FlagOutput,
1, MVT::i32, 5, 2, 0, 1, 3, 4,
0,
- 8|128,4, ISD::SUBE,
- OPC_Scope, 35,
- OPC_CheckPredicate, 57,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/1, /*#*/1,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::SBCrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
- 1, MVT::i32, 7, 0, 2, 3, 4, 5, 6, 7,
- 23,
- OPC_CheckPredicate, 58,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/1, /*#*/1,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::SBCSSrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
- 1, MVT::i32, 4, 0, 2, 3, 4,
- 81,
- OPC_CheckPredicate, 57,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
+ 96|128,3, ISD::SUBE,
+ OPC_CaptureFlagInput,
+ OPC_RecordChild0,
+ OPC_Scope, 96|128,1,
OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
- OPC_Scope, 43,
+ OPC_Scope, 32,
+ OPC_CheckPredicate, 57,
+ OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/1, /*#*/0,
- OPC_Scope, 23,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SBCrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 7, 0, 2, 3, 4, 5, 6, 7,
+ 20,
+ OPC_CheckPredicate, 58,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SBCSSrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 4, 0, 2, 3, 4,
+ 78,
+ OPC_CheckPredicate, 57,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 43,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/0,
+ OPC_Scope, 23,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::RSCrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 7, 1, 2, 3, 4, 5, 6, 7,
+ 11,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::RSCSrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 4, 1, 2, 3, 4,
+ 0,
+ 27,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::RSCrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
- 1, MVT::i32, 7, 1, 2, 3, 4, 5, 6, 7,
- 11,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::RSCSrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
- 1, MVT::i32, 4, 1, 2, 3, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SBCrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 6, 0, 2, 3, 4, 5, 6,
0,
- 27,
+ 31,
+ OPC_CheckPredicate, 58,
+ OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 2,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SBCrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SBCSrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
1, MVT::i32, 6, 0, 2, 3, 4, 5, 6,
+ 55,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 5,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 57,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SBCri), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 15,
+ OPC_CheckPredicate, 58,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SBCSSri), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 2, 0, 2,
+ 0,
0,
- 34,
- OPC_CheckPredicate, 58,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SBCSrs), 0|OPFL_FlagInput|OPFL_FlagOutput,
- 1, MVT::i32, 6, 0, 2, 3, 4, 5, 6,
- 39,
- OPC_CheckPredicate, 57,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
+ 50,
+ OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::Constant,
OPC_CheckPredicate, 5,
OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_EmitConvertToTarget, 1,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::SBCri), 0|OPFL_FlagInput|OPFL_FlagOutput,
- 1, MVT::i32, 5, 0, 2, 3, 4, 5,
- 27,
- OPC_CheckPredicate, 58,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckPredicate, 5,
- OPC_MoveParent,
+ OPC_CheckPredicate, 57,
OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 5,
- OPC_EmitConvertToTarget, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::SBCSSri), 0|OPFL_FlagInput|OPFL_FlagOutput,
- 1, MVT::i32, 2, 0, 2,
- 91,
- OPC_CheckPredicate, 57,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
- OPC_Scope, 48,
- OPC_MoveChild, 0,
+ OPC_EmitConvertToTarget, 0,
+ OPC_Scope, 21,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::RSCri), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 1, 2, 3, 4, 5,
+ 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::RSCSri), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 2, 1, 2,
+ 0,
+ 69|128,1,
+ OPC_RecordChild1,
+ OPC_Scope, 67,
+ OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::Constant,
- OPC_CheckPredicate, 5,
+ OPC_CheckPredicate, 4,
OPC_MoveParent,
- OPC_RecordChild1,
OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_EmitConvertToTarget, 0,
- OPC_Scope, 21,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 57,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::RSCri), 0|OPFL_FlagInput|OPFL_FlagOutput,
- 1, MVT::i32, 5, 1, 2, 3, 4, 5,
- 9,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::RSCSri), 0|OPFL_FlagInput|OPFL_FlagOutput,
- 1, MVT::i32, 2, 1, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SBCri), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ 27,
+ OPC_CheckPredicate, 58,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitConvertToTarget, 1,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SBCSri), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 0, 2, 3, 4, 5,
0,
- 35,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckPredicate, 4,
- OPC_MoveParent,
+ 27,
+ OPC_CheckPredicate, 57,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SBCrr), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 15,
+ OPC_CheckPredicate, 58,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 5,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::SBCSSrr), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 2, 0, 1,
+ 27,
+ OPC_CheckPredicate, 57,
OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 2,
- OPC_EmitConvertToTarget, 1,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SBCri), 0|OPFL_FlagInput|OPFL_FlagOutput,
- 1, MVT::i32, 5, 0, 2, 3, 4, 5,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SBCrr), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 27,
+ OPC_CheckPredicate, 58,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 2,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SBCSrr), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 0, 1, 2, 3, 4,
+ 25,
+ OPC_CheckType, MVT::i32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitRegister, MVT::i32, ARM::CPSR,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::tSBC), 0|OPFL_FlagInput|OPFL_FlagOutput,
+ 1, MVT::i32, 5, 2, 0, 1, 3, 4,
0,
- 39,
- OPC_CheckPredicate, 58,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckPredicate, 4,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_EmitConvertToTarget, 1,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SBCSri), 0|OPFL_FlagInput|OPFL_FlagOutput,
- 1, MVT::i32, 5, 0, 2, 3, 4, 5,
- 30,
- OPC_CheckPredicate, 57,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::SBCrr), 0|OPFL_FlagInput|OPFL_FlagOutput,
- 1, MVT::i32, 5, 0, 1, 2, 3, 4,
- 18,
- OPC_CheckPredicate, 58,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 5,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::SBCSSrr), 0|OPFL_FlagInput|OPFL_FlagOutput,
- 1, MVT::i32, 2, 0, 1,
- 30,
- OPC_CheckPredicate, 57,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SBCrr), 0|OPFL_FlagInput|OPFL_FlagOutput,
- 1, MVT::i32, 5, 0, 1, 2, 3, 4,
- 30,
- OPC_CheckPredicate, 58,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 2,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2SBCSrr), 0|OPFL_FlagInput|OPFL_FlagOutput,
- 1, MVT::i32, 5, 0, 1, 2, 3, 4,
- 28,
- OPC_CaptureFlagInput,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
- OPC_CheckPatternPredicate, 6,
- OPC_EmitRegister, MVT::i32, ARM::CPSR,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::tSBC), 0|OPFL_FlagInput|OPFL_FlagOutput,
- 1, MVT::i32, 5, 2, 0, 1, 3, 4,
0,
118, ARMISD::PIC_ADD,
OPC_Scope, 67,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 25,
- OPC_CheckPredicate, 26,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
@@ -14610,6 +14045,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::TargetConstantPool,
OPC_MoveParent,
OPC_MoveParent,
+ OPC_CheckPredicate, 25,
+ OPC_CheckPredicate, 26,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 1,
@@ -15513,9 +14950,9 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2CMPrr), 0|OPFL_FlagOutput,
0, 4, 0, 1, 2, 3,
0,
- 15|128,114, ISD::INTRINSIC_WO_CHAIN,
+ 47|128,111, ISD::INTRINSIC_WO_CHAIN,
OPC_MoveChild, 0,
- OPC_Scope, 41|128,5,
+ OPC_Scope, 37|128,5,
OPC_CheckInteger, 68,
OPC_MoveParent,
OPC_Scope, 47|128,1,
@@ -15756,43 +15193,39 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMULHslv4i32), 0,
1, MVT::v4i32, 5, 2, 5, 7, 8, 9,
0,
- 111,
+ 107,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMULHv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMULHv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMULHv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
@@ -15800,7 +15233,7 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v4i32, 4, 0, 1, 2, 3,
0,
0,
- 41|128,5,
+ 37|128,5,
OPC_CheckInteger, 74,
OPC_MoveParent,
OPC_Scope, 47|128,1,
@@ -16041,43 +15474,39 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRDMULHslv4i32), 0,
1, MVT::v4i32, 5, 2, 5, 7, 8, 9,
0,
- 111,
+ 107,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRDMULHv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRDMULHv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRDMULHv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
@@ -16085,7 +15514,7 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v4i32, 4, 0, 1, 2, 3,
0,
0,
- 10|128,2,
+ 7|128,2,
OPC_CheckInteger, 51,
OPC_MoveParent,
OPC_Scope, 89,
@@ -16168,33 +15597,30 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULLslsv2i32), 0,
1, MVT::v2i64, 5, 2, 0, 3, 4, 5,
0,
- 84,
+ 81,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULLsv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i64,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULLsv2i64), 0,
1, MVT::v2i64, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
@@ -16202,7 +15628,7 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v8i16, 4, 0, 1, 2, 3,
0,
0,
- 10|128,2,
+ 7|128,2,
OPC_CheckInteger, 52,
OPC_MoveParent,
OPC_Scope, 89,
@@ -16285,33 +15711,30 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULLsluv2i32), 0,
1, MVT::v2i64, 5, 2, 0, 3, 4, 5,
0,
- 84,
+ 81,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULLuv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i64,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULLuv2i64), 0,
1, MVT::v2i64, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
@@ -16319,7 +15742,7 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v8i16, 4, 0, 1, 2, 3,
0,
0,
- 111|128,1,
+ 109|128,1,
OPC_CheckInteger, 69,
OPC_MoveParent,
OPC_Scope, 89,
@@ -16402,23 +15825,21 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMULLslv2i32), 0,
1, MVT::v2i64, 5, 2, 0, 3, 4, 5,
0,
- 57,
+ 55,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQDMULLv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i64,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
@@ -17444,70 +16865,64 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCVTxu2fq), 0,
1, MVT::v4f32, 4, 0, 2, 3, 4,
0,
- 87,
+ 84,
OPC_CheckInteger, 17,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDLsv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i64,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDLsv2i64), 0,
1, MVT::v2i64, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDLsv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
0,
- 87,
+ 84,
OPC_CheckInteger, 18,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDLuv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i64,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDLuv2i64), 0,
1, MVT::v2i64, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
@@ -17518,651 +16933,603 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckInteger, 19,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
- OPC_CheckChild1Type, MVT::v8i16,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i16,
- OPC_CheckPatternPredicate, 3,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWsv8i16), 0,
- 1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
- OPC_CheckChild1Type, MVT::v4i32,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i32,
- OPC_CheckPatternPredicate, 3,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWsv4i32), 0,
- 1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
- OPC_CheckChild1Type, MVT::v2i64,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i64,
- OPC_CheckPatternPredicate, 3,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWsv2i64), 0,
- 1, MVT::v2i64, 4, 0, 1, 2, 3,
- 26,
- OPC_CheckChild1Type, MVT::v8i8,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
- OPC_CheckPatternPredicate, 3,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWsv8i16), 0,
- 1, MVT::v8i16, 4, 1, 0, 2, 3,
- 26,
- OPC_CheckChild1Type, MVT::v4i16,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
- OPC_CheckPatternPredicate, 3,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWsv4i32), 0,
- 1, MVT::v4i32, 4, 1, 0, 2, 3,
- 26,
- OPC_CheckChild1Type, MVT::v2i32,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::v2i64,
- OPC_CheckType, MVT::v2i64,
- OPC_CheckPatternPredicate, 3,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWsv2i64), 0,
- 1, MVT::v2i64, 4, 1, 0, 2, 3,
+ OPC_SwitchType , 52, MVT::v8i16,
+ OPC_Scope, 24,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWsv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWsv8i16), 0,
+ 1, MVT::v8i16, 4, 1, 0, 2, 3,
+ 0,
+ 52, MVT::v4i32,
+ OPC_Scope, 24,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWsv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWsv4i32), 0,
+ 1, MVT::v4i32, 4, 1, 0, 2, 3,
+ 0,
+ 52, MVT::v2i64,
+ OPC_Scope, 24,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWsv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWsv2i64), 0,
+ 1, MVT::v2i64, 4, 1, 0, 2, 3,
+ 0,
0,
40|128,1,
OPC_CheckInteger, 20,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
- OPC_CheckChild1Type, MVT::v8i16,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i16,
- OPC_CheckPatternPredicate, 3,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWuv8i16), 0,
- 1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
- OPC_CheckChild1Type, MVT::v4i32,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i32,
- OPC_CheckPatternPredicate, 3,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWuv4i32), 0,
- 1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
- OPC_CheckChild1Type, MVT::v2i64,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i64,
- OPC_CheckPatternPredicate, 3,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWuv2i64), 0,
- 1, MVT::v2i64, 4, 0, 1, 2, 3,
- 26,
- OPC_CheckChild1Type, MVT::v8i8,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
- OPC_CheckPatternPredicate, 3,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWuv8i16), 0,
- 1, MVT::v8i16, 4, 1, 0, 2, 3,
- 26,
- OPC_CheckChild1Type, MVT::v4i16,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
- OPC_CheckPatternPredicate, 3,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWuv4i32), 0,
- 1, MVT::v4i32, 4, 1, 0, 2, 3,
- 26,
- OPC_CheckChild1Type, MVT::v2i32,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::v2i64,
- OPC_CheckType, MVT::v2i64,
- OPC_CheckPatternPredicate, 3,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWuv2i64), 0,
- 1, MVT::v2i64, 4, 1, 0, 2, 3,
+ OPC_SwitchType , 52, MVT::v8i16,
+ OPC_Scope, 24,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i8,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWuv8i16), 0,
+ 1, MVT::v8i16, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v8i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWuv8i16), 0,
+ 1, MVT::v8i16, 4, 1, 0, 2, 3,
+ 0,
+ 52, MVT::v4i32,
+ OPC_Scope, 24,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i16,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWuv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v4i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWuv4i32), 0,
+ 1, MVT::v4i32, 4, 1, 0, 2, 3,
+ 0,
+ 52, MVT::v2i64,
+ OPC_Scope, 24,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i32,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWuv2i64), 0,
+ 1, MVT::v2i64, 4, 0, 1, 2, 3,
+ 24,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::v2i64,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDWuv2i64), 0,
+ 1, MVT::v2i64, 4, 1, 0, 2, 3,
+ 0,
0,
- 40|128,1,
+ 34|128,1,
OPC_CheckInteger, 28,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHADDsv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHADDsv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHADDsv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHADDsv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHADDsv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHADDsv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
0,
- 40|128,1,
+ 34|128,1,
OPC_CheckInteger, 29,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHADDuv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHADDuv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHADDuv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHADDuv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHADDuv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHADDuv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
0,
- 40|128,1,
+ 34|128,1,
OPC_CheckInteger, 91,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRHADDsv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRHADDsv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRHADDsv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRHADDsv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRHADDsv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRHADDsv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
0,
- 40|128,1,
+ 34|128,1,
OPC_CheckInteger, 92,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRHADDuv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRHADDuv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRHADDuv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRHADDuv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRHADDuv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRHADDuv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
0,
- 94|128,1,
+ 86|128,1,
OPC_CheckInteger, 64,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDsv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDsv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDsv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDsv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDsv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDsv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v1i64,
OPC_CheckChild1Type, MVT::v1i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v1i64,
- OPC_CheckType, MVT::v1i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDsv1i64), 0,
1, MVT::v1i64, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i64,
OPC_CheckChild1Type, MVT::v2i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i64,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDsv2i64), 0,
1, MVT::v2i64, 4, 0, 1, 2, 3,
0,
- 94|128,1,
+ 86|128,1,
OPC_CheckInteger, 65,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDuv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDuv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDuv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDuv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDuv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDuv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v1i64,
OPC_CheckChild1Type, MVT::v1i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v1i64,
- OPC_CheckType, MVT::v1i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDuv1i64), 0,
1, MVT::v1i64, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i64,
OPC_CheckChild1Type, MVT::v2i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i64,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQADDuv2i64), 0,
1, MVT::v2i64, 4, 0, 1, 2, 3,
0,
- 87,
+ 84,
OPC_CheckInteger, 16,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDHNv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDHNv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i64,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VADDHNv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
0,
- 87,
+ 84,
OPC_CheckInteger, 88,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRADDHNv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRADDHNv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i64,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRADDHNv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
0,
- 60,
+ 58,
OPC_CheckInteger, 53,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULpd), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
@@ -18182,510 +17549,464 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMULLp), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 87,
+ 84,
OPC_CheckInteger, 113,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBLsv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i64,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBLsv2i64), 0,
1, MVT::v2i64, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBLsv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
0,
- 87,
+ 84,
OPC_CheckInteger, 114,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBLuv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i64,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBLuv2i64), 0,
1, MVT::v2i64, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBLuv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
0,
- 87,
+ 84,
OPC_CheckInteger, 115,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBWsv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBWsv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i64,
OPC_CheckChild1Type, MVT::v2i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBWsv2i64), 0,
1, MVT::v2i64, 4, 0, 1, 2, 3,
0,
- 87,
+ 84,
OPC_CheckInteger, 116,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBWuv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBWuv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i64,
OPC_CheckChild1Type, MVT::v2i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBWuv2i64), 0,
1, MVT::v2i64, 4, 0, 1, 2, 3,
0,
- 40|128,1,
+ 34|128,1,
OPC_CheckInteger, 30,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHSUBsv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHSUBsv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHSUBsv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHSUBsv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHSUBsv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHSUBsv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
0,
- 40|128,1,
+ 34|128,1,
OPC_CheckInteger, 31,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHSUBuv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHSUBuv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHSUBuv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHSUBuv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHSUBuv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VHSUBuv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
0,
- 94|128,1,
+ 86|128,1,
OPC_CheckInteger, 86,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBsv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBsv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBsv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBsv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBsv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBsv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v1i64,
OPC_CheckChild1Type, MVT::v1i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v1i64,
- OPC_CheckType, MVT::v1i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBsv1i64), 0,
1, MVT::v1i64, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i64,
OPC_CheckChild1Type, MVT::v2i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i64,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBsv2i64), 0,
1, MVT::v2i64, 4, 0, 1, 2, 3,
0,
- 94|128,1,
+ 86|128,1,
OPC_CheckInteger, 87,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBuv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBuv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBuv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBuv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBuv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBuv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v1i64,
OPC_CheckChild1Type, MVT::v1i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v1i64,
- OPC_CheckType, MVT::v1i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBuv1i64), 0,
1, MVT::v1i64, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i64,
OPC_CheckChild1Type, MVT::v2i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i64,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSUBuv2i64), 0,
1, MVT::v2i64, 4, 0, 1, 2, 3,
0,
- 87,
+ 84,
OPC_CheckInteger, 112,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBHNv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBHNv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i64,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSUBHNv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
0,
- 87,
+ 84,
OPC_CheckInteger, 98,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSUBHNv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSUBHNv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i64,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
@@ -18732,2477 +18053,2241 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VACGTq), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 94|128,1,
+ 86|128,1,
OPC_CheckInteger, 9,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDsv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDsv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDsv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDsv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDsv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDsv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2f32,
OPC_CheckChild1Type, MVT::v2f32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2f32,
- OPC_CheckType, MVT::v2f32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDfd), 0,
1, MVT::v2f32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4f32,
OPC_CheckChild1Type, MVT::v4f32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4f32,
- OPC_CheckType, MVT::v4f32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDfq), 0,
1, MVT::v4f32, 4, 0, 1, 2, 3,
0,
- 40|128,1,
+ 34|128,1,
OPC_CheckInteger, 10,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDuv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDuv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDuv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDuv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDuv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDuv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
0,
- 87,
+ 84,
OPC_CheckInteger, 7,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDLsv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i64,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDLsv2i64), 0,
1, MVT::v2i64, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDLsv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
0,
- 87,
+ 84,
OPC_CheckInteger, 8,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDLuv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i64,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDLuv2i64), 0,
1, MVT::v2i64, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABDLuv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
0,
- 64|128,1,
+ 58|128,1,
OPC_CheckInteger, 5,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 30,
+ OPC_SwitchType , 28, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
OPC_RecordChild3,
OPC_CheckChild3Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABAsv8i8), 0,
1, MVT::v8i8, 5, 0, 1, 2, 3, 4,
- 30,
+ 28, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
OPC_RecordChild3,
OPC_CheckChild3Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABAsv4i16), 0,
1, MVT::v4i16, 5, 0, 1, 2, 3, 4,
- 30,
+ 28, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
OPC_RecordChild3,
OPC_CheckChild3Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABAsv2i32), 0,
1, MVT::v2i32, 5, 0, 1, 2, 3, 4,
- 30,
+ 28, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v16i8,
OPC_RecordChild3,
OPC_CheckChild3Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABAsv16i8), 0,
1, MVT::v16i8, 5, 0, 1, 2, 3, 4,
- 30,
+ 28, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
OPC_RecordChild3,
OPC_CheckChild3Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABAsv8i16), 0,
1, MVT::v8i16, 5, 0, 1, 2, 3, 4,
- 30,
+ 28, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
OPC_RecordChild3,
OPC_CheckChild3Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABAsv4i32), 0,
1, MVT::v4i32, 5, 0, 1, 2, 3, 4,
0,
- 64|128,1,
+ 58|128,1,
OPC_CheckInteger, 6,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 30,
+ OPC_SwitchType , 28, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
OPC_RecordChild3,
OPC_CheckChild3Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABAuv8i8), 0,
1, MVT::v8i8, 5, 0, 1, 2, 3, 4,
- 30,
+ 28, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
OPC_RecordChild3,
OPC_CheckChild3Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABAuv4i16), 0,
1, MVT::v4i16, 5, 0, 1, 2, 3, 4,
- 30,
+ 28, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
OPC_RecordChild3,
OPC_CheckChild3Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABAuv2i32), 0,
1, MVT::v2i32, 5, 0, 1, 2, 3, 4,
- 30,
+ 28, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v16i8,
OPC_RecordChild3,
OPC_CheckChild3Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABAuv16i8), 0,
1, MVT::v16i8, 5, 0, 1, 2, 3, 4,
- 30,
+ 28, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
OPC_RecordChild3,
OPC_CheckChild3Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABAuv8i16), 0,
1, MVT::v8i16, 5, 0, 1, 2, 3, 4,
- 30,
+ 28, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
OPC_RecordChild3,
OPC_CheckChild3Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABAuv4i32), 0,
1, MVT::v4i32, 5, 0, 1, 2, 3, 4,
0,
- 99,
+ 96,
OPC_CheckInteger, 3,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 30,
+ OPC_SwitchType , 28, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
OPC_RecordChild3,
OPC_CheckChild3Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABALsv4i32), 0,
1, MVT::v4i32, 5, 0, 1, 2, 3, 4,
- 30,
+ 28, MVT::v2i64,
OPC_CheckChild1Type, MVT::v2i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
OPC_RecordChild3,
OPC_CheckChild3Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABALsv2i64), 0,
1, MVT::v2i64, 5, 0, 1, 2, 3, 4,
- 30,
+ 28, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
OPC_RecordChild3,
OPC_CheckChild3Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABALsv8i16), 0,
1, MVT::v8i16, 5, 0, 1, 2, 3, 4,
0,
- 99,
+ 96,
OPC_CheckInteger, 4,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 30,
+ OPC_SwitchType , 28, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
OPC_RecordChild3,
OPC_CheckChild3Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABALuv4i32), 0,
1, MVT::v4i32, 5, 0, 1, 2, 3, 4,
- 30,
+ 28, MVT::v2i64,
OPC_CheckChild1Type, MVT::v2i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
OPC_RecordChild3,
OPC_CheckChild3Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABALuv2i64), 0,
1, MVT::v2i64, 5, 0, 1, 2, 3, 4,
- 30,
+ 28, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
OPC_RecordChild3,
OPC_CheckChild3Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABALuv8i16), 0,
1, MVT::v8i16, 5, 0, 1, 2, 3, 4,
0,
- 94|128,1,
+ 86|128,1,
OPC_CheckInteger, 39,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMAXsv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMAXsv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMAXsv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMAXsv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMAXsv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMAXsv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2f32,
OPC_CheckChild1Type, MVT::v2f32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2f32,
- OPC_CheckType, MVT::v2f32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMAXfd), 0,
1, MVT::v2f32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4f32,
OPC_CheckChild1Type, MVT::v4f32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4f32,
- OPC_CheckType, MVT::v4f32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMAXfq), 0,
1, MVT::v4f32, 4, 0, 1, 2, 3,
0,
- 40|128,1,
+ 34|128,1,
OPC_CheckInteger, 40,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMAXuv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMAXuv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMAXuv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMAXuv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMAXuv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMAXuv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
0,
- 94|128,1,
+ 86|128,1,
OPC_CheckInteger, 41,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMINsv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMINsv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMINsv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMINsv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMINsv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMINsv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2f32,
OPC_CheckChild1Type, MVT::v2f32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2f32,
- OPC_CheckType, MVT::v2f32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMINfd), 0,
1, MVT::v2f32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4f32,
OPC_CheckChild1Type, MVT::v4f32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4f32,
- OPC_CheckType, MVT::v4f32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMINfq), 0,
1, MVT::v4f32, 4, 0, 1, 2, 3,
0,
- 40|128,1,
+ 34|128,1,
OPC_CheckInteger, 42,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMINuv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMINuv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMINuv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMINuv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMINuv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMINuv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
0,
- 114,
+ 110,
OPC_CheckInteger, 56,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDi8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDi16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDi32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2f32,
OPC_CheckChild1Type, MVT::v2f32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2f32,
- OPC_CheckType, MVT::v2f32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDf), 0,
1, MVT::v2f32, 4, 0, 1, 2, 3,
0,
- 16|128,1,
+ 10|128,1,
OPC_CheckInteger, 57,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 22,
+ OPC_SwitchType , 20, MVT::v4i16,
OPC_CheckChild1Type, MVT::v8i8,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDLsv8i8), 0,
1, MVT::v4i16, 3, 0, 1, 2,
- 22,
+ 20, MVT::v2i32,
OPC_CheckChild1Type, MVT::v4i16,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDLsv4i16), 0,
1, MVT::v2i32, 3, 0, 1, 2,
- 22,
+ 20, MVT::v1i64,
OPC_CheckChild1Type, MVT::v2i32,
- OPC_CheckType, MVT::v1i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDLsv2i32), 0,
1, MVT::v1i64, 3, 0, 1, 2,
- 22,
+ 20, MVT::v8i16,
OPC_CheckChild1Type, MVT::v16i8,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDLsv16i8), 0,
1, MVT::v8i16, 3, 0, 1, 2,
- 22,
+ 20, MVT::v4i32,
OPC_CheckChild1Type, MVT::v8i16,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDLsv8i16), 0,
1, MVT::v4i32, 3, 0, 1, 2,
- 22,
+ 20, MVT::v2i64,
OPC_CheckChild1Type, MVT::v4i32,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDLsv4i32), 0,
1, MVT::v2i64, 3, 0, 1, 2,
0,
- 16|128,1,
+ 10|128,1,
OPC_CheckInteger, 58,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 22,
+ OPC_SwitchType , 20, MVT::v4i16,
OPC_CheckChild1Type, MVT::v8i8,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDLuv8i8), 0,
1, MVT::v4i16, 3, 0, 1, 2,
- 22,
+ 20, MVT::v2i32,
OPC_CheckChild1Type, MVT::v4i16,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDLuv4i16), 0,
1, MVT::v2i32, 3, 0, 1, 2,
- 22,
+ 20, MVT::v1i64,
OPC_CheckChild1Type, MVT::v2i32,
- OPC_CheckType, MVT::v1i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDLuv2i32), 0,
1, MVT::v1i64, 3, 0, 1, 2,
- 22,
+ 20, MVT::v8i16,
OPC_CheckChild1Type, MVT::v16i8,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDLuv16i8), 0,
1, MVT::v8i16, 3, 0, 1, 2,
- 22,
+ 20, MVT::v4i32,
OPC_CheckChild1Type, MVT::v8i16,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDLuv8i16), 0,
1, MVT::v4i32, 3, 0, 1, 2,
- 22,
+ 20, MVT::v2i64,
OPC_CheckChild1Type, MVT::v4i32,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADDLuv4i32), 0,
1, MVT::v2i64, 3, 0, 1, 2,
0,
- 40|128,1,
+ 34|128,1,
OPC_CheckInteger, 54,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADALsv8i8), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADALsv4i16), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v1i64,
OPC_CheckChild1Type, MVT::v1i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v1i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADALsv2i32), 0,
1, MVT::v1i64, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v16i8,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADALsv16i8), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADALsv8i16), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i64,
OPC_CheckChild1Type, MVT::v2i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADALsv4i32), 0,
1, MVT::v2i64, 4, 0, 1, 2, 3,
0,
- 40|128,1,
+ 34|128,1,
OPC_CheckInteger, 55,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADALuv8i8), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADALuv4i16), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v1i64,
OPC_CheckChild1Type, MVT::v1i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v1i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADALuv2i32), 0,
1, MVT::v1i64, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v16i8,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADALuv16i8), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADALuv8i16), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i64,
OPC_CheckChild1Type, MVT::v2i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPADALuv4i32), 0,
1, MVT::v2i64, 4, 0, 1, 2, 3,
0,
- 114,
+ 110,
OPC_CheckInteger, 59,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPMAXs8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPMAXs16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPMAXs32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2f32,
OPC_CheckChild1Type, MVT::v2f32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2f32,
- OPC_CheckType, MVT::v2f32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPMAXf), 0,
1, MVT::v2f32, 4, 0, 1, 2, 3,
0,
- 87,
+ 84,
OPC_CheckInteger, 60,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPMAXu8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPMAXu16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPMAXu32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
0,
- 114,
+ 110,
OPC_CheckInteger, 61,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPMINs8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPMINs16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPMINs32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2f32,
OPC_CheckChild1Type, MVT::v2f32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2f32,
- OPC_CheckType, MVT::v2f32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPMINf), 0,
1, MVT::v2f32, 4, 0, 1, 2, 3,
0,
- 87,
+ 84,
OPC_CheckInteger, 62,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPMINu8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPMINu16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VPMINu32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
0,
- 98,
+ 94,
OPC_CheckInteger, 89,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 22,
+ OPC_SwitchType , 20, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRECPEd), 0,
1, MVT::v2i32, 3, 0, 1, 2,
- 22,
+ 20, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRECPEq), 0,
1, MVT::v4i32, 3, 0, 1, 2,
- 22,
+ 20, MVT::v2f32,
OPC_CheckChild1Type, MVT::v2f32,
- OPC_CheckType, MVT::v2f32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRECPEfd), 0,
1, MVT::v2f32, 3, 0, 1, 2,
- 22,
+ 20, MVT::v4f32,
OPC_CheckChild1Type, MVT::v4f32,
- OPC_CheckType, MVT::v4f32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRECPEfq), 0,
1, MVT::v4f32, 3, 0, 1, 2,
0,
- 60,
+ 58,
OPC_CheckInteger, 90,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v2f32,
OPC_CheckChild1Type, MVT::v2f32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2f32,
- OPC_CheckType, MVT::v2f32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRECPSfd), 0,
1, MVT::v2f32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4f32,
OPC_CheckChild1Type, MVT::v4f32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4f32,
- OPC_CheckType, MVT::v4f32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRECPSfq), 0,
1, MVT::v4f32, 4, 0, 1, 2, 3,
0,
- 98,
+ 94,
OPC_CheckInteger, 96,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 22,
+ OPC_SwitchType , 20, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSQRTEd), 0,
1, MVT::v2i32, 3, 0, 1, 2,
- 22,
+ 20, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSQRTEq), 0,
1, MVT::v4i32, 3, 0, 1, 2,
- 22,
+ 20, MVT::v2f32,
OPC_CheckChild1Type, MVT::v2f32,
- OPC_CheckType, MVT::v2f32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSQRTEfd), 0,
1, MVT::v2f32, 3, 0, 1, 2,
- 22,
+ 20, MVT::v4f32,
OPC_CheckChild1Type, MVT::v4f32,
- OPC_CheckType, MVT::v4f32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSQRTEfq), 0,
1, MVT::v4f32, 3, 0, 1, 2,
0,
- 60,
+ 58,
OPC_CheckInteger, 97,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v2f32,
OPC_CheckChild1Type, MVT::v2f32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2f32,
- OPC_CheckType, MVT::v2f32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSQRTSfd), 0,
1, MVT::v2f32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4f32,
OPC_CheckChild1Type, MVT::v4f32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4f32,
- OPC_CheckType, MVT::v4f32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSQRTSfq), 0,
1, MVT::v4f32, 4, 0, 1, 2, 3,
0,
- 94|128,1,
+ 86|128,1,
OPC_CheckInteger, 103,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLsv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLsv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLsv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLsv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLsv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLsv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v1i64,
OPC_CheckChild1Type, MVT::v1i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v1i64,
- OPC_CheckType, MVT::v1i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLsv1i64), 0,
1, MVT::v1i64, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i64,
OPC_CheckChild1Type, MVT::v2i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i64,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLsv2i64), 0,
1, MVT::v2i64, 4, 0, 1, 2, 3,
0,
- 94|128,1,
+ 86|128,1,
OPC_CheckInteger, 104,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLuv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLuv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLuv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLuv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLuv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLuv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v1i64,
OPC_CheckChild1Type, MVT::v1i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v1i64,
- OPC_CheckType, MVT::v1i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLuv1i64), 0,
1, MVT::v1i64, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i64,
OPC_CheckChild1Type, MVT::v2i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i64,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VSHLuv2i64), 0,
1, MVT::v2i64, 4, 0, 1, 2, 3,
0,
- 94|128,1,
+ 86|128,1,
OPC_CheckInteger, 94,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLsv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLsv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLsv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLsv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLsv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLsv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v1i64,
OPC_CheckChild1Type, MVT::v1i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v1i64,
- OPC_CheckType, MVT::v1i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLsv1i64), 0,
1, MVT::v1i64, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i64,
OPC_CheckChild1Type, MVT::v2i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i64,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLsv2i64), 0,
1, MVT::v2i64, 4, 0, 1, 2, 3,
0,
- 94|128,1,
+ 86|128,1,
OPC_CheckInteger, 95,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLuv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLuv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLuv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLuv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLuv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLuv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v1i64,
OPC_CheckChild1Type, MVT::v1i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v1i64,
- OPC_CheckType, MVT::v1i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLuv1i64), 0,
1, MVT::v1i64, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i64,
OPC_CheckChild1Type, MVT::v2i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i64,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VRSHLuv2i64), 0,
1, MVT::v2i64, 4, 0, 1, 2, 3,
0,
- 94|128,1,
+ 86|128,1,
OPC_CheckInteger, 83,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v1i64,
OPC_CheckChild1Type, MVT::v1i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v1i64,
- OPC_CheckType, MVT::v1i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsv1i64), 0,
1, MVT::v1i64, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i64,
OPC_CheckChild1Type, MVT::v2i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i64,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLsv2i64), 0,
1, MVT::v2i64, 4, 0, 1, 2, 3,
0,
- 94|128,1,
+ 86|128,1,
OPC_CheckInteger, 85,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLuv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLuv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLuv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLuv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLuv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLuv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v1i64,
OPC_CheckChild1Type, MVT::v1i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v1i64,
- OPC_CheckType, MVT::v1i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLuv1i64), 0,
1, MVT::v1i64, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i64,
OPC_CheckChild1Type, MVT::v2i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i64,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQSHLuv2i64), 0,
1, MVT::v2i64, 4, 0, 1, 2, 3,
0,
- 94|128,1,
+ 86|128,1,
OPC_CheckInteger, 78,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLsv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLsv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLsv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLsv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLsv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLsv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v1i64,
OPC_CheckChild1Type, MVT::v1i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v1i64,
- OPC_CheckType, MVT::v1i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLsv1i64), 0,
1, MVT::v1i64, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i64,
OPC_CheckChild1Type, MVT::v2i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i64,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLsv2i64), 0,
1, MVT::v2i64, 4, 0, 1, 2, 3,
0,
- 94|128,1,
+ 86|128,1,
OPC_CheckInteger, 79,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 26,
+ OPC_SwitchType , 24, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLuv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLuv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLuv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLuv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLuv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLuv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v1i64,
OPC_CheckChild1Type, MVT::v1i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v1i64,
- OPC_CheckType, MVT::v1i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLuv1i64), 0,
1, MVT::v1i64, 4, 0, 1, 2, 3,
- 26,
+ 24, MVT::v2i64,
OPC_CheckChild1Type, MVT::v2i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::v2i64,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQRSHLuv2i64), 0,
1, MVT::v2i64, 4, 0, 1, 2, 3,
0,
- 62|128,1,
+ 54|128,1,
OPC_CheckInteger, 11,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 22,
+ OPC_SwitchType , 20, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABSv8i8), 0,
1, MVT::v8i8, 3, 0, 1, 2,
- 22,
+ 20, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABSv4i16), 0,
1, MVT::v4i16, 3, 0, 1, 2,
- 22,
+ 20, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABSv2i32), 0,
1, MVT::v2i32, 3, 0, 1, 2,
- 22,
+ 20, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABSv16i8), 0,
1, MVT::v16i8, 3, 0, 1, 2,
- 22,
+ 20, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABSv8i16), 0,
1, MVT::v8i16, 3, 0, 1, 2,
- 22,
+ 20, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABSv4i32), 0,
1, MVT::v4i32, 3, 0, 1, 2,
- 22,
+ 20, MVT::v2f32,
OPC_CheckChild1Type, MVT::v2f32,
- OPC_CheckType, MVT::v2f32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABSfd), 0,
1, MVT::v2f32, 3, 0, 1, 2,
- 22,
+ 20, MVT::v4f32,
OPC_CheckChild1Type, MVT::v4f32,
- OPC_CheckType, MVT::v4f32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VABSfq), 0,
1, MVT::v4f32, 3, 0, 1, 2,
0,
- 16|128,1,
+ 10|128,1,
OPC_CheckInteger, 63,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 22,
+ OPC_SwitchType , 20, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQABSv8i8), 0,
1, MVT::v8i8, 3, 0, 1, 2,
- 22,
+ 20, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQABSv4i16), 0,
1, MVT::v4i16, 3, 0, 1, 2,
- 22,
+ 20, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQABSv2i32), 0,
1, MVT::v2i32, 3, 0, 1, 2,
- 22,
+ 20, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQABSv16i8), 0,
1, MVT::v16i8, 3, 0, 1, 2,
- 22,
+ 20, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQABSv8i16), 0,
1, MVT::v8i16, 3, 0, 1, 2,
- 22,
+ 20, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQABSv4i32), 0,
1, MVT::v4i32, 3, 0, 1, 2,
0,
- 16|128,1,
+ 10|128,1,
OPC_CheckInteger, 73,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 22,
+ OPC_SwitchType , 20, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQNEGv8i8), 0,
1, MVT::v8i8, 3, 0, 1, 2,
- 22,
+ 20, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQNEGv4i16), 0,
1, MVT::v4i16, 3, 0, 1, 2,
- 22,
+ 20, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQNEGv2i32), 0,
1, MVT::v2i32, 3, 0, 1, 2,
- 22,
+ 20, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQNEGv16i8), 0,
1, MVT::v16i8, 3, 0, 1, 2,
- 22,
+ 20, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQNEGv8i16), 0,
1, MVT::v8i16, 3, 0, 1, 2,
- 22,
+ 20, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQNEGv4i32), 0,
1, MVT::v4i32, 3, 0, 1, 2,
0,
- 16|128,1,
+ 10|128,1,
OPC_CheckInteger, 21,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 22,
+ OPC_SwitchType , 20, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCLSv8i8), 0,
1, MVT::v8i8, 3, 0, 1, 2,
- 22,
+ 20, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCLSv4i16), 0,
1, MVT::v4i16, 3, 0, 1, 2,
- 22,
+ 20, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCLSv2i32), 0,
1, MVT::v2i32, 3, 0, 1, 2,
- 22,
+ 20, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCLSv16i8), 0,
1, MVT::v16i8, 3, 0, 1, 2,
- 22,
+ 20, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCLSv8i16), 0,
1, MVT::v8i16, 3, 0, 1, 2,
- 22,
+ 20, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCLSv4i32), 0,
1, MVT::v4i32, 3, 0, 1, 2,
0,
- 16|128,1,
+ 10|128,1,
OPC_CheckInteger, 22,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 22,
+ OPC_SwitchType , 20, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCLZv8i8), 0,
1, MVT::v8i8, 3, 0, 1, 2,
- 22,
+ 20, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCLZv4i16), 0,
1, MVT::v4i16, 3, 0, 1, 2,
- 22,
+ 20, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCLZv2i32), 0,
1, MVT::v2i32, 3, 0, 1, 2,
- 22,
+ 20, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCLZv16i8), 0,
1, MVT::v16i8, 3, 0, 1, 2,
- 22,
+ 20, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCLZv8i16), 0,
1, MVT::v8i16, 3, 0, 1, 2,
- 22,
+ 20, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCLZv4i32), 0,
1, MVT::v4i32, 3, 0, 1, 2,
0,
- 52,
+ 50,
OPC_CheckInteger, 23,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 22,
+ OPC_SwitchType , 20, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCNTd), 0,
1, MVT::v8i8, 3, 0, 1, 2,
- 22,
+ 20, MVT::v16i8,
OPC_CheckChild1Type, MVT::v16i8,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCNTq), 0,
1, MVT::v16i8, 3, 0, 1, 2,
0,
- 75,
+ 72,
OPC_CheckInteger, 49,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 22,
+ OPC_SwitchType , 20, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMOVNv8i8), 0,
1, MVT::v8i8, 3, 0, 1, 2,
- 22,
+ 20, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMOVNv4i16), 0,
1, MVT::v4i16, 3, 0, 1, 2,
- 22,
+ 20, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i64,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMOVNv2i32), 0,
1, MVT::v2i32, 3, 0, 1, 2,
0,
- 75,
+ 72,
OPC_CheckInteger, 70,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 22,
+ OPC_SwitchType , 20, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQMOVNsv8i8), 0,
1, MVT::v8i8, 3, 0, 1, 2,
- 22,
+ 20, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQMOVNsv4i16), 0,
1, MVT::v4i16, 3, 0, 1, 2,
- 22,
+ 20, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i64,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQMOVNsv2i32), 0,
1, MVT::v2i32, 3, 0, 1, 2,
0,
- 75,
+ 72,
OPC_CheckInteger, 72,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 22,
+ OPC_SwitchType , 20, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQMOVNuv8i8), 0,
1, MVT::v8i8, 3, 0, 1, 2,
- 22,
+ 20, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQMOVNuv4i16), 0,
1, MVT::v4i16, 3, 0, 1, 2,
- 22,
+ 20, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i64,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQMOVNuv2i32), 0,
1, MVT::v2i32, 3, 0, 1, 2,
0,
- 75,
+ 72,
OPC_CheckInteger, 71,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 22,
+ OPC_SwitchType , 20, MVT::v8i8,
OPC_CheckChild1Type, MVT::v8i16,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQMOVNsuv8i8), 0,
1, MVT::v8i8, 3, 0, 1, 2,
- 22,
+ 20, MVT::v4i16,
OPC_CheckChild1Type, MVT::v4i32,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQMOVNsuv4i16), 0,
1, MVT::v4i16, 3, 0, 1, 2,
- 22,
+ 20, MVT::v2i32,
OPC_CheckChild1Type, MVT::v2i64,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VQMOVNsuv2i32), 0,
1, MVT::v2i32, 3, 0, 1, 2,
0,
- 75,
+ 72,
OPC_CheckInteger, 47,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 22,
+ OPC_SwitchType , 20, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMOVLsv8i16), 0,
1, MVT::v8i16, 3, 0, 1, 2,
- 22,
+ 20, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMOVLsv4i32), 0,
1, MVT::v4i32, 3, 0, 1, 2,
- 22,
+ 20, MVT::v2i64,
OPC_CheckChild1Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMOVLsv2i64), 0,
1, MVT::v2i64, 3, 0, 1, 2,
0,
- 75,
+ 72,
OPC_CheckInteger, 48,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 22,
+ OPC_SwitchType , 20, MVT::v8i16,
OPC_CheckChild1Type, MVT::v8i8,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMOVLuv8i16), 0,
1, MVT::v8i16, 3, 0, 1, 2,
- 22,
+ 20, MVT::v4i32,
OPC_CheckChild1Type, MVT::v4i16,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMOVLuv4i32), 0,
1, MVT::v4i32, 3, 0, 1, 2,
- 22,
+ 20, MVT::v2i64,
OPC_CheckChild1Type, MVT::v2i32,
- OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
@@ -21306,7 +20391,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VTBX4), 0,
1, MVT::v8i8, 8, 0, 1, 2, 3, 4, 5, 6, 7,
0,
- 37|128,1, ISD::SHL,
+ 35|128,1, ISD::SHL,
OPC_Scope, 30,
OPC_RecordNode,
OPC_CheckType, MVT::i32,
@@ -21317,15 +20402,15 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::MOVs), 0,
1, MVT::i32, 6, 1, 2, 3, 4, 5, 6,
- 2|128,1,
+ 0|128,1,
OPC_RecordChild0,
OPC_RecordChild1,
- OPC_Scope, 70,
+ OPC_Scope, 68,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::Constant,
- OPC_Scope, 32,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 30,
OPC_CheckPredicate, 24,
- OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 2,
@@ -21335,8 +20420,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LSLri), 0,
1, MVT::i32, 5, 0, 2, 3, 4, 5,
- 30,
- OPC_CheckType, MVT::i32,
+ 28,
OPC_MoveParent,
OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 6,
@@ -21367,7 +20451,7 @@ SDNode *SelectCode(SDNode *N) {
0,
0,
0,
- 37|128,1, ISD::SRL,
+ 35|128,1, ISD::SRL,
OPC_Scope, 30,
OPC_RecordNode,
OPC_CheckType, MVT::i32,
@@ -21378,15 +20462,15 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::MOVs), 0,
1, MVT::i32, 6, 1, 2, 3, 4, 5, 6,
- 2|128,1,
+ 0|128,1,
OPC_RecordChild0,
OPC_RecordChild1,
- OPC_Scope, 70,
+ OPC_Scope, 68,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::Constant,
- OPC_Scope, 32,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 30,
OPC_CheckPredicate, 24,
- OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 2,
@@ -21396,8 +20480,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2LSRri), 0,
1, MVT::i32, 5, 0, 2, 3, 4, 5,
- 30,
- OPC_CheckType, MVT::i32,
+ 28,
OPC_MoveParent,
OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 6,
@@ -24420,11 +23503,11 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VEXTqf), 0,
1, MVT::v4f32, 5, 0, 1, 3, 4, 5,
0,
- 2|128,3, ISD::Constant,
+ 110|128,2, ISD::Constant,
OPC_RecordNode,
- OPC_Scope, 28,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 26,
OPC_CheckPredicate, 4,
- OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 2,
OPC_EmitConvertToTarget, 0,
OPC_EmitInteger, MVT::i32, 14,
@@ -24432,9 +23515,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2MOVi), 0,
1, MVT::i32, 4, 1, 2, 3, 4,
- 28,
+ 26,
OPC_CheckPredicate, 5,
- OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 5,
OPC_EmitConvertToTarget, 0,
OPC_EmitInteger, MVT::i32, 14,
@@ -24442,18 +23524,16 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::MOVi), 0,
1, MVT::i32, 4, 1, 2, 3, 4,
- 24,
+ 22,
OPC_CheckPredicate, 61,
- OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 4,
OPC_EmitConvertToTarget, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::MOVi16), 0,
1, MVT::i32, 3, 1, 2, 3,
- 31,
+ 29,
OPC_CheckPredicate, 23,
- OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 5,
OPC_EmitConvertToTarget, 0,
OPC_EmitNodeXForm, 17, 1,
@@ -24462,18 +23542,16 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::MVNi), 0,
1, MVT::i32, 4, 2, 3, 4, 5,
- 24,
+ 22,
OPC_CheckPredicate, 7,
- OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 26,
OPC_EmitConvertToTarget, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::MOVi2pieces), 0,
1, MVT::i32, 3, 1, 2, 3,
- 28,
+ 26,
OPC_CheckPredicate, 53,
- OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 6,
OPC_EmitRegister, MVT::i32, ARM::CPSR,
OPC_EmitConvertToTarget, 0,
@@ -24481,18 +23559,16 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::tMOVi8), 0,
1, MVT::i32, 4, 1, 2, 3, 4,
- 24,
+ 22,
OPC_CheckPredicate, 61,
- OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 2,
OPC_EmitConvertToTarget, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2MOVi16), 0,
1, MVT::i32, 3, 1, 2, 3,
- 31,
+ 29,
OPC_CheckPredicate, 6,
- OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 2,
OPC_EmitConvertToTarget, 0,
OPC_EmitNodeXForm, 1, 1,
@@ -24501,9 +23577,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::t2MVNi), 0,
1, MVT::i32, 4, 2, 3, 4, 5,
- 57,
+ 55,
OPC_CheckPredicate, 62,
- OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 6,
OPC_EmitRegister, MVT::i32, ARM::CPSR,
OPC_EmitRegister, MVT::i32, ARM::CPSR,
@@ -24519,9 +23594,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::tLSLri), 0,
1, MVT::i32, 5, 1, 7, 9, 10, 11,
- 51,
+ 49,
OPC_CheckPredicate, 63,
- OPC_CheckType, MVT::i32,
OPC_CheckPatternPredicate, 6,
OPC_EmitRegister, MVT::i32, ARM::CPSR,
OPC_EmitRegister, MVT::i32, ARM::CPSR,
@@ -24535,8 +23609,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::tMVN), 0,
1, MVT::i32, 4, 1, 7, 8, 9,
- 46,
- OPC_CheckType, MVT::i32,
+ 44,
OPC_Scope, 20,
OPC_CheckPatternPredicate, 4,
OPC_EmitConvertToTarget, 0,
@@ -24553,20 +23626,18 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::i32, 3, 1, 2, 3,
0,
0,
- 53, ISD::ConstantFP,
+ 51, ISD::ConstantFP,
OPC_RecordNode,
- OPC_Scope, 24,
+ OPC_SwitchType , 22, MVT::f64,
OPC_CheckPredicate, 64,
- OPC_CheckType, MVT::f64,
OPC_CheckPatternPredicate, 27,
OPC_EmitConvertToTarget, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::FCONSTD), 0,
1, MVT::f64, 3, 1, 2, 3,
- 24,
+ 22, MVT::f32,
OPC_CheckPredicate, 65,
- OPC_CheckType, MVT::f32,
OPC_CheckPatternPredicate, 27,
OPC_EmitConvertToTarget, 0,
OPC_EmitInteger, MVT::i32, 14,
@@ -24645,285 +23716,187 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v2i64, 3, 1, 2, 3,
0,
0,
- 71, ISD::ATOMIC_LOAD_ADD,
- OPC_Scope, 22,
+ 55, ISD::ATOMIC_LOAD_ADD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 14,
OPC_CheckPredicate, 70,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_ADD_I8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 1, 2,
- 22,
+ 14,
OPC_CheckPredicate, 71,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_ADD_I16), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 1, 2,
- 22,
+ 14,
OPC_CheckPredicate, 72,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_ADD_I32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 1, 2,
0,
- 71, ISD::ATOMIC_LOAD_SUB,
- OPC_Scope, 22,
+ 55, ISD::ATOMIC_LOAD_SUB,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 14,
OPC_CheckPredicate, 73,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_SUB_I8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 1, 2,
- 22,
+ 14,
OPC_CheckPredicate, 74,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_SUB_I16), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 1, 2,
- 22,
+ 14,
OPC_CheckPredicate, 75,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_SUB_I32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 1, 2,
0,
- 71, ISD::ATOMIC_LOAD_AND,
- OPC_Scope, 22,
+ 55, ISD::ATOMIC_LOAD_AND,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 14,
OPC_CheckPredicate, 76,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_AND_I8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 1, 2,
- 22,
+ 14,
OPC_CheckPredicate, 77,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_AND_I16), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 1, 2,
- 22,
+ 14,
OPC_CheckPredicate, 78,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_AND_I32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 1, 2,
0,
- 71, ISD::ATOMIC_LOAD_OR,
- OPC_Scope, 22,
+ 55, ISD::ATOMIC_LOAD_OR,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 14,
OPC_CheckPredicate, 79,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_OR_I8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 1, 2,
- 22,
+ 14,
OPC_CheckPredicate, 80,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_OR_I16), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 1, 2,
- 22,
+ 14,
OPC_CheckPredicate, 81,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_OR_I32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 1, 2,
0,
- 71, ISD::ATOMIC_LOAD_XOR,
- OPC_Scope, 22,
+ 55, ISD::ATOMIC_LOAD_XOR,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 14,
OPC_CheckPredicate, 82,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_XOR_I8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 1, 2,
- 22,
+ 14,
OPC_CheckPredicate, 83,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_XOR_I16), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 1, 2,
- 22,
+ 14,
OPC_CheckPredicate, 84,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_XOR_I32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 1, 2,
0,
- 71, ISD::ATOMIC_LOAD_NAND,
- OPC_Scope, 22,
+ 55, ISD::ATOMIC_LOAD_NAND,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 14,
OPC_CheckPredicate, 85,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_NAND_I8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 1, 2,
- 22,
+ 14,
OPC_CheckPredicate, 86,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_NAND_I16), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 1, 2,
- 22,
+ 14,
OPC_CheckPredicate, 87,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_LOAD_NAND_I32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 1, 2,
0,
- 71, ISD::ATOMIC_SWAP,
- OPC_Scope, 22,
+ 55, ISD::ATOMIC_SWAP,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 14,
OPC_CheckPredicate, 88,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_SWAP_I8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 1, 2,
- 22,
+ 14,
OPC_CheckPredicate, 89,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_SWAP_I16), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 1, 2,
- 22,
+ 14,
OPC_CheckPredicate, 90,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_SWAP_I32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 1, 2,
0,
- 77, ISD::ATOMIC_CMP_SWAP,
- OPC_Scope, 24,
+ 59, ISD::ATOMIC_CMP_SWAP,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 15,
OPC_CheckPredicate, 91,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_RecordChild3,
- OPC_CheckType, MVT::i32,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_CMP_SWAP_I8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 3, 1, 2, 3,
- 24,
+ 15,
OPC_CheckPredicate, 92,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_RecordChild3,
- OPC_CheckType, MVT::i32,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_CMP_SWAP_I16), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 3, 1, 2, 3,
- 24,
+ 15,
OPC_CheckPredicate, 93,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_RecordChild3,
- OPC_CheckType, MVT::i32,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::ATOMIC_CMP_SWAP_I32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 3, 1, 2, 3,
@@ -25163,59 +24136,81 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VMOVSR), 0,
1, MVT::f32, 3, 0, 1, 2,
0,
- 36, ARMISD::RET_FLAG,
+ 56, ARMISD::RET_FLAG,
OPC_RecordNode,
OPC_CaptureFlagInput,
OPC_Scope, 19,
- OPC_CheckPatternPredicate, 5,
+ OPC_CheckPatternPredicate, 28,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::BX_RET), 0|OPFL_Chain|OPFL_FlagInput,
0, 2, 1, 2,
+ 19,
+ OPC_CheckPatternPredicate, 29,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::MOVPCLR), 0|OPFL_Chain|OPFL_FlagInput,
+ 0, 2, 1, 2,
11,
OPC_CheckPatternPredicate, 9,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::tBX_RET), 0|OPFL_Chain|OPFL_FlagInput,
0, 0,
0,
- 32, ISD::BRIND,
+ 45, ISD::BRIND,
OPC_RecordNode,
OPC_RecordChild1,
OPC_CheckChild1Type, MVT::i32,
OPC_Scope, 12,
- OPC_CheckPatternPredicate, 5,
+ OPC_CheckPatternPredicate, 28,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::BRIND), 0|OPFL_Chain,
0, 1, 1,
12,
+ OPC_CheckPatternPredicate, 29,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::MOVPCRX), 0|OPFL_Chain,
+ 0, 1, 1,
+ 12,
OPC_CheckPatternPredicate, 9,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::tBRIND), 0|OPFL_Chain,
0, 1, 1,
0,
- 59, ARMISD::CALL_NOLINK,
+ 85, ARMISD::CALL_NOLINK,
OPC_RecordNode,
OPC_CaptureFlagInput,
OPC_RecordChild1,
OPC_CheckChild1Type, MVT::i32,
OPC_Scope, 12,
- OPC_CheckPatternPredicate, 14,
+ OPC_CheckPatternPredicate, 30,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::BX), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
0, 1, 1,
12,
- OPC_CheckPatternPredicate, 15,
+ OPC_CheckPatternPredicate, 31,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::BMOVPCRX), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 12,
+ OPC_CheckPatternPredicate, 32,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::BXr9), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
0, 1, 1,
12,
- OPC_CheckPatternPredicate, 28,
+ OPC_CheckPatternPredicate, 33,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::BMOVPCRXr9), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
+ 0, 1, 1,
+ 12,
+ OPC_CheckPatternPredicate, 34,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::tBX), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
0, 1, 1,
12,
- OPC_CheckPatternPredicate, 29,
+ OPC_CheckPatternPredicate, 35,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::tBXr9), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_Variadic1,
0, 1, 1,
@@ -25310,7 +24305,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_RecordChild0,
OPC_CheckType, MVT::i32,
OPC_Scope, 18,
- OPC_CheckPatternPredicate, 30,
+ OPC_CheckPatternPredicate, 36,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::CLZ), 0,
@@ -25363,7 +24358,7 @@ SDNode *SelectCode(SDNode *N) {
43, ARMISD::MEMBARRIER,
OPC_RecordNode,
OPC_Scope, 11,
- OPC_CheckPatternPredicate, 31,
+ OPC_CheckPatternPredicate, 37,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::Int_MemBarrierV7), 0|OPFL_Chain,
0, 0,
@@ -25383,7 +24378,7 @@ SDNode *SelectCode(SDNode *N) {
43, ARMISD::SYNCBARRIER,
OPC_RecordNode,
OPC_Scope, 11,
- OPC_CheckPatternPredicate, 31,
+ OPC_CheckPatternPredicate, 37,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::Int_SyncBarrierV7), 0|OPFL_Chain,
0, 0,
@@ -25693,472 +24688,434 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::FMSTAT), 0|OPFL_FlagInput|OPFL_FlagOutput,
0, 2, 0, 1,
- 75|128,1, ARMISD::VCEQ,
+ 71|128,1, ARMISD::VCEQ,
OPC_RecordChild0,
- OPC_Scope, 24,
+ OPC_SwitchType , 22, MVT::v8i8,
OPC_CheckChild0Type, MVT::v8i8,
OPC_RecordChild1,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCEQv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 24,
+ 22, MVT::v4i16,
OPC_CheckChild0Type, MVT::v4i16,
OPC_RecordChild1,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCEQv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 24,
- OPC_CheckChild0Type, MVT::v2i32,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v2i32,
- OPC_CheckPatternPredicate, 3,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCEQv2i32), 0,
- 1, MVT::v2i32, 4, 0, 1, 2, 3,
- 24,
+ 48, MVT::v2i32,
+ OPC_Scope, 22,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCEQv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 22,
+ OPC_CheckChild0Type, MVT::v2f32,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCEQfd), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 0,
+ 22, MVT::v16i8,
OPC_CheckChild0Type, MVT::v16i8,
OPC_RecordChild1,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCEQv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
- 24,
+ 22, MVT::v8i16,
OPC_CheckChild0Type, MVT::v8i16,
OPC_RecordChild1,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCEQv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 24,
- OPC_CheckChild0Type, MVT::v4i32,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v4i32,
- OPC_CheckPatternPredicate, 3,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCEQv4i32), 0,
- 1, MVT::v4i32, 4, 0, 1, 2, 3,
- 24,
- OPC_CheckChild0Type, MVT::v2f32,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v2i32,
- OPC_CheckPatternPredicate, 3,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCEQfd), 0,
- 1, MVT::v2i32, 4, 0, 1, 2, 3,
- 24,
- OPC_CheckChild0Type, MVT::v4f32,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v4i32,
- OPC_CheckPatternPredicate, 3,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCEQfq), 0,
- 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 48, MVT::v4i32,
+ OPC_Scope, 22,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCEQv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 22,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCEQfq), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 0,
0,
- 75|128,1, ARMISD::VCGE,
+ 71|128,1, ARMISD::VCGE,
OPC_RecordChild0,
- OPC_Scope, 24,
+ OPC_SwitchType , 22, MVT::v8i8,
OPC_CheckChild0Type, MVT::v8i8,
OPC_RecordChild1,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEsv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 24,
+ 22, MVT::v4i16,
OPC_CheckChild0Type, MVT::v4i16,
OPC_RecordChild1,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEsv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 24,
- OPC_CheckChild0Type, MVT::v2i32,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v2i32,
- OPC_CheckPatternPredicate, 3,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEsv2i32), 0,
- 1, MVT::v2i32, 4, 0, 1, 2, 3,
- 24,
+ 48, MVT::v2i32,
+ OPC_Scope, 22,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEsv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 22,
+ OPC_CheckChild0Type, MVT::v2f32,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEfd), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 0,
+ 22, MVT::v16i8,
OPC_CheckChild0Type, MVT::v16i8,
OPC_RecordChild1,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEsv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
- 24,
+ 22, MVT::v8i16,
OPC_CheckChild0Type, MVT::v8i16,
OPC_RecordChild1,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEsv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 24,
- OPC_CheckChild0Type, MVT::v4i32,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v4i32,
- OPC_CheckPatternPredicate, 3,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEsv4i32), 0,
- 1, MVT::v4i32, 4, 0, 1, 2, 3,
- 24,
- OPC_CheckChild0Type, MVT::v2f32,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v2i32,
- OPC_CheckPatternPredicate, 3,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEfd), 0,
- 1, MVT::v2i32, 4, 0, 1, 2, 3,
- 24,
- OPC_CheckChild0Type, MVT::v4f32,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v4i32,
- OPC_CheckPatternPredicate, 3,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEfq), 0,
- 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 48, MVT::v4i32,
+ OPC_Scope, 22,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEsv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 22,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEfq), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 0,
0,
- 25|128,1, ARMISD::VCGEU,
+ 19|128,1, ARMISD::VCGEU,
OPC_RecordChild0,
- OPC_Scope, 24,
+ OPC_SwitchType , 22, MVT::v8i8,
OPC_CheckChild0Type, MVT::v8i8,
OPC_RecordChild1,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEuv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 24,
+ 22, MVT::v4i16,
OPC_CheckChild0Type, MVT::v4i16,
OPC_RecordChild1,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEuv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 24,
+ 22, MVT::v2i32,
OPC_CheckChild0Type, MVT::v2i32,
OPC_RecordChild1,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEuv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 24,
+ 22, MVT::v16i8,
OPC_CheckChild0Type, MVT::v16i8,
OPC_RecordChild1,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEuv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
- 24,
+ 22, MVT::v8i16,
OPC_CheckChild0Type, MVT::v8i16,
OPC_RecordChild1,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEuv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 24,
+ 22, MVT::v4i32,
OPC_CheckChild0Type, MVT::v4i32,
OPC_RecordChild1,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGEuv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
0,
- 75|128,1, ARMISD::VCGT,
+ 71|128,1, ARMISD::VCGT,
OPC_RecordChild0,
- OPC_Scope, 24,
+ OPC_SwitchType , 22, MVT::v8i8,
OPC_CheckChild0Type, MVT::v8i8,
OPC_RecordChild1,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTsv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 24,
+ 22, MVT::v4i16,
OPC_CheckChild0Type, MVT::v4i16,
OPC_RecordChild1,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTsv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 24,
- OPC_CheckChild0Type, MVT::v2i32,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v2i32,
- OPC_CheckPatternPredicate, 3,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTsv2i32), 0,
- 1, MVT::v2i32, 4, 0, 1, 2, 3,
- 24,
+ 48, MVT::v2i32,
+ OPC_Scope, 22,
+ OPC_CheckChild0Type, MVT::v2i32,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTsv2i32), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 22,
+ OPC_CheckChild0Type, MVT::v2f32,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTfd), 0,
+ 1, MVT::v2i32, 4, 0, 1, 2, 3,
+ 0,
+ 22, MVT::v16i8,
OPC_CheckChild0Type, MVT::v16i8,
OPC_RecordChild1,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTsv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
- 24,
+ 22, MVT::v8i16,
OPC_CheckChild0Type, MVT::v8i16,
OPC_RecordChild1,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTsv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 24,
- OPC_CheckChild0Type, MVT::v4i32,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v4i32,
- OPC_CheckPatternPredicate, 3,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTsv4i32), 0,
- 1, MVT::v4i32, 4, 0, 1, 2, 3,
- 24,
- OPC_CheckChild0Type, MVT::v2f32,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v2i32,
- OPC_CheckPatternPredicate, 3,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTfd), 0,
- 1, MVT::v2i32, 4, 0, 1, 2, 3,
- 24,
- OPC_CheckChild0Type, MVT::v4f32,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v4i32,
- OPC_CheckPatternPredicate, 3,
- OPC_EmitInteger, MVT::i32, 14,
- OPC_EmitRegister, MVT::i32, 0 ,
- OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTfq), 0,
- 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 48, MVT::v4i32,
+ OPC_Scope, 22,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTsv4i32), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 22,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_RecordChild1,
+ OPC_CheckPatternPredicate, 3,
+ OPC_EmitInteger, MVT::i32, 14,
+ OPC_EmitRegister, MVT::i32, 0 ,
+ OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTfq), 0,
+ 1, MVT::v4i32, 4, 0, 1, 2, 3,
+ 0,
0,
- 25|128,1, ARMISD::VCGTU,
+ 19|128,1, ARMISD::VCGTU,
OPC_RecordChild0,
- OPC_Scope, 24,
+ OPC_SwitchType , 22, MVT::v8i8,
OPC_CheckChild0Type, MVT::v8i8,
OPC_RecordChild1,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTuv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 24,
+ 22, MVT::v4i16,
OPC_CheckChild0Type, MVT::v4i16,
OPC_RecordChild1,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTuv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 24,
+ 22, MVT::v2i32,
OPC_CheckChild0Type, MVT::v2i32,
OPC_RecordChild1,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTuv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 24,
+ 22, MVT::v16i8,
OPC_CheckChild0Type, MVT::v16i8,
OPC_RecordChild1,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTuv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
- 24,
+ 22, MVT::v8i16,
OPC_CheckChild0Type, MVT::v8i16,
OPC_RecordChild1,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTuv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 24,
+ 22, MVT::v4i32,
OPC_CheckChild0Type, MVT::v4i32,
OPC_RecordChild1,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCGTuv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
0,
- 25|128,1, ARMISD::VTST,
+ 19|128,1, ARMISD::VTST,
OPC_RecordChild0,
- OPC_Scope, 24,
+ OPC_SwitchType , 22, MVT::v8i8,
OPC_CheckChild0Type, MVT::v8i8,
OPC_RecordChild1,
- OPC_CheckType, MVT::v8i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VTSTv8i8), 0,
1, MVT::v8i8, 4, 0, 1, 2, 3,
- 24,
+ 22, MVT::v4i16,
OPC_CheckChild0Type, MVT::v4i16,
OPC_RecordChild1,
- OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VTSTv4i16), 0,
1, MVT::v4i16, 4, 0, 1, 2, 3,
- 24,
+ 22, MVT::v2i32,
OPC_CheckChild0Type, MVT::v2i32,
OPC_RecordChild1,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VTSTv2i32), 0,
1, MVT::v2i32, 4, 0, 1, 2, 3,
- 24,
+ 22, MVT::v16i8,
OPC_CheckChild0Type, MVT::v16i8,
OPC_RecordChild1,
- OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VTSTv16i8), 0,
1, MVT::v16i8, 4, 0, 1, 2, 3,
- 24,
+ 22, MVT::v8i16,
OPC_CheckChild0Type, MVT::v8i16,
OPC_RecordChild1,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VTSTv8i16), 0,
1, MVT::v8i16, 4, 0, 1, 2, 3,
- 24,
+ 22, MVT::v4i32,
OPC_CheckChild0Type, MVT::v4i32,
OPC_RecordChild1,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VTSTv4i32), 0,
1, MVT::v4i32, 4, 0, 1, 2, 3,
0,
- 49, ISD::FP_TO_SINT,
+ 47, ISD::FP_TO_SINT,
OPC_RecordChild0,
- OPC_Scope, 22,
+ OPC_SwitchType , 20, MVT::v2i32,
OPC_CheckChild0Type, MVT::v2f32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCVTf2sd), 0,
1, MVT::v2i32, 3, 0, 1, 2,
- 22,
+ 20, MVT::v4i32,
OPC_CheckChild0Type, MVT::v4f32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCVTf2sq), 0,
1, MVT::v4i32, 3, 0, 1, 2,
0,
- 49, ISD::FP_TO_UINT,
+ 47, ISD::FP_TO_UINT,
OPC_RecordChild0,
- OPC_Scope, 22,
+ OPC_SwitchType , 20, MVT::v2i32,
OPC_CheckChild0Type, MVT::v2f32,
- OPC_CheckType, MVT::v2i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCVTf2ud), 0,
1, MVT::v2i32, 3, 0, 1, 2,
- 22,
+ 20, MVT::v4i32,
OPC_CheckChild0Type, MVT::v4f32,
- OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCVTf2uq), 0,
1, MVT::v4i32, 3, 0, 1, 2,
0,
- 49, ISD::SINT_TO_FP,
+ 47, ISD::SINT_TO_FP,
OPC_RecordChild0,
- OPC_Scope, 22,
+ OPC_SwitchType , 20, MVT::v2f32,
OPC_CheckChild0Type, MVT::v2i32,
- OPC_CheckType, MVT::v2f32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCVTs2fd), 0,
1, MVT::v2f32, 3, 0, 1, 2,
- 22,
+ 20, MVT::v4f32,
OPC_CheckChild0Type, MVT::v4i32,
- OPC_CheckType, MVT::v4f32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCVTs2fq), 0,
1, MVT::v4f32, 3, 0, 1, 2,
0,
- 49, ISD::UINT_TO_FP,
+ 47, ISD::UINT_TO_FP,
OPC_RecordChild0,
- OPC_Scope, 22,
+ OPC_SwitchType , 20, MVT::v2f32,
OPC_CheckChild0Type, MVT::v2i32,
- OPC_CheckType, MVT::v2f32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
OPC_MorphNodeTo, TARGET_OPCODE(ARM::VCVTu2fd), 0,
1, MVT::v2f32, 3, 0, 1, 2,
- 22,
+ 20, MVT::v4f32,
OPC_CheckChild0Type, MVT::v4i32,
- OPC_CheckType, MVT::v4f32,
OPC_CheckPatternPredicate, 3,
OPC_EmitInteger, MVT::i32, 14,
OPC_EmitRegister, MVT::i32, 0 ,
@@ -26394,7 +25351,7 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::f32, 2, 10, 11,
0,
0
- }; // Total Array size is 63661 bytes
+ }; // Total Array size is 62431 bytes
#undef TARGET_OPCODE
return SelectCodeCommon(N, MatcherTable,sizeof(MatcherTable));
@@ -26431,10 +25388,16 @@ bool CheckPatternPredicate(unsigned PredNo) const {
case 25: return (Subtarget->isThumb()) && (Subtarget->isTargetDarwin());
case 26: return (!Subtarget->isThumb()) && (!Subtarget->hasV6T2Ops());
case 27: return (Subtarget->hasVFP3());
- case 28: return (Subtarget->isThumb1Only()) && (!Subtarget->isTargetDarwin());
- case 29: return (Subtarget->isThumb1Only()) && (Subtarget->isTargetDarwin());
- case 30: return (!Subtarget->isThumb()) && (Subtarget->hasV5TOps());
- case 31: return (!Subtarget->isThumb()) && (Subtarget->hasV7Ops());
+ case 28: return (!Subtarget->isThumb()) && (Subtarget->hasV4TOps());
+ case 29: return (!Subtarget->isThumb()) && (!Subtarget->hasV4TOps());
+ case 30: return (!Subtarget->isThumb()) && (Subtarget->hasV4TOps()) && (!Subtarget->isTargetDarwin());
+ case 31: return (!Subtarget->isThumb()) && (!Subtarget->hasV4TOps()) && (!Subtarget->isTargetDarwin());
+ case 32: return (!Subtarget->isThumb()) && (Subtarget->hasV4TOps()) && (Subtarget->isTargetDarwin());
+ case 33: return (!Subtarget->isThumb()) && (!Subtarget->hasV4TOps()) && (Subtarget->isTargetDarwin());
+ case 34: return (Subtarget->isThumb1Only()) && (!Subtarget->isTargetDarwin());
+ case 35: return (Subtarget->isThumb1Only()) && (Subtarget->isTargetDarwin());
+ case 36: return (!Subtarget->isThumb()) && (Subtarget->hasV5TOps());
+ case 37: return (!Subtarget->isThumb()) && (Subtarget->hasV7Ops());
}
}
diff --git a/libclamav/c++/ARMGenInstrInfo.inc b/libclamav/c++/ARMGenInstrInfo.inc
index 9b4a39c..8348acf 100644
--- a/libclamav/c++/ARMGenInstrInfo.inc
+++ b/libclamav/c++/ARMGenInstrInfo.inc
@@ -38,10 +38,10 @@ static const TargetOperandInfo OperandInfo13[] = { { ARM::GPRRegClassID, 0, 0 },
static const TargetOperandInfo OperandInfo14[] = { { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo15[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, ((0 << 16) | (1 << TOI::TIED_TO)) }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo16[] = { { ARM::GPRRegClassID, 0, 0 }, };
-static const TargetOperandInfo OperandInfo17[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo18[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo19[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
-static const TargetOperandInfo OperandInfo20[] = { { ARM::tGPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo17[] = { { ARM::tGPRRegClassID, 0, 0 }, };
+static const TargetOperandInfo OperandInfo18[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo19[] = { { ARM::GPRRegClassID, 0, 0 }, { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
+static const TargetOperandInfo OperandInfo20[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, };
static const TargetOperandInfo OperandInfo21[] = { { ARM::GPRRegClassID, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo22[] = { { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
static const TargetOperandInfo OperandInfo23[] = { { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0, 0 }, { 0, 0|(1<<TOI::Predicate), 0 }, { ARM::CCRRegClassID, 0|(1<<TOI::Predicate), 0 }, };
@@ -267,1884 +267,1888 @@ static const TargetInstrDesc ARMInsts[] = {
{ 63, 3, 0, 0, "BL_pred", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList3, Barriers2, OperandInfo11 }, // Inst #63 = BL_pred
{ 64, 1, 0, 0, "BLr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList4, Barriers2, OperandInfo14 }, // Inst #64 = BLr9
{ 65, 3, 0, 0, "BLr9_pred", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::Variadic), 0|(3<<4)|(2<<9), NULL, ImplicitList4, Barriers2, OperandInfo11 }, // Inst #65 = BLr9_pred
- { 66, 1, 0, 0, "BRIND", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(3<<4)|(3<<9), NULL, NULL, NULL, OperandInfo16 }, // Inst #66 = BRIND
- { 67, 4, 0, 0, "BR_JTadd", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo17 }, // Inst #67 = BR_JTadd
- { 68, 5, 0, 0, "BR_JTm", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo18 }, // Inst #68 = BR_JTm
- { 69, 3, 0, 0, "BR_JTr", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo19 }, // Inst #69 = BR_JTr
- { 70, 1, 0, 0, "BX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(2<<4)|(3<<9), NULL, ImplicitList3, Barriers2, OperandInfo20 }, // Inst #70 = BX
- { 71, 3, 0, 128, "BXJ", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #71 = BXJ
- { 72, 2, 0, 0, "BX_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(3<<4)|(3<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #72 = BX_RET
- { 73, 1, 0, 0, "BXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(2<<4)|(3<<9), NULL, ImplicitList4, Barriers2, OperandInfo20 }, // Inst #73 = BXr9
- { 74, 3, 0, 0, "Bcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #74 = Bcc
- { 75, 8, 0, 128, "CDP", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #75 = CDP
- { 76, 6, 0, 128, "CDP2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #76 = CDP2
- { 77, 0, 0, 128, "CLREX", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #77 = CLREX
- { 78, 4, 1, 125, "CLZ", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #78 = CLZ
- { 79, 4, 0, 97, "CMNzri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #79 = CMNzri
- { 80, 4, 0, 98, "CMNzrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #80 = CMNzrr
- { 81, 6, 0, 100, "CMNzrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo27 }, // Inst #81 = CMNzrs
- { 82, 4, 0, 97, "CMPri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #82 = CMPri
- { 83, 4, 0, 98, "CMPrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #83 = CMPrr
- { 84, 6, 0, 100, "CMPrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo27 }, // Inst #84 = CMPrs
- { 85, 4, 0, 97, "CMPzri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #85 = CMPzri
- { 86, 4, 0, 98, "CMPzrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #86 = CMPzrr
- { 87, 6, 0, 100, "CMPzrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo27 }, // Inst #87 = CMPzrs
- { 88, 3, 0, 128, "CONSTPOOL_ENTRY", 0|(1<<TID::NotDuplicable), 0|(1<<4), NULL, NULL, NULL, OperandInfo28 }, // Inst #88 = CONSTPOOL_ENTRY
- { 89, 1, 0, 128, "CPS", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #89 = CPS
- { 90, 3, 0, 128, "DBG", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #90 = DBG
- { 91, 0, 0, 128, "DMBish", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #91 = DMBish
- { 92, 0, 0, 128, "DMBishst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #92 = DMBishst
- { 93, 0, 0, 128, "DMBnsh", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #93 = DMBnsh
- { 94, 0, 0, 128, "DMBnshst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #94 = DMBnshst
- { 95, 0, 0, 128, "DMBosh", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #95 = DMBosh
- { 96, 0, 0, 128, "DMBoshst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #96 = DMBoshst
- { 97, 0, 0, 128, "DMBst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #97 = DMBst
- { 98, 0, 0, 128, "DSBish", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #98 = DSBish
- { 99, 0, 0, 128, "DSBishst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #99 = DSBishst
- { 100, 0, 0, 128, "DSBnsh", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #100 = DSBnsh
- { 101, 0, 0, 128, "DSBnshst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #101 = DSBnshst
- { 102, 0, 0, 128, "DSBosh", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #102 = DSBosh
- { 103, 0, 0, 128, "DSBoshst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #103 = DSBoshst
- { 104, 0, 0, 128, "DSBst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #104 = DSBst
- { 105, 6, 1, 88, "EORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #105 = EORri
- { 106, 6, 1, 89, "EORrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #106 = EORrr
- { 107, 8, 1, 91, "EORrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #107 = EORrs
- { 108, 4, 1, 26, "FCONSTD", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(3<<4)|(22<<9)|(1<<17), NULL, NULL, NULL, OperandInfo29 }, // Inst #108 = FCONSTD
- { 109, 4, 1, 26, "FCONSTS", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(3<<4)|(22<<9)|(1<<17), NULL, NULL, NULL, OperandInfo30 }, // Inst #109 = FCONSTS
- { 110, 2, 0, 82, "FMSTAT", 0|(1<<TID::Predicable), 0|(3<<4)|(22<<9)|(1<<17), ImplicitList5, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #110 = FMSTAT
- { 111, 0, 0, 128, "ISBsy", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #111 = ISBsy
- { 112, 1, 0, 128, "Int_MemBarrierV6", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, OperandInfo16 }, // Inst #112 = Int_MemBarrierV6
- { 113, 0, 0, 128, "Int_MemBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #113 = Int_MemBarrierV7
- { 114, 1, 0, 128, "Int_SyncBarrierV6", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, OperandInfo16 }, // Inst #114 = Int_SyncBarrierV6
- { 115, 0, 0, 128, "Int_SyncBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #115 = Int_SyncBarrierV7
- { 116, 2, 0, 128, "Int_eh_sjlj_setjmp", 0, 0|(1<<4), NULL, ImplicitList6, Barriers3, OperandInfo32 }, // Inst #116 = Int_eh_sjlj_setjmp
- { 117, 7, 0, 128, "LDC2L_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #117 = LDC2L_OFFSET
- { 118, 6, 0, 128, "LDC2L_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 }, // Inst #118 = LDC2L_OPTION
- { 119, 7, 0, 128, "LDC2L_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #119 = LDC2L_POST
- { 120, 7, 0, 128, "LDC2L_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #120 = LDC2L_PRE
- { 121, 7, 0, 128, "LDC2_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #121 = LDC2_OFFSET
- { 122, 6, 0, 128, "LDC2_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 }, // Inst #122 = LDC2_OPTION
- { 123, 7, 0, 128, "LDC2_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #123 = LDC2_POST
- { 124, 7, 0, 128, "LDC2_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #124 = LDC2_PRE
- { 125, 7, 0, 128, "LDCL_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #125 = LDCL_OFFSET
- { 126, 6, 0, 128, "LDCL_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 }, // Inst #126 = LDCL_OPTION
- { 127, 7, 0, 128, "LDCL_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #127 = LDCL_POST
- { 128, 7, 0, 128, "LDCL_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #128 = LDCL_PRE
- { 129, 7, 0, 128, "LDC_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #129 = LDC_OFFSET
- { 130, 6, 0, 128, "LDC_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 }, // Inst #130 = LDC_OPTION
- { 131, 7, 0, 128, "LDC_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #131 = LDC_POST
- { 132, 7, 0, 128, "LDC_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #132 = LDC_PRE
- { 133, 5, 0, 103, "LDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #133 = LDM
- { 134, 5, 0, 0, "LDM_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #134 = LDM_RET
- { 135, 6, 1, 104, "LDR", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #135 = LDR
- { 136, 6, 1, 104, "LDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #136 = LDRB
- { 137, 7, 2, 105, "LDRBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #137 = LDRBT
- { 138, 7, 2, 105, "LDRB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #138 = LDRB_POST
- { 139, 7, 2, 105, "LDRB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(1<<7)|(6<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #139 = LDRB_PRE
- { 140, 7, 2, 104, "LDRD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo10 }, // Inst #140 = LDRD
- { 141, 8, 3, 104, "LDRD_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #141 = LDRD_POST
- { 142, 8, 3, 104, "LDRD_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #142 = LDRD_PRE
- { 143, 4, 1, 128, "LDREX", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #143 = LDREX
- { 144, 4, 1, 128, "LDREXB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #144 = LDREXB
- { 145, 5, 2, 128, "LDREXD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #145 = LDREXD
- { 146, 4, 1, 128, "LDREXH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #146 = LDREXH
- { 147, 6, 1, 104, "LDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #147 = LDRH
- { 148, 7, 2, 105, "LDRHT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #148 = LDRHT
- { 149, 7, 2, 105, "LDRH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #149 = LDRH_POST
- { 150, 7, 2, 105, "LDRH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #150 = LDRH_PRE
- { 151, 6, 1, 104, "LDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #151 = LDRSB
- { 152, 7, 2, 105, "LDRSBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #152 = LDRSBT
- { 153, 7, 2, 105, "LDRSB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #153 = LDRSB_POST
- { 154, 7, 2, 105, "LDRSB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #154 = LDRSB_PRE
- { 155, 6, 1, 104, "LDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #155 = LDRSH
- { 156, 7, 2, 105, "LDRSHT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #156 = LDRSHT
- { 157, 7, 2, 105, "LDRSH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #157 = LDRSH_POST
- { 158, 7, 2, 105, "LDRSH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #158 = LDRSH_PRE
- { 159, 7, 2, 105, "LDRT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #159 = LDRT
- { 160, 7, 2, 105, "LDR_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #160 = LDR_POST
- { 161, 7, 2, 105, "LDR_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(1<<7)|(6<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #161 = LDR_PRE
- { 162, 6, 1, 104, "LDRcp", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #162 = LDRcp
- { 163, 4, 1, 88, "LEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo26 }, // Inst #163 = LEApcrel
- { 164, 5, 1, 88, "LEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo38 }, // Inst #164 = LEApcrelJT
- { 165, 8, 0, 128, "MCR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #165 = MCR
- { 166, 6, 0, 128, "MCR2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #166 = MCR2
- { 167, 7, 0, 128, "MCRR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #167 = MCRR
- { 168, 5, 0, 128, "MCRR2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo41 }, // Inst #168 = MCRR2
- { 169, 7, 1, 109, "MLA", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo42 }, // Inst #169 = MLA
- { 170, 6, 1, 109, "MLS", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #170 = MLS
- { 171, 5, 1, 93, "MOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo15 }, // Inst #171 = MOVCCi
- { 172, 5, 1, 94, "MOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo44 }, // Inst #172 = MOVCCr
- { 173, 7, 1, 96, "MOVCCs", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo45 }, // Inst #173 = MOVCCs
- { 174, 5, 1, 111, "MOVTi16", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo15 }, // Inst #174 = MOVTi16
- { 175, 5, 1, 111, "MOVi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo46 }, // Inst #175 = MOVi
- { 176, 4, 1, 111, "MOVi16", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo26 }, // Inst #176 = MOVi16
- { 177, 4, 1, 111, "MOVi2pieces", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|1|(2<<4), NULL, NULL, NULL, OperandInfo26 }, // Inst #177 = MOVi2pieces
- { 178, 4, 1, 111, "MOVi32imm", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|1|(2<<4), NULL, NULL, NULL, OperandInfo26 }, // Inst #178 = MOVi32imm
- { 179, 5, 1, 112, "MOVr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo47 }, // Inst #179 = MOVr
- { 180, 5, 1, 113, "MOVrx", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(1<<15), ImplicitList1, NULL, NULL, OperandInfo47 }, // Inst #180 = MOVrx
- { 181, 7, 1, 114, "MOVs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo48 }, // Inst #181 = MOVs
- { 182, 4, 1, 113, "MOVsra_flag", 0|(1<<TID::Predicable), 0|1|(3<<4)|(1<<15), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #182 = MOVsra_flag
- { 183, 4, 1, 113, "MOVsrl_flag", 0|(1<<TID::Predicable), 0|1|(3<<4)|(1<<15), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #183 = MOVsrl_flag
- { 184, 8, 0, 128, "MRC", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #184 = MRC
- { 185, 6, 0, 128, "MRC2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #185 = MRC2
- { 186, 7, 0, 128, "MRRC", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #186 = MRRC
- { 187, 5, 0, 128, "MRRC2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo41 }, // Inst #187 = MRRC2
- { 188, 3, 1, 128, "MRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #188 = MRS
- { 189, 3, 1, 128, "MRSsys", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #189 = MRSsys
- { 190, 3, 0, 128, "MSR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #190 = MSR
- { 191, 3, 0, 128, "MSRi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #191 = MSRi
- { 192, 3, 0, 128, "MSRsys", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #192 = MSRsys
- { 193, 3, 0, 128, "MSRsysi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #193 = MSRsysi
- { 194, 6, 1, 116, "MUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #194 = MUL
- { 195, 5, 1, 111, "MVNi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo46 }, // Inst #195 = MVNi
- { 196, 5, 1, 112, "MVNr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo47 }, // Inst #196 = MVNr
- { 197, 7, 1, 114, "MVNs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo48 }, // Inst #197 = MVNs
- { 198, 2, 0, 128, "NOP", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #198 = NOP
- { 199, 6, 1, 88, "ORRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #199 = ORRri
- { 200, 6, 1, 89, "ORRrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #200 = ORRrr
- { 201, 8, 1, 91, "ORRrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #201 = ORRrs
- { 202, 5, 1, 89, "PICADD", 0|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #202 = PICADD
- { 203, 5, 1, 104, "PICLDR", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #203 = PICLDR
- { 204, 5, 1, 104, "PICLDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #204 = PICLDRB
- { 205, 5, 1, 104, "PICLDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #205 = PICLDRH
- { 206, 5, 1, 104, "PICLDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #206 = PICLDRSB
- { 207, 5, 1, 104, "PICLDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #207 = PICLDRSH
- { 208, 5, 0, 121, "PICSTR", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #208 = PICSTR
- { 209, 5, 0, 121, "PICSTRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #209 = PICSTRB
- { 210, 5, 0, 121, "PICSTRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #210 = PICSTRH
- { 211, 6, 1, 90, "PKHBT", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #211 = PKHBT
- { 212, 6, 1, 90, "PKHTB", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #212 = PKHTB
- { 213, 2, 0, 128, "PLDWi", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo49 }, // Inst #213 = PLDWi
- { 214, 3, 0, 128, "PLDWr", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo2 }, // Inst #214 = PLDWr
- { 215, 2, 0, 128, "PLDi", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo49 }, // Inst #215 = PLDi
- { 216, 3, 0, 128, "PLDr", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo2 }, // Inst #216 = PLDr
- { 217, 2, 0, 128, "PLIi", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo49 }, // Inst #217 = PLIi
- { 218, 3, 0, 128, "PLIr", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo2 }, // Inst #218 = PLIr
- { 219, 5, 1, 89, "QADD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #219 = QADD
- { 220, 5, 1, 89, "QADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #220 = QADD16
- { 221, 5, 1, 89, "QADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #221 = QADD8
- { 222, 5, 1, 89, "QASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #222 = QASX
- { 223, 5, 1, 89, "QDADD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #223 = QDADD
- { 224, 5, 1, 89, "QDSUB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #224 = QDSUB
- { 225, 5, 1, 89, "QSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #225 = QSAX
- { 226, 5, 1, 89, "QSUB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #226 = QSUB
- { 227, 5, 1, 89, "QSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #227 = QSUB16
- { 228, 5, 1, 89, "QSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #228 = QSUB8
- { 229, 4, 1, 125, "RBIT", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #229 = RBIT
- { 230, 4, 1, 125, "REV", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #230 = REV
- { 231, 4, 1, 125, "REV16", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #231 = REV16
- { 232, 4, 1, 125, "REVSH", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #232 = REVSH
- { 233, 3, 0, 128, "RFE", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo50 }, // Inst #233 = RFE
- { 234, 3, 0, 128, "RFEW", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo50 }, // Inst #234 = RFEW
- { 235, 5, 1, 88, "RSBSri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #235 = RSBSri
- { 236, 7, 1, 91, "RSBSrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #236 = RSBSrs
- { 237, 6, 1, 88, "RSBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #237 = RSBri
- { 238, 8, 1, 91, "RSBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #238 = RSBrs
- { 239, 3, 1, 88, "RSCSri", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #239 = RSCSri
- { 240, 5, 1, 91, "RSCSrs", 0, 0|1|(3<<4)|(5<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #240 = RSCSrs
- { 241, 6, 1, 88, "RSCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #241 = RSCri
- { 242, 8, 1, 91, "RSCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), ImplicitList1, NULL, NULL, OperandInfo7 }, // Inst #242 = RSCrs
- { 243, 5, 1, 89, "SADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #243 = SADD16
- { 244, 5, 1, 89, "SADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #244 = SADD8
- { 245, 5, 1, 89, "SASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #245 = SASX
- { 246, 3, 1, 88, "SBCSSri", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #246 = SBCSSri
- { 247, 3, 1, 89, "SBCSSrr", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #247 = SBCSSrr
- { 248, 5, 1, 91, "SBCSSrs", 0, 0|1|(3<<4)|(5<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #248 = SBCSSrs
- { 249, 6, 1, 88, "SBCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #249 = SBCri
- { 250, 6, 1, 89, "SBCrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #250 = SBCrr
- { 251, 8, 1, 91, "SBCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), ImplicitList1, NULL, NULL, OperandInfo7 }, // Inst #251 = SBCrs
- { 252, 6, 1, 88, "SBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo51 }, // Inst #252 = SBFX
- { 253, 5, 1, 128, "SEL", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #253 = SEL
- { 254, 0, 0, 128, "SETENDBE", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #254 = SETENDBE
- { 255, 0, 0, 128, "SETENDLE", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #255 = SETENDLE
- { 256, 2, 0, 128, "SEV", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #256 = SEV
- { 257, 5, 1, 89, "SHADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #257 = SHADD16
- { 258, 5, 1, 89, "SHADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #258 = SHADD8
- { 259, 5, 1, 89, "SHASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #259 = SHASX
- { 260, 5, 1, 89, "SHSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #260 = SHSAX
- { 261, 5, 1, 89, "SHSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #261 = SHSUB16
- { 262, 5, 1, 89, "SHSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #262 = SHSUB8
- { 263, 3, 0, 128, "SMC", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #263 = SMC
- { 264, 6, 1, 108, "SMLABB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #264 = SMLABB
- { 265, 6, 1, 108, "SMLABT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #265 = SMLABT
- { 266, 6, 1, 128, "SMLAD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #266 = SMLAD
- { 267, 6, 1, 128, "SMLADX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #267 = SMLADX
- { 268, 7, 2, 110, "SMLAL", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo42 }, // Inst #268 = SMLAL
- { 269, 6, 2, 110, "SMLALBB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #269 = SMLALBB
- { 270, 6, 2, 110, "SMLALBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #270 = SMLALBT
- { 271, 6, 2, 128, "SMLALD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #271 = SMLALD
- { 272, 6, 2, 128, "SMLALDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #272 = SMLALDX
- { 273, 6, 2, 110, "SMLALTB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #273 = SMLALTB
- { 274, 6, 2, 110, "SMLALTT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #274 = SMLALTT
- { 275, 6, 1, 108, "SMLATB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #275 = SMLATB
- { 276, 6, 1, 108, "SMLATT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #276 = SMLATT
- { 277, 6, 1, 108, "SMLAWB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #277 = SMLAWB
- { 278, 6, 1, 108, "SMLAWT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #278 = SMLAWT
- { 279, 6, 1, 128, "SMLSD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #279 = SMLSD
- { 280, 6, 1, 128, "SMLSDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #280 = SMLSDX
- { 281, 6, 2, 128, "SMLSLD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #281 = SMLSLD
- { 282, 6, 2, 128, "SMLSLDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #282 = SMLSLDX
- { 283, 6, 1, 109, "SMMLA", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #283 = SMMLA
- { 284, 6, 1, 109, "SMMLAR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #284 = SMMLAR
- { 285, 6, 1, 109, "SMMLS", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #285 = SMMLS
- { 286, 6, 1, 109, "SMMLSR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #286 = SMMLSR
- { 287, 5, 1, 116, "SMMUL", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #287 = SMMUL
- { 288, 5, 1, 116, "SMMULR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #288 = SMMULR
- { 289, 5, 1, 128, "SMUAD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #289 = SMUAD
- { 290, 5, 1, 128, "SMUADX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #290 = SMUADX
- { 291, 5, 1, 116, "SMULBB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #291 = SMULBB
- { 292, 5, 1, 116, "SMULBT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #292 = SMULBT
- { 293, 7, 2, 117, "SMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo42 }, // Inst #293 = SMULL
- { 294, 5, 1, 116, "SMULTB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #294 = SMULTB
- { 295, 5, 1, 116, "SMULTT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #295 = SMULTT
- { 296, 5, 1, 115, "SMULWB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #296 = SMULWB
- { 297, 5, 1, 115, "SMULWT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #297 = SMULWT
- { 298, 5, 1, 128, "SMUSD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #298 = SMUSD
- { 299, 5, 1, 128, "SMUSDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #299 = SMUSDX
- { 300, 3, 0, 128, "SRS", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo19 }, // Inst #300 = SRS
- { 301, 3, 0, 128, "SRSW", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo19 }, // Inst #301 = SRSW
- { 302, 5, 1, 128, "SSAT16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo52 }, // Inst #302 = SSAT16
- { 303, 6, 1, 128, "SSATasr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo53 }, // Inst #303 = SSATasr
- { 304, 6, 1, 128, "SSATlsl", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo53 }, // Inst #304 = SSATlsl
- { 305, 5, 1, 89, "SSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #305 = SSAX
- { 306, 5, 1, 89, "SSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #306 = SSUB16
- { 307, 5, 1, 89, "SSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #307 = SSUB8
- { 308, 7, 0, 128, "STC2L_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #308 = STC2L_OFFSET
- { 309, 6, 0, 128, "STC2L_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 }, // Inst #309 = STC2L_OPTION
- { 310, 7, 0, 128, "STC2L_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #310 = STC2L_POST
- { 311, 7, 0, 128, "STC2L_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #311 = STC2L_PRE
- { 312, 7, 0, 128, "STC2_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #312 = STC2_OFFSET
- { 313, 6, 0, 128, "STC2_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 }, // Inst #313 = STC2_OPTION
- { 314, 7, 0, 128, "STC2_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #314 = STC2_POST
- { 315, 7, 0, 128, "STC2_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #315 = STC2_PRE
- { 316, 7, 0, 128, "STCL_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #316 = STCL_OFFSET
- { 317, 6, 0, 128, "STCL_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 }, // Inst #317 = STCL_OPTION
- { 318, 7, 0, 128, "STCL_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #318 = STCL_POST
- { 319, 7, 0, 128, "STCL_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #319 = STCL_PRE
- { 320, 7, 0, 128, "STC_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #320 = STC_OFFSET
- { 321, 6, 0, 128, "STC_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 }, // Inst #321 = STC_OPTION
- { 322, 7, 0, 128, "STC_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #322 = STC_POST
- { 323, 7, 0, 128, "STC_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #323 = STC_PRE
- { 324, 5, 0, 120, "STM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #324 = STM
- { 325, 6, 0, 121, "STR", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(7<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #325 = STR
- { 326, 6, 0, 121, "STRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(7<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #326 = STRB
- { 327, 7, 1, 122, "STRBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo54 }, // Inst #327 = STRBT
- { 328, 7, 1, 122, "STRB_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo54 }, // Inst #328 = STRB_POST
- { 329, 7, 1, 122, "STRB_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(1<<7)|(7<<9), NULL, NULL, NULL, OperandInfo54 }, // Inst #329 = STRB_PRE
- { 330, 7, 0, 121, "STRD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|3|(3<<4)|(9<<9), NULL, NULL, NULL, OperandInfo10 }, // Inst #330 = STRD
- { 331, 8, 1, 122, "STRD_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|3|(3<<4)|(2<<7)|(9<<9), NULL, NULL, NULL, OperandInfo55 }, // Inst #331 = STRD_POST
- { 332, 8, 1, 122, "STRD_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|3|(3<<4)|(1<<7)|(9<<9), NULL, NULL, NULL, OperandInfo55 }, // Inst #332 = STRD_PRE
- { 333, 5, 1, 128, "STREX", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo56 }, // Inst #333 = STREX
- { 334, 5, 1, 128, "STREXB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo56 }, // Inst #334 = STREXB
- { 335, 6, 1, 128, "STREXD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo57 }, // Inst #335 = STREXD
- { 336, 5, 1, 128, "STREXH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo56 }, // Inst #336 = STREXH
- { 337, 6, 0, 121, "STRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(9<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #337 = STRH
- { 338, 7, 1, 122, "STRHT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|3|(3<<4)|(2<<7)|(9<<9), NULL, NULL, NULL, OperandInfo54 }, // Inst #338 = STRHT
- { 339, 7, 1, 122, "STRH_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(2<<7)|(9<<9), NULL, NULL, NULL, OperandInfo54 }, // Inst #339 = STRH_POST
- { 340, 7, 1, 122, "STRH_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(1<<7)|(9<<9), NULL, NULL, NULL, OperandInfo54 }, // Inst #340 = STRH_PRE
- { 341, 7, 1, 122, "STRT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo54 }, // Inst #341 = STRT
- { 342, 7, 1, 122, "STR_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo54 }, // Inst #342 = STR_POST
- { 343, 7, 1, 122, "STR_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(1<<7)|(7<<9), NULL, NULL, NULL, OperandInfo54 }, // Inst #343 = STR_PRE
- { 344, 5, 1, 88, "SUBSri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #344 = SUBSri
- { 345, 5, 1, 89, "SUBSrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #345 = SUBSrr
- { 346, 7, 1, 91, "SUBSrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #346 = SUBSrs
- { 347, 6, 1, 88, "SUBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #347 = SUBri
- { 348, 6, 1, 89, "SUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #348 = SUBrr
- { 349, 8, 1, 91, "SUBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #349 = SUBrs
- { 350, 3, 0, 0, "SVC", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #350 = SVC
- { 351, 5, 1, 128, "SWP", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #351 = SWP
- { 352, 5, 1, 128, "SWPB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #352 = SWPB
- { 353, 5, 1, 89, "SXTAB16rr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #353 = SXTAB16rr
- { 354, 6, 1, 90, "SXTAB16rr_rot", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #354 = SXTAB16rr_rot
- { 355, 5, 1, 89, "SXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #355 = SXTABrr
- { 356, 6, 1, 90, "SXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #356 = SXTABrr_rot
- { 357, 5, 1, 89, "SXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #357 = SXTAHrr
- { 358, 6, 1, 90, "SXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #358 = SXTAHrr_rot
- { 359, 4, 1, 125, "SXTB16r", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #359 = SXTB16r
- { 360, 5, 1, 126, "SXTB16r_rot", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #360 = SXTB16r_rot
- { 361, 4, 1, 125, "SXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #361 = SXTBr
- { 362, 5, 1, 126, "SXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #362 = SXTBr_rot
- { 363, 4, 1, 125, "SXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #363 = SXTHr
- { 364, 5, 1, 126, "SXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #364 = SXTHr_rot
- { 365, 4, 0, 97, "TEQri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #365 = TEQri
- { 366, 4, 0, 98, "TEQrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #366 = TEQrr
- { 367, 6, 0, 100, "TEQrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo27 }, // Inst #367 = TEQrs
- { 368, 0, 0, 0, "TPsoft", 0|(1<<TID::Call), 0|(3<<4)|(2<<9), NULL, ImplicitList7, Barriers1, 0 }, // Inst #368 = TPsoft
- { 369, 2, 0, 128, "TRAP", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #369 = TRAP
- { 370, 4, 0, 97, "TSTri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #370 = TSTri
- { 371, 4, 0, 98, "TSTrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #371 = TSTrr
- { 372, 6, 0, 100, "TSTrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo27 }, // Inst #372 = TSTrs
- { 373, 5, 1, 89, "UADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #373 = UADD16
- { 374, 5, 1, 89, "UADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #374 = UADD8
- { 375, 5, 1, 89, "UASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #375 = UASX
- { 376, 6, 1, 88, "UBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo51 }, // Inst #376 = UBFX
- { 377, 5, 1, 89, "UHADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #377 = UHADD16
- { 378, 5, 1, 89, "UHADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #378 = UHADD8
- { 379, 5, 1, 89, "UHASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #379 = UHASX
- { 380, 5, 1, 89, "UHSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #380 = UHSAX
- { 381, 5, 1, 89, "UHSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #381 = UHSUB16
- { 382, 5, 1, 89, "UHSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #382 = UHSUB8
- { 383, 6, 2, 110, "UMAAL", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #383 = UMAAL
- { 384, 7, 2, 110, "UMLAL", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo42 }, // Inst #384 = UMLAL
- { 385, 7, 2, 117, "UMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo42 }, // Inst #385 = UMULL
- { 386, 5, 1, 89, "UQADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #386 = UQADD16
- { 387, 5, 1, 89, "UQADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #387 = UQADD8
- { 388, 5, 1, 89, "UQASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #388 = UQASX
- { 389, 5, 1, 89, "UQSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #389 = UQSAX
- { 390, 5, 1, 89, "UQSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #390 = UQSUB16
- { 391, 5, 1, 89, "UQSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #391 = UQSUB8
- { 392, 5, 1, 128, "USAD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #392 = USAD8
- { 393, 6, 1, 128, "USADA8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #393 = USADA8
- { 394, 5, 1, 128, "USAT16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo52 }, // Inst #394 = USAT16
- { 395, 6, 1, 128, "USATasr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo53 }, // Inst #395 = USATasr
- { 396, 6, 1, 128, "USATlsl", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo53 }, // Inst #396 = USATlsl
- { 397, 5, 1, 89, "USAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #397 = USAX
- { 398, 5, 1, 89, "USUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #398 = USUB16
- { 399, 5, 1, 89, "USUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #399 = USUB8
- { 400, 5, 1, 89, "UXTAB16rr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #400 = UXTAB16rr
- { 401, 6, 1, 90, "UXTAB16rr_rot", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #401 = UXTAB16rr_rot
- { 402, 5, 1, 89, "UXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #402 = UXTABrr
- { 403, 6, 1, 90, "UXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #403 = UXTABrr_rot
- { 404, 5, 1, 89, "UXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #404 = UXTAHrr
- { 405, 6, 1, 90, "UXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #405 = UXTAHrr_rot
- { 406, 4, 1, 125, "UXTB16r", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #406 = UXTB16r
- { 407, 5, 1, 126, "UXTB16r_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #407 = UXTB16r_rot
- { 408, 4, 1, 125, "UXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #408 = UXTBr
- { 409, 5, 1, 126, "UXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #409 = UXTBr_rot
- { 410, 4, 1, 125, "UXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #410 = UXTHr
- { 411, 5, 1, 126, "UXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #411 = UXTHr_rot
- { 412, 6, 1, 17, "VABALsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #412 = VABALsv2i64
- { 413, 6, 1, 17, "VABALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #413 = VABALsv4i32
- { 414, 6, 1, 17, "VABALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #414 = VABALsv8i16
- { 415, 6, 1, 17, "VABALuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #415 = VABALuv2i64
- { 416, 6, 1, 17, "VABALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #416 = VABALuv4i32
- { 417, 6, 1, 17, "VABALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #417 = VABALuv8i16
- { 418, 6, 1, 18, "VABAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #418 = VABAsv16i8
- { 419, 6, 1, 19, "VABAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #419 = VABAsv2i32
- { 420, 6, 1, 17, "VABAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #420 = VABAsv4i16
- { 421, 6, 1, 20, "VABAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #421 = VABAsv4i32
- { 422, 6, 1, 18, "VABAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #422 = VABAsv8i16
- { 423, 6, 1, 17, "VABAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #423 = VABAsv8i8
- { 424, 6, 1, 18, "VABAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #424 = VABAuv16i8
- { 425, 6, 1, 19, "VABAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #425 = VABAuv2i32
- { 426, 6, 1, 17, "VABAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #426 = VABAuv4i16
- { 427, 6, 1, 20, "VABAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #427 = VABAuv4i32
- { 428, 6, 1, 18, "VABAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #428 = VABAuv8i16
- { 429, 6, 1, 17, "VABAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #429 = VABAuv8i8
- { 430, 5, 1, 4, "VABDLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #430 = VABDLsv2i64
- { 431, 5, 1, 4, "VABDLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #431 = VABDLsv4i32
- { 432, 5, 1, 4, "VABDLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #432 = VABDLsv8i16
- { 433, 5, 1, 4, "VABDLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #433 = VABDLuv2i64
- { 434, 5, 1, 4, "VABDLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #434 = VABDLuv4i32
- { 435, 5, 1, 4, "VABDLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #435 = VABDLuv8i16
- { 436, 5, 1, 1, "VABDfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #436 = VABDfd
- { 437, 5, 1, 2, "VABDfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #437 = VABDfq
- { 438, 5, 1, 4, "VABDsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #438 = VABDsv16i8
- { 439, 5, 1, 3, "VABDsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #439 = VABDsv2i32
- { 440, 5, 1, 3, "VABDsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #440 = VABDsv4i16
- { 441, 5, 1, 4, "VABDsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #441 = VABDsv4i32
- { 442, 5, 1, 4, "VABDsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #442 = VABDsv8i16
- { 443, 5, 1, 3, "VABDsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #443 = VABDsv8i8
- { 444, 5, 1, 4, "VABDuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #444 = VABDuv16i8
- { 445, 5, 1, 3, "VABDuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #445 = VABDuv2i32
- { 446, 5, 1, 3, "VABDuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #446 = VABDuv4i16
- { 447, 5, 1, 4, "VABDuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #447 = VABDuv4i32
- { 448, 5, 1, 4, "VABDuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #448 = VABDuv8i16
- { 449, 5, 1, 3, "VABDuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #449 = VABDuv8i8
- { 450, 4, 1, 87, "VABSD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #450 = VABSD
- { 451, 4, 1, 86, "VABSS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #451 = VABSS
- { 452, 4, 1, 57, "VABSfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #452 = VABSfd
- { 453, 4, 1, 57, "VABSfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #453 = VABSfd_sfp
- { 454, 4, 1, 58, "VABSfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #454 = VABSfq
- { 455, 4, 1, 60, "VABSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #455 = VABSv16i8
- { 456, 4, 1, 59, "VABSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #456 = VABSv2i32
- { 457, 4, 1, 59, "VABSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #457 = VABSv4i16
- { 458, 4, 1, 60, "VABSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #458 = VABSv4i32
- { 459, 4, 1, 60, "VABSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #459 = VABSv8i16
- { 460, 4, 1, 59, "VABSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #460 = VABSv8i8
- { 461, 5, 1, 1, "VACGEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #461 = VACGEd
- { 462, 5, 1, 2, "VACGEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #462 = VACGEq
- { 463, 5, 1, 1, "VACGTd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #463 = VACGTd
- { 464, 5, 1, 2, "VACGTq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #464 = VACGTq
- { 465, 5, 1, 62, "VADDD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #465 = VADDD
- { 466, 5, 1, 3, "VADDHNv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #466 = VADDHNv2i32
- { 467, 5, 1, 3, "VADDHNv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #467 = VADDHNv4i16
- { 468, 5, 1, 3, "VADDHNv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #468 = VADDHNv8i8
- { 469, 5, 1, 44, "VADDLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #469 = VADDLsv2i64
- { 470, 5, 1, 44, "VADDLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #470 = VADDLsv4i32
- { 471, 5, 1, 44, "VADDLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #471 = VADDLsv8i16
- { 472, 5, 1, 44, "VADDLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #472 = VADDLuv2i64
- { 473, 5, 1, 44, "VADDLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #473 = VADDLuv4i32
- { 474, 5, 1, 44, "VADDLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #474 = VADDLuv8i16
- { 475, 5, 1, 61, "VADDS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #475 = VADDS
- { 476, 5, 1, 47, "VADDWsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #476 = VADDWsv2i64
- { 477, 5, 1, 47, "VADDWsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #477 = VADDWsv4i32
- { 478, 5, 1, 47, "VADDWsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #478 = VADDWsv8i16
- { 479, 5, 1, 47, "VADDWuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #479 = VADDWuv2i64
- { 480, 5, 1, 47, "VADDWuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #480 = VADDWuv4i32
- { 481, 5, 1, 47, "VADDWuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #481 = VADDWuv8i16
- { 482, 5, 1, 1, "VADDfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #482 = VADDfd
- { 483, 5, 1, 1, "VADDfd_sfp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #483 = VADDfd_sfp
- { 484, 5, 1, 2, "VADDfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #484 = VADDfq
- { 485, 5, 1, 6, "VADDv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #485 = VADDv16i8
- { 486, 5, 1, 5, "VADDv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #486 = VADDv1i64
- { 487, 5, 1, 5, "VADDv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #487 = VADDv2i32
- { 488, 5, 1, 6, "VADDv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #488 = VADDv2i64
- { 489, 5, 1, 5, "VADDv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #489 = VADDv4i16
- { 490, 5, 1, 6, "VADDv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #490 = VADDv4i32
- { 491, 5, 1, 6, "VADDv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #491 = VADDv8i16
- { 492, 5, 1, 5, "VADDv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #492 = VADDv8i8
- { 493, 5, 1, 5, "VANDd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #493 = VANDd
- { 494, 5, 1, 6, "VANDq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #494 = VANDq
- { 495, 5, 1, 5, "VBICd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #495 = VBICd
- { 496, 5, 1, 6, "VBICq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #496 = VBICq
- { 497, 6, 1, 5, "VBIFd", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #497 = VBIFd
- { 498, 6, 1, 6, "VBIFq", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #498 = VBIFq
- { 499, 6, 1, 5, "VBITd", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #499 = VBITd
- { 500, 6, 1, 6, "VBITq", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #500 = VBITq
- { 501, 6, 1, 7, "VBSLd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #501 = VBSLd
- { 502, 6, 1, 8, "VBSLq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #502 = VBSLq
- { 503, 5, 1, 1, "VCEQfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #503 = VCEQfd
- { 504, 5, 1, 2, "VCEQfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #504 = VCEQfq
- { 505, 5, 1, 4, "VCEQv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #505 = VCEQv16i8
- { 506, 5, 1, 3, "VCEQv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #506 = VCEQv2i32
- { 507, 5, 1, 3, "VCEQv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #507 = VCEQv4i16
- { 508, 5, 1, 4, "VCEQv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #508 = VCEQv4i32
- { 509, 5, 1, 4, "VCEQv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #509 = VCEQv8i16
- { 510, 5, 1, 3, "VCEQv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #510 = VCEQv8i8
- { 511, 4, 1, 128, "VCEQzv16i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #511 = VCEQzv16i8
- { 512, 4, 1, 128, "VCEQzv2f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #512 = VCEQzv2f32
- { 513, 4, 1, 128, "VCEQzv2i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #513 = VCEQzv2i32
- { 514, 4, 1, 128, "VCEQzv4f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #514 = VCEQzv4f32
- { 515, 4, 1, 128, "VCEQzv4i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #515 = VCEQzv4i16
- { 516, 4, 1, 128, "VCEQzv4i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #516 = VCEQzv4i32
- { 517, 4, 1, 128, "VCEQzv8i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #517 = VCEQzv8i16
- { 518, 4, 1, 128, "VCEQzv8i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #518 = VCEQzv8i8
- { 519, 5, 1, 1, "VCGEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #519 = VCGEfd
- { 520, 5, 1, 2, "VCGEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #520 = VCGEfq
- { 521, 5, 1, 4, "VCGEsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #521 = VCGEsv16i8
- { 522, 5, 1, 3, "VCGEsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #522 = VCGEsv2i32
- { 523, 5, 1, 3, "VCGEsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #523 = VCGEsv4i16
- { 524, 5, 1, 4, "VCGEsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #524 = VCGEsv4i32
- { 525, 5, 1, 4, "VCGEsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #525 = VCGEsv8i16
- { 526, 5, 1, 3, "VCGEsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #526 = VCGEsv8i8
- { 527, 5, 1, 4, "VCGEuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #527 = VCGEuv16i8
- { 528, 5, 1, 3, "VCGEuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #528 = VCGEuv2i32
- { 529, 5, 1, 3, "VCGEuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #529 = VCGEuv4i16
- { 530, 5, 1, 4, "VCGEuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #530 = VCGEuv4i32
- { 531, 5, 1, 4, "VCGEuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #531 = VCGEuv8i16
- { 532, 5, 1, 3, "VCGEuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #532 = VCGEuv8i8
- { 533, 4, 1, 128, "VCGEzv16i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #533 = VCGEzv16i8
- { 534, 4, 1, 128, "VCGEzv2f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #534 = VCGEzv2f32
- { 535, 4, 1, 128, "VCGEzv2i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #535 = VCGEzv2i32
- { 536, 4, 1, 128, "VCGEzv4f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #536 = VCGEzv4f32
- { 537, 4, 1, 128, "VCGEzv4i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #537 = VCGEzv4i16
- { 538, 4, 1, 128, "VCGEzv4i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #538 = VCGEzv4i32
- { 539, 4, 1, 128, "VCGEzv8i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #539 = VCGEzv8i16
- { 540, 4, 1, 128, "VCGEzv8i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #540 = VCGEzv8i8
- { 541, 5, 1, 1, "VCGTfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #541 = VCGTfd
- { 542, 5, 1, 2, "VCGTfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #542 = VCGTfq
- { 543, 5, 1, 4, "VCGTsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #543 = VCGTsv16i8
- { 544, 5, 1, 3, "VCGTsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #544 = VCGTsv2i32
- { 545, 5, 1, 3, "VCGTsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #545 = VCGTsv4i16
- { 546, 5, 1, 4, "VCGTsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #546 = VCGTsv4i32
- { 547, 5, 1, 4, "VCGTsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #547 = VCGTsv8i16
- { 548, 5, 1, 3, "VCGTsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #548 = VCGTsv8i8
- { 549, 5, 1, 4, "VCGTuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #549 = VCGTuv16i8
- { 550, 5, 1, 3, "VCGTuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #550 = VCGTuv2i32
- { 551, 5, 1, 3, "VCGTuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #551 = VCGTuv4i16
- { 552, 5, 1, 4, "VCGTuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #552 = VCGTuv4i32
- { 553, 5, 1, 4, "VCGTuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #553 = VCGTuv8i16
- { 554, 5, 1, 3, "VCGTuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #554 = VCGTuv8i8
- { 555, 4, 1, 128, "VCGTzv16i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #555 = VCGTzv16i8
- { 556, 4, 1, 128, "VCGTzv2f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #556 = VCGTzv2f32
- { 557, 4, 1, 128, "VCGTzv2i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #557 = VCGTzv2i32
- { 558, 4, 1, 128, "VCGTzv4f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #558 = VCGTzv4f32
- { 559, 4, 1, 128, "VCGTzv4i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #559 = VCGTzv4i16
- { 560, 4, 1, 128, "VCGTzv4i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #560 = VCGTzv4i32
- { 561, 4, 1, 128, "VCGTzv8i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #561 = VCGTzv8i16
- { 562, 4, 1, 128, "VCGTzv8i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #562 = VCGTzv8i8
- { 563, 4, 1, 128, "VCLEzv16i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #563 = VCLEzv16i8
- { 564, 4, 1, 128, "VCLEzv2f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #564 = VCLEzv2f32
- { 565, 4, 1, 128, "VCLEzv2i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #565 = VCLEzv2i32
- { 566, 4, 1, 128, "VCLEzv4f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #566 = VCLEzv4f32
- { 567, 4, 1, 128, "VCLEzv4i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #567 = VCLEzv4i16
- { 568, 4, 1, 128, "VCLEzv4i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #568 = VCLEzv4i32
- { 569, 4, 1, 128, "VCLEzv8i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #569 = VCLEzv8i16
- { 570, 4, 1, 128, "VCLEzv8i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #570 = VCLEzv8i8
- { 571, 4, 1, 8, "VCLSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #571 = VCLSv16i8
- { 572, 4, 1, 7, "VCLSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #572 = VCLSv2i32
- { 573, 4, 1, 7, "VCLSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #573 = VCLSv4i16
- { 574, 4, 1, 8, "VCLSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #574 = VCLSv4i32
- { 575, 4, 1, 8, "VCLSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #575 = VCLSv8i16
- { 576, 4, 1, 7, "VCLSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #576 = VCLSv8i8
- { 577, 4, 1, 128, "VCLTzv16i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #577 = VCLTzv16i8
- { 578, 4, 1, 128, "VCLTzv2f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #578 = VCLTzv2f32
- { 579, 4, 1, 128, "VCLTzv2i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #579 = VCLTzv2i32
- { 580, 4, 1, 128, "VCLTzv4f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #580 = VCLTzv4f32
- { 581, 4, 1, 128, "VCLTzv4i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #581 = VCLTzv4i16
- { 582, 4, 1, 128, "VCLTzv4i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #582 = VCLTzv4i32
- { 583, 4, 1, 128, "VCLTzv8i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #583 = VCLTzv8i16
- { 584, 4, 1, 128, "VCLTzv8i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #584 = VCLTzv8i8
- { 585, 4, 1, 8, "VCLZv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #585 = VCLZv16i8
- { 586, 4, 1, 7, "VCLZv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #586 = VCLZv2i32
- { 587, 4, 1, 7, "VCLZv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #587 = VCLZv4i16
- { 588, 4, 1, 8, "VCLZv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #588 = VCLZv4i32
- { 589, 4, 1, 8, "VCLZv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #589 = VCLZv8i16
- { 590, 4, 1, 7, "VCLZv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #590 = VCLZv8i8
- { 591, 4, 0, 64, "VCMPD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo65 }, // Inst #591 = VCMPD
- { 592, 4, 0, 64, "VCMPED", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo65 }, // Inst #592 = VCMPED
- { 593, 4, 0, 63, "VCMPES", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo66 }, // Inst #593 = VCMPES
- { 594, 3, 0, 64, "VCMPEZD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo73 }, // Inst #594 = VCMPEZD
- { 595, 3, 0, 63, "VCMPEZS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo74 }, // Inst #595 = VCMPEZS
- { 596, 4, 0, 63, "VCMPS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo66 }, // Inst #596 = VCMPS
- { 597, 3, 0, 64, "VCMPZD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo73 }, // Inst #597 = VCMPZD
- { 598, 3, 0, 63, "VCMPZS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo74 }, // Inst #598 = VCMPZS
- { 599, 4, 1, 7, "VCNTd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #599 = VCNTd
- { 600, 4, 1, 8, "VCNTq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #600 = VCNTq
- { 601, 4, 1, 66, "VCVTBHS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #601 = VCVTBHS
- { 602, 4, 1, 66, "VCVTBSH", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #602 = VCVTBSH
- { 603, 4, 1, 66, "VCVTDS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #603 = VCVTDS
- { 604, 4, 1, 69, "VCVTSD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #604 = VCVTSD
- { 605, 4, 1, 66, "VCVTTHS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #605 = VCVTTHS
- { 606, 4, 1, 66, "VCVTTSH", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #606 = VCVTTSH
- { 607, 4, 1, 57, "VCVTf2sd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #607 = VCVTf2sd
- { 608, 4, 1, 57, "VCVTf2sd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #608 = VCVTf2sd_sfp
- { 609, 4, 1, 58, "VCVTf2sq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #609 = VCVTf2sq
- { 610, 4, 1, 57, "VCVTf2ud", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #610 = VCVTf2ud
- { 611, 4, 1, 57, "VCVTf2ud_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #611 = VCVTf2ud_sfp
- { 612, 4, 1, 58, "VCVTf2uq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #612 = VCVTf2uq
- { 613, 5, 1, 57, "VCVTf2xsd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #613 = VCVTf2xsd
- { 614, 5, 1, 58, "VCVTf2xsq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #614 = VCVTf2xsq
- { 615, 5, 1, 57, "VCVTf2xud", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #615 = VCVTf2xud
- { 616, 5, 1, 58, "VCVTf2xuq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #616 = VCVTf2xuq
- { 617, 4, 1, 57, "VCVTs2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #617 = VCVTs2fd
- { 618, 4, 1, 57, "VCVTs2fd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #618 = VCVTs2fd_sfp
- { 619, 4, 1, 58, "VCVTs2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #619 = VCVTs2fq
- { 620, 4, 1, 57, "VCVTu2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #620 = VCVTu2fd
- { 621, 4, 1, 57, "VCVTu2fd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #621 = VCVTu2fd_sfp
- { 622, 4, 1, 58, "VCVTu2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #622 = VCVTu2fq
- { 623, 5, 1, 57, "VCVTxs2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #623 = VCVTxs2fd
- { 624, 5, 1, 58, "VCVTxs2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #624 = VCVTxs2fq
- { 625, 5, 1, 57, "VCVTxu2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #625 = VCVTxu2fd
- { 626, 5, 1, 58, "VCVTxu2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #626 = VCVTxu2fq
- { 627, 5, 1, 72, "VDIVD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #627 = VDIVD
- { 628, 5, 1, 71, "VDIVS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #628 = VDIVS
- { 629, 4, 1, 24, "VDUP16d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo79 }, // Inst #629 = VDUP16d
- { 630, 4, 1, 24, "VDUP16q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo80 }, // Inst #630 = VDUP16q
- { 631, 4, 1, 24, "VDUP32d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo79 }, // Inst #631 = VDUP32d
- { 632, 4, 1, 24, "VDUP32q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo80 }, // Inst #632 = VDUP32q
- { 633, 4, 1, 24, "VDUP8d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo79 }, // Inst #633 = VDUP8d
- { 634, 4, 1, 24, "VDUP8q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo80 }, // Inst #634 = VDUP8q
- { 635, 5, 1, 21, "VDUPLN16d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #635 = VDUPLN16d
- { 636, 5, 1, 21, "VDUPLN16q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #636 = VDUPLN16q
- { 637, 5, 1, 21, "VDUPLN32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #637 = VDUPLN32d
- { 638, 5, 1, 21, "VDUPLN32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #638 = VDUPLN32q
- { 639, 5, 1, 21, "VDUPLN8d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #639 = VDUPLN8d
- { 640, 5, 1, 21, "VDUPLN8q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #640 = VDUPLN8q
- { 641, 5, 1, 21, "VDUPLNfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #641 = VDUPLNfd
- { 642, 5, 1, 21, "VDUPLNfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #642 = VDUPLNfq
- { 643, 4, 1, 24, "VDUPfd", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo79 }, // Inst #643 = VDUPfd
- { 644, 4, 1, 21, "VDUPfdf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #644 = VDUPfdf
- { 645, 4, 1, 24, "VDUPfq", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo80 }, // Inst #645 = VDUPfq
- { 646, 4, 1, 21, "VDUPfqf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #646 = VDUPfqf
- { 647, 5, 1, 5, "VEORd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #647 = VEORd
- { 648, 5, 1, 6, "VEORq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #648 = VEORq
- { 649, 6, 1, 9, "VEXTd16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #649 = VEXTd16
- { 650, 6, 1, 9, "VEXTd32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #650 = VEXTd32
- { 651, 6, 1, 9, "VEXTd8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #651 = VEXTd8
- { 652, 6, 1, 9, "VEXTdf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #652 = VEXTdf
- { 653, 6, 1, 10, "VEXTq16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #653 = VEXTq16
- { 654, 6, 1, 10, "VEXTq32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #654 = VEXTq32
- { 655, 6, 1, 10, "VEXTq8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #655 = VEXTq8
- { 656, 6, 1, 10, "VEXTqf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #656 = VEXTqf
- { 657, 5, 1, 28, "VGETLNi32", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo85 }, // Inst #657 = VGETLNi32
- { 658, 5, 1, 28, "VGETLNs16", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo85 }, // Inst #658 = VGETLNs16
- { 659, 5, 1, 28, "VGETLNs8", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo85 }, // Inst #659 = VGETLNs8
- { 660, 5, 1, 28, "VGETLNu16", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo85 }, // Inst #660 = VGETLNu16
- { 661, 5, 1, 28, "VGETLNu8", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo85 }, // Inst #661 = VGETLNu8
- { 662, 5, 1, 4, "VHADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #662 = VHADDsv16i8
- { 663, 5, 1, 3, "VHADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #663 = VHADDsv2i32
- { 664, 5, 1, 3, "VHADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #664 = VHADDsv4i16
- { 665, 5, 1, 4, "VHADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #665 = VHADDsv4i32
- { 666, 5, 1, 4, "VHADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #666 = VHADDsv8i16
- { 667, 5, 1, 3, "VHADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #667 = VHADDsv8i8
- { 668, 5, 1, 4, "VHADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #668 = VHADDuv16i8
- { 669, 5, 1, 3, "VHADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #669 = VHADDuv2i32
- { 670, 5, 1, 3, "VHADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #670 = VHADDuv4i16
- { 671, 5, 1, 4, "VHADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #671 = VHADDuv4i32
- { 672, 5, 1, 4, "VHADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #672 = VHADDuv8i16
- { 673, 5, 1, 3, "VHADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #673 = VHADDuv8i8
- { 674, 5, 1, 4, "VHSUBsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #674 = VHSUBsv16i8
- { 675, 5, 1, 3, "VHSUBsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #675 = VHSUBsv2i32
- { 676, 5, 1, 3, "VHSUBsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #676 = VHSUBsv4i16
- { 677, 5, 1, 4, "VHSUBsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #677 = VHSUBsv4i32
- { 678, 5, 1, 4, "VHSUBsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #678 = VHSUBsv8i16
- { 679, 5, 1, 3, "VHSUBsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #679 = VHSUBsv8i8
- { 680, 5, 1, 4, "VHSUBuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #680 = VHSUBuv16i8
- { 681, 5, 1, 3, "VHSUBuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #681 = VHSUBuv2i32
- { 682, 5, 1, 3, "VHSUBuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #682 = VHSUBuv4i16
- { 683, 5, 1, 4, "VHSUBuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #683 = VHSUBuv4i32
- { 684, 5, 1, 4, "VHSUBuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #684 = VHSUBuv8i16
- { 685, 5, 1, 3, "VHSUBuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #685 = VHSUBuv8i8
- { 686, 7, 1, 11, "VLD1d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #686 = VLD1d16
- { 687, 10, 4, 11, "VLD1d16Q", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #687 = VLD1d16Q
- { 688, 9, 3, 11, "VLD1d16T", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #688 = VLD1d16T
- { 689, 7, 1, 11, "VLD1d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #689 = VLD1d32
- { 690, 10, 4, 11, "VLD1d32Q", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #690 = VLD1d32Q
- { 691, 9, 3, 11, "VLD1d32T", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #691 = VLD1d32T
- { 692, 7, 1, 11, "VLD1d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #692 = VLD1d64
- { 693, 7, 1, 11, "VLD1d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #693 = VLD1d8
- { 694, 10, 4, 11, "VLD1d8Q", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #694 = VLD1d8Q
- { 695, 9, 3, 11, "VLD1d8T", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #695 = VLD1d8T
- { 696, 7, 1, 11, "VLD1df", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #696 = VLD1df
- { 697, 7, 1, 11, "VLD1q16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #697 = VLD1q16
- { 698, 7, 1, 11, "VLD1q32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #698 = VLD1q32
- { 699, 7, 1, 11, "VLD1q64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #699 = VLD1q64
- { 700, 7, 1, 11, "VLD1q8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #700 = VLD1q8
- { 701, 7, 1, 11, "VLD1qf", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #701 = VLD1qf
- { 702, 11, 2, 12, "VLD2LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #702 = VLD2LNd16
- { 703, 11, 2, 12, "VLD2LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #703 = VLD2LNd32
- { 704, 11, 2, 12, "VLD2LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #704 = VLD2LNd8
- { 705, 11, 2, 12, "VLD2LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #705 = VLD2LNq16a
- { 706, 11, 2, 12, "VLD2LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #706 = VLD2LNq16b
- { 707, 11, 2, 12, "VLD2LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #707 = VLD2LNq32a
- { 708, 11, 2, 12, "VLD2LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #708 = VLD2LNq32b
- { 709, 8, 2, 12, "VLD2d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #709 = VLD2d16
- { 710, 8, 2, 12, "VLD2d16D", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #710 = VLD2d16D
- { 711, 8, 2, 12, "VLD2d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #711 = VLD2d32
- { 712, 8, 2, 12, "VLD2d32D", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #712 = VLD2d32D
- { 713, 8, 2, 11, "VLD2d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #713 = VLD2d64
- { 714, 8, 2, 12, "VLD2d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #714 = VLD2d8
- { 715, 8, 2, 12, "VLD2d8D", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #715 = VLD2d8D
- { 716, 10, 4, 12, "VLD2q16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #716 = VLD2q16
- { 717, 10, 4, 12, "VLD2q32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #717 = VLD2q32
- { 718, 10, 4, 12, "VLD2q8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #718 = VLD2q8
- { 719, 13, 3, 13, "VLD3LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #719 = VLD3LNd16
- { 720, 13, 3, 13, "VLD3LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #720 = VLD3LNd32
- { 721, 13, 3, 13, "VLD3LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #721 = VLD3LNd8
- { 722, 13, 3, 13, "VLD3LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #722 = VLD3LNq16a
- { 723, 13, 3, 13, "VLD3LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #723 = VLD3LNq16b
- { 724, 13, 3, 13, "VLD3LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #724 = VLD3LNq32a
- { 725, 13, 3, 13, "VLD3LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #725 = VLD3LNq32b
- { 726, 9, 3, 13, "VLD3d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #726 = VLD3d16
- { 727, 9, 3, 13, "VLD3d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #727 = VLD3d32
- { 728, 9, 3, 11, "VLD3d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #728 = VLD3d64
- { 729, 9, 3, 13, "VLD3d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #729 = VLD3d8
- { 730, 10, 4, 13, "VLD3q16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #730 = VLD3q16a
- { 731, 10, 4, 13, "VLD3q16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #731 = VLD3q16b
- { 732, 10, 4, 13, "VLD3q32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #732 = VLD3q32a
- { 733, 10, 4, 13, "VLD3q32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #733 = VLD3q32b
- { 734, 10, 4, 13, "VLD3q8a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #734 = VLD3q8a
- { 735, 10, 4, 13, "VLD3q8b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #735 = VLD3q8b
- { 736, 15, 4, 14, "VLD4LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #736 = VLD4LNd16
- { 737, 15, 4, 14, "VLD4LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #737 = VLD4LNd32
- { 738, 15, 4, 14, "VLD4LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #738 = VLD4LNd8
- { 739, 15, 4, 14, "VLD4LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #739 = VLD4LNq16a
- { 740, 15, 4, 14, "VLD4LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #740 = VLD4LNq16b
- { 741, 15, 4, 14, "VLD4LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #741 = VLD4LNq32a
- { 742, 15, 4, 14, "VLD4LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #742 = VLD4LNq32b
- { 743, 10, 4, 14, "VLD4d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #743 = VLD4d16
- { 744, 10, 4, 14, "VLD4d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #744 = VLD4d32
- { 745, 10, 4, 11, "VLD4d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #745 = VLD4d64
- { 746, 10, 4, 14, "VLD4d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #746 = VLD4d8
- { 747, 11, 5, 14, "VLD4q16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #747 = VLD4q16a
- { 748, 11, 5, 14, "VLD4q16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #748 = VLD4q16b
- { 749, 11, 5, 14, "VLD4q32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #749 = VLD4q32a
- { 750, 11, 5, 14, "VLD4q32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #750 = VLD4q32b
- { 751, 11, 5, 14, "VLD4q8a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #751 = VLD4q8a
- { 752, 11, 5, 14, "VLD4q8b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #752 = VLD4q8b
- { 753, 5, 0, 75, "VLDMD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|5|(3<<4)|(21<<9)|(3<<17), NULL, NULL, NULL, OperandInfo35 }, // Inst #753 = VLDMD
- { 754, 5, 0, 75, "VLDMS", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|5|(3<<4)|(21<<9)|(1<<17), NULL, NULL, NULL, OperandInfo35 }, // Inst #754 = VLDMS
- { 755, 5, 1, 74, "VLDRD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|5|(3<<4)|(20<<9)|(3<<17), NULL, NULL, NULL, OperandInfo96 }, // Inst #755 = VLDRD
- { 756, 5, 1, 75, "VLDRQ", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|4|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo97 }, // Inst #756 = VLDRQ
- { 757, 5, 1, 73, "VLDRS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|5|(3<<4)|(20<<9)|(1<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #757 = VLDRS
- { 758, 5, 1, 1, "VMAXfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #758 = VMAXfd
- { 759, 5, 1, 1, "VMAXfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #759 = VMAXfd_sfp
- { 760, 5, 1, 2, "VMAXfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #760 = VMAXfq
- { 761, 5, 1, 4, "VMAXsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #761 = VMAXsv16i8
- { 762, 5, 1, 3, "VMAXsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #762 = VMAXsv2i32
- { 763, 5, 1, 3, "VMAXsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #763 = VMAXsv4i16
- { 764, 5, 1, 4, "VMAXsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #764 = VMAXsv4i32
- { 765, 5, 1, 4, "VMAXsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #765 = VMAXsv8i16
- { 766, 5, 1, 3, "VMAXsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #766 = VMAXsv8i8
- { 767, 5, 1, 4, "VMAXuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #767 = VMAXuv16i8
- { 768, 5, 1, 3, "VMAXuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #768 = VMAXuv2i32
- { 769, 5, 1, 3, "VMAXuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #769 = VMAXuv4i16
- { 770, 5, 1, 4, "VMAXuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #770 = VMAXuv4i32
- { 771, 5, 1, 4, "VMAXuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #771 = VMAXuv8i16
- { 772, 5, 1, 3, "VMAXuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #772 = VMAXuv8i8
- { 773, 5, 1, 1, "VMINfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #773 = VMINfd
- { 774, 5, 1, 1, "VMINfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #774 = VMINfd_sfp
- { 775, 5, 1, 2, "VMINfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #775 = VMINfq
- { 776, 5, 1, 4, "VMINsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #776 = VMINsv16i8
- { 777, 5, 1, 3, "VMINsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #777 = VMINsv2i32
- { 778, 5, 1, 3, "VMINsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #778 = VMINsv4i16
- { 779, 5, 1, 4, "VMINsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #779 = VMINsv4i32
- { 780, 5, 1, 4, "VMINsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #780 = VMINsv8i16
- { 781, 5, 1, 3, "VMINsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #781 = VMINsv8i8
- { 782, 5, 1, 4, "VMINuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #782 = VMINuv16i8
- { 783, 5, 1, 3, "VMINuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #783 = VMINuv2i32
- { 784, 5, 1, 3, "VMINuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #784 = VMINuv4i16
- { 785, 5, 1, 4, "VMINuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #785 = VMINuv4i32
- { 786, 5, 1, 4, "VMINuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #786 = VMINuv8i16
- { 787, 5, 1, 3, "VMINuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #787 = VMINuv8i8
- { 788, 6, 1, 77, "VMLAD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #788 = VMLAD
- { 789, 7, 1, 19, "VMLALslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #789 = VMLALslsv2i32
- { 790, 7, 1, 17, "VMLALslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #790 = VMLALslsv4i16
- { 791, 7, 1, 19, "VMLALsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #791 = VMLALsluv2i32
- { 792, 7, 1, 17, "VMLALsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #792 = VMLALsluv4i16
- { 793, 6, 1, 17, "VMLALsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #793 = VMLALsv2i64
- { 794, 6, 1, 17, "VMLALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #794 = VMLALsv4i32
- { 795, 6, 1, 17, "VMLALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #795 = VMLALsv8i16
- { 796, 6, 1, 17, "VMLALuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #796 = VMLALuv2i64
- { 797, 6, 1, 17, "VMLALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #797 = VMLALuv4i32
- { 798, 6, 1, 17, "VMLALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #798 = VMLALuv8i16
- { 799, 6, 1, 76, "VMLAS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #799 = VMLAS
- { 800, 6, 1, 15, "VMLAfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #800 = VMLAfd
- { 801, 6, 1, 16, "VMLAfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #801 = VMLAfq
- { 802, 7, 1, 15, "VMLAslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #802 = VMLAslfd
- { 803, 7, 1, 16, "VMLAslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #803 = VMLAslfq
- { 804, 7, 1, 19, "VMLAslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #804 = VMLAslv2i32
- { 805, 7, 1, 17, "VMLAslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #805 = VMLAslv4i16
- { 806, 7, 1, 20, "VMLAslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #806 = VMLAslv4i32
- { 807, 7, 1, 18, "VMLAslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #807 = VMLAslv8i16
- { 808, 6, 1, 18, "VMLAv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #808 = VMLAv16i8
- { 809, 6, 1, 19, "VMLAv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #809 = VMLAv2i32
- { 810, 6, 1, 17, "VMLAv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #810 = VMLAv4i16
- { 811, 6, 1, 20, "VMLAv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #811 = VMLAv4i32
- { 812, 6, 1, 18, "VMLAv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #812 = VMLAv8i16
- { 813, 6, 1, 17, "VMLAv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #813 = VMLAv8i8
- { 814, 6, 1, 77, "VMLSD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #814 = VMLSD
- { 815, 7, 1, 19, "VMLSLslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #815 = VMLSLslsv2i32
- { 816, 7, 1, 17, "VMLSLslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #816 = VMLSLslsv4i16
- { 817, 7, 1, 19, "VMLSLsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #817 = VMLSLsluv2i32
- { 818, 7, 1, 17, "VMLSLsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #818 = VMLSLsluv4i16
- { 819, 6, 1, 17, "VMLSLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #819 = VMLSLsv2i64
- { 820, 6, 1, 17, "VMLSLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #820 = VMLSLsv4i32
- { 821, 6, 1, 17, "VMLSLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #821 = VMLSLsv8i16
- { 822, 6, 1, 17, "VMLSLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #822 = VMLSLuv2i64
- { 823, 6, 1, 17, "VMLSLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #823 = VMLSLuv4i32
- { 824, 6, 1, 17, "VMLSLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #824 = VMLSLuv8i16
- { 825, 6, 1, 76, "VMLSS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #825 = VMLSS
- { 826, 6, 1, 15, "VMLSfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #826 = VMLSfd
- { 827, 6, 1, 16, "VMLSfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #827 = VMLSfq
- { 828, 7, 1, 15, "VMLSslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #828 = VMLSslfd
- { 829, 7, 1, 16, "VMLSslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #829 = VMLSslfq
- { 830, 7, 1, 19, "VMLSslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #830 = VMLSslv2i32
- { 831, 7, 1, 17, "VMLSslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #831 = VMLSslv4i16
- { 832, 7, 1, 20, "VMLSslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #832 = VMLSslv4i32
- { 833, 7, 1, 18, "VMLSslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #833 = VMLSslv8i16
- { 834, 6, 1, 18, "VMLSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #834 = VMLSv16i8
- { 835, 6, 1, 19, "VMLSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #835 = VMLSv2i32
- { 836, 6, 1, 17, "VMLSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #836 = VMLSv4i16
- { 837, 6, 1, 20, "VMLSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #837 = VMLSv4i32
- { 838, 6, 1, 18, "VMLSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #838 = VMLSv8i16
- { 839, 6, 1, 17, "VMLSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #839 = VMLSv8i8
- { 840, 4, 1, 87, "VMOVD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #840 = VMOVD
- { 841, 5, 1, 23, "VMOVDRR", 0|(1<<TID::Predicable), 0|(3<<4)|(19<<9)|(1<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #841 = VMOVDRR
- { 842, 5, 1, 87, "VMOVDcc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #842 = VMOVDcc
- { 843, 4, 1, 21, "VMOVDneon", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #843 = VMOVDneon
- { 844, 4, 1, 38, "VMOVLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #844 = VMOVLsv2i64
- { 845, 4, 1, 38, "VMOVLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #845 = VMOVLsv4i32
- { 846, 4, 1, 38, "VMOVLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #846 = VMOVLsv8i16
- { 847, 4, 1, 38, "VMOVLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #847 = VMOVLuv2i64
- { 848, 4, 1, 38, "VMOVLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #848 = VMOVLuv4i32
- { 849, 4, 1, 38, "VMOVLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #849 = VMOVLuv8i16
- { 850, 4, 1, 21, "VMOVNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #850 = VMOVNv2i32
- { 851, 4, 1, 21, "VMOVNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #851 = VMOVNv4i16
- { 852, 4, 1, 21, "VMOVNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #852 = VMOVNv8i8
- { 853, 4, 1, 21, "VMOVQ", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #853 = VMOVQ
- { 854, 5, 2, 22, "VMOVRRD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(17<<9)|(1<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #854 = VMOVRRD
- { 855, 6, 2, 22, "VMOVRRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(17<<9)|(1<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #855 = VMOVRRS
- { 856, 4, 1, 28, "VMOVRS", 0|(1<<TID::Predicable), 0|(3<<4)|(16<<9)|(1<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #856 = VMOVRS
- { 857, 4, 1, 86, "VMOVS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #857 = VMOVS
- { 858, 4, 1, 24, "VMOVSR", 0|(1<<TID::Predicable), 0|(3<<4)|(18<<9)|(1<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #858 = VMOVSR
- { 859, 6, 2, 23, "VMOVSRR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(19<<9)|(1<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #859 = VMOVSRR
- { 860, 5, 1, 86, "VMOVScc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #860 = VMOVScc
- { 861, 4, 1, 26, "VMOVv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #861 = VMOVv16i8
- { 862, 4, 1, 26, "VMOVv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo29 }, // Inst #862 = VMOVv1i64
- { 863, 4, 1, 26, "VMOVv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo29 }, // Inst #863 = VMOVv2i32
- { 864, 4, 1, 26, "VMOVv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #864 = VMOVv2i64
- { 865, 4, 1, 26, "VMOVv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo29 }, // Inst #865 = VMOVv4i16
- { 866, 4, 1, 26, "VMOVv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #866 = VMOVv4i32
- { 867, 4, 1, 26, "VMOVv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #867 = VMOVv8i16
- { 868, 4, 1, 26, "VMOVv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo29 }, // Inst #868 = VMOVv8i8
- { 869, 3, 1, 82, "VMRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(22<<9)|(1<<17), ImplicitList5, NULL, NULL, OperandInfo21 }, // Inst #869 = VMRS
- { 870, 3, 0, 82, "VMSR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(22<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo21 }, // Inst #870 = VMSR
- { 871, 5, 1, 79, "VMULD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #871 = VMULD
- { 872, 5, 1, 29, "VMULLp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #872 = VMULLp
- { 873, 6, 1, 29, "VMULLslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #873 = VMULLslsv2i32
- { 874, 6, 1, 29, "VMULLslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #874 = VMULLslsv4i16
- { 875, 6, 1, 29, "VMULLsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #875 = VMULLsluv2i32
- { 876, 6, 1, 29, "VMULLsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #876 = VMULLsluv4i16
- { 877, 5, 1, 29, "VMULLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #877 = VMULLsv2i64
- { 878, 5, 1, 29, "VMULLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #878 = VMULLsv4i32
- { 879, 5, 1, 29, "VMULLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #879 = VMULLsv8i16
- { 880, 5, 1, 29, "VMULLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #880 = VMULLuv2i64
- { 881, 5, 1, 29, "VMULLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #881 = VMULLuv4i32
- { 882, 5, 1, 29, "VMULLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #882 = VMULLuv8i16
- { 883, 5, 1, 78, "VMULS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #883 = VMULS
- { 884, 5, 1, 1, "VMULfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #884 = VMULfd
- { 885, 5, 1, 1, "VMULfd_sfp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #885 = VMULfd_sfp
- { 886, 5, 1, 2, "VMULfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #886 = VMULfq
- { 887, 5, 1, 29, "VMULpd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #887 = VMULpd
- { 888, 5, 1, 30, "VMULpq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #888 = VMULpq
- { 889, 6, 1, 1, "VMULslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #889 = VMULslfd
- { 890, 6, 1, 2, "VMULslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #890 = VMULslfq
- { 891, 6, 1, 31, "VMULslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #891 = VMULslv2i32
- { 892, 6, 1, 29, "VMULslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #892 = VMULslv4i16
- { 893, 6, 1, 32, "VMULslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #893 = VMULslv4i32
- { 894, 6, 1, 30, "VMULslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo122 }, // Inst #894 = VMULslv8i16
- { 895, 5, 1, 30, "VMULv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #895 = VMULv16i8
- { 896, 5, 1, 31, "VMULv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #896 = VMULv2i32
- { 897, 5, 1, 29, "VMULv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #897 = VMULv4i16
- { 898, 5, 1, 32, "VMULv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #898 = VMULv4i32
- { 899, 5, 1, 30, "VMULv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #899 = VMULv8i16
- { 900, 5, 1, 29, "VMULv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #900 = VMULv8i8
- { 901, 4, 1, 44, "VMVNd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #901 = VMVNd
- { 902, 4, 1, 44, "VMVNq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #902 = VMVNq
- { 903, 4, 1, 87, "VNEGD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #903 = VNEGD
- { 904, 5, 1, 87, "VNEGDcc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #904 = VNEGDcc
- { 905, 4, 1, 86, "VNEGS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #905 = VNEGS
- { 906, 5, 1, 86, "VNEGScc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #906 = VNEGScc
- { 907, 4, 1, 58, "VNEGf32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #907 = VNEGf32q
- { 908, 4, 1, 57, "VNEGfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #908 = VNEGfd
- { 909, 4, 1, 57, "VNEGfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #909 = VNEGfd_sfp
- { 910, 4, 1, 44, "VNEGs16d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #910 = VNEGs16d
- { 911, 4, 1, 44, "VNEGs16q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #911 = VNEGs16q
- { 912, 4, 1, 44, "VNEGs32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #912 = VNEGs32d
- { 913, 4, 1, 44, "VNEGs32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #913 = VNEGs32q
- { 914, 4, 1, 44, "VNEGs8d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #914 = VNEGs8d
- { 915, 4, 1, 44, "VNEGs8q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #915 = VNEGs8q
- { 916, 6, 1, 77, "VNMLAD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #916 = VNMLAD
- { 917, 6, 1, 76, "VNMLAS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #917 = VNMLAS
- { 918, 6, 1, 77, "VNMLSD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #918 = VNMLSD
- { 919, 6, 1, 76, "VNMLSS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #919 = VNMLSS
- { 920, 5, 1, 79, "VNMULD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #920 = VNMULD
- { 921, 5, 1, 78, "VNMULS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #921 = VNMULS
- { 922, 5, 1, 5, "VORNd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #922 = VORNd
- { 923, 5, 1, 6, "VORNq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #923 = VORNq
- { 924, 5, 1, 5, "VORRd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #924 = VORRd
- { 925, 5, 1, 6, "VORRq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #925 = VORRq
- { 926, 5, 1, 34, "VPADALsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #926 = VPADALsv16i8
- { 927, 5, 1, 33, "VPADALsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #927 = VPADALsv2i32
- { 928, 5, 1, 33, "VPADALsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #928 = VPADALsv4i16
- { 929, 5, 1, 34, "VPADALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #929 = VPADALsv4i32
- { 930, 5, 1, 34, "VPADALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #930 = VPADALsv8i16
- { 931, 5, 1, 33, "VPADALsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #931 = VPADALsv8i8
- { 932, 5, 1, 34, "VPADALuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #932 = VPADALuv16i8
- { 933, 5, 1, 33, "VPADALuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #933 = VPADALuv2i32
- { 934, 5, 1, 33, "VPADALuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #934 = VPADALuv4i16
- { 935, 5, 1, 34, "VPADALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #935 = VPADALuv4i32
- { 936, 5, 1, 34, "VPADALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #936 = VPADALuv8i16
- { 937, 5, 1, 33, "VPADALuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #937 = VPADALuv8i8
- { 938, 4, 1, 44, "VPADDLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #938 = VPADDLsv16i8
- { 939, 4, 1, 44, "VPADDLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #939 = VPADDLsv2i32
- { 940, 4, 1, 44, "VPADDLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #940 = VPADDLsv4i16
- { 941, 4, 1, 44, "VPADDLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #941 = VPADDLsv4i32
- { 942, 4, 1, 44, "VPADDLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #942 = VPADDLsv8i16
- { 943, 4, 1, 44, "VPADDLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #943 = VPADDLsv8i8
- { 944, 4, 1, 44, "VPADDLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #944 = VPADDLuv16i8
- { 945, 4, 1, 44, "VPADDLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #945 = VPADDLuv2i32
- { 946, 4, 1, 44, "VPADDLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #946 = VPADDLuv4i16
- { 947, 4, 1, 44, "VPADDLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #947 = VPADDLuv4i32
- { 948, 4, 1, 44, "VPADDLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #948 = VPADDLuv8i16
- { 949, 4, 1, 44, "VPADDLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #949 = VPADDLuv8i8
- { 950, 5, 1, 1, "VPADDf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #950 = VPADDf
- { 951, 5, 1, 5, "VPADDi16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #951 = VPADDi16
- { 952, 5, 1, 5, "VPADDi32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #952 = VPADDi32
- { 953, 5, 1, 5, "VPADDi8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #953 = VPADDi8
- { 954, 5, 1, 3, "VPMAXf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #954 = VPMAXf
- { 955, 5, 1, 3, "VPMAXs16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #955 = VPMAXs16
- { 956, 5, 1, 3, "VPMAXs32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #956 = VPMAXs32
- { 957, 5, 1, 3, "VPMAXs8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #957 = VPMAXs8
- { 958, 5, 1, 3, "VPMAXu16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #958 = VPMAXu16
- { 959, 5, 1, 3, "VPMAXu32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #959 = VPMAXu32
- { 960, 5, 1, 3, "VPMAXu8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #960 = VPMAXu8
- { 961, 5, 1, 3, "VPMINf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #961 = VPMINf
- { 962, 5, 1, 3, "VPMINs16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #962 = VPMINs16
- { 963, 5, 1, 3, "VPMINs32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #963 = VPMINs32
- { 964, 5, 1, 3, "VPMINs8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #964 = VPMINs8
- { 965, 5, 1, 3, "VPMINu16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #965 = VPMINu16
- { 966, 5, 1, 3, "VPMINu32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #966 = VPMINu32
- { 967, 5, 1, 3, "VPMINu8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #967 = VPMINu8
- { 968, 4, 1, 39, "VQABSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #968 = VQABSv16i8
- { 969, 4, 1, 38, "VQABSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #969 = VQABSv2i32
- { 970, 4, 1, 38, "VQABSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #970 = VQABSv4i16
- { 971, 4, 1, 39, "VQABSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #971 = VQABSv4i32
- { 972, 4, 1, 39, "VQABSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #972 = VQABSv8i16
- { 973, 4, 1, 38, "VQABSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #973 = VQABSv8i8
- { 974, 5, 1, 4, "VQADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #974 = VQADDsv16i8
- { 975, 5, 1, 3, "VQADDsv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #975 = VQADDsv1i64
- { 976, 5, 1, 3, "VQADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #976 = VQADDsv2i32
- { 977, 5, 1, 4, "VQADDsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #977 = VQADDsv2i64
- { 978, 5, 1, 3, "VQADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #978 = VQADDsv4i16
- { 979, 5, 1, 4, "VQADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #979 = VQADDsv4i32
- { 980, 5, 1, 4, "VQADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #980 = VQADDsv8i16
- { 981, 5, 1, 3, "VQADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #981 = VQADDsv8i8
- { 982, 5, 1, 4, "VQADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #982 = VQADDuv16i8
- { 983, 5, 1, 3, "VQADDuv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #983 = VQADDuv1i64
- { 984, 5, 1, 3, "VQADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #984 = VQADDuv2i32
- { 985, 5, 1, 4, "VQADDuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #985 = VQADDuv2i64
- { 986, 5, 1, 3, "VQADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #986 = VQADDuv4i16
- { 987, 5, 1, 4, "VQADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #987 = VQADDuv4i32
- { 988, 5, 1, 4, "VQADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #988 = VQADDuv8i16
- { 989, 5, 1, 3, "VQADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #989 = VQADDuv8i8
- { 990, 7, 1, 19, "VQDMLALslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #990 = VQDMLALslv2i32
- { 991, 7, 1, 17, "VQDMLALslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #991 = VQDMLALslv4i16
- { 992, 6, 1, 17, "VQDMLALv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #992 = VQDMLALv2i64
- { 993, 6, 1, 17, "VQDMLALv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #993 = VQDMLALv4i32
- { 994, 7, 1, 19, "VQDMLSLslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #994 = VQDMLSLslv2i32
- { 995, 7, 1, 17, "VQDMLSLslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #995 = VQDMLSLslv4i16
- { 996, 6, 1, 17, "VQDMLSLv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #996 = VQDMLSLv2i64
- { 997, 6, 1, 17, "VQDMLSLv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #997 = VQDMLSLv4i32
- { 998, 6, 1, 31, "VQDMULHslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #998 = VQDMULHslv2i32
- { 999, 6, 1, 29, "VQDMULHslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #999 = VQDMULHslv4i16
- { 1000, 6, 1, 32, "VQDMULHslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #1000 = VQDMULHslv4i32
- { 1001, 6, 1, 30, "VQDMULHslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo122 }, // Inst #1001 = VQDMULHslv8i16
- { 1002, 5, 1, 31, "VQDMULHv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1002 = VQDMULHv2i32
- { 1003, 5, 1, 29, "VQDMULHv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1003 = VQDMULHv4i16
- { 1004, 5, 1, 32, "VQDMULHv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1004 = VQDMULHv4i32
- { 1005, 5, 1, 30, "VQDMULHv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1005 = VQDMULHv8i16
- { 1006, 6, 1, 29, "VQDMULLslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1006 = VQDMULLslv2i32
- { 1007, 6, 1, 29, "VQDMULLslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1007 = VQDMULLslv4i16
- { 1008, 5, 1, 29, "VQDMULLv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1008 = VQDMULLv2i64
- { 1009, 5, 1, 29, "VQDMULLv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1009 = VQDMULLv4i32
- { 1010, 4, 1, 38, "VQMOVNsuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1010 = VQMOVNsuv2i32
- { 1011, 4, 1, 38, "VQMOVNsuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1011 = VQMOVNsuv4i16
- { 1012, 4, 1, 38, "VQMOVNsuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1012 = VQMOVNsuv8i8
- { 1013, 4, 1, 38, "VQMOVNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1013 = VQMOVNsv2i32
- { 1014, 4, 1, 38, "VQMOVNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1014 = VQMOVNsv4i16
- { 1015, 4, 1, 38, "VQMOVNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1015 = VQMOVNsv8i8
- { 1016, 4, 1, 38, "VQMOVNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1016 = VQMOVNuv2i32
- { 1017, 4, 1, 38, "VQMOVNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1017 = VQMOVNuv4i16
- { 1018, 4, 1, 38, "VQMOVNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1018 = VQMOVNuv8i8
- { 1019, 4, 1, 39, "VQNEGv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1019 = VQNEGv16i8
- { 1020, 4, 1, 38, "VQNEGv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1020 = VQNEGv2i32
- { 1021, 4, 1, 38, "VQNEGv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1021 = VQNEGv4i16
- { 1022, 4, 1, 39, "VQNEGv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1022 = VQNEGv4i32
- { 1023, 4, 1, 39, "VQNEGv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1023 = VQNEGv8i16
- { 1024, 4, 1, 38, "VQNEGv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1024 = VQNEGv8i8
- { 1025, 6, 1, 31, "VQRDMULHslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1025 = VQRDMULHslv2i32
- { 1026, 6, 1, 29, "VQRDMULHslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #1026 = VQRDMULHslv4i16
- { 1027, 6, 1, 32, "VQRDMULHslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #1027 = VQRDMULHslv4i32
- { 1028, 6, 1, 30, "VQRDMULHslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo122 }, // Inst #1028 = VQRDMULHslv8i16
- { 1029, 5, 1, 31, "VQRDMULHv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1029 = VQRDMULHv2i32
- { 1030, 5, 1, 29, "VQRDMULHv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1030 = VQRDMULHv4i16
- { 1031, 5, 1, 32, "VQRDMULHv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1031 = VQRDMULHv4i32
- { 1032, 5, 1, 30, "VQRDMULHv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1032 = VQRDMULHv8i16
- { 1033, 5, 1, 43, "VQRSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1033 = VQRSHLsv16i8
- { 1034, 5, 1, 42, "VQRSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1034 = VQRSHLsv1i64
- { 1035, 5, 1, 42, "VQRSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1035 = VQRSHLsv2i32
- { 1036, 5, 1, 43, "VQRSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1036 = VQRSHLsv2i64
- { 1037, 5, 1, 42, "VQRSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1037 = VQRSHLsv4i16
- { 1038, 5, 1, 43, "VQRSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1038 = VQRSHLsv4i32
- { 1039, 5, 1, 43, "VQRSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1039 = VQRSHLsv8i16
- { 1040, 5, 1, 42, "VQRSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1040 = VQRSHLsv8i8
- { 1041, 5, 1, 43, "VQRSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1041 = VQRSHLuv16i8
- { 1042, 5, 1, 42, "VQRSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1042 = VQRSHLuv1i64
- { 1043, 5, 1, 42, "VQRSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1043 = VQRSHLuv2i32
- { 1044, 5, 1, 43, "VQRSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1044 = VQRSHLuv2i64
- { 1045, 5, 1, 42, "VQRSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1045 = VQRSHLuv4i16
- { 1046, 5, 1, 43, "VQRSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1046 = VQRSHLuv4i32
- { 1047, 5, 1, 43, "VQRSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1047 = VQRSHLuv8i16
- { 1048, 5, 1, 42, "VQRSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1048 = VQRSHLuv8i8
- { 1049, 5, 1, 42, "VQRSHRNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1049 = VQRSHRNsv2i32
- { 1050, 5, 1, 42, "VQRSHRNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1050 = VQRSHRNsv4i16
- { 1051, 5, 1, 42, "VQRSHRNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1051 = VQRSHRNsv8i8
- { 1052, 5, 1, 42, "VQRSHRNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1052 = VQRSHRNuv2i32
- { 1053, 5, 1, 42, "VQRSHRNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1053 = VQRSHRNuv4i16
- { 1054, 5, 1, 42, "VQRSHRNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1054 = VQRSHRNuv8i8
- { 1055, 5, 1, 42, "VQRSHRUNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1055 = VQRSHRUNv2i32
- { 1056, 5, 1, 42, "VQRSHRUNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1056 = VQRSHRUNv4i16
- { 1057, 5, 1, 42, "VQRSHRUNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1057 = VQRSHRUNv8i8
- { 1058, 5, 1, 42, "VQSHLsiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1058 = VQSHLsiv16i8
- { 1059, 5, 1, 42, "VQSHLsiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1059 = VQSHLsiv1i64
- { 1060, 5, 1, 42, "VQSHLsiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1060 = VQSHLsiv2i32
- { 1061, 5, 1, 42, "VQSHLsiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1061 = VQSHLsiv2i64
- { 1062, 5, 1, 42, "VQSHLsiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1062 = VQSHLsiv4i16
- { 1063, 5, 1, 42, "VQSHLsiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1063 = VQSHLsiv4i32
- { 1064, 5, 1, 42, "VQSHLsiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1064 = VQSHLsiv8i16
- { 1065, 5, 1, 42, "VQSHLsiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1065 = VQSHLsiv8i8
- { 1066, 5, 1, 42, "VQSHLsuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1066 = VQSHLsuv16i8
- { 1067, 5, 1, 42, "VQSHLsuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1067 = VQSHLsuv1i64
- { 1068, 5, 1, 42, "VQSHLsuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1068 = VQSHLsuv2i32
- { 1069, 5, 1, 42, "VQSHLsuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1069 = VQSHLsuv2i64
- { 1070, 5, 1, 42, "VQSHLsuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1070 = VQSHLsuv4i16
- { 1071, 5, 1, 42, "VQSHLsuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1071 = VQSHLsuv4i32
- { 1072, 5, 1, 42, "VQSHLsuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1072 = VQSHLsuv8i16
- { 1073, 5, 1, 42, "VQSHLsuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1073 = VQSHLsuv8i8
- { 1074, 5, 1, 43, "VQSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1074 = VQSHLsv16i8
- { 1075, 5, 1, 42, "VQSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1075 = VQSHLsv1i64
- { 1076, 5, 1, 42, "VQSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1076 = VQSHLsv2i32
- { 1077, 5, 1, 43, "VQSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1077 = VQSHLsv2i64
- { 1078, 5, 1, 42, "VQSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1078 = VQSHLsv4i16
- { 1079, 5, 1, 43, "VQSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1079 = VQSHLsv4i32
- { 1080, 5, 1, 43, "VQSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1080 = VQSHLsv8i16
- { 1081, 5, 1, 42, "VQSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1081 = VQSHLsv8i8
- { 1082, 5, 1, 42, "VQSHLuiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1082 = VQSHLuiv16i8
- { 1083, 5, 1, 42, "VQSHLuiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1083 = VQSHLuiv1i64
- { 1084, 5, 1, 42, "VQSHLuiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1084 = VQSHLuiv2i32
- { 1085, 5, 1, 42, "VQSHLuiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1085 = VQSHLuiv2i64
- { 1086, 5, 1, 42, "VQSHLuiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1086 = VQSHLuiv4i16
- { 1087, 5, 1, 42, "VQSHLuiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1087 = VQSHLuiv4i32
- { 1088, 5, 1, 42, "VQSHLuiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1088 = VQSHLuiv8i16
- { 1089, 5, 1, 42, "VQSHLuiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1089 = VQSHLuiv8i8
- { 1090, 5, 1, 43, "VQSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1090 = VQSHLuv16i8
- { 1091, 5, 1, 42, "VQSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1091 = VQSHLuv1i64
- { 1092, 5, 1, 42, "VQSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1092 = VQSHLuv2i32
- { 1093, 5, 1, 43, "VQSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1093 = VQSHLuv2i64
- { 1094, 5, 1, 42, "VQSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1094 = VQSHLuv4i16
- { 1095, 5, 1, 43, "VQSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1095 = VQSHLuv4i32
- { 1096, 5, 1, 43, "VQSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1096 = VQSHLuv8i16
- { 1097, 5, 1, 42, "VQSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1097 = VQSHLuv8i8
- { 1098, 5, 1, 42, "VQSHRNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1098 = VQSHRNsv2i32
- { 1099, 5, 1, 42, "VQSHRNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1099 = VQSHRNsv4i16
- { 1100, 5, 1, 42, "VQSHRNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1100 = VQSHRNsv8i8
- { 1101, 5, 1, 42, "VQSHRNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1101 = VQSHRNuv2i32
- { 1102, 5, 1, 42, "VQSHRNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1102 = VQSHRNuv4i16
- { 1103, 5, 1, 42, "VQSHRNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1103 = VQSHRNuv8i8
- { 1104, 5, 1, 42, "VQSHRUNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1104 = VQSHRUNv2i32
- { 1105, 5, 1, 42, "VQSHRUNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1105 = VQSHRUNv4i16
- { 1106, 5, 1, 42, "VQSHRUNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1106 = VQSHRUNv8i8
- { 1107, 5, 1, 4, "VQSUBsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1107 = VQSUBsv16i8
- { 1108, 5, 1, 3, "VQSUBsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1108 = VQSUBsv1i64
- { 1109, 5, 1, 3, "VQSUBsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1109 = VQSUBsv2i32
- { 1110, 5, 1, 4, "VQSUBsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1110 = VQSUBsv2i64
- { 1111, 5, 1, 3, "VQSUBsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1111 = VQSUBsv4i16
- { 1112, 5, 1, 4, "VQSUBsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1112 = VQSUBsv4i32
- { 1113, 5, 1, 4, "VQSUBsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1113 = VQSUBsv8i16
- { 1114, 5, 1, 3, "VQSUBsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1114 = VQSUBsv8i8
- { 1115, 5, 1, 4, "VQSUBuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1115 = VQSUBuv16i8
- { 1116, 5, 1, 3, "VQSUBuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1116 = VQSUBuv1i64
- { 1117, 5, 1, 3, "VQSUBuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1117 = VQSUBuv2i32
- { 1118, 5, 1, 4, "VQSUBuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1118 = VQSUBuv2i64
- { 1119, 5, 1, 3, "VQSUBuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1119 = VQSUBuv4i16
- { 1120, 5, 1, 4, "VQSUBuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1120 = VQSUBuv4i32
- { 1121, 5, 1, 4, "VQSUBuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1121 = VQSUBuv8i16
- { 1122, 5, 1, 3, "VQSUBuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1122 = VQSUBuv8i8
- { 1123, 5, 1, 3, "VRADDHNv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1123 = VRADDHNv2i32
- { 1124, 5, 1, 3, "VRADDHNv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1124 = VRADDHNv4i16
- { 1125, 5, 1, 3, "VRADDHNv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1125 = VRADDHNv8i8
- { 1126, 4, 1, 57, "VRECPEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1126 = VRECPEd
- { 1127, 4, 1, 57, "VRECPEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1127 = VRECPEfd
- { 1128, 4, 1, 58, "VRECPEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1128 = VRECPEfq
- { 1129, 4, 1, 58, "VRECPEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1129 = VRECPEq
- { 1130, 5, 1, 40, "VRECPSfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1130 = VRECPSfd
- { 1131, 5, 1, 41, "VRECPSfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1131 = VRECPSfq
- { 1132, 4, 1, 21, "VREV16d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1132 = VREV16d8
- { 1133, 4, 1, 21, "VREV16q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1133 = VREV16q8
- { 1134, 4, 1, 21, "VREV32d16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1134 = VREV32d16
- { 1135, 4, 1, 21, "VREV32d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1135 = VREV32d8
- { 1136, 4, 1, 21, "VREV32q16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1136 = VREV32q16
- { 1137, 4, 1, 21, "VREV32q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1137 = VREV32q8
- { 1138, 4, 1, 21, "VREV64d16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1138 = VREV64d16
- { 1139, 4, 1, 21, "VREV64d32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1139 = VREV64d32
- { 1140, 4, 1, 21, "VREV64d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1140 = VREV64d8
- { 1141, 4, 1, 21, "VREV64df", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1141 = VREV64df
- { 1142, 4, 1, 21, "VREV64q16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1142 = VREV64q16
- { 1143, 4, 1, 21, "VREV64q32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1143 = VREV64q32
- { 1144, 4, 1, 21, "VREV64q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1144 = VREV64q8
- { 1145, 4, 1, 21, "VREV64qf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1145 = VREV64qf
- { 1146, 5, 1, 4, "VRHADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1146 = VRHADDsv16i8
- { 1147, 5, 1, 3, "VRHADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1147 = VRHADDsv2i32
- { 1148, 5, 1, 3, "VRHADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1148 = VRHADDsv4i16
- { 1149, 5, 1, 4, "VRHADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1149 = VRHADDsv4i32
- { 1150, 5, 1, 4, "VRHADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1150 = VRHADDsv8i16
- { 1151, 5, 1, 3, "VRHADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1151 = VRHADDsv8i8
- { 1152, 5, 1, 4, "VRHADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1152 = VRHADDuv16i8
- { 1153, 5, 1, 3, "VRHADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1153 = VRHADDuv2i32
- { 1154, 5, 1, 3, "VRHADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1154 = VRHADDuv4i16
- { 1155, 5, 1, 4, "VRHADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1155 = VRHADDuv4i32
- { 1156, 5, 1, 4, "VRHADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1156 = VRHADDuv8i16
- { 1157, 5, 1, 3, "VRHADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1157 = VRHADDuv8i8
- { 1158, 5, 1, 43, "VRSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1158 = VRSHLsv16i8
- { 1159, 5, 1, 42, "VRSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1159 = VRSHLsv1i64
- { 1160, 5, 1, 42, "VRSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1160 = VRSHLsv2i32
- { 1161, 5, 1, 43, "VRSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1161 = VRSHLsv2i64
- { 1162, 5, 1, 42, "VRSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1162 = VRSHLsv4i16
- { 1163, 5, 1, 43, "VRSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1163 = VRSHLsv4i32
- { 1164, 5, 1, 43, "VRSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1164 = VRSHLsv8i16
- { 1165, 5, 1, 42, "VRSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1165 = VRSHLsv8i8
- { 1166, 5, 1, 43, "VRSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1166 = VRSHLuv16i8
- { 1167, 5, 1, 42, "VRSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1167 = VRSHLuv1i64
- { 1168, 5, 1, 42, "VRSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1168 = VRSHLuv2i32
- { 1169, 5, 1, 43, "VRSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1169 = VRSHLuv2i64
- { 1170, 5, 1, 42, "VRSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1170 = VRSHLuv4i16
- { 1171, 5, 1, 43, "VRSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1171 = VRSHLuv4i32
- { 1172, 5, 1, 43, "VRSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1172 = VRSHLuv8i16
- { 1173, 5, 1, 42, "VRSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1173 = VRSHLuv8i8
- { 1174, 5, 1, 42, "VRSHRNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1174 = VRSHRNv2i32
- { 1175, 5, 1, 42, "VRSHRNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1175 = VRSHRNv4i16
- { 1176, 5, 1, 42, "VRSHRNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1176 = VRSHRNv8i8
- { 1177, 5, 1, 42, "VRSHRsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1177 = VRSHRsv16i8
- { 1178, 5, 1, 42, "VRSHRsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1178 = VRSHRsv1i64
- { 1179, 5, 1, 42, "VRSHRsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1179 = VRSHRsv2i32
- { 1180, 5, 1, 42, "VRSHRsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1180 = VRSHRsv2i64
- { 1181, 5, 1, 42, "VRSHRsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1181 = VRSHRsv4i16
- { 1182, 5, 1, 42, "VRSHRsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1182 = VRSHRsv4i32
- { 1183, 5, 1, 42, "VRSHRsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1183 = VRSHRsv8i16
- { 1184, 5, 1, 42, "VRSHRsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1184 = VRSHRsv8i8
- { 1185, 5, 1, 42, "VRSHRuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1185 = VRSHRuv16i8
- { 1186, 5, 1, 42, "VRSHRuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1186 = VRSHRuv1i64
- { 1187, 5, 1, 42, "VRSHRuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1187 = VRSHRuv2i32
- { 1188, 5, 1, 42, "VRSHRuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1188 = VRSHRuv2i64
- { 1189, 5, 1, 42, "VRSHRuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1189 = VRSHRuv4i16
- { 1190, 5, 1, 42, "VRSHRuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1190 = VRSHRuv4i32
- { 1191, 5, 1, 42, "VRSHRuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1191 = VRSHRuv8i16
- { 1192, 5, 1, 42, "VRSHRuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1192 = VRSHRuv8i8
- { 1193, 4, 1, 57, "VRSQRTEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1193 = VRSQRTEd
- { 1194, 4, 1, 57, "VRSQRTEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1194 = VRSQRTEfd
- { 1195, 4, 1, 58, "VRSQRTEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1195 = VRSQRTEfq
- { 1196, 4, 1, 58, "VRSQRTEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1196 = VRSQRTEq
- { 1197, 5, 1, 40, "VRSQRTSfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1197 = VRSQRTSfd
- { 1198, 5, 1, 41, "VRSQRTSfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1198 = VRSQRTSfq
- { 1199, 6, 1, 33, "VRSRAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1199 = VRSRAsv16i8
- { 1200, 6, 1, 33, "VRSRAsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1200 = VRSRAsv1i64
- { 1201, 6, 1, 33, "VRSRAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1201 = VRSRAsv2i32
- { 1202, 6, 1, 33, "VRSRAsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1202 = VRSRAsv2i64
- { 1203, 6, 1, 33, "VRSRAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1203 = VRSRAsv4i16
- { 1204, 6, 1, 33, "VRSRAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1204 = VRSRAsv4i32
- { 1205, 6, 1, 33, "VRSRAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1205 = VRSRAsv8i16
- { 1206, 6, 1, 33, "VRSRAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1206 = VRSRAsv8i8
- { 1207, 6, 1, 33, "VRSRAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1207 = VRSRAuv16i8
- { 1208, 6, 1, 33, "VRSRAuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1208 = VRSRAuv1i64
- { 1209, 6, 1, 33, "VRSRAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1209 = VRSRAuv2i32
- { 1210, 6, 1, 33, "VRSRAuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1210 = VRSRAuv2i64
- { 1211, 6, 1, 33, "VRSRAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1211 = VRSRAuv4i16
- { 1212, 6, 1, 33, "VRSRAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1212 = VRSRAuv4i32
- { 1213, 6, 1, 33, "VRSRAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1213 = VRSRAuv8i16
- { 1214, 6, 1, 33, "VRSRAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1214 = VRSRAuv8i8
- { 1215, 5, 1, 3, "VRSUBHNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1215 = VRSUBHNv2i32
- { 1216, 5, 1, 3, "VRSUBHNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1216 = VRSUBHNv4i16
- { 1217, 5, 1, 3, "VRSUBHNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1217 = VRSUBHNv8i8
- { 1218, 6, 1, 25, "VSETLNi16", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo127 }, // Inst #1218 = VSETLNi16
- { 1219, 6, 1, 25, "VSETLNi32", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo127 }, // Inst #1219 = VSETLNi32
- { 1220, 6, 1, 25, "VSETLNi8", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo127 }, // Inst #1220 = VSETLNi8
- { 1221, 5, 1, 44, "VSHLLi16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1221 = VSHLLi16
- { 1222, 5, 1, 44, "VSHLLi32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1222 = VSHLLi32
- { 1223, 5, 1, 44, "VSHLLi8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1223 = VSHLLi8
- { 1224, 5, 1, 44, "VSHLLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1224 = VSHLLsv2i64
- { 1225, 5, 1, 44, "VSHLLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1225 = VSHLLsv4i32
- { 1226, 5, 1, 44, "VSHLLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1226 = VSHLLsv8i16
- { 1227, 5, 1, 44, "VSHLLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1227 = VSHLLuv2i64
- { 1228, 5, 1, 44, "VSHLLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1228 = VSHLLuv4i32
- { 1229, 5, 1, 44, "VSHLLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1229 = VSHLLuv8i16
- { 1230, 5, 1, 44, "VSHLiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1230 = VSHLiv16i8
- { 1231, 5, 1, 44, "VSHLiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1231 = VSHLiv1i64
- { 1232, 5, 1, 44, "VSHLiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1232 = VSHLiv2i32
- { 1233, 5, 1, 44, "VSHLiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1233 = VSHLiv2i64
- { 1234, 5, 1, 44, "VSHLiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1234 = VSHLiv4i16
- { 1235, 5, 1, 44, "VSHLiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1235 = VSHLiv4i32
- { 1236, 5, 1, 44, "VSHLiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1236 = VSHLiv8i16
- { 1237, 5, 1, 44, "VSHLiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1237 = VSHLiv8i8
- { 1238, 5, 1, 45, "VSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1238 = VSHLsv16i8
- { 1239, 5, 1, 44, "VSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1239 = VSHLsv1i64
- { 1240, 5, 1, 44, "VSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1240 = VSHLsv2i32
- { 1241, 5, 1, 45, "VSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1241 = VSHLsv2i64
- { 1242, 5, 1, 44, "VSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1242 = VSHLsv4i16
- { 1243, 5, 1, 45, "VSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1243 = VSHLsv4i32
- { 1244, 5, 1, 45, "VSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1244 = VSHLsv8i16
- { 1245, 5, 1, 44, "VSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1245 = VSHLsv8i8
- { 1246, 5, 1, 45, "VSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1246 = VSHLuv16i8
- { 1247, 5, 1, 44, "VSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1247 = VSHLuv1i64
- { 1248, 5, 1, 44, "VSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1248 = VSHLuv2i32
- { 1249, 5, 1, 45, "VSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1249 = VSHLuv2i64
- { 1250, 5, 1, 44, "VSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1250 = VSHLuv4i16
- { 1251, 5, 1, 45, "VSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1251 = VSHLuv4i32
- { 1252, 5, 1, 45, "VSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1252 = VSHLuv8i16
- { 1253, 5, 1, 44, "VSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1253 = VSHLuv8i8
- { 1254, 5, 1, 44, "VSHRNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1254 = VSHRNv2i32
- { 1255, 5, 1, 44, "VSHRNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1255 = VSHRNv4i16
- { 1256, 5, 1, 44, "VSHRNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1256 = VSHRNv8i8
- { 1257, 5, 1, 44, "VSHRsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1257 = VSHRsv16i8
- { 1258, 5, 1, 44, "VSHRsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1258 = VSHRsv1i64
- { 1259, 5, 1, 44, "VSHRsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1259 = VSHRsv2i32
- { 1260, 5, 1, 44, "VSHRsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1260 = VSHRsv2i64
- { 1261, 5, 1, 44, "VSHRsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1261 = VSHRsv4i16
- { 1262, 5, 1, 44, "VSHRsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1262 = VSHRsv4i32
- { 1263, 5, 1, 44, "VSHRsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1263 = VSHRsv8i16
- { 1264, 5, 1, 44, "VSHRsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1264 = VSHRsv8i8
- { 1265, 5, 1, 44, "VSHRuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1265 = VSHRuv16i8
- { 1266, 5, 1, 44, "VSHRuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1266 = VSHRuv1i64
- { 1267, 5, 1, 44, "VSHRuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1267 = VSHRuv2i32
- { 1268, 5, 1, 44, "VSHRuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1268 = VSHRuv2i64
- { 1269, 5, 1, 44, "VSHRuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1269 = VSHRuv4i16
- { 1270, 5, 1, 44, "VSHRuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1270 = VSHRuv4i32
- { 1271, 5, 1, 44, "VSHRuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1271 = VSHRuv8i16
- { 1272, 5, 1, 44, "VSHRuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1272 = VSHRuv8i8
- { 1273, 5, 1, 67, "VSHTOD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1273 = VSHTOD
- { 1274, 5, 1, 68, "VSHTOS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1274 = VSHTOS
- { 1275, 4, 1, 67, "VSITOD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #1275 = VSITOD
- { 1276, 4, 1, 68, "VSITOS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #1276 = VSITOS
- { 1277, 6, 1, 45, "VSLIv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1277 = VSLIv16i8
- { 1278, 6, 1, 44, "VSLIv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1278 = VSLIv1i64
- { 1279, 6, 1, 44, "VSLIv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1279 = VSLIv2i32
- { 1280, 6, 1, 45, "VSLIv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1280 = VSLIv2i64
- { 1281, 6, 1, 44, "VSLIv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1281 = VSLIv4i16
- { 1282, 6, 1, 45, "VSLIv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1282 = VSLIv4i32
- { 1283, 6, 1, 45, "VSLIv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1283 = VSLIv8i16
- { 1284, 6, 1, 44, "VSLIv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1284 = VSLIv8i8
- { 1285, 5, 1, 67, "VSLTOD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1285 = VSLTOD
- { 1286, 5, 1, 68, "VSLTOS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1286 = VSLTOS
- { 1287, 4, 1, 81, "VSQRTD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1287 = VSQRTD
- { 1288, 4, 1, 80, "VSQRTS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #1288 = VSQRTS
- { 1289, 6, 1, 33, "VSRAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1289 = VSRAsv16i8
- { 1290, 6, 1, 33, "VSRAsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1290 = VSRAsv1i64
- { 1291, 6, 1, 33, "VSRAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1291 = VSRAsv2i32
- { 1292, 6, 1, 33, "VSRAsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1292 = VSRAsv2i64
- { 1293, 6, 1, 33, "VSRAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1293 = VSRAsv4i16
- { 1294, 6, 1, 33, "VSRAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1294 = VSRAsv4i32
- { 1295, 6, 1, 33, "VSRAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1295 = VSRAsv8i16
- { 1296, 6, 1, 33, "VSRAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1296 = VSRAsv8i8
- { 1297, 6, 1, 33, "VSRAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1297 = VSRAuv16i8
- { 1298, 6, 1, 33, "VSRAuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1298 = VSRAuv1i64
- { 1299, 6, 1, 33, "VSRAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1299 = VSRAuv2i32
- { 1300, 6, 1, 33, "VSRAuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1300 = VSRAuv2i64
- { 1301, 6, 1, 33, "VSRAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1301 = VSRAuv4i16
- { 1302, 6, 1, 33, "VSRAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1302 = VSRAuv4i32
- { 1303, 6, 1, 33, "VSRAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1303 = VSRAuv8i16
- { 1304, 6, 1, 33, "VSRAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1304 = VSRAuv8i8
- { 1305, 6, 1, 45, "VSRIv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1305 = VSRIv16i8
- { 1306, 6, 1, 44, "VSRIv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1306 = VSRIv1i64
- { 1307, 6, 1, 44, "VSRIv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1307 = VSRIv2i32
- { 1308, 6, 1, 45, "VSRIv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1308 = VSRIv2i64
- { 1309, 6, 1, 44, "VSRIv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1309 = VSRIv4i16
- { 1310, 6, 1, 45, "VSRIv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1310 = VSRIv4i32
- { 1311, 6, 1, 45, "VSRIv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1311 = VSRIv8i16
- { 1312, 6, 1, 44, "VSRIv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1312 = VSRIv8i8
- { 1313, 7, 0, 46, "VST1d16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 }, // Inst #1313 = VST1d16
- { 1314, 10, 0, 46, "VST1d16Q", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1314 = VST1d16Q
- { 1315, 9, 0, 46, "VST1d16T", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 }, // Inst #1315 = VST1d16T
- { 1316, 7, 0, 46, "VST1d32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 }, // Inst #1316 = VST1d32
- { 1317, 10, 0, 46, "VST1d32Q", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1317 = VST1d32Q
- { 1318, 9, 0, 46, "VST1d32T", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 }, // Inst #1318 = VST1d32T
- { 1319, 7, 0, 46, "VST1d64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 }, // Inst #1319 = VST1d64
- { 1320, 7, 0, 46, "VST1d8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 }, // Inst #1320 = VST1d8
- { 1321, 10, 0, 46, "VST1d8Q", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1321 = VST1d8Q
- { 1322, 9, 0, 46, "VST1d8T", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 }, // Inst #1322 = VST1d8T
- { 1323, 7, 0, 46, "VST1df", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 }, // Inst #1323 = VST1df
- { 1324, 7, 0, 46, "VST1q16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo133 }, // Inst #1324 = VST1q16
- { 1325, 7, 0, 46, "VST1q32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo133 }, // Inst #1325 = VST1q32
- { 1326, 7, 0, 46, "VST1q64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo133 }, // Inst #1326 = VST1q64
- { 1327, 7, 0, 46, "VST1q8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo133 }, // Inst #1327 = VST1q8
- { 1328, 7, 0, 46, "VST1qf", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo133 }, // Inst #1328 = VST1qf
- { 1329, 9, 0, 46, "VST2LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 }, // Inst #1329 = VST2LNd16
- { 1330, 9, 0, 46, "VST2LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 }, // Inst #1330 = VST2LNd32
- { 1331, 9, 0, 46, "VST2LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 }, // Inst #1331 = VST2LNd8
- { 1332, 9, 0, 46, "VST2LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 }, // Inst #1332 = VST2LNq16a
- { 1333, 9, 0, 46, "VST2LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 }, // Inst #1333 = VST2LNq16b
- { 1334, 9, 0, 46, "VST2LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 }, // Inst #1334 = VST2LNq32a
- { 1335, 9, 0, 46, "VST2LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 }, // Inst #1335 = VST2LNq32b
- { 1336, 8, 0, 46, "VST2d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 }, // Inst #1336 = VST2d16
- { 1337, 8, 0, 46, "VST2d16D", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 }, // Inst #1337 = VST2d16D
- { 1338, 8, 0, 46, "VST2d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 }, // Inst #1338 = VST2d32
- { 1339, 8, 0, 46, "VST2d32D", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 }, // Inst #1339 = VST2d32D
- { 1340, 8, 0, 46, "VST2d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 }, // Inst #1340 = VST2d64
- { 1341, 8, 0, 46, "VST2d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 }, // Inst #1341 = VST2d8
- { 1342, 8, 0, 46, "VST2d8D", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 }, // Inst #1342 = VST2d8D
- { 1343, 10, 0, 46, "VST2q16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1343 = VST2q16
- { 1344, 10, 0, 46, "VST2q32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1344 = VST2q32
- { 1345, 10, 0, 46, "VST2q8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1345 = VST2q8
- { 1346, 10, 0, 46, "VST3LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 }, // Inst #1346 = VST3LNd16
- { 1347, 10, 0, 46, "VST3LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 }, // Inst #1347 = VST3LNd32
- { 1348, 10, 0, 46, "VST3LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 }, // Inst #1348 = VST3LNd8
- { 1349, 10, 0, 46, "VST3LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 }, // Inst #1349 = VST3LNq16a
- { 1350, 10, 0, 46, "VST3LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 }, // Inst #1350 = VST3LNq16b
- { 1351, 10, 0, 46, "VST3LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 }, // Inst #1351 = VST3LNq32a
- { 1352, 10, 0, 46, "VST3LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 }, // Inst #1352 = VST3LNq32b
- { 1353, 9, 0, 46, "VST3d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 }, // Inst #1353 = VST3d16
- { 1354, 9, 0, 46, "VST3d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 }, // Inst #1354 = VST3d32
- { 1355, 9, 0, 46, "VST3d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 }, // Inst #1355 = VST3d64
- { 1356, 9, 0, 46, "VST3d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 }, // Inst #1356 = VST3d8
- { 1357, 10, 1, 46, "VST3q16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo137 }, // Inst #1357 = VST3q16a
- { 1358, 10, 1, 46, "VST3q16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo137 }, // Inst #1358 = VST3q16b
- { 1359, 10, 1, 46, "VST3q32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo137 }, // Inst #1359 = VST3q32a
- { 1360, 10, 1, 46, "VST3q32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo137 }, // Inst #1360 = VST3q32b
- { 1361, 10, 1, 46, "VST3q8a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo137 }, // Inst #1361 = VST3q8a
- { 1362, 10, 1, 46, "VST3q8b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo137 }, // Inst #1362 = VST3q8b
- { 1363, 11, 0, 46, "VST4LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1363 = VST4LNd16
- { 1364, 11, 0, 46, "VST4LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1364 = VST4LNd32
- { 1365, 11, 0, 46, "VST4LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1365 = VST4LNd8
- { 1366, 11, 0, 46, "VST4LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1366 = VST4LNq16a
- { 1367, 11, 0, 46, "VST4LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1367 = VST4LNq16b
- { 1368, 11, 0, 46, "VST4LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1368 = VST4LNq32a
- { 1369, 11, 0, 46, "VST4LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1369 = VST4LNq32b
- { 1370, 10, 0, 46, "VST4d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1370 = VST4d16
- { 1371, 10, 0, 46, "VST4d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1371 = VST4d32
- { 1372, 10, 0, 46, "VST4d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1372 = VST4d64
- { 1373, 10, 0, 46, "VST4d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1373 = VST4d8
- { 1374, 11, 1, 46, "VST4q16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1374 = VST4q16a
- { 1375, 11, 1, 46, "VST4q16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1375 = VST4q16b
- { 1376, 11, 1, 46, "VST4q32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1376 = VST4q32a
- { 1377, 11, 1, 46, "VST4q32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1377 = VST4q32b
- { 1378, 11, 1, 46, "VST4q8a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1378 = VST4q8a
- { 1379, 11, 1, 46, "VST4q8b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1379 = VST4q8b
- { 1380, 5, 0, 85, "VSTMD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|5|(3<<4)|(21<<9)|(3<<17), NULL, NULL, NULL, OperandInfo35 }, // Inst #1380 = VSTMD
- { 1381, 5, 0, 85, "VSTMS", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|5|(3<<4)|(21<<9)|(1<<17), NULL, NULL, NULL, OperandInfo35 }, // Inst #1381 = VSTMS
- { 1382, 5, 0, 84, "VSTRD", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|5|(3<<4)|(20<<9)|(3<<17), NULL, NULL, NULL, OperandInfo96 }, // Inst #1382 = VSTRD
- { 1383, 5, 0, 85, "VSTRQ", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|4|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo97 }, // Inst #1383 = VSTRQ
- { 1384, 5, 0, 83, "VSTRS", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|5|(3<<4)|(20<<9)|(1<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #1384 = VSTRS
- { 1385, 5, 1, 62, "VSUBD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1385 = VSUBD
- { 1386, 5, 1, 3, "VSUBHNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1386 = VSUBHNv2i32
- { 1387, 5, 1, 3, "VSUBHNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1387 = VSUBHNv4i16
- { 1388, 5, 1, 3, "VSUBHNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1388 = VSUBHNv8i8
- { 1389, 5, 1, 44, "VSUBLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1389 = VSUBLsv2i64
- { 1390, 5, 1, 44, "VSUBLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1390 = VSUBLsv4i32
- { 1391, 5, 1, 44, "VSUBLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1391 = VSUBLsv8i16
- { 1392, 5, 1, 44, "VSUBLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1392 = VSUBLuv2i64
- { 1393, 5, 1, 44, "VSUBLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1393 = VSUBLuv4i32
- { 1394, 5, 1, 44, "VSUBLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1394 = VSUBLuv8i16
- { 1395, 5, 1, 61, "VSUBS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1395 = VSUBS
- { 1396, 5, 1, 47, "VSUBWsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #1396 = VSUBWsv2i64
- { 1397, 5, 1, 47, "VSUBWsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #1397 = VSUBWsv4i32
- { 1398, 5, 1, 47, "VSUBWsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #1398 = VSUBWsv8i16
- { 1399, 5, 1, 47, "VSUBWuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #1399 = VSUBWuv2i64
- { 1400, 5, 1, 47, "VSUBWuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #1400 = VSUBWuv4i32
- { 1401, 5, 1, 47, "VSUBWuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #1401 = VSUBWuv8i16
- { 1402, 5, 1, 1, "VSUBfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1402 = VSUBfd
- { 1403, 5, 1, 1, "VSUBfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #1403 = VSUBfd_sfp
- { 1404, 5, 1, 2, "VSUBfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1404 = VSUBfq
- { 1405, 5, 1, 48, "VSUBv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1405 = VSUBv16i8
- { 1406, 5, 1, 47, "VSUBv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1406 = VSUBv1i64
- { 1407, 5, 1, 47, "VSUBv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1407 = VSUBv2i32
- { 1408, 5, 1, 48, "VSUBv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1408 = VSUBv2i64
- { 1409, 5, 1, 47, "VSUBv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1409 = VSUBv4i16
- { 1410, 5, 1, 48, "VSUBv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1410 = VSUBv4i32
- { 1411, 5, 1, 48, "VSUBv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1411 = VSUBv8i16
- { 1412, 5, 1, 47, "VSUBv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1412 = VSUBv8i8
- { 1413, 4, 1, 128, "VSWPd", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1413 = VSWPd
- { 1414, 4, 1, 128, "VSWPq", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1414 = VSWPq
- { 1415, 5, 1, 49, "VTBL1", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1415 = VTBL1
- { 1416, 6, 1, 50, "VTBL2", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo140 }, // Inst #1416 = VTBL2
- { 1417, 7, 1, 51, "VTBL3", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo141 }, // Inst #1417 = VTBL3
- { 1418, 8, 1, 52, "VTBL4", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo142 }, // Inst #1418 = VTBL4
- { 1419, 6, 1, 53, "VTBX1", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1419 = VTBX1
- { 1420, 7, 1, 54, "VTBX2", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo143 }, // Inst #1420 = VTBX2
- { 1421, 8, 1, 55, "VTBX3", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo144 }, // Inst #1421 = VTBX3
- { 1422, 9, 1, 56, "VTBX4", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo145 }, // Inst #1422 = VTBX4
- { 1423, 5, 1, 65, "VTOSHD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1423 = VTOSHD
- { 1424, 5, 1, 70, "VTOSHS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1424 = VTOSHS
- { 1425, 4, 1, 65, "VTOSIRD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #1425 = VTOSIRD
- { 1426, 4, 1, 70, "VTOSIRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #1426 = VTOSIRS
- { 1427, 4, 1, 65, "VTOSIZD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #1427 = VTOSIZD
- { 1428, 4, 1, 70, "VTOSIZS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #1428 = VTOSIZS
- { 1429, 5, 1, 65, "VTOSLD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1429 = VTOSLD
- { 1430, 5, 1, 70, "VTOSLS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1430 = VTOSLS
- { 1431, 5, 1, 65, "VTOUHD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1431 = VTOUHD
- { 1432, 5, 1, 70, "VTOUHS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1432 = VTOUHS
- { 1433, 4, 1, 65, "VTOUIRD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #1433 = VTOUIRD
- { 1434, 4, 1, 70, "VTOUIRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #1434 = VTOUIRS
- { 1435, 4, 1, 65, "VTOUIZD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #1435 = VTOUIZD
- { 1436, 4, 1, 70, "VTOUIZS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #1436 = VTOUIZS
- { 1437, 5, 1, 65, "VTOULD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1437 = VTOULD
- { 1438, 5, 1, 70, "VTOULS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1438 = VTOULS
- { 1439, 6, 2, 35, "VTRNd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 }, // Inst #1439 = VTRNd16
- { 1440, 6, 2, 35, "VTRNd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 }, // Inst #1440 = VTRNd32
- { 1441, 6, 2, 35, "VTRNd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 }, // Inst #1441 = VTRNd8
- { 1442, 6, 2, 36, "VTRNq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 }, // Inst #1442 = VTRNq16
- { 1443, 6, 2, 36, "VTRNq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 }, // Inst #1443 = VTRNq32
- { 1444, 6, 2, 36, "VTRNq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 }, // Inst #1444 = VTRNq8
- { 1445, 5, 1, 4, "VTSTv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1445 = VTSTv16i8
- { 1446, 5, 1, 3, "VTSTv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1446 = VTSTv2i32
- { 1447, 5, 1, 3, "VTSTv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1447 = VTSTv4i16
- { 1448, 5, 1, 4, "VTSTv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1448 = VTSTv4i32
- { 1449, 5, 1, 4, "VTSTv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1449 = VTSTv8i16
- { 1450, 5, 1, 3, "VTSTv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1450 = VTSTv8i8
- { 1451, 5, 1, 67, "VUHTOD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1451 = VUHTOD
- { 1452, 5, 1, 68, "VUHTOS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1452 = VUHTOS
- { 1453, 4, 1, 67, "VUITOD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #1453 = VUITOD
- { 1454, 4, 1, 68, "VUITOS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #1454 = VUITOS
- { 1455, 5, 1, 67, "VULTOD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1455 = VULTOD
- { 1456, 5, 1, 68, "VULTOS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1456 = VULTOS
- { 1457, 6, 2, 35, "VUZPd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 }, // Inst #1457 = VUZPd16
- { 1458, 6, 2, 35, "VUZPd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 }, // Inst #1458 = VUZPd32
- { 1459, 6, 2, 35, "VUZPd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 }, // Inst #1459 = VUZPd8
- { 1460, 6, 2, 37, "VUZPq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 }, // Inst #1460 = VUZPq16
- { 1461, 6, 2, 37, "VUZPq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 }, // Inst #1461 = VUZPq32
- { 1462, 6, 2, 37, "VUZPq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 }, // Inst #1462 = VUZPq8
- { 1463, 6, 2, 35, "VZIPd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 }, // Inst #1463 = VZIPd16
- { 1464, 6, 2, 35, "VZIPd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 }, // Inst #1464 = VZIPd32
- { 1465, 6, 2, 35, "VZIPd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 }, // Inst #1465 = VZIPd8
- { 1466, 6, 2, 37, "VZIPq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 }, // Inst #1466 = VZIPq16
- { 1467, 6, 2, 37, "VZIPq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 }, // Inst #1467 = VZIPq32
- { 1468, 6, 2, 37, "VZIPq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 }, // Inst #1468 = VZIPq8
- { 1469, 2, 0, 128, "WFE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1469 = WFE
- { 1470, 2, 0, 128, "WFI", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1470 = WFI
- { 1471, 2, 0, 128, "YIELD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1471 = YIELD
- { 1472, 6, 1, 88, "t2ADCSri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1472 = t2ADCSri
- { 1473, 6, 1, 89, "t2ADCSrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1473 = t2ADCSrr
- { 1474, 7, 1, 90, "t2ADCSrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #1474 = t2ADCSrs
- { 1475, 6, 1, 88, "t2ADCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #1475 = t2ADCri
- { 1476, 6, 1, 89, "t2ADCrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #1476 = t2ADCrr
- { 1477, 7, 1, 90, "t2ADCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo48 }, // Inst #1477 = t2ADCrs
- { 1478, 5, 1, 88, "t2ADDSri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1478 = t2ADDSri
- { 1479, 5, 1, 89, "t2ADDSrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1479 = t2ADDSrr
- { 1480, 6, 1, 90, "t2ADDSrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo27 }, // Inst #1480 = t2ADDSrs
- { 1481, 6, 1, 88, "t2ADDrSPi", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1481 = t2ADDrSPi
- { 1482, 5, 1, 88, "t2ADDrSPi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1482 = t2ADDrSPi12
- { 1483, 7, 1, 90, "t2ADDrSPs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1483 = t2ADDrSPs
- { 1484, 6, 1, 88, "t2ADDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1484 = t2ADDri
- { 1485, 6, 1, 88, "t2ADDri12", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1485 = t2ADDri12
- { 1486, 6, 1, 89, "t2ADDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1486 = t2ADDrr
- { 1487, 7, 1, 90, "t2ADDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1487 = t2ADDrs
- { 1488, 6, 1, 88, "t2ANDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1488 = t2ANDri
- { 1489, 6, 1, 89, "t2ANDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1489 = t2ANDrr
- { 1490, 7, 1, 90, "t2ANDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1490 = t2ANDrs
- { 1491, 6, 1, 113, "t2ASRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1491 = t2ASRri
- { 1492, 6, 1, 114, "t2ASRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1492 = t2ASRrr
- { 1493, 1, 0, 0, "t2B", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1493 = t2B
- { 1494, 5, 1, 126, "t2BFC", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1494 = t2BFC
- { 1495, 6, 1, 88, "t2BFI", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo51 }, // Inst #1495 = t2BFI
- { 1496, 6, 1, 88, "t2BICri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1496 = t2BICri
- { 1497, 6, 1, 89, "t2BICrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1497 = t2BICrr
- { 1498, 7, 1, 90, "t2BICrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1498 = t2BICrs
- { 1499, 4, 0, 0, "t2BR_JT", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo17 }, // Inst #1499 = t2BR_JT
- { 1500, 3, 0, 128, "t2BXJ", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1500 = t2BXJ
- { 1501, 3, 0, 0, "t2Bcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1501 = t2Bcc
- { 1502, 2, 0, 128, "t2CLREX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1502 = t2CLREX
- { 1503, 4, 1, 125, "t2CLZ", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1503 = t2CLZ
- { 1504, 4, 0, 97, "t2CMNzri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #1504 = t2CMNzri
- { 1505, 4, 0, 98, "t2CMNzrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1505 = t2CMNzrr
- { 1506, 5, 0, 99, "t2CMNzrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1506 = t2CMNzrs
- { 1507, 4, 0, 97, "t2CMPri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #1507 = t2CMPri
- { 1508, 4, 0, 98, "t2CMPrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1508 = t2CMPrr
- { 1509, 5, 0, 99, "t2CMPrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1509 = t2CMPrs
- { 1510, 4, 0, 97, "t2CMPzri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #1510 = t2CMPzri
- { 1511, 4, 0, 98, "t2CMPzrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1511 = t2CMPzrr
- { 1512, 5, 0, 99, "t2CMPzrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1512 = t2CMPzrs
- { 1513, 1, 0, 128, "t2CPS", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1513 = t2CPS
- { 1514, 3, 0, 128, "t2DBG", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1514 = t2DBG
- { 1515, 2, 0, 128, "t2DMBish", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1515 = t2DMBish
- { 1516, 2, 0, 128, "t2DMBishst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1516 = t2DMBishst
- { 1517, 2, 0, 128, "t2DMBnsh", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1517 = t2DMBnsh
- { 1518, 2, 0, 128, "t2DMBnshst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1518 = t2DMBnshst
- { 1519, 2, 0, 128, "t2DMBosh", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1519 = t2DMBosh
- { 1520, 2, 0, 128, "t2DMBoshst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1520 = t2DMBoshst
- { 1521, 2, 0, 128, "t2DMBst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1521 = t2DMBst
- { 1522, 2, 0, 128, "t2DSBish", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1522 = t2DSBish
- { 1523, 2, 0, 128, "t2DSBishst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1523 = t2DSBishst
- { 1524, 2, 0, 128, "t2DSBnsh", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1524 = t2DSBnsh
- { 1525, 2, 0, 128, "t2DSBnshst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1525 = t2DSBnshst
- { 1526, 2, 0, 128, "t2DSBosh", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1526 = t2DSBosh
- { 1527, 2, 0, 128, "t2DSBoshst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1527 = t2DSBoshst
- { 1528, 2, 0, 128, "t2DSBst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1528 = t2DSBst
- { 1529, 6, 1, 88, "t2EORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1529 = t2EORri
- { 1530, 6, 1, 89, "t2EORrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1530 = t2EORrr
- { 1531, 7, 1, 90, "t2EORrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1531 = t2EORrs
- { 1532, 2, 0, 128, "t2ISBsy", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1532 = t2ISBsy
- { 1533, 2, 0, 92, "t2IT", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1533 = t2IT
- { 1534, 0, 0, 128, "t2Int_MemBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #1534 = t2Int_MemBarrierV7
- { 1535, 0, 0, 128, "t2Int_SyncBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #1535 = t2Int_SyncBarrierV7
- { 1536, 2, 0, 128, "t2Int_eh_sjlj_setjmp", 0, 0|(1<<4)|(23<<9), NULL, ImplicitList6, Barriers3, OperandInfo149 }, // Inst #1536 = t2Int_eh_sjlj_setjmp
- { 1537, 5, 0, 103, "t2LDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #1537 = t2LDM
- { 1538, 5, 0, 0, "t2LDM_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #1538 = t2LDM_RET
- { 1539, 5, 1, 101, "t2LDRBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1539 = t2LDRBT
- { 1540, 6, 2, 102, "t2LDRB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1540 = t2LDRB_POST
- { 1541, 6, 2, 102, "t2LDRB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1541 = t2LDRB_PRE
- { 1542, 5, 1, 101, "t2LDRBi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1542 = t2LDRBi12
- { 1543, 5, 1, 101, "t2LDRBi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1543 = t2LDRBi8
- { 1544, 4, 1, 101, "t2LDRBpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1544 = t2LDRBpci
- { 1545, 6, 1, 104, "t2LDRBs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1545 = t2LDRBs
- { 1546, 6, 2, 101, "t2LDRDi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1546 = t2LDRDi8
- { 1547, 5, 2, 101, "t2LDRDpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1547 = t2LDRDpci
- { 1548, 4, 1, 128, "t2LDREX", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1548 = t2LDREX
- { 1549, 4, 1, 128, "t2LDREXB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1549 = t2LDREXB
- { 1550, 5, 2, 128, "t2LDREXD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1550 = t2LDREXD
- { 1551, 4, 1, 128, "t2LDREXH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1551 = t2LDREXH
- { 1552, 5, 1, 101, "t2LDRHT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1552 = t2LDRHT
- { 1553, 6, 2, 102, "t2LDRH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1553 = t2LDRH_POST
- { 1554, 6, 2, 102, "t2LDRH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1554 = t2LDRH_PRE
- { 1555, 5, 1, 101, "t2LDRHi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1555 = t2LDRHi12
- { 1556, 5, 1, 101, "t2LDRHi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1556 = t2LDRHi8
- { 1557, 4, 1, 101, "t2LDRHpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1557 = t2LDRHpci
- { 1558, 6, 1, 104, "t2LDRHs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1558 = t2LDRHs
- { 1559, 5, 1, 101, "t2LDRSBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1559 = t2LDRSBT
- { 1560, 6, 2, 102, "t2LDRSB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1560 = t2LDRSB_POST
- { 1561, 6, 2, 102, "t2LDRSB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1561 = t2LDRSB_PRE
- { 1562, 5, 1, 101, "t2LDRSBi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1562 = t2LDRSBi12
- { 1563, 5, 1, 101, "t2LDRSBi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1563 = t2LDRSBi8
- { 1564, 4, 1, 101, "t2LDRSBpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1564 = t2LDRSBpci
- { 1565, 6, 1, 104, "t2LDRSBs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1565 = t2LDRSBs
- { 1566, 5, 1, 101, "t2LDRSHT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1566 = t2LDRSHT
- { 1567, 6, 2, 102, "t2LDRSH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1567 = t2LDRSH_POST
- { 1568, 6, 2, 102, "t2LDRSH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1568 = t2LDRSH_PRE
- { 1569, 5, 1, 101, "t2LDRSHi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1569 = t2LDRSHi12
- { 1570, 5, 1, 101, "t2LDRSHi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1570 = t2LDRSHi8
- { 1571, 4, 1, 101, "t2LDRSHpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1571 = t2LDRSHpci
- { 1572, 6, 1, 104, "t2LDRSHs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1572 = t2LDRSHs
- { 1573, 5, 1, 101, "t2LDRT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1573 = t2LDRT
- { 1574, 6, 2, 102, "t2LDR_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1574 = t2LDR_POST
- { 1575, 6, 2, 102, "t2LDR_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1575 = t2LDR_PRE
- { 1576, 5, 1, 101, "t2LDRi12", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1576 = t2LDRi12
- { 1577, 5, 1, 101, "t2LDRi8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1577 = t2LDRi8
- { 1578, 4, 1, 101, "t2LDRpci", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1578 = t2LDRpci
- { 1579, 3, 1, 128, "t2LDRpci_pic", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|(1<<4), NULL, NULL, NULL, OperandInfo19 }, // Inst #1579 = t2LDRpci_pic
- { 1580, 6, 1, 104, "t2LDRs", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1580 = t2LDRs
- { 1581, 4, 1, 88, "t2LEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1581 = t2LEApcrel
- { 1582, 5, 1, 88, "t2LEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo38 }, // Inst #1582 = t2LEApcrelJT
- { 1583, 6, 1, 113, "t2LSLri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1583 = t2LSLri
- { 1584, 6, 1, 114, "t2LSLrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1584 = t2LSLrr
- { 1585, 6, 1, 113, "t2LSRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1585 = t2LSRri
- { 1586, 6, 1, 114, "t2LSRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1586 = t2LSRrr
- { 1587, 6, 1, 109, "t2MLA", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1587 = t2MLA
- { 1588, 6, 1, 109, "t2MLS", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1588 = t2MLS
- { 1589, 6, 1, 95, "t2MOVCCasr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1589 = t2MOVCCasr
- { 1590, 5, 1, 93, "t2MOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1590 = t2MOVCCi
- { 1591, 6, 1, 95, "t2MOVCClsl", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1591 = t2MOVCClsl
- { 1592, 6, 1, 95, "t2MOVCClsr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1592 = t2MOVCClsr
- { 1593, 5, 1, 94, "t2MOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo44 }, // Inst #1593 = t2MOVCCr
- { 1594, 6, 1, 95, "t2MOVCCror", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1594 = t2MOVCCror
- { 1595, 5, 1, 111, "t2MOVTi16", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1595 = t2MOVTi16
- { 1596, 5, 1, 111, "t2MOVi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo46 }, // Inst #1596 = t2MOVi
- { 1597, 4, 1, 111, "t2MOVi16", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1597 = t2MOVi16
- { 1598, 4, 1, 111, "t2MOVi32imm", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(2<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1598 = t2MOVi32imm
- { 1599, 5, 1, 112, "t2MOVr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo47 }, // Inst #1599 = t2MOVr
- { 1600, 5, 1, 113, "t2MOVrx", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo47 }, // Inst #1600 = t2MOVrx
- { 1601, 2, 1, 113, "t2MOVsra_flag", 0, 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo32 }, // Inst #1601 = t2MOVsra_flag
- { 1602, 2, 1, 113, "t2MOVsrl_flag", 0, 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo32 }, // Inst #1602 = t2MOVsrl_flag
- { 1603, 3, 1, 128, "t2MRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1603 = t2MRS
- { 1604, 3, 1, 128, "t2MRSsys", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1604 = t2MRSsys
- { 1605, 3, 0, 128, "t2MSR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1605 = t2MSR
- { 1606, 3, 0, 128, "t2MSRsys", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1606 = t2MSRsys
- { 1607, 5, 1, 116, "t2MUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1607 = t2MUL
- { 1608, 5, 1, 111, "t2MVNi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo46 }, // Inst #1608 = t2MVNi
- { 1609, 4, 1, 112, "t2MVNr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1609 = t2MVNr
- { 1610, 5, 1, 113, "t2MVNs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1610 = t2MVNs
- { 1611, 2, 0, 128, "t2NOP", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1611 = t2NOP
- { 1612, 6, 1, 88, "t2ORNri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1612 = t2ORNri
- { 1613, 6, 1, 89, "t2ORNrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1613 = t2ORNrr
- { 1614, 7, 1, 90, "t2ORNrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1614 = t2ORNrs
- { 1615, 6, 1, 88, "t2ORRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1615 = t2ORRri
- { 1616, 6, 1, 89, "t2ORRrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1616 = t2ORRrr
- { 1617, 7, 1, 90, "t2ORRrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1617 = t2ORRrs
- { 1618, 6, 1, 90, "t2PKHBT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1618 = t2PKHBT
- { 1619, 6, 1, 90, "t2PKHTB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1619 = t2PKHTB
- { 1620, 4, 0, 101, "t2PLDWi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1620 = t2PLDWi12
- { 1621, 4, 0, 101, "t2PLDWi8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1621 = t2PLDWi8
- { 1622, 4, 0, 101, "t2PLDWpci", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1622 = t2PLDWpci
- { 1623, 4, 0, 101, "t2PLDWr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1623 = t2PLDWr
- { 1624, 5, 0, 101, "t2PLDWs", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1624 = t2PLDWs
- { 1625, 4, 0, 101, "t2PLDi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1625 = t2PLDi12
- { 1626, 4, 0, 101, "t2PLDi8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1626 = t2PLDi8
- { 1627, 4, 0, 101, "t2PLDpci", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1627 = t2PLDpci
- { 1628, 4, 0, 101, "t2PLDr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1628 = t2PLDr
- { 1629, 5, 0, 101, "t2PLDs", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1629 = t2PLDs
- { 1630, 4, 0, 101, "t2PLIi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1630 = t2PLIi12
- { 1631, 4, 0, 101, "t2PLIi8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1631 = t2PLIi8
- { 1632, 4, 0, 101, "t2PLIpci", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1632 = t2PLIpci
- { 1633, 4, 0, 101, "t2PLIr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1633 = t2PLIr
- { 1634, 5, 0, 101, "t2PLIs", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1634 = t2PLIs
- { 1635, 5, 1, 128, "t2QADD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1635 = t2QADD
- { 1636, 5, 1, 128, "t2QADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1636 = t2QADD16
- { 1637, 5, 1, 128, "t2QADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1637 = t2QADD8
- { 1638, 5, 1, 128, "t2QASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1638 = t2QASX
- { 1639, 5, 1, 128, "t2QDADD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1639 = t2QDADD
- { 1640, 5, 1, 128, "t2QDSUB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1640 = t2QDSUB
- { 1641, 5, 1, 128, "t2QSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1641 = t2QSAX
- { 1642, 5, 1, 128, "t2QSUB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1642 = t2QSUB
- { 1643, 5, 1, 128, "t2QSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1643 = t2QSUB16
- { 1644, 5, 1, 128, "t2QSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1644 = t2QSUB8
- { 1645, 4, 1, 125, "t2RBIT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1645 = t2RBIT
- { 1646, 4, 1, 125, "t2REV", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1646 = t2REV
- { 1647, 4, 1, 125, "t2REV16", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1647 = t2REV16
- { 1648, 4, 1, 125, "t2REVSH", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1648 = t2REVSH
- { 1649, 3, 0, 128, "t2RFEDB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1649 = t2RFEDB
- { 1650, 3, 0, 128, "t2RFEDBW", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1650 = t2RFEDBW
- { 1651, 3, 0, 128, "t2RFEIA", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1651 = t2RFEIA
- { 1652, 3, 0, 128, "t2RFEIAW", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1652 = t2RFEIAW
- { 1653, 6, 1, 113, "t2RORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1653 = t2RORri
- { 1654, 6, 1, 114, "t2RORrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1654 = t2RORrr
- { 1655, 4, 1, 88, "t2RSBSri", 0|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo152 }, // Inst #1655 = t2RSBSri
- { 1656, 5, 1, 90, "t2RSBSrs", 0|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo153 }, // Inst #1656 = t2RSBSrs
- { 1657, 5, 1, 88, "t2RSBri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1657 = t2RSBri
- { 1658, 6, 1, 90, "t2RSBrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1658 = t2RSBrs
- { 1659, 5, 1, 128, "t2SADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1659 = t2SADD16
- { 1660, 5, 1, 128, "t2SADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1660 = t2SADD8
- { 1661, 5, 1, 128, "t2SASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1661 = t2SASX
- { 1662, 6, 1, 88, "t2SBCSri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1662 = t2SBCSri
- { 1663, 6, 1, 89, "t2SBCSrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1663 = t2SBCSrr
- { 1664, 7, 1, 90, "t2SBCSrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #1664 = t2SBCSrs
- { 1665, 6, 1, 88, "t2SBCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #1665 = t2SBCri
- { 1666, 6, 1, 89, "t2SBCrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #1666 = t2SBCrr
- { 1667, 7, 1, 90, "t2SBCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo48 }, // Inst #1667 = t2SBCrs
- { 1668, 6, 1, 88, "t2SBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo51 }, // Inst #1668 = t2SBFX
- { 1669, 5, 1, 88, "t2SDIV", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1669 = t2SDIV
- { 1670, 5, 1, 128, "t2SEL", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1670 = t2SEL
- { 1671, 2, 0, 128, "t2SEV", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1671 = t2SEV
- { 1672, 5, 1, 128, "t2SHADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1672 = t2SHADD16
- { 1673, 5, 1, 128, "t2SHADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1673 = t2SHADD8
- { 1674, 5, 1, 128, "t2SHASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1674 = t2SHASX
- { 1675, 5, 1, 128, "t2SHSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1675 = t2SHSAX
- { 1676, 5, 1, 128, "t2SHSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1676 = t2SHSUB16
- { 1677, 5, 1, 128, "t2SHSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1677 = t2SHSUB8
- { 1678, 3, 0, 128, "t2SMC", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1678 = t2SMC
- { 1679, 6, 1, 108, "t2SMLABB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1679 = t2SMLABB
- { 1680, 6, 1, 108, "t2SMLABT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1680 = t2SMLABT
- { 1681, 6, 1, 109, "t2SMLAD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1681 = t2SMLAD
- { 1682, 6, 1, 109, "t2SMLADX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1682 = t2SMLADX
- { 1683, 6, 2, 110, "t2SMLAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1683 = t2SMLAL
- { 1684, 6, 2, 110, "t2SMLALBB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1684 = t2SMLALBB
- { 1685, 6, 2, 110, "t2SMLALBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1685 = t2SMLALBT
- { 1686, 6, 2, 110, "t2SMLALD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1686 = t2SMLALD
- { 1687, 6, 2, 110, "t2SMLALDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1687 = t2SMLALDX
- { 1688, 6, 2, 110, "t2SMLALTB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1688 = t2SMLALTB
- { 1689, 6, 2, 110, "t2SMLALTT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1689 = t2SMLALTT
- { 1690, 6, 1, 108, "t2SMLATB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1690 = t2SMLATB
- { 1691, 6, 1, 108, "t2SMLATT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1691 = t2SMLATT
- { 1692, 6, 1, 108, "t2SMLAWB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1692 = t2SMLAWB
- { 1693, 6, 1, 108, "t2SMLAWT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1693 = t2SMLAWT
- { 1694, 6, 1, 109, "t2SMLSD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1694 = t2SMLSD
- { 1695, 6, 1, 109, "t2SMLSDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1695 = t2SMLSDX
- { 1696, 6, 2, 110, "t2SMLSLD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1696 = t2SMLSLD
- { 1697, 6, 2, 110, "t2SMLSLDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1697 = t2SMLSLDX
- { 1698, 6, 1, 109, "t2SMMLA", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1698 = t2SMMLA
- { 1699, 6, 1, 109, "t2SMMLAR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1699 = t2SMMLAR
- { 1700, 6, 1, 109, "t2SMMLS", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1700 = t2SMMLS
- { 1701, 6, 1, 109, "t2SMMLSR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1701 = t2SMMLSR
- { 1702, 5, 1, 116, "t2SMMUL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1702 = t2SMMUL
- { 1703, 5, 1, 116, "t2SMMULR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1703 = t2SMMULR
- { 1704, 5, 1, 109, "t2SMUAD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1704 = t2SMUAD
- { 1705, 5, 1, 109, "t2SMUADX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1705 = t2SMUADX
- { 1706, 5, 1, 116, "t2SMULBB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1706 = t2SMULBB
- { 1707, 5, 1, 116, "t2SMULBT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1707 = t2SMULBT
- { 1708, 6, 2, 117, "t2SMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1708 = t2SMULL
- { 1709, 5, 1, 116, "t2SMULTB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1709 = t2SMULTB
- { 1710, 5, 1, 116, "t2SMULTT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1710 = t2SMULTT
- { 1711, 5, 1, 115, "t2SMULWB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1711 = t2SMULWB
- { 1712, 5, 1, 115, "t2SMULWT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1712 = t2SMULWT
- { 1713, 5, 1, 109, "t2SMUSD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1713 = t2SMUSD
- { 1714, 5, 1, 109, "t2SMUSDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1714 = t2SMUSDX
- { 1715, 3, 0, 128, "t2SRSDB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1715 = t2SRSDB
- { 1716, 3, 0, 128, "t2SRSDBW", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1716 = t2SRSDBW
- { 1717, 3, 0, 128, "t2SRSIA", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1717 = t2SRSIA
- { 1718, 3, 0, 128, "t2SRSIAW", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1718 = t2SRSIAW
- { 1719, 5, 1, 128, "t2SSAT16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo52 }, // Inst #1719 = t2SSAT16
- { 1720, 6, 1, 128, "t2SSATasr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo53 }, // Inst #1720 = t2SSATasr
- { 1721, 6, 1, 128, "t2SSATlsl", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo53 }, // Inst #1721 = t2SSATlsl
- { 1722, 5, 1, 128, "t2SSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1722 = t2SSAX
- { 1723, 5, 1, 128, "t2SSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1723 = t2SSUB16
- { 1724, 5, 1, 128, "t2SSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1724 = t2SSUB8
- { 1725, 5, 0, 120, "t2STM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #1725 = t2STM
- { 1726, 5, 1, 118, "t2STRBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1726 = t2STRBT
- { 1727, 6, 1, 119, "t2STRB_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo154 }, // Inst #1727 = t2STRB_POST
- { 1728, 6, 1, 119, "t2STRB_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo154 }, // Inst #1728 = t2STRB_PRE
- { 1729, 5, 0, 118, "t2STRBi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1729 = t2STRBi12
- { 1730, 5, 0, 118, "t2STRBi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1730 = t2STRBi8
- { 1731, 6, 0, 121, "t2STRBs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1731 = t2STRBs
- { 1732, 6, 0, 121, "t2STRDi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1732 = t2STRDi8
- { 1733, 5, 1, 128, "t2STREX", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo56 }, // Inst #1733 = t2STREX
- { 1734, 5, 1, 128, "t2STREXB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo56 }, // Inst #1734 = t2STREXB
- { 1735, 6, 1, 128, "t2STREXD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo57 }, // Inst #1735 = t2STREXD
- { 1736, 5, 1, 128, "t2STREXH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo56 }, // Inst #1736 = t2STREXH
- { 1737, 5, 1, 118, "t2STRHT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1737 = t2STRHT
- { 1738, 6, 1, 119, "t2STRH_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo154 }, // Inst #1738 = t2STRH_POST
- { 1739, 6, 1, 119, "t2STRH_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo154 }, // Inst #1739 = t2STRH_PRE
- { 1740, 5, 0, 118, "t2STRHi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1740 = t2STRHi12
- { 1741, 5, 0, 118, "t2STRHi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1741 = t2STRHi8
- { 1742, 6, 0, 121, "t2STRHs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1742 = t2STRHs
- { 1743, 5, 1, 118, "t2STRT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1743 = t2STRT
- { 1744, 6, 1, 119, "t2STR_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo154 }, // Inst #1744 = t2STR_POST
- { 1745, 6, 1, 119, "t2STR_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo154 }, // Inst #1745 = t2STR_PRE
- { 1746, 5, 0, 118, "t2STRi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1746 = t2STRi12
- { 1747, 5, 0, 118, "t2STRi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1747 = t2STRi8
- { 1748, 6, 0, 121, "t2STRs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1748 = t2STRs
- { 1749, 5, 1, 88, "t2SUBSri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1749 = t2SUBSri
- { 1750, 5, 1, 89, "t2SUBSrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1750 = t2SUBSrr
- { 1751, 6, 1, 90, "t2SUBSrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo27 }, // Inst #1751 = t2SUBSrs
- { 1752, 6, 1, 88, "t2SUBrSPi", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1752 = t2SUBrSPi
- { 1753, 5, 1, 88, "t2SUBrSPi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1753 = t2SUBrSPi12
- { 1754, 3, 1, 128, "t2SUBrSPi12_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1754 = t2SUBrSPi12_
- { 1755, 3, 1, 128, "t2SUBrSPi_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1755 = t2SUBrSPi_
- { 1756, 7, 1, 90, "t2SUBrSPs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1756 = t2SUBrSPs
- { 1757, 4, 1, 128, "t2SUBrSPs_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo155 }, // Inst #1757 = t2SUBrSPs_
- { 1758, 6, 1, 88, "t2SUBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1758 = t2SUBri
- { 1759, 6, 1, 88, "t2SUBri12", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1759 = t2SUBri12
- { 1760, 6, 1, 89, "t2SUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1760 = t2SUBrr
- { 1761, 7, 1, 90, "t2SUBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1761 = t2SUBrs
- { 1762, 5, 1, 89, "t2SXTAB16rr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1762 = t2SXTAB16rr
- { 1763, 6, 1, 91, "t2SXTAB16rr_rot", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1763 = t2SXTAB16rr_rot
- { 1764, 5, 1, 89, "t2SXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1764 = t2SXTABrr
- { 1765, 6, 1, 91, "t2SXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1765 = t2SXTABrr_rot
- { 1766, 5, 1, 89, "t2SXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1766 = t2SXTAHrr
- { 1767, 6, 1, 91, "t2SXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1767 = t2SXTAHrr_rot
- { 1768, 4, 1, 125, "t2SXTB16r", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1768 = t2SXTB16r
- { 1769, 5, 1, 126, "t2SXTB16r_rot", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1769 = t2SXTB16r_rot
- { 1770, 4, 1, 125, "t2SXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1770 = t2SXTBr
- { 1771, 5, 1, 126, "t2SXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1771 = t2SXTBr_rot
- { 1772, 4, 1, 125, "t2SXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1772 = t2SXTHr
- { 1773, 5, 1, 126, "t2SXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1773 = t2SXTHr_rot
- { 1774, 3, 0, 0, "t2TBB", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1774 = t2TBB
- { 1775, 4, 0, 0, "t2TBBgen", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1775 = t2TBBgen
- { 1776, 3, 0, 0, "t2TBH", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1776 = t2TBH
- { 1777, 4, 0, 0, "t2TBHgen", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1777 = t2TBHgen
- { 1778, 4, 0, 97, "t2TEQri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #1778 = t2TEQri
- { 1779, 4, 0, 98, "t2TEQrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1779 = t2TEQrr
- { 1780, 5, 0, 99, "t2TEQrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1780 = t2TEQrs
- { 1781, 0, 0, 0, "t2TPsoft", 0|(1<<TID::Call), 0|(3<<4)|(23<<9), NULL, ImplicitList7, Barriers1, 0 }, // Inst #1781 = t2TPsoft
- { 1782, 4, 0, 97, "t2TSTri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #1782 = t2TSTri
- { 1783, 4, 0, 98, "t2TSTrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1783 = t2TSTrr
- { 1784, 5, 0, 99, "t2TSTrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1784 = t2TSTrs
- { 1785, 5, 1, 128, "t2UADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1785 = t2UADD16
- { 1786, 5, 1, 128, "t2UADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1786 = t2UADD8
- { 1787, 5, 1, 128, "t2UASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1787 = t2UASX
- { 1788, 6, 1, 88, "t2UBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo51 }, // Inst #1788 = t2UBFX
- { 1789, 5, 1, 88, "t2UDIV", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1789 = t2UDIV
- { 1790, 5, 1, 128, "t2UHADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1790 = t2UHADD16
- { 1791, 5, 1, 128, "t2UHADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1791 = t2UHADD8
- { 1792, 5, 1, 128, "t2UHASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1792 = t2UHASX
- { 1793, 5, 1, 128, "t2UHSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1793 = t2UHSAX
- { 1794, 5, 1, 128, "t2UHSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1794 = t2UHSUB16
- { 1795, 5, 1, 128, "t2UHSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1795 = t2UHSUB8
- { 1796, 6, 2, 110, "t2UMAAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1796 = t2UMAAL
- { 1797, 6, 2, 110, "t2UMLAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1797 = t2UMLAL
- { 1798, 6, 2, 117, "t2UMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1798 = t2UMULL
- { 1799, 5, 1, 128, "t2UQADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1799 = t2UQADD16
- { 1800, 5, 1, 128, "t2UQADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1800 = t2UQADD8
- { 1801, 5, 1, 128, "t2UQASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1801 = t2UQASX
- { 1802, 5, 1, 128, "t2UQSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1802 = t2UQSAX
- { 1803, 5, 1, 128, "t2UQSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1803 = t2UQSUB16
- { 1804, 5, 1, 128, "t2UQSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1804 = t2UQSUB8
- { 1805, 5, 1, 128, "t2USAD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1805 = t2USAD8
- { 1806, 6, 1, 128, "t2USADA8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1806 = t2USADA8
- { 1807, 5, 1, 128, "t2USAT16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo52 }, // Inst #1807 = t2USAT16
- { 1808, 6, 1, 128, "t2USATasr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo53 }, // Inst #1808 = t2USATasr
- { 1809, 6, 1, 128, "t2USATlsl", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo53 }, // Inst #1809 = t2USATlsl
- { 1810, 5, 1, 128, "t2USAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1810 = t2USAX
- { 1811, 5, 1, 128, "t2USUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1811 = t2USUB16
- { 1812, 5, 1, 128, "t2USUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1812 = t2USUB8
- { 1813, 5, 1, 89, "t2UXTAB16rr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1813 = t2UXTAB16rr
- { 1814, 6, 1, 91, "t2UXTAB16rr_rot", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1814 = t2UXTAB16rr_rot
- { 1815, 5, 1, 89, "t2UXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1815 = t2UXTABrr
- { 1816, 6, 1, 91, "t2UXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1816 = t2UXTABrr_rot
- { 1817, 5, 1, 89, "t2UXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1817 = t2UXTAHrr
- { 1818, 6, 1, 91, "t2UXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1818 = t2UXTAHrr_rot
- { 1819, 4, 1, 125, "t2UXTB16r", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1819 = t2UXTB16r
- { 1820, 5, 1, 126, "t2UXTB16r_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1820 = t2UXTB16r_rot
- { 1821, 4, 1, 125, "t2UXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1821 = t2UXTBr
- { 1822, 5, 1, 126, "t2UXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1822 = t2UXTBr_rot
- { 1823, 4, 1, 125, "t2UXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1823 = t2UXTHr
- { 1824, 5, 1, 126, "t2UXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1824 = t2UXTHr_rot
- { 1825, 2, 0, 128, "t2WFE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1825 = t2WFE
- { 1826, 2, 0, 128, "t2WFI", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1826 = t2WFI
- { 1827, 2, 0, 128, "t2YIELD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1827 = t2YIELD
- { 1828, 6, 2, 89, "tADC", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo156 }, // Inst #1828 = tADC
- { 1829, 5, 1, 89, "tADDhirr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo44 }, // Inst #1829 = tADDhirr
- { 1830, 6, 2, 88, "tADDi3", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 }, // Inst #1830 = tADDi3
- { 1831, 6, 2, 88, "tADDi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo158 }, // Inst #1831 = tADDi8
- { 1832, 2, 1, 88, "tADDrPCi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo159 }, // Inst #1832 = tADDrPCi
- { 1833, 3, 1, 89, "tADDrSP", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo160 }, // Inst #1833 = tADDrSP
- { 1834, 3, 1, 88, "tADDrSPi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo161 }, // Inst #1834 = tADDrSPi
- { 1835, 6, 2, 89, "tADDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1835 = tADDrr
- { 1836, 3, 1, 88, "tADDspi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo163 }, // Inst #1836 = tADDspi
- { 1837, 3, 1, 89, "tADDspr", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo160 }, // Inst #1837 = tADDspr
- { 1838, 3, 1, 128, "tADDspr_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo3 }, // Inst #1838 = tADDspr_
- { 1839, 1, 0, 128, "tADJCALLSTACKDOWN", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo14 }, // Inst #1839 = tADJCALLSTACKDOWN
- { 1840, 2, 0, 128, "tADJCALLSTACKUP", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo148 }, // Inst #1840 = tADJCALLSTACKUP
- { 1841, 6, 2, 89, "tAND", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1841 = tAND
- { 1842, 3, 1, 128, "tANDsp", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, ImplicitList1, Barriers1, OperandInfo164 }, // Inst #1842 = tANDsp
- { 1843, 6, 2, 113, "tASRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 }, // Inst #1843 = tASRri
- { 1844, 6, 2, 114, "tASRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1844 = tASRrr
- { 1845, 1, 0, 0, "tB", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1845 = tB
- { 1846, 6, 2, 89, "tBIC", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1846 = tBIC
- { 1847, 1, 0, 128, "tBKPT", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1847 = tBKPT
- { 1848, 1, 0, 0, "tBL", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo14 }, // Inst #1848 = tBL
- { 1849, 1, 0, 0, "tBLXi", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo14 }, // Inst #1849 = tBLXi
- { 1850, 1, 0, 0, "tBLXi_r9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo14 }, // Inst #1850 = tBLXi_r9
- { 1851, 1, 0, 0, "tBLXr", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(4<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo16 }, // Inst #1851 = tBLXr
- { 1852, 1, 0, 0, "tBLXr_r9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(4<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo16 }, // Inst #1852 = tBLXr_r9
- { 1853, 1, 0, 0, "tBLr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo14 }, // Inst #1853 = tBLr9
- { 1854, 1, 0, 0, "tBRIND", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo16 }, // Inst #1854 = tBRIND
- { 1855, 3, 0, 0, "tBR_JTr", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo165 }, // Inst #1855 = tBR_JTr
- { 1856, 1, 0, 0, "tBX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo20 }, // Inst #1856 = tBX
- { 1857, 0, 0, 0, "tBX_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, 0 }, // Inst #1857 = tBX_RET
- { 1858, 1, 0, 0, "tBX_RET_vararg", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo20 }, // Inst #1858 = tBX_RET_vararg
- { 1859, 1, 0, 0, "tBXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo20 }, // Inst #1859 = tBXr9
- { 1860, 3, 0, 0, "tBcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1860 = tBcc
- { 1861, 1, 0, 0, "tBfar", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, ImplicitList8, NULL, OperandInfo14 }, // Inst #1861 = tBfar
- { 1862, 2, 0, 0, "tCBNZ", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo159 }, // Inst #1862 = tCBNZ
- { 1863, 2, 0, 0, "tCBZ", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo159 }, // Inst #1863 = tCBZ
- { 1864, 4, 0, 98, "tCMNz", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo166 }, // Inst #1864 = tCMNz
- { 1865, 4, 0, 98, "tCMPhir", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1865 = tCMPhir
- { 1866, 4, 0, 97, "tCMPi8", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo167 }, // Inst #1866 = tCMPi8
- { 1867, 4, 0, 98, "tCMPr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo166 }, // Inst #1867 = tCMPr
- { 1868, 4, 0, 98, "tCMPzhir", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1868 = tCMPzhir
- { 1869, 4, 0, 97, "tCMPzi8", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo167 }, // Inst #1869 = tCMPzi8
- { 1870, 4, 0, 98, "tCMPzr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo166 }, // Inst #1870 = tCMPzr
- { 1871, 1, 0, 128, "tCPS", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1871 = tCPS
- { 1872, 6, 2, 89, "tEOR", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1872 = tEOR
- { 1873, 2, 0, 128, "tInt_eh_sjlj_setjmp", 0, 0|(1<<4)|(23<<9), NULL, ImplicitList9, Barriers4, OperandInfo168 }, // Inst #1873 = tInt_eh_sjlj_setjmp
- { 1874, 5, 0, 103, "tLDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #1874 = tLDM
- { 1875, 6, 1, 104, "tLDR", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1875 = tLDR
- { 1876, 6, 1, 104, "tLDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1876 = tLDRB
- { 1877, 6, 1, 104, "tLDRBi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1877 = tLDRBi
- { 1878, 6, 1, 104, "tLDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1878 = tLDRH
- { 1879, 6, 1, 104, "tLDRHi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1879 = tLDRHi
- { 1880, 5, 1, 104, "tLDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo170 }, // Inst #1880 = tLDRSB
- { 1881, 5, 1, 104, "tLDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo170 }, // Inst #1881 = tLDRSH
- { 1882, 4, 1, 101, "tLDRcp", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo167 }, // Inst #1882 = tLDRcp
- { 1883, 6, 1, 104, "tLDRi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1883 = tLDRi
- { 1884, 4, 1, 101, "tLDRpci", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo167 }, // Inst #1884 = tLDRpci
- { 1885, 3, 1, 128, "tLDRpci_pic", 0|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|(1<<4), NULL, NULL, NULL, OperandInfo19 }, // Inst #1885 = tLDRpci_pic
- { 1886, 5, 1, 101, "tLDRspi", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo171 }, // Inst #1886 = tLDRspi
- { 1887, 4, 1, 88, "tLEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo167 }, // Inst #1887 = tLEApcrel
- { 1888, 5, 1, 88, "tLEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo172 }, // Inst #1888 = tLEApcrelJT
- { 1889, 6, 2, 113, "tLSLri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 }, // Inst #1889 = tLSLri
- { 1890, 6, 2, 114, "tLSLrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1890 = tLSLrr
- { 1891, 6, 2, 113, "tLSRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 }, // Inst #1891 = tLSRri
- { 1892, 6, 2, 114, "tLSRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1892 = tLSRrr
- { 1893, 5, 1, 93, "tMOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo173 }, // Inst #1893 = tMOVCCi
- { 1894, 5, 1, 94, "tMOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo44 }, // Inst #1894 = tMOVCCr
- { 1895, 5, 1, 128, "tMOVCCr_pseudo", 0|(1<<TID::Predicable)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo170 }, // Inst #1895 = tMOVCCr_pseudo
- { 1896, 2, 1, 112, "tMOVSr", 0, 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo168 }, // Inst #1896 = tMOVSr
- { 1897, 2, 1, 112, "tMOVgpr2gpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1897 = tMOVgpr2gpr
- { 1898, 2, 1, 112, "tMOVgpr2tgpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo174 }, // Inst #1898 = tMOVgpr2tgpr
- { 1899, 5, 2, 111, "tMOVi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo175 }, // Inst #1899 = tMOVi8
- { 1900, 2, 1, 112, "tMOVr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo168 }, // Inst #1900 = tMOVr
- { 1901, 2, 1, 112, "tMOVtgpr2gpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1901 = tMOVtgpr2gpr
- { 1902, 6, 2, 116, "tMUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1902 = tMUL
- { 1903, 5, 2, 112, "tMVN", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo176 }, // Inst #1903 = tMVN
- { 1904, 2, 0, 128, "tNOP", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1904 = tNOP
- { 1905, 6, 2, 89, "tORR", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1905 = tORR
- { 1906, 3, 1, 89, "tPICADD", 0|(1<<TID::NotDuplicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo163 }, // Inst #1906 = tPICADD
- { 1907, 3, 0, 0, "tPOP", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), ImplicitList2, ImplicitList2, NULL, OperandInfo177 }, // Inst #1907 = tPOP
- { 1908, 3, 0, 0, "tPOP_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo177 }, // Inst #1908 = tPOP_RET
- { 1909, 3, 0, 0, "tPUSH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(4<<4)|(23<<9), ImplicitList2, ImplicitList2, NULL, OperandInfo177 }, // Inst #1909 = tPUSH
- { 1910, 4, 1, 125, "tREV", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 }, // Inst #1910 = tREV
- { 1911, 4, 1, 125, "tREV16", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 }, // Inst #1911 = tREV16
- { 1912, 4, 1, 125, "tREVSH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 }, // Inst #1912 = tREVSH
- { 1913, 6, 2, 114, "tROR", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1913 = tROR
- { 1914, 5, 2, 88, "tRSB", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo176 }, // Inst #1914 = tRSB
- { 1915, 5, 1, 101, "tRestore", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo171 }, // Inst #1915 = tRestore
- { 1916, 6, 2, 89, "tSBC", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo156 }, // Inst #1916 = tSBC
- { 1917, 0, 0, 128, "tSETENDBE", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, 0 }, // Inst #1917 = tSETENDBE
- { 1918, 0, 0, 128, "tSETENDLE", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, 0 }, // Inst #1918 = tSETENDLE
- { 1919, 2, 0, 128, "tSEV", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1919 = tSEV
- { 1920, 5, 0, 120, "tSTM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #1920 = tSTM
- { 1921, 6, 0, 121, "tSTR", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1921 = tSTR
- { 1922, 6, 0, 121, "tSTRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1922 = tSTRB
- { 1923, 6, 0, 121, "tSTRBi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1923 = tSTRBi
- { 1924, 6, 0, 121, "tSTRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1924 = tSTRH
- { 1925, 6, 0, 121, "tSTRHi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1925 = tSTRHi
- { 1926, 6, 0, 121, "tSTRi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1926 = tSTRi
- { 1927, 5, 0, 118, "tSTRspi", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo171 }, // Inst #1927 = tSTRspi
- { 1928, 6, 2, 88, "tSUBi3", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 }, // Inst #1928 = tSUBi3
- { 1929, 6, 2, 88, "tSUBi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo158 }, // Inst #1929 = tSUBi8
- { 1930, 6, 2, 89, "tSUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1930 = tSUBrr
- { 1931, 3, 1, 88, "tSUBspi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo163 }, // Inst #1931 = tSUBspi
- { 1932, 3, 1, 128, "tSUBspi_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1932 = tSUBspi_
- { 1933, 3, 0, 0, "tSVC", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1933 = tSVC
- { 1934, 4, 1, 125, "tSXTB", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 }, // Inst #1934 = tSXTB
- { 1935, 4, 1, 125, "tSXTH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 }, // Inst #1935 = tSXTH
- { 1936, 5, 0, 118, "tSpill", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo171 }, // Inst #1936 = tSpill
- { 1937, 0, 0, 0, "tTPsoft", 0|(1<<TID::Call), 0|(3<<4)|(23<<9), NULL, ImplicitList10, NULL, 0 }, // Inst #1937 = tTPsoft
- { 1938, 0, 0, 0, "tTRAP", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, 0 }, // Inst #1938 = tTRAP
- { 1939, 4, 0, 98, "tTST", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo166 }, // Inst #1939 = tTST
- { 1940, 4, 1, 125, "tUXTB", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 }, // Inst #1940 = tUXTB
- { 1941, 4, 1, 125, "tUXTH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 }, // Inst #1941 = tUXTH
- { 1942, 2, 0, 128, "tWFE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1942 = tWFE
- { 1943, 2, 0, 128, "tWFI", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1943 = tWFI
- { 1944, 2, 0, 128, "tYIELD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1944 = tYIELD
+ { 66, 1, 0, 0, "BMOVPCRX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(2<<4)|(3<<9), NULL, ImplicitList3, Barriers2, OperandInfo17 }, // Inst #66 = BMOVPCRX
+ { 67, 1, 0, 0, "BMOVPCRXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(2<<4)|(3<<9), NULL, ImplicitList4, Barriers2, OperandInfo17 }, // Inst #67 = BMOVPCRXr9
+ { 68, 1, 0, 0, "BRIND", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(3<<4)|(3<<9), NULL, NULL, NULL, OperandInfo16 }, // Inst #68 = BRIND
+ { 69, 4, 0, 0, "BR_JTadd", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo18 }, // Inst #69 = BR_JTadd
+ { 70, 5, 0, 0, "BR_JTm", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo19 }, // Inst #70 = BR_JTm
+ { 71, 3, 0, 0, "BR_JTr", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(3<<9), NULL, NULL, NULL, OperandInfo20 }, // Inst #71 = BR_JTr
+ { 72, 1, 0, 0, "BX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(2<<4)|(3<<9), NULL, ImplicitList3, Barriers2, OperandInfo17 }, // Inst #72 = BX
+ { 73, 3, 0, 128, "BXJ", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #73 = BXJ
+ { 74, 2, 0, 0, "BX_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(3<<4)|(3<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #74 = BX_RET
+ { 75, 1, 0, 0, "BXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(2<<4)|(3<<9), NULL, ImplicitList4, Barriers2, OperandInfo17 }, // Inst #75 = BXr9
+ { 76, 3, 0, 0, "Bcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #76 = Bcc
+ { 77, 8, 0, 128, "CDP", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo23 }, // Inst #77 = CDP
+ { 78, 6, 0, 128, "CDP2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo24 }, // Inst #78 = CDP2
+ { 79, 0, 0, 128, "CLREX", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #79 = CLREX
+ { 80, 4, 1, 125, "CLZ", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #80 = CLZ
+ { 81, 4, 0, 97, "CMNzri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #81 = CMNzri
+ { 82, 4, 0, 98, "CMNzrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #82 = CMNzrr
+ { 83, 6, 0, 100, "CMNzrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo27 }, // Inst #83 = CMNzrs
+ { 84, 4, 0, 97, "CMPri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #84 = CMPri
+ { 85, 4, 0, 98, "CMPrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #85 = CMPrr
+ { 86, 6, 0, 100, "CMPrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo27 }, // Inst #86 = CMPrs
+ { 87, 4, 0, 97, "CMPzri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #87 = CMPzri
+ { 88, 4, 0, 98, "CMPzrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #88 = CMPzrr
+ { 89, 6, 0, 100, "CMPzrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo27 }, // Inst #89 = CMPzrs
+ { 90, 3, 0, 128, "CONSTPOOL_ENTRY", 0|(1<<TID::NotDuplicable), 0|(1<<4), NULL, NULL, NULL, OperandInfo28 }, // Inst #90 = CONSTPOOL_ENTRY
+ { 91, 1, 0, 128, "CPS", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #91 = CPS
+ { 92, 3, 0, 128, "DBG", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #92 = DBG
+ { 93, 0, 0, 128, "DMBish", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #93 = DMBish
+ { 94, 0, 0, 128, "DMBishst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #94 = DMBishst
+ { 95, 0, 0, 128, "DMBnsh", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #95 = DMBnsh
+ { 96, 0, 0, 128, "DMBnshst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #96 = DMBnshst
+ { 97, 0, 0, 128, "DMBosh", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #97 = DMBosh
+ { 98, 0, 0, 128, "DMBoshst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #98 = DMBoshst
+ { 99, 0, 0, 128, "DMBst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #99 = DMBst
+ { 100, 0, 0, 128, "DSBish", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #100 = DSBish
+ { 101, 0, 0, 128, "DSBishst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #101 = DSBishst
+ { 102, 0, 0, 128, "DSBnsh", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #102 = DSBnsh
+ { 103, 0, 0, 128, "DSBnshst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #103 = DSBnshst
+ { 104, 0, 0, 128, "DSBosh", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #104 = DSBosh
+ { 105, 0, 0, 128, "DSBoshst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #105 = DSBoshst
+ { 106, 0, 0, 128, "DSBst", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #106 = DSBst
+ { 107, 6, 1, 88, "EORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #107 = EORri
+ { 108, 6, 1, 89, "EORrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #108 = EORrr
+ { 109, 8, 1, 91, "EORrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #109 = EORrs
+ { 110, 4, 1, 26, "FCONSTD", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(3<<4)|(22<<9)|(1<<17), NULL, NULL, NULL, OperandInfo29 }, // Inst #110 = FCONSTD
+ { 111, 4, 1, 26, "FCONSTS", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(3<<4)|(22<<9)|(1<<17), NULL, NULL, NULL, OperandInfo30 }, // Inst #111 = FCONSTS
+ { 112, 2, 0, 82, "FMSTAT", 0|(1<<TID::Predicable), 0|(3<<4)|(22<<9)|(1<<17), ImplicitList5, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #112 = FMSTAT
+ { 113, 0, 0, 128, "ISBsy", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #113 = ISBsy
+ { 114, 1, 0, 128, "Int_MemBarrierV6", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, OperandInfo16 }, // Inst #114 = Int_MemBarrierV6
+ { 115, 0, 0, 128, "Int_MemBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #115 = Int_MemBarrierV7
+ { 116, 1, 0, 128, "Int_SyncBarrierV6", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, OperandInfo16 }, // Inst #116 = Int_SyncBarrierV6
+ { 117, 0, 0, 128, "Int_SyncBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #117 = Int_SyncBarrierV7
+ { 118, 2, 0, 128, "Int_eh_sjlj_setjmp", 0, 0|(1<<4), NULL, ImplicitList6, Barriers3, OperandInfo32 }, // Inst #118 = Int_eh_sjlj_setjmp
+ { 119, 7, 0, 128, "LDC2L_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #119 = LDC2L_OFFSET
+ { 120, 6, 0, 128, "LDC2L_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 }, // Inst #120 = LDC2L_OPTION
+ { 121, 7, 0, 128, "LDC2L_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #121 = LDC2L_POST
+ { 122, 7, 0, 128, "LDC2L_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #122 = LDC2L_PRE
+ { 123, 7, 0, 128, "LDC2_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #123 = LDC2_OFFSET
+ { 124, 6, 0, 128, "LDC2_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 }, // Inst #124 = LDC2_OPTION
+ { 125, 7, 0, 128, "LDC2_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #125 = LDC2_POST
+ { 126, 7, 0, 128, "LDC2_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #126 = LDC2_PRE
+ { 127, 7, 0, 128, "LDCL_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #127 = LDCL_OFFSET
+ { 128, 6, 0, 128, "LDCL_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 }, // Inst #128 = LDCL_OPTION
+ { 129, 7, 0, 128, "LDCL_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #129 = LDCL_POST
+ { 130, 7, 0, 128, "LDCL_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #130 = LDCL_PRE
+ { 131, 7, 0, 128, "LDC_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #131 = LDC_OFFSET
+ { 132, 6, 0, 128, "LDC_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 }, // Inst #132 = LDC_OPTION
+ { 133, 7, 0, 128, "LDC_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #133 = LDC_POST
+ { 134, 7, 0, 128, "LDC_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #134 = LDC_PRE
+ { 135, 5, 0, 103, "LDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #135 = LDM
+ { 136, 5, 0, 0, "LDM_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #136 = LDM_RET
+ { 137, 6, 1, 104, "LDR", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #137 = LDR
+ { 138, 6, 1, 104, "LDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #138 = LDRB
+ { 139, 7, 2, 105, "LDRBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #139 = LDRBT
+ { 140, 7, 2, 105, "LDRB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #140 = LDRB_POST
+ { 141, 7, 2, 105, "LDRB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(1<<7)|(6<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #141 = LDRB_PRE
+ { 142, 7, 2, 104, "LDRD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo10 }, // Inst #142 = LDRD
+ { 143, 8, 3, 104, "LDRD_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #143 = LDRD_POST
+ { 144, 8, 3, 104, "LDRD_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo37 }, // Inst #144 = LDRD_PRE
+ { 145, 4, 1, 128, "LDREX", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #145 = LDREX
+ { 146, 4, 1, 128, "LDREXB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #146 = LDREXB
+ { 147, 5, 2, 128, "LDREXD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #147 = LDREXD
+ { 148, 4, 1, 128, "LDREXH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #148 = LDREXH
+ { 149, 6, 1, 104, "LDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #149 = LDRH
+ { 150, 7, 2, 105, "LDRHT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #150 = LDRHT
+ { 151, 7, 2, 105, "LDRH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #151 = LDRH_POST
+ { 152, 7, 2, 105, "LDRH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #152 = LDRH_PRE
+ { 153, 6, 1, 104, "LDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #153 = LDRSB
+ { 154, 7, 2, 105, "LDRSBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #154 = LDRSBT
+ { 155, 7, 2, 105, "LDRSB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #155 = LDRSB_POST
+ { 156, 7, 2, 105, "LDRSB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #156 = LDRSB_PRE
+ { 157, 6, 1, 104, "LDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|3|(3<<4)|(8<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #157 = LDRSH
+ { 158, 7, 2, 105, "LDRSHT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #158 = LDRSHT
+ { 159, 7, 2, 105, "LDRSH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(2<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #159 = LDRSH_POST
+ { 160, 7, 2, 105, "LDRSH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|3|(3<<4)|(1<<7)|(8<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #160 = LDRSH_PRE
+ { 161, 7, 2, 105, "LDRT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #161 = LDRT
+ { 162, 7, 2, 105, "LDR_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(2<<7)|(6<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #162 = LDR_POST
+ { 163, 7, 2, 105, "LDR_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|2|(3<<4)|(1<<7)|(6<<9), NULL, NULL, NULL, OperandInfo36 }, // Inst #163 = LDR_PRE
+ { 164, 6, 1, 104, "LDRcp", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(6<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #164 = LDRcp
+ { 165, 4, 1, 88, "LEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo26 }, // Inst #165 = LEApcrel
+ { 166, 5, 1, 88, "LEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo38 }, // Inst #166 = LEApcrelJT
+ { 167, 8, 0, 128, "MCR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #167 = MCR
+ { 168, 6, 0, 128, "MCR2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #168 = MCR2
+ { 169, 7, 0, 128, "MCRR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #169 = MCRR
+ { 170, 5, 0, 128, "MCRR2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo41 }, // Inst #170 = MCRR2
+ { 171, 7, 1, 109, "MLA", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo42 }, // Inst #171 = MLA
+ { 172, 6, 1, 109, "MLS", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #172 = MLS
+ { 173, 5, 1, 93, "MOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo15 }, // Inst #173 = MOVCCi
+ { 174, 5, 1, 94, "MOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo44 }, // Inst #174 = MOVCCr
+ { 175, 7, 1, 96, "MOVCCs", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo45 }, // Inst #175 = MOVCCs
+ { 176, 2, 0, 0, "MOVPCLR", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(3<<4)|(3<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #176 = MOVPCLR
+ { 177, 1, 0, 0, "MOVPCRX", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(3<<4)|(3<<9), NULL, NULL, NULL, OperandInfo16 }, // Inst #177 = MOVPCRX
+ { 178, 5, 1, 111, "MOVTi16", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo15 }, // Inst #178 = MOVTi16
+ { 179, 5, 1, 111, "MOVi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo46 }, // Inst #179 = MOVi
+ { 180, 4, 1, 111, "MOVi16", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo26 }, // Inst #180 = MOVi16
+ { 181, 4, 1, 111, "MOVi2pieces", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|1|(2<<4), NULL, NULL, NULL, OperandInfo26 }, // Inst #181 = MOVi2pieces
+ { 182, 4, 1, 111, "MOVi32imm", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|1|(2<<4), NULL, NULL, NULL, OperandInfo26 }, // Inst #182 = MOVi32imm
+ { 183, 5, 1, 112, "MOVr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo47 }, // Inst #183 = MOVr
+ { 184, 5, 1, 113, "MOVrx", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(1<<15), ImplicitList1, NULL, NULL, OperandInfo47 }, // Inst #184 = MOVrx
+ { 185, 7, 1, 114, "MOVs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo48 }, // Inst #185 = MOVs
+ { 186, 4, 1, 113, "MOVsra_flag", 0|(1<<TID::Predicable), 0|1|(3<<4)|(1<<15), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #186 = MOVsra_flag
+ { 187, 4, 1, 113, "MOVsrl_flag", 0|(1<<TID::Predicable), 0|1|(3<<4)|(1<<15), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #187 = MOVsrl_flag
+ { 188, 8, 0, 128, "MRC", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo39 }, // Inst #188 = MRC
+ { 189, 6, 0, 128, "MRC2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo40 }, // Inst #189 = MRC2
+ { 190, 7, 0, 128, "MRRC", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #190 = MRRC
+ { 191, 5, 0, 128, "MRRC2", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo41 }, // Inst #191 = MRRC2
+ { 192, 3, 1, 128, "MRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #192 = MRS
+ { 193, 3, 1, 128, "MRSsys", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #193 = MRSsys
+ { 194, 3, 0, 128, "MSR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #194 = MSR
+ { 195, 3, 0, 128, "MSRi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #195 = MSRi
+ { 196, 3, 0, 128, "MSRsys", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #196 = MSRsys
+ { 197, 3, 0, 128, "MSRsysi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #197 = MSRsysi
+ { 198, 6, 1, 116, "MUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #198 = MUL
+ { 199, 5, 1, 111, "MVNi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo46 }, // Inst #199 = MVNi
+ { 200, 5, 1, 112, "MVNr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9)|(1<<15), NULL, NULL, NULL, OperandInfo47 }, // Inst #200 = MVNr
+ { 201, 7, 1, 114, "MVNs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9)|(1<<15), NULL, NULL, NULL, OperandInfo48 }, // Inst #201 = MVNs
+ { 202, 2, 0, 128, "NOP", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #202 = NOP
+ { 203, 6, 1, 88, "ORRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #203 = ORRri
+ { 204, 6, 1, 89, "ORRrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #204 = ORRrr
+ { 205, 8, 1, 91, "ORRrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #205 = ORRrs
+ { 206, 5, 1, 89, "PICADD", 0|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|1|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #206 = PICADD
+ { 207, 5, 1, 104, "PICLDR", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #207 = PICLDR
+ { 208, 5, 1, 104, "PICLDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #208 = PICLDRB
+ { 209, 5, 1, 104, "PICLDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #209 = PICLDRH
+ { 210, 5, 1, 104, "PICLDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #210 = PICLDRSB
+ { 211, 5, 1, 104, "PICLDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #211 = PICLDRSH
+ { 212, 5, 0, 121, "PICSTR", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #212 = PICSTR
+ { 213, 5, 0, 121, "PICSTRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|2|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #213 = PICSTRB
+ { 214, 5, 0, 121, "PICSTRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::NotDuplicable), 0|3|(3<<4), NULL, NULL, NULL, OperandInfo8 }, // Inst #214 = PICSTRH
+ { 215, 6, 1, 90, "PKHBT", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #215 = PKHBT
+ { 216, 6, 1, 90, "PKHTB", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #216 = PKHTB
+ { 217, 2, 0, 128, "PLDWi", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo49 }, // Inst #217 = PLDWi
+ { 218, 3, 0, 128, "PLDWr", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo2 }, // Inst #218 = PLDWr
+ { 219, 2, 0, 128, "PLDi", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo49 }, // Inst #219 = PLDi
+ { 220, 3, 0, 128, "PLDr", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo2 }, // Inst #220 = PLDr
+ { 221, 2, 0, 128, "PLIi", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo49 }, // Inst #221 = PLIi
+ { 222, 3, 0, 128, "PLIr", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo2 }, // Inst #222 = PLIr
+ { 223, 5, 1, 89, "QADD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #223 = QADD
+ { 224, 5, 1, 89, "QADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #224 = QADD16
+ { 225, 5, 1, 89, "QADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #225 = QADD8
+ { 226, 5, 1, 89, "QASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #226 = QASX
+ { 227, 5, 1, 89, "QDADD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #227 = QDADD
+ { 228, 5, 1, 89, "QDSUB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #228 = QDSUB
+ { 229, 5, 1, 89, "QSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #229 = QSAX
+ { 230, 5, 1, 89, "QSUB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #230 = QSUB
+ { 231, 5, 1, 89, "QSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #231 = QSUB16
+ { 232, 5, 1, 89, "QSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #232 = QSUB8
+ { 233, 4, 1, 125, "RBIT", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #233 = RBIT
+ { 234, 4, 1, 125, "REV", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #234 = REV
+ { 235, 4, 1, 125, "REV16", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #235 = REV16
+ { 236, 4, 1, 125, "REVSH", 0|(1<<TID::Predicable), 0|(3<<4)|(11<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #236 = REVSH
+ { 237, 3, 0, 128, "RFE", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo50 }, // Inst #237 = RFE
+ { 238, 3, 0, 128, "RFEW", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo50 }, // Inst #238 = RFEW
+ { 239, 5, 1, 88, "RSBSri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #239 = RSBSri
+ { 240, 7, 1, 91, "RSBSrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #240 = RSBSrs
+ { 241, 6, 1, 88, "RSBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #241 = RSBri
+ { 242, 8, 1, 91, "RSBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #242 = RSBrs
+ { 243, 3, 1, 88, "RSCSri", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #243 = RSCSri
+ { 244, 5, 1, 91, "RSCSrs", 0, 0|1|(3<<4)|(5<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #244 = RSCSrs
+ { 245, 6, 1, 88, "RSCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #245 = RSCri
+ { 246, 8, 1, 91, "RSCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), ImplicitList1, NULL, NULL, OperandInfo7 }, // Inst #246 = RSCrs
+ { 247, 5, 1, 89, "SADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #247 = SADD16
+ { 248, 5, 1, 89, "SADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #248 = SADD8
+ { 249, 5, 1, 89, "SASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #249 = SASX
+ { 250, 3, 1, 88, "SBCSSri", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #250 = SBCSSri
+ { 251, 3, 1, 89, "SBCSSrr", 0, 0|1|(3<<4)|(4<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #251 = SBCSSrr
+ { 252, 5, 1, 91, "SBCSSrs", 0, 0|1|(3<<4)|(5<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #252 = SBCSSrs
+ { 253, 6, 1, 88, "SBCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #253 = SBCri
+ { 254, 6, 1, 89, "SBCrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #254 = SBCrr
+ { 255, 8, 1, 91, "SBCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), ImplicitList1, NULL, NULL, OperandInfo7 }, // Inst #255 = SBCrs
+ { 256, 6, 1, 88, "SBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo51 }, // Inst #256 = SBFX
+ { 257, 5, 1, 128, "SEL", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #257 = SEL
+ { 258, 0, 0, 128, "SETENDBE", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #258 = SETENDBE
+ { 259, 0, 0, 128, "SETENDLE", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, 0 }, // Inst #259 = SETENDLE
+ { 260, 2, 0, 128, "SEV", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #260 = SEV
+ { 261, 5, 1, 89, "SHADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #261 = SHADD16
+ { 262, 5, 1, 89, "SHADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #262 = SHADD8
+ { 263, 5, 1, 89, "SHASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #263 = SHASX
+ { 264, 5, 1, 89, "SHSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #264 = SHSAX
+ { 265, 5, 1, 89, "SHSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #265 = SHSUB16
+ { 266, 5, 1, 89, "SHSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #266 = SHSUB8
+ { 267, 3, 0, 128, "SMC", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #267 = SMC
+ { 268, 6, 1, 108, "SMLABB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #268 = SMLABB
+ { 269, 6, 1, 108, "SMLABT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #269 = SMLABT
+ { 270, 6, 1, 128, "SMLAD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #270 = SMLAD
+ { 271, 6, 1, 128, "SMLADX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #271 = SMLADX
+ { 272, 7, 2, 110, "SMLAL", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo42 }, // Inst #272 = SMLAL
+ { 273, 6, 2, 110, "SMLALBB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #273 = SMLALBB
+ { 274, 6, 2, 110, "SMLALBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #274 = SMLALBT
+ { 275, 6, 2, 128, "SMLALD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #275 = SMLALD
+ { 276, 6, 2, 128, "SMLALDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #276 = SMLALDX
+ { 277, 6, 2, 110, "SMLALTB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #277 = SMLALTB
+ { 278, 6, 2, 110, "SMLALTT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #278 = SMLALTT
+ { 279, 6, 1, 108, "SMLATB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #279 = SMLATB
+ { 280, 6, 1, 108, "SMLATT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #280 = SMLATT
+ { 281, 6, 1, 108, "SMLAWB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #281 = SMLAWB
+ { 282, 6, 1, 108, "SMLAWT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #282 = SMLAWT
+ { 283, 6, 1, 128, "SMLSD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #283 = SMLSD
+ { 284, 6, 1, 128, "SMLSDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #284 = SMLSDX
+ { 285, 6, 2, 128, "SMLSLD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #285 = SMLSLD
+ { 286, 6, 2, 128, "SMLSLDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #286 = SMLSLDX
+ { 287, 6, 1, 109, "SMMLA", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #287 = SMMLA
+ { 288, 6, 1, 109, "SMMLAR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #288 = SMMLAR
+ { 289, 6, 1, 109, "SMMLS", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #289 = SMMLS
+ { 290, 6, 1, 109, "SMMLSR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #290 = SMMLSR
+ { 291, 5, 1, 116, "SMMUL", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #291 = SMMUL
+ { 292, 5, 1, 116, "SMMULR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #292 = SMMULR
+ { 293, 5, 1, 128, "SMUAD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #293 = SMUAD
+ { 294, 5, 1, 128, "SMUADX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #294 = SMUADX
+ { 295, 5, 1, 116, "SMULBB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #295 = SMULBB
+ { 296, 5, 1, 116, "SMULBT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #296 = SMULBT
+ { 297, 7, 2, 117, "SMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo42 }, // Inst #297 = SMULL
+ { 298, 5, 1, 116, "SMULTB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #298 = SMULTB
+ { 299, 5, 1, 116, "SMULTT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #299 = SMULTT
+ { 300, 5, 1, 115, "SMULWB", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #300 = SMULWB
+ { 301, 5, 1, 115, "SMULWT", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #301 = SMULWT
+ { 302, 5, 1, 128, "SMUSD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #302 = SMUSD
+ { 303, 5, 1, 128, "SMUSDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #303 = SMUSDX
+ { 304, 3, 0, 128, "SRS", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo20 }, // Inst #304 = SRS
+ { 305, 3, 0, 128, "SRSW", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo20 }, // Inst #305 = SRSW
+ { 306, 5, 1, 128, "SSAT16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo52 }, // Inst #306 = SSAT16
+ { 307, 6, 1, 128, "SSATasr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo53 }, // Inst #307 = SSATasr
+ { 308, 6, 1, 128, "SSATlsl", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo53 }, // Inst #308 = SSATlsl
+ { 309, 5, 1, 89, "SSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #309 = SSAX
+ { 310, 5, 1, 89, "SSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #310 = SSUB16
+ { 311, 5, 1, 89, "SSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #311 = SSUB8
+ { 312, 7, 0, 128, "STC2L_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #312 = STC2L_OFFSET
+ { 313, 6, 0, 128, "STC2L_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 }, // Inst #313 = STC2L_OPTION
+ { 314, 7, 0, 128, "STC2L_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #314 = STC2L_POST
+ { 315, 7, 0, 128, "STC2L_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #315 = STC2L_PRE
+ { 316, 7, 0, 128, "STC2_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #316 = STC2_OFFSET
+ { 317, 6, 0, 128, "STC2_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 }, // Inst #317 = STC2_OPTION
+ { 318, 7, 0, 128, "STC2_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #318 = STC2_POST
+ { 319, 7, 0, 128, "STC2_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #319 = STC2_PRE
+ { 320, 7, 0, 128, "STCL_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #320 = STCL_OFFSET
+ { 321, 6, 0, 128, "STCL_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 }, // Inst #321 = STCL_OPTION
+ { 322, 7, 0, 128, "STCL_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #322 = STCL_POST
+ { 323, 7, 0, 128, "STCL_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #323 = STCL_PRE
+ { 324, 7, 0, 128, "STC_OFFSET", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #324 = STC_OFFSET
+ { 325, 6, 0, 128, "STC_OPTION", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo34 }, // Inst #325 = STC_OPTION
+ { 326, 7, 0, 128, "STC_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #326 = STC_POST
+ { 327, 7, 0, 128, "STC_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo33 }, // Inst #327 = STC_PRE
+ { 328, 5, 0, 120, "STM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|4|(3<<4)|(10<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #328 = STM
+ { 329, 6, 0, 121, "STR", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(7<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #329 = STR
+ { 330, 6, 0, 121, "STRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(7<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #330 = STRB
+ { 331, 7, 1, 122, "STRBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo54 }, // Inst #331 = STRBT
+ { 332, 7, 1, 122, "STRB_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo54 }, // Inst #332 = STRB_POST
+ { 333, 7, 1, 122, "STRB_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(1<<7)|(7<<9), NULL, NULL, NULL, OperandInfo54 }, // Inst #333 = STRB_PRE
+ { 334, 7, 0, 121, "STRD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|3|(3<<4)|(9<<9), NULL, NULL, NULL, OperandInfo10 }, // Inst #334 = STRD
+ { 335, 8, 1, 122, "STRD_POST", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|3|(3<<4)|(2<<7)|(9<<9), NULL, NULL, NULL, OperandInfo55 }, // Inst #335 = STRD_POST
+ { 336, 8, 1, 122, "STRD_PRE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|3|(3<<4)|(1<<7)|(9<<9), NULL, NULL, NULL, OperandInfo55 }, // Inst #336 = STRD_PRE
+ { 337, 5, 1, 128, "STREX", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo56 }, // Inst #337 = STREX
+ { 338, 5, 1, 128, "STREXB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo56 }, // Inst #338 = STREXB
+ { 339, 6, 1, 128, "STREXD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo57 }, // Inst #339 = STREXD
+ { 340, 5, 1, 128, "STREXH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo56 }, // Inst #340 = STREXH
+ { 341, 6, 0, 121, "STRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(9<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #341 = STRH
+ { 342, 7, 1, 122, "STRHT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|3|(3<<4)|(2<<7)|(9<<9), NULL, NULL, NULL, OperandInfo54 }, // Inst #342 = STRHT
+ { 343, 7, 1, 122, "STRH_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(2<<7)|(9<<9), NULL, NULL, NULL, OperandInfo54 }, // Inst #343 = STRH_POST
+ { 344, 7, 1, 122, "STRH_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|3|(3<<4)|(1<<7)|(9<<9), NULL, NULL, NULL, OperandInfo54 }, // Inst #344 = STRH_PRE
+ { 345, 7, 1, 122, "STRT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo54 }, // Inst #345 = STRT
+ { 346, 7, 1, 122, "STR_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(2<<7)|(7<<9), NULL, NULL, NULL, OperandInfo54 }, // Inst #346 = STR_POST
+ { 347, 7, 1, 122, "STR_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|2|(3<<4)|(1<<7)|(7<<9), NULL, NULL, NULL, OperandInfo54 }, // Inst #347 = STR_PRE
+ { 348, 5, 1, 88, "SUBSri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #348 = SUBSri
+ { 349, 5, 1, 89, "SUBSrr", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #349 = SUBSrr
+ { 350, 7, 1, 91, "SUBSrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #350 = SUBSrs
+ { 351, 6, 1, 88, "SUBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #351 = SUBri
+ { 352, 6, 1, 89, "SUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #352 = SUBrr
+ { 353, 8, 1, 91, "SUBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|1|(3<<4)|(5<<9), NULL, NULL, NULL, OperandInfo7 }, // Inst #353 = SUBrs
+ { 354, 3, 0, 0, "SVC", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(2<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #354 = SVC
+ { 355, 5, 1, 128, "SWP", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #355 = SWP
+ { 356, 5, 1, 128, "SWPB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(28<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #356 = SWPB
+ { 357, 5, 1, 89, "SXTAB16rr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #357 = SXTAB16rr
+ { 358, 6, 1, 90, "SXTAB16rr_rot", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #358 = SXTAB16rr_rot
+ { 359, 5, 1, 89, "SXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #359 = SXTABrr
+ { 360, 6, 1, 90, "SXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #360 = SXTABrr_rot
+ { 361, 5, 1, 89, "SXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #361 = SXTAHrr
+ { 362, 6, 1, 90, "SXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #362 = SXTAHrr_rot
+ { 363, 4, 1, 125, "SXTB16r", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #363 = SXTB16r
+ { 364, 5, 1, 126, "SXTB16r_rot", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #364 = SXTB16r_rot
+ { 365, 4, 1, 125, "SXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #365 = SXTBr
+ { 366, 5, 1, 126, "SXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #366 = SXTBr_rot
+ { 367, 4, 1, 125, "SXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #367 = SXTHr
+ { 368, 5, 1, 126, "SXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #368 = SXTHr_rot
+ { 369, 4, 0, 97, "TEQri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #369 = TEQri
+ { 370, 4, 0, 98, "TEQrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #370 = TEQrr
+ { 371, 6, 0, 100, "TEQrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo27 }, // Inst #371 = TEQrs
+ { 372, 0, 0, 0, "TPsoft", 0|(1<<TID::Call), 0|(3<<4)|(2<<9), NULL, ImplicitList7, Barriers1, 0 }, // Inst #372 = TPsoft
+ { 373, 2, 0, 128, "TRAP", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #373 = TRAP
+ { 374, 4, 0, 97, "TSTri", 0|(1<<TID::Predicable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #374 = TSTri
+ { 375, 4, 0, 98, "TSTrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|1|(3<<4)|(4<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #375 = TSTrr
+ { 376, 6, 0, 100, "TSTrs", 0|(1<<TID::Predicable), 0|1|(3<<4)|(5<<9), NULL, ImplicitList1, Barriers1, OperandInfo27 }, // Inst #376 = TSTrs
+ { 377, 5, 1, 89, "UADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #377 = UADD16
+ { 378, 5, 1, 89, "UADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #378 = UADD8
+ { 379, 5, 1, 89, "UASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #379 = UASX
+ { 380, 6, 1, 88, "UBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|1|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo51 }, // Inst #380 = UBFX
+ { 381, 5, 1, 89, "UHADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #381 = UHADD16
+ { 382, 5, 1, 89, "UHADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #382 = UHADD8
+ { 383, 5, 1, 89, "UHASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #383 = UHASX
+ { 384, 5, 1, 89, "UHSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #384 = UHSAX
+ { 385, 5, 1, 89, "UHSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #385 = UHSUB16
+ { 386, 5, 1, 89, "UHSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #386 = UHSUB8
+ { 387, 6, 2, 110, "UMAAL", 0|(1<<TID::Predicable), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #387 = UMAAL
+ { 388, 7, 2, 110, "UMLAL", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo42 }, // Inst #388 = UMLAL
+ { 389, 7, 2, 117, "UMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo42 }, // Inst #389 = UMULL
+ { 390, 5, 1, 89, "UQADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #390 = UQADD16
+ { 391, 5, 1, 89, "UQADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #391 = UQADD8
+ { 392, 5, 1, 89, "UQASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #392 = UQASX
+ { 393, 5, 1, 89, "UQSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #393 = UQSAX
+ { 394, 5, 1, 89, "UQSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #394 = UQSUB16
+ { 395, 5, 1, 89, "UQSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #395 = UQSUB8
+ { 396, 5, 1, 128, "USAD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #396 = USAD8
+ { 397, 6, 1, 128, "USADA8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(1<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #397 = USADA8
+ { 398, 5, 1, 128, "USAT16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo52 }, // Inst #398 = USAT16
+ { 399, 6, 1, 128, "USATasr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo53 }, // Inst #399 = USATasr
+ { 400, 6, 1, 128, "USATlsl", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo53 }, // Inst #400 = USATlsl
+ { 401, 5, 1, 89, "USAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #401 = USAX
+ { 402, 5, 1, 89, "USUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #402 = USUB16
+ { 403, 5, 1, 89, "USUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(4<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #403 = USUB8
+ { 404, 5, 1, 89, "UXTAB16rr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #404 = UXTAB16rr
+ { 405, 6, 1, 90, "UXTAB16rr_rot", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #405 = UXTAB16rr_rot
+ { 406, 5, 1, 89, "UXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #406 = UXTABrr
+ { 407, 6, 1, 90, "UXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #407 = UXTABrr_rot
+ { 408, 5, 1, 89, "UXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #408 = UXTAHrr
+ { 409, 6, 1, 90, "UXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #409 = UXTAHrr_rot
+ { 410, 4, 1, 125, "UXTB16r", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #410 = UXTB16r
+ { 411, 5, 1, 126, "UXTB16r_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #411 = UXTB16r_rot
+ { 412, 4, 1, 125, "UXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #412 = UXTBr
+ { 413, 5, 1, 126, "UXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #413 = UXTBr_rot
+ { 414, 4, 1, 125, "UXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #414 = UXTHr
+ { 415, 5, 1, 126, "UXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(12<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #415 = UXTHr_rot
+ { 416, 6, 1, 17, "VABALsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #416 = VABALsv2i64
+ { 417, 6, 1, 17, "VABALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #417 = VABALsv4i32
+ { 418, 6, 1, 17, "VABALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #418 = VABALsv8i16
+ { 419, 6, 1, 17, "VABALuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #419 = VABALuv2i64
+ { 420, 6, 1, 17, "VABALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #420 = VABALuv4i32
+ { 421, 6, 1, 17, "VABALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #421 = VABALuv8i16
+ { 422, 6, 1, 18, "VABAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #422 = VABAsv16i8
+ { 423, 6, 1, 19, "VABAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #423 = VABAsv2i32
+ { 424, 6, 1, 17, "VABAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #424 = VABAsv4i16
+ { 425, 6, 1, 20, "VABAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #425 = VABAsv4i32
+ { 426, 6, 1, 18, "VABAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #426 = VABAsv8i16
+ { 427, 6, 1, 17, "VABAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #427 = VABAsv8i8
+ { 428, 6, 1, 18, "VABAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #428 = VABAuv16i8
+ { 429, 6, 1, 19, "VABAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #429 = VABAuv2i32
+ { 430, 6, 1, 17, "VABAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #430 = VABAuv4i16
+ { 431, 6, 1, 20, "VABAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #431 = VABAuv4i32
+ { 432, 6, 1, 18, "VABAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #432 = VABAuv8i16
+ { 433, 6, 1, 17, "VABAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #433 = VABAuv8i8
+ { 434, 5, 1, 4, "VABDLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #434 = VABDLsv2i64
+ { 435, 5, 1, 4, "VABDLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #435 = VABDLsv4i32
+ { 436, 5, 1, 4, "VABDLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #436 = VABDLsv8i16
+ { 437, 5, 1, 4, "VABDLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #437 = VABDLuv2i64
+ { 438, 5, 1, 4, "VABDLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #438 = VABDLuv4i32
+ { 439, 5, 1, 4, "VABDLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #439 = VABDLuv8i16
+ { 440, 5, 1, 1, "VABDfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #440 = VABDfd
+ { 441, 5, 1, 2, "VABDfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #441 = VABDfq
+ { 442, 5, 1, 4, "VABDsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #442 = VABDsv16i8
+ { 443, 5, 1, 3, "VABDsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #443 = VABDsv2i32
+ { 444, 5, 1, 3, "VABDsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #444 = VABDsv4i16
+ { 445, 5, 1, 4, "VABDsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #445 = VABDsv4i32
+ { 446, 5, 1, 4, "VABDsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #446 = VABDsv8i16
+ { 447, 5, 1, 3, "VABDsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #447 = VABDsv8i8
+ { 448, 5, 1, 4, "VABDuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #448 = VABDuv16i8
+ { 449, 5, 1, 3, "VABDuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #449 = VABDuv2i32
+ { 450, 5, 1, 3, "VABDuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #450 = VABDuv4i16
+ { 451, 5, 1, 4, "VABDuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #451 = VABDuv4i32
+ { 452, 5, 1, 4, "VABDuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #452 = VABDuv8i16
+ { 453, 5, 1, 3, "VABDuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #453 = VABDuv8i8
+ { 454, 4, 1, 87, "VABSD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #454 = VABSD
+ { 455, 4, 1, 86, "VABSS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #455 = VABSS
+ { 456, 4, 1, 57, "VABSfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #456 = VABSfd
+ { 457, 4, 1, 57, "VABSfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #457 = VABSfd_sfp
+ { 458, 4, 1, 58, "VABSfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #458 = VABSfq
+ { 459, 4, 1, 60, "VABSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #459 = VABSv16i8
+ { 460, 4, 1, 59, "VABSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #460 = VABSv2i32
+ { 461, 4, 1, 59, "VABSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #461 = VABSv4i16
+ { 462, 4, 1, 60, "VABSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #462 = VABSv4i32
+ { 463, 4, 1, 60, "VABSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #463 = VABSv8i16
+ { 464, 4, 1, 59, "VABSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #464 = VABSv8i8
+ { 465, 5, 1, 1, "VACGEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #465 = VACGEd
+ { 466, 5, 1, 2, "VACGEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #466 = VACGEq
+ { 467, 5, 1, 1, "VACGTd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #467 = VACGTd
+ { 468, 5, 1, 2, "VACGTq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #468 = VACGTq
+ { 469, 5, 1, 62, "VADDD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #469 = VADDD
+ { 470, 5, 1, 3, "VADDHNv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #470 = VADDHNv2i32
+ { 471, 5, 1, 3, "VADDHNv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #471 = VADDHNv4i16
+ { 472, 5, 1, 3, "VADDHNv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #472 = VADDHNv8i8
+ { 473, 5, 1, 44, "VADDLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #473 = VADDLsv2i64
+ { 474, 5, 1, 44, "VADDLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #474 = VADDLsv4i32
+ { 475, 5, 1, 44, "VADDLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #475 = VADDLsv8i16
+ { 476, 5, 1, 44, "VADDLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #476 = VADDLuv2i64
+ { 477, 5, 1, 44, "VADDLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #477 = VADDLuv4i32
+ { 478, 5, 1, 44, "VADDLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #478 = VADDLuv8i16
+ { 479, 5, 1, 61, "VADDS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #479 = VADDS
+ { 480, 5, 1, 47, "VADDWsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #480 = VADDWsv2i64
+ { 481, 5, 1, 47, "VADDWsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #481 = VADDWsv4i32
+ { 482, 5, 1, 47, "VADDWsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #482 = VADDWsv8i16
+ { 483, 5, 1, 47, "VADDWuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #483 = VADDWuv2i64
+ { 484, 5, 1, 47, "VADDWuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #484 = VADDWuv4i32
+ { 485, 5, 1, 47, "VADDWuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #485 = VADDWuv8i16
+ { 486, 5, 1, 1, "VADDfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #486 = VADDfd
+ { 487, 5, 1, 1, "VADDfd_sfp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #487 = VADDfd_sfp
+ { 488, 5, 1, 2, "VADDfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #488 = VADDfq
+ { 489, 5, 1, 6, "VADDv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #489 = VADDv16i8
+ { 490, 5, 1, 5, "VADDv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #490 = VADDv1i64
+ { 491, 5, 1, 5, "VADDv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #491 = VADDv2i32
+ { 492, 5, 1, 6, "VADDv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #492 = VADDv2i64
+ { 493, 5, 1, 5, "VADDv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #493 = VADDv4i16
+ { 494, 5, 1, 6, "VADDv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #494 = VADDv4i32
+ { 495, 5, 1, 6, "VADDv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #495 = VADDv8i16
+ { 496, 5, 1, 5, "VADDv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #496 = VADDv8i8
+ { 497, 5, 1, 5, "VANDd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #497 = VANDd
+ { 498, 5, 1, 6, "VANDq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #498 = VANDq
+ { 499, 5, 1, 5, "VBICd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #499 = VBICd
+ { 500, 5, 1, 6, "VBICq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #500 = VBICq
+ { 501, 6, 1, 5, "VBIFd", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #501 = VBIFd
+ { 502, 6, 1, 6, "VBIFq", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #502 = VBIFq
+ { 503, 6, 1, 5, "VBITd", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #503 = VBITd
+ { 504, 6, 1, 6, "VBITq", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #504 = VBITq
+ { 505, 6, 1, 7, "VBSLd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #505 = VBSLd
+ { 506, 6, 1, 8, "VBSLq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #506 = VBSLq
+ { 507, 5, 1, 1, "VCEQfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #507 = VCEQfd
+ { 508, 5, 1, 2, "VCEQfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #508 = VCEQfq
+ { 509, 5, 1, 4, "VCEQv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #509 = VCEQv16i8
+ { 510, 5, 1, 3, "VCEQv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #510 = VCEQv2i32
+ { 511, 5, 1, 3, "VCEQv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #511 = VCEQv4i16
+ { 512, 5, 1, 4, "VCEQv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #512 = VCEQv4i32
+ { 513, 5, 1, 4, "VCEQv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #513 = VCEQv8i16
+ { 514, 5, 1, 3, "VCEQv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #514 = VCEQv8i8
+ { 515, 4, 1, 128, "VCEQzv16i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #515 = VCEQzv16i8
+ { 516, 4, 1, 128, "VCEQzv2f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #516 = VCEQzv2f32
+ { 517, 4, 1, 128, "VCEQzv2i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #517 = VCEQzv2i32
+ { 518, 4, 1, 128, "VCEQzv4f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #518 = VCEQzv4f32
+ { 519, 4, 1, 128, "VCEQzv4i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #519 = VCEQzv4i16
+ { 520, 4, 1, 128, "VCEQzv4i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #520 = VCEQzv4i32
+ { 521, 4, 1, 128, "VCEQzv8i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #521 = VCEQzv8i16
+ { 522, 4, 1, 128, "VCEQzv8i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #522 = VCEQzv8i8
+ { 523, 5, 1, 1, "VCGEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #523 = VCGEfd
+ { 524, 5, 1, 2, "VCGEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #524 = VCGEfq
+ { 525, 5, 1, 4, "VCGEsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #525 = VCGEsv16i8
+ { 526, 5, 1, 3, "VCGEsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #526 = VCGEsv2i32
+ { 527, 5, 1, 3, "VCGEsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #527 = VCGEsv4i16
+ { 528, 5, 1, 4, "VCGEsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #528 = VCGEsv4i32
+ { 529, 5, 1, 4, "VCGEsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #529 = VCGEsv8i16
+ { 530, 5, 1, 3, "VCGEsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #530 = VCGEsv8i8
+ { 531, 5, 1, 4, "VCGEuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #531 = VCGEuv16i8
+ { 532, 5, 1, 3, "VCGEuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #532 = VCGEuv2i32
+ { 533, 5, 1, 3, "VCGEuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #533 = VCGEuv4i16
+ { 534, 5, 1, 4, "VCGEuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #534 = VCGEuv4i32
+ { 535, 5, 1, 4, "VCGEuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #535 = VCGEuv8i16
+ { 536, 5, 1, 3, "VCGEuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #536 = VCGEuv8i8
+ { 537, 4, 1, 128, "VCGEzv16i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #537 = VCGEzv16i8
+ { 538, 4, 1, 128, "VCGEzv2f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #538 = VCGEzv2f32
+ { 539, 4, 1, 128, "VCGEzv2i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #539 = VCGEzv2i32
+ { 540, 4, 1, 128, "VCGEzv4f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #540 = VCGEzv4f32
+ { 541, 4, 1, 128, "VCGEzv4i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #541 = VCGEzv4i16
+ { 542, 4, 1, 128, "VCGEzv4i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #542 = VCGEzv4i32
+ { 543, 4, 1, 128, "VCGEzv8i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #543 = VCGEzv8i16
+ { 544, 4, 1, 128, "VCGEzv8i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #544 = VCGEzv8i8
+ { 545, 5, 1, 1, "VCGTfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #545 = VCGTfd
+ { 546, 5, 1, 2, "VCGTfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #546 = VCGTfq
+ { 547, 5, 1, 4, "VCGTsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #547 = VCGTsv16i8
+ { 548, 5, 1, 3, "VCGTsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #548 = VCGTsv2i32
+ { 549, 5, 1, 3, "VCGTsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #549 = VCGTsv4i16
+ { 550, 5, 1, 4, "VCGTsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #550 = VCGTsv4i32
+ { 551, 5, 1, 4, "VCGTsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #551 = VCGTsv8i16
+ { 552, 5, 1, 3, "VCGTsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #552 = VCGTsv8i8
+ { 553, 5, 1, 4, "VCGTuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #553 = VCGTuv16i8
+ { 554, 5, 1, 3, "VCGTuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #554 = VCGTuv2i32
+ { 555, 5, 1, 3, "VCGTuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #555 = VCGTuv4i16
+ { 556, 5, 1, 4, "VCGTuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #556 = VCGTuv4i32
+ { 557, 5, 1, 4, "VCGTuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #557 = VCGTuv8i16
+ { 558, 5, 1, 3, "VCGTuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #558 = VCGTuv8i8
+ { 559, 4, 1, 128, "VCGTzv16i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #559 = VCGTzv16i8
+ { 560, 4, 1, 128, "VCGTzv2f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #560 = VCGTzv2f32
+ { 561, 4, 1, 128, "VCGTzv2i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #561 = VCGTzv2i32
+ { 562, 4, 1, 128, "VCGTzv4f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #562 = VCGTzv4f32
+ { 563, 4, 1, 128, "VCGTzv4i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #563 = VCGTzv4i16
+ { 564, 4, 1, 128, "VCGTzv4i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #564 = VCGTzv4i32
+ { 565, 4, 1, 128, "VCGTzv8i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #565 = VCGTzv8i16
+ { 566, 4, 1, 128, "VCGTzv8i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #566 = VCGTzv8i8
+ { 567, 4, 1, 128, "VCLEzv16i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #567 = VCLEzv16i8
+ { 568, 4, 1, 128, "VCLEzv2f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #568 = VCLEzv2f32
+ { 569, 4, 1, 128, "VCLEzv2i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #569 = VCLEzv2i32
+ { 570, 4, 1, 128, "VCLEzv4f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #570 = VCLEzv4f32
+ { 571, 4, 1, 128, "VCLEzv4i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #571 = VCLEzv4i16
+ { 572, 4, 1, 128, "VCLEzv4i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #572 = VCLEzv4i32
+ { 573, 4, 1, 128, "VCLEzv8i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #573 = VCLEzv8i16
+ { 574, 4, 1, 128, "VCLEzv8i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #574 = VCLEzv8i8
+ { 575, 4, 1, 8, "VCLSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #575 = VCLSv16i8
+ { 576, 4, 1, 7, "VCLSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #576 = VCLSv2i32
+ { 577, 4, 1, 7, "VCLSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #577 = VCLSv4i16
+ { 578, 4, 1, 8, "VCLSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #578 = VCLSv4i32
+ { 579, 4, 1, 8, "VCLSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #579 = VCLSv8i16
+ { 580, 4, 1, 7, "VCLSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #580 = VCLSv8i8
+ { 581, 4, 1, 128, "VCLTzv16i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #581 = VCLTzv16i8
+ { 582, 4, 1, 128, "VCLTzv2f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #582 = VCLTzv2f32
+ { 583, 4, 1, 128, "VCLTzv2i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #583 = VCLTzv2i32
+ { 584, 4, 1, 128, "VCLTzv4f32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #584 = VCLTzv4f32
+ { 585, 4, 1, 128, "VCLTzv4i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #585 = VCLTzv4i16
+ { 586, 4, 1, 128, "VCLTzv4i32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #586 = VCLTzv4i32
+ { 587, 4, 1, 128, "VCLTzv8i16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #587 = VCLTzv8i16
+ { 588, 4, 1, 128, "VCLTzv8i8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #588 = VCLTzv8i8
+ { 589, 4, 1, 8, "VCLZv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #589 = VCLZv16i8
+ { 590, 4, 1, 7, "VCLZv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #590 = VCLZv2i32
+ { 591, 4, 1, 7, "VCLZv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #591 = VCLZv4i16
+ { 592, 4, 1, 8, "VCLZv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #592 = VCLZv4i32
+ { 593, 4, 1, 8, "VCLZv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #593 = VCLZv8i16
+ { 594, 4, 1, 7, "VCLZv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #594 = VCLZv8i8
+ { 595, 4, 0, 64, "VCMPD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo65 }, // Inst #595 = VCMPD
+ { 596, 4, 0, 64, "VCMPED", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo65 }, // Inst #596 = VCMPED
+ { 597, 4, 0, 63, "VCMPES", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo66 }, // Inst #597 = VCMPES
+ { 598, 3, 0, 64, "VCMPEZD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo73 }, // Inst #598 = VCMPEZD
+ { 599, 3, 0, 63, "VCMPEZS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo74 }, // Inst #599 = VCMPEZS
+ { 600, 4, 0, 63, "VCMPS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo66 }, // Inst #600 = VCMPS
+ { 601, 3, 0, 64, "VCMPZD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo73 }, // Inst #601 = VCMPZD
+ { 602, 3, 0, 63, "VCMPZS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo74 }, // Inst #602 = VCMPZS
+ { 603, 4, 1, 7, "VCNTd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #603 = VCNTd
+ { 604, 4, 1, 8, "VCNTq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #604 = VCNTq
+ { 605, 4, 1, 66, "VCVTBHS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #605 = VCVTBHS
+ { 606, 4, 1, 66, "VCVTBSH", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #606 = VCVTBSH
+ { 607, 4, 1, 66, "VCVTDS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #607 = VCVTDS
+ { 608, 4, 1, 69, "VCVTSD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #608 = VCVTSD
+ { 609, 4, 1, 66, "VCVTTHS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #609 = VCVTTHS
+ { 610, 4, 1, 66, "VCVTTSH", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #610 = VCVTTSH
+ { 611, 4, 1, 57, "VCVTf2sd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #611 = VCVTf2sd
+ { 612, 4, 1, 57, "VCVTf2sd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #612 = VCVTf2sd_sfp
+ { 613, 4, 1, 58, "VCVTf2sq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #613 = VCVTf2sq
+ { 614, 4, 1, 57, "VCVTf2ud", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #614 = VCVTf2ud
+ { 615, 4, 1, 57, "VCVTf2ud_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #615 = VCVTf2ud_sfp
+ { 616, 4, 1, 58, "VCVTf2uq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #616 = VCVTf2uq
+ { 617, 5, 1, 57, "VCVTf2xsd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #617 = VCVTf2xsd
+ { 618, 5, 1, 58, "VCVTf2xsq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #618 = VCVTf2xsq
+ { 619, 5, 1, 57, "VCVTf2xud", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #619 = VCVTf2xud
+ { 620, 5, 1, 58, "VCVTf2xuq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #620 = VCVTf2xuq
+ { 621, 4, 1, 57, "VCVTs2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #621 = VCVTs2fd
+ { 622, 4, 1, 57, "VCVTs2fd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #622 = VCVTs2fd_sfp
+ { 623, 4, 1, 58, "VCVTs2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #623 = VCVTs2fq
+ { 624, 4, 1, 57, "VCVTu2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #624 = VCVTu2fd
+ { 625, 4, 1, 57, "VCVTu2fd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #625 = VCVTu2fd_sfp
+ { 626, 4, 1, 58, "VCVTu2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #626 = VCVTu2fq
+ { 627, 5, 1, 57, "VCVTxs2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #627 = VCVTxs2fd
+ { 628, 5, 1, 58, "VCVTxs2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #628 = VCVTxs2fq
+ { 629, 5, 1, 57, "VCVTxu2fd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #629 = VCVTxu2fd
+ { 630, 5, 1, 58, "VCVTxu2fq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #630 = VCVTxu2fq
+ { 631, 5, 1, 72, "VDIVD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #631 = VDIVD
+ { 632, 5, 1, 71, "VDIVS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #632 = VDIVS
+ { 633, 4, 1, 24, "VDUP16d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo79 }, // Inst #633 = VDUP16d
+ { 634, 4, 1, 24, "VDUP16q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo80 }, // Inst #634 = VDUP16q
+ { 635, 4, 1, 24, "VDUP32d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo79 }, // Inst #635 = VDUP32d
+ { 636, 4, 1, 24, "VDUP32q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo80 }, // Inst #636 = VDUP32q
+ { 637, 4, 1, 24, "VDUP8d", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo79 }, // Inst #637 = VDUP8d
+ { 638, 4, 1, 24, "VDUP8q", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo80 }, // Inst #638 = VDUP8q
+ { 639, 5, 1, 21, "VDUPLN16d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #639 = VDUPLN16d
+ { 640, 5, 1, 21, "VDUPLN16q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #640 = VDUPLN16q
+ { 641, 5, 1, 21, "VDUPLN32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #641 = VDUPLN32d
+ { 642, 5, 1, 21, "VDUPLN32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #642 = VDUPLN32q
+ { 643, 5, 1, 21, "VDUPLN8d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #643 = VDUPLN8d
+ { 644, 5, 1, 21, "VDUPLN8q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #644 = VDUPLN8q
+ { 645, 5, 1, 21, "VDUPLNfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #645 = VDUPLNfd
+ { 646, 5, 1, 21, "VDUPLNfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #646 = VDUPLNfq
+ { 647, 4, 1, 24, "VDUPfd", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo79 }, // Inst #647 = VDUPfd
+ { 648, 4, 1, 21, "VDUPfdf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #648 = VDUPfdf
+ { 649, 4, 1, 24, "VDUPfq", 0|(1<<TID::Predicable), 0|(3<<4)|(27<<9), NULL, NULL, NULL, OperandInfo80 }, // Inst #649 = VDUPfq
+ { 650, 4, 1, 21, "VDUPfqf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo82 }, // Inst #650 = VDUPfqf
+ { 651, 5, 1, 5, "VEORd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #651 = VEORd
+ { 652, 5, 1, 6, "VEORq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #652 = VEORq
+ { 653, 6, 1, 9, "VEXTd16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #653 = VEXTd16
+ { 654, 6, 1, 9, "VEXTd32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #654 = VEXTd32
+ { 655, 6, 1, 9, "VEXTd8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #655 = VEXTd8
+ { 656, 6, 1, 9, "VEXTdf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo83 }, // Inst #656 = VEXTdf
+ { 657, 6, 1, 10, "VEXTq16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #657 = VEXTq16
+ { 658, 6, 1, 10, "VEXTq32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #658 = VEXTq32
+ { 659, 6, 1, 10, "VEXTq8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #659 = VEXTq8
+ { 660, 6, 1, 10, "VEXTqf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo84 }, // Inst #660 = VEXTqf
+ { 661, 5, 1, 28, "VGETLNi32", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo85 }, // Inst #661 = VGETLNi32
+ { 662, 5, 1, 28, "VGETLNs16", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo85 }, // Inst #662 = VGETLNs16
+ { 663, 5, 1, 28, "VGETLNs8", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo85 }, // Inst #663 = VGETLNs8
+ { 664, 5, 1, 28, "VGETLNu16", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo85 }, // Inst #664 = VGETLNu16
+ { 665, 5, 1, 28, "VGETLNu8", 0|(1<<TID::Predicable), 0|(3<<4)|(25<<9), NULL, NULL, NULL, OperandInfo85 }, // Inst #665 = VGETLNu8
+ { 666, 5, 1, 4, "VHADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #666 = VHADDsv16i8
+ { 667, 5, 1, 3, "VHADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #667 = VHADDsv2i32
+ { 668, 5, 1, 3, "VHADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #668 = VHADDsv4i16
+ { 669, 5, 1, 4, "VHADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #669 = VHADDsv4i32
+ { 670, 5, 1, 4, "VHADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #670 = VHADDsv8i16
+ { 671, 5, 1, 3, "VHADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #671 = VHADDsv8i8
+ { 672, 5, 1, 4, "VHADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #672 = VHADDuv16i8
+ { 673, 5, 1, 3, "VHADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #673 = VHADDuv2i32
+ { 674, 5, 1, 3, "VHADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #674 = VHADDuv4i16
+ { 675, 5, 1, 4, "VHADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #675 = VHADDuv4i32
+ { 676, 5, 1, 4, "VHADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #676 = VHADDuv8i16
+ { 677, 5, 1, 3, "VHADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #677 = VHADDuv8i8
+ { 678, 5, 1, 4, "VHSUBsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #678 = VHSUBsv16i8
+ { 679, 5, 1, 3, "VHSUBsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #679 = VHSUBsv2i32
+ { 680, 5, 1, 3, "VHSUBsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #680 = VHSUBsv4i16
+ { 681, 5, 1, 4, "VHSUBsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #681 = VHSUBsv4i32
+ { 682, 5, 1, 4, "VHSUBsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #682 = VHSUBsv8i16
+ { 683, 5, 1, 3, "VHSUBsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #683 = VHSUBsv8i8
+ { 684, 5, 1, 4, "VHSUBuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #684 = VHSUBuv16i8
+ { 685, 5, 1, 3, "VHSUBuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #685 = VHSUBuv2i32
+ { 686, 5, 1, 3, "VHSUBuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #686 = VHSUBuv4i16
+ { 687, 5, 1, 4, "VHSUBuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #687 = VHSUBuv4i32
+ { 688, 5, 1, 4, "VHSUBuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #688 = VHSUBuv8i16
+ { 689, 5, 1, 3, "VHSUBuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #689 = VHSUBuv8i8
+ { 690, 7, 1, 11, "VLD1d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #690 = VLD1d16
+ { 691, 10, 4, 11, "VLD1d16Q", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #691 = VLD1d16Q
+ { 692, 9, 3, 11, "VLD1d16T", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #692 = VLD1d16T
+ { 693, 7, 1, 11, "VLD1d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #693 = VLD1d32
+ { 694, 10, 4, 11, "VLD1d32Q", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #694 = VLD1d32Q
+ { 695, 9, 3, 11, "VLD1d32T", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #695 = VLD1d32T
+ { 696, 7, 1, 11, "VLD1d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #696 = VLD1d64
+ { 697, 7, 1, 11, "VLD1d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #697 = VLD1d8
+ { 698, 10, 4, 11, "VLD1d8Q", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #698 = VLD1d8Q
+ { 699, 9, 3, 11, "VLD1d8T", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #699 = VLD1d8T
+ { 700, 7, 1, 11, "VLD1df", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo86 }, // Inst #700 = VLD1df
+ { 701, 7, 1, 11, "VLD1q16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #701 = VLD1q16
+ { 702, 7, 1, 11, "VLD1q32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #702 = VLD1q32
+ { 703, 7, 1, 11, "VLD1q64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #703 = VLD1q64
+ { 704, 7, 1, 11, "VLD1q8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #704 = VLD1q8
+ { 705, 7, 1, 11, "VLD1qf", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo89 }, // Inst #705 = VLD1qf
+ { 706, 11, 2, 12, "VLD2LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #706 = VLD2LNd16
+ { 707, 11, 2, 12, "VLD2LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #707 = VLD2LNd32
+ { 708, 11, 2, 12, "VLD2LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #708 = VLD2LNd8
+ { 709, 11, 2, 12, "VLD2LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #709 = VLD2LNq16a
+ { 710, 11, 2, 12, "VLD2LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #710 = VLD2LNq16b
+ { 711, 11, 2, 12, "VLD2LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #711 = VLD2LNq32a
+ { 712, 11, 2, 12, "VLD2LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo90 }, // Inst #712 = VLD2LNq32b
+ { 713, 8, 2, 12, "VLD2d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #713 = VLD2d16
+ { 714, 8, 2, 12, "VLD2d16D", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #714 = VLD2d16D
+ { 715, 8, 2, 12, "VLD2d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #715 = VLD2d32
+ { 716, 8, 2, 12, "VLD2d32D", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #716 = VLD2d32D
+ { 717, 8, 2, 11, "VLD2d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #717 = VLD2d64
+ { 718, 8, 2, 12, "VLD2d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #718 = VLD2d8
+ { 719, 8, 2, 12, "VLD2d8D", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo91 }, // Inst #719 = VLD2d8D
+ { 720, 10, 4, 12, "VLD2q16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #720 = VLD2q16
+ { 721, 10, 4, 12, "VLD2q32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #721 = VLD2q32
+ { 722, 10, 4, 12, "VLD2q8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #722 = VLD2q8
+ { 723, 13, 3, 13, "VLD3LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #723 = VLD3LNd16
+ { 724, 13, 3, 13, "VLD3LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #724 = VLD3LNd32
+ { 725, 13, 3, 13, "VLD3LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #725 = VLD3LNd8
+ { 726, 13, 3, 13, "VLD3LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #726 = VLD3LNq16a
+ { 727, 13, 3, 13, "VLD3LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #727 = VLD3LNq16b
+ { 728, 13, 3, 13, "VLD3LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #728 = VLD3LNq32a
+ { 729, 13, 3, 13, "VLD3LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo92 }, // Inst #729 = VLD3LNq32b
+ { 730, 9, 3, 13, "VLD3d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #730 = VLD3d16
+ { 731, 9, 3, 13, "VLD3d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #731 = VLD3d32
+ { 732, 9, 3, 11, "VLD3d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #732 = VLD3d64
+ { 733, 9, 3, 13, "VLD3d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo88 }, // Inst #733 = VLD3d8
+ { 734, 10, 4, 13, "VLD3q16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #734 = VLD3q16a
+ { 735, 10, 4, 13, "VLD3q16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #735 = VLD3q16b
+ { 736, 10, 4, 13, "VLD3q32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #736 = VLD3q32a
+ { 737, 10, 4, 13, "VLD3q32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #737 = VLD3q32b
+ { 738, 10, 4, 13, "VLD3q8a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #738 = VLD3q8a
+ { 739, 10, 4, 13, "VLD3q8b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo93 }, // Inst #739 = VLD3q8b
+ { 740, 15, 4, 14, "VLD4LNd16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #740 = VLD4LNd16
+ { 741, 15, 4, 14, "VLD4LNd32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #741 = VLD4LNd32
+ { 742, 15, 4, 14, "VLD4LNd8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #742 = VLD4LNd8
+ { 743, 15, 4, 14, "VLD4LNq16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #743 = VLD4LNq16a
+ { 744, 15, 4, 14, "VLD4LNq16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #744 = VLD4LNq16b
+ { 745, 15, 4, 14, "VLD4LNq32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #745 = VLD4LNq32a
+ { 746, 15, 4, 14, "VLD4LNq32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo94 }, // Inst #746 = VLD4LNq32b
+ { 747, 10, 4, 14, "VLD4d16", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #747 = VLD4d16
+ { 748, 10, 4, 14, "VLD4d32", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #748 = VLD4d32
+ { 749, 10, 4, 11, "VLD4d64", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #749 = VLD4d64
+ { 750, 10, 4, 14, "VLD4d8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo87 }, // Inst #750 = VLD4d8
+ { 751, 11, 5, 14, "VLD4q16a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #751 = VLD4q16a
+ { 752, 11, 5, 14, "VLD4q16b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #752 = VLD4q16b
+ { 753, 11, 5, 14, "VLD4q32a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #753 = VLD4q32a
+ { 754, 11, 5, 14, "VLD4q32b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #754 = VLD4q32b
+ { 755, 11, 5, 14, "VLD4q8a", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #755 = VLD4q8a
+ { 756, 11, 5, 14, "VLD4q8b", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo95 }, // Inst #756 = VLD4q8b
+ { 757, 5, 0, 75, "VLDMD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|5|(3<<4)|(21<<9)|(3<<17), NULL, NULL, NULL, OperandInfo35 }, // Inst #757 = VLDMD
+ { 758, 5, 0, 75, "VLDMS", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|5|(3<<4)|(21<<9)|(1<<17), NULL, NULL, NULL, OperandInfo35 }, // Inst #758 = VLDMS
+ { 759, 5, 1, 74, "VLDRD", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|5|(3<<4)|(20<<9)|(3<<17), NULL, NULL, NULL, OperandInfo96 }, // Inst #759 = VLDRD
+ { 760, 5, 1, 75, "VLDRQ", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|4|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo97 }, // Inst #760 = VLDRQ
+ { 761, 5, 1, 73, "VLDRS", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|5|(3<<4)|(20<<9)|(1<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #761 = VLDRS
+ { 762, 5, 1, 1, "VMAXfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #762 = VMAXfd
+ { 763, 5, 1, 1, "VMAXfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #763 = VMAXfd_sfp
+ { 764, 5, 1, 2, "VMAXfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #764 = VMAXfq
+ { 765, 5, 1, 4, "VMAXsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #765 = VMAXsv16i8
+ { 766, 5, 1, 3, "VMAXsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #766 = VMAXsv2i32
+ { 767, 5, 1, 3, "VMAXsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #767 = VMAXsv4i16
+ { 768, 5, 1, 4, "VMAXsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #768 = VMAXsv4i32
+ { 769, 5, 1, 4, "VMAXsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #769 = VMAXsv8i16
+ { 770, 5, 1, 3, "VMAXsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #770 = VMAXsv8i8
+ { 771, 5, 1, 4, "VMAXuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #771 = VMAXuv16i8
+ { 772, 5, 1, 3, "VMAXuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #772 = VMAXuv2i32
+ { 773, 5, 1, 3, "VMAXuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #773 = VMAXuv4i16
+ { 774, 5, 1, 4, "VMAXuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #774 = VMAXuv4i32
+ { 775, 5, 1, 4, "VMAXuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #775 = VMAXuv8i16
+ { 776, 5, 1, 3, "VMAXuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #776 = VMAXuv8i8
+ { 777, 5, 1, 1, "VMINfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #777 = VMINfd
+ { 778, 5, 1, 1, "VMINfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #778 = VMINfd_sfp
+ { 779, 5, 1, 2, "VMINfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #779 = VMINfq
+ { 780, 5, 1, 4, "VMINsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #780 = VMINsv16i8
+ { 781, 5, 1, 3, "VMINsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #781 = VMINsv2i32
+ { 782, 5, 1, 3, "VMINsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #782 = VMINsv4i16
+ { 783, 5, 1, 4, "VMINsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #783 = VMINsv4i32
+ { 784, 5, 1, 4, "VMINsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #784 = VMINsv8i16
+ { 785, 5, 1, 3, "VMINsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #785 = VMINsv8i8
+ { 786, 5, 1, 4, "VMINuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #786 = VMINuv16i8
+ { 787, 5, 1, 3, "VMINuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #787 = VMINuv2i32
+ { 788, 5, 1, 3, "VMINuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #788 = VMINuv4i16
+ { 789, 5, 1, 4, "VMINuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #789 = VMINuv4i32
+ { 790, 5, 1, 4, "VMINuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #790 = VMINuv8i16
+ { 791, 5, 1, 3, "VMINuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #791 = VMINuv8i8
+ { 792, 6, 1, 77, "VMLAD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #792 = VMLAD
+ { 793, 7, 1, 19, "VMLALslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #793 = VMLALslsv2i32
+ { 794, 7, 1, 17, "VMLALslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #794 = VMLALslsv4i16
+ { 795, 7, 1, 19, "VMLALsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #795 = VMLALsluv2i32
+ { 796, 7, 1, 17, "VMLALsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #796 = VMLALsluv4i16
+ { 797, 6, 1, 17, "VMLALsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #797 = VMLALsv2i64
+ { 798, 6, 1, 17, "VMLALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #798 = VMLALsv4i32
+ { 799, 6, 1, 17, "VMLALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #799 = VMLALsv8i16
+ { 800, 6, 1, 17, "VMLALuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #800 = VMLALuv2i64
+ { 801, 6, 1, 17, "VMLALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #801 = VMLALuv4i32
+ { 802, 6, 1, 17, "VMLALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #802 = VMLALuv8i16
+ { 803, 6, 1, 76, "VMLAS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #803 = VMLAS
+ { 804, 6, 1, 15, "VMLAfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #804 = VMLAfd
+ { 805, 6, 1, 16, "VMLAfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #805 = VMLAfq
+ { 806, 7, 1, 15, "VMLAslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #806 = VMLAslfd
+ { 807, 7, 1, 16, "VMLAslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #807 = VMLAslfq
+ { 808, 7, 1, 19, "VMLAslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #808 = VMLAslv2i32
+ { 809, 7, 1, 17, "VMLAslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #809 = VMLAslv4i16
+ { 810, 7, 1, 20, "VMLAslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #810 = VMLAslv4i32
+ { 811, 7, 1, 18, "VMLAslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #811 = VMLAslv8i16
+ { 812, 6, 1, 18, "VMLAv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #812 = VMLAv16i8
+ { 813, 6, 1, 19, "VMLAv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #813 = VMLAv2i32
+ { 814, 6, 1, 17, "VMLAv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #814 = VMLAv4i16
+ { 815, 6, 1, 20, "VMLAv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #815 = VMLAv4i32
+ { 816, 6, 1, 18, "VMLAv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #816 = VMLAv8i16
+ { 817, 6, 1, 17, "VMLAv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #817 = VMLAv8i8
+ { 818, 6, 1, 77, "VMLSD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #818 = VMLSD
+ { 819, 7, 1, 19, "VMLSLslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #819 = VMLSLslsv2i32
+ { 820, 7, 1, 17, "VMLSLslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #820 = VMLSLslsv4i16
+ { 821, 7, 1, 19, "VMLSLsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #821 = VMLSLsluv2i32
+ { 822, 7, 1, 17, "VMLSLsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #822 = VMLSLsluv4i16
+ { 823, 6, 1, 17, "VMLSLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #823 = VMLSLsv2i64
+ { 824, 6, 1, 17, "VMLSLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #824 = VMLSLsv4i32
+ { 825, 6, 1, 17, "VMLSLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #825 = VMLSLsv8i16
+ { 826, 6, 1, 17, "VMLSLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #826 = VMLSLuv2i64
+ { 827, 6, 1, 17, "VMLSLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #827 = VMLSLuv4i32
+ { 828, 6, 1, 17, "VMLSLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #828 = VMLSLuv8i16
+ { 829, 6, 1, 76, "VMLSS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #829 = VMLSS
+ { 830, 6, 1, 15, "VMLSfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #830 = VMLSfd
+ { 831, 6, 1, 16, "VMLSfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #831 = VMLSfq
+ { 832, 7, 1, 15, "VMLSslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #832 = VMLSslfd
+ { 833, 7, 1, 16, "VMLSslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #833 = VMLSslfq
+ { 834, 7, 1, 19, "VMLSslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo102 }, // Inst #834 = VMLSslv2i32
+ { 835, 7, 1, 17, "VMLSslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo104 }, // Inst #835 = VMLSslv4i16
+ { 836, 7, 1, 20, "VMLSslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo103 }, // Inst #836 = VMLSslv4i32
+ { 837, 7, 1, 18, "VMLSslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo105 }, // Inst #837 = VMLSslv8i16
+ { 838, 6, 1, 18, "VMLSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #838 = VMLSv16i8
+ { 839, 6, 1, 19, "VMLSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #839 = VMLSv2i32
+ { 840, 6, 1, 17, "VMLSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #840 = VMLSv4i16
+ { 841, 6, 1, 20, "VMLSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #841 = VMLSv4i32
+ { 842, 6, 1, 18, "VMLSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo60 }, // Inst #842 = VMLSv8i16
+ { 843, 6, 1, 17, "VMLSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #843 = VMLSv8i8
+ { 844, 4, 1, 87, "VMOVD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #844 = VMOVD
+ { 845, 5, 1, 23, "VMOVDRR", 0|(1<<TID::Predicable), 0|(3<<4)|(19<<9)|(1<<17), NULL, NULL, NULL, OperandInfo106 }, // Inst #845 = VMOVDRR
+ { 846, 5, 1, 87, "VMOVDcc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #846 = VMOVDcc
+ { 847, 4, 1, 21, "VMOVDneon", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #847 = VMOVDneon
+ { 848, 4, 1, 38, "VMOVLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #848 = VMOVLsv2i64
+ { 849, 4, 1, 38, "VMOVLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #849 = VMOVLsv4i32
+ { 850, 4, 1, 38, "VMOVLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #850 = VMOVLsv8i16
+ { 851, 4, 1, 38, "VMOVLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #851 = VMOVLuv2i64
+ { 852, 4, 1, 38, "VMOVLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #852 = VMOVLuv4i32
+ { 853, 4, 1, 38, "VMOVLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo108 }, // Inst #853 = VMOVLuv8i16
+ { 854, 4, 1, 21, "VMOVNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #854 = VMOVNv2i32
+ { 855, 4, 1, 21, "VMOVNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #855 = VMOVNv4i16
+ { 856, 4, 1, 21, "VMOVNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #856 = VMOVNv8i8
+ { 857, 4, 1, 21, "VMOVQ", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #857 = VMOVQ
+ { 858, 5, 2, 22, "VMOVRRD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(17<<9)|(1<<17), NULL, NULL, NULL, OperandInfo110 }, // Inst #858 = VMOVRRD
+ { 859, 6, 2, 22, "VMOVRRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(17<<9)|(1<<17), NULL, NULL, NULL, OperandInfo111 }, // Inst #859 = VMOVRRS
+ { 860, 4, 1, 28, "VMOVRS", 0|(1<<TID::Predicable), 0|(3<<4)|(16<<9)|(1<<17), NULL, NULL, NULL, OperandInfo112 }, // Inst #860 = VMOVRS
+ { 861, 4, 1, 86, "VMOVS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #861 = VMOVS
+ { 862, 4, 1, 24, "VMOVSR", 0|(1<<TID::Predicable), 0|(3<<4)|(18<<9)|(1<<17), NULL, NULL, NULL, OperandInfo113 }, // Inst #862 = VMOVSR
+ { 863, 6, 2, 23, "VMOVSRR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(19<<9)|(1<<17), NULL, NULL, NULL, OperandInfo114 }, // Inst #863 = VMOVSRR
+ { 864, 5, 1, 86, "VMOVScc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #864 = VMOVScc
+ { 865, 4, 1, 26, "VMOVv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #865 = VMOVv16i8
+ { 866, 4, 1, 26, "VMOVv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo29 }, // Inst #866 = VMOVv1i64
+ { 867, 4, 1, 26, "VMOVv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo29 }, // Inst #867 = VMOVv2i32
+ { 868, 4, 1, 26, "VMOVv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #868 = VMOVv2i64
+ { 869, 4, 1, 26, "VMOVv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo29 }, // Inst #869 = VMOVv4i16
+ { 870, 4, 1, 26, "VMOVv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #870 = VMOVv4i32
+ { 871, 4, 1, 26, "VMOVv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo116 }, // Inst #871 = VMOVv8i16
+ { 872, 4, 1, 26, "VMOVv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo29 }, // Inst #872 = VMOVv8i8
+ { 873, 3, 1, 82, "VMRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(22<<9)|(1<<17), ImplicitList5, NULL, NULL, OperandInfo21 }, // Inst #873 = VMRS
+ { 874, 3, 0, 82, "VMSR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(22<<9)|(1<<17), NULL, ImplicitList5, NULL, OperandInfo21 }, // Inst #874 = VMSR
+ { 875, 5, 1, 79, "VMULD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #875 = VMULD
+ { 876, 5, 1, 29, "VMULLp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #876 = VMULLp
+ { 877, 6, 1, 29, "VMULLslsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #877 = VMULLslsv2i32
+ { 878, 6, 1, 29, "VMULLslsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #878 = VMULLslsv4i16
+ { 879, 6, 1, 29, "VMULLsluv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #879 = VMULLsluv2i32
+ { 880, 6, 1, 29, "VMULLsluv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #880 = VMULLsluv4i16
+ { 881, 5, 1, 29, "VMULLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #881 = VMULLsv2i64
+ { 882, 5, 1, 29, "VMULLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #882 = VMULLsv4i32
+ { 883, 5, 1, 29, "VMULLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #883 = VMULLsv8i16
+ { 884, 5, 1, 29, "VMULLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #884 = VMULLuv2i64
+ { 885, 5, 1, 29, "VMULLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #885 = VMULLuv4i32
+ { 886, 5, 1, 29, "VMULLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #886 = VMULLuv8i16
+ { 887, 5, 1, 78, "VMULS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #887 = VMULS
+ { 888, 5, 1, 1, "VMULfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #888 = VMULfd
+ { 889, 5, 1, 1, "VMULfd_sfp", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #889 = VMULfd_sfp
+ { 890, 5, 1, 2, "VMULfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #890 = VMULfq
+ { 891, 5, 1, 29, "VMULpd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #891 = VMULpd
+ { 892, 5, 1, 30, "VMULpq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #892 = VMULpq
+ { 893, 6, 1, 1, "VMULslfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #893 = VMULslfd
+ { 894, 6, 1, 2, "VMULslfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #894 = VMULslfq
+ { 895, 6, 1, 31, "VMULslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #895 = VMULslv2i32
+ { 896, 6, 1, 29, "VMULslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #896 = VMULslv4i16
+ { 897, 6, 1, 32, "VMULslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #897 = VMULslv4i32
+ { 898, 6, 1, 30, "VMULslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo122 }, // Inst #898 = VMULslv8i16
+ { 899, 5, 1, 30, "VMULv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #899 = VMULv16i8
+ { 900, 5, 1, 31, "VMULv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #900 = VMULv2i32
+ { 901, 5, 1, 29, "VMULv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #901 = VMULv4i16
+ { 902, 5, 1, 32, "VMULv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #902 = VMULv4i32
+ { 903, 5, 1, 30, "VMULv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #903 = VMULv8i16
+ { 904, 5, 1, 29, "VMULv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #904 = VMULv8i8
+ { 905, 4, 1, 44, "VMVNd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #905 = VMVNd
+ { 906, 4, 1, 44, "VMVNq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #906 = VMVNq
+ { 907, 4, 1, 87, "VNEGD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #907 = VNEGD
+ { 908, 5, 1, 87, "VNEGDcc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #908 = VNEGDcc
+ { 909, 4, 1, 86, "VNEGS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #909 = VNEGS
+ { 910, 5, 1, 86, "VNEGScc", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo115 }, // Inst #910 = VNEGScc
+ { 911, 4, 1, 58, "VNEGf32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #911 = VNEGf32q
+ { 912, 4, 1, 57, "VNEGfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #912 = VNEGfd
+ { 913, 4, 1, 57, "VNEGfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo67 }, // Inst #913 = VNEGfd_sfp
+ { 914, 4, 1, 44, "VNEGs16d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #914 = VNEGs16d
+ { 915, 4, 1, 44, "VNEGs16q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #915 = VNEGs16q
+ { 916, 4, 1, 44, "VNEGs32d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #916 = VNEGs32d
+ { 917, 4, 1, 44, "VNEGs32q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #917 = VNEGs32q
+ { 918, 4, 1, 44, "VNEGs8d", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #918 = VNEGs8d
+ { 919, 4, 1, 44, "VNEGs8q", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #919 = VNEGs8q
+ { 920, 6, 1, 77, "VNMLAD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #920 = VNMLAD
+ { 921, 6, 1, 76, "VNMLAS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #921 = VNMLAS
+ { 922, 6, 1, 77, "VNMLSD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #922 = VNMLSD
+ { 923, 6, 1, 76, "VNMLSS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo101 }, // Inst #923 = VNMLSS
+ { 924, 5, 1, 79, "VNMULD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #924 = VNMULD
+ { 925, 5, 1, 78, "VNMULS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #925 = VNMULS
+ { 926, 5, 1, 5, "VORNd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #926 = VORNd
+ { 927, 5, 1, 6, "VORNq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #927 = VORNq
+ { 928, 5, 1, 5, "VORRd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #928 = VORRd
+ { 929, 5, 1, 6, "VORRq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #929 = VORRq
+ { 930, 5, 1, 34, "VPADALsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #930 = VPADALsv16i8
+ { 931, 5, 1, 33, "VPADALsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #931 = VPADALsv2i32
+ { 932, 5, 1, 33, "VPADALsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #932 = VPADALsv4i16
+ { 933, 5, 1, 34, "VPADALsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #933 = VPADALsv4i32
+ { 934, 5, 1, 34, "VPADALsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #934 = VPADALsv8i16
+ { 935, 5, 1, 33, "VPADALsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #935 = VPADALsv8i8
+ { 936, 5, 1, 34, "VPADALuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #936 = VPADALuv16i8
+ { 937, 5, 1, 33, "VPADALuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #937 = VPADALuv2i32
+ { 938, 5, 1, 33, "VPADALuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #938 = VPADALuv4i16
+ { 939, 5, 1, 34, "VPADALuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #939 = VPADALuv4i32
+ { 940, 5, 1, 34, "VPADALuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo123 }, // Inst #940 = VPADALuv8i16
+ { 941, 5, 1, 33, "VPADALuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo107 }, // Inst #941 = VPADALuv8i8
+ { 942, 4, 1, 44, "VPADDLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #942 = VPADDLsv16i8
+ { 943, 4, 1, 44, "VPADDLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #943 = VPADDLsv2i32
+ { 944, 4, 1, 44, "VPADDLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #944 = VPADDLsv4i16
+ { 945, 4, 1, 44, "VPADDLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #945 = VPADDLsv4i32
+ { 946, 4, 1, 44, "VPADDLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #946 = VPADDLsv8i16
+ { 947, 4, 1, 44, "VPADDLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #947 = VPADDLsv8i8
+ { 948, 4, 1, 44, "VPADDLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #948 = VPADDLuv16i8
+ { 949, 4, 1, 44, "VPADDLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #949 = VPADDLuv2i32
+ { 950, 4, 1, 44, "VPADDLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #950 = VPADDLuv4i16
+ { 951, 4, 1, 44, "VPADDLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #951 = VPADDLuv4i32
+ { 952, 4, 1, 44, "VPADDLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #952 = VPADDLuv8i16
+ { 953, 4, 1, 44, "VPADDLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #953 = VPADDLuv8i8
+ { 954, 5, 1, 1, "VPADDf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #954 = VPADDf
+ { 955, 5, 1, 5, "VPADDi16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #955 = VPADDi16
+ { 956, 5, 1, 5, "VPADDi32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #956 = VPADDi32
+ { 957, 5, 1, 5, "VPADDi8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #957 = VPADDi8
+ { 958, 5, 1, 3, "VPMAXf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #958 = VPMAXf
+ { 959, 5, 1, 3, "VPMAXs16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #959 = VPMAXs16
+ { 960, 5, 1, 3, "VPMAXs32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #960 = VPMAXs32
+ { 961, 5, 1, 3, "VPMAXs8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #961 = VPMAXs8
+ { 962, 5, 1, 3, "VPMAXu16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #962 = VPMAXu16
+ { 963, 5, 1, 3, "VPMAXu32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #963 = VPMAXu32
+ { 964, 5, 1, 3, "VPMAXu8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #964 = VPMAXu8
+ { 965, 5, 1, 3, "VPMINf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #965 = VPMINf
+ { 966, 5, 1, 3, "VPMINs16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #966 = VPMINs16
+ { 967, 5, 1, 3, "VPMINs32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #967 = VPMINs32
+ { 968, 5, 1, 3, "VPMINs8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #968 = VPMINs8
+ { 969, 5, 1, 3, "VPMINu16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #969 = VPMINu16
+ { 970, 5, 1, 3, "VPMINu32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #970 = VPMINu32
+ { 971, 5, 1, 3, "VPMINu8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #971 = VPMINu8
+ { 972, 4, 1, 39, "VQABSv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #972 = VQABSv16i8
+ { 973, 4, 1, 38, "VQABSv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #973 = VQABSv2i32
+ { 974, 4, 1, 38, "VQABSv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #974 = VQABSv4i16
+ { 975, 4, 1, 39, "VQABSv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #975 = VQABSv4i32
+ { 976, 4, 1, 39, "VQABSv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #976 = VQABSv8i16
+ { 977, 4, 1, 38, "VQABSv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #977 = VQABSv8i8
+ { 978, 5, 1, 4, "VQADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #978 = VQADDsv16i8
+ { 979, 5, 1, 3, "VQADDsv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #979 = VQADDsv1i64
+ { 980, 5, 1, 3, "VQADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #980 = VQADDsv2i32
+ { 981, 5, 1, 4, "VQADDsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #981 = VQADDsv2i64
+ { 982, 5, 1, 3, "VQADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #982 = VQADDsv4i16
+ { 983, 5, 1, 4, "VQADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #983 = VQADDsv4i32
+ { 984, 5, 1, 4, "VQADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #984 = VQADDsv8i16
+ { 985, 5, 1, 3, "VQADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #985 = VQADDsv8i8
+ { 986, 5, 1, 4, "VQADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #986 = VQADDuv16i8
+ { 987, 5, 1, 3, "VQADDuv1i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #987 = VQADDuv1i64
+ { 988, 5, 1, 3, "VQADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #988 = VQADDuv2i32
+ { 989, 5, 1, 4, "VQADDuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #989 = VQADDuv2i64
+ { 990, 5, 1, 3, "VQADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #990 = VQADDuv4i16
+ { 991, 5, 1, 4, "VQADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #991 = VQADDuv4i32
+ { 992, 5, 1, 4, "VQADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #992 = VQADDuv8i16
+ { 993, 5, 1, 3, "VQADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #993 = VQADDuv8i8
+ { 994, 7, 1, 19, "VQDMLALslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #994 = VQDMLALslv2i32
+ { 995, 7, 1, 17, "VQDMLALslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #995 = VQDMLALslv4i16
+ { 996, 6, 1, 17, "VQDMLALv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #996 = VQDMLALv2i64
+ { 997, 6, 1, 17, "VQDMLALv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #997 = VQDMLALv4i32
+ { 998, 7, 1, 19, "VQDMLSLslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo99 }, // Inst #998 = VQDMLSLslv2i32
+ { 999, 7, 1, 17, "VQDMLSLslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo100 }, // Inst #999 = VQDMLSLslv4i16
+ { 1000, 6, 1, 17, "VQDMLSLv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #1000 = VQDMLSLv2i64
+ { 1001, 6, 1, 17, "VQDMLSLv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo59 }, // Inst #1001 = VQDMLSLv4i32
+ { 1002, 6, 1, 31, "VQDMULHslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1002 = VQDMULHslv2i32
+ { 1003, 6, 1, 29, "VQDMULHslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #1003 = VQDMULHslv4i16
+ { 1004, 6, 1, 32, "VQDMULHslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #1004 = VQDMULHslv4i32
+ { 1005, 6, 1, 30, "VQDMULHslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo122 }, // Inst #1005 = VQDMULHslv8i16
+ { 1006, 5, 1, 31, "VQDMULHv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1006 = VQDMULHv2i32
+ { 1007, 5, 1, 29, "VQDMULHv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1007 = VQDMULHv4i16
+ { 1008, 5, 1, 32, "VQDMULHv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1008 = VQDMULHv4i32
+ { 1009, 5, 1, 30, "VQDMULHv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1009 = VQDMULHv8i16
+ { 1010, 6, 1, 29, "VQDMULLslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo117 }, // Inst #1010 = VQDMULLslv2i32
+ { 1011, 6, 1, 29, "VQDMULLslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo118 }, // Inst #1011 = VQDMULLslv4i16
+ { 1012, 5, 1, 29, "VQDMULLv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1012 = VQDMULLv2i64
+ { 1013, 5, 1, 29, "VQDMULLv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1013 = VQDMULLv4i32
+ { 1014, 4, 1, 38, "VQMOVNsuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1014 = VQMOVNsuv2i32
+ { 1015, 4, 1, 38, "VQMOVNsuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1015 = VQMOVNsuv4i16
+ { 1016, 4, 1, 38, "VQMOVNsuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1016 = VQMOVNsuv8i8
+ { 1017, 4, 1, 38, "VQMOVNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1017 = VQMOVNsv2i32
+ { 1018, 4, 1, 38, "VQMOVNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1018 = VQMOVNsv4i16
+ { 1019, 4, 1, 38, "VQMOVNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1019 = VQMOVNsv8i8
+ { 1020, 4, 1, 38, "VQMOVNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1020 = VQMOVNuv2i32
+ { 1021, 4, 1, 38, "VQMOVNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1021 = VQMOVNuv4i16
+ { 1022, 4, 1, 38, "VQMOVNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo109 }, // Inst #1022 = VQMOVNuv8i8
+ { 1023, 4, 1, 39, "VQNEGv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1023 = VQNEGv16i8
+ { 1024, 4, 1, 38, "VQNEGv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1024 = VQNEGv2i32
+ { 1025, 4, 1, 38, "VQNEGv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1025 = VQNEGv4i16
+ { 1026, 4, 1, 39, "VQNEGv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1026 = VQNEGv4i32
+ { 1027, 4, 1, 39, "VQNEGv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1027 = VQNEGv8i16
+ { 1028, 4, 1, 38, "VQNEGv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1028 = VQNEGv8i8
+ { 1029, 6, 1, 31, "VQRDMULHslv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo119 }, // Inst #1029 = VQRDMULHslv2i32
+ { 1030, 6, 1, 29, "VQRDMULHslv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo121 }, // Inst #1030 = VQRDMULHslv4i16
+ { 1031, 6, 1, 32, "VQRDMULHslv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo120 }, // Inst #1031 = VQRDMULHslv4i32
+ { 1032, 6, 1, 30, "VQRDMULHslv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo122 }, // Inst #1032 = VQRDMULHslv8i16
+ { 1033, 5, 1, 31, "VQRDMULHv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1033 = VQRDMULHv2i32
+ { 1034, 5, 1, 29, "VQRDMULHv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1034 = VQRDMULHv4i16
+ { 1035, 5, 1, 32, "VQRDMULHv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1035 = VQRDMULHv4i32
+ { 1036, 5, 1, 30, "VQRDMULHv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1036 = VQRDMULHv8i16
+ { 1037, 5, 1, 43, "VQRSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1037 = VQRSHLsv16i8
+ { 1038, 5, 1, 42, "VQRSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1038 = VQRSHLsv1i64
+ { 1039, 5, 1, 42, "VQRSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1039 = VQRSHLsv2i32
+ { 1040, 5, 1, 43, "VQRSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1040 = VQRSHLsv2i64
+ { 1041, 5, 1, 42, "VQRSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1041 = VQRSHLsv4i16
+ { 1042, 5, 1, 43, "VQRSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1042 = VQRSHLsv4i32
+ { 1043, 5, 1, 43, "VQRSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1043 = VQRSHLsv8i16
+ { 1044, 5, 1, 42, "VQRSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1044 = VQRSHLsv8i8
+ { 1045, 5, 1, 43, "VQRSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1045 = VQRSHLuv16i8
+ { 1046, 5, 1, 42, "VQRSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1046 = VQRSHLuv1i64
+ { 1047, 5, 1, 42, "VQRSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1047 = VQRSHLuv2i32
+ { 1048, 5, 1, 43, "VQRSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1048 = VQRSHLuv2i64
+ { 1049, 5, 1, 42, "VQRSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1049 = VQRSHLuv4i16
+ { 1050, 5, 1, 43, "VQRSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1050 = VQRSHLuv4i32
+ { 1051, 5, 1, 43, "VQRSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1051 = VQRSHLuv8i16
+ { 1052, 5, 1, 42, "VQRSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1052 = VQRSHLuv8i8
+ { 1053, 5, 1, 42, "VQRSHRNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1053 = VQRSHRNsv2i32
+ { 1054, 5, 1, 42, "VQRSHRNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1054 = VQRSHRNsv4i16
+ { 1055, 5, 1, 42, "VQRSHRNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1055 = VQRSHRNsv8i8
+ { 1056, 5, 1, 42, "VQRSHRNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1056 = VQRSHRNuv2i32
+ { 1057, 5, 1, 42, "VQRSHRNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1057 = VQRSHRNuv4i16
+ { 1058, 5, 1, 42, "VQRSHRNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1058 = VQRSHRNuv8i8
+ { 1059, 5, 1, 42, "VQRSHRUNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1059 = VQRSHRUNv2i32
+ { 1060, 5, 1, 42, "VQRSHRUNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1060 = VQRSHRUNv4i16
+ { 1061, 5, 1, 42, "VQRSHRUNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1061 = VQRSHRUNv8i8
+ { 1062, 5, 1, 42, "VQSHLsiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1062 = VQSHLsiv16i8
+ { 1063, 5, 1, 42, "VQSHLsiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1063 = VQSHLsiv1i64
+ { 1064, 5, 1, 42, "VQSHLsiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1064 = VQSHLsiv2i32
+ { 1065, 5, 1, 42, "VQSHLsiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1065 = VQSHLsiv2i64
+ { 1066, 5, 1, 42, "VQSHLsiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1066 = VQSHLsiv4i16
+ { 1067, 5, 1, 42, "VQSHLsiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1067 = VQSHLsiv4i32
+ { 1068, 5, 1, 42, "VQSHLsiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1068 = VQSHLsiv8i16
+ { 1069, 5, 1, 42, "VQSHLsiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1069 = VQSHLsiv8i8
+ { 1070, 5, 1, 42, "VQSHLsuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1070 = VQSHLsuv16i8
+ { 1071, 5, 1, 42, "VQSHLsuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1071 = VQSHLsuv1i64
+ { 1072, 5, 1, 42, "VQSHLsuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1072 = VQSHLsuv2i32
+ { 1073, 5, 1, 42, "VQSHLsuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1073 = VQSHLsuv2i64
+ { 1074, 5, 1, 42, "VQSHLsuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1074 = VQSHLsuv4i16
+ { 1075, 5, 1, 42, "VQSHLsuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1075 = VQSHLsuv4i32
+ { 1076, 5, 1, 42, "VQSHLsuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1076 = VQSHLsuv8i16
+ { 1077, 5, 1, 42, "VQSHLsuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1077 = VQSHLsuv8i8
+ { 1078, 5, 1, 43, "VQSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1078 = VQSHLsv16i8
+ { 1079, 5, 1, 42, "VQSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1079 = VQSHLsv1i64
+ { 1080, 5, 1, 42, "VQSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1080 = VQSHLsv2i32
+ { 1081, 5, 1, 43, "VQSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1081 = VQSHLsv2i64
+ { 1082, 5, 1, 42, "VQSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1082 = VQSHLsv4i16
+ { 1083, 5, 1, 43, "VQSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1083 = VQSHLsv4i32
+ { 1084, 5, 1, 43, "VQSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1084 = VQSHLsv8i16
+ { 1085, 5, 1, 42, "VQSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1085 = VQSHLsv8i8
+ { 1086, 5, 1, 42, "VQSHLuiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1086 = VQSHLuiv16i8
+ { 1087, 5, 1, 42, "VQSHLuiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1087 = VQSHLuiv1i64
+ { 1088, 5, 1, 42, "VQSHLuiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1088 = VQSHLuiv2i32
+ { 1089, 5, 1, 42, "VQSHLuiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1089 = VQSHLuiv2i64
+ { 1090, 5, 1, 42, "VQSHLuiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1090 = VQSHLuiv4i16
+ { 1091, 5, 1, 42, "VQSHLuiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1091 = VQSHLuiv4i32
+ { 1092, 5, 1, 42, "VQSHLuiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1092 = VQSHLuiv8i16
+ { 1093, 5, 1, 42, "VQSHLuiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1093 = VQSHLuiv8i8
+ { 1094, 5, 1, 43, "VQSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1094 = VQSHLuv16i8
+ { 1095, 5, 1, 42, "VQSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1095 = VQSHLuv1i64
+ { 1096, 5, 1, 42, "VQSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1096 = VQSHLuv2i32
+ { 1097, 5, 1, 43, "VQSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1097 = VQSHLuv2i64
+ { 1098, 5, 1, 42, "VQSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1098 = VQSHLuv4i16
+ { 1099, 5, 1, 43, "VQSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1099 = VQSHLuv4i32
+ { 1100, 5, 1, 43, "VQSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1100 = VQSHLuv8i16
+ { 1101, 5, 1, 42, "VQSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1101 = VQSHLuv8i8
+ { 1102, 5, 1, 42, "VQSHRNsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1102 = VQSHRNsv2i32
+ { 1103, 5, 1, 42, "VQSHRNsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1103 = VQSHRNsv4i16
+ { 1104, 5, 1, 42, "VQSHRNsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1104 = VQSHRNsv8i8
+ { 1105, 5, 1, 42, "VQSHRNuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1105 = VQSHRNuv2i32
+ { 1106, 5, 1, 42, "VQSHRNuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1106 = VQSHRNuv4i16
+ { 1107, 5, 1, 42, "VQSHRNuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1107 = VQSHRNuv8i8
+ { 1108, 5, 1, 42, "VQSHRUNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1108 = VQSHRUNv2i32
+ { 1109, 5, 1, 42, "VQSHRUNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1109 = VQSHRUNv4i16
+ { 1110, 5, 1, 42, "VQSHRUNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1110 = VQSHRUNv8i8
+ { 1111, 5, 1, 4, "VQSUBsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1111 = VQSUBsv16i8
+ { 1112, 5, 1, 3, "VQSUBsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1112 = VQSUBsv1i64
+ { 1113, 5, 1, 3, "VQSUBsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1113 = VQSUBsv2i32
+ { 1114, 5, 1, 4, "VQSUBsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1114 = VQSUBsv2i64
+ { 1115, 5, 1, 3, "VQSUBsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1115 = VQSUBsv4i16
+ { 1116, 5, 1, 4, "VQSUBsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1116 = VQSUBsv4i32
+ { 1117, 5, 1, 4, "VQSUBsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1117 = VQSUBsv8i16
+ { 1118, 5, 1, 3, "VQSUBsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1118 = VQSUBsv8i8
+ { 1119, 5, 1, 4, "VQSUBuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1119 = VQSUBuv16i8
+ { 1120, 5, 1, 3, "VQSUBuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1120 = VQSUBuv1i64
+ { 1121, 5, 1, 3, "VQSUBuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1121 = VQSUBuv2i32
+ { 1122, 5, 1, 4, "VQSUBuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1122 = VQSUBuv2i64
+ { 1123, 5, 1, 3, "VQSUBuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1123 = VQSUBuv4i16
+ { 1124, 5, 1, 4, "VQSUBuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1124 = VQSUBuv4i32
+ { 1125, 5, 1, 4, "VQSUBuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1125 = VQSUBuv8i16
+ { 1126, 5, 1, 3, "VQSUBuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1126 = VQSUBuv8i8
+ { 1127, 5, 1, 3, "VRADDHNv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1127 = VRADDHNv2i32
+ { 1128, 5, 1, 3, "VRADDHNv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1128 = VRADDHNv4i16
+ { 1129, 5, 1, 3, "VRADDHNv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1129 = VRADDHNv8i8
+ { 1130, 4, 1, 57, "VRECPEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1130 = VRECPEd
+ { 1131, 4, 1, 57, "VRECPEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1131 = VRECPEfd
+ { 1132, 4, 1, 58, "VRECPEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1132 = VRECPEfq
+ { 1133, 4, 1, 58, "VRECPEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1133 = VRECPEq
+ { 1134, 5, 1, 40, "VRECPSfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1134 = VRECPSfd
+ { 1135, 5, 1, 41, "VRECPSfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1135 = VRECPSfq
+ { 1136, 4, 1, 21, "VREV16d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1136 = VREV16d8
+ { 1137, 4, 1, 21, "VREV16q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1137 = VREV16q8
+ { 1138, 4, 1, 21, "VREV32d16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1138 = VREV32d16
+ { 1139, 4, 1, 21, "VREV32d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1139 = VREV32d8
+ { 1140, 4, 1, 21, "VREV32q16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1140 = VREV32q16
+ { 1141, 4, 1, 21, "VREV32q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1141 = VREV32q8
+ { 1142, 4, 1, 21, "VREV64d16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1142 = VREV64d16
+ { 1143, 4, 1, 21, "VREV64d32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1143 = VREV64d32
+ { 1144, 4, 1, 21, "VREV64d8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1144 = VREV64d8
+ { 1145, 4, 1, 21, "VREV64df", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1145 = VREV64df
+ { 1146, 4, 1, 21, "VREV64q16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1146 = VREV64q16
+ { 1147, 4, 1, 21, "VREV64q32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1147 = VREV64q32
+ { 1148, 4, 1, 21, "VREV64q8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1148 = VREV64q8
+ { 1149, 4, 1, 21, "VREV64qf", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1149 = VREV64qf
+ { 1150, 5, 1, 4, "VRHADDsv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1150 = VRHADDsv16i8
+ { 1151, 5, 1, 3, "VRHADDsv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1151 = VRHADDsv2i32
+ { 1152, 5, 1, 3, "VRHADDsv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1152 = VRHADDsv4i16
+ { 1153, 5, 1, 4, "VRHADDsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1153 = VRHADDsv4i32
+ { 1154, 5, 1, 4, "VRHADDsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1154 = VRHADDsv8i16
+ { 1155, 5, 1, 3, "VRHADDsv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1155 = VRHADDsv8i8
+ { 1156, 5, 1, 4, "VRHADDuv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1156 = VRHADDuv16i8
+ { 1157, 5, 1, 3, "VRHADDuv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1157 = VRHADDuv2i32
+ { 1158, 5, 1, 3, "VRHADDuv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1158 = VRHADDuv4i16
+ { 1159, 5, 1, 4, "VRHADDuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1159 = VRHADDuv4i32
+ { 1160, 5, 1, 4, "VRHADDuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1160 = VRHADDuv8i16
+ { 1161, 5, 1, 3, "VRHADDuv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1161 = VRHADDuv8i8
+ { 1162, 5, 1, 43, "VRSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1162 = VRSHLsv16i8
+ { 1163, 5, 1, 42, "VRSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1163 = VRSHLsv1i64
+ { 1164, 5, 1, 42, "VRSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1164 = VRSHLsv2i32
+ { 1165, 5, 1, 43, "VRSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1165 = VRSHLsv2i64
+ { 1166, 5, 1, 42, "VRSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1166 = VRSHLsv4i16
+ { 1167, 5, 1, 43, "VRSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1167 = VRSHLsv4i32
+ { 1168, 5, 1, 43, "VRSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1168 = VRSHLsv8i16
+ { 1169, 5, 1, 42, "VRSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1169 = VRSHLsv8i8
+ { 1170, 5, 1, 43, "VRSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1170 = VRSHLuv16i8
+ { 1171, 5, 1, 42, "VRSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1171 = VRSHLuv1i64
+ { 1172, 5, 1, 42, "VRSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1172 = VRSHLuv2i32
+ { 1173, 5, 1, 43, "VRSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1173 = VRSHLuv2i64
+ { 1174, 5, 1, 42, "VRSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1174 = VRSHLuv4i16
+ { 1175, 5, 1, 43, "VRSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1175 = VRSHLuv4i32
+ { 1176, 5, 1, 43, "VRSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1176 = VRSHLuv8i16
+ { 1177, 5, 1, 42, "VRSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1177 = VRSHLuv8i8
+ { 1178, 5, 1, 42, "VRSHRNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1178 = VRSHRNv2i32
+ { 1179, 5, 1, 42, "VRSHRNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1179 = VRSHRNv4i16
+ { 1180, 5, 1, 42, "VRSHRNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1180 = VRSHRNv8i8
+ { 1181, 5, 1, 42, "VRSHRsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1181 = VRSHRsv16i8
+ { 1182, 5, 1, 42, "VRSHRsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1182 = VRSHRsv1i64
+ { 1183, 5, 1, 42, "VRSHRsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1183 = VRSHRsv2i32
+ { 1184, 5, 1, 42, "VRSHRsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1184 = VRSHRsv2i64
+ { 1185, 5, 1, 42, "VRSHRsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1185 = VRSHRsv4i16
+ { 1186, 5, 1, 42, "VRSHRsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1186 = VRSHRsv4i32
+ { 1187, 5, 1, 42, "VRSHRsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1187 = VRSHRsv8i16
+ { 1188, 5, 1, 42, "VRSHRsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1188 = VRSHRsv8i8
+ { 1189, 5, 1, 42, "VRSHRuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1189 = VRSHRuv16i8
+ { 1190, 5, 1, 42, "VRSHRuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1190 = VRSHRuv1i64
+ { 1191, 5, 1, 42, "VRSHRuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1191 = VRSHRuv2i32
+ { 1192, 5, 1, 42, "VRSHRuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1192 = VRSHRuv2i64
+ { 1193, 5, 1, 42, "VRSHRuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1193 = VRSHRuv4i16
+ { 1194, 5, 1, 42, "VRSHRuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1194 = VRSHRuv4i32
+ { 1195, 5, 1, 42, "VRSHRuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1195 = VRSHRuv8i16
+ { 1196, 5, 1, 42, "VRSHRuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1196 = VRSHRuv8i8
+ { 1197, 4, 1, 57, "VRSQRTEd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1197 = VRSQRTEd
+ { 1198, 4, 1, 57, "VRSQRTEfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1198 = VRSQRTEfd
+ { 1199, 4, 1, 58, "VRSQRTEfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1199 = VRSQRTEfq
+ { 1200, 4, 1, 58, "VRSQRTEq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1200 = VRSQRTEq
+ { 1201, 5, 1, 40, "VRSQRTSfd", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1201 = VRSQRTSfd
+ { 1202, 5, 1, 41, "VRSQRTSfq", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1202 = VRSQRTSfq
+ { 1203, 6, 1, 33, "VRSRAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1203 = VRSRAsv16i8
+ { 1204, 6, 1, 33, "VRSRAsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1204 = VRSRAsv1i64
+ { 1205, 6, 1, 33, "VRSRAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1205 = VRSRAsv2i32
+ { 1206, 6, 1, 33, "VRSRAsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1206 = VRSRAsv2i64
+ { 1207, 6, 1, 33, "VRSRAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1207 = VRSRAsv4i16
+ { 1208, 6, 1, 33, "VRSRAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1208 = VRSRAsv4i32
+ { 1209, 6, 1, 33, "VRSRAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1209 = VRSRAsv8i16
+ { 1210, 6, 1, 33, "VRSRAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1210 = VRSRAsv8i8
+ { 1211, 6, 1, 33, "VRSRAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1211 = VRSRAuv16i8
+ { 1212, 6, 1, 33, "VRSRAuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1212 = VRSRAuv1i64
+ { 1213, 6, 1, 33, "VRSRAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1213 = VRSRAuv2i32
+ { 1214, 6, 1, 33, "VRSRAuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1214 = VRSRAuv2i64
+ { 1215, 6, 1, 33, "VRSRAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1215 = VRSRAuv4i16
+ { 1216, 6, 1, 33, "VRSRAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1216 = VRSRAuv4i32
+ { 1217, 6, 1, 33, "VRSRAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1217 = VRSRAuv8i16
+ { 1218, 6, 1, 33, "VRSRAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1218 = VRSRAuv8i8
+ { 1219, 5, 1, 3, "VRSUBHNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1219 = VRSUBHNv2i32
+ { 1220, 5, 1, 3, "VRSUBHNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1220 = VRSUBHNv4i16
+ { 1221, 5, 1, 3, "VRSUBHNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1221 = VRSUBHNv8i8
+ { 1222, 6, 1, 25, "VSETLNi16", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo127 }, // Inst #1222 = VSETLNi16
+ { 1223, 6, 1, 25, "VSETLNi32", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo127 }, // Inst #1223 = VSETLNi32
+ { 1224, 6, 1, 25, "VSETLNi8", 0|(1<<TID::Predicable), 0|(3<<4)|(26<<9), NULL, NULL, NULL, OperandInfo127 }, // Inst #1224 = VSETLNi8
+ { 1225, 5, 1, 44, "VSHLLi16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1225 = VSHLLi16
+ { 1226, 5, 1, 44, "VSHLLi32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1226 = VSHLLi32
+ { 1227, 5, 1, 44, "VSHLLi8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1227 = VSHLLi8
+ { 1228, 5, 1, 44, "VSHLLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1228 = VSHLLsv2i64
+ { 1229, 5, 1, 44, "VSHLLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1229 = VSHLLsv4i32
+ { 1230, 5, 1, 44, "VSHLLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1230 = VSHLLsv8i16
+ { 1231, 5, 1, 44, "VSHLLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1231 = VSHLLuv2i64
+ { 1232, 5, 1, 44, "VSHLLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1232 = VSHLLuv4i32
+ { 1233, 5, 1, 44, "VSHLLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo81 }, // Inst #1233 = VSHLLuv8i16
+ { 1234, 5, 1, 44, "VSHLiv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1234 = VSHLiv16i8
+ { 1235, 5, 1, 44, "VSHLiv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1235 = VSHLiv1i64
+ { 1236, 5, 1, 44, "VSHLiv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1236 = VSHLiv2i32
+ { 1237, 5, 1, 44, "VSHLiv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1237 = VSHLiv2i64
+ { 1238, 5, 1, 44, "VSHLiv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1238 = VSHLiv4i16
+ { 1239, 5, 1, 44, "VSHLiv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1239 = VSHLiv4i32
+ { 1240, 5, 1, 44, "VSHLiv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1240 = VSHLiv8i16
+ { 1241, 5, 1, 44, "VSHLiv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1241 = VSHLiv8i8
+ { 1242, 5, 1, 45, "VSHLsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1242 = VSHLsv16i8
+ { 1243, 5, 1, 44, "VSHLsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1243 = VSHLsv1i64
+ { 1244, 5, 1, 44, "VSHLsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1244 = VSHLsv2i32
+ { 1245, 5, 1, 45, "VSHLsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1245 = VSHLsv2i64
+ { 1246, 5, 1, 44, "VSHLsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1246 = VSHLsv4i16
+ { 1247, 5, 1, 45, "VSHLsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1247 = VSHLsv4i32
+ { 1248, 5, 1, 45, "VSHLsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1248 = VSHLsv8i16
+ { 1249, 5, 1, 44, "VSHLsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1249 = VSHLsv8i8
+ { 1250, 5, 1, 45, "VSHLuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1250 = VSHLuv16i8
+ { 1251, 5, 1, 44, "VSHLuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1251 = VSHLuv1i64
+ { 1252, 5, 1, 44, "VSHLuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1252 = VSHLuv2i32
+ { 1253, 5, 1, 45, "VSHLuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1253 = VSHLuv2i64
+ { 1254, 5, 1, 44, "VSHLuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1254 = VSHLuv4i16
+ { 1255, 5, 1, 45, "VSHLuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1255 = VSHLuv4i32
+ { 1256, 5, 1, 45, "VSHLuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1256 = VSHLuv8i16
+ { 1257, 5, 1, 44, "VSHLuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1257 = VSHLuv8i8
+ { 1258, 5, 1, 44, "VSHRNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1258 = VSHRNv2i32
+ { 1259, 5, 1, 44, "VSHRNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1259 = VSHRNv4i16
+ { 1260, 5, 1, 44, "VSHRNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo124 }, // Inst #1260 = VSHRNv8i8
+ { 1261, 5, 1, 44, "VSHRsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1261 = VSHRsv16i8
+ { 1262, 5, 1, 44, "VSHRsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1262 = VSHRsv1i64
+ { 1263, 5, 1, 44, "VSHRsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1263 = VSHRsv2i32
+ { 1264, 5, 1, 44, "VSHRsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1264 = VSHRsv2i64
+ { 1265, 5, 1, 44, "VSHRsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1265 = VSHRsv4i16
+ { 1266, 5, 1, 44, "VSHRsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1266 = VSHRsv4i32
+ { 1267, 5, 1, 44, "VSHRsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1267 = VSHRsv8i16
+ { 1268, 5, 1, 44, "VSHRsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1268 = VSHRsv8i8
+ { 1269, 5, 1, 44, "VSHRuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1269 = VSHRuv16i8
+ { 1270, 5, 1, 44, "VSHRuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1270 = VSHRuv1i64
+ { 1271, 5, 1, 44, "VSHRuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1271 = VSHRuv2i32
+ { 1272, 5, 1, 44, "VSHRuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1272 = VSHRuv2i64
+ { 1273, 5, 1, 44, "VSHRuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1273 = VSHRuv4i16
+ { 1274, 5, 1, 44, "VSHRuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1274 = VSHRuv4i32
+ { 1275, 5, 1, 44, "VSHRuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo78 }, // Inst #1275 = VSHRuv8i16
+ { 1276, 5, 1, 44, "VSHRuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo77 }, // Inst #1276 = VSHRuv8i8
+ { 1277, 5, 1, 67, "VSHTOD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1277 = VSHTOD
+ { 1278, 5, 1, 68, "VSHTOS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1278 = VSHTOS
+ { 1279, 4, 1, 67, "VSITOD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #1279 = VSITOD
+ { 1280, 4, 1, 68, "VSITOS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #1280 = VSITOS
+ { 1281, 6, 1, 45, "VSLIv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1281 = VSLIv16i8
+ { 1282, 6, 1, 44, "VSLIv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1282 = VSLIv1i64
+ { 1283, 6, 1, 44, "VSLIv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1283 = VSLIv2i32
+ { 1284, 6, 1, 45, "VSLIv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1284 = VSLIv2i64
+ { 1285, 6, 1, 44, "VSLIv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1285 = VSLIv4i16
+ { 1286, 6, 1, 45, "VSLIv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1286 = VSLIv4i32
+ { 1287, 6, 1, 45, "VSLIv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1287 = VSLIv8i16
+ { 1288, 6, 1, 44, "VSLIv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1288 = VSLIv8i8
+ { 1289, 5, 1, 67, "VSLTOD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1289 = VSLTOD
+ { 1290, 5, 1, 68, "VSLTOS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1290 = VSLTOS
+ { 1291, 4, 1, 81, "VSQRTD", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1291 = VSQRTD
+ { 1292, 4, 1, 80, "VSQRTS", 0|(1<<TID::Predicable), 0|(3<<4)|(13<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #1292 = VSQRTS
+ { 1293, 6, 1, 33, "VSRAsv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1293 = VSRAsv16i8
+ { 1294, 6, 1, 33, "VSRAsv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1294 = VSRAsv1i64
+ { 1295, 6, 1, 33, "VSRAsv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1295 = VSRAsv2i32
+ { 1296, 6, 1, 33, "VSRAsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1296 = VSRAsv2i64
+ { 1297, 6, 1, 33, "VSRAsv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1297 = VSRAsv4i16
+ { 1298, 6, 1, 33, "VSRAsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1298 = VSRAsv4i32
+ { 1299, 6, 1, 33, "VSRAsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1299 = VSRAsv8i16
+ { 1300, 6, 1, 33, "VSRAsv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1300 = VSRAsv8i8
+ { 1301, 6, 1, 33, "VSRAuv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1301 = VSRAuv16i8
+ { 1302, 6, 1, 33, "VSRAuv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1302 = VSRAuv1i64
+ { 1303, 6, 1, 33, "VSRAuv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1303 = VSRAuv2i32
+ { 1304, 6, 1, 33, "VSRAuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1304 = VSRAuv2i64
+ { 1305, 6, 1, 33, "VSRAuv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1305 = VSRAuv4i16
+ { 1306, 6, 1, 33, "VSRAuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1306 = VSRAuv4i32
+ { 1307, 6, 1, 33, "VSRAuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1307 = VSRAuv8i16
+ { 1308, 6, 1, 33, "VSRAuv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1308 = VSRAuv8i8
+ { 1309, 6, 1, 45, "VSRIv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1309 = VSRIv16i8
+ { 1310, 6, 1, 44, "VSRIv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1310 = VSRIv1i64
+ { 1311, 6, 1, 44, "VSRIv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1311 = VSRIv2i32
+ { 1312, 6, 1, 45, "VSRIv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1312 = VSRIv2i64
+ { 1313, 6, 1, 44, "VSRIv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1313 = VSRIv4i16
+ { 1314, 6, 1, 45, "VSRIv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1314 = VSRIv4i32
+ { 1315, 6, 1, 45, "VSRIv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo125 }, // Inst #1315 = VSRIv8i16
+ { 1316, 6, 1, 44, "VSRIv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo126 }, // Inst #1316 = VSRIv8i8
+ { 1317, 7, 0, 46, "VST1d16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 }, // Inst #1317 = VST1d16
+ { 1318, 10, 0, 46, "VST1d16Q", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1318 = VST1d16Q
+ { 1319, 9, 0, 46, "VST1d16T", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 }, // Inst #1319 = VST1d16T
+ { 1320, 7, 0, 46, "VST1d32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 }, // Inst #1320 = VST1d32
+ { 1321, 10, 0, 46, "VST1d32Q", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1321 = VST1d32Q
+ { 1322, 9, 0, 46, "VST1d32T", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 }, // Inst #1322 = VST1d32T
+ { 1323, 7, 0, 46, "VST1d64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 }, // Inst #1323 = VST1d64
+ { 1324, 7, 0, 46, "VST1d8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 }, // Inst #1324 = VST1d8
+ { 1325, 10, 0, 46, "VST1d8Q", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1325 = VST1d8Q
+ { 1326, 9, 0, 46, "VST1d8T", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 }, // Inst #1326 = VST1d8T
+ { 1327, 7, 0, 46, "VST1df", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo130 }, // Inst #1327 = VST1df
+ { 1328, 7, 0, 46, "VST1q16", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo133 }, // Inst #1328 = VST1q16
+ { 1329, 7, 0, 46, "VST1q32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo133 }, // Inst #1329 = VST1q32
+ { 1330, 7, 0, 46, "VST1q64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo133 }, // Inst #1330 = VST1q64
+ { 1331, 7, 0, 46, "VST1q8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo133 }, // Inst #1331 = VST1q8
+ { 1332, 7, 0, 46, "VST1qf", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo133 }, // Inst #1332 = VST1qf
+ { 1333, 9, 0, 46, "VST2LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 }, // Inst #1333 = VST2LNd16
+ { 1334, 9, 0, 46, "VST2LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 }, // Inst #1334 = VST2LNd32
+ { 1335, 9, 0, 46, "VST2LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 }, // Inst #1335 = VST2LNd8
+ { 1336, 9, 0, 46, "VST2LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 }, // Inst #1336 = VST2LNq16a
+ { 1337, 9, 0, 46, "VST2LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 }, // Inst #1337 = VST2LNq16b
+ { 1338, 9, 0, 46, "VST2LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 }, // Inst #1338 = VST2LNq32a
+ { 1339, 9, 0, 46, "VST2LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo134 }, // Inst #1339 = VST2LNq32b
+ { 1340, 8, 0, 46, "VST2d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 }, // Inst #1340 = VST2d16
+ { 1341, 8, 0, 46, "VST2d16D", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 }, // Inst #1341 = VST2d16D
+ { 1342, 8, 0, 46, "VST2d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 }, // Inst #1342 = VST2d32
+ { 1343, 8, 0, 46, "VST2d32D", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 }, // Inst #1343 = VST2d32D
+ { 1344, 8, 0, 46, "VST2d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 }, // Inst #1344 = VST2d64
+ { 1345, 8, 0, 46, "VST2d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 }, // Inst #1345 = VST2d8
+ { 1346, 8, 0, 46, "VST2d8D", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo135 }, // Inst #1346 = VST2d8D
+ { 1347, 10, 0, 46, "VST2q16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1347 = VST2q16
+ { 1348, 10, 0, 46, "VST2q32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1348 = VST2q32
+ { 1349, 10, 0, 46, "VST2q8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1349 = VST2q8
+ { 1350, 10, 0, 46, "VST3LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 }, // Inst #1350 = VST3LNd16
+ { 1351, 10, 0, 46, "VST3LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 }, // Inst #1351 = VST3LNd32
+ { 1352, 10, 0, 46, "VST3LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 }, // Inst #1352 = VST3LNd8
+ { 1353, 10, 0, 46, "VST3LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 }, // Inst #1353 = VST3LNq16a
+ { 1354, 10, 0, 46, "VST3LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 }, // Inst #1354 = VST3LNq16b
+ { 1355, 10, 0, 46, "VST3LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 }, // Inst #1355 = VST3LNq32a
+ { 1356, 10, 0, 46, "VST3LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo136 }, // Inst #1356 = VST3LNq32b
+ { 1357, 9, 0, 46, "VST3d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 }, // Inst #1357 = VST3d16
+ { 1358, 9, 0, 46, "VST3d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 }, // Inst #1358 = VST3d32
+ { 1359, 9, 0, 46, "VST3d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 }, // Inst #1359 = VST3d64
+ { 1360, 9, 0, 46, "VST3d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo132 }, // Inst #1360 = VST3d8
+ { 1361, 10, 1, 46, "VST3q16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo137 }, // Inst #1361 = VST3q16a
+ { 1362, 10, 1, 46, "VST3q16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo137 }, // Inst #1362 = VST3q16b
+ { 1363, 10, 1, 46, "VST3q32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo137 }, // Inst #1363 = VST3q32a
+ { 1364, 10, 1, 46, "VST3q32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo137 }, // Inst #1364 = VST3q32b
+ { 1365, 10, 1, 46, "VST3q8a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo137 }, // Inst #1365 = VST3q8a
+ { 1366, 10, 1, 46, "VST3q8b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo137 }, // Inst #1366 = VST3q8b
+ { 1367, 11, 0, 46, "VST4LNd16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1367 = VST4LNd16
+ { 1368, 11, 0, 46, "VST4LNd32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1368 = VST4LNd32
+ { 1369, 11, 0, 46, "VST4LNd8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1369 = VST4LNd8
+ { 1370, 11, 0, 46, "VST4LNq16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1370 = VST4LNq16a
+ { 1371, 11, 0, 46, "VST4LNq16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1371 = VST4LNq16b
+ { 1372, 11, 0, 46, "VST4LNq32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1372 = VST4LNq32a
+ { 1373, 11, 0, 46, "VST4LNq32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo138 }, // Inst #1373 = VST4LNq32b
+ { 1374, 10, 0, 46, "VST4d16", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1374 = VST4d16
+ { 1375, 10, 0, 46, "VST4d32", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1375 = VST4d32
+ { 1376, 10, 0, 46, "VST4d64", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1376 = VST4d64
+ { 1377, 10, 0, 46, "VST4d8", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo131 }, // Inst #1377 = VST4d8
+ { 1378, 11, 1, 46, "VST4q16a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1378 = VST4q16a
+ { 1379, 11, 1, 46, "VST4q16b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1379 = VST4q16b
+ { 1380, 11, 1, 46, "VST4q32a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1380 = VST4q32a
+ { 1381, 11, 1, 46, "VST4q32b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1381 = VST4q32b
+ { 1382, 11, 1, 46, "VST4q8a", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1382 = VST4q8a
+ { 1383, 11, 1, 46, "VST4q8b", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|6|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo139 }, // Inst #1383 = VST4q8b
+ { 1384, 5, 0, 85, "VSTMD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|5|(3<<4)|(21<<9)|(3<<17), NULL, NULL, NULL, OperandInfo35 }, // Inst #1384 = VSTMD
+ { 1385, 5, 0, 85, "VSTMS", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|5|(3<<4)|(21<<9)|(1<<17), NULL, NULL, NULL, OperandInfo35 }, // Inst #1385 = VSTMS
+ { 1386, 5, 0, 84, "VSTRD", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|5|(3<<4)|(20<<9)|(3<<17), NULL, NULL, NULL, OperandInfo96 }, // Inst #1386 = VSTRD
+ { 1387, 5, 0, 85, "VSTRQ", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|4|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo97 }, // Inst #1387 = VSTRQ
+ { 1388, 5, 0, 83, "VSTRS", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|5|(3<<4)|(20<<9)|(1<<17), NULL, NULL, NULL, OperandInfo98 }, // Inst #1388 = VSTRS
+ { 1389, 5, 1, 62, "VSUBD", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1389 = VSUBD
+ { 1390, 5, 1, 3, "VSUBHNv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1390 = VSUBHNv2i32
+ { 1391, 5, 1, 3, "VSUBHNv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1391 = VSUBHNv4i16
+ { 1392, 5, 1, 3, "VSUBHNv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo69 }, // Inst #1392 = VSUBHNv8i8
+ { 1393, 5, 1, 44, "VSUBLsv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1393 = VSUBLsv2i64
+ { 1394, 5, 1, 44, "VSUBLsv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1394 = VSUBLsv4i32
+ { 1395, 5, 1, 44, "VSUBLsv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1395 = VSUBLsv8i16
+ { 1396, 5, 1, 44, "VSUBLuv2i64", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1396 = VSUBLuv2i64
+ { 1397, 5, 1, 44, "VSUBLuv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1397 = VSUBLuv4i32
+ { 1398, 5, 1, 44, "VSUBLuv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo62 }, // Inst #1398 = VSUBLuv8i16
+ { 1399, 5, 1, 61, "VSUBS", 0|(1<<TID::Predicable), 0|(3<<4)|(14<<9)|(1<<17), NULL, NULL, NULL, OperandInfo70 }, // Inst #1399 = VSUBS
+ { 1400, 5, 1, 47, "VSUBWsv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #1400 = VSUBWsv2i64
+ { 1401, 5, 1, 47, "VSUBWsv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #1401 = VSUBWsv4i32
+ { 1402, 5, 1, 47, "VSUBWsv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #1402 = VSUBWsv8i16
+ { 1403, 5, 1, 47, "VSUBWuv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #1403 = VSUBWuv2i64
+ { 1404, 5, 1, 47, "VSUBWuv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #1404 = VSUBWuv4i32
+ { 1405, 5, 1, 47, "VSUBWuv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo71 }, // Inst #1405 = VSUBWuv8i16
+ { 1406, 5, 1, 1, "VSUBfd", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1406 = VSUBfd
+ { 1407, 5, 1, 1, "VSUBfd_sfp", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo72 }, // Inst #1407 = VSUBfd_sfp
+ { 1408, 5, 1, 2, "VSUBfq", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1408 = VSUBfq
+ { 1409, 5, 1, 48, "VSUBv16i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1409 = VSUBv16i8
+ { 1410, 5, 1, 47, "VSUBv1i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1410 = VSUBv1i64
+ { 1411, 5, 1, 47, "VSUBv2i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1411 = VSUBv2i32
+ { 1412, 5, 1, 48, "VSUBv2i64", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1412 = VSUBv2i64
+ { 1413, 5, 1, 47, "VSUBv4i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1413 = VSUBv4i16
+ { 1414, 5, 1, 48, "VSUBv4i32", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1414 = VSUBv4i32
+ { 1415, 5, 1, 48, "VSUBv8i16", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1415 = VSUBv8i16
+ { 1416, 5, 1, 47, "VSUBv8i8", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1416 = VSUBv8i8
+ { 1417, 4, 1, 128, "VSWPd", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo65 }, // Inst #1417 = VSWPd
+ { 1418, 4, 1, 128, "VSWPq", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo68 }, // Inst #1418 = VSWPq
+ { 1419, 5, 1, 49, "VTBL1", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1419 = VTBL1
+ { 1420, 6, 1, 50, "VTBL2", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo140 }, // Inst #1420 = VTBL2
+ { 1421, 7, 1, 51, "VTBL3", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo141 }, // Inst #1421 = VTBL3
+ { 1422, 8, 1, 52, "VTBL4", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo142 }, // Inst #1422 = VTBL4
+ { 1423, 6, 1, 53, "VTBX1", 0|(1<<TID::Predicable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo61 }, // Inst #1423 = VTBX1
+ { 1424, 7, 1, 54, "VTBX2", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo143 }, // Inst #1424 = VTBX2
+ { 1425, 8, 1, 55, "VTBX3", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo144 }, // Inst #1425 = VTBX3
+ { 1426, 9, 1, 56, "VTBX4", 0|(1<<TID::Predicable)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo145 }, // Inst #1426 = VTBX4
+ { 1427, 5, 1, 65, "VTOSHD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1427 = VTOSHD
+ { 1428, 5, 1, 70, "VTOSHS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1428 = VTOSHS
+ { 1429, 4, 1, 65, "VTOSIRD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #1429 = VTOSIRD
+ { 1430, 4, 1, 70, "VTOSIRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #1430 = VTOSIRS
+ { 1431, 4, 1, 65, "VTOSIZD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #1431 = VTOSIZD
+ { 1432, 4, 1, 70, "VTOSIZS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #1432 = VTOSIZS
+ { 1433, 5, 1, 65, "VTOSLD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1433 = VTOSLD
+ { 1434, 5, 1, 70, "VTOSLS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1434 = VTOSLS
+ { 1435, 5, 1, 65, "VTOUHD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1435 = VTOUHD
+ { 1436, 5, 1, 70, "VTOUHS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1436 = VTOUHS
+ { 1437, 4, 1, 65, "VTOUIRD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #1437 = VTOUIRD
+ { 1438, 4, 1, 70, "VTOUIRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #1438 = VTOUIRS
+ { 1439, 4, 1, 65, "VTOUIZD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo76 }, // Inst #1439 = VTOUIZD
+ { 1440, 4, 1, 70, "VTOUIZS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #1440 = VTOUIZS
+ { 1441, 5, 1, 65, "VTOULD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1441 = VTOULD
+ { 1442, 5, 1, 70, "VTOULS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1442 = VTOULS
+ { 1443, 6, 2, 35, "VTRNd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 }, // Inst #1443 = VTRNd16
+ { 1444, 6, 2, 35, "VTRNd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 }, // Inst #1444 = VTRNd32
+ { 1445, 6, 2, 35, "VTRNd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 }, // Inst #1445 = VTRNd8
+ { 1446, 6, 2, 36, "VTRNq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 }, // Inst #1446 = VTRNq16
+ { 1447, 6, 2, 36, "VTRNq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 }, // Inst #1447 = VTRNq32
+ { 1448, 6, 2, 36, "VTRNq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 }, // Inst #1448 = VTRNq8
+ { 1449, 5, 1, 4, "VTSTv16i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1449 = VTSTv16i8
+ { 1450, 5, 1, 3, "VTSTv2i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1450 = VTSTv2i32
+ { 1451, 5, 1, 3, "VTSTv4i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1451 = VTSTv4i16
+ { 1452, 5, 1, 4, "VTSTv4i32", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1452 = VTSTv4i32
+ { 1453, 5, 1, 4, "VTSTv8i16", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo64 }, // Inst #1453 = VTSTv8i16
+ { 1454, 5, 1, 3, "VTSTv8i8", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo63 }, // Inst #1454 = VTSTv8i8
+ { 1455, 5, 1, 67, "VUHTOD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1455 = VUHTOD
+ { 1456, 5, 1, 68, "VUHTOS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1456 = VUHTOS
+ { 1457, 4, 1, 67, "VUITOD", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo75 }, // Inst #1457 = VUITOD
+ { 1458, 4, 1, 68, "VUITOS", 0|(1<<TID::Predicable), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo66 }, // Inst #1458 = VUITOS
+ { 1459, 5, 1, 67, "VULTOD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo128 }, // Inst #1459 = VULTOD
+ { 1460, 5, 1, 68, "VULTOS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(15<<9)|(1<<17), NULL, NULL, NULL, OperandInfo129 }, // Inst #1460 = VULTOS
+ { 1461, 6, 2, 35, "VUZPd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 }, // Inst #1461 = VUZPd16
+ { 1462, 6, 2, 35, "VUZPd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 }, // Inst #1462 = VUZPd32
+ { 1463, 6, 2, 35, "VUZPd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 }, // Inst #1463 = VUZPd8
+ { 1464, 6, 2, 37, "VUZPq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 }, // Inst #1464 = VUZPq16
+ { 1465, 6, 2, 37, "VUZPq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 }, // Inst #1465 = VUZPq32
+ { 1466, 6, 2, 37, "VUZPq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 }, // Inst #1466 = VUZPq8
+ { 1467, 6, 2, 35, "VZIPd16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 }, // Inst #1467 = VZIPd16
+ { 1468, 6, 2, 35, "VZIPd32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 }, // Inst #1468 = VZIPd32
+ { 1469, 6, 2, 35, "VZIPd8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo146 }, // Inst #1469 = VZIPd8
+ { 1470, 6, 2, 37, "VZIPq16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 }, // Inst #1470 = VZIPq16
+ { 1471, 6, 2, 37, "VZIPq32", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 }, // Inst #1471 = VZIPq32
+ { 1472, 6, 2, 37, "VZIPq8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(24<<9)|(2<<17), NULL, NULL, NULL, OperandInfo147 }, // Inst #1472 = VZIPq8
+ { 1473, 2, 0, 128, "WFE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1473 = WFE
+ { 1474, 2, 0, 128, "WFI", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1474 = WFI
+ { 1475, 2, 0, 128, "YIELD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(29<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1475 = YIELD
+ { 1476, 6, 1, 88, "t2ADCSri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1476 = t2ADCSri
+ { 1477, 6, 1, 89, "t2ADCSrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1477 = t2ADCSrr
+ { 1478, 7, 1, 90, "t2ADCSrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #1478 = t2ADCSrs
+ { 1479, 6, 1, 88, "t2ADCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #1479 = t2ADCri
+ { 1480, 6, 1, 89, "t2ADCrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #1480 = t2ADCrr
+ { 1481, 7, 1, 90, "t2ADCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo48 }, // Inst #1481 = t2ADCrs
+ { 1482, 5, 1, 88, "t2ADDSri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1482 = t2ADDSri
+ { 1483, 5, 1, 89, "t2ADDSrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1483 = t2ADDSrr
+ { 1484, 6, 1, 90, "t2ADDSrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo27 }, // Inst #1484 = t2ADDSrs
+ { 1485, 6, 1, 88, "t2ADDrSPi", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1485 = t2ADDrSPi
+ { 1486, 5, 1, 88, "t2ADDrSPi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1486 = t2ADDrSPi12
+ { 1487, 7, 1, 90, "t2ADDrSPs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1487 = t2ADDrSPs
+ { 1488, 6, 1, 88, "t2ADDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1488 = t2ADDri
+ { 1489, 6, 1, 88, "t2ADDri12", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1489 = t2ADDri12
+ { 1490, 6, 1, 89, "t2ADDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1490 = t2ADDrr
+ { 1491, 7, 1, 90, "t2ADDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1491 = t2ADDrs
+ { 1492, 6, 1, 88, "t2ANDri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1492 = t2ANDri
+ { 1493, 6, 1, 89, "t2ANDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1493 = t2ANDrr
+ { 1494, 7, 1, 90, "t2ANDrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1494 = t2ANDrs
+ { 1495, 6, 1, 113, "t2ASRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1495 = t2ASRri
+ { 1496, 6, 1, 114, "t2ASRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1496 = t2ASRrr
+ { 1497, 1, 0, 0, "t2B", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1497 = t2B
+ { 1498, 5, 1, 126, "t2BFC", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1498 = t2BFC
+ { 1499, 6, 1, 88, "t2BFI", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo51 }, // Inst #1499 = t2BFI
+ { 1500, 6, 1, 88, "t2BICri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1500 = t2BICri
+ { 1501, 6, 1, 89, "t2BICrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1501 = t2BICrr
+ { 1502, 7, 1, 90, "t2BICrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1502 = t2BICrs
+ { 1503, 4, 0, 0, "t2BR_JT", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo18 }, // Inst #1503 = t2BR_JT
+ { 1504, 3, 0, 128, "t2BXJ", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1504 = t2BXJ
+ { 1505, 3, 0, 0, "t2Bcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1505 = t2Bcc
+ { 1506, 2, 0, 128, "t2CLREX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1506 = t2CLREX
+ { 1507, 4, 1, 125, "t2CLZ", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1507 = t2CLZ
+ { 1508, 4, 0, 97, "t2CMNzri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #1508 = t2CMNzri
+ { 1509, 4, 0, 98, "t2CMNzrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1509 = t2CMNzrr
+ { 1510, 5, 0, 99, "t2CMNzrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1510 = t2CMNzrs
+ { 1511, 4, 0, 97, "t2CMPri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #1511 = t2CMPri
+ { 1512, 4, 0, 98, "t2CMPrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1512 = t2CMPrr
+ { 1513, 5, 0, 99, "t2CMPrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1513 = t2CMPrs
+ { 1514, 4, 0, 97, "t2CMPzri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #1514 = t2CMPzri
+ { 1515, 4, 0, 98, "t2CMPzrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1515 = t2CMPzrr
+ { 1516, 5, 0, 99, "t2CMPzrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1516 = t2CMPzrs
+ { 1517, 1, 0, 128, "t2CPS", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1517 = t2CPS
+ { 1518, 3, 0, 128, "t2DBG", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1518 = t2DBG
+ { 1519, 2, 0, 128, "t2DMBish", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1519 = t2DMBish
+ { 1520, 2, 0, 128, "t2DMBishst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1520 = t2DMBishst
+ { 1521, 2, 0, 128, "t2DMBnsh", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1521 = t2DMBnsh
+ { 1522, 2, 0, 128, "t2DMBnshst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1522 = t2DMBnshst
+ { 1523, 2, 0, 128, "t2DMBosh", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1523 = t2DMBosh
+ { 1524, 2, 0, 128, "t2DMBoshst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1524 = t2DMBoshst
+ { 1525, 2, 0, 128, "t2DMBst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1525 = t2DMBst
+ { 1526, 2, 0, 128, "t2DSBish", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1526 = t2DSBish
+ { 1527, 2, 0, 128, "t2DSBishst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1527 = t2DSBishst
+ { 1528, 2, 0, 128, "t2DSBnsh", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1528 = t2DSBnsh
+ { 1529, 2, 0, 128, "t2DSBnshst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1529 = t2DSBnshst
+ { 1530, 2, 0, 128, "t2DSBosh", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1530 = t2DSBosh
+ { 1531, 2, 0, 128, "t2DSBoshst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1531 = t2DSBoshst
+ { 1532, 2, 0, 128, "t2DSBst", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1532 = t2DSBst
+ { 1533, 6, 1, 88, "t2EORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1533 = t2EORri
+ { 1534, 6, 1, 89, "t2EORrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1534 = t2EORrr
+ { 1535, 7, 1, 90, "t2EORrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1535 = t2EORrs
+ { 1536, 2, 0, 128, "t2ISBsy", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1536 = t2ISBsy
+ { 1537, 2, 0, 92, "t2IT", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo148 }, // Inst #1537 = t2IT
+ { 1538, 0, 0, 128, "t2Int_MemBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #1538 = t2Int_MemBarrierV7
+ { 1539, 0, 0, 128, "t2Int_SyncBarrierV7", 0|(1<<TID::UnmodeledSideEffects), 0|(3<<4), NULL, NULL, NULL, 0 }, // Inst #1539 = t2Int_SyncBarrierV7
+ { 1540, 2, 0, 128, "t2Int_eh_sjlj_setjmp", 0, 0|(1<<4)|(23<<9), NULL, ImplicitList6, Barriers3, OperandInfo149 }, // Inst #1540 = t2Int_eh_sjlj_setjmp
+ { 1541, 5, 0, 103, "t2LDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #1541 = t2LDM
+ { 1542, 5, 0, 0, "t2LDM_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #1542 = t2LDM_RET
+ { 1543, 5, 1, 101, "t2LDRBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1543 = t2LDRBT
+ { 1544, 6, 2, 102, "t2LDRB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1544 = t2LDRB_POST
+ { 1545, 6, 2, 102, "t2LDRB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1545 = t2LDRB_PRE
+ { 1546, 5, 1, 101, "t2LDRBi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1546 = t2LDRBi12
+ { 1547, 5, 1, 101, "t2LDRBi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1547 = t2LDRBi8
+ { 1548, 4, 1, 101, "t2LDRBpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1548 = t2LDRBpci
+ { 1549, 6, 1, 104, "t2LDRBs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1549 = t2LDRBs
+ { 1550, 6, 2, 101, "t2LDRDi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1550 = t2LDRDi8
+ { 1551, 5, 2, 101, "t2LDRDpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1551 = t2LDRDpci
+ { 1552, 4, 1, 128, "t2LDREX", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1552 = t2LDREX
+ { 1553, 4, 1, 128, "t2LDREXB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1553 = t2LDREXB
+ { 1554, 5, 2, 128, "t2LDREXD", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1554 = t2LDREXD
+ { 1555, 4, 1, 128, "t2LDREXH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1555 = t2LDREXH
+ { 1556, 5, 1, 101, "t2LDRHT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1556 = t2LDRHT
+ { 1557, 6, 2, 102, "t2LDRH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1557 = t2LDRH_POST
+ { 1558, 6, 2, 102, "t2LDRH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1558 = t2LDRH_PRE
+ { 1559, 5, 1, 101, "t2LDRHi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1559 = t2LDRHi12
+ { 1560, 5, 1, 101, "t2LDRHi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1560 = t2LDRHi8
+ { 1561, 4, 1, 101, "t2LDRHpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1561 = t2LDRHpci
+ { 1562, 6, 1, 104, "t2LDRHs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1562 = t2LDRHs
+ { 1563, 5, 1, 101, "t2LDRSBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1563 = t2LDRSBT
+ { 1564, 6, 2, 102, "t2LDRSB_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1564 = t2LDRSB_POST
+ { 1565, 6, 2, 102, "t2LDRSB_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1565 = t2LDRSB_PRE
+ { 1566, 5, 1, 101, "t2LDRSBi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1566 = t2LDRSBi12
+ { 1567, 5, 1, 101, "t2LDRSBi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1567 = t2LDRSBi8
+ { 1568, 4, 1, 101, "t2LDRSBpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1568 = t2LDRSBpci
+ { 1569, 6, 1, 104, "t2LDRSBs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1569 = t2LDRSBs
+ { 1570, 5, 1, 101, "t2LDRSHT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1570 = t2LDRSHT
+ { 1571, 6, 2, 102, "t2LDRSH_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1571 = t2LDRSH_POST
+ { 1572, 6, 2, 102, "t2LDRSH_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1572 = t2LDRSH_PRE
+ { 1573, 5, 1, 101, "t2LDRSHi12", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1573 = t2LDRSHi12
+ { 1574, 5, 1, 101, "t2LDRSHi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1574 = t2LDRSHi8
+ { 1575, 4, 1, 101, "t2LDRSHpci", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1575 = t2LDRSHpci
+ { 1576, 6, 1, 104, "t2LDRSHs", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1576 = t2LDRSHs
+ { 1577, 5, 1, 101, "t2LDRT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1577 = t2LDRT
+ { 1578, 6, 2, 102, "t2LDR_POST", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1578 = t2LDR_POST
+ { 1579, 6, 2, 102, "t2LDR_PRE", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo150 }, // Inst #1579 = t2LDR_PRE
+ { 1580, 5, 1, 101, "t2LDRi12", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1580 = t2LDRi12
+ { 1581, 5, 1, 101, "t2LDRi8", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1581 = t2LDRi8
+ { 1582, 4, 1, 101, "t2LDRpci", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|14|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1582 = t2LDRpci
+ { 1583, 3, 1, 128, "t2LDRpci_pic", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|(1<<4), NULL, NULL, NULL, OperandInfo20 }, // Inst #1583 = t2LDRpci_pic
+ { 1584, 6, 1, 104, "t2LDRs", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1584 = t2LDRs
+ { 1585, 4, 1, 88, "t2LEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1585 = t2LEApcrel
+ { 1586, 5, 1, 88, "t2LEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo38 }, // Inst #1586 = t2LEApcrelJT
+ { 1587, 6, 1, 113, "t2LSLri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1587 = t2LSLri
+ { 1588, 6, 1, 114, "t2LSLrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1588 = t2LSLrr
+ { 1589, 6, 1, 113, "t2LSRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1589 = t2LSRri
+ { 1590, 6, 1, 114, "t2LSRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1590 = t2LSRrr
+ { 1591, 6, 1, 109, "t2MLA", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1591 = t2MLA
+ { 1592, 6, 1, 109, "t2MLS", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1592 = t2MLS
+ { 1593, 6, 1, 95, "t2MOVCCasr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1593 = t2MOVCCasr
+ { 1594, 5, 1, 93, "t2MOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1594 = t2MOVCCi
+ { 1595, 6, 1, 95, "t2MOVCClsl", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1595 = t2MOVCClsl
+ { 1596, 6, 1, 95, "t2MOVCClsr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1596 = t2MOVCClsr
+ { 1597, 5, 1, 94, "t2MOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo44 }, // Inst #1597 = t2MOVCCr
+ { 1598, 6, 1, 95, "t2MOVCCror", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo151 }, // Inst #1598 = t2MOVCCror
+ { 1599, 5, 1, 111, "t2MOVTi16", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo15 }, // Inst #1599 = t2MOVTi16
+ { 1600, 5, 1, 111, "t2MOVi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo46 }, // Inst #1600 = t2MOVi
+ { 1601, 4, 1, 111, "t2MOVi16", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1601 = t2MOVi16
+ { 1602, 4, 1, 111, "t2MOVi32imm", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|(2<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1602 = t2MOVi32imm
+ { 1603, 5, 1, 112, "t2MOVr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo47 }, // Inst #1603 = t2MOVr
+ { 1604, 5, 1, 113, "t2MOVrx", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo47 }, // Inst #1604 = t2MOVrx
+ { 1605, 2, 1, 113, "t2MOVsra_flag", 0, 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo32 }, // Inst #1605 = t2MOVsra_flag
+ { 1606, 2, 1, 113, "t2MOVsrl_flag", 0, 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo32 }, // Inst #1606 = t2MOVsrl_flag
+ { 1607, 3, 1, 128, "t2MRS", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1607 = t2MRS
+ { 1608, 3, 1, 128, "t2MRSsys", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1608 = t2MRSsys
+ { 1609, 3, 0, 128, "t2MSR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1609 = t2MSR
+ { 1610, 3, 0, 128, "t2MSRsys", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1610 = t2MSRsys
+ { 1611, 5, 1, 116, "t2MUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1611 = t2MUL
+ { 1612, 5, 1, 111, "t2MVNi", 0|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::HasOptionalDef)|(1<<TID::CheapAsAMove), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo46 }, // Inst #1612 = t2MVNi
+ { 1613, 4, 1, 112, "t2MVNr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1613 = t2MVNr
+ { 1614, 5, 1, 113, "t2MVNs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1614 = t2MVNs
+ { 1615, 2, 0, 128, "t2NOP", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1615 = t2NOP
+ { 1616, 6, 1, 88, "t2ORNri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1616 = t2ORNri
+ { 1617, 6, 1, 89, "t2ORNrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1617 = t2ORNrr
+ { 1618, 7, 1, 90, "t2ORNrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1618 = t2ORNrs
+ { 1619, 6, 1, 88, "t2ORRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1619 = t2ORRri
+ { 1620, 6, 1, 89, "t2ORRrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1620 = t2ORRrr
+ { 1621, 7, 1, 90, "t2ORRrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1621 = t2ORRrs
+ { 1622, 6, 1, 90, "t2PKHBT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1622 = t2PKHBT
+ { 1623, 6, 1, 90, "t2PKHTB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1623 = t2PKHTB
+ { 1624, 4, 0, 101, "t2PLDWi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1624 = t2PLDWi12
+ { 1625, 4, 0, 101, "t2PLDWi8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1625 = t2PLDWi8
+ { 1626, 4, 0, 101, "t2PLDWpci", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1626 = t2PLDWpci
+ { 1627, 4, 0, 101, "t2PLDWr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1627 = t2PLDWr
+ { 1628, 5, 0, 101, "t2PLDWs", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1628 = t2PLDWs
+ { 1629, 4, 0, 101, "t2PLDi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1629 = t2PLDi12
+ { 1630, 4, 0, 101, "t2PLDi8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1630 = t2PLDi8
+ { 1631, 4, 0, 101, "t2PLDpci", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1631 = t2PLDpci
+ { 1632, 4, 0, 101, "t2PLDr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1632 = t2PLDr
+ { 1633, 5, 0, 101, "t2PLDs", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1633 = t2PLDs
+ { 1634, 4, 0, 101, "t2PLIi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1634 = t2PLIi12
+ { 1635, 4, 0, 101, "t2PLIi8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1635 = t2PLIi8
+ { 1636, 4, 0, 101, "t2PLIpci", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo26 }, // Inst #1636 = t2PLIpci
+ { 1637, 4, 0, 101, "t2PLIr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1637 = t2PLIr
+ { 1638, 5, 0, 101, "t2PLIs", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1638 = t2PLIs
+ { 1639, 5, 1, 128, "t2QADD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1639 = t2QADD
+ { 1640, 5, 1, 128, "t2QADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1640 = t2QADD16
+ { 1641, 5, 1, 128, "t2QADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1641 = t2QADD8
+ { 1642, 5, 1, 128, "t2QASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1642 = t2QASX
+ { 1643, 5, 1, 128, "t2QDADD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1643 = t2QDADD
+ { 1644, 5, 1, 128, "t2QDSUB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1644 = t2QDSUB
+ { 1645, 5, 1, 128, "t2QSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1645 = t2QSAX
+ { 1646, 5, 1, 128, "t2QSUB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1646 = t2QSUB
+ { 1647, 5, 1, 128, "t2QSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1647 = t2QSUB16
+ { 1648, 5, 1, 128, "t2QSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1648 = t2QSUB8
+ { 1649, 4, 1, 125, "t2RBIT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1649 = t2RBIT
+ { 1650, 4, 1, 125, "t2REV", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1650 = t2REV
+ { 1651, 4, 1, 125, "t2REV16", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1651 = t2REV16
+ { 1652, 4, 1, 125, "t2REVSH", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1652 = t2REVSH
+ { 1653, 3, 0, 128, "t2RFEDB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1653 = t2RFEDB
+ { 1654, 3, 0, 128, "t2RFEDBW", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1654 = t2RFEDBW
+ { 1655, 3, 0, 128, "t2RFEIA", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1655 = t2RFEIA
+ { 1656, 3, 0, 128, "t2RFEIAW", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo21 }, // Inst #1656 = t2RFEIAW
+ { 1657, 6, 1, 113, "t2RORri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1657 = t2RORri
+ { 1658, 6, 1, 114, "t2RORrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1658 = t2RORrr
+ { 1659, 4, 1, 88, "t2RSBSri", 0|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo152 }, // Inst #1659 = t2RSBSri
+ { 1660, 5, 1, 90, "t2RSBSrs", 0|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo153 }, // Inst #1660 = t2RSBSrs
+ { 1661, 5, 1, 88, "t2RSBri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1661 = t2RSBri
+ { 1662, 6, 1, 90, "t2RSBrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1662 = t2RSBrs
+ { 1663, 5, 1, 128, "t2SADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1663 = t2SADD16
+ { 1664, 5, 1, 128, "t2SADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1664 = t2SADD8
+ { 1665, 5, 1, 128, "t2SASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1665 = t2SASX
+ { 1666, 6, 1, 88, "t2SBCSri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1666 = t2SBCSri
+ { 1667, 6, 1, 89, "t2SBCSrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1667 = t2SBCSrr
+ { 1668, 7, 1, 90, "t2SBCSrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #1668 = t2SBCSrs
+ { 1669, 6, 1, 88, "t2SBCri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo5 }, // Inst #1669 = t2SBCri
+ { 1670, 6, 1, 89, "t2SBCrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo6 }, // Inst #1670 = t2SBCrr
+ { 1671, 7, 1, 90, "t2SBCrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo48 }, // Inst #1671 = t2SBCrs
+ { 1672, 6, 1, 88, "t2SBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo51 }, // Inst #1672 = t2SBFX
+ { 1673, 5, 1, 88, "t2SDIV", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1673 = t2SDIV
+ { 1674, 5, 1, 128, "t2SEL", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1674 = t2SEL
+ { 1675, 2, 0, 128, "t2SEV", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1675 = t2SEV
+ { 1676, 5, 1, 128, "t2SHADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1676 = t2SHADD16
+ { 1677, 5, 1, 128, "t2SHADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1677 = t2SHADD8
+ { 1678, 5, 1, 128, "t2SHASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1678 = t2SHASX
+ { 1679, 5, 1, 128, "t2SHSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1679 = t2SHSAX
+ { 1680, 5, 1, 128, "t2SHSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1680 = t2SHSUB16
+ { 1681, 5, 1, 128, "t2SHSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1681 = t2SHSUB8
+ { 1682, 3, 0, 128, "t2SMC", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1682 = t2SMC
+ { 1683, 6, 1, 108, "t2SMLABB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1683 = t2SMLABB
+ { 1684, 6, 1, 108, "t2SMLABT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1684 = t2SMLABT
+ { 1685, 6, 1, 109, "t2SMLAD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1685 = t2SMLAD
+ { 1686, 6, 1, 109, "t2SMLADX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1686 = t2SMLADX
+ { 1687, 6, 2, 110, "t2SMLAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1687 = t2SMLAL
+ { 1688, 6, 2, 110, "t2SMLALBB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1688 = t2SMLALBB
+ { 1689, 6, 2, 110, "t2SMLALBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1689 = t2SMLALBT
+ { 1690, 6, 2, 110, "t2SMLALD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1690 = t2SMLALD
+ { 1691, 6, 2, 110, "t2SMLALDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1691 = t2SMLALDX
+ { 1692, 6, 2, 110, "t2SMLALTB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1692 = t2SMLALTB
+ { 1693, 6, 2, 110, "t2SMLALTT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1693 = t2SMLALTT
+ { 1694, 6, 1, 108, "t2SMLATB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1694 = t2SMLATB
+ { 1695, 6, 1, 108, "t2SMLATT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1695 = t2SMLATT
+ { 1696, 6, 1, 108, "t2SMLAWB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1696 = t2SMLAWB
+ { 1697, 6, 1, 108, "t2SMLAWT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1697 = t2SMLAWT
+ { 1698, 6, 1, 109, "t2SMLSD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1698 = t2SMLSD
+ { 1699, 6, 1, 109, "t2SMLSDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1699 = t2SMLSDX
+ { 1700, 6, 2, 110, "t2SMLSLD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1700 = t2SMLSLD
+ { 1701, 6, 2, 110, "t2SMLSLDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1701 = t2SMLSLDX
+ { 1702, 6, 1, 109, "t2SMMLA", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1702 = t2SMMLA
+ { 1703, 6, 1, 109, "t2SMMLAR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1703 = t2SMMLAR
+ { 1704, 6, 1, 109, "t2SMMLS", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1704 = t2SMMLS
+ { 1705, 6, 1, 109, "t2SMMLSR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1705 = t2SMMLSR
+ { 1706, 5, 1, 116, "t2SMMUL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1706 = t2SMMUL
+ { 1707, 5, 1, 116, "t2SMMULR", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1707 = t2SMMULR
+ { 1708, 5, 1, 109, "t2SMUAD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1708 = t2SMUAD
+ { 1709, 5, 1, 109, "t2SMUADX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1709 = t2SMUADX
+ { 1710, 5, 1, 116, "t2SMULBB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1710 = t2SMULBB
+ { 1711, 5, 1, 116, "t2SMULBT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1711 = t2SMULBT
+ { 1712, 6, 2, 117, "t2SMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1712 = t2SMULL
+ { 1713, 5, 1, 116, "t2SMULTB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1713 = t2SMULTB
+ { 1714, 5, 1, 116, "t2SMULTT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1714 = t2SMULTT
+ { 1715, 5, 1, 115, "t2SMULWB", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1715 = t2SMULWB
+ { 1716, 5, 1, 115, "t2SMULWT", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1716 = t2SMULWT
+ { 1717, 5, 1, 109, "t2SMUSD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1717 = t2SMUSD
+ { 1718, 5, 1, 109, "t2SMUSDX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1718 = t2SMUSDX
+ { 1719, 3, 0, 128, "t2SRSDB", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1719 = t2SRSDB
+ { 1720, 3, 0, 128, "t2SRSDBW", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1720 = t2SRSDBW
+ { 1721, 3, 0, 128, "t2SRSIA", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1721 = t2SRSIA
+ { 1722, 3, 0, 128, "t2SRSIAW", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1722 = t2SRSIAW
+ { 1723, 5, 1, 128, "t2SSAT16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo52 }, // Inst #1723 = t2SSAT16
+ { 1724, 6, 1, 128, "t2SSATasr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo53 }, // Inst #1724 = t2SSATasr
+ { 1725, 6, 1, 128, "t2SSATlsl", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo53 }, // Inst #1725 = t2SSATlsl
+ { 1726, 5, 1, 128, "t2SSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1726 = t2SSAX
+ { 1727, 5, 1, 128, "t2SSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1727 = t2SSUB16
+ { 1728, 5, 1, 128, "t2SSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1728 = t2SSUB8
+ { 1729, 5, 0, 120, "t2STM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #1729 = t2STM
+ { 1730, 5, 1, 118, "t2STRBT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1730 = t2STRBT
+ { 1731, 6, 1, 119, "t2STRB_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo154 }, // Inst #1731 = t2STRB_POST
+ { 1732, 6, 1, 119, "t2STRB_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo154 }, // Inst #1732 = t2STRB_PRE
+ { 1733, 5, 0, 118, "t2STRBi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1733 = t2STRBi12
+ { 1734, 5, 0, 118, "t2STRBi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1734 = t2STRBi8
+ { 1735, 6, 0, 121, "t2STRBs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1735 = t2STRBs
+ { 1736, 6, 0, 121, "t2STRDi8", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|15|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1736 = t2STRDi8
+ { 1737, 5, 1, 128, "t2STREX", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo56 }, // Inst #1737 = t2STREX
+ { 1738, 5, 1, 128, "t2STREXB", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo56 }, // Inst #1738 = t2STREXB
+ { 1739, 6, 1, 128, "t2STREXD", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo57 }, // Inst #1739 = t2STREXD
+ { 1740, 5, 1, 128, "t2STREXH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo56 }, // Inst #1740 = t2STREXH
+ { 1741, 5, 1, 118, "t2STRHT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1741 = t2STRHT
+ { 1742, 6, 1, 119, "t2STRH_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo154 }, // Inst #1742 = t2STRH_POST
+ { 1743, 6, 1, 119, "t2STRH_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo154 }, // Inst #1743 = t2STRH_PRE
+ { 1744, 5, 0, 118, "t2STRHi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1744 = t2STRHi12
+ { 1745, 5, 0, 118, "t2STRHi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1745 = t2STRHi8
+ { 1746, 6, 0, 121, "t2STRHs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1746 = t2STRHs
+ { 1747, 5, 1, 118, "t2STRT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1747 = t2STRT
+ { 1748, 6, 1, 119, "t2STR_POST", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(2<<7)|(23<<9), NULL, NULL, NULL, OperandInfo154 }, // Inst #1748 = t2STR_POST
+ { 1749, 6, 1, 119, "t2STR_PRE", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(1<<7)|(23<<9), NULL, NULL, NULL, OperandInfo154 }, // Inst #1749 = t2STR_PRE
+ { 1750, 5, 0, 118, "t2STRi12", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|11|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1750 = t2STRi12
+ { 1751, 5, 0, 118, "t2STRi8", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|12|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1751 = t2STRi8
+ { 1752, 6, 0, 121, "t2STRs", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|13|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1752 = t2STRs
+ { 1753, 5, 1, 88, "t2SUBSri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1753 = t2SUBSri
+ { 1754, 5, 1, 89, "t2SUBSrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1754 = t2SUBSrr
+ { 1755, 6, 1, 90, "t2SUBSrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo27 }, // Inst #1755 = t2SUBSrs
+ { 1756, 6, 1, 88, "t2SUBrSPi", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1756 = t2SUBrSPi
+ { 1757, 5, 1, 88, "t2SUBrSPi12", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1757 = t2SUBrSPi12
+ { 1758, 3, 1, 128, "t2SUBrSPi12_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1758 = t2SUBrSPi12_
+ { 1759, 3, 1, 128, "t2SUBrSPi_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1759 = t2SUBrSPi_
+ { 1760, 7, 1, 90, "t2SUBrSPs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1760 = t2SUBrSPs
+ { 1761, 4, 1, 128, "t2SUBrSPs_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo155 }, // Inst #1761 = t2SUBrSPs_
+ { 1762, 6, 1, 88, "t2SUBri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1762 = t2SUBri
+ { 1763, 6, 1, 88, "t2SUBri12", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo5 }, // Inst #1763 = t2SUBri12
+ { 1764, 6, 1, 89, "t2SUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo6 }, // Inst #1764 = t2SUBrr
+ { 1765, 7, 1, 90, "t2SUBrs", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo48 }, // Inst #1765 = t2SUBrs
+ { 1766, 5, 1, 89, "t2SXTAB16rr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1766 = t2SXTAB16rr
+ { 1767, 6, 1, 91, "t2SXTAB16rr_rot", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1767 = t2SXTAB16rr_rot
+ { 1768, 5, 1, 89, "t2SXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1768 = t2SXTABrr
+ { 1769, 6, 1, 91, "t2SXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1769 = t2SXTABrr_rot
+ { 1770, 5, 1, 89, "t2SXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1770 = t2SXTAHrr
+ { 1771, 6, 1, 91, "t2SXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1771 = t2SXTAHrr_rot
+ { 1772, 4, 1, 125, "t2SXTB16r", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1772 = t2SXTB16r
+ { 1773, 5, 1, 126, "t2SXTB16r_rot", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1773 = t2SXTB16r_rot
+ { 1774, 4, 1, 125, "t2SXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1774 = t2SXTBr
+ { 1775, 5, 1, 126, "t2SXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1775 = t2SXTBr_rot
+ { 1776, 4, 1, 125, "t2SXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1776 = t2SXTHr
+ { 1777, 5, 1, 126, "t2SXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1777 = t2SXTHr_rot
+ { 1778, 3, 0, 0, "t2TBB", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1778 = t2TBB
+ { 1779, 4, 0, 0, "t2TBBgen", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1779 = t2TBBgen
+ { 1780, 3, 0, 0, "t2TBH", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo28 }, // Inst #1780 = t2TBH
+ { 1781, 4, 0, 0, "t2TBHgen", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::NotDuplicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1781 = t2TBHgen
+ { 1782, 4, 0, 97, "t2TEQri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #1782 = t2TEQri
+ { 1783, 4, 0, 98, "t2TEQrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1783 = t2TEQrr
+ { 1784, 5, 0, 99, "t2TEQrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1784 = t2TEQrs
+ { 1785, 0, 0, 0, "t2TPsoft", 0|(1<<TID::Call), 0|(3<<4)|(23<<9), NULL, ImplicitList7, Barriers1, 0 }, // Inst #1785 = t2TPsoft
+ { 1786, 4, 0, 97, "t2TSTri", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo26 }, // Inst #1786 = t2TSTri
+ { 1787, 4, 0, 98, "t2TSTrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1787 = t2TSTrr
+ { 1788, 5, 0, 99, "t2TSTrs", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1788 = t2TSTrs
+ { 1789, 5, 1, 128, "t2UADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1789 = t2UADD16
+ { 1790, 5, 1, 128, "t2UADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1790 = t2UADD8
+ { 1791, 5, 1, 128, "t2UASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1791 = t2UASX
+ { 1792, 6, 1, 88, "t2UBFX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo51 }, // Inst #1792 = t2UBFX
+ { 1793, 5, 1, 88, "t2UDIV", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1793 = t2UDIV
+ { 1794, 5, 1, 128, "t2UHADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1794 = t2UHADD16
+ { 1795, 5, 1, 128, "t2UHADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1795 = t2UHADD8
+ { 1796, 5, 1, 128, "t2UHASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1796 = t2UHASX
+ { 1797, 5, 1, 128, "t2UHSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1797 = t2UHSAX
+ { 1798, 5, 1, 128, "t2UHSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1798 = t2UHSUB16
+ { 1799, 5, 1, 128, "t2UHSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1799 = t2UHSUB8
+ { 1800, 6, 2, 110, "t2UMAAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1800 = t2UMAAL
+ { 1801, 6, 2, 110, "t2UMLAL", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1801 = t2UMLAL
+ { 1802, 6, 2, 117, "t2UMULL", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1802 = t2UMULL
+ { 1803, 5, 1, 128, "t2UQADD16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1803 = t2UQADD16
+ { 1804, 5, 1, 128, "t2UQADD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1804 = t2UQADD8
+ { 1805, 5, 1, 128, "t2UQASX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1805 = t2UQASX
+ { 1806, 5, 1, 128, "t2UQSAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1806 = t2UQSAX
+ { 1807, 5, 1, 128, "t2UQSUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1807 = t2UQSUB16
+ { 1808, 5, 1, 128, "t2UQSUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1808 = t2UQSUB8
+ { 1809, 5, 1, 128, "t2USAD8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1809 = t2USAD8
+ { 1810, 6, 1, 128, "t2USADA8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo43 }, // Inst #1810 = t2USADA8
+ { 1811, 5, 1, 128, "t2USAT16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo52 }, // Inst #1811 = t2USAT16
+ { 1812, 6, 1, 128, "t2USATasr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo53 }, // Inst #1812 = t2USATasr
+ { 1813, 6, 1, 128, "t2USATlsl", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo53 }, // Inst #1813 = t2USATlsl
+ { 1814, 5, 1, 128, "t2USAX", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1814 = t2USAX
+ { 1815, 5, 1, 128, "t2USUB16", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1815 = t2USUB16
+ { 1816, 5, 1, 128, "t2USUB8", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1816 = t2USUB8
+ { 1817, 5, 1, 89, "t2UXTAB16rr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1817 = t2UXTAB16rr
+ { 1818, 6, 1, 91, "t2UXTAB16rr_rot", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1818 = t2UXTAB16rr_rot
+ { 1819, 5, 1, 89, "t2UXTABrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1819 = t2UXTABrr
+ { 1820, 6, 1, 91, "t2UXTABrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1820 = t2UXTABrr_rot
+ { 1821, 5, 1, 89, "t2UXTAHrr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo9 }, // Inst #1821 = t2UXTAHrr
+ { 1822, 6, 1, 91, "t2UXTAHrr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo27 }, // Inst #1822 = t2UXTAHrr_rot
+ { 1823, 4, 1, 125, "t2UXTB16r", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1823 = t2UXTB16r
+ { 1824, 5, 1, 126, "t2UXTB16r_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1824 = t2UXTB16r_rot
+ { 1825, 4, 1, 125, "t2UXTBr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1825 = t2UXTBr
+ { 1826, 5, 1, 126, "t2UXTBr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1826 = t2UXTBr_rot
+ { 1827, 4, 1, 125, "t2UXTHr", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo25 }, // Inst #1827 = t2UXTHr
+ { 1828, 5, 1, 126, "t2UXTHr_rot", 0|(1<<TID::Predicable), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo8 }, // Inst #1828 = t2UXTHr_rot
+ { 1829, 2, 0, 128, "t2WFE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1829 = t2WFE
+ { 1830, 2, 0, 128, "t2WFI", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1830 = t2WFI
+ { 1831, 2, 0, 128, "t2YIELD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1831 = t2YIELD
+ { 1832, 6, 2, 89, "tADC", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo156 }, // Inst #1832 = tADC
+ { 1833, 5, 1, 89, "tADDhirr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo44 }, // Inst #1833 = tADDhirr
+ { 1834, 6, 2, 88, "tADDi3", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 }, // Inst #1834 = tADDi3
+ { 1835, 6, 2, 88, "tADDi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo158 }, // Inst #1835 = tADDi8
+ { 1836, 2, 1, 88, "tADDrPCi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo159 }, // Inst #1836 = tADDrPCi
+ { 1837, 3, 1, 89, "tADDrSP", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo160 }, // Inst #1837 = tADDrSP
+ { 1838, 3, 1, 88, "tADDrSPi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo161 }, // Inst #1838 = tADDrSPi
+ { 1839, 6, 2, 89, "tADDrr", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1839 = tADDrr
+ { 1840, 3, 1, 88, "tADDspi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo163 }, // Inst #1840 = tADDspi
+ { 1841, 3, 1, 89, "tADDspr", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo160 }, // Inst #1841 = tADDspr
+ { 1842, 3, 1, 128, "tADDspr_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo3 }, // Inst #1842 = tADDspr_
+ { 1843, 1, 0, 128, "tADJCALLSTACKDOWN", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo14 }, // Inst #1843 = tADJCALLSTACKDOWN
+ { 1844, 2, 0, 128, "tADJCALLSTACKUP", 0|(1<<TID::UnmodeledSideEffects), 0|(1<<4), ImplicitList2, ImplicitList2, NULL, OperandInfo148 }, // Inst #1844 = tADJCALLSTACKUP
+ { 1845, 6, 2, 89, "tAND", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1845 = tAND
+ { 1846, 3, 1, 128, "tANDsp", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, ImplicitList1, Barriers1, OperandInfo164 }, // Inst #1846 = tANDsp
+ { 1847, 6, 2, 113, "tASRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 }, // Inst #1847 = tASRri
+ { 1848, 6, 2, 114, "tASRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1848 = tASRrr
+ { 1849, 1, 0, 0, "tB", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Predicable)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1849 = tB
+ { 1850, 6, 2, 89, "tBIC", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1850 = tBIC
+ { 1851, 1, 0, 128, "tBKPT", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1851 = tBKPT
+ { 1852, 1, 0, 0, "tBL", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo14 }, // Inst #1852 = tBL
+ { 1853, 1, 0, 0, "tBLXi", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo14 }, // Inst #1853 = tBLXi
+ { 1854, 1, 0, 0, "tBLXi_r9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo14 }, // Inst #1854 = tBLXi_r9
+ { 1855, 1, 0, 0, "tBLXr", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(4<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo16 }, // Inst #1855 = tBLXr
+ { 1856, 1, 0, 0, "tBLXr_r9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(4<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo16 }, // Inst #1856 = tBLXr_r9
+ { 1857, 1, 0, 0, "tBLr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo14 }, // Inst #1857 = tBLr9
+ { 1858, 1, 0, 0, "tBRIND", 0|(1<<TID::Branch)|(1<<TID::IndirectBranch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo16 }, // Inst #1858 = tBRIND
+ { 1859, 3, 0, 0, "tBR_JTr", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(1<<4)|(23<<9), NULL, NULL, NULL, OperandInfo165 }, // Inst #1859 = tBR_JTr
+ { 1860, 1, 0, 0, "tBX", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList3, Barriers2, OperandInfo17 }, // Inst #1860 = tBX
+ { 1861, 0, 0, 0, "tBX_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator), 0|(4<<4)|(23<<9), NULL, NULL, NULL, 0 }, // Inst #1861 = tBX_RET
+ { 1862, 1, 0, 0, "tBX_RET_vararg", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo17 }, // Inst #1862 = tBX_RET_vararg
+ { 1863, 1, 0, 0, "tBXr9", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|(3<<4)|(23<<9), NULL, ImplicitList4, Barriers2, OperandInfo17 }, // Inst #1863 = tBXr9
+ { 1864, 3, 0, 0, "tBcc", 0|(1<<TID::Branch)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1864 = tBcc
+ { 1865, 1, 0, 0, "tBfar", 0|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(3<<4)|(23<<9), NULL, ImplicitList8, NULL, OperandInfo14 }, // Inst #1865 = tBfar
+ { 1866, 2, 0, 0, "tCBNZ", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo159 }, // Inst #1866 = tCBNZ
+ { 1867, 2, 0, 0, "tCBZ", 0|(1<<TID::Branch)|(1<<TID::Terminator)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo159 }, // Inst #1867 = tCBZ
+ { 1868, 4, 0, 98, "tCMNz", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo166 }, // Inst #1868 = tCMNz
+ { 1869, 4, 0, 98, "tCMPhir", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1869 = tCMPhir
+ { 1870, 4, 0, 97, "tCMPi8", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo167 }, // Inst #1870 = tCMPi8
+ { 1871, 4, 0, 98, "tCMPr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo166 }, // Inst #1871 = tCMPr
+ { 1872, 4, 0, 98, "tCMPzhir", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo25 }, // Inst #1872 = tCMPzhir
+ { 1873, 4, 0, 97, "tCMPzi8", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo167 }, // Inst #1873 = tCMPzi8
+ { 1874, 4, 0, 98, "tCMPzr", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo166 }, // Inst #1874 = tCMPzr
+ { 1875, 1, 0, 128, "tCPS", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo14 }, // Inst #1875 = tCPS
+ { 1876, 6, 2, 89, "tEOR", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1876 = tEOR
+ { 1877, 2, 0, 128, "tInt_eh_sjlj_setjmp", 0, 0|(1<<4)|(23<<9), NULL, ImplicitList9, Barriers4, OperandInfo168 }, // Inst #1877 = tInt_eh_sjlj_setjmp
+ { 1878, 5, 0, 103, "tLDM", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #1878 = tLDM
+ { 1879, 6, 1, 104, "tLDR", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1879 = tLDR
+ { 1880, 6, 1, 104, "tLDRB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1880 = tLDRB
+ { 1881, 6, 1, 104, "tLDRBi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1881 = tLDRBi
+ { 1882, 6, 1, 104, "tLDRH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1882 = tLDRH
+ { 1883, 6, 1, 104, "tLDRHi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1883 = tLDRHi
+ { 1884, 5, 1, 104, "tLDRSB", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo170 }, // Inst #1884 = tLDRSB
+ { 1885, 5, 1, 104, "tLDRSH", 0|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo170 }, // Inst #1885 = tLDRSH
+ { 1886, 4, 1, 101, "tLDRcp", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo167 }, // Inst #1886 = tLDRcp
+ { 1887, 6, 1, 104, "tLDRi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1887 = tLDRi
+ { 1888, 4, 1, 101, "tLDRpci", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Rematerializable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo167 }, // Inst #1888 = tLDRpci
+ { 1889, 3, 1, 128, "tLDRpci_pic", 0|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|(1<<4), NULL, NULL, NULL, OperandInfo20 }, // Inst #1889 = tLDRpci_pic
+ { 1890, 5, 1, 101, "tLDRspi", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo171 }, // Inst #1890 = tLDRspi
+ { 1891, 4, 1, 88, "tLEApcrel", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo167 }, // Inst #1891 = tLEApcrel
+ { 1892, 5, 1, 88, "tLEApcrelJT", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo172 }, // Inst #1892 = tLEApcrelJT
+ { 1893, 6, 2, 113, "tLSLri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 }, // Inst #1893 = tLSLri
+ { 1894, 6, 2, 114, "tLSLrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1894 = tLSLrr
+ { 1895, 6, 2, 113, "tLSRri", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 }, // Inst #1895 = tLSRri
+ { 1896, 6, 2, 114, "tLSRrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1896 = tLSRrr
+ { 1897, 5, 1, 93, "tMOVCCi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo173 }, // Inst #1897 = tMOVCCi
+ { 1898, 5, 1, 94, "tMOVCCr", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo44 }, // Inst #1898 = tMOVCCr
+ { 1899, 5, 1, 128, "tMOVCCr_pseudo", 0|(1<<TID::Predicable)|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo170 }, // Inst #1899 = tMOVCCr_pseudo
+ { 1900, 2, 1, 112, "tMOVSr", 0, 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo168 }, // Inst #1900 = tMOVSr
+ { 1901, 2, 1, 112, "tMOVgpr2gpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo32 }, // Inst #1901 = tMOVgpr2gpr
+ { 1902, 2, 1, 112, "tMOVgpr2tgpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo174 }, // Inst #1902 = tMOVgpr2tgpr
+ { 1903, 5, 2, 111, "tMOVi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo175 }, // Inst #1903 = tMOVi8
+ { 1904, 2, 1, 112, "tMOVr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo168 }, // Inst #1904 = tMOVr
+ { 1905, 2, 1, 112, "tMOVtgpr2gpr", 0, 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo149 }, // Inst #1905 = tMOVtgpr2gpr
+ { 1906, 6, 2, 116, "tMUL", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1906 = tMUL
+ { 1907, 5, 2, 112, "tMVN", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo176 }, // Inst #1907 = tMVN
+ { 1908, 2, 0, 128, "tNOP", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1908 = tNOP
+ { 1909, 6, 2, 89, "tORR", 0|(1<<TID::Predicable)|(1<<TID::Commutable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1909 = tORR
+ { 1910, 3, 1, 89, "tPICADD", 0|(1<<TID::NotDuplicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo163 }, // Inst #1910 = tPICADD
+ { 1911, 3, 0, 0, "tPOP", 0|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), ImplicitList2, ImplicitList2, NULL, OperandInfo177 }, // Inst #1911 = tPOP
+ { 1912, 3, 0, 0, "tPOP_RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraDefRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo177 }, // Inst #1912 = tPOP_RET
+ { 1913, 3, 0, 0, "tPUSH", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(4<<4)|(23<<9), ImplicitList2, ImplicitList2, NULL, OperandInfo177 }, // Inst #1913 = tPUSH
+ { 1914, 4, 1, 125, "tREV", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 }, // Inst #1914 = tREV
+ { 1915, 4, 1, 125, "tREV16", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 }, // Inst #1915 = tREV16
+ { 1916, 4, 1, 125, "tREVSH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 }, // Inst #1916 = tREVSH
+ { 1917, 6, 2, 114, "tROR", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo156 }, // Inst #1917 = tROR
+ { 1918, 5, 2, 88, "tRSB", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo176 }, // Inst #1918 = tRSB
+ { 1919, 5, 1, 101, "tRestore", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo171 }, // Inst #1919 = tRestore
+ { 1920, 6, 2, 89, "tSBC", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), ImplicitList1, NULL, NULL, OperandInfo156 }, // Inst #1920 = tSBC
+ { 1921, 0, 0, 128, "tSETENDBE", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, 0 }, // Inst #1921 = tSETENDBE
+ { 1922, 0, 0, 128, "tSETENDLE", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, 0 }, // Inst #1922 = tSETENDLE
+ { 1923, 2, 0, 128, "tSEV", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1923 = tSEV
+ { 1924, 5, 0, 120, "tSTM", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects)|(1<<TID::ExtraSrcRegAllocReq), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo35 }, // Inst #1924 = tSTM
+ { 1925, 6, 0, 121, "tSTR", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1925 = tSTR
+ { 1926, 6, 0, 121, "tSTRB", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1926 = tSTRB
+ { 1927, 6, 0, 121, "tSTRBi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|7|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1927 = tSTRBi
+ { 1928, 6, 0, 121, "tSTRH", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1928 = tSTRH
+ { 1929, 6, 0, 121, "tSTRHi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|8|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1929 = tSTRHi
+ { 1930, 6, 0, 121, "tSTRi", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|9|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo169 }, // Inst #1930 = tSTRi
+ { 1931, 5, 0, 118, "tSTRspi", 0|(1<<TID::MayStore)|(1<<TID::Predicable), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo171 }, // Inst #1931 = tSTRspi
+ { 1932, 6, 2, 88, "tSUBi3", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo157 }, // Inst #1932 = tSUBi3
+ { 1933, 6, 2, 88, "tSUBi8", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo158 }, // Inst #1933 = tSUBi8
+ { 1934, 6, 2, 89, "tSUBrr", 0|(1<<TID::Predicable)|(1<<TID::HasOptionalDef), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo162 }, // Inst #1934 = tSUBrr
+ { 1935, 3, 1, 88, "tSUBspi", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo163 }, // Inst #1935 = tSUBspi
+ { 1936, 3, 1, 128, "tSUBspi_", 0|(1<<TID::UsesCustomInserter)|(1<<TID::UnmodeledSideEffects), 0|(1<<4), NULL, NULL, NULL, OperandInfo2 }, // Inst #1936 = tSUBspi_
+ { 1937, 3, 0, 0, "tSVC", 0|(1<<TID::Call)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo11 }, // Inst #1937 = tSVC
+ { 1938, 4, 1, 125, "tSXTB", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 }, // Inst #1938 = tSXTB
+ { 1939, 4, 1, 125, "tSXTH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 }, // Inst #1939 = tSXTH
+ { 1940, 5, 0, 118, "tSpill", 0|(1<<TID::MayStore)|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|10|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo171 }, // Inst #1940 = tSpill
+ { 1941, 0, 0, 0, "tTPsoft", 0|(1<<TID::Call), 0|(3<<4)|(23<<9), NULL, ImplicitList10, NULL, 0 }, // Inst #1941 = tTPsoft
+ { 1942, 0, 0, 0, "tTRAP", 0|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, 0 }, // Inst #1942 = tTRAP
+ { 1943, 4, 0, 98, "tTST", 0|(1<<TID::Predicable)|(1<<TID::Commutable), 0|(4<<4)|(23<<9), NULL, ImplicitList1, Barriers1, OperandInfo166 }, // Inst #1943 = tTST
+ { 1944, 4, 1, 125, "tUXTB", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 }, // Inst #1944 = tUXTB
+ { 1945, 4, 1, 125, "tUXTH", 0|(1<<TID::Predicable), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo166 }, // Inst #1945 = tUXTH
+ { 1946, 2, 0, 128, "tWFE", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1946 = tWFE
+ { 1947, 2, 0, 128, "tWFI", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1947 = tWFI
+ { 1948, 2, 0, 128, "tYIELD", 0|(1<<TID::Predicable)|(1<<TID::UnmodeledSideEffects), 0|(4<<4)|(23<<9), NULL, NULL, NULL, OperandInfo22 }, // Inst #1948 = tYIELD
};
} // End llvm namespace
diff --git a/libclamav/c++/ARMGenInstrNames.inc b/libclamav/c++/ARMGenInstrNames.inc
index 4f6ccea..db1f6bb 100644
--- a/libclamav/c++/ARMGenInstrNames.inc
+++ b/libclamav/c++/ARMGenInstrNames.inc
@@ -76,1886 +76,1890 @@ namespace ARM {
BL_pred = 63,
BLr9 = 64,
BLr9_pred = 65,
- BRIND = 66,
- BR_JTadd = 67,
- BR_JTm = 68,
- BR_JTr = 69,
- BX = 70,
- BXJ = 71,
- BX_RET = 72,
- BXr9 = 73,
- Bcc = 74,
- CDP = 75,
- CDP2 = 76,
- CLREX = 77,
- CLZ = 78,
- CMNzri = 79,
- CMNzrr = 80,
- CMNzrs = 81,
- CMPri = 82,
- CMPrr = 83,
- CMPrs = 84,
- CMPzri = 85,
- CMPzrr = 86,
- CMPzrs = 87,
- CONSTPOOL_ENTRY = 88,
- CPS = 89,
- DBG = 90,
- DMBish = 91,
- DMBishst = 92,
- DMBnsh = 93,
- DMBnshst = 94,
- DMBosh = 95,
- DMBoshst = 96,
- DMBst = 97,
- DSBish = 98,
- DSBishst = 99,
- DSBnsh = 100,
- DSBnshst = 101,
- DSBosh = 102,
- DSBoshst = 103,
- DSBst = 104,
- EORri = 105,
- EORrr = 106,
- EORrs = 107,
- FCONSTD = 108,
- FCONSTS = 109,
- FMSTAT = 110,
- ISBsy = 111,
- Int_MemBarrierV6 = 112,
- Int_MemBarrierV7 = 113,
- Int_SyncBarrierV6 = 114,
- Int_SyncBarrierV7 = 115,
- Int_eh_sjlj_setjmp = 116,
- LDC2L_OFFSET = 117,
- LDC2L_OPTION = 118,
- LDC2L_POST = 119,
- LDC2L_PRE = 120,
- LDC2_OFFSET = 121,
- LDC2_OPTION = 122,
- LDC2_POST = 123,
- LDC2_PRE = 124,
- LDCL_OFFSET = 125,
- LDCL_OPTION = 126,
- LDCL_POST = 127,
- LDCL_PRE = 128,
- LDC_OFFSET = 129,
- LDC_OPTION = 130,
- LDC_POST = 131,
- LDC_PRE = 132,
- LDM = 133,
- LDM_RET = 134,
- LDR = 135,
- LDRB = 136,
- LDRBT = 137,
- LDRB_POST = 138,
- LDRB_PRE = 139,
- LDRD = 140,
- LDRD_POST = 141,
- LDRD_PRE = 142,
- LDREX = 143,
- LDREXB = 144,
- LDREXD = 145,
- LDREXH = 146,
- LDRH = 147,
- LDRHT = 148,
- LDRH_POST = 149,
- LDRH_PRE = 150,
- LDRSB = 151,
- LDRSBT = 152,
- LDRSB_POST = 153,
- LDRSB_PRE = 154,
- LDRSH = 155,
- LDRSHT = 156,
- LDRSH_POST = 157,
- LDRSH_PRE = 158,
- LDRT = 159,
- LDR_POST = 160,
- LDR_PRE = 161,
- LDRcp = 162,
- LEApcrel = 163,
- LEApcrelJT = 164,
- MCR = 165,
- MCR2 = 166,
- MCRR = 167,
- MCRR2 = 168,
- MLA = 169,
- MLS = 170,
- MOVCCi = 171,
- MOVCCr = 172,
- MOVCCs = 173,
- MOVTi16 = 174,
- MOVi = 175,
- MOVi16 = 176,
- MOVi2pieces = 177,
- MOVi32imm = 178,
- MOVr = 179,
- MOVrx = 180,
- MOVs = 181,
- MOVsra_flag = 182,
- MOVsrl_flag = 183,
- MRC = 184,
- MRC2 = 185,
- MRRC = 186,
- MRRC2 = 187,
- MRS = 188,
- MRSsys = 189,
- MSR = 190,
- MSRi = 191,
- MSRsys = 192,
- MSRsysi = 193,
- MUL = 194,
- MVNi = 195,
- MVNr = 196,
- MVNs = 197,
- NOP = 198,
- ORRri = 199,
- ORRrr = 200,
- ORRrs = 201,
- PICADD = 202,
- PICLDR = 203,
- PICLDRB = 204,
- PICLDRH = 205,
- PICLDRSB = 206,
- PICLDRSH = 207,
- PICSTR = 208,
- PICSTRB = 209,
- PICSTRH = 210,
- PKHBT = 211,
- PKHTB = 212,
- PLDWi = 213,
- PLDWr = 214,
- PLDi = 215,
- PLDr = 216,
- PLIi = 217,
- PLIr = 218,
- QADD = 219,
- QADD16 = 220,
- QADD8 = 221,
- QASX = 222,
- QDADD = 223,
- QDSUB = 224,
- QSAX = 225,
- QSUB = 226,
- QSUB16 = 227,
- QSUB8 = 228,
- RBIT = 229,
- REV = 230,
- REV16 = 231,
- REVSH = 232,
- RFE = 233,
- RFEW = 234,
- RSBSri = 235,
- RSBSrs = 236,
- RSBri = 237,
- RSBrs = 238,
- RSCSri = 239,
- RSCSrs = 240,
- RSCri = 241,
- RSCrs = 242,
- SADD16 = 243,
- SADD8 = 244,
- SASX = 245,
- SBCSSri = 246,
- SBCSSrr = 247,
- SBCSSrs = 248,
- SBCri = 249,
- SBCrr = 250,
- SBCrs = 251,
- SBFX = 252,
- SEL = 253,
- SETENDBE = 254,
- SETENDLE = 255,
- SEV = 256,
- SHADD16 = 257,
- SHADD8 = 258,
- SHASX = 259,
- SHSAX = 260,
- SHSUB16 = 261,
- SHSUB8 = 262,
- SMC = 263,
- SMLABB = 264,
- SMLABT = 265,
- SMLAD = 266,
- SMLADX = 267,
- SMLAL = 268,
- SMLALBB = 269,
- SMLALBT = 270,
- SMLALD = 271,
- SMLALDX = 272,
- SMLALTB = 273,
- SMLALTT = 274,
- SMLATB = 275,
- SMLATT = 276,
- SMLAWB = 277,
- SMLAWT = 278,
- SMLSD = 279,
- SMLSDX = 280,
- SMLSLD = 281,
- SMLSLDX = 282,
- SMMLA = 283,
- SMMLAR = 284,
- SMMLS = 285,
- SMMLSR = 286,
- SMMUL = 287,
- SMMULR = 288,
- SMUAD = 289,
- SMUADX = 290,
- SMULBB = 291,
- SMULBT = 292,
- SMULL = 293,
- SMULTB = 294,
- SMULTT = 295,
- SMULWB = 296,
- SMULWT = 297,
- SMUSD = 298,
- SMUSDX = 299,
- SRS = 300,
- SRSW = 301,
- SSAT16 = 302,
- SSATasr = 303,
- SSATlsl = 304,
- SSAX = 305,
- SSUB16 = 306,
- SSUB8 = 307,
- STC2L_OFFSET = 308,
- STC2L_OPTION = 309,
- STC2L_POST = 310,
- STC2L_PRE = 311,
- STC2_OFFSET = 312,
- STC2_OPTION = 313,
- STC2_POST = 314,
- STC2_PRE = 315,
- STCL_OFFSET = 316,
- STCL_OPTION = 317,
- STCL_POST = 318,
- STCL_PRE = 319,
- STC_OFFSET = 320,
- STC_OPTION = 321,
- STC_POST = 322,
- STC_PRE = 323,
- STM = 324,
- STR = 325,
- STRB = 326,
- STRBT = 327,
- STRB_POST = 328,
- STRB_PRE = 329,
- STRD = 330,
- STRD_POST = 331,
- STRD_PRE = 332,
- STREX = 333,
- STREXB = 334,
- STREXD = 335,
- STREXH = 336,
- STRH = 337,
- STRHT = 338,
- STRH_POST = 339,
- STRH_PRE = 340,
- STRT = 341,
- STR_POST = 342,
- STR_PRE = 343,
- SUBSri = 344,
- SUBSrr = 345,
- SUBSrs = 346,
- SUBri = 347,
- SUBrr = 348,
- SUBrs = 349,
- SVC = 350,
- SWP = 351,
- SWPB = 352,
- SXTAB16rr = 353,
- SXTAB16rr_rot = 354,
- SXTABrr = 355,
- SXTABrr_rot = 356,
- SXTAHrr = 357,
- SXTAHrr_rot = 358,
- SXTB16r = 359,
- SXTB16r_rot = 360,
- SXTBr = 361,
- SXTBr_rot = 362,
- SXTHr = 363,
- SXTHr_rot = 364,
- TEQri = 365,
- TEQrr = 366,
- TEQrs = 367,
- TPsoft = 368,
- TRAP = 369,
- TSTri = 370,
- TSTrr = 371,
- TSTrs = 372,
- UADD16 = 373,
- UADD8 = 374,
- UASX = 375,
- UBFX = 376,
- UHADD16 = 377,
- UHADD8 = 378,
- UHASX = 379,
- UHSAX = 380,
- UHSUB16 = 381,
- UHSUB8 = 382,
- UMAAL = 383,
- UMLAL = 384,
- UMULL = 385,
- UQADD16 = 386,
- UQADD8 = 387,
- UQASX = 388,
- UQSAX = 389,
- UQSUB16 = 390,
- UQSUB8 = 391,
- USAD8 = 392,
- USADA8 = 393,
- USAT16 = 394,
- USATasr = 395,
- USATlsl = 396,
- USAX = 397,
- USUB16 = 398,
- USUB8 = 399,
- UXTAB16rr = 400,
- UXTAB16rr_rot = 401,
- UXTABrr = 402,
- UXTABrr_rot = 403,
- UXTAHrr = 404,
- UXTAHrr_rot = 405,
- UXTB16r = 406,
- UXTB16r_rot = 407,
- UXTBr = 408,
- UXTBr_rot = 409,
- UXTHr = 410,
- UXTHr_rot = 411,
- VABALsv2i64 = 412,
- VABALsv4i32 = 413,
- VABALsv8i16 = 414,
- VABALuv2i64 = 415,
- VABALuv4i32 = 416,
- VABALuv8i16 = 417,
- VABAsv16i8 = 418,
- VABAsv2i32 = 419,
- VABAsv4i16 = 420,
- VABAsv4i32 = 421,
- VABAsv8i16 = 422,
- VABAsv8i8 = 423,
- VABAuv16i8 = 424,
- VABAuv2i32 = 425,
- VABAuv4i16 = 426,
- VABAuv4i32 = 427,
- VABAuv8i16 = 428,
- VABAuv8i8 = 429,
- VABDLsv2i64 = 430,
- VABDLsv4i32 = 431,
- VABDLsv8i16 = 432,
- VABDLuv2i64 = 433,
- VABDLuv4i32 = 434,
- VABDLuv8i16 = 435,
- VABDfd = 436,
- VABDfq = 437,
- VABDsv16i8 = 438,
- VABDsv2i32 = 439,
- VABDsv4i16 = 440,
- VABDsv4i32 = 441,
- VABDsv8i16 = 442,
- VABDsv8i8 = 443,
- VABDuv16i8 = 444,
- VABDuv2i32 = 445,
- VABDuv4i16 = 446,
- VABDuv4i32 = 447,
- VABDuv8i16 = 448,
- VABDuv8i8 = 449,
- VABSD = 450,
- VABSS = 451,
- VABSfd = 452,
- VABSfd_sfp = 453,
- VABSfq = 454,
- VABSv16i8 = 455,
- VABSv2i32 = 456,
- VABSv4i16 = 457,
- VABSv4i32 = 458,
- VABSv8i16 = 459,
- VABSv8i8 = 460,
- VACGEd = 461,
- VACGEq = 462,
- VACGTd = 463,
- VACGTq = 464,
- VADDD = 465,
- VADDHNv2i32 = 466,
- VADDHNv4i16 = 467,
- VADDHNv8i8 = 468,
- VADDLsv2i64 = 469,
- VADDLsv4i32 = 470,
- VADDLsv8i16 = 471,
- VADDLuv2i64 = 472,
- VADDLuv4i32 = 473,
- VADDLuv8i16 = 474,
- VADDS = 475,
- VADDWsv2i64 = 476,
- VADDWsv4i32 = 477,
- VADDWsv8i16 = 478,
- VADDWuv2i64 = 479,
- VADDWuv4i32 = 480,
- VADDWuv8i16 = 481,
- VADDfd = 482,
- VADDfd_sfp = 483,
- VADDfq = 484,
- VADDv16i8 = 485,
- VADDv1i64 = 486,
- VADDv2i32 = 487,
- VADDv2i64 = 488,
- VADDv4i16 = 489,
- VADDv4i32 = 490,
- VADDv8i16 = 491,
- VADDv8i8 = 492,
- VANDd = 493,
- VANDq = 494,
- VBICd = 495,
- VBICq = 496,
- VBIFd = 497,
- VBIFq = 498,
- VBITd = 499,
- VBITq = 500,
- VBSLd = 501,
- VBSLq = 502,
- VCEQfd = 503,
- VCEQfq = 504,
- VCEQv16i8 = 505,
- VCEQv2i32 = 506,
- VCEQv4i16 = 507,
- VCEQv4i32 = 508,
- VCEQv8i16 = 509,
- VCEQv8i8 = 510,
- VCEQzv16i8 = 511,
- VCEQzv2f32 = 512,
- VCEQzv2i32 = 513,
- VCEQzv4f32 = 514,
- VCEQzv4i16 = 515,
- VCEQzv4i32 = 516,
- VCEQzv8i16 = 517,
- VCEQzv8i8 = 518,
- VCGEfd = 519,
- VCGEfq = 520,
- VCGEsv16i8 = 521,
- VCGEsv2i32 = 522,
- VCGEsv4i16 = 523,
- VCGEsv4i32 = 524,
- VCGEsv8i16 = 525,
- VCGEsv8i8 = 526,
- VCGEuv16i8 = 527,
- VCGEuv2i32 = 528,
- VCGEuv4i16 = 529,
- VCGEuv4i32 = 530,
- VCGEuv8i16 = 531,
- VCGEuv8i8 = 532,
- VCGEzv16i8 = 533,
- VCGEzv2f32 = 534,
- VCGEzv2i32 = 535,
- VCGEzv4f32 = 536,
- VCGEzv4i16 = 537,
- VCGEzv4i32 = 538,
- VCGEzv8i16 = 539,
- VCGEzv8i8 = 540,
- VCGTfd = 541,
- VCGTfq = 542,
- VCGTsv16i8 = 543,
- VCGTsv2i32 = 544,
- VCGTsv4i16 = 545,
- VCGTsv4i32 = 546,
- VCGTsv8i16 = 547,
- VCGTsv8i8 = 548,
- VCGTuv16i8 = 549,
- VCGTuv2i32 = 550,
- VCGTuv4i16 = 551,
- VCGTuv4i32 = 552,
- VCGTuv8i16 = 553,
- VCGTuv8i8 = 554,
- VCGTzv16i8 = 555,
- VCGTzv2f32 = 556,
- VCGTzv2i32 = 557,
- VCGTzv4f32 = 558,
- VCGTzv4i16 = 559,
- VCGTzv4i32 = 560,
- VCGTzv8i16 = 561,
- VCGTzv8i8 = 562,
- VCLEzv16i8 = 563,
- VCLEzv2f32 = 564,
- VCLEzv2i32 = 565,
- VCLEzv4f32 = 566,
- VCLEzv4i16 = 567,
- VCLEzv4i32 = 568,
- VCLEzv8i16 = 569,
- VCLEzv8i8 = 570,
- VCLSv16i8 = 571,
- VCLSv2i32 = 572,
- VCLSv4i16 = 573,
- VCLSv4i32 = 574,
- VCLSv8i16 = 575,
- VCLSv8i8 = 576,
- VCLTzv16i8 = 577,
- VCLTzv2f32 = 578,
- VCLTzv2i32 = 579,
- VCLTzv4f32 = 580,
- VCLTzv4i16 = 581,
- VCLTzv4i32 = 582,
- VCLTzv8i16 = 583,
- VCLTzv8i8 = 584,
- VCLZv16i8 = 585,
- VCLZv2i32 = 586,
- VCLZv4i16 = 587,
- VCLZv4i32 = 588,
- VCLZv8i16 = 589,
- VCLZv8i8 = 590,
- VCMPD = 591,
- VCMPED = 592,
- VCMPES = 593,
- VCMPEZD = 594,
- VCMPEZS = 595,
- VCMPS = 596,
- VCMPZD = 597,
- VCMPZS = 598,
- VCNTd = 599,
- VCNTq = 600,
- VCVTBHS = 601,
- VCVTBSH = 602,
- VCVTDS = 603,
- VCVTSD = 604,
- VCVTTHS = 605,
- VCVTTSH = 606,
- VCVTf2sd = 607,
- VCVTf2sd_sfp = 608,
- VCVTf2sq = 609,
- VCVTf2ud = 610,
- VCVTf2ud_sfp = 611,
- VCVTf2uq = 612,
- VCVTf2xsd = 613,
- VCVTf2xsq = 614,
- VCVTf2xud = 615,
- VCVTf2xuq = 616,
- VCVTs2fd = 617,
- VCVTs2fd_sfp = 618,
- VCVTs2fq = 619,
- VCVTu2fd = 620,
- VCVTu2fd_sfp = 621,
- VCVTu2fq = 622,
- VCVTxs2fd = 623,
- VCVTxs2fq = 624,
- VCVTxu2fd = 625,
- VCVTxu2fq = 626,
- VDIVD = 627,
- VDIVS = 628,
- VDUP16d = 629,
- VDUP16q = 630,
- VDUP32d = 631,
- VDUP32q = 632,
- VDUP8d = 633,
- VDUP8q = 634,
- VDUPLN16d = 635,
- VDUPLN16q = 636,
- VDUPLN32d = 637,
- VDUPLN32q = 638,
- VDUPLN8d = 639,
- VDUPLN8q = 640,
- VDUPLNfd = 641,
- VDUPLNfq = 642,
- VDUPfd = 643,
- VDUPfdf = 644,
- VDUPfq = 645,
- VDUPfqf = 646,
- VEORd = 647,
- VEORq = 648,
- VEXTd16 = 649,
- VEXTd32 = 650,
- VEXTd8 = 651,
- VEXTdf = 652,
- VEXTq16 = 653,
- VEXTq32 = 654,
- VEXTq8 = 655,
- VEXTqf = 656,
- VGETLNi32 = 657,
- VGETLNs16 = 658,
- VGETLNs8 = 659,
- VGETLNu16 = 660,
- VGETLNu8 = 661,
- VHADDsv16i8 = 662,
- VHADDsv2i32 = 663,
- VHADDsv4i16 = 664,
- VHADDsv4i32 = 665,
- VHADDsv8i16 = 666,
- VHADDsv8i8 = 667,
- VHADDuv16i8 = 668,
- VHADDuv2i32 = 669,
- VHADDuv4i16 = 670,
- VHADDuv4i32 = 671,
- VHADDuv8i16 = 672,
- VHADDuv8i8 = 673,
- VHSUBsv16i8 = 674,
- VHSUBsv2i32 = 675,
- VHSUBsv4i16 = 676,
- VHSUBsv4i32 = 677,
- VHSUBsv8i16 = 678,
- VHSUBsv8i8 = 679,
- VHSUBuv16i8 = 680,
- VHSUBuv2i32 = 681,
- VHSUBuv4i16 = 682,
- VHSUBuv4i32 = 683,
- VHSUBuv8i16 = 684,
- VHSUBuv8i8 = 685,
- VLD1d16 = 686,
- VLD1d16Q = 687,
- VLD1d16T = 688,
- VLD1d32 = 689,
- VLD1d32Q = 690,
- VLD1d32T = 691,
- VLD1d64 = 692,
- VLD1d8 = 693,
- VLD1d8Q = 694,
- VLD1d8T = 695,
- VLD1df = 696,
- VLD1q16 = 697,
- VLD1q32 = 698,
- VLD1q64 = 699,
- VLD1q8 = 700,
- VLD1qf = 701,
- VLD2LNd16 = 702,
- VLD2LNd32 = 703,
- VLD2LNd8 = 704,
- VLD2LNq16a = 705,
- VLD2LNq16b = 706,
- VLD2LNq32a = 707,
- VLD2LNq32b = 708,
- VLD2d16 = 709,
- VLD2d16D = 710,
- VLD2d32 = 711,
- VLD2d32D = 712,
- VLD2d64 = 713,
- VLD2d8 = 714,
- VLD2d8D = 715,
- VLD2q16 = 716,
- VLD2q32 = 717,
- VLD2q8 = 718,
- VLD3LNd16 = 719,
- VLD3LNd32 = 720,
- VLD3LNd8 = 721,
- VLD3LNq16a = 722,
- VLD3LNq16b = 723,
- VLD3LNq32a = 724,
- VLD3LNq32b = 725,
- VLD3d16 = 726,
- VLD3d32 = 727,
- VLD3d64 = 728,
- VLD3d8 = 729,
- VLD3q16a = 730,
- VLD3q16b = 731,
- VLD3q32a = 732,
- VLD3q32b = 733,
- VLD3q8a = 734,
- VLD3q8b = 735,
- VLD4LNd16 = 736,
- VLD4LNd32 = 737,
- VLD4LNd8 = 738,
- VLD4LNq16a = 739,
- VLD4LNq16b = 740,
- VLD4LNq32a = 741,
- VLD4LNq32b = 742,
- VLD4d16 = 743,
- VLD4d32 = 744,
- VLD4d64 = 745,
- VLD4d8 = 746,
- VLD4q16a = 747,
- VLD4q16b = 748,
- VLD4q32a = 749,
- VLD4q32b = 750,
- VLD4q8a = 751,
- VLD4q8b = 752,
- VLDMD = 753,
- VLDMS = 754,
- VLDRD = 755,
- VLDRQ = 756,
- VLDRS = 757,
- VMAXfd = 758,
- VMAXfd_sfp = 759,
- VMAXfq = 760,
- VMAXsv16i8 = 761,
- VMAXsv2i32 = 762,
- VMAXsv4i16 = 763,
- VMAXsv4i32 = 764,
- VMAXsv8i16 = 765,
- VMAXsv8i8 = 766,
- VMAXuv16i8 = 767,
- VMAXuv2i32 = 768,
- VMAXuv4i16 = 769,
- VMAXuv4i32 = 770,
- VMAXuv8i16 = 771,
- VMAXuv8i8 = 772,
- VMINfd = 773,
- VMINfd_sfp = 774,
- VMINfq = 775,
- VMINsv16i8 = 776,
- VMINsv2i32 = 777,
- VMINsv4i16 = 778,
- VMINsv4i32 = 779,
- VMINsv8i16 = 780,
- VMINsv8i8 = 781,
- VMINuv16i8 = 782,
- VMINuv2i32 = 783,
- VMINuv4i16 = 784,
- VMINuv4i32 = 785,
- VMINuv8i16 = 786,
- VMINuv8i8 = 787,
- VMLAD = 788,
- VMLALslsv2i32 = 789,
- VMLALslsv4i16 = 790,
- VMLALsluv2i32 = 791,
- VMLALsluv4i16 = 792,
- VMLALsv2i64 = 793,
- VMLALsv4i32 = 794,
- VMLALsv8i16 = 795,
- VMLALuv2i64 = 796,
- VMLALuv4i32 = 797,
- VMLALuv8i16 = 798,
- VMLAS = 799,
- VMLAfd = 800,
- VMLAfq = 801,
- VMLAslfd = 802,
- VMLAslfq = 803,
- VMLAslv2i32 = 804,
- VMLAslv4i16 = 805,
- VMLAslv4i32 = 806,
- VMLAslv8i16 = 807,
- VMLAv16i8 = 808,
- VMLAv2i32 = 809,
- VMLAv4i16 = 810,
- VMLAv4i32 = 811,
- VMLAv8i16 = 812,
- VMLAv8i8 = 813,
- VMLSD = 814,
- VMLSLslsv2i32 = 815,
- VMLSLslsv4i16 = 816,
- VMLSLsluv2i32 = 817,
- VMLSLsluv4i16 = 818,
- VMLSLsv2i64 = 819,
- VMLSLsv4i32 = 820,
- VMLSLsv8i16 = 821,
- VMLSLuv2i64 = 822,
- VMLSLuv4i32 = 823,
- VMLSLuv8i16 = 824,
- VMLSS = 825,
- VMLSfd = 826,
- VMLSfq = 827,
- VMLSslfd = 828,
- VMLSslfq = 829,
- VMLSslv2i32 = 830,
- VMLSslv4i16 = 831,
- VMLSslv4i32 = 832,
- VMLSslv8i16 = 833,
- VMLSv16i8 = 834,
- VMLSv2i32 = 835,
- VMLSv4i16 = 836,
- VMLSv4i32 = 837,
- VMLSv8i16 = 838,
- VMLSv8i8 = 839,
- VMOVD = 840,
- VMOVDRR = 841,
- VMOVDcc = 842,
- VMOVDneon = 843,
- VMOVLsv2i64 = 844,
- VMOVLsv4i32 = 845,
- VMOVLsv8i16 = 846,
- VMOVLuv2i64 = 847,
- VMOVLuv4i32 = 848,
- VMOVLuv8i16 = 849,
- VMOVNv2i32 = 850,
- VMOVNv4i16 = 851,
- VMOVNv8i8 = 852,
- VMOVQ = 853,
- VMOVRRD = 854,
- VMOVRRS = 855,
- VMOVRS = 856,
- VMOVS = 857,
- VMOVSR = 858,
- VMOVSRR = 859,
- VMOVScc = 860,
- VMOVv16i8 = 861,
- VMOVv1i64 = 862,
- VMOVv2i32 = 863,
- VMOVv2i64 = 864,
- VMOVv4i16 = 865,
- VMOVv4i32 = 866,
- VMOVv8i16 = 867,
- VMOVv8i8 = 868,
- VMRS = 869,
- VMSR = 870,
- VMULD = 871,
- VMULLp = 872,
- VMULLslsv2i32 = 873,
- VMULLslsv4i16 = 874,
- VMULLsluv2i32 = 875,
- VMULLsluv4i16 = 876,
- VMULLsv2i64 = 877,
- VMULLsv4i32 = 878,
- VMULLsv8i16 = 879,
- VMULLuv2i64 = 880,
- VMULLuv4i32 = 881,
- VMULLuv8i16 = 882,
- VMULS = 883,
- VMULfd = 884,
- VMULfd_sfp = 885,
- VMULfq = 886,
- VMULpd = 887,
- VMULpq = 888,
- VMULslfd = 889,
- VMULslfq = 890,
- VMULslv2i32 = 891,
- VMULslv4i16 = 892,
- VMULslv4i32 = 893,
- VMULslv8i16 = 894,
- VMULv16i8 = 895,
- VMULv2i32 = 896,
- VMULv4i16 = 897,
- VMULv4i32 = 898,
- VMULv8i16 = 899,
- VMULv8i8 = 900,
- VMVNd = 901,
- VMVNq = 902,
- VNEGD = 903,
- VNEGDcc = 904,
- VNEGS = 905,
- VNEGScc = 906,
- VNEGf32q = 907,
- VNEGfd = 908,
- VNEGfd_sfp = 909,
- VNEGs16d = 910,
- VNEGs16q = 911,
- VNEGs32d = 912,
- VNEGs32q = 913,
- VNEGs8d = 914,
- VNEGs8q = 915,
- VNMLAD = 916,
- VNMLAS = 917,
- VNMLSD = 918,
- VNMLSS = 919,
- VNMULD = 920,
- VNMULS = 921,
- VORNd = 922,
- VORNq = 923,
- VORRd = 924,
- VORRq = 925,
- VPADALsv16i8 = 926,
- VPADALsv2i32 = 927,
- VPADALsv4i16 = 928,
- VPADALsv4i32 = 929,
- VPADALsv8i16 = 930,
- VPADALsv8i8 = 931,
- VPADALuv16i8 = 932,
- VPADALuv2i32 = 933,
- VPADALuv4i16 = 934,
- VPADALuv4i32 = 935,
- VPADALuv8i16 = 936,
- VPADALuv8i8 = 937,
- VPADDLsv16i8 = 938,
- VPADDLsv2i32 = 939,
- VPADDLsv4i16 = 940,
- VPADDLsv4i32 = 941,
- VPADDLsv8i16 = 942,
- VPADDLsv8i8 = 943,
- VPADDLuv16i8 = 944,
- VPADDLuv2i32 = 945,
- VPADDLuv4i16 = 946,
- VPADDLuv4i32 = 947,
- VPADDLuv8i16 = 948,
- VPADDLuv8i8 = 949,
- VPADDf = 950,
- VPADDi16 = 951,
- VPADDi32 = 952,
- VPADDi8 = 953,
- VPMAXf = 954,
- VPMAXs16 = 955,
- VPMAXs32 = 956,
- VPMAXs8 = 957,
- VPMAXu16 = 958,
- VPMAXu32 = 959,
- VPMAXu8 = 960,
- VPMINf = 961,
- VPMINs16 = 962,
- VPMINs32 = 963,
- VPMINs8 = 964,
- VPMINu16 = 965,
- VPMINu32 = 966,
- VPMINu8 = 967,
- VQABSv16i8 = 968,
- VQABSv2i32 = 969,
- VQABSv4i16 = 970,
- VQABSv4i32 = 971,
- VQABSv8i16 = 972,
- VQABSv8i8 = 973,
- VQADDsv16i8 = 974,
- VQADDsv1i64 = 975,
- VQADDsv2i32 = 976,
- VQADDsv2i64 = 977,
- VQADDsv4i16 = 978,
- VQADDsv4i32 = 979,
- VQADDsv8i16 = 980,
- VQADDsv8i8 = 981,
- VQADDuv16i8 = 982,
- VQADDuv1i64 = 983,
- VQADDuv2i32 = 984,
- VQADDuv2i64 = 985,
- VQADDuv4i16 = 986,
- VQADDuv4i32 = 987,
- VQADDuv8i16 = 988,
- VQADDuv8i8 = 989,
- VQDMLALslv2i32 = 990,
- VQDMLALslv4i16 = 991,
- VQDMLALv2i64 = 992,
- VQDMLALv4i32 = 993,
- VQDMLSLslv2i32 = 994,
- VQDMLSLslv4i16 = 995,
- VQDMLSLv2i64 = 996,
- VQDMLSLv4i32 = 997,
- VQDMULHslv2i32 = 998,
- VQDMULHslv4i16 = 999,
- VQDMULHslv4i32 = 1000,
- VQDMULHslv8i16 = 1001,
- VQDMULHv2i32 = 1002,
- VQDMULHv4i16 = 1003,
- VQDMULHv4i32 = 1004,
- VQDMULHv8i16 = 1005,
- VQDMULLslv2i32 = 1006,
- VQDMULLslv4i16 = 1007,
- VQDMULLv2i64 = 1008,
- VQDMULLv4i32 = 1009,
- VQMOVNsuv2i32 = 1010,
- VQMOVNsuv4i16 = 1011,
- VQMOVNsuv8i8 = 1012,
- VQMOVNsv2i32 = 1013,
- VQMOVNsv4i16 = 1014,
- VQMOVNsv8i8 = 1015,
- VQMOVNuv2i32 = 1016,
- VQMOVNuv4i16 = 1017,
- VQMOVNuv8i8 = 1018,
- VQNEGv16i8 = 1019,
- VQNEGv2i32 = 1020,
- VQNEGv4i16 = 1021,
- VQNEGv4i32 = 1022,
- VQNEGv8i16 = 1023,
- VQNEGv8i8 = 1024,
- VQRDMULHslv2i32 = 1025,
- VQRDMULHslv4i16 = 1026,
- VQRDMULHslv4i32 = 1027,
- VQRDMULHslv8i16 = 1028,
- VQRDMULHv2i32 = 1029,
- VQRDMULHv4i16 = 1030,
- VQRDMULHv4i32 = 1031,
- VQRDMULHv8i16 = 1032,
- VQRSHLsv16i8 = 1033,
- VQRSHLsv1i64 = 1034,
- VQRSHLsv2i32 = 1035,
- VQRSHLsv2i64 = 1036,
- VQRSHLsv4i16 = 1037,
- VQRSHLsv4i32 = 1038,
- VQRSHLsv8i16 = 1039,
- VQRSHLsv8i8 = 1040,
- VQRSHLuv16i8 = 1041,
- VQRSHLuv1i64 = 1042,
- VQRSHLuv2i32 = 1043,
- VQRSHLuv2i64 = 1044,
- VQRSHLuv4i16 = 1045,
- VQRSHLuv4i32 = 1046,
- VQRSHLuv8i16 = 1047,
- VQRSHLuv8i8 = 1048,
- VQRSHRNsv2i32 = 1049,
- VQRSHRNsv4i16 = 1050,
- VQRSHRNsv8i8 = 1051,
- VQRSHRNuv2i32 = 1052,
- VQRSHRNuv4i16 = 1053,
- VQRSHRNuv8i8 = 1054,
- VQRSHRUNv2i32 = 1055,
- VQRSHRUNv4i16 = 1056,
- VQRSHRUNv8i8 = 1057,
- VQSHLsiv16i8 = 1058,
- VQSHLsiv1i64 = 1059,
- VQSHLsiv2i32 = 1060,
- VQSHLsiv2i64 = 1061,
- VQSHLsiv4i16 = 1062,
- VQSHLsiv4i32 = 1063,
- VQSHLsiv8i16 = 1064,
- VQSHLsiv8i8 = 1065,
- VQSHLsuv16i8 = 1066,
- VQSHLsuv1i64 = 1067,
- VQSHLsuv2i32 = 1068,
- VQSHLsuv2i64 = 1069,
- VQSHLsuv4i16 = 1070,
- VQSHLsuv4i32 = 1071,
- VQSHLsuv8i16 = 1072,
- VQSHLsuv8i8 = 1073,
- VQSHLsv16i8 = 1074,
- VQSHLsv1i64 = 1075,
- VQSHLsv2i32 = 1076,
- VQSHLsv2i64 = 1077,
- VQSHLsv4i16 = 1078,
- VQSHLsv4i32 = 1079,
- VQSHLsv8i16 = 1080,
- VQSHLsv8i8 = 1081,
- VQSHLuiv16i8 = 1082,
- VQSHLuiv1i64 = 1083,
- VQSHLuiv2i32 = 1084,
- VQSHLuiv2i64 = 1085,
- VQSHLuiv4i16 = 1086,
- VQSHLuiv4i32 = 1087,
- VQSHLuiv8i16 = 1088,
- VQSHLuiv8i8 = 1089,
- VQSHLuv16i8 = 1090,
- VQSHLuv1i64 = 1091,
- VQSHLuv2i32 = 1092,
- VQSHLuv2i64 = 1093,
- VQSHLuv4i16 = 1094,
- VQSHLuv4i32 = 1095,
- VQSHLuv8i16 = 1096,
- VQSHLuv8i8 = 1097,
- VQSHRNsv2i32 = 1098,
- VQSHRNsv4i16 = 1099,
- VQSHRNsv8i8 = 1100,
- VQSHRNuv2i32 = 1101,
- VQSHRNuv4i16 = 1102,
- VQSHRNuv8i8 = 1103,
- VQSHRUNv2i32 = 1104,
- VQSHRUNv4i16 = 1105,
- VQSHRUNv8i8 = 1106,
- VQSUBsv16i8 = 1107,
- VQSUBsv1i64 = 1108,
- VQSUBsv2i32 = 1109,
- VQSUBsv2i64 = 1110,
- VQSUBsv4i16 = 1111,
- VQSUBsv4i32 = 1112,
- VQSUBsv8i16 = 1113,
- VQSUBsv8i8 = 1114,
- VQSUBuv16i8 = 1115,
- VQSUBuv1i64 = 1116,
- VQSUBuv2i32 = 1117,
- VQSUBuv2i64 = 1118,
- VQSUBuv4i16 = 1119,
- VQSUBuv4i32 = 1120,
- VQSUBuv8i16 = 1121,
- VQSUBuv8i8 = 1122,
- VRADDHNv2i32 = 1123,
- VRADDHNv4i16 = 1124,
- VRADDHNv8i8 = 1125,
- VRECPEd = 1126,
- VRECPEfd = 1127,
- VRECPEfq = 1128,
- VRECPEq = 1129,
- VRECPSfd = 1130,
- VRECPSfq = 1131,
- VREV16d8 = 1132,
- VREV16q8 = 1133,
- VREV32d16 = 1134,
- VREV32d8 = 1135,
- VREV32q16 = 1136,
- VREV32q8 = 1137,
- VREV64d16 = 1138,
- VREV64d32 = 1139,
- VREV64d8 = 1140,
- VREV64df = 1141,
- VREV64q16 = 1142,
- VREV64q32 = 1143,
- VREV64q8 = 1144,
- VREV64qf = 1145,
- VRHADDsv16i8 = 1146,
- VRHADDsv2i32 = 1147,
- VRHADDsv4i16 = 1148,
- VRHADDsv4i32 = 1149,
- VRHADDsv8i16 = 1150,
- VRHADDsv8i8 = 1151,
- VRHADDuv16i8 = 1152,
- VRHADDuv2i32 = 1153,
- VRHADDuv4i16 = 1154,
- VRHADDuv4i32 = 1155,
- VRHADDuv8i16 = 1156,
- VRHADDuv8i8 = 1157,
- VRSHLsv16i8 = 1158,
- VRSHLsv1i64 = 1159,
- VRSHLsv2i32 = 1160,
- VRSHLsv2i64 = 1161,
- VRSHLsv4i16 = 1162,
- VRSHLsv4i32 = 1163,
- VRSHLsv8i16 = 1164,
- VRSHLsv8i8 = 1165,
- VRSHLuv16i8 = 1166,
- VRSHLuv1i64 = 1167,
- VRSHLuv2i32 = 1168,
- VRSHLuv2i64 = 1169,
- VRSHLuv4i16 = 1170,
- VRSHLuv4i32 = 1171,
- VRSHLuv8i16 = 1172,
- VRSHLuv8i8 = 1173,
- VRSHRNv2i32 = 1174,
- VRSHRNv4i16 = 1175,
- VRSHRNv8i8 = 1176,
- VRSHRsv16i8 = 1177,
- VRSHRsv1i64 = 1178,
- VRSHRsv2i32 = 1179,
- VRSHRsv2i64 = 1180,
- VRSHRsv4i16 = 1181,
- VRSHRsv4i32 = 1182,
- VRSHRsv8i16 = 1183,
- VRSHRsv8i8 = 1184,
- VRSHRuv16i8 = 1185,
- VRSHRuv1i64 = 1186,
- VRSHRuv2i32 = 1187,
- VRSHRuv2i64 = 1188,
- VRSHRuv4i16 = 1189,
- VRSHRuv4i32 = 1190,
- VRSHRuv8i16 = 1191,
- VRSHRuv8i8 = 1192,
- VRSQRTEd = 1193,
- VRSQRTEfd = 1194,
- VRSQRTEfq = 1195,
- VRSQRTEq = 1196,
- VRSQRTSfd = 1197,
- VRSQRTSfq = 1198,
- VRSRAsv16i8 = 1199,
- VRSRAsv1i64 = 1200,
- VRSRAsv2i32 = 1201,
- VRSRAsv2i64 = 1202,
- VRSRAsv4i16 = 1203,
- VRSRAsv4i32 = 1204,
- VRSRAsv8i16 = 1205,
- VRSRAsv8i8 = 1206,
- VRSRAuv16i8 = 1207,
- VRSRAuv1i64 = 1208,
- VRSRAuv2i32 = 1209,
- VRSRAuv2i64 = 1210,
- VRSRAuv4i16 = 1211,
- VRSRAuv4i32 = 1212,
- VRSRAuv8i16 = 1213,
- VRSRAuv8i8 = 1214,
- VRSUBHNv2i32 = 1215,
- VRSUBHNv4i16 = 1216,
- VRSUBHNv8i8 = 1217,
- VSETLNi16 = 1218,
- VSETLNi32 = 1219,
- VSETLNi8 = 1220,
- VSHLLi16 = 1221,
- VSHLLi32 = 1222,
- VSHLLi8 = 1223,
- VSHLLsv2i64 = 1224,
- VSHLLsv4i32 = 1225,
- VSHLLsv8i16 = 1226,
- VSHLLuv2i64 = 1227,
- VSHLLuv4i32 = 1228,
- VSHLLuv8i16 = 1229,
- VSHLiv16i8 = 1230,
- VSHLiv1i64 = 1231,
- VSHLiv2i32 = 1232,
- VSHLiv2i64 = 1233,
- VSHLiv4i16 = 1234,
- VSHLiv4i32 = 1235,
- VSHLiv8i16 = 1236,
- VSHLiv8i8 = 1237,
- VSHLsv16i8 = 1238,
- VSHLsv1i64 = 1239,
- VSHLsv2i32 = 1240,
- VSHLsv2i64 = 1241,
- VSHLsv4i16 = 1242,
- VSHLsv4i32 = 1243,
- VSHLsv8i16 = 1244,
- VSHLsv8i8 = 1245,
- VSHLuv16i8 = 1246,
- VSHLuv1i64 = 1247,
- VSHLuv2i32 = 1248,
- VSHLuv2i64 = 1249,
- VSHLuv4i16 = 1250,
- VSHLuv4i32 = 1251,
- VSHLuv8i16 = 1252,
- VSHLuv8i8 = 1253,
- VSHRNv2i32 = 1254,
- VSHRNv4i16 = 1255,
- VSHRNv8i8 = 1256,
- VSHRsv16i8 = 1257,
- VSHRsv1i64 = 1258,
- VSHRsv2i32 = 1259,
- VSHRsv2i64 = 1260,
- VSHRsv4i16 = 1261,
- VSHRsv4i32 = 1262,
- VSHRsv8i16 = 1263,
- VSHRsv8i8 = 1264,
- VSHRuv16i8 = 1265,
- VSHRuv1i64 = 1266,
- VSHRuv2i32 = 1267,
- VSHRuv2i64 = 1268,
- VSHRuv4i16 = 1269,
- VSHRuv4i32 = 1270,
- VSHRuv8i16 = 1271,
- VSHRuv8i8 = 1272,
- VSHTOD = 1273,
- VSHTOS = 1274,
- VSITOD = 1275,
- VSITOS = 1276,
- VSLIv16i8 = 1277,
- VSLIv1i64 = 1278,
- VSLIv2i32 = 1279,
- VSLIv2i64 = 1280,
- VSLIv4i16 = 1281,
- VSLIv4i32 = 1282,
- VSLIv8i16 = 1283,
- VSLIv8i8 = 1284,
- VSLTOD = 1285,
- VSLTOS = 1286,
- VSQRTD = 1287,
- VSQRTS = 1288,
- VSRAsv16i8 = 1289,
- VSRAsv1i64 = 1290,
- VSRAsv2i32 = 1291,
- VSRAsv2i64 = 1292,
- VSRAsv4i16 = 1293,
- VSRAsv4i32 = 1294,
- VSRAsv8i16 = 1295,
- VSRAsv8i8 = 1296,
- VSRAuv16i8 = 1297,
- VSRAuv1i64 = 1298,
- VSRAuv2i32 = 1299,
- VSRAuv2i64 = 1300,
- VSRAuv4i16 = 1301,
- VSRAuv4i32 = 1302,
- VSRAuv8i16 = 1303,
- VSRAuv8i8 = 1304,
- VSRIv16i8 = 1305,
- VSRIv1i64 = 1306,
- VSRIv2i32 = 1307,
- VSRIv2i64 = 1308,
- VSRIv4i16 = 1309,
- VSRIv4i32 = 1310,
- VSRIv8i16 = 1311,
- VSRIv8i8 = 1312,
- VST1d16 = 1313,
- VST1d16Q = 1314,
- VST1d16T = 1315,
- VST1d32 = 1316,
- VST1d32Q = 1317,
- VST1d32T = 1318,
- VST1d64 = 1319,
- VST1d8 = 1320,
- VST1d8Q = 1321,
- VST1d8T = 1322,
- VST1df = 1323,
- VST1q16 = 1324,
- VST1q32 = 1325,
- VST1q64 = 1326,
- VST1q8 = 1327,
- VST1qf = 1328,
- VST2LNd16 = 1329,
- VST2LNd32 = 1330,
- VST2LNd8 = 1331,
- VST2LNq16a = 1332,
- VST2LNq16b = 1333,
- VST2LNq32a = 1334,
- VST2LNq32b = 1335,
- VST2d16 = 1336,
- VST2d16D = 1337,
- VST2d32 = 1338,
- VST2d32D = 1339,
- VST2d64 = 1340,
- VST2d8 = 1341,
- VST2d8D = 1342,
- VST2q16 = 1343,
- VST2q32 = 1344,
- VST2q8 = 1345,
- VST3LNd16 = 1346,
- VST3LNd32 = 1347,
- VST3LNd8 = 1348,
- VST3LNq16a = 1349,
- VST3LNq16b = 1350,
- VST3LNq32a = 1351,
- VST3LNq32b = 1352,
- VST3d16 = 1353,
- VST3d32 = 1354,
- VST3d64 = 1355,
- VST3d8 = 1356,
- VST3q16a = 1357,
- VST3q16b = 1358,
- VST3q32a = 1359,
- VST3q32b = 1360,
- VST3q8a = 1361,
- VST3q8b = 1362,
- VST4LNd16 = 1363,
- VST4LNd32 = 1364,
- VST4LNd8 = 1365,
- VST4LNq16a = 1366,
- VST4LNq16b = 1367,
- VST4LNq32a = 1368,
- VST4LNq32b = 1369,
- VST4d16 = 1370,
- VST4d32 = 1371,
- VST4d64 = 1372,
- VST4d8 = 1373,
- VST4q16a = 1374,
- VST4q16b = 1375,
- VST4q32a = 1376,
- VST4q32b = 1377,
- VST4q8a = 1378,
- VST4q8b = 1379,
- VSTMD = 1380,
- VSTMS = 1381,
- VSTRD = 1382,
- VSTRQ = 1383,
- VSTRS = 1384,
- VSUBD = 1385,
- VSUBHNv2i32 = 1386,
- VSUBHNv4i16 = 1387,
- VSUBHNv8i8 = 1388,
- VSUBLsv2i64 = 1389,
- VSUBLsv4i32 = 1390,
- VSUBLsv8i16 = 1391,
- VSUBLuv2i64 = 1392,
- VSUBLuv4i32 = 1393,
- VSUBLuv8i16 = 1394,
- VSUBS = 1395,
- VSUBWsv2i64 = 1396,
- VSUBWsv4i32 = 1397,
- VSUBWsv8i16 = 1398,
- VSUBWuv2i64 = 1399,
- VSUBWuv4i32 = 1400,
- VSUBWuv8i16 = 1401,
- VSUBfd = 1402,
- VSUBfd_sfp = 1403,
- VSUBfq = 1404,
- VSUBv16i8 = 1405,
- VSUBv1i64 = 1406,
- VSUBv2i32 = 1407,
- VSUBv2i64 = 1408,
- VSUBv4i16 = 1409,
- VSUBv4i32 = 1410,
- VSUBv8i16 = 1411,
- VSUBv8i8 = 1412,
- VSWPd = 1413,
- VSWPq = 1414,
- VTBL1 = 1415,
- VTBL2 = 1416,
- VTBL3 = 1417,
- VTBL4 = 1418,
- VTBX1 = 1419,
- VTBX2 = 1420,
- VTBX3 = 1421,
- VTBX4 = 1422,
- VTOSHD = 1423,
- VTOSHS = 1424,
- VTOSIRD = 1425,
- VTOSIRS = 1426,
- VTOSIZD = 1427,
- VTOSIZS = 1428,
- VTOSLD = 1429,
- VTOSLS = 1430,
- VTOUHD = 1431,
- VTOUHS = 1432,
- VTOUIRD = 1433,
- VTOUIRS = 1434,
- VTOUIZD = 1435,
- VTOUIZS = 1436,
- VTOULD = 1437,
- VTOULS = 1438,
- VTRNd16 = 1439,
- VTRNd32 = 1440,
- VTRNd8 = 1441,
- VTRNq16 = 1442,
- VTRNq32 = 1443,
- VTRNq8 = 1444,
- VTSTv16i8 = 1445,
- VTSTv2i32 = 1446,
- VTSTv4i16 = 1447,
- VTSTv4i32 = 1448,
- VTSTv8i16 = 1449,
- VTSTv8i8 = 1450,
- VUHTOD = 1451,
- VUHTOS = 1452,
- VUITOD = 1453,
- VUITOS = 1454,
- VULTOD = 1455,
- VULTOS = 1456,
- VUZPd16 = 1457,
- VUZPd32 = 1458,
- VUZPd8 = 1459,
- VUZPq16 = 1460,
- VUZPq32 = 1461,
- VUZPq8 = 1462,
- VZIPd16 = 1463,
- VZIPd32 = 1464,
- VZIPd8 = 1465,
- VZIPq16 = 1466,
- VZIPq32 = 1467,
- VZIPq8 = 1468,
- WFE = 1469,
- WFI = 1470,
- YIELD = 1471,
- t2ADCSri = 1472,
- t2ADCSrr = 1473,
- t2ADCSrs = 1474,
- t2ADCri = 1475,
- t2ADCrr = 1476,
- t2ADCrs = 1477,
- t2ADDSri = 1478,
- t2ADDSrr = 1479,
- t2ADDSrs = 1480,
- t2ADDrSPi = 1481,
- t2ADDrSPi12 = 1482,
- t2ADDrSPs = 1483,
- t2ADDri = 1484,
- t2ADDri12 = 1485,
- t2ADDrr = 1486,
- t2ADDrs = 1487,
- t2ANDri = 1488,
- t2ANDrr = 1489,
- t2ANDrs = 1490,
- t2ASRri = 1491,
- t2ASRrr = 1492,
- t2B = 1493,
- t2BFC = 1494,
- t2BFI = 1495,
- t2BICri = 1496,
- t2BICrr = 1497,
- t2BICrs = 1498,
- t2BR_JT = 1499,
- t2BXJ = 1500,
- t2Bcc = 1501,
- t2CLREX = 1502,
- t2CLZ = 1503,
- t2CMNzri = 1504,
- t2CMNzrr = 1505,
- t2CMNzrs = 1506,
- t2CMPri = 1507,
- t2CMPrr = 1508,
- t2CMPrs = 1509,
- t2CMPzri = 1510,
- t2CMPzrr = 1511,
- t2CMPzrs = 1512,
- t2CPS = 1513,
- t2DBG = 1514,
- t2DMBish = 1515,
- t2DMBishst = 1516,
- t2DMBnsh = 1517,
- t2DMBnshst = 1518,
- t2DMBosh = 1519,
- t2DMBoshst = 1520,
- t2DMBst = 1521,
- t2DSBish = 1522,
- t2DSBishst = 1523,
- t2DSBnsh = 1524,
- t2DSBnshst = 1525,
- t2DSBosh = 1526,
- t2DSBoshst = 1527,
- t2DSBst = 1528,
- t2EORri = 1529,
- t2EORrr = 1530,
- t2EORrs = 1531,
- t2ISBsy = 1532,
- t2IT = 1533,
- t2Int_MemBarrierV7 = 1534,
- t2Int_SyncBarrierV7 = 1535,
- t2Int_eh_sjlj_setjmp = 1536,
- t2LDM = 1537,
- t2LDM_RET = 1538,
- t2LDRBT = 1539,
- t2LDRB_POST = 1540,
- t2LDRB_PRE = 1541,
- t2LDRBi12 = 1542,
- t2LDRBi8 = 1543,
- t2LDRBpci = 1544,
- t2LDRBs = 1545,
- t2LDRDi8 = 1546,
- t2LDRDpci = 1547,
- t2LDREX = 1548,
- t2LDREXB = 1549,
- t2LDREXD = 1550,
- t2LDREXH = 1551,
- t2LDRHT = 1552,
- t2LDRH_POST = 1553,
- t2LDRH_PRE = 1554,
- t2LDRHi12 = 1555,
- t2LDRHi8 = 1556,
- t2LDRHpci = 1557,
- t2LDRHs = 1558,
- t2LDRSBT = 1559,
- t2LDRSB_POST = 1560,
- t2LDRSB_PRE = 1561,
- t2LDRSBi12 = 1562,
- t2LDRSBi8 = 1563,
- t2LDRSBpci = 1564,
- t2LDRSBs = 1565,
- t2LDRSHT = 1566,
- t2LDRSH_POST = 1567,
- t2LDRSH_PRE = 1568,
- t2LDRSHi12 = 1569,
- t2LDRSHi8 = 1570,
- t2LDRSHpci = 1571,
- t2LDRSHs = 1572,
- t2LDRT = 1573,
- t2LDR_POST = 1574,
- t2LDR_PRE = 1575,
- t2LDRi12 = 1576,
- t2LDRi8 = 1577,
- t2LDRpci = 1578,
- t2LDRpci_pic = 1579,
- t2LDRs = 1580,
- t2LEApcrel = 1581,
- t2LEApcrelJT = 1582,
- t2LSLri = 1583,
- t2LSLrr = 1584,
- t2LSRri = 1585,
- t2LSRrr = 1586,
- t2MLA = 1587,
- t2MLS = 1588,
- t2MOVCCasr = 1589,
- t2MOVCCi = 1590,
- t2MOVCClsl = 1591,
- t2MOVCClsr = 1592,
- t2MOVCCr = 1593,
- t2MOVCCror = 1594,
- t2MOVTi16 = 1595,
- t2MOVi = 1596,
- t2MOVi16 = 1597,
- t2MOVi32imm = 1598,
- t2MOVr = 1599,
- t2MOVrx = 1600,
- t2MOVsra_flag = 1601,
- t2MOVsrl_flag = 1602,
- t2MRS = 1603,
- t2MRSsys = 1604,
- t2MSR = 1605,
- t2MSRsys = 1606,
- t2MUL = 1607,
- t2MVNi = 1608,
- t2MVNr = 1609,
- t2MVNs = 1610,
- t2NOP = 1611,
- t2ORNri = 1612,
- t2ORNrr = 1613,
- t2ORNrs = 1614,
- t2ORRri = 1615,
- t2ORRrr = 1616,
- t2ORRrs = 1617,
- t2PKHBT = 1618,
- t2PKHTB = 1619,
- t2PLDWi12 = 1620,
- t2PLDWi8 = 1621,
- t2PLDWpci = 1622,
- t2PLDWr = 1623,
- t2PLDWs = 1624,
- t2PLDi12 = 1625,
- t2PLDi8 = 1626,
- t2PLDpci = 1627,
- t2PLDr = 1628,
- t2PLDs = 1629,
- t2PLIi12 = 1630,
- t2PLIi8 = 1631,
- t2PLIpci = 1632,
- t2PLIr = 1633,
- t2PLIs = 1634,
- t2QADD = 1635,
- t2QADD16 = 1636,
- t2QADD8 = 1637,
- t2QASX = 1638,
- t2QDADD = 1639,
- t2QDSUB = 1640,
- t2QSAX = 1641,
- t2QSUB = 1642,
- t2QSUB16 = 1643,
- t2QSUB8 = 1644,
- t2RBIT = 1645,
- t2REV = 1646,
- t2REV16 = 1647,
- t2REVSH = 1648,
- t2RFEDB = 1649,
- t2RFEDBW = 1650,
- t2RFEIA = 1651,
- t2RFEIAW = 1652,
- t2RORri = 1653,
- t2RORrr = 1654,
- t2RSBSri = 1655,
- t2RSBSrs = 1656,
- t2RSBri = 1657,
- t2RSBrs = 1658,
- t2SADD16 = 1659,
- t2SADD8 = 1660,
- t2SASX = 1661,
- t2SBCSri = 1662,
- t2SBCSrr = 1663,
- t2SBCSrs = 1664,
- t2SBCri = 1665,
- t2SBCrr = 1666,
- t2SBCrs = 1667,
- t2SBFX = 1668,
- t2SDIV = 1669,
- t2SEL = 1670,
- t2SEV = 1671,
- t2SHADD16 = 1672,
- t2SHADD8 = 1673,
- t2SHASX = 1674,
- t2SHSAX = 1675,
- t2SHSUB16 = 1676,
- t2SHSUB8 = 1677,
- t2SMC = 1678,
- t2SMLABB = 1679,
- t2SMLABT = 1680,
- t2SMLAD = 1681,
- t2SMLADX = 1682,
- t2SMLAL = 1683,
- t2SMLALBB = 1684,
- t2SMLALBT = 1685,
- t2SMLALD = 1686,
- t2SMLALDX = 1687,
- t2SMLALTB = 1688,
- t2SMLALTT = 1689,
- t2SMLATB = 1690,
- t2SMLATT = 1691,
- t2SMLAWB = 1692,
- t2SMLAWT = 1693,
- t2SMLSD = 1694,
- t2SMLSDX = 1695,
- t2SMLSLD = 1696,
- t2SMLSLDX = 1697,
- t2SMMLA = 1698,
- t2SMMLAR = 1699,
- t2SMMLS = 1700,
- t2SMMLSR = 1701,
- t2SMMUL = 1702,
- t2SMMULR = 1703,
- t2SMUAD = 1704,
- t2SMUADX = 1705,
- t2SMULBB = 1706,
- t2SMULBT = 1707,
- t2SMULL = 1708,
- t2SMULTB = 1709,
- t2SMULTT = 1710,
- t2SMULWB = 1711,
- t2SMULWT = 1712,
- t2SMUSD = 1713,
- t2SMUSDX = 1714,
- t2SRSDB = 1715,
- t2SRSDBW = 1716,
- t2SRSIA = 1717,
- t2SRSIAW = 1718,
- t2SSAT16 = 1719,
- t2SSATasr = 1720,
- t2SSATlsl = 1721,
- t2SSAX = 1722,
- t2SSUB16 = 1723,
- t2SSUB8 = 1724,
- t2STM = 1725,
- t2STRBT = 1726,
- t2STRB_POST = 1727,
- t2STRB_PRE = 1728,
- t2STRBi12 = 1729,
- t2STRBi8 = 1730,
- t2STRBs = 1731,
- t2STRDi8 = 1732,
- t2STREX = 1733,
- t2STREXB = 1734,
- t2STREXD = 1735,
- t2STREXH = 1736,
- t2STRHT = 1737,
- t2STRH_POST = 1738,
- t2STRH_PRE = 1739,
- t2STRHi12 = 1740,
- t2STRHi8 = 1741,
- t2STRHs = 1742,
- t2STRT = 1743,
- t2STR_POST = 1744,
- t2STR_PRE = 1745,
- t2STRi12 = 1746,
- t2STRi8 = 1747,
- t2STRs = 1748,
- t2SUBSri = 1749,
- t2SUBSrr = 1750,
- t2SUBSrs = 1751,
- t2SUBrSPi = 1752,
- t2SUBrSPi12 = 1753,
- t2SUBrSPi12_ = 1754,
- t2SUBrSPi_ = 1755,
- t2SUBrSPs = 1756,
- t2SUBrSPs_ = 1757,
- t2SUBri = 1758,
- t2SUBri12 = 1759,
- t2SUBrr = 1760,
- t2SUBrs = 1761,
- t2SXTAB16rr = 1762,
- t2SXTAB16rr_rot = 1763,
- t2SXTABrr = 1764,
- t2SXTABrr_rot = 1765,
- t2SXTAHrr = 1766,
- t2SXTAHrr_rot = 1767,
- t2SXTB16r = 1768,
- t2SXTB16r_rot = 1769,
- t2SXTBr = 1770,
- t2SXTBr_rot = 1771,
- t2SXTHr = 1772,
- t2SXTHr_rot = 1773,
- t2TBB = 1774,
- t2TBBgen = 1775,
- t2TBH = 1776,
- t2TBHgen = 1777,
- t2TEQri = 1778,
- t2TEQrr = 1779,
- t2TEQrs = 1780,
- t2TPsoft = 1781,
- t2TSTri = 1782,
- t2TSTrr = 1783,
- t2TSTrs = 1784,
- t2UADD16 = 1785,
- t2UADD8 = 1786,
- t2UASX = 1787,
- t2UBFX = 1788,
- t2UDIV = 1789,
- t2UHADD16 = 1790,
- t2UHADD8 = 1791,
- t2UHASX = 1792,
- t2UHSAX = 1793,
- t2UHSUB16 = 1794,
- t2UHSUB8 = 1795,
- t2UMAAL = 1796,
- t2UMLAL = 1797,
- t2UMULL = 1798,
- t2UQADD16 = 1799,
- t2UQADD8 = 1800,
- t2UQASX = 1801,
- t2UQSAX = 1802,
- t2UQSUB16 = 1803,
- t2UQSUB8 = 1804,
- t2USAD8 = 1805,
- t2USADA8 = 1806,
- t2USAT16 = 1807,
- t2USATasr = 1808,
- t2USATlsl = 1809,
- t2USAX = 1810,
- t2USUB16 = 1811,
- t2USUB8 = 1812,
- t2UXTAB16rr = 1813,
- t2UXTAB16rr_rot = 1814,
- t2UXTABrr = 1815,
- t2UXTABrr_rot = 1816,
- t2UXTAHrr = 1817,
- t2UXTAHrr_rot = 1818,
- t2UXTB16r = 1819,
- t2UXTB16r_rot = 1820,
- t2UXTBr = 1821,
- t2UXTBr_rot = 1822,
- t2UXTHr = 1823,
- t2UXTHr_rot = 1824,
- t2WFE = 1825,
- t2WFI = 1826,
- t2YIELD = 1827,
- tADC = 1828,
- tADDhirr = 1829,
- tADDi3 = 1830,
- tADDi8 = 1831,
- tADDrPCi = 1832,
- tADDrSP = 1833,
- tADDrSPi = 1834,
- tADDrr = 1835,
- tADDspi = 1836,
- tADDspr = 1837,
- tADDspr_ = 1838,
- tADJCALLSTACKDOWN = 1839,
- tADJCALLSTACKUP = 1840,
- tAND = 1841,
- tANDsp = 1842,
- tASRri = 1843,
- tASRrr = 1844,
- tB = 1845,
- tBIC = 1846,
- tBKPT = 1847,
- tBL = 1848,
- tBLXi = 1849,
- tBLXi_r9 = 1850,
- tBLXr = 1851,
- tBLXr_r9 = 1852,
- tBLr9 = 1853,
- tBRIND = 1854,
- tBR_JTr = 1855,
- tBX = 1856,
- tBX_RET = 1857,
- tBX_RET_vararg = 1858,
- tBXr9 = 1859,
- tBcc = 1860,
- tBfar = 1861,
- tCBNZ = 1862,
- tCBZ = 1863,
- tCMNz = 1864,
- tCMPhir = 1865,
- tCMPi8 = 1866,
- tCMPr = 1867,
- tCMPzhir = 1868,
- tCMPzi8 = 1869,
- tCMPzr = 1870,
- tCPS = 1871,
- tEOR = 1872,
- tInt_eh_sjlj_setjmp = 1873,
- tLDM = 1874,
- tLDR = 1875,
- tLDRB = 1876,
- tLDRBi = 1877,
- tLDRH = 1878,
- tLDRHi = 1879,
- tLDRSB = 1880,
- tLDRSH = 1881,
- tLDRcp = 1882,
- tLDRi = 1883,
- tLDRpci = 1884,
- tLDRpci_pic = 1885,
- tLDRspi = 1886,
- tLEApcrel = 1887,
- tLEApcrelJT = 1888,
- tLSLri = 1889,
- tLSLrr = 1890,
- tLSRri = 1891,
- tLSRrr = 1892,
- tMOVCCi = 1893,
- tMOVCCr = 1894,
- tMOVCCr_pseudo = 1895,
- tMOVSr = 1896,
- tMOVgpr2gpr = 1897,
- tMOVgpr2tgpr = 1898,
- tMOVi8 = 1899,
- tMOVr = 1900,
- tMOVtgpr2gpr = 1901,
- tMUL = 1902,
- tMVN = 1903,
- tNOP = 1904,
- tORR = 1905,
- tPICADD = 1906,
- tPOP = 1907,
- tPOP_RET = 1908,
- tPUSH = 1909,
- tREV = 1910,
- tREV16 = 1911,
- tREVSH = 1912,
- tROR = 1913,
- tRSB = 1914,
- tRestore = 1915,
- tSBC = 1916,
- tSETENDBE = 1917,
- tSETENDLE = 1918,
- tSEV = 1919,
- tSTM = 1920,
- tSTR = 1921,
- tSTRB = 1922,
- tSTRBi = 1923,
- tSTRH = 1924,
- tSTRHi = 1925,
- tSTRi = 1926,
- tSTRspi = 1927,
- tSUBi3 = 1928,
- tSUBi8 = 1929,
- tSUBrr = 1930,
- tSUBspi = 1931,
- tSUBspi_ = 1932,
- tSVC = 1933,
- tSXTB = 1934,
- tSXTH = 1935,
- tSpill = 1936,
- tTPsoft = 1937,
- tTRAP = 1938,
- tTST = 1939,
- tUXTB = 1940,
- tUXTH = 1941,
- tWFE = 1942,
- tWFI = 1943,
- tYIELD = 1944,
- INSTRUCTION_LIST_END = 1945
+ BMOVPCRX = 66,
+ BMOVPCRXr9 = 67,
+ BRIND = 68,
+ BR_JTadd = 69,
+ BR_JTm = 70,
+ BR_JTr = 71,
+ BX = 72,
+ BXJ = 73,
+ BX_RET = 74,
+ BXr9 = 75,
+ Bcc = 76,
+ CDP = 77,
+ CDP2 = 78,
+ CLREX = 79,
+ CLZ = 80,
+ CMNzri = 81,
+ CMNzrr = 82,
+ CMNzrs = 83,
+ CMPri = 84,
+ CMPrr = 85,
+ CMPrs = 86,
+ CMPzri = 87,
+ CMPzrr = 88,
+ CMPzrs = 89,
+ CONSTPOOL_ENTRY = 90,
+ CPS = 91,
+ DBG = 92,
+ DMBish = 93,
+ DMBishst = 94,
+ DMBnsh = 95,
+ DMBnshst = 96,
+ DMBosh = 97,
+ DMBoshst = 98,
+ DMBst = 99,
+ DSBish = 100,
+ DSBishst = 101,
+ DSBnsh = 102,
+ DSBnshst = 103,
+ DSBosh = 104,
+ DSBoshst = 105,
+ DSBst = 106,
+ EORri = 107,
+ EORrr = 108,
+ EORrs = 109,
+ FCONSTD = 110,
+ FCONSTS = 111,
+ FMSTAT = 112,
+ ISBsy = 113,
+ Int_MemBarrierV6 = 114,
+ Int_MemBarrierV7 = 115,
+ Int_SyncBarrierV6 = 116,
+ Int_SyncBarrierV7 = 117,
+ Int_eh_sjlj_setjmp = 118,
+ LDC2L_OFFSET = 119,
+ LDC2L_OPTION = 120,
+ LDC2L_POST = 121,
+ LDC2L_PRE = 122,
+ LDC2_OFFSET = 123,
+ LDC2_OPTION = 124,
+ LDC2_POST = 125,
+ LDC2_PRE = 126,
+ LDCL_OFFSET = 127,
+ LDCL_OPTION = 128,
+ LDCL_POST = 129,
+ LDCL_PRE = 130,
+ LDC_OFFSET = 131,
+ LDC_OPTION = 132,
+ LDC_POST = 133,
+ LDC_PRE = 134,
+ LDM = 135,
+ LDM_RET = 136,
+ LDR = 137,
+ LDRB = 138,
+ LDRBT = 139,
+ LDRB_POST = 140,
+ LDRB_PRE = 141,
+ LDRD = 142,
+ LDRD_POST = 143,
+ LDRD_PRE = 144,
+ LDREX = 145,
+ LDREXB = 146,
+ LDREXD = 147,
+ LDREXH = 148,
+ LDRH = 149,
+ LDRHT = 150,
+ LDRH_POST = 151,
+ LDRH_PRE = 152,
+ LDRSB = 153,
+ LDRSBT = 154,
+ LDRSB_POST = 155,
+ LDRSB_PRE = 156,
+ LDRSH = 157,
+ LDRSHT = 158,
+ LDRSH_POST = 159,
+ LDRSH_PRE = 160,
+ LDRT = 161,
+ LDR_POST = 162,
+ LDR_PRE = 163,
+ LDRcp = 164,
+ LEApcrel = 165,
+ LEApcrelJT = 166,
+ MCR = 167,
+ MCR2 = 168,
+ MCRR = 169,
+ MCRR2 = 170,
+ MLA = 171,
+ MLS = 172,
+ MOVCCi = 173,
+ MOVCCr = 174,
+ MOVCCs = 175,
+ MOVPCLR = 176,
+ MOVPCRX = 177,
+ MOVTi16 = 178,
+ MOVi = 179,
+ MOVi16 = 180,
+ MOVi2pieces = 181,
+ MOVi32imm = 182,
+ MOVr = 183,
+ MOVrx = 184,
+ MOVs = 185,
+ MOVsra_flag = 186,
+ MOVsrl_flag = 187,
+ MRC = 188,
+ MRC2 = 189,
+ MRRC = 190,
+ MRRC2 = 191,
+ MRS = 192,
+ MRSsys = 193,
+ MSR = 194,
+ MSRi = 195,
+ MSRsys = 196,
+ MSRsysi = 197,
+ MUL = 198,
+ MVNi = 199,
+ MVNr = 200,
+ MVNs = 201,
+ NOP = 202,
+ ORRri = 203,
+ ORRrr = 204,
+ ORRrs = 205,
+ PICADD = 206,
+ PICLDR = 207,
+ PICLDRB = 208,
+ PICLDRH = 209,
+ PICLDRSB = 210,
+ PICLDRSH = 211,
+ PICSTR = 212,
+ PICSTRB = 213,
+ PICSTRH = 214,
+ PKHBT = 215,
+ PKHTB = 216,
+ PLDWi = 217,
+ PLDWr = 218,
+ PLDi = 219,
+ PLDr = 220,
+ PLIi = 221,
+ PLIr = 222,
+ QADD = 223,
+ QADD16 = 224,
+ QADD8 = 225,
+ QASX = 226,
+ QDADD = 227,
+ QDSUB = 228,
+ QSAX = 229,
+ QSUB = 230,
+ QSUB16 = 231,
+ QSUB8 = 232,
+ RBIT = 233,
+ REV = 234,
+ REV16 = 235,
+ REVSH = 236,
+ RFE = 237,
+ RFEW = 238,
+ RSBSri = 239,
+ RSBSrs = 240,
+ RSBri = 241,
+ RSBrs = 242,
+ RSCSri = 243,
+ RSCSrs = 244,
+ RSCri = 245,
+ RSCrs = 246,
+ SADD16 = 247,
+ SADD8 = 248,
+ SASX = 249,
+ SBCSSri = 250,
+ SBCSSrr = 251,
+ SBCSSrs = 252,
+ SBCri = 253,
+ SBCrr = 254,
+ SBCrs = 255,
+ SBFX = 256,
+ SEL = 257,
+ SETENDBE = 258,
+ SETENDLE = 259,
+ SEV = 260,
+ SHADD16 = 261,
+ SHADD8 = 262,
+ SHASX = 263,
+ SHSAX = 264,
+ SHSUB16 = 265,
+ SHSUB8 = 266,
+ SMC = 267,
+ SMLABB = 268,
+ SMLABT = 269,
+ SMLAD = 270,
+ SMLADX = 271,
+ SMLAL = 272,
+ SMLALBB = 273,
+ SMLALBT = 274,
+ SMLALD = 275,
+ SMLALDX = 276,
+ SMLALTB = 277,
+ SMLALTT = 278,
+ SMLATB = 279,
+ SMLATT = 280,
+ SMLAWB = 281,
+ SMLAWT = 282,
+ SMLSD = 283,
+ SMLSDX = 284,
+ SMLSLD = 285,
+ SMLSLDX = 286,
+ SMMLA = 287,
+ SMMLAR = 288,
+ SMMLS = 289,
+ SMMLSR = 290,
+ SMMUL = 291,
+ SMMULR = 292,
+ SMUAD = 293,
+ SMUADX = 294,
+ SMULBB = 295,
+ SMULBT = 296,
+ SMULL = 297,
+ SMULTB = 298,
+ SMULTT = 299,
+ SMULWB = 300,
+ SMULWT = 301,
+ SMUSD = 302,
+ SMUSDX = 303,
+ SRS = 304,
+ SRSW = 305,
+ SSAT16 = 306,
+ SSATasr = 307,
+ SSATlsl = 308,
+ SSAX = 309,
+ SSUB16 = 310,
+ SSUB8 = 311,
+ STC2L_OFFSET = 312,
+ STC2L_OPTION = 313,
+ STC2L_POST = 314,
+ STC2L_PRE = 315,
+ STC2_OFFSET = 316,
+ STC2_OPTION = 317,
+ STC2_POST = 318,
+ STC2_PRE = 319,
+ STCL_OFFSET = 320,
+ STCL_OPTION = 321,
+ STCL_POST = 322,
+ STCL_PRE = 323,
+ STC_OFFSET = 324,
+ STC_OPTION = 325,
+ STC_POST = 326,
+ STC_PRE = 327,
+ STM = 328,
+ STR = 329,
+ STRB = 330,
+ STRBT = 331,
+ STRB_POST = 332,
+ STRB_PRE = 333,
+ STRD = 334,
+ STRD_POST = 335,
+ STRD_PRE = 336,
+ STREX = 337,
+ STREXB = 338,
+ STREXD = 339,
+ STREXH = 340,
+ STRH = 341,
+ STRHT = 342,
+ STRH_POST = 343,
+ STRH_PRE = 344,
+ STRT = 345,
+ STR_POST = 346,
+ STR_PRE = 347,
+ SUBSri = 348,
+ SUBSrr = 349,
+ SUBSrs = 350,
+ SUBri = 351,
+ SUBrr = 352,
+ SUBrs = 353,
+ SVC = 354,
+ SWP = 355,
+ SWPB = 356,
+ SXTAB16rr = 357,
+ SXTAB16rr_rot = 358,
+ SXTABrr = 359,
+ SXTABrr_rot = 360,
+ SXTAHrr = 361,
+ SXTAHrr_rot = 362,
+ SXTB16r = 363,
+ SXTB16r_rot = 364,
+ SXTBr = 365,
+ SXTBr_rot = 366,
+ SXTHr = 367,
+ SXTHr_rot = 368,
+ TEQri = 369,
+ TEQrr = 370,
+ TEQrs = 371,
+ TPsoft = 372,
+ TRAP = 373,
+ TSTri = 374,
+ TSTrr = 375,
+ TSTrs = 376,
+ UADD16 = 377,
+ UADD8 = 378,
+ UASX = 379,
+ UBFX = 380,
+ UHADD16 = 381,
+ UHADD8 = 382,
+ UHASX = 383,
+ UHSAX = 384,
+ UHSUB16 = 385,
+ UHSUB8 = 386,
+ UMAAL = 387,
+ UMLAL = 388,
+ UMULL = 389,
+ UQADD16 = 390,
+ UQADD8 = 391,
+ UQASX = 392,
+ UQSAX = 393,
+ UQSUB16 = 394,
+ UQSUB8 = 395,
+ USAD8 = 396,
+ USADA8 = 397,
+ USAT16 = 398,
+ USATasr = 399,
+ USATlsl = 400,
+ USAX = 401,
+ USUB16 = 402,
+ USUB8 = 403,
+ UXTAB16rr = 404,
+ UXTAB16rr_rot = 405,
+ UXTABrr = 406,
+ UXTABrr_rot = 407,
+ UXTAHrr = 408,
+ UXTAHrr_rot = 409,
+ UXTB16r = 410,
+ UXTB16r_rot = 411,
+ UXTBr = 412,
+ UXTBr_rot = 413,
+ UXTHr = 414,
+ UXTHr_rot = 415,
+ VABALsv2i64 = 416,
+ VABALsv4i32 = 417,
+ VABALsv8i16 = 418,
+ VABALuv2i64 = 419,
+ VABALuv4i32 = 420,
+ VABALuv8i16 = 421,
+ VABAsv16i8 = 422,
+ VABAsv2i32 = 423,
+ VABAsv4i16 = 424,
+ VABAsv4i32 = 425,
+ VABAsv8i16 = 426,
+ VABAsv8i8 = 427,
+ VABAuv16i8 = 428,
+ VABAuv2i32 = 429,
+ VABAuv4i16 = 430,
+ VABAuv4i32 = 431,
+ VABAuv8i16 = 432,
+ VABAuv8i8 = 433,
+ VABDLsv2i64 = 434,
+ VABDLsv4i32 = 435,
+ VABDLsv8i16 = 436,
+ VABDLuv2i64 = 437,
+ VABDLuv4i32 = 438,
+ VABDLuv8i16 = 439,
+ VABDfd = 440,
+ VABDfq = 441,
+ VABDsv16i8 = 442,
+ VABDsv2i32 = 443,
+ VABDsv4i16 = 444,
+ VABDsv4i32 = 445,
+ VABDsv8i16 = 446,
+ VABDsv8i8 = 447,
+ VABDuv16i8 = 448,
+ VABDuv2i32 = 449,
+ VABDuv4i16 = 450,
+ VABDuv4i32 = 451,
+ VABDuv8i16 = 452,
+ VABDuv8i8 = 453,
+ VABSD = 454,
+ VABSS = 455,
+ VABSfd = 456,
+ VABSfd_sfp = 457,
+ VABSfq = 458,
+ VABSv16i8 = 459,
+ VABSv2i32 = 460,
+ VABSv4i16 = 461,
+ VABSv4i32 = 462,
+ VABSv8i16 = 463,
+ VABSv8i8 = 464,
+ VACGEd = 465,
+ VACGEq = 466,
+ VACGTd = 467,
+ VACGTq = 468,
+ VADDD = 469,
+ VADDHNv2i32 = 470,
+ VADDHNv4i16 = 471,
+ VADDHNv8i8 = 472,
+ VADDLsv2i64 = 473,
+ VADDLsv4i32 = 474,
+ VADDLsv8i16 = 475,
+ VADDLuv2i64 = 476,
+ VADDLuv4i32 = 477,
+ VADDLuv8i16 = 478,
+ VADDS = 479,
+ VADDWsv2i64 = 480,
+ VADDWsv4i32 = 481,
+ VADDWsv8i16 = 482,
+ VADDWuv2i64 = 483,
+ VADDWuv4i32 = 484,
+ VADDWuv8i16 = 485,
+ VADDfd = 486,
+ VADDfd_sfp = 487,
+ VADDfq = 488,
+ VADDv16i8 = 489,
+ VADDv1i64 = 490,
+ VADDv2i32 = 491,
+ VADDv2i64 = 492,
+ VADDv4i16 = 493,
+ VADDv4i32 = 494,
+ VADDv8i16 = 495,
+ VADDv8i8 = 496,
+ VANDd = 497,
+ VANDq = 498,
+ VBICd = 499,
+ VBICq = 500,
+ VBIFd = 501,
+ VBIFq = 502,
+ VBITd = 503,
+ VBITq = 504,
+ VBSLd = 505,
+ VBSLq = 506,
+ VCEQfd = 507,
+ VCEQfq = 508,
+ VCEQv16i8 = 509,
+ VCEQv2i32 = 510,
+ VCEQv4i16 = 511,
+ VCEQv4i32 = 512,
+ VCEQv8i16 = 513,
+ VCEQv8i8 = 514,
+ VCEQzv16i8 = 515,
+ VCEQzv2f32 = 516,
+ VCEQzv2i32 = 517,
+ VCEQzv4f32 = 518,
+ VCEQzv4i16 = 519,
+ VCEQzv4i32 = 520,
+ VCEQzv8i16 = 521,
+ VCEQzv8i8 = 522,
+ VCGEfd = 523,
+ VCGEfq = 524,
+ VCGEsv16i8 = 525,
+ VCGEsv2i32 = 526,
+ VCGEsv4i16 = 527,
+ VCGEsv4i32 = 528,
+ VCGEsv8i16 = 529,
+ VCGEsv8i8 = 530,
+ VCGEuv16i8 = 531,
+ VCGEuv2i32 = 532,
+ VCGEuv4i16 = 533,
+ VCGEuv4i32 = 534,
+ VCGEuv8i16 = 535,
+ VCGEuv8i8 = 536,
+ VCGEzv16i8 = 537,
+ VCGEzv2f32 = 538,
+ VCGEzv2i32 = 539,
+ VCGEzv4f32 = 540,
+ VCGEzv4i16 = 541,
+ VCGEzv4i32 = 542,
+ VCGEzv8i16 = 543,
+ VCGEzv8i8 = 544,
+ VCGTfd = 545,
+ VCGTfq = 546,
+ VCGTsv16i8 = 547,
+ VCGTsv2i32 = 548,
+ VCGTsv4i16 = 549,
+ VCGTsv4i32 = 550,
+ VCGTsv8i16 = 551,
+ VCGTsv8i8 = 552,
+ VCGTuv16i8 = 553,
+ VCGTuv2i32 = 554,
+ VCGTuv4i16 = 555,
+ VCGTuv4i32 = 556,
+ VCGTuv8i16 = 557,
+ VCGTuv8i8 = 558,
+ VCGTzv16i8 = 559,
+ VCGTzv2f32 = 560,
+ VCGTzv2i32 = 561,
+ VCGTzv4f32 = 562,
+ VCGTzv4i16 = 563,
+ VCGTzv4i32 = 564,
+ VCGTzv8i16 = 565,
+ VCGTzv8i8 = 566,
+ VCLEzv16i8 = 567,
+ VCLEzv2f32 = 568,
+ VCLEzv2i32 = 569,
+ VCLEzv4f32 = 570,
+ VCLEzv4i16 = 571,
+ VCLEzv4i32 = 572,
+ VCLEzv8i16 = 573,
+ VCLEzv8i8 = 574,
+ VCLSv16i8 = 575,
+ VCLSv2i32 = 576,
+ VCLSv4i16 = 577,
+ VCLSv4i32 = 578,
+ VCLSv8i16 = 579,
+ VCLSv8i8 = 580,
+ VCLTzv16i8 = 581,
+ VCLTzv2f32 = 582,
+ VCLTzv2i32 = 583,
+ VCLTzv4f32 = 584,
+ VCLTzv4i16 = 585,
+ VCLTzv4i32 = 586,
+ VCLTzv8i16 = 587,
+ VCLTzv8i8 = 588,
+ VCLZv16i8 = 589,
+ VCLZv2i32 = 590,
+ VCLZv4i16 = 591,
+ VCLZv4i32 = 592,
+ VCLZv8i16 = 593,
+ VCLZv8i8 = 594,
+ VCMPD = 595,
+ VCMPED = 596,
+ VCMPES = 597,
+ VCMPEZD = 598,
+ VCMPEZS = 599,
+ VCMPS = 600,
+ VCMPZD = 601,
+ VCMPZS = 602,
+ VCNTd = 603,
+ VCNTq = 604,
+ VCVTBHS = 605,
+ VCVTBSH = 606,
+ VCVTDS = 607,
+ VCVTSD = 608,
+ VCVTTHS = 609,
+ VCVTTSH = 610,
+ VCVTf2sd = 611,
+ VCVTf2sd_sfp = 612,
+ VCVTf2sq = 613,
+ VCVTf2ud = 614,
+ VCVTf2ud_sfp = 615,
+ VCVTf2uq = 616,
+ VCVTf2xsd = 617,
+ VCVTf2xsq = 618,
+ VCVTf2xud = 619,
+ VCVTf2xuq = 620,
+ VCVTs2fd = 621,
+ VCVTs2fd_sfp = 622,
+ VCVTs2fq = 623,
+ VCVTu2fd = 624,
+ VCVTu2fd_sfp = 625,
+ VCVTu2fq = 626,
+ VCVTxs2fd = 627,
+ VCVTxs2fq = 628,
+ VCVTxu2fd = 629,
+ VCVTxu2fq = 630,
+ VDIVD = 631,
+ VDIVS = 632,
+ VDUP16d = 633,
+ VDUP16q = 634,
+ VDUP32d = 635,
+ VDUP32q = 636,
+ VDUP8d = 637,
+ VDUP8q = 638,
+ VDUPLN16d = 639,
+ VDUPLN16q = 640,
+ VDUPLN32d = 641,
+ VDUPLN32q = 642,
+ VDUPLN8d = 643,
+ VDUPLN8q = 644,
+ VDUPLNfd = 645,
+ VDUPLNfq = 646,
+ VDUPfd = 647,
+ VDUPfdf = 648,
+ VDUPfq = 649,
+ VDUPfqf = 650,
+ VEORd = 651,
+ VEORq = 652,
+ VEXTd16 = 653,
+ VEXTd32 = 654,
+ VEXTd8 = 655,
+ VEXTdf = 656,
+ VEXTq16 = 657,
+ VEXTq32 = 658,
+ VEXTq8 = 659,
+ VEXTqf = 660,
+ VGETLNi32 = 661,
+ VGETLNs16 = 662,
+ VGETLNs8 = 663,
+ VGETLNu16 = 664,
+ VGETLNu8 = 665,
+ VHADDsv16i8 = 666,
+ VHADDsv2i32 = 667,
+ VHADDsv4i16 = 668,
+ VHADDsv4i32 = 669,
+ VHADDsv8i16 = 670,
+ VHADDsv8i8 = 671,
+ VHADDuv16i8 = 672,
+ VHADDuv2i32 = 673,
+ VHADDuv4i16 = 674,
+ VHADDuv4i32 = 675,
+ VHADDuv8i16 = 676,
+ VHADDuv8i8 = 677,
+ VHSUBsv16i8 = 678,
+ VHSUBsv2i32 = 679,
+ VHSUBsv4i16 = 680,
+ VHSUBsv4i32 = 681,
+ VHSUBsv8i16 = 682,
+ VHSUBsv8i8 = 683,
+ VHSUBuv16i8 = 684,
+ VHSUBuv2i32 = 685,
+ VHSUBuv4i16 = 686,
+ VHSUBuv4i32 = 687,
+ VHSUBuv8i16 = 688,
+ VHSUBuv8i8 = 689,
+ VLD1d16 = 690,
+ VLD1d16Q = 691,
+ VLD1d16T = 692,
+ VLD1d32 = 693,
+ VLD1d32Q = 694,
+ VLD1d32T = 695,
+ VLD1d64 = 696,
+ VLD1d8 = 697,
+ VLD1d8Q = 698,
+ VLD1d8T = 699,
+ VLD1df = 700,
+ VLD1q16 = 701,
+ VLD1q32 = 702,
+ VLD1q64 = 703,
+ VLD1q8 = 704,
+ VLD1qf = 705,
+ VLD2LNd16 = 706,
+ VLD2LNd32 = 707,
+ VLD2LNd8 = 708,
+ VLD2LNq16a = 709,
+ VLD2LNq16b = 710,
+ VLD2LNq32a = 711,
+ VLD2LNq32b = 712,
+ VLD2d16 = 713,
+ VLD2d16D = 714,
+ VLD2d32 = 715,
+ VLD2d32D = 716,
+ VLD2d64 = 717,
+ VLD2d8 = 718,
+ VLD2d8D = 719,
+ VLD2q16 = 720,
+ VLD2q32 = 721,
+ VLD2q8 = 722,
+ VLD3LNd16 = 723,
+ VLD3LNd32 = 724,
+ VLD3LNd8 = 725,
+ VLD3LNq16a = 726,
+ VLD3LNq16b = 727,
+ VLD3LNq32a = 728,
+ VLD3LNq32b = 729,
+ VLD3d16 = 730,
+ VLD3d32 = 731,
+ VLD3d64 = 732,
+ VLD3d8 = 733,
+ VLD3q16a = 734,
+ VLD3q16b = 735,
+ VLD3q32a = 736,
+ VLD3q32b = 737,
+ VLD3q8a = 738,
+ VLD3q8b = 739,
+ VLD4LNd16 = 740,
+ VLD4LNd32 = 741,
+ VLD4LNd8 = 742,
+ VLD4LNq16a = 743,
+ VLD4LNq16b = 744,
+ VLD4LNq32a = 745,
+ VLD4LNq32b = 746,
+ VLD4d16 = 747,
+ VLD4d32 = 748,
+ VLD4d64 = 749,
+ VLD4d8 = 750,
+ VLD4q16a = 751,
+ VLD4q16b = 752,
+ VLD4q32a = 753,
+ VLD4q32b = 754,
+ VLD4q8a = 755,
+ VLD4q8b = 756,
+ VLDMD = 757,
+ VLDMS = 758,
+ VLDRD = 759,
+ VLDRQ = 760,
+ VLDRS = 761,
+ VMAXfd = 762,
+ VMAXfd_sfp = 763,
+ VMAXfq = 764,
+ VMAXsv16i8 = 765,
+ VMAXsv2i32 = 766,
+ VMAXsv4i16 = 767,
+ VMAXsv4i32 = 768,
+ VMAXsv8i16 = 769,
+ VMAXsv8i8 = 770,
+ VMAXuv16i8 = 771,
+ VMAXuv2i32 = 772,
+ VMAXuv4i16 = 773,
+ VMAXuv4i32 = 774,
+ VMAXuv8i16 = 775,
+ VMAXuv8i8 = 776,
+ VMINfd = 777,
+ VMINfd_sfp = 778,
+ VMINfq = 779,
+ VMINsv16i8 = 780,
+ VMINsv2i32 = 781,
+ VMINsv4i16 = 782,
+ VMINsv4i32 = 783,
+ VMINsv8i16 = 784,
+ VMINsv8i8 = 785,
+ VMINuv16i8 = 786,
+ VMINuv2i32 = 787,
+ VMINuv4i16 = 788,
+ VMINuv4i32 = 789,
+ VMINuv8i16 = 790,
+ VMINuv8i8 = 791,
+ VMLAD = 792,
+ VMLALslsv2i32 = 793,
+ VMLALslsv4i16 = 794,
+ VMLALsluv2i32 = 795,
+ VMLALsluv4i16 = 796,
+ VMLALsv2i64 = 797,
+ VMLALsv4i32 = 798,
+ VMLALsv8i16 = 799,
+ VMLALuv2i64 = 800,
+ VMLALuv4i32 = 801,
+ VMLALuv8i16 = 802,
+ VMLAS = 803,
+ VMLAfd = 804,
+ VMLAfq = 805,
+ VMLAslfd = 806,
+ VMLAslfq = 807,
+ VMLAslv2i32 = 808,
+ VMLAslv4i16 = 809,
+ VMLAslv4i32 = 810,
+ VMLAslv8i16 = 811,
+ VMLAv16i8 = 812,
+ VMLAv2i32 = 813,
+ VMLAv4i16 = 814,
+ VMLAv4i32 = 815,
+ VMLAv8i16 = 816,
+ VMLAv8i8 = 817,
+ VMLSD = 818,
+ VMLSLslsv2i32 = 819,
+ VMLSLslsv4i16 = 820,
+ VMLSLsluv2i32 = 821,
+ VMLSLsluv4i16 = 822,
+ VMLSLsv2i64 = 823,
+ VMLSLsv4i32 = 824,
+ VMLSLsv8i16 = 825,
+ VMLSLuv2i64 = 826,
+ VMLSLuv4i32 = 827,
+ VMLSLuv8i16 = 828,
+ VMLSS = 829,
+ VMLSfd = 830,
+ VMLSfq = 831,
+ VMLSslfd = 832,
+ VMLSslfq = 833,
+ VMLSslv2i32 = 834,
+ VMLSslv4i16 = 835,
+ VMLSslv4i32 = 836,
+ VMLSslv8i16 = 837,
+ VMLSv16i8 = 838,
+ VMLSv2i32 = 839,
+ VMLSv4i16 = 840,
+ VMLSv4i32 = 841,
+ VMLSv8i16 = 842,
+ VMLSv8i8 = 843,
+ VMOVD = 844,
+ VMOVDRR = 845,
+ VMOVDcc = 846,
+ VMOVDneon = 847,
+ VMOVLsv2i64 = 848,
+ VMOVLsv4i32 = 849,
+ VMOVLsv8i16 = 850,
+ VMOVLuv2i64 = 851,
+ VMOVLuv4i32 = 852,
+ VMOVLuv8i16 = 853,
+ VMOVNv2i32 = 854,
+ VMOVNv4i16 = 855,
+ VMOVNv8i8 = 856,
+ VMOVQ = 857,
+ VMOVRRD = 858,
+ VMOVRRS = 859,
+ VMOVRS = 860,
+ VMOVS = 861,
+ VMOVSR = 862,
+ VMOVSRR = 863,
+ VMOVScc = 864,
+ VMOVv16i8 = 865,
+ VMOVv1i64 = 866,
+ VMOVv2i32 = 867,
+ VMOVv2i64 = 868,
+ VMOVv4i16 = 869,
+ VMOVv4i32 = 870,
+ VMOVv8i16 = 871,
+ VMOVv8i8 = 872,
+ VMRS = 873,
+ VMSR = 874,
+ VMULD = 875,
+ VMULLp = 876,
+ VMULLslsv2i32 = 877,
+ VMULLslsv4i16 = 878,
+ VMULLsluv2i32 = 879,
+ VMULLsluv4i16 = 880,
+ VMULLsv2i64 = 881,
+ VMULLsv4i32 = 882,
+ VMULLsv8i16 = 883,
+ VMULLuv2i64 = 884,
+ VMULLuv4i32 = 885,
+ VMULLuv8i16 = 886,
+ VMULS = 887,
+ VMULfd = 888,
+ VMULfd_sfp = 889,
+ VMULfq = 890,
+ VMULpd = 891,
+ VMULpq = 892,
+ VMULslfd = 893,
+ VMULslfq = 894,
+ VMULslv2i32 = 895,
+ VMULslv4i16 = 896,
+ VMULslv4i32 = 897,
+ VMULslv8i16 = 898,
+ VMULv16i8 = 899,
+ VMULv2i32 = 900,
+ VMULv4i16 = 901,
+ VMULv4i32 = 902,
+ VMULv8i16 = 903,
+ VMULv8i8 = 904,
+ VMVNd = 905,
+ VMVNq = 906,
+ VNEGD = 907,
+ VNEGDcc = 908,
+ VNEGS = 909,
+ VNEGScc = 910,
+ VNEGf32q = 911,
+ VNEGfd = 912,
+ VNEGfd_sfp = 913,
+ VNEGs16d = 914,
+ VNEGs16q = 915,
+ VNEGs32d = 916,
+ VNEGs32q = 917,
+ VNEGs8d = 918,
+ VNEGs8q = 919,
+ VNMLAD = 920,
+ VNMLAS = 921,
+ VNMLSD = 922,
+ VNMLSS = 923,
+ VNMULD = 924,
+ VNMULS = 925,
+ VORNd = 926,
+ VORNq = 927,
+ VORRd = 928,
+ VORRq = 929,
+ VPADALsv16i8 = 930,
+ VPADALsv2i32 = 931,
+ VPADALsv4i16 = 932,
+ VPADALsv4i32 = 933,
+ VPADALsv8i16 = 934,
+ VPADALsv8i8 = 935,
+ VPADALuv16i8 = 936,
+ VPADALuv2i32 = 937,
+ VPADALuv4i16 = 938,
+ VPADALuv4i32 = 939,
+ VPADALuv8i16 = 940,
+ VPADALuv8i8 = 941,
+ VPADDLsv16i8 = 942,
+ VPADDLsv2i32 = 943,
+ VPADDLsv4i16 = 944,
+ VPADDLsv4i32 = 945,
+ VPADDLsv8i16 = 946,
+ VPADDLsv8i8 = 947,
+ VPADDLuv16i8 = 948,
+ VPADDLuv2i32 = 949,
+ VPADDLuv4i16 = 950,
+ VPADDLuv4i32 = 951,
+ VPADDLuv8i16 = 952,
+ VPADDLuv8i8 = 953,
+ VPADDf = 954,
+ VPADDi16 = 955,
+ VPADDi32 = 956,
+ VPADDi8 = 957,
+ VPMAXf = 958,
+ VPMAXs16 = 959,
+ VPMAXs32 = 960,
+ VPMAXs8 = 961,
+ VPMAXu16 = 962,
+ VPMAXu32 = 963,
+ VPMAXu8 = 964,
+ VPMINf = 965,
+ VPMINs16 = 966,
+ VPMINs32 = 967,
+ VPMINs8 = 968,
+ VPMINu16 = 969,
+ VPMINu32 = 970,
+ VPMINu8 = 971,
+ VQABSv16i8 = 972,
+ VQABSv2i32 = 973,
+ VQABSv4i16 = 974,
+ VQABSv4i32 = 975,
+ VQABSv8i16 = 976,
+ VQABSv8i8 = 977,
+ VQADDsv16i8 = 978,
+ VQADDsv1i64 = 979,
+ VQADDsv2i32 = 980,
+ VQADDsv2i64 = 981,
+ VQADDsv4i16 = 982,
+ VQADDsv4i32 = 983,
+ VQADDsv8i16 = 984,
+ VQADDsv8i8 = 985,
+ VQADDuv16i8 = 986,
+ VQADDuv1i64 = 987,
+ VQADDuv2i32 = 988,
+ VQADDuv2i64 = 989,
+ VQADDuv4i16 = 990,
+ VQADDuv4i32 = 991,
+ VQADDuv8i16 = 992,
+ VQADDuv8i8 = 993,
+ VQDMLALslv2i32 = 994,
+ VQDMLALslv4i16 = 995,
+ VQDMLALv2i64 = 996,
+ VQDMLALv4i32 = 997,
+ VQDMLSLslv2i32 = 998,
+ VQDMLSLslv4i16 = 999,
+ VQDMLSLv2i64 = 1000,
+ VQDMLSLv4i32 = 1001,
+ VQDMULHslv2i32 = 1002,
+ VQDMULHslv4i16 = 1003,
+ VQDMULHslv4i32 = 1004,
+ VQDMULHslv8i16 = 1005,
+ VQDMULHv2i32 = 1006,
+ VQDMULHv4i16 = 1007,
+ VQDMULHv4i32 = 1008,
+ VQDMULHv8i16 = 1009,
+ VQDMULLslv2i32 = 1010,
+ VQDMULLslv4i16 = 1011,
+ VQDMULLv2i64 = 1012,
+ VQDMULLv4i32 = 1013,
+ VQMOVNsuv2i32 = 1014,
+ VQMOVNsuv4i16 = 1015,
+ VQMOVNsuv8i8 = 1016,
+ VQMOVNsv2i32 = 1017,
+ VQMOVNsv4i16 = 1018,
+ VQMOVNsv8i8 = 1019,
+ VQMOVNuv2i32 = 1020,
+ VQMOVNuv4i16 = 1021,
+ VQMOVNuv8i8 = 1022,
+ VQNEGv16i8 = 1023,
+ VQNEGv2i32 = 1024,
+ VQNEGv4i16 = 1025,
+ VQNEGv4i32 = 1026,
+ VQNEGv8i16 = 1027,
+ VQNEGv8i8 = 1028,
+ VQRDMULHslv2i32 = 1029,
+ VQRDMULHslv4i16 = 1030,
+ VQRDMULHslv4i32 = 1031,
+ VQRDMULHslv8i16 = 1032,
+ VQRDMULHv2i32 = 1033,
+ VQRDMULHv4i16 = 1034,
+ VQRDMULHv4i32 = 1035,
+ VQRDMULHv8i16 = 1036,
+ VQRSHLsv16i8 = 1037,
+ VQRSHLsv1i64 = 1038,
+ VQRSHLsv2i32 = 1039,
+ VQRSHLsv2i64 = 1040,
+ VQRSHLsv4i16 = 1041,
+ VQRSHLsv4i32 = 1042,
+ VQRSHLsv8i16 = 1043,
+ VQRSHLsv8i8 = 1044,
+ VQRSHLuv16i8 = 1045,
+ VQRSHLuv1i64 = 1046,
+ VQRSHLuv2i32 = 1047,
+ VQRSHLuv2i64 = 1048,
+ VQRSHLuv4i16 = 1049,
+ VQRSHLuv4i32 = 1050,
+ VQRSHLuv8i16 = 1051,
+ VQRSHLuv8i8 = 1052,
+ VQRSHRNsv2i32 = 1053,
+ VQRSHRNsv4i16 = 1054,
+ VQRSHRNsv8i8 = 1055,
+ VQRSHRNuv2i32 = 1056,
+ VQRSHRNuv4i16 = 1057,
+ VQRSHRNuv8i8 = 1058,
+ VQRSHRUNv2i32 = 1059,
+ VQRSHRUNv4i16 = 1060,
+ VQRSHRUNv8i8 = 1061,
+ VQSHLsiv16i8 = 1062,
+ VQSHLsiv1i64 = 1063,
+ VQSHLsiv2i32 = 1064,
+ VQSHLsiv2i64 = 1065,
+ VQSHLsiv4i16 = 1066,
+ VQSHLsiv4i32 = 1067,
+ VQSHLsiv8i16 = 1068,
+ VQSHLsiv8i8 = 1069,
+ VQSHLsuv16i8 = 1070,
+ VQSHLsuv1i64 = 1071,
+ VQSHLsuv2i32 = 1072,
+ VQSHLsuv2i64 = 1073,
+ VQSHLsuv4i16 = 1074,
+ VQSHLsuv4i32 = 1075,
+ VQSHLsuv8i16 = 1076,
+ VQSHLsuv8i8 = 1077,
+ VQSHLsv16i8 = 1078,
+ VQSHLsv1i64 = 1079,
+ VQSHLsv2i32 = 1080,
+ VQSHLsv2i64 = 1081,
+ VQSHLsv4i16 = 1082,
+ VQSHLsv4i32 = 1083,
+ VQSHLsv8i16 = 1084,
+ VQSHLsv8i8 = 1085,
+ VQSHLuiv16i8 = 1086,
+ VQSHLuiv1i64 = 1087,
+ VQSHLuiv2i32 = 1088,
+ VQSHLuiv2i64 = 1089,
+ VQSHLuiv4i16 = 1090,
+ VQSHLuiv4i32 = 1091,
+ VQSHLuiv8i16 = 1092,
+ VQSHLuiv8i8 = 1093,
+ VQSHLuv16i8 = 1094,
+ VQSHLuv1i64 = 1095,
+ VQSHLuv2i32 = 1096,
+ VQSHLuv2i64 = 1097,
+ VQSHLuv4i16 = 1098,
+ VQSHLuv4i32 = 1099,
+ VQSHLuv8i16 = 1100,
+ VQSHLuv8i8 = 1101,
+ VQSHRNsv2i32 = 1102,
+ VQSHRNsv4i16 = 1103,
+ VQSHRNsv8i8 = 1104,
+ VQSHRNuv2i32 = 1105,
+ VQSHRNuv4i16 = 1106,
+ VQSHRNuv8i8 = 1107,
+ VQSHRUNv2i32 = 1108,
+ VQSHRUNv4i16 = 1109,
+ VQSHRUNv8i8 = 1110,
+ VQSUBsv16i8 = 1111,
+ VQSUBsv1i64 = 1112,
+ VQSUBsv2i32 = 1113,
+ VQSUBsv2i64 = 1114,
+ VQSUBsv4i16 = 1115,
+ VQSUBsv4i32 = 1116,
+ VQSUBsv8i16 = 1117,
+ VQSUBsv8i8 = 1118,
+ VQSUBuv16i8 = 1119,
+ VQSUBuv1i64 = 1120,
+ VQSUBuv2i32 = 1121,
+ VQSUBuv2i64 = 1122,
+ VQSUBuv4i16 = 1123,
+ VQSUBuv4i32 = 1124,
+ VQSUBuv8i16 = 1125,
+ VQSUBuv8i8 = 1126,
+ VRADDHNv2i32 = 1127,
+ VRADDHNv4i16 = 1128,
+ VRADDHNv8i8 = 1129,
+ VRECPEd = 1130,
+ VRECPEfd = 1131,
+ VRECPEfq = 1132,
+ VRECPEq = 1133,
+ VRECPSfd = 1134,
+ VRECPSfq = 1135,
+ VREV16d8 = 1136,
+ VREV16q8 = 1137,
+ VREV32d16 = 1138,
+ VREV32d8 = 1139,
+ VREV32q16 = 1140,
+ VREV32q8 = 1141,
+ VREV64d16 = 1142,
+ VREV64d32 = 1143,
+ VREV64d8 = 1144,
+ VREV64df = 1145,
+ VREV64q16 = 1146,
+ VREV64q32 = 1147,
+ VREV64q8 = 1148,
+ VREV64qf = 1149,
+ VRHADDsv16i8 = 1150,
+ VRHADDsv2i32 = 1151,
+ VRHADDsv4i16 = 1152,
+ VRHADDsv4i32 = 1153,
+ VRHADDsv8i16 = 1154,
+ VRHADDsv8i8 = 1155,
+ VRHADDuv16i8 = 1156,
+ VRHADDuv2i32 = 1157,
+ VRHADDuv4i16 = 1158,
+ VRHADDuv4i32 = 1159,
+ VRHADDuv8i16 = 1160,
+ VRHADDuv8i8 = 1161,
+ VRSHLsv16i8 = 1162,
+ VRSHLsv1i64 = 1163,
+ VRSHLsv2i32 = 1164,
+ VRSHLsv2i64 = 1165,
+ VRSHLsv4i16 = 1166,
+ VRSHLsv4i32 = 1167,
+ VRSHLsv8i16 = 1168,
+ VRSHLsv8i8 = 1169,
+ VRSHLuv16i8 = 1170,
+ VRSHLuv1i64 = 1171,
+ VRSHLuv2i32 = 1172,
+ VRSHLuv2i64 = 1173,
+ VRSHLuv4i16 = 1174,
+ VRSHLuv4i32 = 1175,
+ VRSHLuv8i16 = 1176,
+ VRSHLuv8i8 = 1177,
+ VRSHRNv2i32 = 1178,
+ VRSHRNv4i16 = 1179,
+ VRSHRNv8i8 = 1180,
+ VRSHRsv16i8 = 1181,
+ VRSHRsv1i64 = 1182,
+ VRSHRsv2i32 = 1183,
+ VRSHRsv2i64 = 1184,
+ VRSHRsv4i16 = 1185,
+ VRSHRsv4i32 = 1186,
+ VRSHRsv8i16 = 1187,
+ VRSHRsv8i8 = 1188,
+ VRSHRuv16i8 = 1189,
+ VRSHRuv1i64 = 1190,
+ VRSHRuv2i32 = 1191,
+ VRSHRuv2i64 = 1192,
+ VRSHRuv4i16 = 1193,
+ VRSHRuv4i32 = 1194,
+ VRSHRuv8i16 = 1195,
+ VRSHRuv8i8 = 1196,
+ VRSQRTEd = 1197,
+ VRSQRTEfd = 1198,
+ VRSQRTEfq = 1199,
+ VRSQRTEq = 1200,
+ VRSQRTSfd = 1201,
+ VRSQRTSfq = 1202,
+ VRSRAsv16i8 = 1203,
+ VRSRAsv1i64 = 1204,
+ VRSRAsv2i32 = 1205,
+ VRSRAsv2i64 = 1206,
+ VRSRAsv4i16 = 1207,
+ VRSRAsv4i32 = 1208,
+ VRSRAsv8i16 = 1209,
+ VRSRAsv8i8 = 1210,
+ VRSRAuv16i8 = 1211,
+ VRSRAuv1i64 = 1212,
+ VRSRAuv2i32 = 1213,
+ VRSRAuv2i64 = 1214,
+ VRSRAuv4i16 = 1215,
+ VRSRAuv4i32 = 1216,
+ VRSRAuv8i16 = 1217,
+ VRSRAuv8i8 = 1218,
+ VRSUBHNv2i32 = 1219,
+ VRSUBHNv4i16 = 1220,
+ VRSUBHNv8i8 = 1221,
+ VSETLNi16 = 1222,
+ VSETLNi32 = 1223,
+ VSETLNi8 = 1224,
+ VSHLLi16 = 1225,
+ VSHLLi32 = 1226,
+ VSHLLi8 = 1227,
+ VSHLLsv2i64 = 1228,
+ VSHLLsv4i32 = 1229,
+ VSHLLsv8i16 = 1230,
+ VSHLLuv2i64 = 1231,
+ VSHLLuv4i32 = 1232,
+ VSHLLuv8i16 = 1233,
+ VSHLiv16i8 = 1234,
+ VSHLiv1i64 = 1235,
+ VSHLiv2i32 = 1236,
+ VSHLiv2i64 = 1237,
+ VSHLiv4i16 = 1238,
+ VSHLiv4i32 = 1239,
+ VSHLiv8i16 = 1240,
+ VSHLiv8i8 = 1241,
+ VSHLsv16i8 = 1242,
+ VSHLsv1i64 = 1243,
+ VSHLsv2i32 = 1244,
+ VSHLsv2i64 = 1245,
+ VSHLsv4i16 = 1246,
+ VSHLsv4i32 = 1247,
+ VSHLsv8i16 = 1248,
+ VSHLsv8i8 = 1249,
+ VSHLuv16i8 = 1250,
+ VSHLuv1i64 = 1251,
+ VSHLuv2i32 = 1252,
+ VSHLuv2i64 = 1253,
+ VSHLuv4i16 = 1254,
+ VSHLuv4i32 = 1255,
+ VSHLuv8i16 = 1256,
+ VSHLuv8i8 = 1257,
+ VSHRNv2i32 = 1258,
+ VSHRNv4i16 = 1259,
+ VSHRNv8i8 = 1260,
+ VSHRsv16i8 = 1261,
+ VSHRsv1i64 = 1262,
+ VSHRsv2i32 = 1263,
+ VSHRsv2i64 = 1264,
+ VSHRsv4i16 = 1265,
+ VSHRsv4i32 = 1266,
+ VSHRsv8i16 = 1267,
+ VSHRsv8i8 = 1268,
+ VSHRuv16i8 = 1269,
+ VSHRuv1i64 = 1270,
+ VSHRuv2i32 = 1271,
+ VSHRuv2i64 = 1272,
+ VSHRuv4i16 = 1273,
+ VSHRuv4i32 = 1274,
+ VSHRuv8i16 = 1275,
+ VSHRuv8i8 = 1276,
+ VSHTOD = 1277,
+ VSHTOS = 1278,
+ VSITOD = 1279,
+ VSITOS = 1280,
+ VSLIv16i8 = 1281,
+ VSLIv1i64 = 1282,
+ VSLIv2i32 = 1283,
+ VSLIv2i64 = 1284,
+ VSLIv4i16 = 1285,
+ VSLIv4i32 = 1286,
+ VSLIv8i16 = 1287,
+ VSLIv8i8 = 1288,
+ VSLTOD = 1289,
+ VSLTOS = 1290,
+ VSQRTD = 1291,
+ VSQRTS = 1292,
+ VSRAsv16i8 = 1293,
+ VSRAsv1i64 = 1294,
+ VSRAsv2i32 = 1295,
+ VSRAsv2i64 = 1296,
+ VSRAsv4i16 = 1297,
+ VSRAsv4i32 = 1298,
+ VSRAsv8i16 = 1299,
+ VSRAsv8i8 = 1300,
+ VSRAuv16i8 = 1301,
+ VSRAuv1i64 = 1302,
+ VSRAuv2i32 = 1303,
+ VSRAuv2i64 = 1304,
+ VSRAuv4i16 = 1305,
+ VSRAuv4i32 = 1306,
+ VSRAuv8i16 = 1307,
+ VSRAuv8i8 = 1308,
+ VSRIv16i8 = 1309,
+ VSRIv1i64 = 1310,
+ VSRIv2i32 = 1311,
+ VSRIv2i64 = 1312,
+ VSRIv4i16 = 1313,
+ VSRIv4i32 = 1314,
+ VSRIv8i16 = 1315,
+ VSRIv8i8 = 1316,
+ VST1d16 = 1317,
+ VST1d16Q = 1318,
+ VST1d16T = 1319,
+ VST1d32 = 1320,
+ VST1d32Q = 1321,
+ VST1d32T = 1322,
+ VST1d64 = 1323,
+ VST1d8 = 1324,
+ VST1d8Q = 1325,
+ VST1d8T = 1326,
+ VST1df = 1327,
+ VST1q16 = 1328,
+ VST1q32 = 1329,
+ VST1q64 = 1330,
+ VST1q8 = 1331,
+ VST1qf = 1332,
+ VST2LNd16 = 1333,
+ VST2LNd32 = 1334,
+ VST2LNd8 = 1335,
+ VST2LNq16a = 1336,
+ VST2LNq16b = 1337,
+ VST2LNq32a = 1338,
+ VST2LNq32b = 1339,
+ VST2d16 = 1340,
+ VST2d16D = 1341,
+ VST2d32 = 1342,
+ VST2d32D = 1343,
+ VST2d64 = 1344,
+ VST2d8 = 1345,
+ VST2d8D = 1346,
+ VST2q16 = 1347,
+ VST2q32 = 1348,
+ VST2q8 = 1349,
+ VST3LNd16 = 1350,
+ VST3LNd32 = 1351,
+ VST3LNd8 = 1352,
+ VST3LNq16a = 1353,
+ VST3LNq16b = 1354,
+ VST3LNq32a = 1355,
+ VST3LNq32b = 1356,
+ VST3d16 = 1357,
+ VST3d32 = 1358,
+ VST3d64 = 1359,
+ VST3d8 = 1360,
+ VST3q16a = 1361,
+ VST3q16b = 1362,
+ VST3q32a = 1363,
+ VST3q32b = 1364,
+ VST3q8a = 1365,
+ VST3q8b = 1366,
+ VST4LNd16 = 1367,
+ VST4LNd32 = 1368,
+ VST4LNd8 = 1369,
+ VST4LNq16a = 1370,
+ VST4LNq16b = 1371,
+ VST4LNq32a = 1372,
+ VST4LNq32b = 1373,
+ VST4d16 = 1374,
+ VST4d32 = 1375,
+ VST4d64 = 1376,
+ VST4d8 = 1377,
+ VST4q16a = 1378,
+ VST4q16b = 1379,
+ VST4q32a = 1380,
+ VST4q32b = 1381,
+ VST4q8a = 1382,
+ VST4q8b = 1383,
+ VSTMD = 1384,
+ VSTMS = 1385,
+ VSTRD = 1386,
+ VSTRQ = 1387,
+ VSTRS = 1388,
+ VSUBD = 1389,
+ VSUBHNv2i32 = 1390,
+ VSUBHNv4i16 = 1391,
+ VSUBHNv8i8 = 1392,
+ VSUBLsv2i64 = 1393,
+ VSUBLsv4i32 = 1394,
+ VSUBLsv8i16 = 1395,
+ VSUBLuv2i64 = 1396,
+ VSUBLuv4i32 = 1397,
+ VSUBLuv8i16 = 1398,
+ VSUBS = 1399,
+ VSUBWsv2i64 = 1400,
+ VSUBWsv4i32 = 1401,
+ VSUBWsv8i16 = 1402,
+ VSUBWuv2i64 = 1403,
+ VSUBWuv4i32 = 1404,
+ VSUBWuv8i16 = 1405,
+ VSUBfd = 1406,
+ VSUBfd_sfp = 1407,
+ VSUBfq = 1408,
+ VSUBv16i8 = 1409,
+ VSUBv1i64 = 1410,
+ VSUBv2i32 = 1411,
+ VSUBv2i64 = 1412,
+ VSUBv4i16 = 1413,
+ VSUBv4i32 = 1414,
+ VSUBv8i16 = 1415,
+ VSUBv8i8 = 1416,
+ VSWPd = 1417,
+ VSWPq = 1418,
+ VTBL1 = 1419,
+ VTBL2 = 1420,
+ VTBL3 = 1421,
+ VTBL4 = 1422,
+ VTBX1 = 1423,
+ VTBX2 = 1424,
+ VTBX3 = 1425,
+ VTBX4 = 1426,
+ VTOSHD = 1427,
+ VTOSHS = 1428,
+ VTOSIRD = 1429,
+ VTOSIRS = 1430,
+ VTOSIZD = 1431,
+ VTOSIZS = 1432,
+ VTOSLD = 1433,
+ VTOSLS = 1434,
+ VTOUHD = 1435,
+ VTOUHS = 1436,
+ VTOUIRD = 1437,
+ VTOUIRS = 1438,
+ VTOUIZD = 1439,
+ VTOUIZS = 1440,
+ VTOULD = 1441,
+ VTOULS = 1442,
+ VTRNd16 = 1443,
+ VTRNd32 = 1444,
+ VTRNd8 = 1445,
+ VTRNq16 = 1446,
+ VTRNq32 = 1447,
+ VTRNq8 = 1448,
+ VTSTv16i8 = 1449,
+ VTSTv2i32 = 1450,
+ VTSTv4i16 = 1451,
+ VTSTv4i32 = 1452,
+ VTSTv8i16 = 1453,
+ VTSTv8i8 = 1454,
+ VUHTOD = 1455,
+ VUHTOS = 1456,
+ VUITOD = 1457,
+ VUITOS = 1458,
+ VULTOD = 1459,
+ VULTOS = 1460,
+ VUZPd16 = 1461,
+ VUZPd32 = 1462,
+ VUZPd8 = 1463,
+ VUZPq16 = 1464,
+ VUZPq32 = 1465,
+ VUZPq8 = 1466,
+ VZIPd16 = 1467,
+ VZIPd32 = 1468,
+ VZIPd8 = 1469,
+ VZIPq16 = 1470,
+ VZIPq32 = 1471,
+ VZIPq8 = 1472,
+ WFE = 1473,
+ WFI = 1474,
+ YIELD = 1475,
+ t2ADCSri = 1476,
+ t2ADCSrr = 1477,
+ t2ADCSrs = 1478,
+ t2ADCri = 1479,
+ t2ADCrr = 1480,
+ t2ADCrs = 1481,
+ t2ADDSri = 1482,
+ t2ADDSrr = 1483,
+ t2ADDSrs = 1484,
+ t2ADDrSPi = 1485,
+ t2ADDrSPi12 = 1486,
+ t2ADDrSPs = 1487,
+ t2ADDri = 1488,
+ t2ADDri12 = 1489,
+ t2ADDrr = 1490,
+ t2ADDrs = 1491,
+ t2ANDri = 1492,
+ t2ANDrr = 1493,
+ t2ANDrs = 1494,
+ t2ASRri = 1495,
+ t2ASRrr = 1496,
+ t2B = 1497,
+ t2BFC = 1498,
+ t2BFI = 1499,
+ t2BICri = 1500,
+ t2BICrr = 1501,
+ t2BICrs = 1502,
+ t2BR_JT = 1503,
+ t2BXJ = 1504,
+ t2Bcc = 1505,
+ t2CLREX = 1506,
+ t2CLZ = 1507,
+ t2CMNzri = 1508,
+ t2CMNzrr = 1509,
+ t2CMNzrs = 1510,
+ t2CMPri = 1511,
+ t2CMPrr = 1512,
+ t2CMPrs = 1513,
+ t2CMPzri = 1514,
+ t2CMPzrr = 1515,
+ t2CMPzrs = 1516,
+ t2CPS = 1517,
+ t2DBG = 1518,
+ t2DMBish = 1519,
+ t2DMBishst = 1520,
+ t2DMBnsh = 1521,
+ t2DMBnshst = 1522,
+ t2DMBosh = 1523,
+ t2DMBoshst = 1524,
+ t2DMBst = 1525,
+ t2DSBish = 1526,
+ t2DSBishst = 1527,
+ t2DSBnsh = 1528,
+ t2DSBnshst = 1529,
+ t2DSBosh = 1530,
+ t2DSBoshst = 1531,
+ t2DSBst = 1532,
+ t2EORri = 1533,
+ t2EORrr = 1534,
+ t2EORrs = 1535,
+ t2ISBsy = 1536,
+ t2IT = 1537,
+ t2Int_MemBarrierV7 = 1538,
+ t2Int_SyncBarrierV7 = 1539,
+ t2Int_eh_sjlj_setjmp = 1540,
+ t2LDM = 1541,
+ t2LDM_RET = 1542,
+ t2LDRBT = 1543,
+ t2LDRB_POST = 1544,
+ t2LDRB_PRE = 1545,
+ t2LDRBi12 = 1546,
+ t2LDRBi8 = 1547,
+ t2LDRBpci = 1548,
+ t2LDRBs = 1549,
+ t2LDRDi8 = 1550,
+ t2LDRDpci = 1551,
+ t2LDREX = 1552,
+ t2LDREXB = 1553,
+ t2LDREXD = 1554,
+ t2LDREXH = 1555,
+ t2LDRHT = 1556,
+ t2LDRH_POST = 1557,
+ t2LDRH_PRE = 1558,
+ t2LDRHi12 = 1559,
+ t2LDRHi8 = 1560,
+ t2LDRHpci = 1561,
+ t2LDRHs = 1562,
+ t2LDRSBT = 1563,
+ t2LDRSB_POST = 1564,
+ t2LDRSB_PRE = 1565,
+ t2LDRSBi12 = 1566,
+ t2LDRSBi8 = 1567,
+ t2LDRSBpci = 1568,
+ t2LDRSBs = 1569,
+ t2LDRSHT = 1570,
+ t2LDRSH_POST = 1571,
+ t2LDRSH_PRE = 1572,
+ t2LDRSHi12 = 1573,
+ t2LDRSHi8 = 1574,
+ t2LDRSHpci = 1575,
+ t2LDRSHs = 1576,
+ t2LDRT = 1577,
+ t2LDR_POST = 1578,
+ t2LDR_PRE = 1579,
+ t2LDRi12 = 1580,
+ t2LDRi8 = 1581,
+ t2LDRpci = 1582,
+ t2LDRpci_pic = 1583,
+ t2LDRs = 1584,
+ t2LEApcrel = 1585,
+ t2LEApcrelJT = 1586,
+ t2LSLri = 1587,
+ t2LSLrr = 1588,
+ t2LSRri = 1589,
+ t2LSRrr = 1590,
+ t2MLA = 1591,
+ t2MLS = 1592,
+ t2MOVCCasr = 1593,
+ t2MOVCCi = 1594,
+ t2MOVCClsl = 1595,
+ t2MOVCClsr = 1596,
+ t2MOVCCr = 1597,
+ t2MOVCCror = 1598,
+ t2MOVTi16 = 1599,
+ t2MOVi = 1600,
+ t2MOVi16 = 1601,
+ t2MOVi32imm = 1602,
+ t2MOVr = 1603,
+ t2MOVrx = 1604,
+ t2MOVsra_flag = 1605,
+ t2MOVsrl_flag = 1606,
+ t2MRS = 1607,
+ t2MRSsys = 1608,
+ t2MSR = 1609,
+ t2MSRsys = 1610,
+ t2MUL = 1611,
+ t2MVNi = 1612,
+ t2MVNr = 1613,
+ t2MVNs = 1614,
+ t2NOP = 1615,
+ t2ORNri = 1616,
+ t2ORNrr = 1617,
+ t2ORNrs = 1618,
+ t2ORRri = 1619,
+ t2ORRrr = 1620,
+ t2ORRrs = 1621,
+ t2PKHBT = 1622,
+ t2PKHTB = 1623,
+ t2PLDWi12 = 1624,
+ t2PLDWi8 = 1625,
+ t2PLDWpci = 1626,
+ t2PLDWr = 1627,
+ t2PLDWs = 1628,
+ t2PLDi12 = 1629,
+ t2PLDi8 = 1630,
+ t2PLDpci = 1631,
+ t2PLDr = 1632,
+ t2PLDs = 1633,
+ t2PLIi12 = 1634,
+ t2PLIi8 = 1635,
+ t2PLIpci = 1636,
+ t2PLIr = 1637,
+ t2PLIs = 1638,
+ t2QADD = 1639,
+ t2QADD16 = 1640,
+ t2QADD8 = 1641,
+ t2QASX = 1642,
+ t2QDADD = 1643,
+ t2QDSUB = 1644,
+ t2QSAX = 1645,
+ t2QSUB = 1646,
+ t2QSUB16 = 1647,
+ t2QSUB8 = 1648,
+ t2RBIT = 1649,
+ t2REV = 1650,
+ t2REV16 = 1651,
+ t2REVSH = 1652,
+ t2RFEDB = 1653,
+ t2RFEDBW = 1654,
+ t2RFEIA = 1655,
+ t2RFEIAW = 1656,
+ t2RORri = 1657,
+ t2RORrr = 1658,
+ t2RSBSri = 1659,
+ t2RSBSrs = 1660,
+ t2RSBri = 1661,
+ t2RSBrs = 1662,
+ t2SADD16 = 1663,
+ t2SADD8 = 1664,
+ t2SASX = 1665,
+ t2SBCSri = 1666,
+ t2SBCSrr = 1667,
+ t2SBCSrs = 1668,
+ t2SBCri = 1669,
+ t2SBCrr = 1670,
+ t2SBCrs = 1671,
+ t2SBFX = 1672,
+ t2SDIV = 1673,
+ t2SEL = 1674,
+ t2SEV = 1675,
+ t2SHADD16 = 1676,
+ t2SHADD8 = 1677,
+ t2SHASX = 1678,
+ t2SHSAX = 1679,
+ t2SHSUB16 = 1680,
+ t2SHSUB8 = 1681,
+ t2SMC = 1682,
+ t2SMLABB = 1683,
+ t2SMLABT = 1684,
+ t2SMLAD = 1685,
+ t2SMLADX = 1686,
+ t2SMLAL = 1687,
+ t2SMLALBB = 1688,
+ t2SMLALBT = 1689,
+ t2SMLALD = 1690,
+ t2SMLALDX = 1691,
+ t2SMLALTB = 1692,
+ t2SMLALTT = 1693,
+ t2SMLATB = 1694,
+ t2SMLATT = 1695,
+ t2SMLAWB = 1696,
+ t2SMLAWT = 1697,
+ t2SMLSD = 1698,
+ t2SMLSDX = 1699,
+ t2SMLSLD = 1700,
+ t2SMLSLDX = 1701,
+ t2SMMLA = 1702,
+ t2SMMLAR = 1703,
+ t2SMMLS = 1704,
+ t2SMMLSR = 1705,
+ t2SMMUL = 1706,
+ t2SMMULR = 1707,
+ t2SMUAD = 1708,
+ t2SMUADX = 1709,
+ t2SMULBB = 1710,
+ t2SMULBT = 1711,
+ t2SMULL = 1712,
+ t2SMULTB = 1713,
+ t2SMULTT = 1714,
+ t2SMULWB = 1715,
+ t2SMULWT = 1716,
+ t2SMUSD = 1717,
+ t2SMUSDX = 1718,
+ t2SRSDB = 1719,
+ t2SRSDBW = 1720,
+ t2SRSIA = 1721,
+ t2SRSIAW = 1722,
+ t2SSAT16 = 1723,
+ t2SSATasr = 1724,
+ t2SSATlsl = 1725,
+ t2SSAX = 1726,
+ t2SSUB16 = 1727,
+ t2SSUB8 = 1728,
+ t2STM = 1729,
+ t2STRBT = 1730,
+ t2STRB_POST = 1731,
+ t2STRB_PRE = 1732,
+ t2STRBi12 = 1733,
+ t2STRBi8 = 1734,
+ t2STRBs = 1735,
+ t2STRDi8 = 1736,
+ t2STREX = 1737,
+ t2STREXB = 1738,
+ t2STREXD = 1739,
+ t2STREXH = 1740,
+ t2STRHT = 1741,
+ t2STRH_POST = 1742,
+ t2STRH_PRE = 1743,
+ t2STRHi12 = 1744,
+ t2STRHi8 = 1745,
+ t2STRHs = 1746,
+ t2STRT = 1747,
+ t2STR_POST = 1748,
+ t2STR_PRE = 1749,
+ t2STRi12 = 1750,
+ t2STRi8 = 1751,
+ t2STRs = 1752,
+ t2SUBSri = 1753,
+ t2SUBSrr = 1754,
+ t2SUBSrs = 1755,
+ t2SUBrSPi = 1756,
+ t2SUBrSPi12 = 1757,
+ t2SUBrSPi12_ = 1758,
+ t2SUBrSPi_ = 1759,
+ t2SUBrSPs = 1760,
+ t2SUBrSPs_ = 1761,
+ t2SUBri = 1762,
+ t2SUBri12 = 1763,
+ t2SUBrr = 1764,
+ t2SUBrs = 1765,
+ t2SXTAB16rr = 1766,
+ t2SXTAB16rr_rot = 1767,
+ t2SXTABrr = 1768,
+ t2SXTABrr_rot = 1769,
+ t2SXTAHrr = 1770,
+ t2SXTAHrr_rot = 1771,
+ t2SXTB16r = 1772,
+ t2SXTB16r_rot = 1773,
+ t2SXTBr = 1774,
+ t2SXTBr_rot = 1775,
+ t2SXTHr = 1776,
+ t2SXTHr_rot = 1777,
+ t2TBB = 1778,
+ t2TBBgen = 1779,
+ t2TBH = 1780,
+ t2TBHgen = 1781,
+ t2TEQri = 1782,
+ t2TEQrr = 1783,
+ t2TEQrs = 1784,
+ t2TPsoft = 1785,
+ t2TSTri = 1786,
+ t2TSTrr = 1787,
+ t2TSTrs = 1788,
+ t2UADD16 = 1789,
+ t2UADD8 = 1790,
+ t2UASX = 1791,
+ t2UBFX = 1792,
+ t2UDIV = 1793,
+ t2UHADD16 = 1794,
+ t2UHADD8 = 1795,
+ t2UHASX = 1796,
+ t2UHSAX = 1797,
+ t2UHSUB16 = 1798,
+ t2UHSUB8 = 1799,
+ t2UMAAL = 1800,
+ t2UMLAL = 1801,
+ t2UMULL = 1802,
+ t2UQADD16 = 1803,
+ t2UQADD8 = 1804,
+ t2UQASX = 1805,
+ t2UQSAX = 1806,
+ t2UQSUB16 = 1807,
+ t2UQSUB8 = 1808,
+ t2USAD8 = 1809,
+ t2USADA8 = 1810,
+ t2USAT16 = 1811,
+ t2USATasr = 1812,
+ t2USATlsl = 1813,
+ t2USAX = 1814,
+ t2USUB16 = 1815,
+ t2USUB8 = 1816,
+ t2UXTAB16rr = 1817,
+ t2UXTAB16rr_rot = 1818,
+ t2UXTABrr = 1819,
+ t2UXTABrr_rot = 1820,
+ t2UXTAHrr = 1821,
+ t2UXTAHrr_rot = 1822,
+ t2UXTB16r = 1823,
+ t2UXTB16r_rot = 1824,
+ t2UXTBr = 1825,
+ t2UXTBr_rot = 1826,
+ t2UXTHr = 1827,
+ t2UXTHr_rot = 1828,
+ t2WFE = 1829,
+ t2WFI = 1830,
+ t2YIELD = 1831,
+ tADC = 1832,
+ tADDhirr = 1833,
+ tADDi3 = 1834,
+ tADDi8 = 1835,
+ tADDrPCi = 1836,
+ tADDrSP = 1837,
+ tADDrSPi = 1838,
+ tADDrr = 1839,
+ tADDspi = 1840,
+ tADDspr = 1841,
+ tADDspr_ = 1842,
+ tADJCALLSTACKDOWN = 1843,
+ tADJCALLSTACKUP = 1844,
+ tAND = 1845,
+ tANDsp = 1846,
+ tASRri = 1847,
+ tASRrr = 1848,
+ tB = 1849,
+ tBIC = 1850,
+ tBKPT = 1851,
+ tBL = 1852,
+ tBLXi = 1853,
+ tBLXi_r9 = 1854,
+ tBLXr = 1855,
+ tBLXr_r9 = 1856,
+ tBLr9 = 1857,
+ tBRIND = 1858,
+ tBR_JTr = 1859,
+ tBX = 1860,
+ tBX_RET = 1861,
+ tBX_RET_vararg = 1862,
+ tBXr9 = 1863,
+ tBcc = 1864,
+ tBfar = 1865,
+ tCBNZ = 1866,
+ tCBZ = 1867,
+ tCMNz = 1868,
+ tCMPhir = 1869,
+ tCMPi8 = 1870,
+ tCMPr = 1871,
+ tCMPzhir = 1872,
+ tCMPzi8 = 1873,
+ tCMPzr = 1874,
+ tCPS = 1875,
+ tEOR = 1876,
+ tInt_eh_sjlj_setjmp = 1877,
+ tLDM = 1878,
+ tLDR = 1879,
+ tLDRB = 1880,
+ tLDRBi = 1881,
+ tLDRH = 1882,
+ tLDRHi = 1883,
+ tLDRSB = 1884,
+ tLDRSH = 1885,
+ tLDRcp = 1886,
+ tLDRi = 1887,
+ tLDRpci = 1888,
+ tLDRpci_pic = 1889,
+ tLDRspi = 1890,
+ tLEApcrel = 1891,
+ tLEApcrelJT = 1892,
+ tLSLri = 1893,
+ tLSLrr = 1894,
+ tLSRri = 1895,
+ tLSRrr = 1896,
+ tMOVCCi = 1897,
+ tMOVCCr = 1898,
+ tMOVCCr_pseudo = 1899,
+ tMOVSr = 1900,
+ tMOVgpr2gpr = 1901,
+ tMOVgpr2tgpr = 1902,
+ tMOVi8 = 1903,
+ tMOVr = 1904,
+ tMOVtgpr2gpr = 1905,
+ tMUL = 1906,
+ tMVN = 1907,
+ tNOP = 1908,
+ tORR = 1909,
+ tPICADD = 1910,
+ tPOP = 1911,
+ tPOP_RET = 1912,
+ tPUSH = 1913,
+ tREV = 1914,
+ tREV16 = 1915,
+ tREVSH = 1916,
+ tROR = 1917,
+ tRSB = 1918,
+ tRestore = 1919,
+ tSBC = 1920,
+ tSETENDBE = 1921,
+ tSETENDLE = 1922,
+ tSEV = 1923,
+ tSTM = 1924,
+ tSTR = 1925,
+ tSTRB = 1926,
+ tSTRBi = 1927,
+ tSTRH = 1928,
+ tSTRHi = 1929,
+ tSTRi = 1930,
+ tSTRspi = 1931,
+ tSUBi3 = 1932,
+ tSUBi8 = 1933,
+ tSUBrr = 1934,
+ tSUBspi = 1935,
+ tSUBspi_ = 1936,
+ tSVC = 1937,
+ tSXTB = 1938,
+ tSXTH = 1939,
+ tSpill = 1940,
+ tTPsoft = 1941,
+ tTRAP = 1942,
+ tTST = 1943,
+ tUXTB = 1944,
+ tUXTH = 1945,
+ tWFE = 1946,
+ tWFI = 1947,
+ tYIELD = 1948,
+ INSTRUCTION_LIST_END = 1949
};
}
} // End llvm namespace
diff --git a/libclamav/c++/PPCGenDAGISel.inc b/libclamav/c++/PPCGenDAGISel.inc
index 88fcf32..cd4615a 100644
--- a/libclamav/c++/PPCGenDAGISel.inc
+++ b/libclamav/c++/PPCGenDAGISel.inc
@@ -2021,46 +2021,37 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::i64, 2, 0, 1,
0,
0,
- 12|128,8, ISD::LOAD,
+ 27|128,7, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
OPC_CheckPredicate, 2,
- OPC_Scope, 24,
+ OPC_Scope, 21,
OPC_CheckPredicate, 3,
OPC_CheckPredicate, 4,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/1, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZ), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 2, 3,
- 24,
+ 21,
OPC_CheckPredicate, 5,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/1, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::LHA), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 2, 3,
- 24,
+ 21,
OPC_CheckPredicate, 3,
OPC_CheckPredicate, 7,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/1, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::LHZ), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 2, 3,
- 58,
+ 55,
OPC_CheckPredicate, 8,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_SwitchType , 15, MVT::i32,
OPC_CheckComplexPat, /*CP*/1, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
@@ -2077,44 +2068,32 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(PPC::LFD), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f64, 2, 2, 3,
0,
- 24,
+ 21,
OPC_CheckPredicate, 3,
OPC_CheckPredicate, 4,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/2, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZX), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 2, 3,
- 24,
+ 21,
OPC_CheckPredicate, 5,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/2, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::LHAX), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 2, 3,
- 24,
+ 21,
OPC_CheckPredicate, 3,
OPC_CheckPredicate, 7,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/2, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::LHZX), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 2, 3,
- 58,
+ 55,
OPC_CheckPredicate, 8,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_SwitchType , 15, MVT::i32,
OPC_CheckComplexPat, /*CP*/2, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
@@ -2131,12 +2110,9 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(PPC::LFDX), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f64, 2, 2, 3,
0,
- 43,
+ 40,
OPC_CheckPredicate, 3,
OPC_CheckPredicate, 9,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i32,
OPC_Scope, 15,
OPC_CheckComplexPat, /*CP*/1, /*#*/1,
@@ -2149,14 +2125,11 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZX), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 2, 3,
0,
- 2|128,1,
+ 117,
OPC_CheckPredicate, 10,
- OPC_Scope, 41,
+ OPC_CheckType, MVT::i32,
+ OPC_Scope, 36,
OPC_CheckPredicate, 11,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
OPC_Scope, 15,
OPC_CheckComplexPat, /*CP*/1, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
@@ -2168,12 +2141,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZX), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 2, 3,
0,
- 41,
+ 36,
OPC_CheckPredicate, 12,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
OPC_Scope, 15,
OPC_CheckComplexPat, /*CP*/1, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
@@ -2185,12 +2154,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZX), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 2, 2, 3,
0,
- 41,
+ 36,
OPC_CheckPredicate, 13,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
OPC_Scope, 15,
OPC_CheckComplexPat, /*CP*/1, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
@@ -2203,127 +2168,83 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::i32, 2, 2, 3,
0,
0,
- 22,
+ 19,
OPC_CheckPredicate, 8,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::v4i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::LVX), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v4i32, 2, 2, 3,
- 96,
+ 78,
OPC_CheckPredicate, 5,
- OPC_Scope, 22,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 17,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/1, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::LHA8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 2, 2, 3,
- 22,
+ 17,
OPC_CheckPredicate, 14,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/3, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::LWA), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 2, 2, 3,
- 22,
+ 17,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/2, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::LHAX8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 2, 2, 3,
- 22,
+ 17,
OPC_CheckPredicate, 14,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/2, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::LWAX), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 2, 2, 3,
0,
- 14|128,1,
+ 114,
OPC_CheckPredicate, 3,
- OPC_Scope, 22,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 17,
OPC_CheckPredicate, 4,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/1, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZ8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 2, 2, 3,
- 22,
+ 17,
OPC_CheckPredicate, 7,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/1, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::LHZ8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 2, 2, 3,
- 22,
+ 17,
OPC_CheckPredicate, 15,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/1, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::LWZ8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 2, 2, 3,
- 22,
+ 17,
OPC_CheckPredicate, 4,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/2, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZX8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 2, 2, 3,
- 22,
+ 17,
OPC_CheckPredicate, 7,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/2, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::LHZX8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 2, 2, 3,
- 22,
+ 17,
OPC_CheckPredicate, 15,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/2, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::LWZX8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 2, 2, 3,
0,
- 41,
+ 38,
OPC_CheckPredicate, 8,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i64,
OPC_Scope, 15,
OPC_CheckComplexPat, /*CP*/3, /*#*/1,
@@ -2336,12 +2257,9 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(PPC::LDX), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 2, 2, 3,
0,
- 43,
+ 40,
OPC_CheckPredicate, 3,
OPC_CheckPredicate, 9,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i64,
OPC_Scope, 15,
OPC_CheckComplexPat, /*CP*/1, /*#*/1,
@@ -2354,82 +2272,64 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZX8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 2, 2, 3,
0,
- 108|128,1,
+ 89|128,1,
OPC_CheckPredicate, 10,
- OPC_Scope, 41,
- OPC_CheckPredicate, 11,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
- OPC_Scope, 15,
- OPC_CheckComplexPat, /*CP*/1, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZ8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i64, 2, 2, 3,
- 15,
- OPC_CheckComplexPat, /*CP*/2, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZX8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i64, 2, 2, 3,
- 0,
- 41,
- OPC_CheckPredicate, 12,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
- OPC_Scope, 15,
- OPC_CheckComplexPat, /*CP*/1, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZ8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i64, 2, 2, 3,
- 15,
- OPC_CheckComplexPat, /*CP*/2, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZX8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i64, 2, 2, 3,
- 0,
- 41,
- OPC_CheckPredicate, 13,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
- OPC_Scope, 15,
- OPC_CheckComplexPat, /*CP*/1, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::LHZ8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i64, 2, 2, 3,
- 15,
- OPC_CheckComplexPat, /*CP*/2, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::LHZX8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i64, 2, 2, 3,
- 0,
- 41,
- OPC_CheckPredicate, 16,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
- OPC_Scope, 15,
- OPC_CheckComplexPat, /*CP*/1, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::LWZ8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i64, 2, 2, 3,
- 15,
- OPC_CheckComplexPat, /*CP*/2, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::LWZX8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i64, 2, 2, 3,
+ OPC_SwitchType , 22|128,1, MVT::i64,
+ OPC_Scope, 36,
+ OPC_CheckPredicate, 11,
+ OPC_Scope, 15,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZ8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 15,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZX8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 0,
+ 36,
+ OPC_CheckPredicate, 12,
+ OPC_Scope, 15,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZ8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 15,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LBZX8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 0,
+ 36,
+ OPC_CheckPredicate, 13,
+ OPC_Scope, 15,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LHZ8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 15,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LHZX8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 0,
+ 36,
+ OPC_CheckPredicate, 16,
+ OPC_Scope, 15,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LWZ8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 15,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LWZX8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i64, 2, 2, 3,
+ 0,
0,
- 63,
+ 58, MVT::f64,
OPC_CheckPredicate, 17,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::f64,
OPC_Scope, 26,
OPC_CheckComplexPat, /*CP*/1, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
@@ -2451,308 +2351,231 @@ SDNode *SelectCode(SDNode *N) {
0,
0,
0,
- 35|128,5, ISD::STORE,
- OPC_Scope, 68|128,3,
- OPC_CheckPredicate, 18,
- OPC_Scope, 52,
- OPC_CheckPredicate, 19,
- OPC_Scope, 23,
- OPC_CheckPredicate, 20,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/1, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::STB), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 3, 1, 3, 4,
- 23,
- OPC_CheckPredicate, 21,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/1, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::STH), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 3, 1, 3, 4,
- 0,
- 64,
- OPC_CheckPredicate, 22,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_Scope, 18,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
+ 83|128,4, ISD::STORE,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_Scope, 70|128,1,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_Scope, 122,
+ OPC_CheckPredicate, 18,
+ OPC_Scope, 40,
+ OPC_CheckPredicate, 19,
+ OPC_Scope, 17,
+ OPC_CheckPredicate, 20,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STB), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 17,
+ OPC_CheckPredicate, 21,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STH), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 0,
+ 17,
+ OPC_CheckPredicate, 22,
OPC_CheckComplexPat, /*CP*/1, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::STW), 0|OPFL_Chain|OPFL_MemRefs,
0, 3, 1, 3, 4,
- 18,
- OPC_CheckChild1Type, MVT::f32,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/1, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::STFS), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 3, 1, 3, 4,
- 18,
- OPC_CheckChild1Type, MVT::f64,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/1, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::STFD), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 3, 1, 3, 4,
- 0,
- 52,
- OPC_CheckPredicate, 19,
- OPC_Scope, 23,
- OPC_CheckPredicate, 20,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/2, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::STBX), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 3, 1, 3, 4,
- 23,
- OPC_CheckPredicate, 21,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/2, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::STHX), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 3, 1, 3, 4,
- 0,
- 83,
- OPC_CheckPredicate, 22,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_Scope, 18,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
+ 40,
+ OPC_CheckPredicate, 19,
+ OPC_Scope, 17,
+ OPC_CheckPredicate, 20,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STBX), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 17,
+ OPC_CheckPredicate, 21,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STHX), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 0,
+ 17,
+ OPC_CheckPredicate, 22,
OPC_CheckComplexPat, /*CP*/2, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::STWX), 0|OPFL_Chain|OPFL_MemRefs,
0, 3, 1, 3, 4,
- 18,
- OPC_CheckChild1Type, MVT::f32,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/2, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::STFSX), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 3, 1, 3, 4,
- 18,
- OPC_CheckChild1Type, MVT::f64,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/2, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::STFDX), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 3, 1, 3, 4,
- 18,
- OPC_CheckChild1Type, MVT::v4i32,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::STVX), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 3, 1, 3, 4,
0,
- 20|128,1,
- OPC_CheckPredicate, 19,
- OPC_Scope, 23,
- OPC_CheckPredicate, 20,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i64,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/1, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::STB8), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 3, 1, 3, 4,
- 23,
- OPC_CheckPredicate, 21,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i64,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/1, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::STH8), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 3, 1, 3, 4,
- 23,
- OPC_CheckPredicate, 23,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i64,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/1, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::STW8), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 3, 1, 3, 4,
- 23,
- OPC_CheckPredicate, 20,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i64,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/2, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::STBX8), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 3, 1, 3, 4,
- 23,
- OPC_CheckPredicate, 21,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i64,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/2, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::STHX8), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 3, 1, 3, 4,
- 23,
+ 69,
+ OPC_RecordChild3,
+ OPC_Scope, 44,
OPC_CheckPredicate, 23,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i64,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/2, /*#*/2,
+ OPC_CheckPredicate, 24,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 25,
+ OPC_CheckComplexPat, /*CP*/4, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STBU), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::iPTR, 3, 1, 4, 2,
+ 18,
+ OPC_CheckPredicate, 26,
+ OPC_CheckComplexPat, /*CP*/4, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STHU), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::iPTR, 3, 1, 4, 2,
+ 0,
+ 20,
+ OPC_CheckPredicate, 27,
+ OPC_CheckPredicate, 28,
+ OPC_CheckComplexPat, /*CP*/4, /*#*/3,
OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::STWX8), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 3, 1, 3, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STWU), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::iPTR, 3, 1, 4, 2,
0,
- 42,
+ 0,
+ 66,
+ OPC_CheckChild1Type, MVT::f32,
+ OPC_RecordChild2,
+ OPC_Scope, 38,
+ OPC_CheckPredicate, 18,
OPC_CheckPredicate, 22,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i64,
- OPC_RecordChild2,
OPC_Scope, 15,
- OPC_CheckComplexPat, /*CP*/3, /*#*/2,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::STD), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STFS), 0|OPFL_Chain|OPFL_MemRefs,
0, 3, 1, 3, 4,
15,
OPC_CheckComplexPat, /*CP*/2, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::STDX), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STFSX), 0|OPFL_Chain|OPFL_MemRefs,
0, 3, 1, 3, 4,
0,
- 0,
- 58,
- OPC_CheckPredicate, 24,
- OPC_CheckPredicate, 25,
- OPC_Scope, 25,
- OPC_CheckPredicate, 26,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
+ 21,
OPC_RecordChild3,
- OPC_CheckComplexPat, /*CP*/4, /*#*/3,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::STBU), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::iPTR, 3, 1, 4, 2,
- 25,
OPC_CheckPredicate, 27,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_RecordChild3,
- OPC_CheckComplexPat, /*CP*/4, /*#*/3,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::STHU), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::iPTR, 3, 1, 4, 2,
- 0,
- 72,
- OPC_CheckPredicate, 28,
- OPC_CheckPredicate, 29,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_Scope, 20,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_RecordChild3,
- OPC_CheckComplexPat, /*CP*/4, /*#*/3,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::STWU), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::iPTR, 3, 1, 4, 2,
- 20,
- OPC_CheckChild1Type, MVT::f32,
- OPC_RecordChild2,
- OPC_RecordChild3,
+ OPC_CheckPredicate, 28,
OPC_CheckComplexPat, /*CP*/4, /*#*/3,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::STFSU), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::iPTR, 3, 1, 4, 2,
- 20,
- OPC_CheckChild1Type, MVT::f64,
- OPC_RecordChild2,
- OPC_RecordChild3,
- OPC_CheckComplexPat, /*CP*/4, /*#*/3,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::STFDU), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::iPTR, 3, 1, 4, 2,
0,
- 58,
- OPC_CheckPredicate, 24,
- OPC_CheckPredicate, 25,
- OPC_Scope, 25,
- OPC_CheckPredicate, 26,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i64,
- OPC_RecordChild2,
+ 66,
+ OPC_CheckChild1Type, MVT::f64,
+ OPC_RecordChild2,
+ OPC_Scope, 38,
+ OPC_CheckPredicate, 18,
+ OPC_CheckPredicate, 22,
+ OPC_Scope, 15,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STFD), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 15,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STFDX), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 0,
+ 21,
OPC_RecordChild3,
- OPC_CheckComplexPat, /*CP*/4, /*#*/3,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::STBU8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::iPTR, 3, 1, 4, 2,
- 25,
OPC_CheckPredicate, 27,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i64,
- OPC_RecordChild2,
- OPC_RecordChild3,
+ OPC_CheckPredicate, 28,
OPC_CheckComplexPat, /*CP*/4, /*#*/3,
OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::STHU8), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STFDU), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::iPTR, 3, 1, 4, 2,
0,
- 27,
- OPC_CheckPredicate, 28,
- OPC_CheckPredicate, 29,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i64,
+ 22,
+ OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
- OPC_RecordChild3,
- OPC_CheckComplexPat, /*CP*/4, /*#*/3,
+ OPC_CheckPredicate, 18,
+ OPC_CheckPredicate, 22,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::STDU), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::iPTR, 3, 1, 4, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STVX), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 103|128,1,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_Scope, 26|128,1,
+ OPC_CheckPredicate, 18,
+ OPC_Scope, 112,
+ OPC_CheckPredicate, 19,
+ OPC_Scope, 17,
+ OPC_CheckPredicate, 20,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STB8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 17,
+ OPC_CheckPredicate, 21,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STH8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 17,
+ OPC_CheckPredicate, 29,
+ OPC_CheckComplexPat, /*CP*/1, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STW8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 17,
+ OPC_CheckPredicate, 20,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STBX8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 17,
+ OPC_CheckPredicate, 21,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STHX8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 17,
+ OPC_CheckPredicate, 29,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STWX8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 0,
+ 36,
+ OPC_CheckPredicate, 22,
+ OPC_Scope, 15,
+ OPC_CheckComplexPat, /*CP*/3, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STD), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 15,
+ OPC_CheckComplexPat, /*CP*/2, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STDX), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 3, 1, 3, 4,
+ 0,
+ 0,
+ 69,
+ OPC_RecordChild3,
+ OPC_Scope, 44,
+ OPC_CheckPredicate, 23,
+ OPC_CheckPredicate, 24,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 25,
+ OPC_CheckComplexPat, /*CP*/4, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STBU8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::iPTR, 3, 1, 4, 2,
+ 18,
+ OPC_CheckPredicate, 26,
+ OPC_CheckComplexPat, /*CP*/4, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STHU8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::iPTR, 3, 1, 4, 2,
+ 0,
+ 20,
+ OPC_CheckPredicate, 27,
+ OPC_CheckPredicate, 28,
+ OPC_CheckComplexPat, /*CP*/4, /*#*/3,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::STDU), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::iPTR, 3, 1, 4, 2,
+ 0,
+ 0,
0,
26|128,1, ISD::FSUB,
OPC_Scope, 72,
@@ -2819,395 +2642,278 @@ SDNode *SelectCode(SDNode *N) {
0,
0,
0,
- 102, ISD::ATOMIC_LOAD_ADD,
- OPC_Scope, 24,
- OPC_CheckPredicate, 31,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_ADD_I8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 3, 3, 4, 2,
- 24,
- OPC_CheckPredicate, 32,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_ADD_I16), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 3, 3, 4, 2,
- 24,
- OPC_CheckPredicate, 33,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_ADD_I32), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 3, 3, 4, 2,
- 24,
+ 87, ISD::ATOMIC_LOAD_ADD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_SwitchType , 59, MVT::i32,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 31,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_ADD_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 18,
+ OPC_CheckPredicate, 32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_ADD_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 18,
+ OPC_CheckPredicate, 33,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_ADD_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 0,
+ 18, MVT::i64,
OPC_CheckPredicate, 34,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_ADD_I64), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 3, 3, 4, 2,
0,
- 102, ISD::ATOMIC_LOAD_SUB,
- OPC_Scope, 24,
- OPC_CheckPredicate, 35,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_SUB_I8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 3, 3, 4, 2,
- 24,
- OPC_CheckPredicate, 36,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_SUB_I16), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 3, 3, 4, 2,
- 24,
- OPC_CheckPredicate, 37,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_SUB_I32), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 3, 3, 4, 2,
- 24,
+ 87, ISD::ATOMIC_LOAD_SUB,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_SwitchType , 59, MVT::i32,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 35,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_SUB_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 18,
+ OPC_CheckPredicate, 36,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_SUB_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 18,
+ OPC_CheckPredicate, 37,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_SUB_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 0,
+ 18, MVT::i64,
OPC_CheckPredicate, 38,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_SUB_I64), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 3, 3, 4, 2,
0,
- 102, ISD::ATOMIC_LOAD_AND,
- OPC_Scope, 24,
- OPC_CheckPredicate, 39,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_AND_I8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 3, 3, 4, 2,
- 24,
- OPC_CheckPredicate, 40,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_AND_I16), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 3, 3, 4, 2,
- 24,
- OPC_CheckPredicate, 41,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_AND_I32), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 3, 3, 4, 2,
- 24,
+ 87, ISD::ATOMIC_LOAD_AND,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_SwitchType , 59, MVT::i32,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 39,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_AND_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 18,
+ OPC_CheckPredicate, 40,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_AND_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 18,
+ OPC_CheckPredicate, 41,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_AND_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 0,
+ 18, MVT::i64,
OPC_CheckPredicate, 42,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_AND_I64), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 3, 3, 4, 2,
0,
- 102, ISD::ATOMIC_LOAD_OR,
- OPC_Scope, 24,
- OPC_CheckPredicate, 43,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_OR_I8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 3, 3, 4, 2,
- 24,
- OPC_CheckPredicate, 44,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_OR_I16), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 3, 3, 4, 2,
- 24,
- OPC_CheckPredicate, 45,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_OR_I32), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 3, 3, 4, 2,
- 24,
+ 87, ISD::ATOMIC_LOAD_OR,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_SwitchType , 59, MVT::i32,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 43,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_OR_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 18,
+ OPC_CheckPredicate, 44,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_OR_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 18,
+ OPC_CheckPredicate, 45,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_OR_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 0,
+ 18, MVT::i64,
OPC_CheckPredicate, 46,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_OR_I64), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 3, 3, 4, 2,
0,
- 102, ISD::ATOMIC_LOAD_XOR,
- OPC_Scope, 24,
- OPC_CheckPredicate, 47,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_XOR_I8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 3, 3, 4, 2,
- 24,
- OPC_CheckPredicate, 48,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_XOR_I16), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 3, 3, 4, 2,
- 24,
- OPC_CheckPredicate, 49,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_XOR_I32), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 3, 3, 4, 2,
- 24,
+ 87, ISD::ATOMIC_LOAD_XOR,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_SwitchType , 59, MVT::i32,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 47,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_XOR_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 18,
+ OPC_CheckPredicate, 48,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_XOR_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 18,
+ OPC_CheckPredicate, 49,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_XOR_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 0,
+ 18, MVT::i64,
OPC_CheckPredicate, 50,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_XOR_I64), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 3, 3, 4, 2,
0,
- 102, ISD::ATOMIC_LOAD_NAND,
- OPC_Scope, 24,
- OPC_CheckPredicate, 51,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_NAND_I8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 3, 3, 4, 2,
- 24,
- OPC_CheckPredicate, 52,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_NAND_I16), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 3, 3, 4, 2,
- 24,
- OPC_CheckPredicate, 53,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_NAND_I32), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 3, 3, 4, 2,
- 24,
+ 87, ISD::ATOMIC_LOAD_NAND,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_SwitchType , 59, MVT::i32,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 51,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_NAND_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 18,
+ OPC_CheckPredicate, 52,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_NAND_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 18,
+ OPC_CheckPredicate, 53,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_NAND_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 0,
+ 18, MVT::i64,
OPC_CheckPredicate, 54,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_LOAD_NAND_I64), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 3, 3, 4, 2,
0,
- 110, ISD::ATOMIC_CMP_SWAP,
- OPC_Scope, 26,
- OPC_CheckPredicate, 55,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_RecordChild3,
- OPC_CheckType, MVT::i32,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_CMP_SWAP_I8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 4, 4, 5, 2, 3,
- 26,
- OPC_CheckPredicate, 56,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_RecordChild3,
- OPC_CheckType, MVT::i32,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_CMP_SWAP_I16), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 4, 4, 5, 2, 3,
- 26,
- OPC_CheckPredicate, 57,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_RecordChild3,
- OPC_CheckType, MVT::i32,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_CMP_SWAP_I32), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 4, 4, 5, 2, 3,
- 26,
+ 92, ISD::ATOMIC_CMP_SWAP,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_RecordChild3,
+ OPC_SwitchType , 62, MVT::i32,
+ OPC_Scope, 19,
+ OPC_CheckPredicate, 55,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_CMP_SWAP_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 4, 5, 2, 3,
+ 19,
+ OPC_CheckPredicate, 56,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_CMP_SWAP_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 4, 5, 2, 3,
+ 19,
+ OPC_CheckPredicate, 57,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_CMP_SWAP_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 4, 4, 5, 2, 3,
+ 0,
+ 19, MVT::i64,
OPC_CheckPredicate, 58,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_RecordChild3,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_CMP_SWAP_I64), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 4, 4, 5, 2, 3,
0,
- 102, ISD::ATOMIC_SWAP,
- OPC_Scope, 24,
- OPC_CheckPredicate, 59,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_SWAP_I8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 3, 3, 4, 2,
- 24,
- OPC_CheckPredicate, 60,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_SWAP_I16), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 3, 3, 4, 2,
- 24,
- OPC_CheckPredicate, 61,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_SWAP_I32), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 3, 3, 4, 2,
- 24,
+ 87, ISD::ATOMIC_SWAP,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_SwitchType , 59, MVT::i32,
+ OPC_Scope, 18,
+ OPC_CheckPredicate, 59,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_SWAP_I8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 18,
+ OPC_CheckPredicate, 60,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_SWAP_I16), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 18,
+ OPC_CheckPredicate, 61,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_SWAP_I32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 3, 3, 4, 2,
+ 0,
+ 18, MVT::i64,
OPC_CheckPredicate, 62,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::ATOMIC_SWAP_I64), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 3, 3, 4, 2,
0,
- 52, PPCISD::DYNALLOC,
+ 50, PPCISD::DYNALLOC,
OPC_RecordNode,
OPC_RecordChild1,
- OPC_Scope, 23,
+ OPC_SwitchType , 21, MVT::i32,
OPC_CheckChild1Type, MVT::i32,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::iPTR,
- OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/1, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::DYNALLOC), 0|OPFL_Chain,
1, MVT::i32, 3, 1, 3, 4,
- 23,
+ 21, MVT::i64,
OPC_CheckChild1Type, MVT::i64,
OPC_RecordChild2,
OPC_CheckChild2Type, MVT::iPTR,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/1, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::DYNALLOC8), 0|OPFL_Chain,
@@ -4524,187 +4230,120 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::i64, 2, 1, 0,
0,
0,
- 24|128,3, ISD::VECTOR_SHUFFLE,
- OPC_Scope, 96,
+ 50|128,2, ISD::VECTOR_SHUFFLE,
+ OPC_Scope, 72,
OPC_RecordNode,
- OPC_Scope, 22,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v16i8,
+ OPC_Scope, 14,
OPC_CheckPredicate, 68,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_CheckType, MVT::v16i8,
OPC_EmitNodeXForm, 5, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSPLTB), 0,
1, MVT::v16i8, 2, 2, 1,
- 22,
+ 14,
OPC_CheckPredicate, 69,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_CheckType, MVT::v16i8,
OPC_EmitNodeXForm, 6, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSPLTH), 0,
1, MVT::v16i8, 2, 2, 1,
- 22,
+ 14,
OPC_CheckPredicate, 70,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_CheckType, MVT::v16i8,
OPC_EmitNodeXForm, 7, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSPLTW), 0,
1, MVT::v16i8, 2, 2, 1,
- 23,
+ 15,
OPC_CheckPredicate, 71,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_CheckType, MVT::v16i8,
OPC_EmitNodeXForm, 8, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSLDOI), 0,
1, MVT::v16i8, 3, 1, 1, 2,
0,
- 19,
- OPC_CheckPredicate, 72,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_CheckType, MVT::v16i8,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::VPKUWUM), 0,
- 1, MVT::v16i8, 2, 0, 0,
- 19,
- OPC_CheckPredicate, 73,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_CheckType, MVT::v16i8,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::VPKUHUM), 0,
- 1, MVT::v16i8, 2, 0, 0,
- 19,
- OPC_CheckPredicate, 74,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_CheckType, MVT::v16i8,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGLB), 0,
- 1, MVT::v16i8, 2, 0, 0,
- 19,
- OPC_CheckPredicate, 75,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_CheckType, MVT::v16i8,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGLH), 0,
- 1, MVT::v16i8, 2, 0, 0,
- 19,
- OPC_CheckPredicate, 76,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_CheckType, MVT::v16i8,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGLW), 0,
- 1, MVT::v16i8, 2, 0, 0,
- 19,
- OPC_CheckPredicate, 77,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_CheckType, MVT::v16i8,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGHB), 0,
- 1, MVT::v16i8, 2, 0, 0,
- 19,
- OPC_CheckPredicate, 78,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_CheckType, MVT::v16i8,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGHH), 0,
- 1, MVT::v16i8, 2, 0, 0,
- 19,
- OPC_CheckPredicate, 79,
+ 106,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::UNDEF,
OPC_MoveParent,
OPC_CheckType, MVT::v16i8,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGHW), 0,
- 1, MVT::v16i8, 2, 0, 0,
+ OPC_Scope, 11,
+ OPC_CheckPredicate, 72,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VPKUWUM), 0,
+ 1, MVT::v16i8, 2, 0, 0,
+ 11,
+ OPC_CheckPredicate, 73,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VPKUHUM), 0,
+ 1, MVT::v16i8, 2, 0, 0,
+ 11,
+ OPC_CheckPredicate, 74,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGLB), 0,
+ 1, MVT::v16i8, 2, 0, 0,
+ 11,
+ OPC_CheckPredicate, 75,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGLH), 0,
+ 1, MVT::v16i8, 2, 0, 0,
+ 11,
+ OPC_CheckPredicate, 76,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGLW), 0,
+ 1, MVT::v16i8, 2, 0, 0,
+ 11,
+ OPC_CheckPredicate, 77,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGHB), 0,
+ 1, MVT::v16i8, 2, 0, 0,
+ 11,
+ OPC_CheckPredicate, 78,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGHH), 0,
+ 1, MVT::v16i8, 2, 0, 0,
+ 11,
+ OPC_CheckPredicate, 79,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGHW), 0,
+ 1, MVT::v16i8, 2, 0, 0,
+ 0,
20,
OPC_RecordNode,
- OPC_CheckPredicate, 80,
OPC_RecordChild0,
OPC_RecordChild1,
+ OPC_CheckPredicate, 80,
OPC_CheckType, MVT::v16i8,
OPC_EmitNodeXForm, 9, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSLDOI), 0,
1, MVT::v16i8, 3, 1, 2, 3,
- 15,
- OPC_CheckPredicate, 81,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v16i8,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGHB), 0,
- 1, MVT::v16i8, 2, 0, 1,
- 15,
- OPC_CheckPredicate, 82,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v16i8,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGHH), 0,
- 1, MVT::v16i8, 2, 0, 1,
- 15,
- OPC_CheckPredicate, 83,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v16i8,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGHW), 0,
- 1, MVT::v16i8, 2, 0, 1,
- 15,
- OPC_CheckPredicate, 84,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v16i8,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGLB), 0,
- 1, MVT::v16i8, 2, 0, 1,
- 15,
- OPC_CheckPredicate, 85,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v16i8,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGLH), 0,
- 1, MVT::v16i8, 2, 0, 1,
- 15,
- OPC_CheckPredicate, 86,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v16i8,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGLW), 0,
- 1, MVT::v16i8, 2, 0, 1,
- 15,
- OPC_CheckPredicate, 87,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v16i8,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::VPKUHUM), 0,
- 1, MVT::v16i8, 2, 0, 1,
- 15,
- OPC_CheckPredicate, 88,
+ 102,
OPC_RecordChild0,
OPC_RecordChild1,
OPC_CheckType, MVT::v16i8,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::VPKUWUM), 0,
- 1, MVT::v16i8, 2, 0, 1,
+ OPC_Scope, 11,
+ OPC_CheckPredicate, 81,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGHB), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 11,
+ OPC_CheckPredicate, 82,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGHH), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 11,
+ OPC_CheckPredicate, 83,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGHW), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 11,
+ OPC_CheckPredicate, 84,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGLB), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 11,
+ OPC_CheckPredicate, 85,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGLH), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 11,
+ OPC_CheckPredicate, 86,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VMRGLW), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 11,
+ OPC_CheckPredicate, 87,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VPKUHUM), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 11,
+ OPC_CheckPredicate, 88,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::VPKUWUM), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 0,
0,
17, ISD::CALLSEQ_START,
OPC_RecordNode,
@@ -5069,63 +4708,59 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckType, MVT::i64,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::LDtoc), 0,
1, MVT::i64, 2, 0, 1,
- 99, ISD::Constant,
+ 97, ISD::Constant,
OPC_RecordNode,
- OPC_Scope, 14,
- OPC_CheckPredicate, 0,
- OPC_CheckType, MVT::i32,
- OPC_EmitConvertToTarget, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::LI), 0,
- 1, MVT::i32, 1, 1,
- 17,
- OPC_CheckPredicate, 1,
- OPC_CheckType, MVT::i32,
- OPC_EmitConvertToTarget, 0,
- OPC_EmitNodeXForm, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::LIS), 0,
- 1, MVT::i32, 1, 2,
- 14,
- OPC_CheckPredicate, 0,
- OPC_CheckType, MVT::i64,
- OPC_EmitConvertToTarget, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::LI8), 0,
- 1, MVT::i64, 1, 1,
- 17,
- OPC_CheckPredicate, 1,
- OPC_CheckType, MVT::i64,
- OPC_EmitConvertToTarget, 0,
- OPC_EmitNodeXForm, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::LIS8), 0,
- 1, MVT::i64, 1, 2,
- 29,
- OPC_CheckType, MVT::i32,
- OPC_EmitConvertToTarget, 0,
- OPC_EmitNodeXForm, 0, 1,
- OPC_EmitNode, TARGET_OPCODE(PPC::LIS), 0,
- 1, MVT::i32, 1, 2,
- OPC_EmitConvertToTarget, 0,
- OPC_EmitNodeXForm, 1, 4,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::ORI), 0,
- 1, MVT::i32, 2, 3, 5,
+ OPC_SwitchType , 59, MVT::i32,
+ OPC_Scope, 12,
+ OPC_CheckPredicate, 0,
+ OPC_EmitConvertToTarget, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LI), 0,
+ 1, MVT::i32, 1, 1,
+ 15,
+ OPC_CheckPredicate, 1,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitNodeXForm, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LIS), 0,
+ 1, MVT::i32, 1, 2,
+ 27,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitNodeXForm, 0, 1,
+ OPC_EmitNode, TARGET_OPCODE(PPC::LIS), 0,
+ 1, MVT::i32, 1, 2,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitNodeXForm, 1, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::ORI), 0,
+ 1, MVT::i32, 2, 3, 5,
+ 0,
+ 31, MVT::i64,
+ OPC_Scope, 12,
+ OPC_CheckPredicate, 0,
+ OPC_EmitConvertToTarget, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LI8), 0,
+ 1, MVT::i64, 1, 1,
+ 15,
+ OPC_CheckPredicate, 1,
+ OPC_EmitConvertToTarget, 0,
+ OPC_EmitNodeXForm, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::LIS8), 0,
+ 1, MVT::i64, 1, 2,
+ 0,
0,
- 66, ISD::BUILD_VECTOR,
- OPC_Scope, 51,
+ 63, ISD::BUILD_VECTOR,
+ OPC_Scope, 48,
OPC_RecordNode,
- OPC_Scope, 15,
+ OPC_SwitchType , 13, MVT::v16i8,
OPC_CheckPredicate, 89,
- OPC_CheckType, MVT::v16i8,
OPC_EmitNodeXForm, 14, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSPLTISB), 0,
1, MVT::v16i8, 1, 1,
- 15,
+ 13, MVT::v8i16,
OPC_CheckPredicate, 90,
- OPC_CheckType, MVT::v8i16,
OPC_EmitNodeXForm, 15, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSPLTISH), 0,
1, MVT::v8i16, 1, 1,
- 15,
+ 13, MVT::v4i32,
OPC_CheckPredicate, 91,
- OPC_CheckType, MVT::v4i32,
OPC_EmitNodeXForm, 16, 0,
OPC_MorphNodeTo, TARGET_OPCODE(PPC::VSPLTISW), 0,
1, MVT::v4i32, 1, 1,
@@ -5279,33 +4914,29 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(PPC::CNTLZD), 0,
1, MVT::i64, 1, 0,
0,
- 75, ISD::SIGN_EXTEND_INREG,
+ 71, ISD::SIGN_EXTEND_INREG,
OPC_RecordChild0,
OPC_MoveChild, 1,
- OPC_Scope, 13,
+ OPC_Scope, 25,
OPC_CheckValueType, MVT::i8,
OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::EXTSB), 0,
- 1, MVT::i32, 1, 0,
- 13,
- OPC_CheckValueType, MVT::i16,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::EXTSH), 0,
- 1, MVT::i32, 1, 0,
- 13,
- OPC_CheckValueType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::EXTSB8), 0,
- 1, MVT::i64, 1, 0,
- 13,
+ OPC_SwitchType , 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::EXTSB), 0,
+ 1, MVT::i32, 1, 0,
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::EXTSB8), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
+ 25,
OPC_CheckValueType, MVT::i16,
OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MorphNodeTo, TARGET_OPCODE(PPC::EXTSH8), 0,
- 1, MVT::i64, 1, 0,
+ OPC_SwitchType , 8, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::EXTSH), 0,
+ 1, MVT::i32, 1, 0,
+ 8, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(PPC::EXTSH8), 0,
+ 1, MVT::i64, 1, 0,
+ 0,
13,
OPC_CheckValueType, MVT::i32,
OPC_MoveParent,
@@ -5533,7 +5164,7 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::i64, 3, 1, 2, 3,
0,
0
- }; // Total Array size is 11495 bytes
+ }; // Total Array size is 11066 bytes
#undef TARGET_OPCODE
return SelectCodeCommon(N, MatcherTable,sizeof(MatcherTable));
@@ -5701,50 +5332,50 @@ bool CheckNodePredicate(SDNode *Node, unsigned PredNo) const {
return !cast<StoreSDNode>(N)->isTruncatingStore();
}
- case 23: { // Predicate_truncstorei32
- SDNode *N = Node;
-
- return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
-
- }
- case 24: { // Predicate_itruncstore
+ case 23: { // Predicate_itruncstore
SDNode *N = Node;
return cast<StoreSDNode>(N)->isTruncatingStore();
}
- case 25: { // Predicate_pre_truncst
+ case 24: { // Predicate_pre_truncst
SDNode *N = Node;
ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
}
- case 26: { // Predicate_pre_truncsti8
+ case 25: { // Predicate_pre_truncsti8
SDNode *N = Node;
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
}
- case 27: { // Predicate_pre_truncsti16
+ case 26: { // Predicate_pre_truncsti16
SDNode *N = Node;
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
}
- case 28: { // Predicate_istore
+ case 27: { // Predicate_istore
SDNode *N = Node;
return !cast<StoreSDNode>(N)->isTruncatingStore();
}
- case 29: { // Predicate_pre_store
+ case 28: { // Predicate_pre_store
SDNode *N = Node;
ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
}
+ case 29: { // Predicate_truncstorei32
+ SDNode *N = Node;
+
+ return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
+
+ }
case 30: { // Predicate_V_immneg0
SDNode *N = Node;
diff --git a/libclamav/c++/X86GenAsmWriter.inc b/libclamav/c++/X86GenAsmWriter.inc
index 9e228ea..2382a9e 100644
--- a/libclamav/c++/X86GenAsmWriter.inc
+++ b/libclamav/c++/X86GenAsmWriter.inc
@@ -1091,22 +1091,23 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
205656412U, // MAXSSrr
205656412U, // MAXSSrr_Int
4451U, // MFENCE
- 536875370U, // MINPDrm
- 536875370U, // MINPDrm_Int
- 205656426U, // MINPDrr
- 205656426U, // MINPDrr_Int
- 536875377U, // MINPSrm
- 536875377U, // MINPSrm_Int
- 205656433U, // MINPSrr
- 205656433U, // MINPSrr_Int
- 603984248U, // MINSDrm
- 603984248U, // MINSDrm_Int
- 205656440U, // MINSDrr
- 205656440U, // MINSDrr_Int
- 671093119U, // MINSSrm
- 671093119U, // MINSSrm_Int
- 205656447U, // MINSSrr
- 205656447U, // MINSSrr_Int
+ 4458U, // MINGW_ALLOCA
+ 536875397U, // MINPDrm
+ 536875397U, // MINPDrm_Int
+ 205656453U, // MINPDrr
+ 205656453U, // MINPDrr_Int
+ 536875404U, // MINPSrm
+ 536875404U, // MINPSrm_Int
+ 205656460U, // MINPSrr
+ 205656460U, // MINPSrr_Int
+ 603984275U, // MINSDrm
+ 603984275U, // MINSDrm_Int
+ 205656467U, // MINSDrr
+ 205656467U, // MINSDrr_Int
+ 671093146U, // MINSSrm
+ 671093146U, // MINSSrm_Int
+ 205656474U, // MINSSrr
+ 205656474U, // MINSSrr_Int
1946160637U, // MMX_CVTPD2PIrm
1279397373U, // MMX_CVTPD2PIrr
1409289735U, // MMX_CVTPI2PDrm
@@ -1119,335 +1120,335 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
1279397444U, // MMX_CVTTPD2PIrr
2013269583U, // MMX_CVTTPS2PIrm
1279397455U, // MMX_CVTTPS2PIrr
- 4486U, // MMX_EMMS
- 4491U, // MMX_FEMMS
- 1279398289U, // MMX_MASKMOVQ
- 1279398289U, // MMX_MASKMOVQ64
- 1279398299U, // MMX_MOVD64from64rr
- 1279398299U, // MMX_MOVD64grr
- 136581531U, // MMX_MOVD64mr
- 1342181787U, // MMX_MOVD64rm
- 1279398299U, // MMX_MOVD64rr
- 1279398299U, // MMX_MOVD64rrv164
- 1279398299U, // MMX_MOVD64to64rr
- 1279398305U, // MMX_MOVDQ2Qrr
- 136712618U, // MMX_MOVNTQmr
- 1279398322U, // MMX_MOVQ2DQrr
- 1279398322U, // MMX_MOVQ2FR64rr
- 136712635U, // MMX_MOVQ64gmr
- 136712635U, // MMX_MOVQ64mr
- 1409290683U, // MMX_MOVQ64rm
- 1279398331U, // MMX_MOVQ64rr
- 1342181787U, // MMX_MOVZDI2PDIrm
- 1279398299U, // MMX_MOVZDI2PDIrr
- 406983105U, // MMX_PACKSSDWrm
- 205656513U, // MMX_PACKSSDWrr
- 406983115U, // MMX_PACKSSWBrm
- 205656523U, // MMX_PACKSSWBrr
- 406983125U, // MMX_PACKUSWBrm
- 205656533U, // MMX_PACKUSWBrr
- 406983135U, // MMX_PADDBrm
- 205656543U, // MMX_PADDBrr
- 406983142U, // MMX_PADDDrm
- 205656550U, // MMX_PADDDrr
- 406983149U, // MMX_PADDQrm
- 205656557U, // MMX_PADDQrr
- 406983156U, // MMX_PADDSBrm
- 205656564U, // MMX_PADDSBrr
- 406983164U, // MMX_PADDSWrm
- 205656572U, // MMX_PADDSWrr
- 406983172U, // MMX_PADDUSBrm
- 205656580U, // MMX_PADDUSBrr
- 406983181U, // MMX_PADDUSWrm
- 205656589U, // MMX_PADDUSWrr
- 406983190U, // MMX_PADDWrm
- 205656598U, // MMX_PADDWrr
- 406983197U, // MMX_PANDNrm
- 205656605U, // MMX_PANDNrr
- 406983204U, // MMX_PANDrm
- 205656612U, // MMX_PANDrr
- 406983210U, // MMX_PAVGBrm
- 205656618U, // MMX_PAVGBrr
- 406983217U, // MMX_PAVGWrm
- 205656625U, // MMX_PAVGWrr
- 406983224U, // MMX_PCMPEQBrm
- 205656632U, // MMX_PCMPEQBrr
- 406983233U, // MMX_PCMPEQDrm
- 205656641U, // MMX_PCMPEQDrr
- 406983242U, // MMX_PCMPEQWrm
- 205656650U, // MMX_PCMPEQWrr
- 406983251U, // MMX_PCMPGTBrm
- 205656659U, // MMX_PCMPGTBrr
- 406983260U, // MMX_PCMPGTDrm
- 205656668U, // MMX_PCMPGTDrr
- 406983269U, // MMX_PCMPGTWrm
- 205656677U, // MMX_PCMPGTWrr
- 230036078U, // MMX_PEXTRWri
- 1050022518U, // MMX_PINSRWrmi
- 1073746550U, // MMX_PINSRWrri
- 406983294U, // MMX_PMADDWDrm
- 205656702U, // MMX_PMADDWDrr
- 406983303U, // MMX_PMAXSWrm
- 205656711U, // MMX_PMAXSWrr
- 406983311U, // MMX_PMAXUBrm
- 205656719U, // MMX_PMAXUBrr
- 406983319U, // MMX_PMINSWrm
- 205656727U, // MMX_PMINSWrr
- 406983327U, // MMX_PMINUBrm
- 205656735U, // MMX_PMINUBrr
- 1279398567U, // MMX_PMOVMSKBrr
- 406983345U, // MMX_PMULHUWrm
- 205656753U, // MMX_PMULHUWrr
- 406983354U, // MMX_PMULHWrm
- 205656762U, // MMX_PMULHWrr
- 406983362U, // MMX_PMULLWrm
- 205656770U, // MMX_PMULLWrr
- 406983370U, // MMX_PMULUDQrm
- 205656778U, // MMX_PMULUDQrr
- 406983379U, // MMX_PORrm
- 205656787U, // MMX_PORrr
- 406983384U, // MMX_PSADBWrm
- 205656792U, // MMX_PSADBWrr
- 2183140064U, // MMX_PSHUFWmi
- 230036192U, // MMX_PSHUFWri
- 205656808U, // MMX_PSLLDri
- 406983400U, // MMX_PSLLDrm
- 205656808U, // MMX_PSLLDrr
- 205656815U, // MMX_PSLLQri
- 406983407U, // MMX_PSLLQrm
- 205656815U, // MMX_PSLLQrr
- 205656822U, // MMX_PSLLWri
- 406983414U, // MMX_PSLLWrm
- 205656822U, // MMX_PSLLWrr
- 205656829U, // MMX_PSRADri
- 406983421U, // MMX_PSRADrm
- 205656829U, // MMX_PSRADrr
- 205656836U, // MMX_PSRAWri
- 406983428U, // MMX_PSRAWrm
- 205656836U, // MMX_PSRAWrr
- 205656843U, // MMX_PSRLDri
- 406983435U, // MMX_PSRLDrm
- 205656843U, // MMX_PSRLDrr
- 205656850U, // MMX_PSRLQri
- 406983442U, // MMX_PSRLQrm
- 205656850U, // MMX_PSRLQrr
- 205656857U, // MMX_PSRLWri
- 406983449U, // MMX_PSRLWrm
- 205656857U, // MMX_PSRLWrr
- 406983456U, // MMX_PSUBBrm
- 205656864U, // MMX_PSUBBrr
- 406983463U, // MMX_PSUBDrm
- 205656871U, // MMX_PSUBDrr
- 406983470U, // MMX_PSUBQrm
- 205656878U, // MMX_PSUBQrr
- 406983477U, // MMX_PSUBSBrm
- 205656885U, // MMX_PSUBSBrr
- 406983485U, // MMX_PSUBSWrm
- 205656893U, // MMX_PSUBSWrr
- 406983493U, // MMX_PSUBUSBrm
- 205656901U, // MMX_PSUBUSBrr
- 406983502U, // MMX_PSUBUSWrm
- 205656910U, // MMX_PSUBUSWrr
- 406983511U, // MMX_PSUBWrm
- 205656919U, // MMX_PSUBWrr
- 406983518U, // MMX_PUNPCKHBWrm
- 205656926U, // MMX_PUNPCKHBWrr
- 406983529U, // MMX_PUNPCKHDQrm
- 205656937U, // MMX_PUNPCKHDQrr
- 406983540U, // MMX_PUNPCKHWDrm
- 205656948U, // MMX_PUNPCKHWDrr
- 406983551U, // MMX_PUNPCKLBWrm
- 205656959U, // MMX_PUNPCKLBWrr
- 406983562U, // MMX_PUNPCKLDQrm
- 205656970U, // MMX_PUNPCKLDQrr
- 406983573U, // MMX_PUNPCKLWDrm
- 205656981U, // MMX_PUNPCKLWDrr
- 406983584U, // MMX_PXORrm
- 205656992U, // MMX_PXORrr
+ 4513U, // MMX_EMMS
+ 4518U, // MMX_FEMMS
+ 1279398316U, // MMX_MASKMOVQ
+ 1279398316U, // MMX_MASKMOVQ64
+ 1279398326U, // MMX_MOVD64from64rr
+ 1279398326U, // MMX_MOVD64grr
+ 136581558U, // MMX_MOVD64mr
+ 1342181814U, // MMX_MOVD64rm
+ 1279398326U, // MMX_MOVD64rr
+ 1279398326U, // MMX_MOVD64rrv164
+ 1279398326U, // MMX_MOVD64to64rr
+ 1279398332U, // MMX_MOVDQ2Qrr
+ 136712645U, // MMX_MOVNTQmr
+ 1279398349U, // MMX_MOVQ2DQrr
+ 1279398349U, // MMX_MOVQ2FR64rr
+ 136712662U, // MMX_MOVQ64gmr
+ 136712662U, // MMX_MOVQ64mr
+ 1409290710U, // MMX_MOVQ64rm
+ 1279398358U, // MMX_MOVQ64rr
+ 1342181814U, // MMX_MOVZDI2PDIrm
+ 1279398326U, // MMX_MOVZDI2PDIrr
+ 406983132U, // MMX_PACKSSDWrm
+ 205656540U, // MMX_PACKSSDWrr
+ 406983142U, // MMX_PACKSSWBrm
+ 205656550U, // MMX_PACKSSWBrr
+ 406983152U, // MMX_PACKUSWBrm
+ 205656560U, // MMX_PACKUSWBrr
+ 406983162U, // MMX_PADDBrm
+ 205656570U, // MMX_PADDBrr
+ 406983169U, // MMX_PADDDrm
+ 205656577U, // MMX_PADDDrr
+ 406983176U, // MMX_PADDQrm
+ 205656584U, // MMX_PADDQrr
+ 406983183U, // MMX_PADDSBrm
+ 205656591U, // MMX_PADDSBrr
+ 406983191U, // MMX_PADDSWrm
+ 205656599U, // MMX_PADDSWrr
+ 406983199U, // MMX_PADDUSBrm
+ 205656607U, // MMX_PADDUSBrr
+ 406983208U, // MMX_PADDUSWrm
+ 205656616U, // MMX_PADDUSWrr
+ 406983217U, // MMX_PADDWrm
+ 205656625U, // MMX_PADDWrr
+ 406983224U, // MMX_PANDNrm
+ 205656632U, // MMX_PANDNrr
+ 406983231U, // MMX_PANDrm
+ 205656639U, // MMX_PANDrr
+ 406983237U, // MMX_PAVGBrm
+ 205656645U, // MMX_PAVGBrr
+ 406983244U, // MMX_PAVGWrm
+ 205656652U, // MMX_PAVGWrr
+ 406983251U, // MMX_PCMPEQBrm
+ 205656659U, // MMX_PCMPEQBrr
+ 406983260U, // MMX_PCMPEQDrm
+ 205656668U, // MMX_PCMPEQDrr
+ 406983269U, // MMX_PCMPEQWrm
+ 205656677U, // MMX_PCMPEQWrr
+ 406983278U, // MMX_PCMPGTBrm
+ 205656686U, // MMX_PCMPGTBrr
+ 406983287U, // MMX_PCMPGTDrm
+ 205656695U, // MMX_PCMPGTDrr
+ 406983296U, // MMX_PCMPGTWrm
+ 205656704U, // MMX_PCMPGTWrr
+ 230036105U, // MMX_PEXTRWri
+ 1050022545U, // MMX_PINSRWrmi
+ 1073746577U, // MMX_PINSRWrri
+ 406983321U, // MMX_PMADDWDrm
+ 205656729U, // MMX_PMADDWDrr
+ 406983330U, // MMX_PMAXSWrm
+ 205656738U, // MMX_PMAXSWrr
+ 406983338U, // MMX_PMAXUBrm
+ 205656746U, // MMX_PMAXUBrr
+ 406983346U, // MMX_PMINSWrm
+ 205656754U, // MMX_PMINSWrr
+ 406983354U, // MMX_PMINUBrm
+ 205656762U, // MMX_PMINUBrr
+ 1279398594U, // MMX_PMOVMSKBrr
+ 406983372U, // MMX_PMULHUWrm
+ 205656780U, // MMX_PMULHUWrr
+ 406983381U, // MMX_PMULHWrm
+ 205656789U, // MMX_PMULHWrr
+ 406983389U, // MMX_PMULLWrm
+ 205656797U, // MMX_PMULLWrr
+ 406983397U, // MMX_PMULUDQrm
+ 205656805U, // MMX_PMULUDQrr
+ 406983406U, // MMX_PORrm
+ 205656814U, // MMX_PORrr
+ 406983411U, // MMX_PSADBWrm
+ 205656819U, // MMX_PSADBWrr
+ 2183140091U, // MMX_PSHUFWmi
+ 230036219U, // MMX_PSHUFWri
+ 205656835U, // MMX_PSLLDri
+ 406983427U, // MMX_PSLLDrm
+ 205656835U, // MMX_PSLLDrr
+ 205656842U, // MMX_PSLLQri
+ 406983434U, // MMX_PSLLQrm
+ 205656842U, // MMX_PSLLQrr
+ 205656849U, // MMX_PSLLWri
+ 406983441U, // MMX_PSLLWrm
+ 205656849U, // MMX_PSLLWrr
+ 205656856U, // MMX_PSRADri
+ 406983448U, // MMX_PSRADrm
+ 205656856U, // MMX_PSRADrr
+ 205656863U, // MMX_PSRAWri
+ 406983455U, // MMX_PSRAWrm
+ 205656863U, // MMX_PSRAWrr
+ 205656870U, // MMX_PSRLDri
+ 406983462U, // MMX_PSRLDrm
+ 205656870U, // MMX_PSRLDrr
+ 205656877U, // MMX_PSRLQri
+ 406983469U, // MMX_PSRLQrm
+ 205656877U, // MMX_PSRLQrr
+ 205656884U, // MMX_PSRLWri
+ 406983476U, // MMX_PSRLWrm
+ 205656884U, // MMX_PSRLWrr
+ 406983483U, // MMX_PSUBBrm
+ 205656891U, // MMX_PSUBBrr
+ 406983490U, // MMX_PSUBDrm
+ 205656898U, // MMX_PSUBDrr
+ 406983497U, // MMX_PSUBQrm
+ 205656905U, // MMX_PSUBQrr
+ 406983504U, // MMX_PSUBSBrm
+ 205656912U, // MMX_PSUBSBrr
+ 406983512U, // MMX_PSUBSWrm
+ 205656920U, // MMX_PSUBSWrr
+ 406983520U, // MMX_PSUBUSBrm
+ 205656928U, // MMX_PSUBUSBrr
+ 406983529U, // MMX_PSUBUSWrm
+ 205656937U, // MMX_PSUBUSWrr
+ 406983538U, // MMX_PSUBWrm
+ 205656946U, // MMX_PSUBWrr
+ 406983545U, // MMX_PUNPCKHBWrm
+ 205656953U, // MMX_PUNPCKHBWrr
+ 406983556U, // MMX_PUNPCKHDQrm
+ 205656964U, // MMX_PUNPCKHDQrr
+ 406983567U, // MMX_PUNPCKHWDrm
+ 205656975U, // MMX_PUNPCKHWDrr
+ 406983578U, // MMX_PUNPCKLBWrm
+ 205656986U, // MMX_PUNPCKLBWrr
+ 406983589U, // MMX_PUNPCKLDQrm
+ 205656997U, // MMX_PUNPCKLDQrr
+ 406983600U, // MMX_PUNPCKLWDrm
+ 205657008U, // MMX_PUNPCKLWDrr
+ 406983611U, // MMX_PXORrm
+ 205657019U, // MMX_PXORrr
0U, // MMX_V_SET0
0U, // MMX_V_SETALLONES
- 5030U, // MONITOR
- 1556091822U, // MOV16ao16
- 136319929U, // MOV16mi
- 136319929U, // MOV16mr
- 136319929U, // MOV16ms
- 1543508921U, // MOV16o16a
+ 5057U, // MONITOR
+ 1556091849U, // MOV16ao16
+ 136319956U, // MOV16mi
+ 136319956U, // MOV16mr
+ 136319956U, // MOV16ms
+ 1543508948U, // MOV16o16a
0U, // MOV16r0
- 1279398841U, // MOV16ri
- 1207964601U, // MOV16rm
- 1279398841U, // MOV16rr
- 1279398841U, // MOV16rr_REV
- 1279398841U, // MOV16rs
- 1207964601U, // MOV16sm
- 1279398841U, // MOV16sr
- 1556091839U, // MOV32ao32
- 1279398331U, // MOV32cr
- 1279398859U, // MOV32dr
- 136582091U, // MOV32mi
- 136582091U, // MOV32mr
- 1549800395U, // MOV32o32a
+ 1279398868U, // MOV16ri
+ 1207964628U, // MOV16rm
+ 1279398868U, // MOV16rr
+ 1279398868U, // MOV16rr_REV
+ 1279398868U, // MOV16rs
+ 1207964628U, // MOV16sm
+ 1279398868U, // MOV16sr
+ 1556091866U, // MOV32ao32
+ 1279398358U, // MOV32cr
+ 1279398886U, // MOV32dr
+ 136582118U, // MOV32mi
+ 136582118U, // MOV32mr
+ 1549800422U, // MOV32o32a
0U, // MOV32r0
- 1279398331U, // MOV32rc
- 1279398859U, // MOV32rd
- 1279398859U, // MOV32ri
- 1342182347U, // MOV32rm
- 1279398859U, // MOV32rr
- 1279398859U, // MOV32rr_REV
- 1409291217U, // MOV64FSrm
- 1409291227U, // MOV64GSrm
- 1556091877U, // MOV64ao64
- 1556091877U, // MOV64ao8
- 1279398331U, // MOV64cr
- 1279398331U, // MOV64dr
- 136712635U, // MOV64mi32
- 136712635U, // MOV64mr
- 136712635U, // MOV64ms
- 1551897019U, // MOV64o64a
- 1551897019U, // MOV64o8a
+ 1279398358U, // MOV32rc
+ 1279398886U, // MOV32rd
+ 1279398886U, // MOV32ri
+ 1342182374U, // MOV32rm
+ 1279398886U, // MOV32rr
+ 1279398886U, // MOV32rr_REV
+ 1409291244U, // MOV64FSrm
+ 1409291254U, // MOV64GSrm
+ 1556091904U, // MOV64ao64
+ 1556091904U, // MOV64ao8
+ 1279398358U, // MOV64cr
+ 1279398358U, // MOV64dr
+ 136712662U, // MOV64mi32
+ 136712662U, // MOV64mr
+ 136712662U, // MOV64ms
+ 1551897046U, // MOV64o64a
+ 1551897046U, // MOV64o8a
0U, // MOV64r0
- 1279398331U, // MOV64rc
- 1279398331U, // MOV64rd
- 1279398897U, // MOV64ri
- 1279398331U, // MOV64ri32
+ 1279398358U, // MOV64rc
+ 1279398358U, // MOV64rd
+ 1279398924U, // MOV64ri
+ 1279398358U, // MOV64ri32
0U, // MOV64ri64i32
- 1409290683U, // MOV64rm
- 1279398331U, // MOV64rr
- 1279398331U, // MOV64rr_REV
- 1279398331U, // MOV64rs
- 1409290683U, // MOV64sm
- 1279398331U, // MOV64sr
- 1279398299U, // MOV64toPQIrr
- 1409290683U, // MOV64toSDrm
- 1279398299U, // MOV64toSDrr
- 1556091898U, // MOV8ao8
- 136844293U, // MOV8mi
- 136844293U, // MOV8mr
- 136877061U, // MOV8mr_NOREX
- 1553994757U, // MOV8o8a
+ 1409290710U, // MOV64rm
+ 1279398358U, // MOV64rr
+ 1279398358U, // MOV64rr_REV
+ 1279398358U, // MOV64rs
+ 1409290710U, // MOV64sm
+ 1279398358U, // MOV64sr
+ 1279398326U, // MOV64toPQIrr
+ 1409290710U, // MOV64toSDrm
+ 1279398326U, // MOV64toSDrr
+ 1556091925U, // MOV8ao8
+ 136844320U, // MOV8mi
+ 136844320U, // MOV8mr
+ 136877088U, // MOV8mr_NOREX
+ 1553994784U, // MOV8o8a
0U, // MOV8r0
- 1279398917U, // MOV8ri
- 1690309637U, // MOV8rm
- 1728058373U, // MOV8rm_NOREX
- 1279398917U, // MOV8rr
- 1280840709U, // MOV8rr_NOREX
- 1279398917U, // MOV8rr_REV
+ 1279398944U, // MOV8ri
+ 1690309664U, // MOV8rm
+ 1728058400U, // MOV8rm_NOREX
+ 1279398944U, // MOV8rr
+ 1280840736U, // MOV8rr_NOREX
+ 1279398944U, // MOV8rr_REV
138022000U, // MOVAPDmr
1946160240U, // MOVAPDrm
1279396976U, // MOVAPDrr
138022008U, // MOVAPSmr
1946160248U, // MOVAPSrm
1279396984U, // MOVAPSrr
- 2013271051U, // MOVDDUPrm
- 1279398923U, // MOVDDUPrr
- 1342181787U, // MOVDI2PDIrm
- 1279398299U, // MOVDI2PDIrr
- 1342181787U, // MOVDI2SSrm
- 1279398299U, // MOVDI2SSrr
- 138155028U, // MOVDQAmr
- 2281706516U, // MOVDQArm
- 1279398932U, // MOVDQArr
- 138155036U, // MOVDQUmr
- 138155036U, // MOVDQUmr_Int
- 2281706524U, // MOVDQUrm
- 2281706524U, // MOVDQUrm_Int
- 205657124U, // MOVHLPSrr
- 138286125U, // MOVHPDmr
- 603984941U, // MOVHPDrm
- 138286133U, // MOVHPSmr
- 603984949U, // MOVHPSrm
- 205657149U, // MOVLHPSrr
- 138286150U, // MOVLPDmr
- 603984966U, // MOVLPDrm
- 138286158U, // MOVLPSmr
- 603984974U, // MOVLPSrm
- 136712635U, // MOVLQ128mr
- 1279398998U, // MOVMSKPDrr
- 1279399008U, // MOVMSKPSrr
- 2281706602U, // MOVNTDQArm
- 138024052U, // MOVNTDQ_64mr
- 138024052U, // MOVNTDQmr
- 138024052U, // MOVNTDQmr_Int
- 136713341U, // MOVNTI_64mr
- 136582269U, // MOVNTImr
- 136582269U, // MOVNTImr_Int
- 138024069U, // MOVNTPDmr
- 138155141U, // MOVNTPDmr_Int
- 138024078U, // MOVNTPSmr
- 138155150U, // MOVNTPSmr_Int
+ 2013271078U, // MOVDDUPrm
+ 1279398950U, // MOVDDUPrr
+ 1342181814U, // MOVDI2PDIrm
+ 1279398326U, // MOVDI2PDIrr
+ 1342181814U, // MOVDI2SSrm
+ 1279398326U, // MOVDI2SSrr
+ 138155055U, // MOVDQAmr
+ 2281706543U, // MOVDQArm
+ 1279398959U, // MOVDQArr
+ 138155063U, // MOVDQUmr
+ 138155063U, // MOVDQUmr_Int
+ 2281706551U, // MOVDQUrm
+ 2281706551U, // MOVDQUrm_Int
+ 205657151U, // MOVHLPSrr
+ 138286152U, // MOVHPDmr
+ 603984968U, // MOVHPDrm
+ 138286160U, // MOVHPSmr
+ 603984976U, // MOVHPSrm
+ 205657176U, // MOVLHPSrr
+ 138286177U, // MOVLPDmr
+ 603984993U, // MOVLPDrm
+ 138286185U, // MOVLPSmr
+ 603985001U, // MOVLPSrm
+ 136712662U, // MOVLQ128mr
+ 1279399025U, // MOVMSKPDrr
+ 1279399035U, // MOVMSKPSrr
+ 2281706629U, // MOVNTDQArm
+ 138024079U, // MOVNTDQ_64mr
+ 138024079U, // MOVNTDQmr
+ 138024079U, // MOVNTDQmr_Int
+ 136713368U, // MOVNTI_64mr
+ 136582296U, // MOVNTImr
+ 136582296U, // MOVNTImr_Int
+ 138024096U, // MOVNTPDmr
+ 138155168U, // MOVNTPDmr_Int
+ 138024105U, // MOVNTPSmr
+ 138155177U, // MOVNTPSmr_Int
0U, // MOVPC32r
- 136581531U, // MOVPDI2DImr
- 1279398299U, // MOVPDI2DIrr
- 136712635U, // MOVPQI2QImr
- 1279398299U, // MOVPQIto64rr
- 1409290683U, // MOVQI2PQIrm
- 1279398331U, // MOVQxrxr
- 5271U, // MOVSB
- 5277U, // MOVSD
- 138286243U, // MOVSDmr
- 2013271203U, // MOVSDrm
- 205657251U, // MOVSDrr
- 136712635U, // MOVSDto64mr
- 1279398299U, // MOVSDto64rr
- 1946162346U, // MOVSHDUPrm
- 1279399082U, // MOVSHDUPrr
- 1946162356U, // MOVSLDUPrm
- 1279399092U, // MOVSLDUPrr
- 136581531U, // MOVSS2DImr
- 1279398299U, // MOVSS2DIrr
- 137630910U, // MOVSSmr
- 2080380094U, // MOVSSrm
- 205657278U, // MOVSSrr
- 5317U, // MOVSW
+ 136581558U, // MOVPDI2DImr
+ 1279398326U, // MOVPDI2DIrr
+ 136712662U, // MOVPQI2QImr
+ 1279398326U, // MOVPQIto64rr
+ 1409290710U, // MOVQI2PQIrm
+ 1279398358U, // MOVQxrxr
+ 5298U, // MOVSB
+ 5304U, // MOVSD
+ 138286270U, // MOVSDmr
+ 2013271230U, // MOVSDrm
+ 205657278U, // MOVSDrr
+ 136712662U, // MOVSDto64mr
+ 1279398326U, // MOVSDto64rr
+ 1946162373U, // MOVSHDUPrm
+ 1279399109U, // MOVSHDUPrr
+ 1946162383U, // MOVSLDUPrm
+ 1279399119U, // MOVSLDUPrr
+ 136581558U, // MOVSS2DImr
+ 1279398326U, // MOVSS2DIrr
+ 137630937U, // MOVSSmr
+ 2080380121U, // MOVSSrm
+ 205657305U, // MOVSSrr
+ 5344U, // MOVSW
0U, // MOVSX16rm8
- 1690309835U, // MOVSX16rm8W
+ 1690309862U, // MOVSX16rm8W
0U, // MOVSX16rr8
- 1279399115U, // MOVSX16rr8W
- 1207964883U, // MOVSX32rm16
- 1690309851U, // MOVSX32rm8
- 1279399123U, // MOVSX32rr16
- 1279399131U, // MOVSX32rr8
- 1207964899U, // MOVSX64rm16
- 1342182635U, // MOVSX64rm32
- 1690309875U, // MOVSX64rm8
- 1279399139U, // MOVSX64rr16
- 1279399147U, // MOVSX64rr32
- 1279399155U, // MOVSX64rr8
- 138024187U, // MOVUPDmr
- 138024187U, // MOVUPDmr_Int
- 1946162427U, // MOVUPDrm
- 1946162427U, // MOVUPDrm_Int
- 1279399163U, // MOVUPDrr
- 138024195U, // MOVUPSmr
- 138024195U, // MOVUPSmr_Int
- 1946162435U, // MOVUPSrm
- 1946162435U, // MOVUPSrm_Int
- 1279399171U, // MOVUPSrr
- 1342181787U, // MOVZDI2PDIrm
- 1279398299U, // MOVZDI2PDIrr
- 2281705915U, // MOVZPQILo2PQIrm
- 1279398331U, // MOVZPQILo2PQIrr
- 1409290683U, // MOVZQI2PQIrm
- 1279398299U, // MOVZQI2PQIrr
+ 1279399142U, // MOVSX16rr8W
+ 1207964910U, // MOVSX32rm16
+ 1690309878U, // MOVSX32rm8
+ 1279399150U, // MOVSX32rr16
+ 1279399158U, // MOVSX32rr8
+ 1207964926U, // MOVSX64rm16
+ 1342182662U, // MOVSX64rm32
+ 1690309902U, // MOVSX64rm8
+ 1279399166U, // MOVSX64rr16
+ 1279399174U, // MOVSX64rr32
+ 1279399182U, // MOVSX64rr8
+ 138024214U, // MOVUPDmr
+ 138024214U, // MOVUPDmr_Int
+ 1946162454U, // MOVUPDrm
+ 1946162454U, // MOVUPDrm_Int
+ 1279399190U, // MOVUPDrr
+ 138024222U, // MOVUPSmr
+ 138024222U, // MOVUPSmr_Int
+ 1946162462U, // MOVUPSrm
+ 1946162462U, // MOVUPSrm_Int
+ 1279399198U, // MOVUPSrr
+ 1342181814U, // MOVZDI2PDIrm
+ 1279398326U, // MOVZDI2PDIrr
+ 2281705942U, // MOVZPQILo2PQIrm
+ 1279398358U, // MOVZPQILo2PQIrr
+ 1409290710U, // MOVZQI2PQIrm
+ 1279398326U, // MOVZQI2PQIrr
0U, // MOVZX16rm8
- 1690309899U, // MOVZX16rm8W
+ 1690309926U, // MOVZX16rm8W
0U, // MOVZX16rr8
- 1279399179U, // MOVZX16rr8W
- 1728058643U, // MOVZX32_NOREXrm8
- 1280840979U, // MOVZX32_NOREXrr8
- 1207964955U, // MOVZX32rm16
- 1690309907U, // MOVZX32rm8
- 1279399195U, // MOVZX32rr16
- 1279399187U, // MOVZX32rr8
+ 1279399206U, // MOVZX16rr8W
+ 1728058670U, // MOVZX32_NOREXrm8
+ 1280841006U, // MOVZX32_NOREXrr8
+ 1207964982U, // MOVZX32rm16
+ 1690309934U, // MOVZX32rm8
+ 1279399222U, // MOVZX32rr16
+ 1279399214U, // MOVZX32rr8
0U, // MOVZX64rm16
- 1207964963U, // MOVZX64rm16_Q
+ 1207964990U, // MOVZX64rm16_Q
0U, // MOVZX64rm32
0U, // MOVZX64rm8
- 1690309931U, // MOVZX64rm8_Q
+ 1690309958U, // MOVZX64rm8_Q
0U, // MOVZX64rr16
- 1279399203U, // MOVZX64rr16_Q
+ 1279399230U, // MOVZX64rr16_Q
0U, // MOVZX64rr32
0U, // MOVZX64rr8
- 1279399211U, // MOVZX64rr8_Q
+ 1279399238U, // MOVZX64rr8_Q
0U, // MOV_Fp3232
0U, // MOV_Fp3264
0U, // MOV_Fp3280
@@ -1457,34 +1458,34 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // MOV_Fp8032
0U, // MOV_Fp8064
0U, // MOV_Fp8080
- 1021318451U, // MPSADBWrmi
- 1073747251U, // MPSADBWrri
- 872420668U, // MUL16m
- 79697212U, // MUL16r
- 952112450U, // MUL32m
- 79697218U, // MUL32r
- 1476400456U, // MUL64m
- 79697224U, // MUL64r
- 1610618190U, // MUL8m
- 79697230U, // MUL8r
- 536876372U, // MULPDrm
- 205657428U, // MULPDrr
- 536876379U, // MULPSrm
- 205657435U, // MULPSrr
- 603985250U, // MULSDrm
- 603985250U, // MULSDrm_Int
- 205657442U, // MULSDrr
- 205657442U, // MULSDrr_Int
- 671094121U, // MULSSrm
- 671094121U, // MULSSrm_Int
- 205657449U, // MULSSrr
- 205657449U, // MULSSrr_Int
- 738202992U, // MUL_F32m
- 805311863U, // MUL_F64m
- 872420734U, // MUL_FI16m
- 952112518U, // MUL_FI32m
- 79697294U, // MUL_FPrST0
- 79697301U, // MUL_FST0r
+ 1021318478U, // MPSADBWrmi
+ 1073747278U, // MPSADBWrri
+ 872420695U, // MUL16m
+ 79697239U, // MUL16r
+ 952112477U, // MUL32m
+ 79697245U, // MUL32r
+ 1476400483U, // MUL64m
+ 79697251U, // MUL64r
+ 1610618217U, // MUL8m
+ 79697257U, // MUL8r
+ 536876399U, // MULPDrm
+ 205657455U, // MULPDrr
+ 536876406U, // MULPSrm
+ 205657462U, // MULPSrr
+ 603985277U, // MULSDrm
+ 603985277U, // MULSDrm_Int
+ 205657469U, // MULSDrr
+ 205657469U, // MULSDrr_Int
+ 671094148U, // MULSSrm
+ 671094148U, // MULSSrm_Int
+ 205657476U, // MULSSrr
+ 205657476U, // MULSSrr_Int
+ 738203019U, // MUL_F32m
+ 805311890U, // MUL_F64m
+ 872420761U, // MUL_FI16m
+ 952112545U, // MUL_FI32m
+ 79697321U, // MUL_FPrST0
+ 79697328U, // MUL_FST0r
0U, // MUL_Fp32
0U, // MUL_Fp32m
0U, // MUL_Fp64
@@ -1499,792 +1500,792 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // MUL_FpI32m32
0U, // MUL_FpI32m64
0U, // MUL_FpI32m80
- 79697307U, // MUL_FrST0
- 5545U, // MWAIT
- 872420783U, // NEG16m
- 79697327U, // NEG16r
- 952112565U, // NEG32m
- 79697333U, // NEG32r
- 1476400571U, // NEG64m
- 79697339U, // NEG64r
- 1610618305U, // NEG8m
- 79697345U, // NEG8r
- 5575U, // NOOP
- 952112587U, // NOOPL
- 872420817U, // NOOPW
- 872420823U, // NOT16m
- 79697367U, // NOT16r
- 952112605U, // NOT32m
- 79697373U, // NOT32r
- 1476400611U, // NOT64m
- 79697379U, // NOT64r
- 1610618345U, // NOT8m
- 79697385U, // NOT8r
- 67114479U, // OR16i16
- 136320495U, // OR16mi
- 136320495U, // OR16mi8
- 136320495U, // OR16mr
- 205657583U, // OR16ri
- 205657583U, // OR16ri8
- 272766447U, // OR16rm
- 205657583U, // OR16rr
- 205657583U, // OR16rr_REV
- 73405940U, // OR32i32
- 136582644U, // OR32mi
- 136582644U, // OR32mi8
- 136582644U, // OR32mr
- 205657588U, // OR32ri
- 205657588U, // OR32ri8
- 339875316U, // OR32rm
- 205657588U, // OR32rr
- 205657588U, // OR32rr_REV
- 75503097U, // OR64i32
- 136713721U, // OR64mi32
- 136713721U, // OR64mi8
- 136713721U, // OR64mr
- 205657593U, // OR64ri32
- 205657593U, // OR64ri8
- 406984185U, // OR64rm
- 205657593U, // OR64rr
- 205657593U, // OR64rr_REV
- 77600254U, // OR8i8
- 136844798U, // OR8mi
- 136844798U, // OR8mr
- 205657598U, // OR8ri
- 474093054U, // OR8rm
- 205657598U, // OR8rr
- 205657598U, // OR8rr_REV
+ 79697334U, // MUL_FrST0
+ 5572U, // MWAIT
+ 872420810U, // NEG16m
+ 79697354U, // NEG16r
+ 952112592U, // NEG32m
+ 79697360U, // NEG32r
+ 1476400598U, // NEG64m
+ 79697366U, // NEG64r
+ 1610618332U, // NEG8m
+ 79697372U, // NEG8r
+ 5602U, // NOOP
+ 952112614U, // NOOPL
+ 872420844U, // NOOPW
+ 872420850U, // NOT16m
+ 79697394U, // NOT16r
+ 952112632U, // NOT32m
+ 79697400U, // NOT32r
+ 1476400638U, // NOT64m
+ 79697406U, // NOT64r
+ 1610618372U, // NOT8m
+ 79697412U, // NOT8r
+ 67114506U, // OR16i16
+ 136320522U, // OR16mi
+ 136320522U, // OR16mi8
+ 136320522U, // OR16mr
+ 205657610U, // OR16ri
+ 205657610U, // OR16ri8
+ 272766474U, // OR16rm
+ 205657610U, // OR16rr
+ 205657610U, // OR16rr_REV
+ 73405967U, // OR32i32
+ 136582671U, // OR32mi
+ 136582671U, // OR32mi8
+ 136582671U, // OR32mr
+ 205657615U, // OR32ri
+ 205657615U, // OR32ri8
+ 339875343U, // OR32rm
+ 205657615U, // OR32rr
+ 205657615U, // OR32rr_REV
+ 75503124U, // OR64i32
+ 136713748U, // OR64mi32
+ 136713748U, // OR64mi8
+ 136713748U, // OR64mr
+ 205657620U, // OR64ri32
+ 205657620U, // OR64ri8
+ 406984212U, // OR64rm
+ 205657620U, // OR64rr
+ 205657620U, // OR64rr_REV
+ 77600281U, // OR8i8
+ 136844825U, // OR8mi
+ 136844825U, // OR8mr
+ 205657625U, // OR8ri
+ 474093081U, // OR8rm
+ 205657625U, // OR8rr
+ 205657625U, // OR8rr_REV
536874112U, // ORPDrm
205655168U, // ORPDrr
536874118U, // ORPSrm
205655174U, // ORPSrr
- 79697411U, // OUT16ir
- 5646U, // OUT16rr
- 79697436U, // OUT32ir
- 5672U, // OUT32rr
- 79697463U, // OUT8ir
- 5698U, // OUT8rr
- 5712U, // OUTSB
- 5718U, // OUTSD
- 5724U, // OUTSW
- 2281707106U, // PABSBrm128
- 1409291874U, // PABSBrm64
- 1279399522U, // PABSBrr128
- 1279399522U, // PABSBrr64
- 2281707113U, // PABSDrm128
- 1409291881U, // PABSDrm64
- 1279399529U, // PABSDrr128
- 1279399529U, // PABSDrr64
- 2281707120U, // PABSWrm128
- 1409291888U, // PABSWrm64
- 1279399536U, // PABSWrr128
- 1279399536U, // PABSWrr64
- 1140855233U, // PACKSSDWrm
- 205656513U, // PACKSSDWrr
- 1140855243U, // PACKSSWBrm
- 205656523U, // PACKSSWBrr
- 1140856439U, // PACKUSDWrm
- 205657719U, // PACKUSDWrr
- 1140855253U, // PACKUSWBrm
- 205656533U, // PACKUSWBrr
- 1140855263U, // PADDBrm
- 205656543U, // PADDBrr
- 1140855270U, // PADDDrm
- 205656550U, // PADDDrr
- 1140855277U, // PADDQrm
- 205656557U, // PADDQrr
- 1140855284U, // PADDSBrm
- 205656564U, // PADDSBrr
- 1140855292U, // PADDSWrm
- 205656572U, // PADDSWrr
- 1140855300U, // PADDUSBrm
- 205656580U, // PADDUSBrr
- 1140855309U, // PADDUSWrm
- 205656589U, // PADDUSWrr
- 1140855318U, // PADDWrm
- 205656598U, // PADDWrr
- 1021318785U, // PALIGNR128rm
- 1073747585U, // PALIGNR128rr
- 1054217857U, // PALIGNR64rm
- 1073747585U, // PALIGNR64rr
- 1140855325U, // PANDNrm
- 205656605U, // PANDNrr
- 1140855332U, // PANDrm
- 205656612U, // PANDrr
- 1140855338U, // PAVGBrm
- 205656618U, // PAVGBrr
- 1140855345U, // PAVGWrm
- 205656625U, // PAVGWrr
- 1140856458U, // PBLENDVBrm0
- 205657738U, // PBLENDVBrr0
- 1021318811U, // PBLENDWrmi
- 1073747611U, // PBLENDWrri
- 1140855352U, // PCMPEQBrm
- 205656632U, // PCMPEQBrr
- 1140855361U, // PCMPEQDrm
- 205656641U, // PCMPEQDrr
- 1140856484U, // PCMPEQQrm
- 205657764U, // PCMPEQQrr
- 1140855370U, // PCMPEQWrm
- 205656650U, // PCMPEQWrr
- 2199918253U, // PCMPESTRIArm
- 230037165U, // PCMPESTRIArr
- 2199918253U, // PCMPESTRICrm
- 230037165U, // PCMPESTRICrr
- 2199918253U, // PCMPESTRIOrm
- 230037165U, // PCMPESTRIOrr
- 2199918253U, // PCMPESTRISrm
- 230037165U, // PCMPESTRISrr
- 2199918253U, // PCMPESTRIZrm
- 230037165U, // PCMPESTRIZrr
- 2199918253U, // PCMPESTRIrm
- 230037165U, // PCMPESTRIrr
- 5816U, // PCMPESTRM128MEM
- 5840U, // PCMPESTRM128REG
- 2199918312U, // PCMPESTRM128rm
- 230037224U, // PCMPESTRM128rr
- 1140855379U, // PCMPGTBrm
- 205656659U, // PCMPGTBrr
- 1140855388U, // PCMPGTDrm
- 205656668U, // PCMPGTDrr
- 1140856563U, // PCMPGTQrm
- 205657843U, // PCMPGTQrr
- 1140855397U, // PCMPGTWrm
- 205656677U, // PCMPGTWrr
- 2199918332U, // PCMPISTRIArm
- 230037244U, // PCMPISTRIArr
- 2199918332U, // PCMPISTRICrm
- 230037244U, // PCMPISTRICrr
- 2199918332U, // PCMPISTRIOrm
- 230037244U, // PCMPISTRIOrr
- 2199918332U, // PCMPISTRISrm
- 230037244U, // PCMPISTRISrr
- 2199918332U, // PCMPISTRIZrm
- 230037244U, // PCMPISTRIZrr
- 2199918332U, // PCMPISTRIrm
- 230037244U, // PCMPISTRIrr
- 5895U, // PCMPISTRM128MEM
- 5919U, // PCMPISTRM128REG
- 2199918391U, // PCMPISTRM128rm
- 230037303U, // PCMPISTRM128rr
- 2177374018U, // PEXTRBmr
- 230037314U, // PEXTRBrr
- 2177111882U, // PEXTRDmr
- 230037322U, // PEXTRDrr
- 2177242962U, // PEXTRQmr
- 230037330U, // PEXTRQrr
- 2176848494U, // PEXTRWmr
- 230036078U, // PEXTRWri
- 1140856666U, // PHADDDrm128
- 406984538U, // PHADDDrm64
- 205657946U, // PHADDDrr128
- 205657946U, // PHADDDrr64
- 1140856674U, // PHADDSWrm128
- 406984546U, // PHADDSWrm64
- 205657954U, // PHADDSWrr128
- 205657954U, // PHADDSWrr64
- 1140856683U, // PHADDWrm128
- 406984555U, // PHADDWrm64
- 205657963U, // PHADDWrr128
- 205657963U, // PHADDWrr64
- 2281707379U, // PHMINPOSUWrm128
- 1279399795U, // PHMINPOSUWrr128
- 1140856703U, // PHSUBDrm128
- 406984575U, // PHSUBDrm64
- 205657983U, // PHSUBDrr128
- 205657983U, // PHSUBDrr64
- 1140856711U, // PHSUBSWrm128
- 406984583U, // PHSUBSWrm64
- 205657991U, // PHSUBSWrr128
- 205657991U, // PHSUBSWrr64
- 1140856720U, // PHSUBWrm128
- 406984592U, // PHSUBWrm64
- 205658000U, // PHSUBWrr128
- 205658000U, // PHSUBWrr64
- 1056315288U, // PINSRBrm
- 1073747864U, // PINSRBrr
- 1052120992U, // PINSRDrm
- 1073747872U, // PINSRDrr
- 1054218152U, // PINSRQrm
- 1073747880U, // PINSRQrr
- 1050022518U, // PINSRWrmi
- 1073746550U, // PINSRWrri
- 1140856752U, // PMADDUBSWrm128
- 406984624U, // PMADDUBSWrm64
- 205658032U, // PMADDUBSWrr128
- 205658032U, // PMADDUBSWrr64
- 1140855422U, // PMADDWDrm
- 205656702U, // PMADDWDrr
- 1140856763U, // PMAXSBrm
- 205658043U, // PMAXSBrr
- 1140856771U, // PMAXSDrm
- 205658051U, // PMAXSDrr
- 1140855431U, // PMAXSWrm
- 205656711U, // PMAXSWrr
- 1140855439U, // PMAXUBrm
- 205656719U, // PMAXUBrr
- 1140856779U, // PMAXUDrm
- 205658059U, // PMAXUDrr
- 1140856787U, // PMAXUWrm
- 205658067U, // PMAXUWrr
- 1140856795U, // PMINSBrm
- 205658075U, // PMINSBrr
- 1140856803U, // PMINSDrm
- 205658083U, // PMINSDrr
- 1140855447U, // PMINSWrm
- 205656727U, // PMINSWrr
- 1140855455U, // PMINUBrm
- 205656735U, // PMINUBrr
- 1140856811U, // PMINUDrm
- 205658091U, // PMINUDrr
- 1140856819U, // PMINUWrm
- 205658099U, // PMINUWrr
- 1279398567U, // PMOVMSKBrr
- 1342183419U, // PMOVSXBDrm
- 1279399931U, // PMOVSXBDrr
- 1207965701U, // PMOVSXBQrm
- 1279399941U, // PMOVSXBQrr
- 1409292303U, // PMOVSXBWrm
- 1279399951U, // PMOVSXBWrr
- 1409292313U, // PMOVSXDQrm
- 1279399961U, // PMOVSXDQrr
- 1409292323U, // PMOVSXWDrm
- 1279399971U, // PMOVSXWDrr
- 1342183469U, // PMOVSXWQrm
- 1279399981U, // PMOVSXWQrr
- 1342183479U, // PMOVZXBDrm
- 1279399991U, // PMOVZXBDrr
- 1207965761U, // PMOVZXBQrm
- 1279400001U, // PMOVZXBQrr
- 1409292363U, // PMOVZXBWrm
- 1279400011U, // PMOVZXBWrr
- 1409292373U, // PMOVZXDQrm
- 1279400021U, // PMOVZXDQrr
- 1409292383U, // PMOVZXWDrm
- 1279400031U, // PMOVZXWDrr
- 1342183529U, // PMOVZXWQrm
- 1279400041U, // PMOVZXWQrr
- 1140856947U, // PMULDQrm
- 205658227U, // PMULDQrr
- 1140856955U, // PMULHRSWrm128
- 406984827U, // PMULHRSWrm64
- 205658235U, // PMULHRSWrr128
- 205658235U, // PMULHRSWrr64
- 1140855473U, // PMULHUWrm
- 205656753U, // PMULHUWrr
- 1140855482U, // PMULHWrm
- 205656762U, // PMULHWrr
- 1140856965U, // PMULLDrm
- 1140856965U, // PMULLDrm_int
- 205658245U, // PMULLDrr
- 205658245U, // PMULLDrr_int
- 1140855490U, // PMULLWrm
- 205656770U, // PMULLWrr
- 1140855498U, // PMULUDQrm
- 205656778U, // PMULUDQrr
- 79698061U, // POP16r
- 872421517U, // POP16rmm
- 79698061U, // POP16rmr
- 79698067U, // POP32r
- 952113299U, // POP32rmm
- 79698067U, // POP32rmr
- 79698073U, // POP64r
- 1476401305U, // POP64rmm
- 79698073U, // POP64rmr
- 1207965855U, // POPCNT16rm
- 1279400095U, // POPCNT16rr
- 1342183592U, // POPCNT32rm
- 1279400104U, // POPCNT32rr
- 1409292465U, // POPCNT64rm
- 1279400113U, // POPCNT64rr
- 6330U, // POPF
- 6336U, // POPFD
- 6342U, // POPFQ
- 6348U, // POPFS16
- 6357U, // POPFS32
- 6366U, // POPFS64
- 6375U, // POPGS16
- 6384U, // POPGS32
- 6393U, // POPGS64
- 1140855507U, // PORrm
- 205656787U, // PORrr
- 1610619138U, // PREFETCHNTA
- 1610619151U, // PREFETCHT0
- 1610619163U, // PREFETCHT1
- 1610619175U, // PREFETCHT2
- 1140855512U, // PSADBWrm
- 205656792U, // PSADBWrr
- 1140857139U, // PSHUFBrm128
- 406985011U, // PSHUFBrm64
- 205658419U, // PSHUFBrr128
- 205658419U, // PSHUFBrr64
- 2199918907U, // PSHUFDmi
- 230037819U, // PSHUFDri
- 2199918915U, // PSHUFHWmi
- 230037827U, // PSHUFHWri
- 2199918924U, // PSHUFLWmi
- 230037836U, // PSHUFLWri
- 1140857173U, // PSIGNBrm128
- 406985045U, // PSIGNBrm64
- 205658453U, // PSIGNBrr128
- 205658453U, // PSIGNBrr64
- 1140857181U, // PSIGNDrm128
- 406985053U, // PSIGNDrm64
- 205658461U, // PSIGNDrr128
- 205658461U, // PSIGNDrr64
- 1140857189U, // PSIGNWrm128
- 406985061U, // PSIGNWrm64
- 205658469U, // PSIGNWrr128
- 205658469U, // PSIGNWrr64
- 205658477U, // PSLLDQri
- 205656808U, // PSLLDri
- 1140855528U, // PSLLDrm
- 205656808U, // PSLLDrr
- 205656815U, // PSLLQri
- 1140855535U, // PSLLQrm
- 205656815U, // PSLLQrr
- 205656822U, // PSLLWri
- 1140855542U, // PSLLWrm
- 205656822U, // PSLLWrr
- 205656829U, // PSRADri
- 1140855549U, // PSRADrm
- 205656829U, // PSRADrr
- 205656836U, // PSRAWri
- 1140855556U, // PSRAWrm
- 205656836U, // PSRAWrr
- 205658485U, // PSRLDQri
- 205656843U, // PSRLDri
- 1140855563U, // PSRLDrm
- 205656843U, // PSRLDrr
- 205656850U, // PSRLQri
- 1140855570U, // PSRLQrm
- 205656850U, // PSRLQrr
- 205656857U, // PSRLWri
- 1140855577U, // PSRLWrm
- 205656857U, // PSRLWrr
- 1140855584U, // PSUBBrm
- 205656864U, // PSUBBrr
- 1140855591U, // PSUBDrm
- 205656871U, // PSUBDrr
- 1140855598U, // PSUBQrm
- 205656878U, // PSUBQrr
- 1140855605U, // PSUBSBrm
- 205656885U, // PSUBSBrr
- 1140855613U, // PSUBSWrm
- 205656893U, // PSUBSWrr
- 1140855621U, // PSUBUSBrm
- 205656901U, // PSUBUSBrr
- 1140855630U, // PSUBUSWrm
- 205656910U, // PSUBUSWrr
- 1140855639U, // PSUBWrm
- 205656919U, // PSUBWrr
- 2281707901U, // PTESTrm
- 1279400317U, // PTESTrr
- 1140855646U, // PUNPCKHBWrm
- 205656926U, // PUNPCKHBWrr
- 1140855657U, // PUNPCKHDQrm
- 205656937U, // PUNPCKHDQrr
- 1140857221U, // PUNPCKHQDQrm
- 205658501U, // PUNPCKHQDQrr
- 1140855668U, // PUNPCKHWDrm
- 205656948U, // PUNPCKHWDrr
- 1140855679U, // PUNPCKLBWrm
- 205656959U, // PUNPCKLBWrr
- 1140855690U, // PUNPCKLDQrm
- 205656970U, // PUNPCKLDQrr
- 1140857233U, // PUNPCKLQDQrm
- 205658513U, // PUNPCKLQDQrr
- 1140855701U, // PUNPCKLWDrm
- 205656981U, // PUNPCKLWDrr
- 79698333U, // PUSH16r
- 872421789U, // PUSH16rmm
- 79698333U, // PUSH16rmr
- 79698340U, // PUSH32i16
- 79698340U, // PUSH32i32
- 79698340U, // PUSH32i8
- 79698340U, // PUSH32r
- 952113572U, // PUSH32rmm
- 79698340U, // PUSH32rmr
- 79698347U, // PUSH64i16
- 79698347U, // PUSH64i32
- 79698347U, // PUSH64i8
- 79698347U, // PUSH64r
- 1476401579U, // PUSH64rmm
- 79698347U, // PUSH64rmr
- 6578U, // PUSHF
- 6585U, // PUSHFD
- 6592U, // PUSHFQ64
- 6599U, // PUSHFS16
- 6609U, // PUSHFS32
- 6619U, // PUSHFS64
- 6629U, // PUSHGS16
- 6639U, // PUSHGS32
- 6649U, // PUSHGS64
- 1140855712U, // PXORrm
- 205656992U, // PXORrr
- 872421891U, // RCL16m1
- 872421900U, // RCL16mCL
- 136321559U, // RCL16mi
- 79698435U, // RCL16r1
- 79698444U, // RCL16rCL
- 205658647U, // RCL16ri
- 952113693U, // RCL32m1
- 952113702U, // RCL32mCL
- 136583729U, // RCL32mi
- 79698461U, // RCL32r1
- 79698470U, // RCL32rCL
- 205658673U, // RCL32ri
- 1476401719U, // RCL64m1
- 1476401728U, // RCL64mCL
- 136714827U, // RCL64mi
- 79698487U, // RCL64r1
- 79698496U, // RCL64rCL
- 205658699U, // RCL64ri
- 1610619473U, // RCL8m1
- 1610619482U, // RCL8mCL
- 136845925U, // RCL8mi
- 79698513U, // RCL8r1
- 79698522U, // RCL8rCL
- 205658725U, // RCL8ri
- 1946163819U, // RCPPSm
- 1946163819U, // RCPPSm_Int
- 1279400555U, // RCPPSr
- 1279400555U, // RCPPSr_Int
- 2080381554U, // RCPSSm
- 2080381554U, // RCPSSm_Int
- 1279400562U, // RCPSSr
- 1279400562U, // RCPSSr_Int
- 872422009U, // RCR16m1
- 872422018U, // RCR16mCL
- 136321677U, // RCR16mi
- 79698553U, // RCR16r1
- 79698562U, // RCR16rCL
- 205658765U, // RCR16ri
- 952113811U, // RCR32m1
- 952113820U, // RCR32mCL
- 136583847U, // RCR32mi
- 79698579U, // RCR32r1
- 79698588U, // RCR32rCL
- 205658791U, // RCR32ri
- 1476401837U, // RCR64m1
- 1476401846U, // RCR64mCL
- 136714945U, // RCR64mi
- 79698605U, // RCR64r1
- 79698614U, // RCR64rCL
- 205658817U, // RCR64ri
- 1610619591U, // RCR8m1
- 1610619600U, // RCR8mCL
- 136846043U, // RCR8mi
- 79698631U, // RCR8r1
- 79698640U, // RCR8rCL
- 205658843U, // RCR8ri
- 6881U, // RDMSR
- 6887U, // RDPMC
- 6893U, // RDTSC
- 6899U, // RDTSCP
- 6906U, // REPNE_PREFIX
- 6912U, // REP_MOVSB
- 6922U, // REP_MOVSD
- 6932U, // REP_MOVSQ
- 6942U, // REP_MOVSW
- 6952U, // REP_PREFIX
- 6956U, // REP_STOSB
- 6966U, // REP_STOSD
- 6976U, // REP_STOSQ
- 6986U, // REP_STOSW
- 6996U, // RET
- 79698776U, // RETI
- 872422237U, // ROL16m1
- 872422243U, // ROL16mCL
- 136321885U, // ROL16mi
- 79698781U, // ROL16r1
- 79698787U, // ROL16rCL
- 205658973U, // ROL16ri
- 952114030U, // ROL32m1
- 952114036U, // ROL32mCL
- 136584046U, // ROL32mi
- 79698798U, // ROL32r1
- 79698804U, // ROL32rCL
- 205658990U, // ROL32ri
- 1476402047U, // ROL64m1
- 1476402053U, // ROL64mCL
- 136715135U, // ROL64mi
- 79698815U, // ROL64r1
- 79698821U, // ROL64rCL
- 205659007U, // ROL64ri
- 1610619792U, // ROL8m1
- 1610619798U, // ROL8mCL
- 136846224U, // ROL8mi
- 79698832U, // ROL8r1
- 79698838U, // ROL8rCL
- 205659024U, // ROL8ri
- 872422305U, // ROR16m1
- 872422311U, // ROR16mCL
- 136321953U, // ROR16mi
- 79698849U, // ROR16r1
- 79698855U, // ROR16rCL
- 205659041U, // ROR16ri
- 952114098U, // ROR32m1
- 952114104U, // ROR32mCL
- 136584114U, // ROR32mi
- 79698866U, // ROR32r1
- 79698872U, // ROR32rCL
- 205659058U, // ROR32ri
- 1476402115U, // ROR64m1
- 1476402121U, // ROR64mCL
- 136715203U, // ROR64mi
- 79698883U, // ROR64r1
- 79698889U, // ROR64rCL
- 205659075U, // ROR64ri
- 1610619860U, // ROR8m1
- 1610619866U, // ROR8mCL
- 136846292U, // ROR8mi
- 79698900U, // ROR8r1
- 79698906U, // ROR8rCL
- 205659092U, // ROR8ri
- 2202016741U, // ROUNDPDm_Int
- 230038501U, // ROUNDPDr_Int
- 2202016750U, // ROUNDPSm_Int
- 230038510U, // ROUNDPSr_Int
- 1063263223U, // ROUNDSDm_Int
- 1073748983U, // ROUNDSDr_Int
- 1044388864U, // ROUNDSSm_Int
- 1073748992U, // ROUNDSSr_Int
- 7177U, // RSM
- 1946164237U, // RSQRTPSm
- 1946164237U, // RSQRTPSm_Int
- 1279400973U, // RSQRTPSr
- 1279400973U, // RSQRTPSr_Int
- 2080381974U, // RSQRTSSm
- 2080381974U, // RSQRTSSm_Int
- 1279400982U, // RSQRTSSr
- 1279400982U, // RSQRTSSr_Int
- 7199U, // SAHF
- 872422436U, // SAR16m1
- 872422442U, // SAR16mCL
- 136322084U, // SAR16mi
- 79698980U, // SAR16r1
- 79698986U, // SAR16rCL
- 205659172U, // SAR16ri
- 952114229U, // SAR32m1
- 952114235U, // SAR32mCL
- 136584245U, // SAR32mi
- 79698997U, // SAR32r1
- 79699003U, // SAR32rCL
- 205659189U, // SAR32ri
- 1476402246U, // SAR64m1
- 1476402252U, // SAR64mCL
- 136715334U, // SAR64mi
- 79699014U, // SAR64r1
- 79699020U, // SAR64rCL
- 205659206U, // SAR64ri
- 1610619991U, // SAR8m1
- 1610619997U, // SAR8mCL
- 136846423U, // SAR8mi
- 79699031U, // SAR8r1
- 79699037U, // SAR8rCL
- 205659223U, // SAR8ri
- 67116136U, // SBB16i16
- 136322152U, // SBB16mi
- 136322152U, // SBB16mi8
- 136322152U, // SBB16mr
- 205659240U, // SBB16ri
- 205659240U, // SBB16ri8
- 272768104U, // SBB16rm
- 205659240U, // SBB16rr
- 205659240U, // SBB16rr_REV
- 73407598U, // SBB32i32
- 136584302U, // SBB32mi
- 136584302U, // SBB32mi8
- 136584302U, // SBB32mr
- 205659246U, // SBB32ri
- 205659246U, // SBB32ri8
- 339876974U, // SBB32rm
- 205659246U, // SBB32rr
- 205659246U, // SBB32rr_REV
- 75504756U, // SBB64i32
- 136715380U, // SBB64mi32
- 136715380U, // SBB64mi8
- 136715380U, // SBB64mr
- 205659252U, // SBB64ri32
- 205659252U, // SBB64ri8
- 406985844U, // SBB64rm
- 205659252U, // SBB64rr
- 205659252U, // SBB64rr_REV
- 77601914U, // SBB8i8
- 136846458U, // SBB8mi
- 136846458U, // SBB8mr
- 205659258U, // SBB8ri
- 474094714U, // SBB8rm
- 205659258U, // SBB8rr
- 205659258U, // SBB8rr_REV
- 7296U, // SCAS16
- 7302U, // SCAS32
- 7308U, // SCAS64
- 7314U, // SCAS8
- 1610620056U, // SETAEm
- 79699096U, // SETAEr
- 1610620063U, // SETAm
- 79699103U, // SETAr
- 1610620069U, // SETBEm
- 79699109U, // SETBEr
+ 79697438U, // OUT16ir
+ 5673U, // OUT16rr
+ 79697463U, // OUT32ir
+ 5699U, // OUT32rr
+ 79697490U, // OUT8ir
+ 5725U, // OUT8rr
+ 5739U, // OUTSB
+ 5745U, // OUTSD
+ 5751U, // OUTSW
+ 2281707133U, // PABSBrm128
+ 1409291901U, // PABSBrm64
+ 1279399549U, // PABSBrr128
+ 1279399549U, // PABSBrr64
+ 2281707140U, // PABSDrm128
+ 1409291908U, // PABSDrm64
+ 1279399556U, // PABSDrr128
+ 1279399556U, // PABSDrr64
+ 2281707147U, // PABSWrm128
+ 1409291915U, // PABSWrm64
+ 1279399563U, // PABSWrr128
+ 1279399563U, // PABSWrr64
+ 1140855260U, // PACKSSDWrm
+ 205656540U, // PACKSSDWrr
+ 1140855270U, // PACKSSWBrm
+ 205656550U, // PACKSSWBrr
+ 1140856466U, // PACKUSDWrm
+ 205657746U, // PACKUSDWrr
+ 1140855280U, // PACKUSWBrm
+ 205656560U, // PACKUSWBrr
+ 1140855290U, // PADDBrm
+ 205656570U, // PADDBrr
+ 1140855297U, // PADDDrm
+ 205656577U, // PADDDrr
+ 1140855304U, // PADDQrm
+ 205656584U, // PADDQrr
+ 1140855311U, // PADDSBrm
+ 205656591U, // PADDSBrr
+ 1140855319U, // PADDSWrm
+ 205656599U, // PADDSWrr
+ 1140855327U, // PADDUSBrm
+ 205656607U, // PADDUSBrr
+ 1140855336U, // PADDUSWrm
+ 205656616U, // PADDUSWrr
+ 1140855345U, // PADDWrm
+ 205656625U, // PADDWrr
+ 1021318812U, // PALIGNR128rm
+ 1073747612U, // PALIGNR128rr
+ 1054217884U, // PALIGNR64rm
+ 1073747612U, // PALIGNR64rr
+ 1140855352U, // PANDNrm
+ 205656632U, // PANDNrr
+ 1140855359U, // PANDrm
+ 205656639U, // PANDrr
+ 1140855365U, // PAVGBrm
+ 205656645U, // PAVGBrr
+ 1140855372U, // PAVGWrm
+ 205656652U, // PAVGWrr
+ 1140856485U, // PBLENDVBrm0
+ 205657765U, // PBLENDVBrr0
+ 1021318838U, // PBLENDWrmi
+ 1073747638U, // PBLENDWrri
+ 1140855379U, // PCMPEQBrm
+ 205656659U, // PCMPEQBrr
+ 1140855388U, // PCMPEQDrm
+ 205656668U, // PCMPEQDrr
+ 1140856511U, // PCMPEQQrm
+ 205657791U, // PCMPEQQrr
+ 1140855397U, // PCMPEQWrm
+ 205656677U, // PCMPEQWrr
+ 2199918280U, // PCMPESTRIArm
+ 230037192U, // PCMPESTRIArr
+ 2199918280U, // PCMPESTRICrm
+ 230037192U, // PCMPESTRICrr
+ 2199918280U, // PCMPESTRIOrm
+ 230037192U, // PCMPESTRIOrr
+ 2199918280U, // PCMPESTRISrm
+ 230037192U, // PCMPESTRISrr
+ 2199918280U, // PCMPESTRIZrm
+ 230037192U, // PCMPESTRIZrr
+ 2199918280U, // PCMPESTRIrm
+ 230037192U, // PCMPESTRIrr
+ 5843U, // PCMPESTRM128MEM
+ 5867U, // PCMPESTRM128REG
+ 2199918339U, // PCMPESTRM128rm
+ 230037251U, // PCMPESTRM128rr
+ 1140855406U, // PCMPGTBrm
+ 205656686U, // PCMPGTBrr
+ 1140855415U, // PCMPGTDrm
+ 205656695U, // PCMPGTDrr
+ 1140856590U, // PCMPGTQrm
+ 205657870U, // PCMPGTQrr
+ 1140855424U, // PCMPGTWrm
+ 205656704U, // PCMPGTWrr
+ 2199918359U, // PCMPISTRIArm
+ 230037271U, // PCMPISTRIArr
+ 2199918359U, // PCMPISTRICrm
+ 230037271U, // PCMPISTRICrr
+ 2199918359U, // PCMPISTRIOrm
+ 230037271U, // PCMPISTRIOrr
+ 2199918359U, // PCMPISTRISrm
+ 230037271U, // PCMPISTRISrr
+ 2199918359U, // PCMPISTRIZrm
+ 230037271U, // PCMPISTRIZrr
+ 2199918359U, // PCMPISTRIrm
+ 230037271U, // PCMPISTRIrr
+ 5922U, // PCMPISTRM128MEM
+ 5946U, // PCMPISTRM128REG
+ 2199918418U, // PCMPISTRM128rm
+ 230037330U, // PCMPISTRM128rr
+ 2177374045U, // PEXTRBmr
+ 230037341U, // PEXTRBrr
+ 2177111909U, // PEXTRDmr
+ 230037349U, // PEXTRDrr
+ 2177242989U, // PEXTRQmr
+ 230037357U, // PEXTRQrr
+ 2176848521U, // PEXTRWmr
+ 230036105U, // PEXTRWri
+ 1140856693U, // PHADDDrm128
+ 406984565U, // PHADDDrm64
+ 205657973U, // PHADDDrr128
+ 205657973U, // PHADDDrr64
+ 1140856701U, // PHADDSWrm128
+ 406984573U, // PHADDSWrm64
+ 205657981U, // PHADDSWrr128
+ 205657981U, // PHADDSWrr64
+ 1140856710U, // PHADDWrm128
+ 406984582U, // PHADDWrm64
+ 205657990U, // PHADDWrr128
+ 205657990U, // PHADDWrr64
+ 2281707406U, // PHMINPOSUWrm128
+ 1279399822U, // PHMINPOSUWrr128
+ 1140856730U, // PHSUBDrm128
+ 406984602U, // PHSUBDrm64
+ 205658010U, // PHSUBDrr128
+ 205658010U, // PHSUBDrr64
+ 1140856738U, // PHSUBSWrm128
+ 406984610U, // PHSUBSWrm64
+ 205658018U, // PHSUBSWrr128
+ 205658018U, // PHSUBSWrr64
+ 1140856747U, // PHSUBWrm128
+ 406984619U, // PHSUBWrm64
+ 205658027U, // PHSUBWrr128
+ 205658027U, // PHSUBWrr64
+ 1056315315U, // PINSRBrm
+ 1073747891U, // PINSRBrr
+ 1052121019U, // PINSRDrm
+ 1073747899U, // PINSRDrr
+ 1054218179U, // PINSRQrm
+ 1073747907U, // PINSRQrr
+ 1050022545U, // PINSRWrmi
+ 1073746577U, // PINSRWrri
+ 1140856779U, // PMADDUBSWrm128
+ 406984651U, // PMADDUBSWrm64
+ 205658059U, // PMADDUBSWrr128
+ 205658059U, // PMADDUBSWrr64
+ 1140855449U, // PMADDWDrm
+ 205656729U, // PMADDWDrr
+ 1140856790U, // PMAXSBrm
+ 205658070U, // PMAXSBrr
+ 1140856798U, // PMAXSDrm
+ 205658078U, // PMAXSDrr
+ 1140855458U, // PMAXSWrm
+ 205656738U, // PMAXSWrr
+ 1140855466U, // PMAXUBrm
+ 205656746U, // PMAXUBrr
+ 1140856806U, // PMAXUDrm
+ 205658086U, // PMAXUDrr
+ 1140856814U, // PMAXUWrm
+ 205658094U, // PMAXUWrr
+ 1140856822U, // PMINSBrm
+ 205658102U, // PMINSBrr
+ 1140856830U, // PMINSDrm
+ 205658110U, // PMINSDrr
+ 1140855474U, // PMINSWrm
+ 205656754U, // PMINSWrr
+ 1140855482U, // PMINUBrm
+ 205656762U, // PMINUBrr
+ 1140856838U, // PMINUDrm
+ 205658118U, // PMINUDrr
+ 1140856846U, // PMINUWrm
+ 205658126U, // PMINUWrr
+ 1279398594U, // PMOVMSKBrr
+ 1342183446U, // PMOVSXBDrm
+ 1279399958U, // PMOVSXBDrr
+ 1207965728U, // PMOVSXBQrm
+ 1279399968U, // PMOVSXBQrr
+ 1409292330U, // PMOVSXBWrm
+ 1279399978U, // PMOVSXBWrr
+ 1409292340U, // PMOVSXDQrm
+ 1279399988U, // PMOVSXDQrr
+ 1409292350U, // PMOVSXWDrm
+ 1279399998U, // PMOVSXWDrr
+ 1342183496U, // PMOVSXWQrm
+ 1279400008U, // PMOVSXWQrr
+ 1342183506U, // PMOVZXBDrm
+ 1279400018U, // PMOVZXBDrr
+ 1207965788U, // PMOVZXBQrm
+ 1279400028U, // PMOVZXBQrr
+ 1409292390U, // PMOVZXBWrm
+ 1279400038U, // PMOVZXBWrr
+ 1409292400U, // PMOVZXDQrm
+ 1279400048U, // PMOVZXDQrr
+ 1409292410U, // PMOVZXWDrm
+ 1279400058U, // PMOVZXWDrr
+ 1342183556U, // PMOVZXWQrm
+ 1279400068U, // PMOVZXWQrr
+ 1140856974U, // PMULDQrm
+ 205658254U, // PMULDQrr
+ 1140856982U, // PMULHRSWrm128
+ 406984854U, // PMULHRSWrm64
+ 205658262U, // PMULHRSWrr128
+ 205658262U, // PMULHRSWrr64
+ 1140855500U, // PMULHUWrm
+ 205656780U, // PMULHUWrr
+ 1140855509U, // PMULHWrm
+ 205656789U, // PMULHWrr
+ 1140856992U, // PMULLDrm
+ 1140856992U, // PMULLDrm_int
+ 205658272U, // PMULLDrr
+ 205658272U, // PMULLDrr_int
+ 1140855517U, // PMULLWrm
+ 205656797U, // PMULLWrr
+ 1140855525U, // PMULUDQrm
+ 205656805U, // PMULUDQrr
+ 79698088U, // POP16r
+ 872421544U, // POP16rmm
+ 79698088U, // POP16rmr
+ 79698094U, // POP32r
+ 952113326U, // POP32rmm
+ 79698094U, // POP32rmr
+ 79698100U, // POP64r
+ 1476401332U, // POP64rmm
+ 79698100U, // POP64rmr
+ 1207965882U, // POPCNT16rm
+ 1279400122U, // POPCNT16rr
+ 1342183619U, // POPCNT32rm
+ 1279400131U, // POPCNT32rr
+ 1409292492U, // POPCNT64rm
+ 1279400140U, // POPCNT64rr
+ 6357U, // POPF
+ 6363U, // POPFD
+ 6369U, // POPFQ
+ 6375U, // POPFS16
+ 6384U, // POPFS32
+ 6393U, // POPFS64
+ 6402U, // POPGS16
+ 6411U, // POPGS32
+ 6420U, // POPGS64
+ 1140855534U, // PORrm
+ 205656814U, // PORrr
+ 1610619165U, // PREFETCHNTA
+ 1610619178U, // PREFETCHT0
+ 1610619190U, // PREFETCHT1
+ 1610619202U, // PREFETCHT2
+ 1140855539U, // PSADBWrm
+ 205656819U, // PSADBWrr
+ 1140857166U, // PSHUFBrm128
+ 406985038U, // PSHUFBrm64
+ 205658446U, // PSHUFBrr128
+ 205658446U, // PSHUFBrr64
+ 2199918934U, // PSHUFDmi
+ 230037846U, // PSHUFDri
+ 2199918942U, // PSHUFHWmi
+ 230037854U, // PSHUFHWri
+ 2199918951U, // PSHUFLWmi
+ 230037863U, // PSHUFLWri
+ 1140857200U, // PSIGNBrm128
+ 406985072U, // PSIGNBrm64
+ 205658480U, // PSIGNBrr128
+ 205658480U, // PSIGNBrr64
+ 1140857208U, // PSIGNDrm128
+ 406985080U, // PSIGNDrm64
+ 205658488U, // PSIGNDrr128
+ 205658488U, // PSIGNDrr64
+ 1140857216U, // PSIGNWrm128
+ 406985088U, // PSIGNWrm64
+ 205658496U, // PSIGNWrr128
+ 205658496U, // PSIGNWrr64
+ 205658504U, // PSLLDQri
+ 205656835U, // PSLLDri
+ 1140855555U, // PSLLDrm
+ 205656835U, // PSLLDrr
+ 205656842U, // PSLLQri
+ 1140855562U, // PSLLQrm
+ 205656842U, // PSLLQrr
+ 205656849U, // PSLLWri
+ 1140855569U, // PSLLWrm
+ 205656849U, // PSLLWrr
+ 205656856U, // PSRADri
+ 1140855576U, // PSRADrm
+ 205656856U, // PSRADrr
+ 205656863U, // PSRAWri
+ 1140855583U, // PSRAWrm
+ 205656863U, // PSRAWrr
+ 205658512U, // PSRLDQri
+ 205656870U, // PSRLDri
+ 1140855590U, // PSRLDrm
+ 205656870U, // PSRLDrr
+ 205656877U, // PSRLQri
+ 1140855597U, // PSRLQrm
+ 205656877U, // PSRLQrr
+ 205656884U, // PSRLWri
+ 1140855604U, // PSRLWrm
+ 205656884U, // PSRLWrr
+ 1140855611U, // PSUBBrm
+ 205656891U, // PSUBBrr
+ 1140855618U, // PSUBDrm
+ 205656898U, // PSUBDrr
+ 1140855625U, // PSUBQrm
+ 205656905U, // PSUBQrr
+ 1140855632U, // PSUBSBrm
+ 205656912U, // PSUBSBrr
+ 1140855640U, // PSUBSWrm
+ 205656920U, // PSUBSWrr
+ 1140855648U, // PSUBUSBrm
+ 205656928U, // PSUBUSBrr
+ 1140855657U, // PSUBUSWrm
+ 205656937U, // PSUBUSWrr
+ 1140855666U, // PSUBWrm
+ 205656946U, // PSUBWrr
+ 2281707928U, // PTESTrm
+ 1279400344U, // PTESTrr
+ 1140855673U, // PUNPCKHBWrm
+ 205656953U, // PUNPCKHBWrr
+ 1140855684U, // PUNPCKHDQrm
+ 205656964U, // PUNPCKHDQrr
+ 1140857248U, // PUNPCKHQDQrm
+ 205658528U, // PUNPCKHQDQrr
+ 1140855695U, // PUNPCKHWDrm
+ 205656975U, // PUNPCKHWDrr
+ 1140855706U, // PUNPCKLBWrm
+ 205656986U, // PUNPCKLBWrr
+ 1140855717U, // PUNPCKLDQrm
+ 205656997U, // PUNPCKLDQrr
+ 1140857260U, // PUNPCKLQDQrm
+ 205658540U, // PUNPCKLQDQrr
+ 1140855728U, // PUNPCKLWDrm
+ 205657008U, // PUNPCKLWDrr
+ 79698360U, // PUSH16r
+ 872421816U, // PUSH16rmm
+ 79698360U, // PUSH16rmr
+ 79698367U, // PUSH32i16
+ 79698367U, // PUSH32i32
+ 79698367U, // PUSH32i8
+ 79698367U, // PUSH32r
+ 952113599U, // PUSH32rmm
+ 79698367U, // PUSH32rmr
+ 79698374U, // PUSH64i16
+ 79698374U, // PUSH64i32
+ 79698374U, // PUSH64i8
+ 79698374U, // PUSH64r
+ 1476401606U, // PUSH64rmm
+ 79698374U, // PUSH64rmr
+ 6605U, // PUSHF
+ 6612U, // PUSHFD
+ 6619U, // PUSHFQ64
+ 6626U, // PUSHFS16
+ 6636U, // PUSHFS32
+ 6646U, // PUSHFS64
+ 6656U, // PUSHGS16
+ 6666U, // PUSHGS32
+ 6676U, // PUSHGS64
+ 1140855739U, // PXORrm
+ 205657019U, // PXORrr
+ 872421918U, // RCL16m1
+ 872421927U, // RCL16mCL
+ 136321586U, // RCL16mi
+ 79698462U, // RCL16r1
+ 79698471U, // RCL16rCL
+ 205658674U, // RCL16ri
+ 952113720U, // RCL32m1
+ 952113729U, // RCL32mCL
+ 136583756U, // RCL32mi
+ 79698488U, // RCL32r1
+ 79698497U, // RCL32rCL
+ 205658700U, // RCL32ri
+ 1476401746U, // RCL64m1
+ 1476401755U, // RCL64mCL
+ 136714854U, // RCL64mi
+ 79698514U, // RCL64r1
+ 79698523U, // RCL64rCL
+ 205658726U, // RCL64ri
+ 1610619500U, // RCL8m1
+ 1610619509U, // RCL8mCL
+ 136845952U, // RCL8mi
+ 79698540U, // RCL8r1
+ 79698549U, // RCL8rCL
+ 205658752U, // RCL8ri
+ 1946163846U, // RCPPSm
+ 1946163846U, // RCPPSm_Int
+ 1279400582U, // RCPPSr
+ 1279400582U, // RCPPSr_Int
+ 2080381581U, // RCPSSm
+ 2080381581U, // RCPSSm_Int
+ 1279400589U, // RCPSSr
+ 1279400589U, // RCPSSr_Int
+ 872422036U, // RCR16m1
+ 872422045U, // RCR16mCL
+ 136321704U, // RCR16mi
+ 79698580U, // RCR16r1
+ 79698589U, // RCR16rCL
+ 205658792U, // RCR16ri
+ 952113838U, // RCR32m1
+ 952113847U, // RCR32mCL
+ 136583874U, // RCR32mi
+ 79698606U, // RCR32r1
+ 79698615U, // RCR32rCL
+ 205658818U, // RCR32ri
+ 1476401864U, // RCR64m1
+ 1476401873U, // RCR64mCL
+ 136714972U, // RCR64mi
+ 79698632U, // RCR64r1
+ 79698641U, // RCR64rCL
+ 205658844U, // RCR64ri
+ 1610619618U, // RCR8m1
+ 1610619627U, // RCR8mCL
+ 136846070U, // RCR8mi
+ 79698658U, // RCR8r1
+ 79698667U, // RCR8rCL
+ 205658870U, // RCR8ri
+ 6908U, // RDMSR
+ 6914U, // RDPMC
+ 6920U, // RDTSC
+ 6926U, // RDTSCP
+ 6933U, // REPNE_PREFIX
+ 6939U, // REP_MOVSB
+ 6949U, // REP_MOVSD
+ 6959U, // REP_MOVSQ
+ 6969U, // REP_MOVSW
+ 6979U, // REP_PREFIX
+ 6983U, // REP_STOSB
+ 6993U, // REP_STOSD
+ 7003U, // REP_STOSQ
+ 7013U, // REP_STOSW
+ 7023U, // RET
+ 79698803U, // RETI
+ 872422264U, // ROL16m1
+ 872422270U, // ROL16mCL
+ 136321912U, // ROL16mi
+ 79698808U, // ROL16r1
+ 79698814U, // ROL16rCL
+ 205659000U, // ROL16ri
+ 952114057U, // ROL32m1
+ 952114063U, // ROL32mCL
+ 136584073U, // ROL32mi
+ 79698825U, // ROL32r1
+ 79698831U, // ROL32rCL
+ 205659017U, // ROL32ri
+ 1476402074U, // ROL64m1
+ 1476402080U, // ROL64mCL
+ 136715162U, // ROL64mi
+ 79698842U, // ROL64r1
+ 79698848U, // ROL64rCL
+ 205659034U, // ROL64ri
+ 1610619819U, // ROL8m1
+ 1610619825U, // ROL8mCL
+ 136846251U, // ROL8mi
+ 79698859U, // ROL8r1
+ 79698865U, // ROL8rCL
+ 205659051U, // ROL8ri
+ 872422332U, // ROR16m1
+ 872422338U, // ROR16mCL
+ 136321980U, // ROR16mi
+ 79698876U, // ROR16r1
+ 79698882U, // ROR16rCL
+ 205659068U, // ROR16ri
+ 952114125U, // ROR32m1
+ 952114131U, // ROR32mCL
+ 136584141U, // ROR32mi
+ 79698893U, // ROR32r1
+ 79698899U, // ROR32rCL
+ 205659085U, // ROR32ri
+ 1476402142U, // ROR64m1
+ 1476402148U, // ROR64mCL
+ 136715230U, // ROR64mi
+ 79698910U, // ROR64r1
+ 79698916U, // ROR64rCL
+ 205659102U, // ROR64ri
+ 1610619887U, // ROR8m1
+ 1610619893U, // ROR8mCL
+ 136846319U, // ROR8mi
+ 79698927U, // ROR8r1
+ 79698933U, // ROR8rCL
+ 205659119U, // ROR8ri
+ 2202016768U, // ROUNDPDm_Int
+ 230038528U, // ROUNDPDr_Int
+ 2202016777U, // ROUNDPSm_Int
+ 230038537U, // ROUNDPSr_Int
+ 1063263250U, // ROUNDSDm_Int
+ 1073749010U, // ROUNDSDr_Int
+ 1044388891U, // ROUNDSSm_Int
+ 1073749019U, // ROUNDSSr_Int
+ 7204U, // RSM
+ 1946164264U, // RSQRTPSm
+ 1946164264U, // RSQRTPSm_Int
+ 1279401000U, // RSQRTPSr
+ 1279401000U, // RSQRTPSr_Int
+ 2080382001U, // RSQRTSSm
+ 2080382001U, // RSQRTSSm_Int
+ 1279401009U, // RSQRTSSr
+ 1279401009U, // RSQRTSSr_Int
+ 7226U, // SAHF
+ 872422463U, // SAR16m1
+ 872422469U, // SAR16mCL
+ 136322111U, // SAR16mi
+ 79699007U, // SAR16r1
+ 79699013U, // SAR16rCL
+ 205659199U, // SAR16ri
+ 952114256U, // SAR32m1
+ 952114262U, // SAR32mCL
+ 136584272U, // SAR32mi
+ 79699024U, // SAR32r1
+ 79699030U, // SAR32rCL
+ 205659216U, // SAR32ri
+ 1476402273U, // SAR64m1
+ 1476402279U, // SAR64mCL
+ 136715361U, // SAR64mi
+ 79699041U, // SAR64r1
+ 79699047U, // SAR64rCL
+ 205659233U, // SAR64ri
+ 1610620018U, // SAR8m1
+ 1610620024U, // SAR8mCL
+ 136846450U, // SAR8mi
+ 79699058U, // SAR8r1
+ 79699064U, // SAR8rCL
+ 205659250U, // SAR8ri
+ 67116163U, // SBB16i16
+ 136322179U, // SBB16mi
+ 136322179U, // SBB16mi8
+ 136322179U, // SBB16mr
+ 205659267U, // SBB16ri
+ 205659267U, // SBB16ri8
+ 272768131U, // SBB16rm
+ 205659267U, // SBB16rr
+ 205659267U, // SBB16rr_REV
+ 73407625U, // SBB32i32
+ 136584329U, // SBB32mi
+ 136584329U, // SBB32mi8
+ 136584329U, // SBB32mr
+ 205659273U, // SBB32ri
+ 205659273U, // SBB32ri8
+ 339877001U, // SBB32rm
+ 205659273U, // SBB32rr
+ 205659273U, // SBB32rr_REV
+ 75504783U, // SBB64i32
+ 136715407U, // SBB64mi32
+ 136715407U, // SBB64mi8
+ 136715407U, // SBB64mr
+ 205659279U, // SBB64ri32
+ 205659279U, // SBB64ri8
+ 406985871U, // SBB64rm
+ 205659279U, // SBB64rr
+ 205659279U, // SBB64rr_REV
+ 77601941U, // SBB8i8
+ 136846485U, // SBB8mi
+ 136846485U, // SBB8mr
+ 205659285U, // SBB8ri
+ 474094741U, // SBB8rm
+ 205659285U, // SBB8rr
+ 205659285U, // SBB8rr_REV
+ 7323U, // SCAS16
+ 7329U, // SCAS32
+ 7335U, // SCAS64
+ 7341U, // SCAS8
+ 1610620083U, // SETAEm
+ 79699123U, // SETAEr
+ 1610620090U, // SETAm
+ 79699130U, // SETAr
+ 1610620096U, // SETBEm
+ 79699136U, // SETBEr
0U, // SETB_C16r
0U, // SETB_C32r
0U, // SETB_C64r
0U, // SETB_C8r
- 1610620076U, // SETBm
- 79699116U, // SETBr
- 1610620082U, // SETEm
- 79699122U, // SETEr
- 1610620088U, // SETGEm
- 79699128U, // SETGEr
- 1610620095U, // SETGm
- 79699135U, // SETGr
- 1610620101U, // SETLEm
- 79699141U, // SETLEr
- 1610620108U, // SETLm
- 79699148U, // SETLr
- 1610620114U, // SETNEm
- 79699154U, // SETNEr
- 1610620121U, // SETNOm
- 79699161U, // SETNOr
- 1610620128U, // SETNPm
- 79699168U, // SETNPr
- 1610620135U, // SETNSm
- 79699175U, // SETNSr
- 1610620142U, // SETOm
- 79699182U, // SETOr
- 1610620148U, // SETPm
- 79699188U, // SETPr
- 1610620154U, // SETSm
- 79699194U, // SETSr
- 7424U, // SFENCE
- 2214599943U, // SGDTm
- 872422669U, // SHL16m1
- 872422675U, // SHL16mCL
- 136322317U, // SHL16mi
- 79699213U, // SHL16r1
- 79699219U, // SHL16rCL
- 205659405U, // SHL16ri
- 952114462U, // SHL32m1
- 952114468U, // SHL32mCL
- 136584478U, // SHL32mi
- 79699230U, // SHL32r1
- 79699236U, // SHL32rCL
- 205659422U, // SHL32ri
- 1476402479U, // SHL64m1
- 1476402485U, // SHL64mCL
- 136715567U, // SHL64mi
- 79699247U, // SHL64r1
- 79699253U, // SHL64rCL
- 205659439U, // SHL64ri
- 1610620224U, // SHL8m1
- 1610620230U, // SHL8mCL
- 136846656U, // SHL8mi
- 79699264U, // SHL8r1
- 79699270U, // SHL8rCL
- 205659456U, // SHL8ri
- 136322385U, // SHLD16mrCL
- 2176851293U, // SHLD16mri8
- 205659473U, // SHLD16rrCL
- 1073749341U, // SHLD16rri8
- 136584548U, // SHLD32mrCL
- 2177113456U, // SHLD32mri8
- 205659492U, // SHLD32rrCL
- 1073749360U, // SHLD32rri8
- 136715639U, // SHLD64mrCL
- 2177244547U, // SHLD64mri8
- 205659511U, // SHLD64rrCL
- 1073749379U, // SHLD64rri8
- 872422794U, // SHR16m1
- 872422800U, // SHR16mCL
- 136322442U, // SHR16mi
- 79699338U, // SHR16r1
- 79699344U, // SHR16rCL
- 205659530U, // SHR16ri
- 952114587U, // SHR32m1
- 952114593U, // SHR32mCL
- 136584603U, // SHR32mi
- 79699355U, // SHR32r1
- 79699361U, // SHR32rCL
- 205659547U, // SHR32ri
- 1476402604U, // SHR64m1
- 1476402610U, // SHR64mCL
- 136715692U, // SHR64mi
- 79699372U, // SHR64r1
- 79699378U, // SHR64rCL
- 205659564U, // SHR64ri
- 1610620349U, // SHR8m1
- 1610620355U, // SHR8mCL
- 136846781U, // SHR8mi
- 79699389U, // SHR8r1
- 79699395U, // SHR8rCL
- 205659581U, // SHR8ri
- 136322510U, // SHRD16mrCL
- 2176851418U, // SHRD16mri8
- 205659598U, // SHRD16rrCL
- 1073749466U, // SHRD16rri8
- 136584673U, // SHRD32mrCL
- 2177113581U, // SHRD32mri8
- 205659617U, // SHRD32rrCL
- 1073749485U, // SHRD32rri8
- 136715764U, // SHRD64mrCL
- 2177244672U, // SHRD64mri8
- 205659636U, // SHRD64rrCL
- 1073749504U, // SHRD64rri8
- 1065360903U, // SHUFPDrmi
- 1073749511U, // SHUFPDrri
- 1065360911U, // SHUFPSrmi
- 1073749519U, // SHUFPSrri
- 2214600215U, // SIDTm
- 7709U, // SIN_F
+ 1610620103U, // SETBm
+ 79699143U, // SETBr
+ 1610620109U, // SETEm
+ 79699149U, // SETEr
+ 1610620115U, // SETGEm
+ 79699155U, // SETGEr
+ 1610620122U, // SETGm
+ 79699162U, // SETGr
+ 1610620128U, // SETLEm
+ 79699168U, // SETLEr
+ 1610620135U, // SETLm
+ 79699175U, // SETLr
+ 1610620141U, // SETNEm
+ 79699181U, // SETNEr
+ 1610620148U, // SETNOm
+ 79699188U, // SETNOr
+ 1610620155U, // SETNPm
+ 79699195U, // SETNPr
+ 1610620162U, // SETNSm
+ 79699202U, // SETNSr
+ 1610620169U, // SETOm
+ 79699209U, // SETOr
+ 1610620175U, // SETPm
+ 79699215U, // SETPr
+ 1610620181U, // SETSm
+ 79699221U, // SETSr
+ 7451U, // SFENCE
+ 2214599970U, // SGDTm
+ 872422696U, // SHL16m1
+ 872422702U, // SHL16mCL
+ 136322344U, // SHL16mi
+ 79699240U, // SHL16r1
+ 79699246U, // SHL16rCL
+ 205659432U, // SHL16ri
+ 952114489U, // SHL32m1
+ 952114495U, // SHL32mCL
+ 136584505U, // SHL32mi
+ 79699257U, // SHL32r1
+ 79699263U, // SHL32rCL
+ 205659449U, // SHL32ri
+ 1476402506U, // SHL64m1
+ 1476402512U, // SHL64mCL
+ 136715594U, // SHL64mi
+ 79699274U, // SHL64r1
+ 79699280U, // SHL64rCL
+ 205659466U, // SHL64ri
+ 1610620251U, // SHL8m1
+ 1610620257U, // SHL8mCL
+ 136846683U, // SHL8mi
+ 79699291U, // SHL8r1
+ 79699297U, // SHL8rCL
+ 205659483U, // SHL8ri
+ 136322412U, // SHLD16mrCL
+ 2176851320U, // SHLD16mri8
+ 205659500U, // SHLD16rrCL
+ 1073749368U, // SHLD16rri8
+ 136584575U, // SHLD32mrCL
+ 2177113483U, // SHLD32mri8
+ 205659519U, // SHLD32rrCL
+ 1073749387U, // SHLD32rri8
+ 136715666U, // SHLD64mrCL
+ 2177244574U, // SHLD64mri8
+ 205659538U, // SHLD64rrCL
+ 1073749406U, // SHLD64rri8
+ 872422821U, // SHR16m1
+ 872422827U, // SHR16mCL
+ 136322469U, // SHR16mi
+ 79699365U, // SHR16r1
+ 79699371U, // SHR16rCL
+ 205659557U, // SHR16ri
+ 952114614U, // SHR32m1
+ 952114620U, // SHR32mCL
+ 136584630U, // SHR32mi
+ 79699382U, // SHR32r1
+ 79699388U, // SHR32rCL
+ 205659574U, // SHR32ri
+ 1476402631U, // SHR64m1
+ 1476402637U, // SHR64mCL
+ 136715719U, // SHR64mi
+ 79699399U, // SHR64r1
+ 79699405U, // SHR64rCL
+ 205659591U, // SHR64ri
+ 1610620376U, // SHR8m1
+ 1610620382U, // SHR8mCL
+ 136846808U, // SHR8mi
+ 79699416U, // SHR8r1
+ 79699422U, // SHR8rCL
+ 205659608U, // SHR8ri
+ 136322537U, // SHRD16mrCL
+ 2176851445U, // SHRD16mri8
+ 205659625U, // SHRD16rrCL
+ 1073749493U, // SHRD16rri8
+ 136584700U, // SHRD32mrCL
+ 2177113608U, // SHRD32mri8
+ 205659644U, // SHRD32rrCL
+ 1073749512U, // SHRD32rri8
+ 136715791U, // SHRD64mrCL
+ 2177244699U, // SHRD64mri8
+ 205659663U, // SHRD64rrCL
+ 1073749531U, // SHRD64rri8
+ 1065360930U, // SHUFPDrmi
+ 1073749538U, // SHUFPDrri
+ 1065360938U, // SHUFPSrmi
+ 1073749546U, // SHUFPSrri
+ 2214600242U, // SIDTm
+ 7736U, // SIN_F
0U, // SIN_Fp32
0U, // SIN_Fp64
0U, // SIN_Fp80
- 872422946U, // SLDT16m
- 79699490U, // SLDT16r
- 872422953U, // SLDT64m
- 79699497U, // SLDT64r
- 872422960U, // SMSW16m
- 79699504U, // SMSW16r
- 79699511U, // SMSW32r
- 79699518U, // SMSW64r
- 1946164805U, // SQRTPDm
- 1946164805U, // SQRTPDm_Int
- 1279401541U, // SQRTPDr
- 1279401541U, // SQRTPDr_Int
- 1946164813U, // SQRTPSm
- 1946164813U, // SQRTPSm_Int
- 1279401549U, // SQRTPSr
- 1279401549U, // SQRTPSr_Int
- 2013273685U, // SQRTSDm
- 2013273685U, // SQRTSDm_Int
- 1279401557U, // SQRTSDr
- 1279401557U, // SQRTSDr_Int
- 2080382557U, // SQRTSSm
- 2080382557U, // SQRTSSm_Int
- 1279401565U, // SQRTSSr
- 1279401565U, // SQRTSSr_Int
- 7781U, // SQRT_F
+ 872422973U, // SLDT16m
+ 79699517U, // SLDT16r
+ 872422980U, // SLDT64m
+ 79699524U, // SLDT64r
+ 872422987U, // SMSW16m
+ 79699531U, // SMSW16r
+ 79699538U, // SMSW32r
+ 79699545U, // SMSW64r
+ 1946164832U, // SQRTPDm
+ 1946164832U, // SQRTPDm_Int
+ 1279401568U, // SQRTPDr
+ 1279401568U, // SQRTPDr_Int
+ 1946164840U, // SQRTPSm
+ 1946164840U, // SQRTPSm_Int
+ 1279401576U, // SQRTPSr
+ 1279401576U, // SQRTPSr_Int
+ 2013273712U, // SQRTSDm
+ 2013273712U, // SQRTSDm_Int
+ 1279401584U, // SQRTSDr
+ 1279401584U, // SQRTSDr_Int
+ 2080382584U, // SQRTSSm
+ 2080382584U, // SQRTSSm_Int
+ 1279401592U, // SQRTSSr
+ 1279401592U, // SQRTSSr_Int
+ 7808U, // SQRT_F
0U, // SQRT_Fp32
0U, // SQRT_Fp64
0U, // SQRT_Fp80
- 7787U, // SS_PREFIX
- 7790U, // STC
- 7794U, // STD
- 7798U, // STI
- 952114810U, // STMXCSR
- 7811U, // STOSB
- 7817U, // STOSD
- 7823U, // STOSW
- 872423061U, // STRm
- 79699605U, // STRr
- 738205339U, // ST_F32m
- 805314209U, // ST_F64m
- 738205351U, // ST_FP32m
- 805314222U, // ST_FP64m
- 2415926965U, // ST_FP80m
- 79699644U, // ST_FPrr
+ 7814U, // SS_PREFIX
+ 7817U, // STC
+ 7821U, // STD
+ 7825U, // STI
+ 952114837U, // STMXCSR
+ 7838U, // STOSB
+ 7844U, // STOSD
+ 7850U, // STOSW
+ 872423088U, // STRm
+ 79699632U, // STRr
+ 738205366U, // ST_F32m
+ 805314236U, // ST_F64m
+ 738205378U, // ST_FP32m
+ 805314249U, // ST_FP64m
+ 2415926992U, // ST_FP80m
+ 79699671U, // ST_FPrr
0U, // ST_Fp32m
0U, // ST_Fp64m
0U, // ST_Fp64m32
@@ -2296,51 +2297,51 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // ST_FpP80m
0U, // ST_FpP80m32
0U, // ST_FpP80m64
- 79699650U, // ST_Frr
- 67116743U, // SUB16i16
- 136322759U, // SUB16mi
- 136322759U, // SUB16mi8
- 136322759U, // SUB16mr
- 205659847U, // SUB16ri
- 205659847U, // SUB16ri8
- 272768711U, // SUB16rm
- 205659847U, // SUB16rr
- 205659847U, // SUB16rr_REV
- 73408205U, // SUB32i32
- 136584909U, // SUB32mi
- 136584909U, // SUB32mi8
- 136584909U, // SUB32mr
- 205659853U, // SUB32ri
- 205659853U, // SUB32ri8
- 339877581U, // SUB32rm
- 205659853U, // SUB32rr
- 205659853U, // SUB32rr_REV
- 75505363U, // SUB64i32
- 136715987U, // SUB64mi32
- 136715987U, // SUB64mi8
- 136715987U, // SUB64mr
- 205659859U, // SUB64ri32
- 205659859U, // SUB64ri8
- 406986451U, // SUB64rm
- 205659859U, // SUB64rr
- 205659859U, // SUB64rr_REV
- 77602521U, // SUB8i8
- 136847065U, // SUB8mi
- 136847065U, // SUB8mr
- 205659865U, // SUB8ri
- 474095321U, // SUB8rm
- 205659865U, // SUB8rr
- 205659865U, // SUB8rr_REV
- 536878815U, // SUBPDrm
- 205659871U, // SUBPDrr
- 536878822U, // SUBPSrm
- 205659878U, // SUBPSrr
- 738205421U, // SUBR_F32m
- 805314293U, // SUBR_F64m
- 872423165U, // SUBR_FI16m
- 952114950U, // SUBR_FI32m
- 79699727U, // SUBR_FPrST0
- 79699734U, // SUBR_FST0r
+ 79699677U, // ST_Frr
+ 67116770U, // SUB16i16
+ 136322786U, // SUB16mi
+ 136322786U, // SUB16mi8
+ 136322786U, // SUB16mr
+ 205659874U, // SUB16ri
+ 205659874U, // SUB16ri8
+ 272768738U, // SUB16rm
+ 205659874U, // SUB16rr
+ 205659874U, // SUB16rr_REV
+ 73408232U, // SUB32i32
+ 136584936U, // SUB32mi
+ 136584936U, // SUB32mi8
+ 136584936U, // SUB32mr
+ 205659880U, // SUB32ri
+ 205659880U, // SUB32ri8
+ 339877608U, // SUB32rm
+ 205659880U, // SUB32rr
+ 205659880U, // SUB32rr_REV
+ 75505390U, // SUB64i32
+ 136716014U, // SUB64mi32
+ 136716014U, // SUB64mi8
+ 136716014U, // SUB64mr
+ 205659886U, // SUB64ri32
+ 205659886U, // SUB64ri8
+ 406986478U, // SUB64rm
+ 205659886U, // SUB64rr
+ 205659886U, // SUB64rr_REV
+ 77602548U, // SUB8i8
+ 136847092U, // SUB8mi
+ 136847092U, // SUB8mr
+ 205659892U, // SUB8ri
+ 474095348U, // SUB8rm
+ 205659892U, // SUB8rr
+ 205659892U, // SUB8rr_REV
+ 536878842U, // SUBPDrm
+ 205659898U, // SUBPDrr
+ 536878849U, // SUBPSrm
+ 205659905U, // SUBPSrr
+ 738205448U, // SUBR_F32m
+ 805314320U, // SUBR_F64m
+ 872423192U, // SUBR_FI16m
+ 952114977U, // SUBR_FI32m
+ 79699754U, // SUBR_FPrST0
+ 79699761U, // SUBR_FST0r
0U, // SUBR_Fp32m
0U, // SUBR_Fp64m
0U, // SUBR_Fp64m32
@@ -2352,21 +2353,21 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // SUBR_FpI32m32
0U, // SUBR_FpI32m64
0U, // SUBR_FpI32m80
- 79699741U, // SUBR_FrST0
- 603987755U, // SUBSDrm
- 603987755U, // SUBSDrm_Int
- 205659947U, // SUBSDrr
- 205659947U, // SUBSDrr_Int
- 671096626U, // SUBSSrm
- 671096626U, // SUBSSrm_Int
- 205659954U, // SUBSSrr
- 205659954U, // SUBSSrr_Int
- 738205497U, // SUB_F32m
- 805314368U, // SUB_F64m
- 872423239U, // SUB_FI16m
- 952115023U, // SUB_FI32m
- 79699799U, // SUB_FPrST0
- 79699807U, // SUB_FST0r
+ 79699768U, // SUBR_FrST0
+ 603987782U, // SUBSDrm
+ 603987782U, // SUBSDrm_Int
+ 205659974U, // SUBSDrr
+ 205659974U, // SUBSDrr_Int
+ 671096653U, // SUBSSrm
+ 671096653U, // SUBSSrm_Int
+ 205659981U, // SUBSSrr
+ 205659981U, // SUBSSrr_Int
+ 738205524U, // SUB_F32m
+ 805314395U, // SUB_F64m
+ 872423266U, // SUB_FI16m
+ 952115050U, // SUB_FI32m
+ 79699826U, // SUB_FPrST0
+ 79699834U, // SUB_FST0r
0U, // SUB_Fp32
0U, // SUB_Fp32m
0U, // SUB_Fp64
@@ -2381,45 +2382,45 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // SUB_FpI32m32
0U, // SUB_FpI32m64
0U, // SUB_FpI32m80
- 79699813U, // SUB_FrST0
- 8052U, // SWAPGS
- 8059U, // SYSCALL
- 8067U, // SYSENTER
- 8076U, // SYSEXIT
- 8076U, // SYSEXIT64
- 8084U, // SYSRET
+ 79699840U, // SUB_FrST0
+ 8079U, // SWAPGS
+ 8086U, // SYSCALL
+ 8094U, // SYSENTER
+ 8103U, // SYSEXIT
+ 8103U, // SYSEXIT64
+ 8111U, // SYSRET
1604325038U, // TAILJMPd
- 1000349595U, // TAILJMPm
+ 1000349622U, // TAILJMPm
127930010U, // TAILJMPr
127930017U, // TAILJMPr64
- 130031521U, // TCRETURNdi
- 130031521U, // TCRETURNdi64
- 130031521U, // TCRETURNri
- 130031521U, // TCRETURNri64
- 67116973U, // TEST16i16
- 136322989U, // TEST16mi
- 1279401901U, // TEST16ri
- 1207967661U, // TEST16rm
- 1279401901U, // TEST16rr
- 73408436U, // TEST32i32
- 136585140U, // TEST32mi
- 1279401908U, // TEST32ri
- 1342185396U, // TEST32rm
- 1279401908U, // TEST32rr
- 75505595U, // TEST64i32
- 136716219U, // TEST64mi32
- 1279401915U, // TEST64ri32
- 1409294267U, // TEST64rm
- 1279401915U, // TEST64rr
- 77602754U, // TEST8i8
- 136847298U, // TEST8mi
- 1279401922U, // TEST8ri
- 1690312642U, // TEST8rm
- 1279401922U, // TEST8rr
+ 130031548U, // TCRETURNdi
+ 130031548U, // TCRETURNdi64
+ 130031548U, // TCRETURNri
+ 130031548U, // TCRETURNri64
+ 67117000U, // TEST16i16
+ 136323016U, // TEST16mi
+ 1279401928U, // TEST16ri
+ 1207967688U, // TEST16rm
+ 1279401928U, // TEST16rr
+ 73408463U, // TEST32i32
+ 136585167U, // TEST32mi
+ 1279401935U, // TEST32ri
+ 1342185423U, // TEST32rm
+ 1279401935U, // TEST32rr
+ 75505622U, // TEST64i32
+ 136716246U, // TEST64mi32
+ 1279401942U, // TEST64ri32
+ 1409294294U, // TEST64rm
+ 1279401942U, // TEST64rr
+ 77602781U, // TEST8i8
+ 136847325U, // TEST8mi
+ 1279401949U, // TEST8ri
+ 1690312669U, // TEST8rm
+ 1279401949U, // TEST8rr
2684358526U, // TLS_addr32
- 2751471561U, // TLS_addr64
- 8155U, // TRAP
- 8159U, // TST_F
+ 2751471588U, // TLS_addr64
+ 8182U, // TRAP
+ 8186U, // TST_F
0U, // TST_Fp32
0U, // TST_Fp64
0U, // TST_Fp80
@@ -2427,109 +2428,109 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
1279397466U, // UCOMISDrr
2080378467U, // UCOMISSrm
1279397475U, // UCOMISSrr
- 83894244U, // UCOM_FIPr
- 83894253U, // UCOM_FIr
- 8181U, // UCOM_FPPr
- 79699965U, // UCOM_FPr
+ 83894271U, // UCOM_FIPr
+ 83894280U, // UCOM_FIr
+ 8208U, // UCOM_FPPr
+ 79699992U, // UCOM_FPr
0U, // UCOM_FpIr32
0U, // UCOM_FpIr64
0U, // UCOM_FpIr80
0U, // UCOM_Fpr32
0U, // UCOM_Fpr64
0U, // UCOM_Fpr80
- 79699973U, // UCOM_Fr
- 536879116U, // UNPCKHPDrm
- 205660172U, // UNPCKHPDrr
- 536879126U, // UNPCKHPSrm
- 205660182U, // UNPCKHPSrr
- 536879136U, // UNPCKLPDrm
- 205660192U, // UNPCKLPDrr
- 536879146U, // UNPCKLPSrm
- 205660202U, // UNPCKLPSrr
- 70459444U, // VASTART_SAVE_XMM_REGS
- 872423500U, // VERRm
- 79700044U, // VERRr
- 872423506U, // VERWm
- 79700050U, // VERWr
- 8280U, // VMCALL
- 1476403295U, // VMCLEARm
- 8296U, // VMLAUNCH
- 1476403313U, // VMPTRLDm
- 1476403322U, // VMPTRSTm
- 136585347U, // VMREAD32rm
- 1279402115U, // VMREAD32rr
- 136716428U, // VMREAD64rm
- 1279402124U, // VMREAD64rr
- 8341U, // VMRESUME
- 1342185630U, // VMWRITE32rm
- 1279402142U, // VMWRITE32rr
- 1409294504U, // VMWRITE64rm
- 1279402152U, // VMWRITE64rr
- 8370U, // VMXOFF
- 1476403385U, // VMXON
+ 79700000U, // UCOM_Fr
+ 536879143U, // UNPCKHPDrm
+ 205660199U, // UNPCKHPDrr
+ 536879153U, // UNPCKHPSrm
+ 205660209U, // UNPCKHPSrr
+ 536879163U, // UNPCKLPDrm
+ 205660219U, // UNPCKLPDrr
+ 536879173U, // UNPCKLPSrm
+ 205660229U, // UNPCKLPSrr
+ 70459471U, // VASTART_SAVE_XMM_REGS
+ 872423527U, // VERRm
+ 79700071U, // VERRr
+ 872423533U, // VERWm
+ 79700077U, // VERWr
+ 8307U, // VMCALL
+ 1476403322U, // VMCLEARm
+ 8323U, // VMLAUNCH
+ 1476403340U, // VMPTRLDm
+ 1476403349U, // VMPTRSTm
+ 136585374U, // VMREAD32rm
+ 1279402142U, // VMREAD32rr
+ 136716455U, // VMREAD64rm
+ 1279402151U, // VMREAD64rr
+ 8368U, // VMRESUME
+ 1342185657U, // VMWRITE32rm
+ 1279402169U, // VMWRITE32rr
+ 1409294531U, // VMWRITE64rm
+ 1279402179U, // VMWRITE64rr
+ 8397U, // VMXOFF
+ 1476403412U, // VMXON
0U, // V_SET0
0U, // V_SETALLONES
- 8384U, // WAIT
- 8389U, // WBINVD
+ 8411U, // WAIT
+ 8416U, // WBINVD
1476396120U, // WINCALL64m
1556087918U, // WINCALL64pcrel32
79692888U, // WINCALL64r
- 8396U, // WRMSR
- 136323282U, // XADD16rm
- 1279402194U, // XADD16rr
- 136585433U, // XADD32rm
- 1279402201U, // XADD32rr
- 136716512U, // XADD64rm
- 1279402208U, // XADD64rr
- 136847591U, // XADD8rm
- 1279402215U, // XADD8rr
- 67117294U, // XCHG16ar
- 1317150958U, // XCHG16rm
- 1340088558U, // XCHG16rr
- 73408757U, // XCHG32ar
- 1319248117U, // XCHG32rm
- 1340088565U, // XCHG32rr
- 75505916U, // XCHG64ar
- 1321345276U, // XCHG64rm
- 1340088572U, // XCHG64rr
- 1323442435U, // XCHG8rm
- 1340088579U, // XCHG8rr
- 79700234U, // XCH_F
- 8464U, // XLAT
- 67117334U, // XOR16i16
- 136323350U, // XOR16mi
- 136323350U, // XOR16mi8
- 136323350U, // XOR16mr
- 205660438U, // XOR16ri
- 205660438U, // XOR16ri8
- 272769302U, // XOR16rm
- 205660438U, // XOR16rr
- 205660438U, // XOR16rr_REV
- 73408796U, // XOR32i32
- 136585500U, // XOR32mi
- 136585500U, // XOR32mi8
- 136585500U, // XOR32mr
- 205660444U, // XOR32ri
- 205660444U, // XOR32ri8
- 339878172U, // XOR32rm
- 205660444U, // XOR32rr
- 205660444U, // XOR32rr_REV
- 75505954U, // XOR64i32
- 136716578U, // XOR64mi32
- 136716578U, // XOR64mi8
- 136716578U, // XOR64mr
- 205660450U, // XOR64ri32
- 205660450U, // XOR64ri8
- 406987042U, // XOR64rm
- 205660450U, // XOR64rr
- 205660450U, // XOR64rr_REV
- 77603112U, // XOR8i8
- 136847656U, // XOR8mi
- 136847656U, // XOR8mr
- 205660456U, // XOR8ri
- 474095912U, // XOR8rm
- 205660456U, // XOR8rr
- 205660456U, // XOR8rr_REV
+ 8423U, // WRMSR
+ 136323309U, // XADD16rm
+ 1279402221U, // XADD16rr
+ 136585460U, // XADD32rm
+ 1279402228U, // XADD32rr
+ 136716539U, // XADD64rm
+ 1279402235U, // XADD64rr
+ 136847618U, // XADD8rm
+ 1279402242U, // XADD8rr
+ 67117321U, // XCHG16ar
+ 1317150985U, // XCHG16rm
+ 1340088585U, // XCHG16rr
+ 73408784U, // XCHG32ar
+ 1319248144U, // XCHG32rm
+ 1340088592U, // XCHG32rr
+ 75505943U, // XCHG64ar
+ 1321345303U, // XCHG64rm
+ 1340088599U, // XCHG64rr
+ 1323442462U, // XCHG8rm
+ 1340088606U, // XCHG8rr
+ 79700261U, // XCH_F
+ 8491U, // XLAT
+ 67117361U, // XOR16i16
+ 136323377U, // XOR16mi
+ 136323377U, // XOR16mi8
+ 136323377U, // XOR16mr
+ 205660465U, // XOR16ri
+ 205660465U, // XOR16ri8
+ 272769329U, // XOR16rm
+ 205660465U, // XOR16rr
+ 205660465U, // XOR16rr_REV
+ 73408823U, // XOR32i32
+ 136585527U, // XOR32mi
+ 136585527U, // XOR32mi8
+ 136585527U, // XOR32mr
+ 205660471U, // XOR32ri
+ 205660471U, // XOR32ri8
+ 339878199U, // XOR32rm
+ 205660471U, // XOR32rr
+ 205660471U, // XOR32rr_REV
+ 75505981U, // XOR64i32
+ 136716605U, // XOR64mi32
+ 136716605U, // XOR64mi8
+ 136716605U, // XOR64mr
+ 205660477U, // XOR64ri32
+ 205660477U, // XOR64ri8
+ 406987069U, // XOR64rm
+ 205660477U, // XOR64rr
+ 205660477U, // XOR64rr_REV
+ 77603139U, // XOR8i8
+ 136847683U, // XOR8mi
+ 136847683U, // XOR8mr
+ 205660483U, // XOR8ri
+ 474095939U, // XOR8rm
+ 205660483U, // XOR8rr
+ 205660483U, // XOR8rr_REV
536874124U, // XORPDrm
205655180U, // XORPDrr
536874131U, // XORPSrm
@@ -2626,90 +2627,90 @@ void X86ATTInstPrinter::printInstruction(const MachineInstr *MI) {
"t\t\000lslw\t\000lsll\t\000lslq\t\000lssw\t\000lssl\t\000lssq\t\000ltrw"
"\t\000lock\n\txaddw\t\000lock\n\txaddl\t\000lock\n\txadd\t\000lock\n\tx"
"addb\t\000maskmovdqu\t\000maxpd\t\000maxps\t\000maxsd\t\000maxss\t\000m"
- "fence\000minpd\t\000minps\t\000minsd\t\000minss\t\000emms\000femms\000m"
- "askmovq\t\000movd\t\000movdq2q\t\000movntq\t\000movq2dq\t\000movq\t\000"
- "packssdw\t\000packsswb\t\000packuswb\t\000paddb\t\000paddd\t\000paddq\t"
- "\000paddsb\t\000paddsw\t\000paddusb\t\000paddusw\t\000paddw\t\000pandn\t"
- "\000pand\t\000pavgb\t\000pavgw\t\000pcmpeqb\t\000pcmpeqd\t\000pcmpeqw\t"
- "\000pcmpgtb\t\000pcmpgtd\t\000pcmpgtw\t\000pextrw\t\000pinsrw\t\000pmad"
- "dwd\t\000pmaxsw\t\000pmaxub\t\000pminsw\t\000pminub\t\000pmovmskb\t\000"
- "pmulhuw\t\000pmulhw\t\000pmullw\t\000pmuludq\t\000por\t\000psadbw\t\000"
- "pshufw\t\000pslld\t\000psllq\t\000psllw\t\000psrad\t\000psraw\t\000psrl"
- "d\t\000psrlq\t\000psrlw\t\000psubb\t\000psubd\t\000psubq\t\000psubsb\t\000"
- "psubsw\t\000psubusb\t\000psubusw\t\000psubw\t\000punpckhbw\t\000punpckh"
- "dq\t\000punpckhwd\t\000punpcklbw\t\000punpckldq\t\000punpcklwd\t\000pxo"
- "r\t\000monitor\000movw\t%ax, \000movw\t\000movl\t%eax, \000movl\t\000mo"
- "vq\t%fs:\000movq\t%gs:\000movq\t%rax, \000movabsq\t\000movb\t%al, \000m"
- "ovb\t\000movddup\t\000movdqa\t\000movdqu\t\000movhlps\t\000movhpd\t\000"
- "movhps\t\000movlhps\t\000movlpd\t\000movlps\t\000movmskpd\t\000movmskps"
- "\t\000movntdqa\t\000movntdq\t\000movnti\t\000movntpd\t\000movntps\t\000"
- "movsb\000movsl\000movsd\t\000movshdup\t\000movsldup\t\000movss\t\000mov"
- "sw\000movsbw\t\000movswl\t\000movsbl\t\000movswq\t\000movslq\t\000movsb"
- "q\t\000movupd\t\000movups\t\000movzbw\t\000movzbl\t\000movzwl\t\000movz"
- "wq\t\000movzbq\t\000mpsadbw\t\000mulw\t\000mull\t\000mulq\t\000mulb\t\000"
- "mulpd\t\000mulps\t\000mulsd\t\000mulss\t\000fmuls\t\000fmull\t\000fimul"
- "s\t\000fimull\t\000fmulp\t\000fmul\t\000fmul\t%st(0), \000mwait\000negw"
- "\t\000negl\t\000negq\t\000negb\t\000nop\000nopl\t\000nopw\t\000notw\t\000"
- "notl\t\000notq\t\000notb\t\000orw\t\000orl\t\000orq\t\000orb\t\000outw\t"
- "%ax, \000outw\t%ax, %dx\000outl\t%eax, \000outl\t%eax, %dx\000outb\t%al"
- ", \000outb\t%al, %dx\000outsb\000outsl\000outsw\000pabsb\t\000pabsd\t\000"
- "pabsw\t\000packusdw\t\000palignr\t\000pblendvb\t%xmm0, \000pblendw\t\000"
- "pcmpeqq\t\000pcmpestri\t\000#PCMPESTRM128rm PSEUDO!\000#PCMPESTRM128rr "
- "PSEUDO!\000pcmpestrm\t\000pcmpgtq\t\000pcmpistri\t\000#PCMPISTRM128rm P"
- "SEUDO!\000#PCMPISTRM128rr PSEUDO!\000pcmpistrm\t\000pextrb\t\000pextrd\t"
- "\000pextrq\t\000phaddd\t\000phaddsw\t\000phaddw\t\000phminposuw\t\000ph"
- "subd\t\000phsubsw\t\000phsubw\t\000pinsrb\t\000pinsrd\t\000pinsrq\t\000"
- "pmaddubsw\t\000pmaxsb\t\000pmaxsd\t\000pmaxud\t\000pmaxuw\t\000pminsb\t"
- "\000pminsd\t\000pminud\t\000pminuw\t\000pmovsxbd\t\000pmovsxbq\t\000pmo"
- "vsxbw\t\000pmovsxdq\t\000pmovsxwd\t\000pmovsxwq\t\000pmovzxbd\t\000pmov"
- "zxbq\t\000pmovzxbw\t\000pmovzxdq\t\000pmovzxwd\t\000pmovzxwq\t\000pmuld"
- "q\t\000pmulhrsw\t\000pmulld\t\000popw\t\000popl\t\000popq\t\000popcntw\t"
- "\000popcntl\t\000popcntq\t\000popfw\000popfl\000popfq\000popw\t%fs\000p"
- "opl\t%fs\000popq\t%fs\000popw\t%gs\000popl\t%gs\000popq\t%gs\000prefetc"
- "hnta\t\000prefetcht0\t\000prefetcht1\t\000prefetcht2\t\000pshufb\t\000p"
- "shufd\t\000pshufhw\t\000pshuflw\t\000psignb\t\000psignd\t\000psignw\t\000"
- "pslldq\t\000psrldq\t\000ptest \t\000punpckhqdq\t\000punpcklqdq\t\000pus"
- "hw\t\000pushl\t\000pushq\t\000pushfw\000pushfl\000pushfq\000pushw\t%fs\000"
- "pushl\t%fs\000pushq\t%fs\000pushw\t%gs\000pushl\t%gs\000pushq\t%gs\000r"
- "clw\t1, \000rclw\t%cl, \000rclw\t\000rcll\t1, \000rcll\t%cl, \000rcll\t"
- "\000rclq\t1, \000rclq\t%cl, \000rclq\t\000rclb\t1, \000rclb\t%cl, \000r"
- "clb\t\000rcpps\t\000rcpss\t\000rcrw\t1, \000rcrw\t%cl, \000rcrw\t\000rc"
- "rl\t1, \000rcrl\t%cl, \000rcrl\t\000rcrq\t1, \000rcrq\t%cl, \000rcrq\t\000"
- "rcrb\t1, \000rcrb\t%cl, \000rcrb\t\000rdmsr\000rdpmc\000rdtsc\000rdtscp"
- "\000repne\000rep;movsb\000rep;movsl\000rep;movsq\000rep;movsw\000rep\000"
- "rep;stosb\000rep;stosl\000rep;stosq\000rep;stosw\000ret\000ret\t\000rol"
- "w\t\000rolw\t%cl, \000roll\t\000roll\t%cl, \000rolq\t\000rolq\t%cl, \000"
- "rolb\t\000rolb\t%cl, \000rorw\t\000rorw\t%cl, \000rorl\t\000rorl\t%cl, "
- "\000rorq\t\000rorq\t%cl, \000rorb\t\000rorb\t%cl, \000roundpd\t\000roun"
- "dps\t\000roundsd\t\000roundss\t\000rsm\000rsqrtps\t\000rsqrtss\t\000sah"
- "f\000sarw\t\000sarw\t%cl, \000sarl\t\000sarl\t%cl, \000sarq\t\000sarq\t"
- "%cl, \000sarb\t\000sarb\t%cl, \000sbbw\t\000sbbl\t\000sbbq\t\000sbbb\t\000"
- "scasw\000scasl\000scasq\000scasb\000setae\t\000seta\t\000setbe\t\000set"
- "b\t\000sete\t\000setge\t\000setg\t\000setle\t\000setl\t\000setne\t\000s"
- "etno\t\000setnp\t\000setns\t\000seto\t\000setp\t\000sets\t\000sfence\000"
- "sgdt\t\000shlw\t\000shlw\t%cl, \000shll\t\000shll\t%cl, \000shlq\t\000s"
- "hlq\t%cl, \000shlb\t\000shlb\t%cl, \000shldw\t%cl, \000shldw\t\000shldl"
- "\t%cl, \000shldl\t\000shldq\t%cl, \000shldq\t\000shrw\t\000shrw\t%cl, \000"
- "shrl\t\000shrl\t%cl, \000shrq\t\000shrq\t%cl, \000shrb\t\000shrb\t%cl, "
- "\000shrdw\t%cl, \000shrdw\t\000shrdl\t%cl, \000shrdl\t\000shrdq\t%cl, \000"
- "shrdq\t\000shufpd\t\000shufps\t\000sidt\t\000fsin\000sldtw\t\000sldtq\t"
- "\000smsww\t\000smswl\t\000smswq\t\000sqrtpd\t\000sqrtps\t\000sqrtsd\t\000"
- "sqrtss\t\000fsqrt\000ss\000stc\000std\000sti\000stmxcsr\t\000stosb\000s"
- "tosl\000stosw\000strw\t\000fsts\t\000fstl\t\000fstps\t\000fstpl\t\000fs"
- "tpt\t\000fstp\t\000fst\t\000subw\t\000subl\t\000subq\t\000subb\t\000sub"
- "pd\t\000subps\t\000fsubrs\t\000fsubrl\t\000fisubrs\t\000fisubrl\t\000fs"
- "ubp\t\000fsubr\t\000fsub\t%st(0), \000subsd\t\000subss\t\000fsubs\t\000"
- "fsubl\t\000fisubs\t\000fisubl\t\000fsubrp\t\000fsub\t\000fsubr\t%st(0),"
- " \000swapgs\000syscall\000sysenter\000sysexit\000sysret\000jmp\t*\000#T"
- "C_RETURN \000testw\t\000testl\t\000testq\t\000testb\t\000.byte\t0x66; l"
- "eaq\t\000ud2\000ftst\000fucomip\t\000fucomi\t\000fucompp\000fucomp\t\000"
- "fucom\t\000unpckhpd\t\000unpckhps\t\000unpcklpd\t\000unpcklps\t\000#VAS"
- "TART_SAVE_XMM_REGS \000verr\t\000verw\t\000vmcall\000vmclear\t\000vmlau"
- "nch\000vmptrld\t\000vmptrst\t\000vmreadl\t\000vmreadq\t\000vmresume\000"
- "vmwritel\t\000vmwriteq\t\000vmxoff\000vmxon\t\000wait\000wbinvd\000wrms"
- "r\000xaddw\t\000xaddl\t\000xaddq\t\000xaddb\t\000xchgw\t\000xchgl\t\000"
- "xchgq\t\000xchgb\t\000fxch\t\000xlatb\000xorw\t\000xorl\t\000xorq\t\000"
- "xorb\t\000";
+ "fence\000# dynamic stack allocation\000minpd\t\000minps\t\000minsd\t\000"
+ "minss\t\000emms\000femms\000maskmovq\t\000movd\t\000movdq2q\t\000movntq"
+ "\t\000movq2dq\t\000movq\t\000packssdw\t\000packsswb\t\000packuswb\t\000"
+ "paddb\t\000paddd\t\000paddq\t\000paddsb\t\000paddsw\t\000paddusb\t\000p"
+ "addusw\t\000paddw\t\000pandn\t\000pand\t\000pavgb\t\000pavgw\t\000pcmpe"
+ "qb\t\000pcmpeqd\t\000pcmpeqw\t\000pcmpgtb\t\000pcmpgtd\t\000pcmpgtw\t\000"
+ "pextrw\t\000pinsrw\t\000pmaddwd\t\000pmaxsw\t\000pmaxub\t\000pminsw\t\000"
+ "pminub\t\000pmovmskb\t\000pmulhuw\t\000pmulhw\t\000pmullw\t\000pmuludq\t"
+ "\000por\t\000psadbw\t\000pshufw\t\000pslld\t\000psllq\t\000psllw\t\000p"
+ "srad\t\000psraw\t\000psrld\t\000psrlq\t\000psrlw\t\000psubb\t\000psubd\t"
+ "\000psubq\t\000psubsb\t\000psubsw\t\000psubusb\t\000psubusw\t\000psubw\t"
+ "\000punpckhbw\t\000punpckhdq\t\000punpckhwd\t\000punpcklbw\t\000punpckl"
+ "dq\t\000punpcklwd\t\000pxor\t\000monitor\000movw\t%ax, \000movw\t\000mo"
+ "vl\t%eax, \000movl\t\000movq\t%fs:\000movq\t%gs:\000movq\t%rax, \000mov"
+ "absq\t\000movb\t%al, \000movb\t\000movddup\t\000movdqa\t\000movdqu\t\000"
+ "movhlps\t\000movhpd\t\000movhps\t\000movlhps\t\000movlpd\t\000movlps\t\000"
+ "movmskpd\t\000movmskps\t\000movntdqa\t\000movntdq\t\000movnti\t\000movn"
+ "tpd\t\000movntps\t\000movsb\000movsl\000movsd\t\000movshdup\t\000movsld"
+ "up\t\000movss\t\000movsw\000movsbw\t\000movswl\t\000movsbl\t\000movswq\t"
+ "\000movslq\t\000movsbq\t\000movupd\t\000movups\t\000movzbw\t\000movzbl\t"
+ "\000movzwl\t\000movzwq\t\000movzbq\t\000mpsadbw\t\000mulw\t\000mull\t\000"
+ "mulq\t\000mulb\t\000mulpd\t\000mulps\t\000mulsd\t\000mulss\t\000fmuls\t"
+ "\000fmull\t\000fimuls\t\000fimull\t\000fmulp\t\000fmul\t\000fmul\t%st(0"
+ "), \000mwait\000negw\t\000negl\t\000negq\t\000negb\t\000nop\000nopl\t\000"
+ "nopw\t\000notw\t\000notl\t\000notq\t\000notb\t\000orw\t\000orl\t\000orq"
+ "\t\000orb\t\000outw\t%ax, \000outw\t%ax, %dx\000outl\t%eax, \000outl\t%"
+ "eax, %dx\000outb\t%al, \000outb\t%al, %dx\000outsb\000outsl\000outsw\000"
+ "pabsb\t\000pabsd\t\000pabsw\t\000packusdw\t\000palignr\t\000pblendvb\t%"
+ "xmm0, \000pblendw\t\000pcmpeqq\t\000pcmpestri\t\000#PCMPESTRM128rm PSEU"
+ "DO!\000#PCMPESTRM128rr PSEUDO!\000pcmpestrm\t\000pcmpgtq\t\000pcmpistri"
+ "\t\000#PCMPISTRM128rm PSEUDO!\000#PCMPISTRM128rr PSEUDO!\000pcmpistrm\t"
+ "\000pextrb\t\000pextrd\t\000pextrq\t\000phaddd\t\000phaddsw\t\000phaddw"
+ "\t\000phminposuw\t\000phsubd\t\000phsubsw\t\000phsubw\t\000pinsrb\t\000"
+ "pinsrd\t\000pinsrq\t\000pmaddubsw\t\000pmaxsb\t\000pmaxsd\t\000pmaxud\t"
+ "\000pmaxuw\t\000pminsb\t\000pminsd\t\000pminud\t\000pminuw\t\000pmovsxb"
+ "d\t\000pmovsxbq\t\000pmovsxbw\t\000pmovsxdq\t\000pmovsxwd\t\000pmovsxwq"
+ "\t\000pmovzxbd\t\000pmovzxbq\t\000pmovzxbw\t\000pmovzxdq\t\000pmovzxwd\t"
+ "\000pmovzxwq\t\000pmuldq\t\000pmulhrsw\t\000pmulld\t\000popw\t\000popl\t"
+ "\000popq\t\000popcntw\t\000popcntl\t\000popcntq\t\000popfw\000popfl\000"
+ "popfq\000popw\t%fs\000popl\t%fs\000popq\t%fs\000popw\t%gs\000popl\t%gs\000"
+ "popq\t%gs\000prefetchnta\t\000prefetcht0\t\000prefetcht1\t\000prefetcht"
+ "2\t\000pshufb\t\000pshufd\t\000pshufhw\t\000pshuflw\t\000psignb\t\000ps"
+ "ignd\t\000psignw\t\000pslldq\t\000psrldq\t\000ptest \t\000punpckhqdq\t\000"
+ "punpcklqdq\t\000pushw\t\000pushl\t\000pushq\t\000pushfw\000pushfl\000pu"
+ "shfq\000pushw\t%fs\000pushl\t%fs\000pushq\t%fs\000pushw\t%gs\000pushl\t"
+ "%gs\000pushq\t%gs\000rclw\t1, \000rclw\t%cl, \000rclw\t\000rcll\t1, \000"
+ "rcll\t%cl, \000rcll\t\000rclq\t1, \000rclq\t%cl, \000rclq\t\000rclb\t1,"
+ " \000rclb\t%cl, \000rclb\t\000rcpps\t\000rcpss\t\000rcrw\t1, \000rcrw\t"
+ "%cl, \000rcrw\t\000rcrl\t1, \000rcrl\t%cl, \000rcrl\t\000rcrq\t1, \000r"
+ "crq\t%cl, \000rcrq\t\000rcrb\t1, \000rcrb\t%cl, \000rcrb\t\000rdmsr\000"
+ "rdpmc\000rdtsc\000rdtscp\000repne\000rep;movsb\000rep;movsl\000rep;movs"
+ "q\000rep;movsw\000rep\000rep;stosb\000rep;stosl\000rep;stosq\000rep;sto"
+ "sw\000ret\000ret\t\000rolw\t\000rolw\t%cl, \000roll\t\000roll\t%cl, \000"
+ "rolq\t\000rolq\t%cl, \000rolb\t\000rolb\t%cl, \000rorw\t\000rorw\t%cl, "
+ "\000rorl\t\000rorl\t%cl, \000rorq\t\000rorq\t%cl, \000rorb\t\000rorb\t%"
+ "cl, \000roundpd\t\000roundps\t\000roundsd\t\000roundss\t\000rsm\000rsqr"
+ "tps\t\000rsqrtss\t\000sahf\000sarw\t\000sarw\t%cl, \000sarl\t\000sarl\t"
+ "%cl, \000sarq\t\000sarq\t%cl, \000sarb\t\000sarb\t%cl, \000sbbw\t\000sb"
+ "bl\t\000sbbq\t\000sbbb\t\000scasw\000scasl\000scasq\000scasb\000setae\t"
+ "\000seta\t\000setbe\t\000setb\t\000sete\t\000setge\t\000setg\t\000setle"
+ "\t\000setl\t\000setne\t\000setno\t\000setnp\t\000setns\t\000seto\t\000s"
+ "etp\t\000sets\t\000sfence\000sgdt\t\000shlw\t\000shlw\t%cl, \000shll\t\000"
+ "shll\t%cl, \000shlq\t\000shlq\t%cl, \000shlb\t\000shlb\t%cl, \000shldw\t"
+ "%cl, \000shldw\t\000shldl\t%cl, \000shldl\t\000shldq\t%cl, \000shldq\t\000"
+ "shrw\t\000shrw\t%cl, \000shrl\t\000shrl\t%cl, \000shrq\t\000shrq\t%cl, "
+ "\000shrb\t\000shrb\t%cl, \000shrdw\t%cl, \000shrdw\t\000shrdl\t%cl, \000"
+ "shrdl\t\000shrdq\t%cl, \000shrdq\t\000shufpd\t\000shufps\t\000sidt\t\000"
+ "fsin\000sldtw\t\000sldtq\t\000smsww\t\000smswl\t\000smswq\t\000sqrtpd\t"
+ "\000sqrtps\t\000sqrtsd\t\000sqrtss\t\000fsqrt\000ss\000stc\000std\000st"
+ "i\000stmxcsr\t\000stosb\000stosl\000stosw\000strw\t\000fsts\t\000fstl\t"
+ "\000fstps\t\000fstpl\t\000fstpt\t\000fstp\t\000fst\t\000subw\t\000subl\t"
+ "\000subq\t\000subb\t\000subpd\t\000subps\t\000fsubrs\t\000fsubrl\t\000f"
+ "isubrs\t\000fisubrl\t\000fsubp\t\000fsubr\t\000fsub\t%st(0), \000subsd\t"
+ "\000subss\t\000fsubs\t\000fsubl\t\000fisubs\t\000fisubl\t\000fsubrp\t\000"
+ "fsub\t\000fsubr\t%st(0), \000swapgs\000syscall\000sysenter\000sysexit\000"
+ "sysret\000jmp\t*\000#TC_RETURN \000testw\t\000testl\t\000testq\t\000tes"
+ "tb\t\000.byte\t0x66; leaq\t\000ud2\000ftst\000fucomip\t\000fucomi\t\000"
+ "fucompp\000fucomp\t\000fucom\t\000unpckhpd\t\000unpckhps\t\000unpcklpd\t"
+ "\000unpcklps\t\000#VASTART_SAVE_XMM_REGS \000verr\t\000verw\t\000vmcall"
+ "\000vmclear\t\000vmlaunch\000vmptrld\t\000vmptrst\t\000vmreadl\t\000vmr"
+ "eadq\t\000vmresume\000vmwritel\t\000vmwriteq\t\000vmxoff\000vmxon\t\000"
+ "wait\000wbinvd\000wrmsr\000xaddw\t\000xaddl\t\000xaddq\t\000xaddb\t\000"
+ "xchgw\t\000xchgl\t\000xchgq\t\000xchgb\t\000fxch\t\000xlatb\000xorw\t\000"
+ "xorl\t\000xorq\t\000xorb\t\000";
O << "\t";
@@ -3304,7 +3305,7 @@ const char *X86ATTInstPrinter::getRegisterName(unsigned RegNo) {
/// from the instruction set description. This returns the enum name of the
/// specified instruction.
const char *X86ATTInstPrinter::getInstructionName(unsigned Opcode) {
- assert(Opcode < 2524 && "Invalid instruction number!");
+ assert(Opcode < 2525 && "Invalid instruction number!");
static const unsigned InstAsmOffset[] = {
0, 4, 14, 24, 33, 42, 47, 62, 76, 89, 103, 120, 130, 136,
@@ -3384,110 +3385,110 @@ const char *X86ATTInstPrinter::getInstructionName(unsigned Opcode) {
10305, 10317, 10329, 10335, 10341, 10347, 10353, 10358, 10364, 10371, 10376, 10382, 10390, 10398,
10406, 10414, 10422, 10430, 10438, 10446, 10454, 10459, 10464, 10472, 10480, 10488, 10495, 10506,
10519, 10527, 10539, 10547, 10559, 10567, 10579, 10587, 10599, 10607, 10619, 10627, 10639, 10647,
- 10659, 10667, 10679, 10686, 10694, 10706, 10714, 10726, 10734, 10746, 10754, 10766, 10774, 10786,
- 10794, 10806, 10814, 10826, 10834, 10846, 10861, 10876, 10891, 10906, 10921, 10936, 10951, 10966,
- 10982, 10998, 11014, 11030, 11039, 11049, 11062, 11077, 11096, 11110, 11123, 11136, 11149, 11166,
- 11183, 11197, 11210, 11224, 11240, 11254, 11267, 11280, 11293, 11310, 11327, 11342, 11357, 11372,
- 11387, 11402, 11417, 11429, 11441, 11453, 11465, 11477, 11489, 11502, 11515, 11528, 11541, 11555,
- 11569, 11583, 11597, 11609, 11621, 11633, 11645, 11656, 11667, 11679, 11691, 11703, 11715, 11729,
- 11743, 11757, 11771, 11785, 11799, 11813, 11827, 11841, 11855, 11869, 11883, 11896, 11910, 11924,
- 11938, 11952, 11965, 11978, 11991, 12004, 12017, 12030, 12043, 12056, 12071, 12085, 12099, 12112,
- 12125, 12138, 12151, 12165, 12179, 12189, 12199, 12212, 12225, 12238, 12251, 12263, 12275, 12287,
- 12299, 12311, 12323, 12335, 12347, 12359, 12371, 12383, 12395, 12407, 12419, 12431, 12443, 12455,
- 12467, 12479, 12491, 12503, 12515, 12527, 12539, 12551, 12563, 12575, 12587, 12599, 12611, 12624,
- 12637, 12650, 12663, 12677, 12691, 12705, 12719, 12731, 12743, 12759, 12775, 12791, 12807, 12823,
- 12839, 12855, 12871, 12887, 12903, 12919, 12935, 12946, 12957, 12968, 12985, 12993, 13003, 13011,
- 13019, 13027, 13037, 13045, 13053, 13061, 13069, 13081, 13089, 13097, 13105, 13115, 13123, 13131,
- 13139, 13147, 13157, 13165, 13173, 13181, 13189, 13197, 13205, 13217, 13227, 13237, 13247, 13256,
- 13264, 13272, 13282, 13290, 13298, 13308, 13317, 13325, 13333, 13341, 13349, 13359, 13372, 13380,
- 13388, 13400, 13408, 13416, 13424, 13437, 13449, 13461, 13469, 13476, 13483, 13496, 13504, 13511,
- 13518, 13525, 13538, 13545, 13558, 13569, 13578, 13587, 13596, 13605, 13614, 13623, 13633, 13643,
- 13655, 13667, 13678, 13689, 13698, 13707, 13716, 13725, 13738, 13747, 13760, 13770, 13779, 13788,
- 13797, 13806, 13816, 13825, 13834, 13843, 13852, 13863, 13874, 13885, 13896, 13909, 13919, 13933,
- 13945, 13954, 13967, 13977, 13991, 14001, 14015, 14024, 14036, 14048, 14060, 14073, 14085, 14094,
- 14100, 14106, 14114, 14122, 14130, 14142, 14154, 14165, 14176, 14187, 14198, 14209, 14220, 14228,
- 14236, 14244, 14250, 14261, 14273, 14284, 14296, 14308, 14319, 14331, 14342, 14354, 14366, 14377,
- 14389, 14401, 14412, 14421, 14434, 14443, 14456, 14465, 14474, 14487, 14496, 14509, 14518, 14531,
- 14544, 14560, 14576, 14589, 14602, 14613, 14625, 14636, 14648, 14665, 14682, 14694, 14705, 14717,
- 14728, 14740, 14754, 14766, 14777, 14790, 14802, 14816, 14828, 14839, 14852, 14863, 14874, 14885,
- 14896, 14907, 14918, 14929, 14940, 14951, 14962, 14973, 14980, 14987, 14994, 15001, 15008, 15015,
- 15021, 15027, 15035, 15043, 15051, 15059, 15067, 15079, 15087, 15099, 15107, 15119, 15127, 15139,
- 15148, 15157, 15167, 15177, 15188, 15198, 15207, 15217, 15226, 15236, 15248, 15257, 15269, 15281,
- 15294, 15307, 15320, 15333, 15346, 15359, 15369, 15375, 15382, 15389, 15396, 15403, 15410, 15417,
- 15423, 15429, 15434, 15440, 15446, 15453, 15460, 15467, 15474, 15481, 15488, 15494, 15500, 15508,
- 15515, 15523, 15530, 15537, 15545, 15552, 15559, 15570, 15578, 15585, 15593, 15600, 15607, 15615,
- 15622, 15629, 15640, 15648, 15657, 15665, 15672, 15681, 15689, 15696, 15703, 15714, 15720, 15726,
- 15732, 15738, 15744, 15750, 15760, 15767, 15774, 15781, 15788, 15796, 15804, 15812, 15820, 15827,
- 15834, 15840, 15846, 15852, 15863, 15873, 15884, 15894, 15905, 15915, 15926, 15936, 15947, 15957,
- 15968, 15978, 15989, 16000, 16011, 16022, 16033, 16044, 16055, 16066, 16074, 16082, 16090, 16098,
- 16106, 16114, 16123, 16132, 16141, 16150, 16160, 16170, 16180, 16190, 16198, 16206, 16219, 16232,
- 16244, 16256, 16264, 16272, 16279, 16286, 16294, 16302, 16310, 16318, 16330, 16342, 16353, 16364,
- 16374, 16384, 16394, 16404, 16414, 16424, 16434, 16444, 16457, 16470, 16483, 16496, 16509, 16522,
- 16535, 16548, 16561, 16574, 16586, 16598, 16614, 16630, 16645, 16660, 16670, 16680, 16690, 16700,
- 16710, 16720, 16730, 16740, 16753, 16766, 16779, 16792, 16805, 16818, 16831, 16844, 16857, 16870,
- 16882, 16894, 16910, 16926, 16941, 16956, 16965, 16974, 16983, 16992, 17001, 17010, 17019, 17028,
- 17040, 17051, 17063, 17074, 17087, 17099, 17112, 17124, 17136, 17147, 17159, 17170, 17186, 17202,
- 17214, 17225, 17237, 17248, 17261, 17273, 17286, 17298, 17310, 17321, 17333, 17344, 17353, 17362,
- 17371, 17380, 17389, 17398, 17408, 17418, 17433, 17447, 17462, 17476, 17486, 17496, 17505, 17514,
- 17523, 17532, 17541, 17550, 17559, 17568, 17577, 17586, 17595, 17604, 17613, 17622, 17631, 17640,
- 17649, 17658, 17667, 17676, 17685, 17694, 17703, 17712, 17723, 17734, 17745, 17756, 17767, 17778,
- 17789, 17800, 17811, 17822, 17833, 17844, 17855, 17866, 17877, 17888, 17899, 17910, 17921, 17932,
- 17943, 17954, 17965, 17976, 17987, 17996, 18005, 18019, 18032, 18046, 18059, 18069, 18079, 18088,
- 18097, 18106, 18119, 18128, 18141, 18150, 18159, 18169, 18179, 18186, 18195, 18204, 18211, 18220,
- 18229, 18236, 18245, 18254, 18265, 18276, 18287, 18298, 18309, 18320, 18325, 18331, 18337, 18345,
- 18353, 18361, 18369, 18377, 18385, 18391, 18397, 18409, 18420, 18431, 18442, 18451, 18460, 18472,
- 18483, 18495, 18506, 18515, 18524, 18534, 18544, 18554, 18564, 18576, 18587, 18599, 18610, 18622,
- 18633, 18645, 18656, 18668, 18679, 18691, 18702, 18711, 18719, 18727, 18735, 18743, 18751, 18759,
- 18767, 18775, 18783, 18791, 18799, 18807, 18815, 18823, 18831, 18840, 18848, 18856, 18864, 18872,
- 18880, 18888, 18896, 18904, 18912, 18920, 18928, 18936, 18944, 18952, 18960, 18969, 18978, 18987,
- 18996, 19006, 19016, 19026, 19036, 19044, 19052, 19060, 19068, 19080, 19092, 19104, 19116, 19129,
- 19142, 19154, 19166, 19178, 19190, 19202, 19214, 19227, 19240, 19252, 19264, 19272, 19282, 19292,
- 19302, 19312, 19321, 19329, 19339, 19349, 19359, 19369, 19378, 19386, 19396, 19406, 19412, 19419,
- 19428, 19437, 19446, 19455, 19464, 19473, 19482, 19489, 19496, 19504, 19513, 19521, 19529, 19538,
- 19546, 19554, 19563, 19571, 19579, 19588, 19596, 19604, 19613, 19621, 19629, 19638, 19646, 19653,
- 19661, 19668, 19675, 19683, 19690, 19697, 19708, 19715, 19726, 19733, 19744, 19751, 19762, 19770,
- 19779, 19787, 19795, 19804, 19812, 19820, 19829, 19837, 19845, 19854, 19862, 19870, 19879, 19887,
- 19895, 19904, 19912, 19919, 19927, 19934, 19941, 19949, 19956, 19962, 19968, 19974, 19981, 19994,
- 20004, 20014, 20024, 20034, 20045, 20055, 20065, 20075, 20085, 20089, 20094, 20102, 20111, 20119,
- 20127, 20136, 20144, 20152, 20161, 20169, 20177, 20186, 20194, 20202, 20211, 20219, 20227, 20236,
- 20244, 20251, 20259, 20266, 20273, 20281, 20288, 20296, 20305, 20313, 20321, 20330, 20338, 20346,
- 20355, 20363, 20371, 20380, 20388, 20396, 20405, 20413, 20421, 20430, 20438, 20445, 20453, 20460,
- 20467, 20475, 20482, 20495, 20508, 20521, 20534, 20547, 20560, 20573, 20586, 20590, 20599, 20612,
- 20621, 20634, 20643, 20656, 20665, 20678, 20683, 20691, 20700, 20708, 20716, 20725, 20733, 20741,
- 20750, 20758, 20766, 20775, 20783, 20791, 20800, 20808, 20816, 20825, 20833, 20840, 20848, 20855,
- 20862, 20870, 20877, 20886, 20894, 20903, 20911, 20919, 20928, 20936, 20944, 20956, 20965, 20973,
- 20982, 20990, 20998, 21007, 21015, 21023, 21035, 21044, 21054, 21063, 21071, 21081, 21090, 21098,
- 21106, 21118, 21125, 21132, 21139, 21146, 21153, 21160, 21171, 21178, 21185, 21192, 21198, 21205,
- 21212, 21218, 21224, 21231, 21238, 21248, 21258, 21268, 21277, 21283, 21289, 21295, 21301, 21308,
- 21315, 21321, 21327, 21334, 21341, 21347, 21353, 21360, 21367, 21374, 21381, 21388, 21395, 21402,
- 21409, 21415, 21421, 21427, 21433, 21439, 21445, 21452, 21458, 21466, 21475, 21483, 21491, 21500,
- 21508, 21516, 21525, 21533, 21541, 21550, 21558, 21566, 21575, 21583, 21591, 21600, 21608, 21615,
- 21623, 21630, 21637, 21645, 21652, 21663, 21674, 21685, 21696, 21707, 21718, 21729, 21740, 21751,
- 21762, 21773, 21784, 21792, 21801, 21809, 21817, 21826, 21834, 21842, 21851, 21859, 21867, 21876,
- 21884, 21892, 21901, 21909, 21917, 21926, 21934, 21941, 21949, 21956, 21963, 21971, 21978, 21989,
- 22000, 22011, 22022, 22033, 22044, 22055, 22066, 22077, 22088, 22099, 22110, 22120, 22130, 22140,
- 22150, 22156, 22162, 22171, 22180, 22189, 22197, 22205, 22213, 22221, 22229, 22237, 22245, 22253,
- 22261, 22273, 22281, 22293, 22301, 22313, 22321, 22333, 22341, 22353, 22361, 22373, 22381, 22393,
- 22401, 22413, 22420, 22430, 22440, 22450, 22460, 22464, 22468, 22472, 22480, 22486, 22492, 22498,
- 22503, 22508, 22516, 22524, 22533, 22542, 22551, 22559, 22568, 22577, 22588, 22599, 22610, 22620,
- 22630, 22642, 22652, 22664, 22676, 22683, 22692, 22700, 22709, 22717, 22725, 22734, 22742, 22750,
- 22762, 22771, 22779, 22788, 22796, 22804, 22813, 22821, 22829, 22841, 22850, 22860, 22869, 22877,
- 22887, 22896, 22904, 22912, 22924, 22931, 22938, 22945, 22952, 22959, 22966, 22977, 22985, 22993,
- 23001, 23009, 23019, 23029, 23040, 23051, 23063, 23074, 23085, 23096, 23109, 23122, 23135, 23149,
- 23163, 23177, 23191, 23205, 23219, 23230, 23238, 23250, 23258, 23270, 23278, 23290, 23298, 23310,
- 23319, 23328, 23338, 23348, 23359, 23369, 23378, 23388, 23397, 23407, 23419, 23428, 23440, 23452,
- 23465, 23478, 23491, 23504, 23517, 23530, 23540, 23547, 23555, 23564, 23572, 23582, 23589, 23598,
- 23607, 23616, 23627, 23638, 23651, 23662, 23675, 23685, 23694, 23703, 23712, 23721, 23731, 23740,
- 23749, 23758, 23767, 23777, 23788, 23799, 23808, 23817, 23825, 23833, 23841, 23849, 23857, 23868,
- 23879, 23884, 23890, 23899, 23908, 23917, 23927, 23937, 23947, 23957, 23967, 23976, 23986, 23995,
- 24007, 24019, 24031, 24042, 24053, 24064, 24072, 24083, 24094, 24105, 24116, 24127, 24138, 24149,
- 24160, 24182, 24188, 24194, 24200, 24206, 24213, 24222, 24231, 24240, 24249, 24260, 24271, 24282,
- 24293, 24302, 24314, 24326, 24338, 24350, 24357, 24363, 24370, 24383, 24388, 24395, 24406, 24423,
- 24434, 24440, 24449, 24458, 24467, 24476, 24485, 24494, 24502, 24510, 24519, 24528, 24537, 24546,
- 24555, 24564, 24573, 24582, 24591, 24599, 24607, 24613, 24618, 24627, 24635, 24644, 24652, 24660,
- 24669, 24677, 24685, 24697, 24706, 24714, 24723, 24731, 24739, 24748, 24756, 24764, 24776, 24785,
- 24795, 24804, 24812, 24822, 24831, 24839, 24847, 24859, 24866, 24873, 24880, 24887, 24894, 24901,
- 24912, 24920, 24928, 24936, 0
+ 10659, 10667, 10679, 10686, 10699, 10707, 10719, 10727, 10739, 10747, 10759, 10767, 10779, 10787,
+ 10799, 10807, 10819, 10827, 10839, 10847, 10859, 10874, 10889, 10904, 10919, 10934, 10949, 10964,
+ 10979, 10995, 11011, 11027, 11043, 11052, 11062, 11075, 11090, 11109, 11123, 11136, 11149, 11162,
+ 11179, 11196, 11210, 11223, 11237, 11253, 11267, 11280, 11293, 11306, 11323, 11340, 11355, 11370,
+ 11385, 11400, 11415, 11430, 11442, 11454, 11466, 11478, 11490, 11502, 11515, 11528, 11541, 11554,
+ 11568, 11582, 11596, 11610, 11622, 11634, 11646, 11658, 11669, 11680, 11692, 11704, 11716, 11728,
+ 11742, 11756, 11770, 11784, 11798, 11812, 11826, 11840, 11854, 11868, 11882, 11896, 11909, 11923,
+ 11937, 11951, 11965, 11978, 11991, 12004, 12017, 12030, 12043, 12056, 12069, 12084, 12098, 12112,
+ 12125, 12138, 12151, 12164, 12178, 12192, 12202, 12212, 12225, 12238, 12251, 12264, 12276, 12288,
+ 12300, 12312, 12324, 12336, 12348, 12360, 12372, 12384, 12396, 12408, 12420, 12432, 12444, 12456,
+ 12468, 12480, 12492, 12504, 12516, 12528, 12540, 12552, 12564, 12576, 12588, 12600, 12612, 12624,
+ 12637, 12650, 12663, 12676, 12690, 12704, 12718, 12732, 12744, 12756, 12772, 12788, 12804, 12820,
+ 12836, 12852, 12868, 12884, 12900, 12916, 12932, 12948, 12959, 12970, 12981, 12998, 13006, 13016,
+ 13024, 13032, 13040, 13050, 13058, 13066, 13074, 13082, 13094, 13102, 13110, 13118, 13128, 13136,
+ 13144, 13152, 13160, 13170, 13178, 13186, 13194, 13202, 13210, 13218, 13230, 13240, 13250, 13260,
+ 13269, 13277, 13285, 13295, 13303, 13311, 13321, 13330, 13338, 13346, 13354, 13362, 13372, 13385,
+ 13393, 13401, 13413, 13421, 13429, 13437, 13450, 13462, 13474, 13482, 13489, 13496, 13509, 13517,
+ 13524, 13531, 13538, 13551, 13558, 13571, 13582, 13591, 13600, 13609, 13618, 13627, 13636, 13646,
+ 13656, 13668, 13680, 13691, 13702, 13711, 13720, 13729, 13738, 13751, 13760, 13773, 13783, 13792,
+ 13801, 13810, 13819, 13829, 13838, 13847, 13856, 13865, 13876, 13887, 13898, 13909, 13922, 13932,
+ 13946, 13958, 13967, 13980, 13990, 14004, 14014, 14028, 14037, 14049, 14061, 14073, 14086, 14098,
+ 14107, 14113, 14119, 14127, 14135, 14143, 14155, 14167, 14178, 14189, 14200, 14211, 14222, 14233,
+ 14241, 14249, 14257, 14263, 14274, 14286, 14297, 14309, 14321, 14332, 14344, 14355, 14367, 14379,
+ 14390, 14402, 14414, 14425, 14434, 14447, 14456, 14469, 14478, 14487, 14500, 14509, 14522, 14531,
+ 14544, 14557, 14573, 14589, 14602, 14615, 14626, 14638, 14649, 14661, 14678, 14695, 14707, 14718,
+ 14730, 14741, 14753, 14767, 14779, 14790, 14803, 14815, 14829, 14841, 14852, 14865, 14876, 14887,
+ 14898, 14909, 14920, 14931, 14942, 14953, 14964, 14975, 14986, 14993, 15000, 15007, 15014, 15021,
+ 15028, 15034, 15040, 15048, 15056, 15064, 15072, 15080, 15092, 15100, 15112, 15120, 15132, 15140,
+ 15152, 15161, 15170, 15180, 15190, 15201, 15211, 15220, 15230, 15239, 15249, 15261, 15270, 15282,
+ 15294, 15307, 15320, 15333, 15346, 15359, 15372, 15382, 15388, 15395, 15402, 15409, 15416, 15423,
+ 15430, 15436, 15442, 15447, 15453, 15459, 15466, 15473, 15480, 15487, 15494, 15501, 15507, 15513,
+ 15521, 15528, 15536, 15543, 15550, 15558, 15565, 15572, 15583, 15591, 15598, 15606, 15613, 15620,
+ 15628, 15635, 15642, 15653, 15661, 15670, 15678, 15685, 15694, 15702, 15709, 15716, 15727, 15733,
+ 15739, 15745, 15751, 15757, 15763, 15773, 15780, 15787, 15794, 15801, 15809, 15817, 15825, 15833,
+ 15840, 15847, 15853, 15859, 15865, 15876, 15886, 15897, 15907, 15918, 15928, 15939, 15949, 15960,
+ 15970, 15981, 15991, 16002, 16013, 16024, 16035, 16046, 16057, 16068, 16079, 16087, 16095, 16103,
+ 16111, 16119, 16127, 16136, 16145, 16154, 16163, 16173, 16183, 16193, 16203, 16211, 16219, 16232,
+ 16245, 16257, 16269, 16277, 16285, 16292, 16299, 16307, 16315, 16323, 16331, 16343, 16355, 16366,
+ 16377, 16387, 16397, 16407, 16417, 16427, 16437, 16447, 16457, 16470, 16483, 16496, 16509, 16522,
+ 16535, 16548, 16561, 16574, 16587, 16599, 16611, 16627, 16643, 16658, 16673, 16683, 16693, 16703,
+ 16713, 16723, 16733, 16743, 16753, 16766, 16779, 16792, 16805, 16818, 16831, 16844, 16857, 16870,
+ 16883, 16895, 16907, 16923, 16939, 16954, 16969, 16978, 16987, 16996, 17005, 17014, 17023, 17032,
+ 17041, 17053, 17064, 17076, 17087, 17100, 17112, 17125, 17137, 17149, 17160, 17172, 17183, 17199,
+ 17215, 17227, 17238, 17250, 17261, 17274, 17286, 17299, 17311, 17323, 17334, 17346, 17357, 17366,
+ 17375, 17384, 17393, 17402, 17411, 17421, 17431, 17446, 17460, 17475, 17489, 17499, 17509, 17518,
+ 17527, 17536, 17545, 17554, 17563, 17572, 17581, 17590, 17599, 17608, 17617, 17626, 17635, 17644,
+ 17653, 17662, 17671, 17680, 17689, 17698, 17707, 17716, 17725, 17736, 17747, 17758, 17769, 17780,
+ 17791, 17802, 17813, 17824, 17835, 17846, 17857, 17868, 17879, 17890, 17901, 17912, 17923, 17934,
+ 17945, 17956, 17967, 17978, 17989, 18000, 18009, 18018, 18032, 18045, 18059, 18072, 18082, 18092,
+ 18101, 18110, 18119, 18132, 18141, 18154, 18163, 18172, 18182, 18192, 18199, 18208, 18217, 18224,
+ 18233, 18242, 18249, 18258, 18267, 18278, 18289, 18300, 18311, 18322, 18333, 18338, 18344, 18350,
+ 18358, 18366, 18374, 18382, 18390, 18398, 18404, 18410, 18422, 18433, 18444, 18455, 18464, 18473,
+ 18485, 18496, 18508, 18519, 18528, 18537, 18547, 18557, 18567, 18577, 18589, 18600, 18612, 18623,
+ 18635, 18646, 18658, 18669, 18681, 18692, 18704, 18715, 18724, 18732, 18740, 18748, 18756, 18764,
+ 18772, 18780, 18788, 18796, 18804, 18812, 18820, 18828, 18836, 18844, 18853, 18861, 18869, 18877,
+ 18885, 18893, 18901, 18909, 18917, 18925, 18933, 18941, 18949, 18957, 18965, 18973, 18982, 18991,
+ 19000, 19009, 19019, 19029, 19039, 19049, 19057, 19065, 19073, 19081, 19093, 19105, 19117, 19129,
+ 19142, 19155, 19167, 19179, 19191, 19203, 19215, 19227, 19240, 19253, 19265, 19277, 19285, 19295,
+ 19305, 19315, 19325, 19334, 19342, 19352, 19362, 19372, 19382, 19391, 19399, 19409, 19419, 19425,
+ 19432, 19441, 19450, 19459, 19468, 19477, 19486, 19495, 19502, 19509, 19517, 19526, 19534, 19542,
+ 19551, 19559, 19567, 19576, 19584, 19592, 19601, 19609, 19617, 19626, 19634, 19642, 19651, 19659,
+ 19666, 19674, 19681, 19688, 19696, 19703, 19710, 19721, 19728, 19739, 19746, 19757, 19764, 19775,
+ 19783, 19792, 19800, 19808, 19817, 19825, 19833, 19842, 19850, 19858, 19867, 19875, 19883, 19892,
+ 19900, 19908, 19917, 19925, 19932, 19940, 19947, 19954, 19962, 19969, 19975, 19981, 19987, 19994,
+ 20007, 20017, 20027, 20037, 20047, 20058, 20068, 20078, 20088, 20098, 20102, 20107, 20115, 20124,
+ 20132, 20140, 20149, 20157, 20165, 20174, 20182, 20190, 20199, 20207, 20215, 20224, 20232, 20240,
+ 20249, 20257, 20264, 20272, 20279, 20286, 20294, 20301, 20309, 20318, 20326, 20334, 20343, 20351,
+ 20359, 20368, 20376, 20384, 20393, 20401, 20409, 20418, 20426, 20434, 20443, 20451, 20458, 20466,
+ 20473, 20480, 20488, 20495, 20508, 20521, 20534, 20547, 20560, 20573, 20586, 20599, 20603, 20612,
+ 20625, 20634, 20647, 20656, 20669, 20678, 20691, 20696, 20704, 20713, 20721, 20729, 20738, 20746,
+ 20754, 20763, 20771, 20779, 20788, 20796, 20804, 20813, 20821, 20829, 20838, 20846, 20853, 20861,
+ 20868, 20875, 20883, 20890, 20899, 20907, 20916, 20924, 20932, 20941, 20949, 20957, 20969, 20978,
+ 20986, 20995, 21003, 21011, 21020, 21028, 21036, 21048, 21057, 21067, 21076, 21084, 21094, 21103,
+ 21111, 21119, 21131, 21138, 21145, 21152, 21159, 21166, 21173, 21184, 21191, 21198, 21205, 21211,
+ 21218, 21225, 21231, 21237, 21244, 21251, 21261, 21271, 21281, 21290, 21296, 21302, 21308, 21314,
+ 21321, 21328, 21334, 21340, 21347, 21354, 21360, 21366, 21373, 21380, 21387, 21394, 21401, 21408,
+ 21415, 21422, 21428, 21434, 21440, 21446, 21452, 21458, 21465, 21471, 21479, 21488, 21496, 21504,
+ 21513, 21521, 21529, 21538, 21546, 21554, 21563, 21571, 21579, 21588, 21596, 21604, 21613, 21621,
+ 21628, 21636, 21643, 21650, 21658, 21665, 21676, 21687, 21698, 21709, 21720, 21731, 21742, 21753,
+ 21764, 21775, 21786, 21797, 21805, 21814, 21822, 21830, 21839, 21847, 21855, 21864, 21872, 21880,
+ 21889, 21897, 21905, 21914, 21922, 21930, 21939, 21947, 21954, 21962, 21969, 21976, 21984, 21991,
+ 22002, 22013, 22024, 22035, 22046, 22057, 22068, 22079, 22090, 22101, 22112, 22123, 22133, 22143,
+ 22153, 22163, 22169, 22175, 22184, 22193, 22202, 22210, 22218, 22226, 22234, 22242, 22250, 22258,
+ 22266, 22274, 22286, 22294, 22306, 22314, 22326, 22334, 22346, 22354, 22366, 22374, 22386, 22394,
+ 22406, 22414, 22426, 22433, 22443, 22453, 22463, 22473, 22477, 22481, 22485, 22493, 22499, 22505,
+ 22511, 22516, 22521, 22529, 22537, 22546, 22555, 22564, 22572, 22581, 22590, 22601, 22612, 22623,
+ 22633, 22643, 22655, 22665, 22677, 22689, 22696, 22705, 22713, 22722, 22730, 22738, 22747, 22755,
+ 22763, 22775, 22784, 22792, 22801, 22809, 22817, 22826, 22834, 22842, 22854, 22863, 22873, 22882,
+ 22890, 22900, 22909, 22917, 22925, 22937, 22944, 22951, 22958, 22965, 22972, 22979, 22990, 22998,
+ 23006, 23014, 23022, 23032, 23042, 23053, 23064, 23076, 23087, 23098, 23109, 23122, 23135, 23148,
+ 23162, 23176, 23190, 23204, 23218, 23232, 23243, 23251, 23263, 23271, 23283, 23291, 23303, 23311,
+ 23323, 23332, 23341, 23351, 23361, 23372, 23382, 23391, 23401, 23410, 23420, 23432, 23441, 23453,
+ 23465, 23478, 23491, 23504, 23517, 23530, 23543, 23553, 23560, 23568, 23577, 23585, 23595, 23602,
+ 23611, 23620, 23629, 23640, 23651, 23664, 23675, 23688, 23698, 23707, 23716, 23725, 23734, 23744,
+ 23753, 23762, 23771, 23780, 23790, 23801, 23812, 23821, 23830, 23838, 23846, 23854, 23862, 23870,
+ 23881, 23892, 23897, 23903, 23912, 23921, 23930, 23940, 23950, 23960, 23970, 23980, 23989, 23999,
+ 24008, 24020, 24032, 24044, 24055, 24066, 24077, 24085, 24096, 24107, 24118, 24129, 24140, 24151,
+ 24162, 24173, 24195, 24201, 24207, 24213, 24219, 24226, 24235, 24244, 24253, 24262, 24273, 24284,
+ 24295, 24306, 24315, 24327, 24339, 24351, 24363, 24370, 24376, 24383, 24396, 24401, 24408, 24419,
+ 24436, 24447, 24453, 24462, 24471, 24480, 24489, 24498, 24507, 24515, 24523, 24532, 24541, 24550,
+ 24559, 24568, 24577, 24586, 24595, 24604, 24612, 24620, 24626, 24631, 24640, 24648, 24657, 24665,
+ 24673, 24682, 24690, 24698, 24710, 24719, 24727, 24736, 24744, 24752, 24761, 24769, 24777, 24789,
+ 24798, 24808, 24817, 24825, 24835, 24844, 24852, 24860, 24872, 24879, 24886, 24893, 24900, 24907,
+ 24914, 24925, 24933, 24941, 24949, 0
};
const char *Strs =
@@ -3685,267 +3686,268 @@ const char *X86ATTInstPrinter::getInstructionName(unsigned Opcode) {
"64\000LXADD8\000MASKMOVDQU\000MASKMOVDQU64\000MAXPDrm\000MAXPDrm_Int\000"
"MAXPDrr\000MAXPDrr_Int\000MAXPSrm\000MAXPSrm_Int\000MAXPSrr\000MAXPSrr_"
"Int\000MAXSDrm\000MAXSDrm_Int\000MAXSDrr\000MAXSDrr_Int\000MAXSSrm\000M"
- "AXSSrm_Int\000MAXSSrr\000MAXSSrr_Int\000MFENCE\000MINPDrm\000MINPDrm_In"
- "t\000MINPDrr\000MINPDrr_Int\000MINPSrm\000MINPSrm_Int\000MINPSrr\000MIN"
- "PSrr_Int\000MINSDrm\000MINSDrm_Int\000MINSDrr\000MINSDrr_Int\000MINSSrm"
- "\000MINSSrm_Int\000MINSSrr\000MINSSrr_Int\000MMX_CVTPD2PIrm\000MMX_CVTP"
- "D2PIrr\000MMX_CVTPI2PDrm\000MMX_CVTPI2PDrr\000MMX_CVTPI2PSrm\000MMX_CVT"
- "PI2PSrr\000MMX_CVTPS2PIrm\000MMX_CVTPS2PIrr\000MMX_CVTTPD2PIrm\000MMX_C"
- "VTTPD2PIrr\000MMX_CVTTPS2PIrm\000MMX_CVTTPS2PIrr\000MMX_EMMS\000MMX_FEM"
- "MS\000MMX_MASKMOVQ\000MMX_MASKMOVQ64\000MMX_MOVD64from64rr\000MMX_MOVD6"
- "4grr\000MMX_MOVD64mr\000MMX_MOVD64rm\000MMX_MOVD64rr\000MMX_MOVD64rrv16"
- "4\000MMX_MOVD64to64rr\000MMX_MOVDQ2Qrr\000MMX_MOVNTQmr\000MMX_MOVQ2DQrr"
- "\000MMX_MOVQ2FR64rr\000MMX_MOVQ64gmr\000MMX_MOVQ64mr\000MMX_MOVQ64rm\000"
- "MMX_MOVQ64rr\000MMX_MOVZDI2PDIrm\000MMX_MOVZDI2PDIrr\000MMX_PACKSSDWrm\000"
- "MMX_PACKSSDWrr\000MMX_PACKSSWBrm\000MMX_PACKSSWBrr\000MMX_PACKUSWBrm\000"
- "MMX_PACKUSWBrr\000MMX_PADDBrm\000MMX_PADDBrr\000MMX_PADDDrm\000MMX_PADD"
- "Drr\000MMX_PADDQrm\000MMX_PADDQrr\000MMX_PADDSBrm\000MMX_PADDSBrr\000MM"
- "X_PADDSWrm\000MMX_PADDSWrr\000MMX_PADDUSBrm\000MMX_PADDUSBrr\000MMX_PAD"
- "DUSWrm\000MMX_PADDUSWrr\000MMX_PADDWrm\000MMX_PADDWrr\000MMX_PANDNrm\000"
- "MMX_PANDNrr\000MMX_PANDrm\000MMX_PANDrr\000MMX_PAVGBrm\000MMX_PAVGBrr\000"
- "MMX_PAVGWrm\000MMX_PAVGWrr\000MMX_PCMPEQBrm\000MMX_PCMPEQBrr\000MMX_PCM"
- "PEQDrm\000MMX_PCMPEQDrr\000MMX_PCMPEQWrm\000MMX_PCMPEQWrr\000MMX_PCMPGT"
- "Brm\000MMX_PCMPGTBrr\000MMX_PCMPGTDrm\000MMX_PCMPGTDrr\000MMX_PCMPGTWrm"
- "\000MMX_PCMPGTWrr\000MMX_PEXTRWri\000MMX_PINSRWrmi\000MMX_PINSRWrri\000"
- "MMX_PMADDWDrm\000MMX_PMADDWDrr\000MMX_PMAXSWrm\000MMX_PMAXSWrr\000MMX_P"
- "MAXUBrm\000MMX_PMAXUBrr\000MMX_PMINSWrm\000MMX_PMINSWrr\000MMX_PMINUBrm"
- "\000MMX_PMINUBrr\000MMX_PMOVMSKBrr\000MMX_PMULHUWrm\000MMX_PMULHUWrr\000"
- "MMX_PMULHWrm\000MMX_PMULHWrr\000MMX_PMULLWrm\000MMX_PMULLWrr\000MMX_PMU"
- "LUDQrm\000MMX_PMULUDQrr\000MMX_PORrm\000MMX_PORrr\000MMX_PSADBWrm\000MM"
- "X_PSADBWrr\000MMX_PSHUFWmi\000MMX_PSHUFWri\000MMX_PSLLDri\000MMX_PSLLDr"
- "m\000MMX_PSLLDrr\000MMX_PSLLQri\000MMX_PSLLQrm\000MMX_PSLLQrr\000MMX_PS"
- "LLWri\000MMX_PSLLWrm\000MMX_PSLLWrr\000MMX_PSRADri\000MMX_PSRADrm\000MM"
- "X_PSRADrr\000MMX_PSRAWri\000MMX_PSRAWrm\000MMX_PSRAWrr\000MMX_PSRLDri\000"
- "MMX_PSRLDrm\000MMX_PSRLDrr\000MMX_PSRLQri\000MMX_PSRLQrm\000MMX_PSRLQrr"
- "\000MMX_PSRLWri\000MMX_PSRLWrm\000MMX_PSRLWrr\000MMX_PSUBBrm\000MMX_PSU"
- "BBrr\000MMX_PSUBDrm\000MMX_PSUBDrr\000MMX_PSUBQrm\000MMX_PSUBQrr\000MMX"
- "_PSUBSBrm\000MMX_PSUBSBrr\000MMX_PSUBSWrm\000MMX_PSUBSWrr\000MMX_PSUBUS"
- "Brm\000MMX_PSUBUSBrr\000MMX_PSUBUSWrm\000MMX_PSUBUSWrr\000MMX_PSUBWrm\000"
- "MMX_PSUBWrr\000MMX_PUNPCKHBWrm\000MMX_PUNPCKHBWrr\000MMX_PUNPCKHDQrm\000"
- "MMX_PUNPCKHDQrr\000MMX_PUNPCKHWDrm\000MMX_PUNPCKHWDrr\000MMX_PUNPCKLBWr"
- "m\000MMX_PUNPCKLBWrr\000MMX_PUNPCKLDQrm\000MMX_PUNPCKLDQrr\000MMX_PUNPC"
- "KLWDrm\000MMX_PUNPCKLWDrr\000MMX_PXORrm\000MMX_PXORrr\000MMX_V_SET0\000"
- "MMX_V_SETALLONES\000MONITOR\000MOV16ao16\000MOV16mi\000MOV16mr\000MOV16"
- "ms\000MOV16o16a\000MOV16r0\000MOV16ri\000MOV16rm\000MOV16rr\000MOV16rr_"
- "REV\000MOV16rs\000MOV16sm\000MOV16sr\000MOV32ao32\000MOV32cr\000MOV32dr"
- "\000MOV32mi\000MOV32mr\000MOV32o32a\000MOV32r0\000MOV32rc\000MOV32rd\000"
- "MOV32ri\000MOV32rm\000MOV32rr\000MOV32rr_REV\000MOV64FSrm\000MOV64GSrm\000"
- "MOV64ao64\000MOV64ao8\000MOV64cr\000MOV64dr\000MOV64mi32\000MOV64mr\000"
- "MOV64ms\000MOV64o64a\000MOV64o8a\000MOV64r0\000MOV64rc\000MOV64rd\000MO"
- "V64ri\000MOV64ri32\000MOV64ri64i32\000MOV64rm\000MOV64rr\000MOV64rr_REV"
- "\000MOV64rs\000MOV64sm\000MOV64sr\000MOV64toPQIrr\000MOV64toSDrm\000MOV"
- "64toSDrr\000MOV8ao8\000MOV8mi\000MOV8mr\000MOV8mr_NOREX\000MOV8o8a\000M"
- "OV8r0\000MOV8ri\000MOV8rm\000MOV8rm_NOREX\000MOV8rr\000MOV8rr_NOREX\000"
- "MOV8rr_REV\000MOVAPDmr\000MOVAPDrm\000MOVAPDrr\000MOVAPSmr\000MOVAPSrm\000"
- "MOVAPSrr\000MOVDDUPrm\000MOVDDUPrr\000MOVDI2PDIrm\000MOVDI2PDIrr\000MOV"
- "DI2SSrm\000MOVDI2SSrr\000MOVDQAmr\000MOVDQArm\000MOVDQArr\000MOVDQUmr\000"
- "MOVDQUmr_Int\000MOVDQUrm\000MOVDQUrm_Int\000MOVHLPSrr\000MOVHPDmr\000MO"
- "VHPDrm\000MOVHPSmr\000MOVHPSrm\000MOVLHPSrr\000MOVLPDmr\000MOVLPDrm\000"
- "MOVLPSmr\000MOVLPSrm\000MOVLQ128mr\000MOVMSKPDrr\000MOVMSKPSrr\000MOVNT"
- "DQArm\000MOVNTDQ_64mr\000MOVNTDQmr\000MOVNTDQmr_Int\000MOVNTI_64mr\000M"
- "OVNTImr\000MOVNTImr_Int\000MOVNTPDmr\000MOVNTPDmr_Int\000MOVNTPSmr\000M"
- "OVNTPSmr_Int\000MOVPC32r\000MOVPDI2DImr\000MOVPDI2DIrr\000MOVPQI2QImr\000"
- "MOVPQIto64rr\000MOVQI2PQIrm\000MOVQxrxr\000MOVSB\000MOVSD\000MOVSDmr\000"
- "MOVSDrm\000MOVSDrr\000MOVSDto64mr\000MOVSDto64rr\000MOVSHDUPrm\000MOVSH"
- "DUPrr\000MOVSLDUPrm\000MOVSLDUPrr\000MOVSS2DImr\000MOVSS2DIrr\000MOVSSm"
- "r\000MOVSSrm\000MOVSSrr\000MOVSW\000MOVSX16rm8\000MOVSX16rm8W\000MOVSX1"
- "6rr8\000MOVSX16rr8W\000MOVSX32rm16\000MOVSX32rm8\000MOVSX32rr16\000MOVS"
- "X32rr8\000MOVSX64rm16\000MOVSX64rm32\000MOVSX64rm8\000MOVSX64rr16\000MO"
- "VSX64rr32\000MOVSX64rr8\000MOVUPDmr\000MOVUPDmr_Int\000MOVUPDrm\000MOVU"
- "PDrm_Int\000MOVUPDrr\000MOVUPSmr\000MOVUPSmr_Int\000MOVUPSrm\000MOVUPSr"
- "m_Int\000MOVUPSrr\000MOVZDI2PDIrm\000MOVZDI2PDIrr\000MOVZPQILo2PQIrm\000"
- "MOVZPQILo2PQIrr\000MOVZQI2PQIrm\000MOVZQI2PQIrr\000MOVZX16rm8\000MOVZX1"
- "6rm8W\000MOVZX16rr8\000MOVZX16rr8W\000MOVZX32_NOREXrm8\000MOVZX32_NOREX"
- "rr8\000MOVZX32rm16\000MOVZX32rm8\000MOVZX32rr16\000MOVZX32rr8\000MOVZX6"
- "4rm16\000MOVZX64rm16_Q\000MOVZX64rm32\000MOVZX64rm8\000MOVZX64rm8_Q\000"
- "MOVZX64rr16\000MOVZX64rr16_Q\000MOVZX64rr32\000MOVZX64rr8\000MOVZX64rr8"
- "_Q\000MOV_Fp3232\000MOV_Fp3264\000MOV_Fp3280\000MOV_Fp6432\000MOV_Fp646"
- "4\000MOV_Fp6480\000MOV_Fp8032\000MOV_Fp8064\000MOV_Fp8080\000MPSADBWrmi"
- "\000MPSADBWrri\000MUL16m\000MUL16r\000MUL32m\000MUL32r\000MUL64m\000MUL"
- "64r\000MUL8m\000MUL8r\000MULPDrm\000MULPDrr\000MULPSrm\000MULPSrr\000MU"
- "LSDrm\000MULSDrm_Int\000MULSDrr\000MULSDrr_Int\000MULSSrm\000MULSSrm_In"
- "t\000MULSSrr\000MULSSrr_Int\000MUL_F32m\000MUL_F64m\000MUL_FI16m\000MUL"
- "_FI32m\000MUL_FPrST0\000MUL_FST0r\000MUL_Fp32\000MUL_Fp32m\000MUL_Fp64\000"
- "MUL_Fp64m\000MUL_Fp64m32\000MUL_Fp80\000MUL_Fp80m32\000MUL_Fp80m64\000M"
- "UL_FpI16m32\000MUL_FpI16m64\000MUL_FpI16m80\000MUL_FpI32m32\000MUL_FpI3"
- "2m64\000MUL_FpI32m80\000MUL_FrST0\000MWAIT\000NEG16m\000NEG16r\000NEG32"
- "m\000NEG32r\000NEG64m\000NEG64r\000NEG8m\000NEG8r\000NOOP\000NOOPL\000N"
- "OOPW\000NOT16m\000NOT16r\000NOT32m\000NOT32r\000NOT64m\000NOT64r\000NOT"
- "8m\000NOT8r\000OR16i16\000OR16mi\000OR16mi8\000OR16mr\000OR16ri\000OR16"
- "ri8\000OR16rm\000OR16rr\000OR16rr_REV\000OR32i32\000OR32mi\000OR32mi8\000"
- "OR32mr\000OR32ri\000OR32ri8\000OR32rm\000OR32rr\000OR32rr_REV\000OR64i3"
- "2\000OR64mi32\000OR64mi8\000OR64mr\000OR64ri32\000OR64ri8\000OR64rm\000"
- "OR64rr\000OR64rr_REV\000OR8i8\000OR8mi\000OR8mr\000OR8ri\000OR8rm\000OR"
- "8rr\000OR8rr_REV\000ORPDrm\000ORPDrr\000ORPSrm\000ORPSrr\000OUT16ir\000"
- "OUT16rr\000OUT32ir\000OUT32rr\000OUT8ir\000OUT8rr\000OUTSB\000OUTSD\000"
- "OUTSW\000PABSBrm128\000PABSBrm64\000PABSBrr128\000PABSBrr64\000PABSDrm1"
- "28\000PABSDrm64\000PABSDrr128\000PABSDrr64\000PABSWrm128\000PABSWrm64\000"
- "PABSWrr128\000PABSWrr64\000PACKSSDWrm\000PACKSSDWrr\000PACKSSWBrm\000PA"
- "CKSSWBrr\000PACKUSDWrm\000PACKUSDWrr\000PACKUSWBrm\000PACKUSWBrr\000PAD"
- "DBrm\000PADDBrr\000PADDDrm\000PADDDrr\000PADDQrm\000PADDQrr\000PADDSBrm"
- "\000PADDSBrr\000PADDSWrm\000PADDSWrr\000PADDUSBrm\000PADDUSBrr\000PADDU"
- "SWrm\000PADDUSWrr\000PADDWrm\000PADDWrr\000PALIGNR128rm\000PALIGNR128rr"
- "\000PALIGNR64rm\000PALIGNR64rr\000PANDNrm\000PANDNrr\000PANDrm\000PANDr"
- "r\000PAVGBrm\000PAVGBrr\000PAVGWrm\000PAVGWrr\000PBLENDVBrm0\000PBLENDV"
- "Brr0\000PBLENDWrmi\000PBLENDWrri\000PCMPEQBrm\000PCMPEQBrr\000PCMPEQDrm"
- "\000PCMPEQDrr\000PCMPEQQrm\000PCMPEQQrr\000PCMPEQWrm\000PCMPEQWrr\000PC"
- "MPESTRIArm\000PCMPESTRIArr\000PCMPESTRICrm\000PCMPESTRICrr\000PCMPESTRI"
- "Orm\000PCMPESTRIOrr\000PCMPESTRISrm\000PCMPESTRISrr\000PCMPESTRIZrm\000"
- "PCMPESTRIZrr\000PCMPESTRIrm\000PCMPESTRIrr\000PCMPESTRM128MEM\000PCMPES"
- "TRM128REG\000PCMPESTRM128rm\000PCMPESTRM128rr\000PCMPGTBrm\000PCMPGTBrr"
- "\000PCMPGTDrm\000PCMPGTDrr\000PCMPGTQrm\000PCMPGTQrr\000PCMPGTWrm\000PC"
- "MPGTWrr\000PCMPISTRIArm\000PCMPISTRIArr\000PCMPISTRICrm\000PCMPISTRICrr"
- "\000PCMPISTRIOrm\000PCMPISTRIOrr\000PCMPISTRISrm\000PCMPISTRISrr\000PCM"
- "PISTRIZrm\000PCMPISTRIZrr\000PCMPISTRIrm\000PCMPISTRIrr\000PCMPISTRM128"
- "MEM\000PCMPISTRM128REG\000PCMPISTRM128rm\000PCMPISTRM128rr\000PEXTRBmr\000"
- "PEXTRBrr\000PEXTRDmr\000PEXTRDrr\000PEXTRQmr\000PEXTRQrr\000PEXTRWmr\000"
- "PEXTRWri\000PHADDDrm128\000PHADDDrm64\000PHADDDrr128\000PHADDDrr64\000P"
- "HADDSWrm128\000PHADDSWrm64\000PHADDSWrr128\000PHADDSWrr64\000PHADDWrm12"
- "8\000PHADDWrm64\000PHADDWrr128\000PHADDWrr64\000PHMINPOSUWrm128\000PHMI"
- "NPOSUWrr128\000PHSUBDrm128\000PHSUBDrm64\000PHSUBDrr128\000PHSUBDrr64\000"
- "PHSUBSWrm128\000PHSUBSWrm64\000PHSUBSWrr128\000PHSUBSWrr64\000PHSUBWrm1"
- "28\000PHSUBWrm64\000PHSUBWrr128\000PHSUBWrr64\000PINSRBrm\000PINSRBrr\000"
- "PINSRDrm\000PINSRDrr\000PINSRQrm\000PINSRQrr\000PINSRWrmi\000PINSRWrri\000"
- "PMADDUBSWrm128\000PMADDUBSWrm64\000PMADDUBSWrr128\000PMADDUBSWrr64\000P"
- "MADDWDrm\000PMADDWDrr\000PMAXSBrm\000PMAXSBrr\000PMAXSDrm\000PMAXSDrr\000"
- "PMAXSWrm\000PMAXSWrr\000PMAXUBrm\000PMAXUBrr\000PMAXUDrm\000PMAXUDrr\000"
- "PMAXUWrm\000PMAXUWrr\000PMINSBrm\000PMINSBrr\000PMINSDrm\000PMINSDrr\000"
- "PMINSWrm\000PMINSWrr\000PMINUBrm\000PMINUBrr\000PMINUDrm\000PMINUDrr\000"
- "PMINUWrm\000PMINUWrr\000PMOVMSKBrr\000PMOVSXBDrm\000PMOVSXBDrr\000PMOVS"
- "XBQrm\000PMOVSXBQrr\000PMOVSXBWrm\000PMOVSXBWrr\000PMOVSXDQrm\000PMOVSX"
- "DQrr\000PMOVSXWDrm\000PMOVSXWDrr\000PMOVSXWQrm\000PMOVSXWQrr\000PMOVZXB"
- "Drm\000PMOVZXBDrr\000PMOVZXBQrm\000PMOVZXBQrr\000PMOVZXBWrm\000PMOVZXBW"
- "rr\000PMOVZXDQrm\000PMOVZXDQrr\000PMOVZXWDrm\000PMOVZXWDrr\000PMOVZXWQr"
- "m\000PMOVZXWQrr\000PMULDQrm\000PMULDQrr\000PMULHRSWrm128\000PMULHRSWrm6"
- "4\000PMULHRSWrr128\000PMULHRSWrr64\000PMULHUWrm\000PMULHUWrr\000PMULHWr"
- "m\000PMULHWrr\000PMULLDrm\000PMULLDrm_int\000PMULLDrr\000PMULLDrr_int\000"
- "PMULLWrm\000PMULLWrr\000PMULUDQrm\000PMULUDQrr\000POP16r\000POP16rmm\000"
- "POP16rmr\000POP32r\000POP32rmm\000POP32rmr\000POP64r\000POP64rmm\000POP"
- "64rmr\000POPCNT16rm\000POPCNT16rr\000POPCNT32rm\000POPCNT32rr\000POPCNT"
- "64rm\000POPCNT64rr\000POPF\000POPFD\000POPFQ\000POPFS16\000POPFS32\000P"
- "OPFS64\000POPGS16\000POPGS32\000POPGS64\000PORrm\000PORrr\000PREFETCHNT"
- "A\000PREFETCHT0\000PREFETCHT1\000PREFETCHT2\000PSADBWrm\000PSADBWrr\000"
- "PSHUFBrm128\000PSHUFBrm64\000PSHUFBrr128\000PSHUFBrr64\000PSHUFDmi\000P"
- "SHUFDri\000PSHUFHWmi\000PSHUFHWri\000PSHUFLWmi\000PSHUFLWri\000PSIGNBrm"
- "128\000PSIGNBrm64\000PSIGNBrr128\000PSIGNBrr64\000PSIGNDrm128\000PSIGND"
- "rm64\000PSIGNDrr128\000PSIGNDrr64\000PSIGNWrm128\000PSIGNWrm64\000PSIGN"
- "Wrr128\000PSIGNWrr64\000PSLLDQri\000PSLLDri\000PSLLDrm\000PSLLDrr\000PS"
- "LLQri\000PSLLQrm\000PSLLQrr\000PSLLWri\000PSLLWrm\000PSLLWrr\000PSRADri"
- "\000PSRADrm\000PSRADrr\000PSRAWri\000PSRAWrm\000PSRAWrr\000PSRLDQri\000"
- "PSRLDri\000PSRLDrm\000PSRLDrr\000PSRLQri\000PSRLQrm\000PSRLQrr\000PSRLW"
- "ri\000PSRLWrm\000PSRLWrr\000PSUBBrm\000PSUBBrr\000PSUBDrm\000PSUBDrr\000"
- "PSUBQrm\000PSUBQrr\000PSUBSBrm\000PSUBSBrr\000PSUBSWrm\000PSUBSWrr\000P"
- "SUBUSBrm\000PSUBUSBrr\000PSUBUSWrm\000PSUBUSWrr\000PSUBWrm\000PSUBWrr\000"
- "PTESTrm\000PTESTrr\000PUNPCKHBWrm\000PUNPCKHBWrr\000PUNPCKHDQrm\000PUNP"
- "CKHDQrr\000PUNPCKHQDQrm\000PUNPCKHQDQrr\000PUNPCKHWDrm\000PUNPCKHWDrr\000"
- "PUNPCKLBWrm\000PUNPCKLBWrr\000PUNPCKLDQrm\000PUNPCKLDQrr\000PUNPCKLQDQr"
- "m\000PUNPCKLQDQrr\000PUNPCKLWDrm\000PUNPCKLWDrr\000PUSH16r\000PUSH16rmm"
- "\000PUSH16rmr\000PUSH32i16\000PUSH32i32\000PUSH32i8\000PUSH32r\000PUSH3"
- "2rmm\000PUSH32rmr\000PUSH64i16\000PUSH64i32\000PUSH64i8\000PUSH64r\000P"
- "USH64rmm\000PUSH64rmr\000PUSHF\000PUSHFD\000PUSHFQ64\000PUSHFS16\000PUS"
- "HFS32\000PUSHFS64\000PUSHGS16\000PUSHGS32\000PUSHGS64\000PXORrm\000PXOR"
- "rr\000RCL16m1\000RCL16mCL\000RCL16mi\000RCL16r1\000RCL16rCL\000RCL16ri\000"
- "RCL32m1\000RCL32mCL\000RCL32mi\000RCL32r1\000RCL32rCL\000RCL32ri\000RCL"
- "64m1\000RCL64mCL\000RCL64mi\000RCL64r1\000RCL64rCL\000RCL64ri\000RCL8m1"
- "\000RCL8mCL\000RCL8mi\000RCL8r1\000RCL8rCL\000RCL8ri\000RCPPSm\000RCPPS"
- "m_Int\000RCPPSr\000RCPPSr_Int\000RCPSSm\000RCPSSm_Int\000RCPSSr\000RCPS"
- "Sr_Int\000RCR16m1\000RCR16mCL\000RCR16mi\000RCR16r1\000RCR16rCL\000RCR1"
- "6ri\000RCR32m1\000RCR32mCL\000RCR32mi\000RCR32r1\000RCR32rCL\000RCR32ri"
- "\000RCR64m1\000RCR64mCL\000RCR64mi\000RCR64r1\000RCR64rCL\000RCR64ri\000"
- "RCR8m1\000RCR8mCL\000RCR8mi\000RCR8r1\000RCR8rCL\000RCR8ri\000RDMSR\000"
- "RDPMC\000RDTSC\000RDTSCP\000REPNE_PREFIX\000REP_MOVSB\000REP_MOVSD\000R"
- "EP_MOVSQ\000REP_MOVSW\000REP_PREFIX\000REP_STOSB\000REP_STOSD\000REP_ST"
- "OSQ\000REP_STOSW\000RET\000RETI\000ROL16m1\000ROL16mCL\000ROL16mi\000RO"
- "L16r1\000ROL16rCL\000ROL16ri\000ROL32m1\000ROL32mCL\000ROL32mi\000ROL32"
- "r1\000ROL32rCL\000ROL32ri\000ROL64m1\000ROL64mCL\000ROL64mi\000ROL64r1\000"
- "ROL64rCL\000ROL64ri\000ROL8m1\000ROL8mCL\000ROL8mi\000ROL8r1\000ROL8rCL"
- "\000ROL8ri\000ROR16m1\000ROR16mCL\000ROR16mi\000ROR16r1\000ROR16rCL\000"
- "ROR16ri\000ROR32m1\000ROR32mCL\000ROR32mi\000ROR32r1\000ROR32rCL\000ROR"
- "32ri\000ROR64m1\000ROR64mCL\000ROR64mi\000ROR64r1\000ROR64rCL\000ROR64r"
- "i\000ROR8m1\000ROR8mCL\000ROR8mi\000ROR8r1\000ROR8rCL\000ROR8ri\000ROUN"
- "DPDm_Int\000ROUNDPDr_Int\000ROUNDPSm_Int\000ROUNDPSr_Int\000ROUNDSDm_In"
- "t\000ROUNDSDr_Int\000ROUNDSSm_Int\000ROUNDSSr_Int\000RSM\000RSQRTPSm\000"
- "RSQRTPSm_Int\000RSQRTPSr\000RSQRTPSr_Int\000RSQRTSSm\000RSQRTSSm_Int\000"
- "RSQRTSSr\000RSQRTSSr_Int\000SAHF\000SAR16m1\000SAR16mCL\000SAR16mi\000S"
- "AR16r1\000SAR16rCL\000SAR16ri\000SAR32m1\000SAR32mCL\000SAR32mi\000SAR3"
- "2r1\000SAR32rCL\000SAR32ri\000SAR64m1\000SAR64mCL\000SAR64mi\000SAR64r1"
- "\000SAR64rCL\000SAR64ri\000SAR8m1\000SAR8mCL\000SAR8mi\000SAR8r1\000SAR"
- "8rCL\000SAR8ri\000SBB16i16\000SBB16mi\000SBB16mi8\000SBB16mr\000SBB16ri"
- "\000SBB16ri8\000SBB16rm\000SBB16rr\000SBB16rr_REV\000SBB32i32\000SBB32m"
- "i\000SBB32mi8\000SBB32mr\000SBB32ri\000SBB32ri8\000SBB32rm\000SBB32rr\000"
- "SBB32rr_REV\000SBB64i32\000SBB64mi32\000SBB64mi8\000SBB64mr\000SBB64ri3"
- "2\000SBB64ri8\000SBB64rm\000SBB64rr\000SBB64rr_REV\000SBB8i8\000SBB8mi\000"
- "SBB8mr\000SBB8ri\000SBB8rm\000SBB8rr\000SBB8rr_REV\000SCAS16\000SCAS32\000"
- "SCAS64\000SCAS8\000SETAEm\000SETAEr\000SETAm\000SETAr\000SETBEm\000SETB"
- "Er\000SETB_C16r\000SETB_C32r\000SETB_C64r\000SETB_C8r\000SETBm\000SETBr"
- "\000SETEm\000SETEr\000SETGEm\000SETGEr\000SETGm\000SETGr\000SETLEm\000S"
- "ETLEr\000SETLm\000SETLr\000SETNEm\000SETNEr\000SETNOm\000SETNOr\000SETN"
- "Pm\000SETNPr\000SETNSm\000SETNSr\000SETOm\000SETOr\000SETPm\000SETPr\000"
- "SETSm\000SETSr\000SFENCE\000SGDTm\000SHL16m1\000SHL16mCL\000SHL16mi\000"
- "SHL16r1\000SHL16rCL\000SHL16ri\000SHL32m1\000SHL32mCL\000SHL32mi\000SHL"
- "32r1\000SHL32rCL\000SHL32ri\000SHL64m1\000SHL64mCL\000SHL64mi\000SHL64r"
- "1\000SHL64rCL\000SHL64ri\000SHL8m1\000SHL8mCL\000SHL8mi\000SHL8r1\000SH"
- "L8rCL\000SHL8ri\000SHLD16mrCL\000SHLD16mri8\000SHLD16rrCL\000SHLD16rri8"
- "\000SHLD32mrCL\000SHLD32mri8\000SHLD32rrCL\000SHLD32rri8\000SHLD64mrCL\000"
- "SHLD64mri8\000SHLD64rrCL\000SHLD64rri8\000SHR16m1\000SHR16mCL\000SHR16m"
- "i\000SHR16r1\000SHR16rCL\000SHR16ri\000SHR32m1\000SHR32mCL\000SHR32mi\000"
- "SHR32r1\000SHR32rCL\000SHR32ri\000SHR64m1\000SHR64mCL\000SHR64mi\000SHR"
- "64r1\000SHR64rCL\000SHR64ri\000SHR8m1\000SHR8mCL\000SHR8mi\000SHR8r1\000"
- "SHR8rCL\000SHR8ri\000SHRD16mrCL\000SHRD16mri8\000SHRD16rrCL\000SHRD16rr"
- "i8\000SHRD32mrCL\000SHRD32mri8\000SHRD32rrCL\000SHRD32rri8\000SHRD64mrC"
- "L\000SHRD64mri8\000SHRD64rrCL\000SHRD64rri8\000SHUFPDrmi\000SHUFPDrri\000"
- "SHUFPSrmi\000SHUFPSrri\000SIDTm\000SIN_F\000SIN_Fp32\000SIN_Fp64\000SIN"
- "_Fp80\000SLDT16m\000SLDT16r\000SLDT64m\000SLDT64r\000SMSW16m\000SMSW16r"
- "\000SMSW32r\000SMSW64r\000SQRTPDm\000SQRTPDm_Int\000SQRTPDr\000SQRTPDr_"
- "Int\000SQRTPSm\000SQRTPSm_Int\000SQRTPSr\000SQRTPSr_Int\000SQRTSDm\000S"
- "QRTSDm_Int\000SQRTSDr\000SQRTSDr_Int\000SQRTSSm\000SQRTSSm_Int\000SQRTS"
- "Sr\000SQRTSSr_Int\000SQRT_F\000SQRT_Fp32\000SQRT_Fp64\000SQRT_Fp80\000S"
- "S_PREFIX\000STC\000STD\000STI\000STMXCSR\000STOSB\000STOSD\000STOSW\000"
- "STRm\000STRr\000ST_F32m\000ST_F64m\000ST_FP32m\000ST_FP64m\000ST_FP80m\000"
- "ST_FPrr\000ST_Fp32m\000ST_Fp64m\000ST_Fp64m32\000ST_Fp80m32\000ST_Fp80m"
- "64\000ST_FpP32m\000ST_FpP64m\000ST_FpP64m32\000ST_FpP80m\000ST_FpP80m32"
- "\000ST_FpP80m64\000ST_Frr\000SUB16i16\000SUB16mi\000SUB16mi8\000SUB16mr"
- "\000SUB16ri\000SUB16ri8\000SUB16rm\000SUB16rr\000SUB16rr_REV\000SUB32i3"
- "2\000SUB32mi\000SUB32mi8\000SUB32mr\000SUB32ri\000SUB32ri8\000SUB32rm\000"
- "SUB32rr\000SUB32rr_REV\000SUB64i32\000SUB64mi32\000SUB64mi8\000SUB64mr\000"
- "SUB64ri32\000SUB64ri8\000SUB64rm\000SUB64rr\000SUB64rr_REV\000SUB8i8\000"
- "SUB8mi\000SUB8mr\000SUB8ri\000SUB8rm\000SUB8rr\000SUB8rr_REV\000SUBPDrm"
- "\000SUBPDrr\000SUBPSrm\000SUBPSrr\000SUBR_F32m\000SUBR_F64m\000SUBR_FI1"
- "6m\000SUBR_FI32m\000SUBR_FPrST0\000SUBR_FST0r\000SUBR_Fp32m\000SUBR_Fp6"
- "4m\000SUBR_Fp64m32\000SUBR_Fp80m32\000SUBR_Fp80m64\000SUBR_FpI16m32\000"
- "SUBR_FpI16m64\000SUBR_FpI16m80\000SUBR_FpI32m32\000SUBR_FpI32m64\000SUB"
- "R_FpI32m80\000SUBR_FrST0\000SUBSDrm\000SUBSDrm_Int\000SUBSDrr\000SUBSDr"
- "r_Int\000SUBSSrm\000SUBSSrm_Int\000SUBSSrr\000SUBSSrr_Int\000SUB_F32m\000"
- "SUB_F64m\000SUB_FI16m\000SUB_FI32m\000SUB_FPrST0\000SUB_FST0r\000SUB_Fp"
- "32\000SUB_Fp32m\000SUB_Fp64\000SUB_Fp64m\000SUB_Fp64m32\000SUB_Fp80\000"
- "SUB_Fp80m32\000SUB_Fp80m64\000SUB_FpI16m32\000SUB_FpI16m64\000SUB_FpI16"
- "m80\000SUB_FpI32m32\000SUB_FpI32m64\000SUB_FpI32m80\000SUB_FrST0\000SWA"
- "PGS\000SYSCALL\000SYSENTER\000SYSEXIT\000SYSEXIT64\000SYSRET\000TAILJMP"
- "d\000TAILJMPm\000TAILJMPr\000TAILJMPr64\000TCRETURNdi\000TCRETURNdi64\000"
- "TCRETURNri\000TCRETURNri64\000TEST16i16\000TEST16mi\000TEST16ri\000TEST"
- "16rm\000TEST16rr\000TEST32i32\000TEST32mi\000TEST32ri\000TEST32rm\000TE"
- "ST32rr\000TEST64i32\000TEST64mi32\000TEST64ri32\000TEST64rm\000TEST64rr"
- "\000TEST8i8\000TEST8mi\000TEST8ri\000TEST8rm\000TEST8rr\000TLS_addr32\000"
- "TLS_addr64\000TRAP\000TST_F\000TST_Fp32\000TST_Fp64\000TST_Fp80\000UCOM"
- "ISDrm\000UCOMISDrr\000UCOMISSrm\000UCOMISSrr\000UCOM_FIPr\000UCOM_FIr\000"
- "UCOM_FPPr\000UCOM_FPr\000UCOM_FpIr32\000UCOM_FpIr64\000UCOM_FpIr80\000U"
- "COM_Fpr32\000UCOM_Fpr64\000UCOM_Fpr80\000UCOM_Fr\000UNPCKHPDrm\000UNPCK"
- "HPDrr\000UNPCKHPSrm\000UNPCKHPSrr\000UNPCKLPDrm\000UNPCKLPDrr\000UNPCKL"
- "PSrm\000UNPCKLPSrr\000VASTART_SAVE_XMM_REGS\000VERRm\000VERRr\000VERWm\000"
- "VERWr\000VMCALL\000VMCLEARm\000VMLAUNCH\000VMPTRLDm\000VMPTRSTm\000VMRE"
- "AD32rm\000VMREAD32rr\000VMREAD64rm\000VMREAD64rr\000VMRESUME\000VMWRITE"
- "32rm\000VMWRITE32rr\000VMWRITE64rm\000VMWRITE64rr\000VMXOFF\000VMXON\000"
- "V_SET0\000V_SETALLONES\000WAIT\000WBINVD\000WINCALL64m\000WINCALL64pcre"
- "l32\000WINCALL64r\000WRMSR\000XADD16rm\000XADD16rr\000XADD32rm\000XADD3"
- "2rr\000XADD64rm\000XADD64rr\000XADD8rm\000XADD8rr\000XCHG16ar\000XCHG16"
- "rm\000XCHG16rr\000XCHG32ar\000XCHG32rm\000XCHG32rr\000XCHG64ar\000XCHG6"
- "4rm\000XCHG64rr\000XCHG8rm\000XCHG8rr\000XCH_F\000XLAT\000XOR16i16\000X"
- "OR16mi\000XOR16mi8\000XOR16mr\000XOR16ri\000XOR16ri8\000XOR16rm\000XOR1"
- "6rr\000XOR16rr_REV\000XOR32i32\000XOR32mi\000XOR32mi8\000XOR32mr\000XOR"
- "32ri\000XOR32ri8\000XOR32rm\000XOR32rr\000XOR32rr_REV\000XOR64i32\000XO"
- "R64mi32\000XOR64mi8\000XOR64mr\000XOR64ri32\000XOR64ri8\000XOR64rm\000X"
- "OR64rr\000XOR64rr_REV\000XOR8i8\000XOR8mi\000XOR8mr\000XOR8ri\000XOR8rm"
- "\000XOR8rr\000XOR8rr_REV\000XORPDrm\000XORPDrr\000XORPSrm\000XORPSrr\000";
+ "AXSSrm_Int\000MAXSSrr\000MAXSSrr_Int\000MFENCE\000MINGW_ALLOCA\000MINPD"
+ "rm\000MINPDrm_Int\000MINPDrr\000MINPDrr_Int\000MINPSrm\000MINPSrm_Int\000"
+ "MINPSrr\000MINPSrr_Int\000MINSDrm\000MINSDrm_Int\000MINSDrr\000MINSDrr_"
+ "Int\000MINSSrm\000MINSSrm_Int\000MINSSrr\000MINSSrr_Int\000MMX_CVTPD2PI"
+ "rm\000MMX_CVTPD2PIrr\000MMX_CVTPI2PDrm\000MMX_CVTPI2PDrr\000MMX_CVTPI2P"
+ "Srm\000MMX_CVTPI2PSrr\000MMX_CVTPS2PIrm\000MMX_CVTPS2PIrr\000MMX_CVTTPD"
+ "2PIrm\000MMX_CVTTPD2PIrr\000MMX_CVTTPS2PIrm\000MMX_CVTTPS2PIrr\000MMX_E"
+ "MMS\000MMX_FEMMS\000MMX_MASKMOVQ\000MMX_MASKMOVQ64\000MMX_MOVD64from64r"
+ "r\000MMX_MOVD64grr\000MMX_MOVD64mr\000MMX_MOVD64rm\000MMX_MOVD64rr\000M"
+ "MX_MOVD64rrv164\000MMX_MOVD64to64rr\000MMX_MOVDQ2Qrr\000MMX_MOVNTQmr\000"
+ "MMX_MOVQ2DQrr\000MMX_MOVQ2FR64rr\000MMX_MOVQ64gmr\000MMX_MOVQ64mr\000MM"
+ "X_MOVQ64rm\000MMX_MOVQ64rr\000MMX_MOVZDI2PDIrm\000MMX_MOVZDI2PDIrr\000M"
+ "MX_PACKSSDWrm\000MMX_PACKSSDWrr\000MMX_PACKSSWBrm\000MMX_PACKSSWBrr\000"
+ "MMX_PACKUSWBrm\000MMX_PACKUSWBrr\000MMX_PADDBrm\000MMX_PADDBrr\000MMX_P"
+ "ADDDrm\000MMX_PADDDrr\000MMX_PADDQrm\000MMX_PADDQrr\000MMX_PADDSBrm\000"
+ "MMX_PADDSBrr\000MMX_PADDSWrm\000MMX_PADDSWrr\000MMX_PADDUSBrm\000MMX_PA"
+ "DDUSBrr\000MMX_PADDUSWrm\000MMX_PADDUSWrr\000MMX_PADDWrm\000MMX_PADDWrr"
+ "\000MMX_PANDNrm\000MMX_PANDNrr\000MMX_PANDrm\000MMX_PANDrr\000MMX_PAVGB"
+ "rm\000MMX_PAVGBrr\000MMX_PAVGWrm\000MMX_PAVGWrr\000MMX_PCMPEQBrm\000MMX"
+ "_PCMPEQBrr\000MMX_PCMPEQDrm\000MMX_PCMPEQDrr\000MMX_PCMPEQWrm\000MMX_PC"
+ "MPEQWrr\000MMX_PCMPGTBrm\000MMX_PCMPGTBrr\000MMX_PCMPGTDrm\000MMX_PCMPG"
+ "TDrr\000MMX_PCMPGTWrm\000MMX_PCMPGTWrr\000MMX_PEXTRWri\000MMX_PINSRWrmi"
+ "\000MMX_PINSRWrri\000MMX_PMADDWDrm\000MMX_PMADDWDrr\000MMX_PMAXSWrm\000"
+ "MMX_PMAXSWrr\000MMX_PMAXUBrm\000MMX_PMAXUBrr\000MMX_PMINSWrm\000MMX_PMI"
+ "NSWrr\000MMX_PMINUBrm\000MMX_PMINUBrr\000MMX_PMOVMSKBrr\000MMX_PMULHUWr"
+ "m\000MMX_PMULHUWrr\000MMX_PMULHWrm\000MMX_PMULHWrr\000MMX_PMULLWrm\000M"
+ "MX_PMULLWrr\000MMX_PMULUDQrm\000MMX_PMULUDQrr\000MMX_PORrm\000MMX_PORrr"
+ "\000MMX_PSADBWrm\000MMX_PSADBWrr\000MMX_PSHUFWmi\000MMX_PSHUFWri\000MMX"
+ "_PSLLDri\000MMX_PSLLDrm\000MMX_PSLLDrr\000MMX_PSLLQri\000MMX_PSLLQrm\000"
+ "MMX_PSLLQrr\000MMX_PSLLWri\000MMX_PSLLWrm\000MMX_PSLLWrr\000MMX_PSRADri"
+ "\000MMX_PSRADrm\000MMX_PSRADrr\000MMX_PSRAWri\000MMX_PSRAWrm\000MMX_PSR"
+ "AWrr\000MMX_PSRLDri\000MMX_PSRLDrm\000MMX_PSRLDrr\000MMX_PSRLQri\000MMX"
+ "_PSRLQrm\000MMX_PSRLQrr\000MMX_PSRLWri\000MMX_PSRLWrm\000MMX_PSRLWrr\000"
+ "MMX_PSUBBrm\000MMX_PSUBBrr\000MMX_PSUBDrm\000MMX_PSUBDrr\000MMX_PSUBQrm"
+ "\000MMX_PSUBQrr\000MMX_PSUBSBrm\000MMX_PSUBSBrr\000MMX_PSUBSWrm\000MMX_"
+ "PSUBSWrr\000MMX_PSUBUSBrm\000MMX_PSUBUSBrr\000MMX_PSUBUSWrm\000MMX_PSUB"
+ "USWrr\000MMX_PSUBWrm\000MMX_PSUBWrr\000MMX_PUNPCKHBWrm\000MMX_PUNPCKHBW"
+ "rr\000MMX_PUNPCKHDQrm\000MMX_PUNPCKHDQrr\000MMX_PUNPCKHWDrm\000MMX_PUNP"
+ "CKHWDrr\000MMX_PUNPCKLBWrm\000MMX_PUNPCKLBWrr\000MMX_PUNPCKLDQrm\000MMX"
+ "_PUNPCKLDQrr\000MMX_PUNPCKLWDrm\000MMX_PUNPCKLWDrr\000MMX_PXORrm\000MMX"
+ "_PXORrr\000MMX_V_SET0\000MMX_V_SETALLONES\000MONITOR\000MOV16ao16\000MO"
+ "V16mi\000MOV16mr\000MOV16ms\000MOV16o16a\000MOV16r0\000MOV16ri\000MOV16"
+ "rm\000MOV16rr\000MOV16rr_REV\000MOV16rs\000MOV16sm\000MOV16sr\000MOV32a"
+ "o32\000MOV32cr\000MOV32dr\000MOV32mi\000MOV32mr\000MOV32o32a\000MOV32r0"
+ "\000MOV32rc\000MOV32rd\000MOV32ri\000MOV32rm\000MOV32rr\000MOV32rr_REV\000"
+ "MOV64FSrm\000MOV64GSrm\000MOV64ao64\000MOV64ao8\000MOV64cr\000MOV64dr\000"
+ "MOV64mi32\000MOV64mr\000MOV64ms\000MOV64o64a\000MOV64o8a\000MOV64r0\000"
+ "MOV64rc\000MOV64rd\000MOV64ri\000MOV64ri32\000MOV64ri64i32\000MOV64rm\000"
+ "MOV64rr\000MOV64rr_REV\000MOV64rs\000MOV64sm\000MOV64sr\000MOV64toPQIrr"
+ "\000MOV64toSDrm\000MOV64toSDrr\000MOV8ao8\000MOV8mi\000MOV8mr\000MOV8mr"
+ "_NOREX\000MOV8o8a\000MOV8r0\000MOV8ri\000MOV8rm\000MOV8rm_NOREX\000MOV8"
+ "rr\000MOV8rr_NOREX\000MOV8rr_REV\000MOVAPDmr\000MOVAPDrm\000MOVAPDrr\000"
+ "MOVAPSmr\000MOVAPSrm\000MOVAPSrr\000MOVDDUPrm\000MOVDDUPrr\000MOVDI2PDI"
+ "rm\000MOVDI2PDIrr\000MOVDI2SSrm\000MOVDI2SSrr\000MOVDQAmr\000MOVDQArm\000"
+ "MOVDQArr\000MOVDQUmr\000MOVDQUmr_Int\000MOVDQUrm\000MOVDQUrm_Int\000MOV"
+ "HLPSrr\000MOVHPDmr\000MOVHPDrm\000MOVHPSmr\000MOVHPSrm\000MOVLHPSrr\000"
+ "MOVLPDmr\000MOVLPDrm\000MOVLPSmr\000MOVLPSrm\000MOVLQ128mr\000MOVMSKPDr"
+ "r\000MOVMSKPSrr\000MOVNTDQArm\000MOVNTDQ_64mr\000MOVNTDQmr\000MOVNTDQmr"
+ "_Int\000MOVNTI_64mr\000MOVNTImr\000MOVNTImr_Int\000MOVNTPDmr\000MOVNTPD"
+ "mr_Int\000MOVNTPSmr\000MOVNTPSmr_Int\000MOVPC32r\000MOVPDI2DImr\000MOVP"
+ "DI2DIrr\000MOVPQI2QImr\000MOVPQIto64rr\000MOVQI2PQIrm\000MOVQxrxr\000MO"
+ "VSB\000MOVSD\000MOVSDmr\000MOVSDrm\000MOVSDrr\000MOVSDto64mr\000MOVSDto"
+ "64rr\000MOVSHDUPrm\000MOVSHDUPrr\000MOVSLDUPrm\000MOVSLDUPrr\000MOVSS2D"
+ "Imr\000MOVSS2DIrr\000MOVSSmr\000MOVSSrm\000MOVSSrr\000MOVSW\000MOVSX16r"
+ "m8\000MOVSX16rm8W\000MOVSX16rr8\000MOVSX16rr8W\000MOVSX32rm16\000MOVSX3"
+ "2rm8\000MOVSX32rr16\000MOVSX32rr8\000MOVSX64rm16\000MOVSX64rm32\000MOVS"
+ "X64rm8\000MOVSX64rr16\000MOVSX64rr32\000MOVSX64rr8\000MOVUPDmr\000MOVUP"
+ "Dmr_Int\000MOVUPDrm\000MOVUPDrm_Int\000MOVUPDrr\000MOVUPSmr\000MOVUPSmr"
+ "_Int\000MOVUPSrm\000MOVUPSrm_Int\000MOVUPSrr\000MOVZDI2PDIrm\000MOVZDI2"
+ "PDIrr\000MOVZPQILo2PQIrm\000MOVZPQILo2PQIrr\000MOVZQI2PQIrm\000MOVZQI2P"
+ "QIrr\000MOVZX16rm8\000MOVZX16rm8W\000MOVZX16rr8\000MOVZX16rr8W\000MOVZX"
+ "32_NOREXrm8\000MOVZX32_NOREXrr8\000MOVZX32rm16\000MOVZX32rm8\000MOVZX32"
+ "rr16\000MOVZX32rr8\000MOVZX64rm16\000MOVZX64rm16_Q\000MOVZX64rm32\000MO"
+ "VZX64rm8\000MOVZX64rm8_Q\000MOVZX64rr16\000MOVZX64rr16_Q\000MOVZX64rr32"
+ "\000MOVZX64rr8\000MOVZX64rr8_Q\000MOV_Fp3232\000MOV_Fp3264\000MOV_Fp328"
+ "0\000MOV_Fp6432\000MOV_Fp6464\000MOV_Fp6480\000MOV_Fp8032\000MOV_Fp8064"
+ "\000MOV_Fp8080\000MPSADBWrmi\000MPSADBWrri\000MUL16m\000MUL16r\000MUL32"
+ "m\000MUL32r\000MUL64m\000MUL64r\000MUL8m\000MUL8r\000MULPDrm\000MULPDrr"
+ "\000MULPSrm\000MULPSrr\000MULSDrm\000MULSDrm_Int\000MULSDrr\000MULSDrr_"
+ "Int\000MULSSrm\000MULSSrm_Int\000MULSSrr\000MULSSrr_Int\000MUL_F32m\000"
+ "MUL_F64m\000MUL_FI16m\000MUL_FI32m\000MUL_FPrST0\000MUL_FST0r\000MUL_Fp"
+ "32\000MUL_Fp32m\000MUL_Fp64\000MUL_Fp64m\000MUL_Fp64m32\000MUL_Fp80\000"
+ "MUL_Fp80m32\000MUL_Fp80m64\000MUL_FpI16m32\000MUL_FpI16m64\000MUL_FpI16"
+ "m80\000MUL_FpI32m32\000MUL_FpI32m64\000MUL_FpI32m80\000MUL_FrST0\000MWA"
+ "IT\000NEG16m\000NEG16r\000NEG32m\000NEG32r\000NEG64m\000NEG64r\000NEG8m"
+ "\000NEG8r\000NOOP\000NOOPL\000NOOPW\000NOT16m\000NOT16r\000NOT32m\000NO"
+ "T32r\000NOT64m\000NOT64r\000NOT8m\000NOT8r\000OR16i16\000OR16mi\000OR16"
+ "mi8\000OR16mr\000OR16ri\000OR16ri8\000OR16rm\000OR16rr\000OR16rr_REV\000"
+ "OR32i32\000OR32mi\000OR32mi8\000OR32mr\000OR32ri\000OR32ri8\000OR32rm\000"
+ "OR32rr\000OR32rr_REV\000OR64i32\000OR64mi32\000OR64mi8\000OR64mr\000OR6"
+ "4ri32\000OR64ri8\000OR64rm\000OR64rr\000OR64rr_REV\000OR8i8\000OR8mi\000"
+ "OR8mr\000OR8ri\000OR8rm\000OR8rr\000OR8rr_REV\000ORPDrm\000ORPDrr\000OR"
+ "PSrm\000ORPSrr\000OUT16ir\000OUT16rr\000OUT32ir\000OUT32rr\000OUT8ir\000"
+ "OUT8rr\000OUTSB\000OUTSD\000OUTSW\000PABSBrm128\000PABSBrm64\000PABSBrr"
+ "128\000PABSBrr64\000PABSDrm128\000PABSDrm64\000PABSDrr128\000PABSDrr64\000"
+ "PABSWrm128\000PABSWrm64\000PABSWrr128\000PABSWrr64\000PACKSSDWrm\000PAC"
+ "KSSDWrr\000PACKSSWBrm\000PACKSSWBrr\000PACKUSDWrm\000PACKUSDWrr\000PACK"
+ "USWBrm\000PACKUSWBrr\000PADDBrm\000PADDBrr\000PADDDrm\000PADDDrr\000PAD"
+ "DQrm\000PADDQrr\000PADDSBrm\000PADDSBrr\000PADDSWrm\000PADDSWrr\000PADD"
+ "USBrm\000PADDUSBrr\000PADDUSWrm\000PADDUSWrr\000PADDWrm\000PADDWrr\000P"
+ "ALIGNR128rm\000PALIGNR128rr\000PALIGNR64rm\000PALIGNR64rr\000PANDNrm\000"
+ "PANDNrr\000PANDrm\000PANDrr\000PAVGBrm\000PAVGBrr\000PAVGWrm\000PAVGWrr"
+ "\000PBLENDVBrm0\000PBLENDVBrr0\000PBLENDWrmi\000PBLENDWrri\000PCMPEQBrm"
+ "\000PCMPEQBrr\000PCMPEQDrm\000PCMPEQDrr\000PCMPEQQrm\000PCMPEQQrr\000PC"
+ "MPEQWrm\000PCMPEQWrr\000PCMPESTRIArm\000PCMPESTRIArr\000PCMPESTRICrm\000"
+ "PCMPESTRICrr\000PCMPESTRIOrm\000PCMPESTRIOrr\000PCMPESTRISrm\000PCMPEST"
+ "RISrr\000PCMPESTRIZrm\000PCMPESTRIZrr\000PCMPESTRIrm\000PCMPESTRIrr\000"
+ "PCMPESTRM128MEM\000PCMPESTRM128REG\000PCMPESTRM128rm\000PCMPESTRM128rr\000"
+ "PCMPGTBrm\000PCMPGTBrr\000PCMPGTDrm\000PCMPGTDrr\000PCMPGTQrm\000PCMPGT"
+ "Qrr\000PCMPGTWrm\000PCMPGTWrr\000PCMPISTRIArm\000PCMPISTRIArr\000PCMPIS"
+ "TRICrm\000PCMPISTRICrr\000PCMPISTRIOrm\000PCMPISTRIOrr\000PCMPISTRISrm\000"
+ "PCMPISTRISrr\000PCMPISTRIZrm\000PCMPISTRIZrr\000PCMPISTRIrm\000PCMPISTR"
+ "Irr\000PCMPISTRM128MEM\000PCMPISTRM128REG\000PCMPISTRM128rm\000PCMPISTR"
+ "M128rr\000PEXTRBmr\000PEXTRBrr\000PEXTRDmr\000PEXTRDrr\000PEXTRQmr\000P"
+ "EXTRQrr\000PEXTRWmr\000PEXTRWri\000PHADDDrm128\000PHADDDrm64\000PHADDDr"
+ "r128\000PHADDDrr64\000PHADDSWrm128\000PHADDSWrm64\000PHADDSWrr128\000PH"
+ "ADDSWrr64\000PHADDWrm128\000PHADDWrm64\000PHADDWrr128\000PHADDWrr64\000"
+ "PHMINPOSUWrm128\000PHMINPOSUWrr128\000PHSUBDrm128\000PHSUBDrm64\000PHSU"
+ "BDrr128\000PHSUBDrr64\000PHSUBSWrm128\000PHSUBSWrm64\000PHSUBSWrr128\000"
+ "PHSUBSWrr64\000PHSUBWrm128\000PHSUBWrm64\000PHSUBWrr128\000PHSUBWrr64\000"
+ "PINSRBrm\000PINSRBrr\000PINSRDrm\000PINSRDrr\000PINSRQrm\000PINSRQrr\000"
+ "PINSRWrmi\000PINSRWrri\000PMADDUBSWrm128\000PMADDUBSWrm64\000PMADDUBSWr"
+ "r128\000PMADDUBSWrr64\000PMADDWDrm\000PMADDWDrr\000PMAXSBrm\000PMAXSBrr"
+ "\000PMAXSDrm\000PMAXSDrr\000PMAXSWrm\000PMAXSWrr\000PMAXUBrm\000PMAXUBr"
+ "r\000PMAXUDrm\000PMAXUDrr\000PMAXUWrm\000PMAXUWrr\000PMINSBrm\000PMINSB"
+ "rr\000PMINSDrm\000PMINSDrr\000PMINSWrm\000PMINSWrr\000PMINUBrm\000PMINU"
+ "Brr\000PMINUDrm\000PMINUDrr\000PMINUWrm\000PMINUWrr\000PMOVMSKBrr\000PM"
+ "OVSXBDrm\000PMOVSXBDrr\000PMOVSXBQrm\000PMOVSXBQrr\000PMOVSXBWrm\000PMO"
+ "VSXBWrr\000PMOVSXDQrm\000PMOVSXDQrr\000PMOVSXWDrm\000PMOVSXWDrr\000PMOV"
+ "SXWQrm\000PMOVSXWQrr\000PMOVZXBDrm\000PMOVZXBDrr\000PMOVZXBQrm\000PMOVZ"
+ "XBQrr\000PMOVZXBWrm\000PMOVZXBWrr\000PMOVZXDQrm\000PMOVZXDQrr\000PMOVZX"
+ "WDrm\000PMOVZXWDrr\000PMOVZXWQrm\000PMOVZXWQrr\000PMULDQrm\000PMULDQrr\000"
+ "PMULHRSWrm128\000PMULHRSWrm64\000PMULHRSWrr128\000PMULHRSWrr64\000PMULH"
+ "UWrm\000PMULHUWrr\000PMULHWrm\000PMULHWrr\000PMULLDrm\000PMULLDrm_int\000"
+ "PMULLDrr\000PMULLDrr_int\000PMULLWrm\000PMULLWrr\000PMULUDQrm\000PMULUD"
+ "Qrr\000POP16r\000POP16rmm\000POP16rmr\000POP32r\000POP32rmm\000POP32rmr"
+ "\000POP64r\000POP64rmm\000POP64rmr\000POPCNT16rm\000POPCNT16rr\000POPCN"
+ "T32rm\000POPCNT32rr\000POPCNT64rm\000POPCNT64rr\000POPF\000POPFD\000POP"
+ "FQ\000POPFS16\000POPFS32\000POPFS64\000POPGS16\000POPGS32\000POPGS64\000"
+ "PORrm\000PORrr\000PREFETCHNTA\000PREFETCHT0\000PREFETCHT1\000PREFETCHT2"
+ "\000PSADBWrm\000PSADBWrr\000PSHUFBrm128\000PSHUFBrm64\000PSHUFBrr128\000"
+ "PSHUFBrr64\000PSHUFDmi\000PSHUFDri\000PSHUFHWmi\000PSHUFHWri\000PSHUFLW"
+ "mi\000PSHUFLWri\000PSIGNBrm128\000PSIGNBrm64\000PSIGNBrr128\000PSIGNBrr"
+ "64\000PSIGNDrm128\000PSIGNDrm64\000PSIGNDrr128\000PSIGNDrr64\000PSIGNWr"
+ "m128\000PSIGNWrm64\000PSIGNWrr128\000PSIGNWrr64\000PSLLDQri\000PSLLDri\000"
+ "PSLLDrm\000PSLLDrr\000PSLLQri\000PSLLQrm\000PSLLQrr\000PSLLWri\000PSLLW"
+ "rm\000PSLLWrr\000PSRADri\000PSRADrm\000PSRADrr\000PSRAWri\000PSRAWrm\000"
+ "PSRAWrr\000PSRLDQri\000PSRLDri\000PSRLDrm\000PSRLDrr\000PSRLQri\000PSRL"
+ "Qrm\000PSRLQrr\000PSRLWri\000PSRLWrm\000PSRLWrr\000PSUBBrm\000PSUBBrr\000"
+ "PSUBDrm\000PSUBDrr\000PSUBQrm\000PSUBQrr\000PSUBSBrm\000PSUBSBrr\000PSU"
+ "BSWrm\000PSUBSWrr\000PSUBUSBrm\000PSUBUSBrr\000PSUBUSWrm\000PSUBUSWrr\000"
+ "PSUBWrm\000PSUBWrr\000PTESTrm\000PTESTrr\000PUNPCKHBWrm\000PUNPCKHBWrr\000"
+ "PUNPCKHDQrm\000PUNPCKHDQrr\000PUNPCKHQDQrm\000PUNPCKHQDQrr\000PUNPCKHWD"
+ "rm\000PUNPCKHWDrr\000PUNPCKLBWrm\000PUNPCKLBWrr\000PUNPCKLDQrm\000PUNPC"
+ "KLDQrr\000PUNPCKLQDQrm\000PUNPCKLQDQrr\000PUNPCKLWDrm\000PUNPCKLWDrr\000"
+ "PUSH16r\000PUSH16rmm\000PUSH16rmr\000PUSH32i16\000PUSH32i32\000PUSH32i8"
+ "\000PUSH32r\000PUSH32rmm\000PUSH32rmr\000PUSH64i16\000PUSH64i32\000PUSH"
+ "64i8\000PUSH64r\000PUSH64rmm\000PUSH64rmr\000PUSHF\000PUSHFD\000PUSHFQ6"
+ "4\000PUSHFS16\000PUSHFS32\000PUSHFS64\000PUSHGS16\000PUSHGS32\000PUSHGS"
+ "64\000PXORrm\000PXORrr\000RCL16m1\000RCL16mCL\000RCL16mi\000RCL16r1\000"
+ "RCL16rCL\000RCL16ri\000RCL32m1\000RCL32mCL\000RCL32mi\000RCL32r1\000RCL"
+ "32rCL\000RCL32ri\000RCL64m1\000RCL64mCL\000RCL64mi\000RCL64r1\000RCL64r"
+ "CL\000RCL64ri\000RCL8m1\000RCL8mCL\000RCL8mi\000RCL8r1\000RCL8rCL\000RC"
+ "L8ri\000RCPPSm\000RCPPSm_Int\000RCPPSr\000RCPPSr_Int\000RCPSSm\000RCPSS"
+ "m_Int\000RCPSSr\000RCPSSr_Int\000RCR16m1\000RCR16mCL\000RCR16mi\000RCR1"
+ "6r1\000RCR16rCL\000RCR16ri\000RCR32m1\000RCR32mCL\000RCR32mi\000RCR32r1"
+ "\000RCR32rCL\000RCR32ri\000RCR64m1\000RCR64mCL\000RCR64mi\000RCR64r1\000"
+ "RCR64rCL\000RCR64ri\000RCR8m1\000RCR8mCL\000RCR8mi\000RCR8r1\000RCR8rCL"
+ "\000RCR8ri\000RDMSR\000RDPMC\000RDTSC\000RDTSCP\000REPNE_PREFIX\000REP_"
+ "MOVSB\000REP_MOVSD\000REP_MOVSQ\000REP_MOVSW\000REP_PREFIX\000REP_STOSB"
+ "\000REP_STOSD\000REP_STOSQ\000REP_STOSW\000RET\000RETI\000ROL16m1\000RO"
+ "L16mCL\000ROL16mi\000ROL16r1\000ROL16rCL\000ROL16ri\000ROL32m1\000ROL32"
+ "mCL\000ROL32mi\000ROL32r1\000ROL32rCL\000ROL32ri\000ROL64m1\000ROL64mCL"
+ "\000ROL64mi\000ROL64r1\000ROL64rCL\000ROL64ri\000ROL8m1\000ROL8mCL\000R"
+ "OL8mi\000ROL8r1\000ROL8rCL\000ROL8ri\000ROR16m1\000ROR16mCL\000ROR16mi\000"
+ "ROR16r1\000ROR16rCL\000ROR16ri\000ROR32m1\000ROR32mCL\000ROR32mi\000ROR"
+ "32r1\000ROR32rCL\000ROR32ri\000ROR64m1\000ROR64mCL\000ROR64mi\000ROR64r"
+ "1\000ROR64rCL\000ROR64ri\000ROR8m1\000ROR8mCL\000ROR8mi\000ROR8r1\000RO"
+ "R8rCL\000ROR8ri\000ROUNDPDm_Int\000ROUNDPDr_Int\000ROUNDPSm_Int\000ROUN"
+ "DPSr_Int\000ROUNDSDm_Int\000ROUNDSDr_Int\000ROUNDSSm_Int\000ROUNDSSr_In"
+ "t\000RSM\000RSQRTPSm\000RSQRTPSm_Int\000RSQRTPSr\000RSQRTPSr_Int\000RSQ"
+ "RTSSm\000RSQRTSSm_Int\000RSQRTSSr\000RSQRTSSr_Int\000SAHF\000SAR16m1\000"
+ "SAR16mCL\000SAR16mi\000SAR16r1\000SAR16rCL\000SAR16ri\000SAR32m1\000SAR"
+ "32mCL\000SAR32mi\000SAR32r1\000SAR32rCL\000SAR32ri\000SAR64m1\000SAR64m"
+ "CL\000SAR64mi\000SAR64r1\000SAR64rCL\000SAR64ri\000SAR8m1\000SAR8mCL\000"
+ "SAR8mi\000SAR8r1\000SAR8rCL\000SAR8ri\000SBB16i16\000SBB16mi\000SBB16mi"
+ "8\000SBB16mr\000SBB16ri\000SBB16ri8\000SBB16rm\000SBB16rr\000SBB16rr_RE"
+ "V\000SBB32i32\000SBB32mi\000SBB32mi8\000SBB32mr\000SBB32ri\000SBB32ri8\000"
+ "SBB32rm\000SBB32rr\000SBB32rr_REV\000SBB64i32\000SBB64mi32\000SBB64mi8\000"
+ "SBB64mr\000SBB64ri32\000SBB64ri8\000SBB64rm\000SBB64rr\000SBB64rr_REV\000"
+ "SBB8i8\000SBB8mi\000SBB8mr\000SBB8ri\000SBB8rm\000SBB8rr\000SBB8rr_REV\000"
+ "SCAS16\000SCAS32\000SCAS64\000SCAS8\000SETAEm\000SETAEr\000SETAm\000SET"
+ "Ar\000SETBEm\000SETBEr\000SETB_C16r\000SETB_C32r\000SETB_C64r\000SETB_C"
+ "8r\000SETBm\000SETBr\000SETEm\000SETEr\000SETGEm\000SETGEr\000SETGm\000"
+ "SETGr\000SETLEm\000SETLEr\000SETLm\000SETLr\000SETNEm\000SETNEr\000SETN"
+ "Om\000SETNOr\000SETNPm\000SETNPr\000SETNSm\000SETNSr\000SETOm\000SETOr\000"
+ "SETPm\000SETPr\000SETSm\000SETSr\000SFENCE\000SGDTm\000SHL16m1\000SHL16"
+ "mCL\000SHL16mi\000SHL16r1\000SHL16rCL\000SHL16ri\000SHL32m1\000SHL32mCL"
+ "\000SHL32mi\000SHL32r1\000SHL32rCL\000SHL32ri\000SHL64m1\000SHL64mCL\000"
+ "SHL64mi\000SHL64r1\000SHL64rCL\000SHL64ri\000SHL8m1\000SHL8mCL\000SHL8m"
+ "i\000SHL8r1\000SHL8rCL\000SHL8ri\000SHLD16mrCL\000SHLD16mri8\000SHLD16r"
+ "rCL\000SHLD16rri8\000SHLD32mrCL\000SHLD32mri8\000SHLD32rrCL\000SHLD32rr"
+ "i8\000SHLD64mrCL\000SHLD64mri8\000SHLD64rrCL\000SHLD64rri8\000SHR16m1\000"
+ "SHR16mCL\000SHR16mi\000SHR16r1\000SHR16rCL\000SHR16ri\000SHR32m1\000SHR"
+ "32mCL\000SHR32mi\000SHR32r1\000SHR32rCL\000SHR32ri\000SHR64m1\000SHR64m"
+ "CL\000SHR64mi\000SHR64r1\000SHR64rCL\000SHR64ri\000SHR8m1\000SHR8mCL\000"
+ "SHR8mi\000SHR8r1\000SHR8rCL\000SHR8ri\000SHRD16mrCL\000SHRD16mri8\000SH"
+ "RD16rrCL\000SHRD16rri8\000SHRD32mrCL\000SHRD32mri8\000SHRD32rrCL\000SHR"
+ "D32rri8\000SHRD64mrCL\000SHRD64mri8\000SHRD64rrCL\000SHRD64rri8\000SHUF"
+ "PDrmi\000SHUFPDrri\000SHUFPSrmi\000SHUFPSrri\000SIDTm\000SIN_F\000SIN_F"
+ "p32\000SIN_Fp64\000SIN_Fp80\000SLDT16m\000SLDT16r\000SLDT64m\000SLDT64r"
+ "\000SMSW16m\000SMSW16r\000SMSW32r\000SMSW64r\000SQRTPDm\000SQRTPDm_Int\000"
+ "SQRTPDr\000SQRTPDr_Int\000SQRTPSm\000SQRTPSm_Int\000SQRTPSr\000SQRTPSr_"
+ "Int\000SQRTSDm\000SQRTSDm_Int\000SQRTSDr\000SQRTSDr_Int\000SQRTSSm\000S"
+ "QRTSSm_Int\000SQRTSSr\000SQRTSSr_Int\000SQRT_F\000SQRT_Fp32\000SQRT_Fp6"
+ "4\000SQRT_Fp80\000SS_PREFIX\000STC\000STD\000STI\000STMXCSR\000STOSB\000"
+ "STOSD\000STOSW\000STRm\000STRr\000ST_F32m\000ST_F64m\000ST_FP32m\000ST_"
+ "FP64m\000ST_FP80m\000ST_FPrr\000ST_Fp32m\000ST_Fp64m\000ST_Fp64m32\000S"
+ "T_Fp80m32\000ST_Fp80m64\000ST_FpP32m\000ST_FpP64m\000ST_FpP64m32\000ST_"
+ "FpP80m\000ST_FpP80m32\000ST_FpP80m64\000ST_Frr\000SUB16i16\000SUB16mi\000"
+ "SUB16mi8\000SUB16mr\000SUB16ri\000SUB16ri8\000SUB16rm\000SUB16rr\000SUB"
+ "16rr_REV\000SUB32i32\000SUB32mi\000SUB32mi8\000SUB32mr\000SUB32ri\000SU"
+ "B32ri8\000SUB32rm\000SUB32rr\000SUB32rr_REV\000SUB64i32\000SUB64mi32\000"
+ "SUB64mi8\000SUB64mr\000SUB64ri32\000SUB64ri8\000SUB64rm\000SUB64rr\000S"
+ "UB64rr_REV\000SUB8i8\000SUB8mi\000SUB8mr\000SUB8ri\000SUB8rm\000SUB8rr\000"
+ "SUB8rr_REV\000SUBPDrm\000SUBPDrr\000SUBPSrm\000SUBPSrr\000SUBR_F32m\000"
+ "SUBR_F64m\000SUBR_FI16m\000SUBR_FI32m\000SUBR_FPrST0\000SUBR_FST0r\000S"
+ "UBR_Fp32m\000SUBR_Fp64m\000SUBR_Fp64m32\000SUBR_Fp80m32\000SUBR_Fp80m64"
+ "\000SUBR_FpI16m32\000SUBR_FpI16m64\000SUBR_FpI16m80\000SUBR_FpI32m32\000"
+ "SUBR_FpI32m64\000SUBR_FpI32m80\000SUBR_FrST0\000SUBSDrm\000SUBSDrm_Int\000"
+ "SUBSDrr\000SUBSDrr_Int\000SUBSSrm\000SUBSSrm_Int\000SUBSSrr\000SUBSSrr_"
+ "Int\000SUB_F32m\000SUB_F64m\000SUB_FI16m\000SUB_FI32m\000SUB_FPrST0\000"
+ "SUB_FST0r\000SUB_Fp32\000SUB_Fp32m\000SUB_Fp64\000SUB_Fp64m\000SUB_Fp64"
+ "m32\000SUB_Fp80\000SUB_Fp80m32\000SUB_Fp80m64\000SUB_FpI16m32\000SUB_Fp"
+ "I16m64\000SUB_FpI16m80\000SUB_FpI32m32\000SUB_FpI32m64\000SUB_FpI32m80\000"
+ "SUB_FrST0\000SWAPGS\000SYSCALL\000SYSENTER\000SYSEXIT\000SYSEXIT64\000S"
+ "YSRET\000TAILJMPd\000TAILJMPm\000TAILJMPr\000TAILJMPr64\000TCRETURNdi\000"
+ "TCRETURNdi64\000TCRETURNri\000TCRETURNri64\000TEST16i16\000TEST16mi\000"
+ "TEST16ri\000TEST16rm\000TEST16rr\000TEST32i32\000TEST32mi\000TEST32ri\000"
+ "TEST32rm\000TEST32rr\000TEST64i32\000TEST64mi32\000TEST64ri32\000TEST64"
+ "rm\000TEST64rr\000TEST8i8\000TEST8mi\000TEST8ri\000TEST8rm\000TEST8rr\000"
+ "TLS_addr32\000TLS_addr64\000TRAP\000TST_F\000TST_Fp32\000TST_Fp64\000TS"
+ "T_Fp80\000UCOMISDrm\000UCOMISDrr\000UCOMISSrm\000UCOMISSrr\000UCOM_FIPr"
+ "\000UCOM_FIr\000UCOM_FPPr\000UCOM_FPr\000UCOM_FpIr32\000UCOM_FpIr64\000"
+ "UCOM_FpIr80\000UCOM_Fpr32\000UCOM_Fpr64\000UCOM_Fpr80\000UCOM_Fr\000UNP"
+ "CKHPDrm\000UNPCKHPDrr\000UNPCKHPSrm\000UNPCKHPSrr\000UNPCKLPDrm\000UNPC"
+ "KLPDrr\000UNPCKLPSrm\000UNPCKLPSrr\000VASTART_SAVE_XMM_REGS\000VERRm\000"
+ "VERRr\000VERWm\000VERWr\000VMCALL\000VMCLEARm\000VMLAUNCH\000VMPTRLDm\000"
+ "VMPTRSTm\000VMREAD32rm\000VMREAD32rr\000VMREAD64rm\000VMREAD64rr\000VMR"
+ "ESUME\000VMWRITE32rm\000VMWRITE32rr\000VMWRITE64rm\000VMWRITE64rr\000VM"
+ "XOFF\000VMXON\000V_SET0\000V_SETALLONES\000WAIT\000WBINVD\000WINCALL64m"
+ "\000WINCALL64pcrel32\000WINCALL64r\000WRMSR\000XADD16rm\000XADD16rr\000"
+ "XADD32rm\000XADD32rr\000XADD64rm\000XADD64rr\000XADD8rm\000XADD8rr\000X"
+ "CHG16ar\000XCHG16rm\000XCHG16rr\000XCHG32ar\000XCHG32rm\000XCHG32rr\000"
+ "XCHG64ar\000XCHG64rm\000XCHG64rr\000XCHG8rm\000XCHG8rr\000XCH_F\000XLAT"
+ "\000XOR16i16\000XOR16mi\000XOR16mi8\000XOR16mr\000XOR16ri\000XOR16ri8\000"
+ "XOR16rm\000XOR16rr\000XOR16rr_REV\000XOR32i32\000XOR32mi\000XOR32mi8\000"
+ "XOR32mr\000XOR32ri\000XOR32ri8\000XOR32rm\000XOR32rr\000XOR32rr_REV\000"
+ "XOR64i32\000XOR64mi32\000XOR64mi8\000XOR64mr\000XOR64ri32\000XOR64ri8\000"
+ "XOR64rm\000XOR64rr\000XOR64rr_REV\000XOR8i8\000XOR8mi\000XOR8mr\000XOR8"
+ "ri\000XOR8rm\000XOR8rr\000XOR8rr_REV\000XORPDrm\000XORPDrr\000XORPSrm\000"
+ "XORPSrr\000";
return Strs+InstAsmOffset[Opcode];
}
diff --git a/libclamav/c++/X86GenAsmWriter1.inc b/libclamav/c++/X86GenAsmWriter1.inc
index 813e673..22a3e54 100644
--- a/libclamav/c++/X86GenAsmWriter1.inc
+++ b/libclamav/c++/X86GenAsmWriter1.inc
@@ -1091,22 +1091,23 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
138546414U, // MAXSSrr
138546414U, // MAXSSrr_Int
3317U, // MFENCE
- 139201788U, // MINPDrm
- 139201788U, // MINPDrm_Int
- 138546428U, // MINPDrr
- 138546428U, // MINPDrr_Int
- 139201795U, // MINPSrm
- 139201795U, // MINPSrm_Int
- 138546435U, // MINPSrr
- 138546435U, // MINPSrr_Int
- 139332874U, // MINSDrm
- 139332874U, // MINSDrm_Int
- 138546442U, // MINSDrr
- 138546442U, // MINSDrr_Int
- 139463953U, // MINSSrm
- 139463953U, // MINSSrm_Int
- 138546449U, // MINSSrr
- 138546449U, // MINSSrr_Int
+ 3324U, // MINGW_ALLOCA
+ 139201815U, // MINPDrm
+ 139201815U, // MINPDrm_Int
+ 138546455U, // MINPDrr
+ 138546455U, // MINPDrr_Int
+ 139201822U, // MINPSrm
+ 139201822U, // MINPSrm_Int
+ 138546462U, // MINPSrr
+ 138546462U, // MINPSrr_Int
+ 139332901U, // MINSDrm
+ 139332901U, // MINSDrm_Int
+ 138546469U, // MINSDrr
+ 138546469U, // MINSDrr_Int
+ 139463980U, // MINSSrm
+ 139463980U, // MINSSrm_Int
+ 138546476U, // MINSSrr
+ 138546476U, // MINSSrr_Int
140380932U, // MMX_CVTPD2PIrm
139856644U, // MMX_CVTPD2PIrr
140118798U, // MMX_CVTPI2PDrm
@@ -1119,335 +1120,335 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
139856695U, // MMX_CVTTPD2PIrr
140512066U, // MMX_CVTTPS2PIrm
139856706U, // MMX_CVTTPS2PIrr
- 3352U, // MMX_EMMS
- 3357U, // MMX_FEMMS
- 139857187U, // MMX_MASKMOVQ
- 139857187U, // MMX_MASKMOVQ64
- 139857197U, // MMX_MOVD64from64rr
- 139857197U, // MMX_MOVD64grr
- 406850861U, // MMX_MOVD64mr
- 139988269U, // MMX_MOVD64rm
- 139857197U, // MMX_MOVD64rr
- 139857197U, // MMX_MOVD64rrv164
- 139857197U, // MMX_MOVD64to64rr
- 139857203U, // MMX_MOVDQ2Qrr
- 541068604U, // MMX_MOVNTQmr
- 139857220U, // MMX_MOVQ2DQrr
- 139857220U, // MMX_MOVQ2FR64rr
- 541068621U, // MMX_MOVQ64gmr
- 541068621U, // MMX_MOVQ64mr
- 140119373U, // MMX_MOVQ64rm
- 139857229U, // MMX_MOVQ64rr
- 139988269U, // MMX_MOVZDI2PDIrm
- 139857197U, // MMX_MOVZDI2PDIrr
- 138939731U, // MMX_PACKSSDWrm
- 138546515U, // MMX_PACKSSDWrr
- 138939741U, // MMX_PACKSSWBrm
- 138546525U, // MMX_PACKSSWBrr
- 138939751U, // MMX_PACKUSWBrm
- 138546535U, // MMX_PACKUSWBrr
- 138939761U, // MMX_PADDBrm
- 138546545U, // MMX_PADDBrr
- 138939768U, // MMX_PADDDrm
- 138546552U, // MMX_PADDDrr
- 138939775U, // MMX_PADDQrm
- 138546559U, // MMX_PADDQrr
- 138939782U, // MMX_PADDSBrm
- 138546566U, // MMX_PADDSBrr
- 138939790U, // MMX_PADDSWrm
- 138546574U, // MMX_PADDSWrr
- 138939798U, // MMX_PADDUSBrm
- 138546582U, // MMX_PADDUSBrr
- 138939807U, // MMX_PADDUSWrm
- 138546591U, // MMX_PADDUSWrr
- 138939816U, // MMX_PADDWrm
- 138546600U, // MMX_PADDWrr
- 138939823U, // MMX_PANDNrm
- 138546607U, // MMX_PANDNrr
- 138939830U, // MMX_PANDrm
- 138546614U, // MMX_PANDrr
- 138939836U, // MMX_PAVGBrm
- 138546620U, // MMX_PAVGBrr
- 138939843U, // MMX_PAVGWrm
- 138546627U, // MMX_PAVGWrr
- 138939850U, // MMX_PCMPEQBrm
- 138546634U, // MMX_PCMPEQBrr
- 138939859U, // MMX_PCMPEQDrm
- 138546643U, // MMX_PCMPEQDrr
- 138939868U, // MMX_PCMPEQWrm
- 138546652U, // MMX_PCMPEQWrr
- 138939877U, // MMX_PCMPGTBrm
- 138546661U, // MMX_PCMPGTBrr
- 138939886U, // MMX_PCMPGTDrm
- 138546670U, // MMX_PCMPGTDrr
- 138939895U, // MMX_PCMPGTWrm
- 138546679U, // MMX_PCMPGTWrr
- 139873792U, // MMX_PEXTRWri
- 138694152U, // MMX_PINSRWrmi
- 138563080U, // MMX_PINSRWrri
- 138939920U, // MMX_PMADDWDrm
- 138546704U, // MMX_PMADDWDrr
- 138939929U, // MMX_PMAXSWrm
- 138546713U, // MMX_PMAXSWrr
- 138939937U, // MMX_PMAXUBrm
- 138546721U, // MMX_PMAXUBrr
- 138939945U, // MMX_PMINSWrm
- 138546729U, // MMX_PMINSWrr
- 138939953U, // MMX_PMINUBrm
- 138546737U, // MMX_PMINUBrr
- 139857465U, // MMX_PMOVMSKBrr
- 138939971U, // MMX_PMULHUWrm
- 138546755U, // MMX_PMULHUWrr
- 138939980U, // MMX_PMULHWrm
- 138546764U, // MMX_PMULHWrr
- 138939988U, // MMX_PMULLWrm
- 138546772U, // MMX_PMULLWrr
- 138939996U, // MMX_PMULUDQrm
- 138546780U, // MMX_PMULUDQrr
- 138940005U, // MMX_PORrm
- 138546789U, // MMX_PORrr
- 138940010U, // MMX_PSADBWrm
- 138546794U, // MMX_PSADBWrr
- 140136050U, // MMX_PSHUFWmi
- 139873906U, // MMX_PSHUFWri
- 138546810U, // MMX_PSLLDri
- 138940026U, // MMX_PSLLDrm
- 138546810U, // MMX_PSLLDrr
- 138546817U, // MMX_PSLLQri
- 138940033U, // MMX_PSLLQrm
- 138546817U, // MMX_PSLLQrr
- 138546824U, // MMX_PSLLWri
- 138940040U, // MMX_PSLLWrm
- 138546824U, // MMX_PSLLWrr
- 138546831U, // MMX_PSRADri
- 138940047U, // MMX_PSRADrm
- 138546831U, // MMX_PSRADrr
- 138546838U, // MMX_PSRAWri
- 138940054U, // MMX_PSRAWrm
- 138546838U, // MMX_PSRAWrr
- 138546845U, // MMX_PSRLDri
- 138940061U, // MMX_PSRLDrm
- 138546845U, // MMX_PSRLDrr
- 138546852U, // MMX_PSRLQri
- 138940068U, // MMX_PSRLQrm
- 138546852U, // MMX_PSRLQrr
- 138546859U, // MMX_PSRLWri
- 138940075U, // MMX_PSRLWrm
- 138546859U, // MMX_PSRLWrr
- 138940082U, // MMX_PSUBBrm
- 138546866U, // MMX_PSUBBrr
- 138940089U, // MMX_PSUBDrm
- 138546873U, // MMX_PSUBDrr
- 138940096U, // MMX_PSUBQrm
- 138546880U, // MMX_PSUBQrr
- 138940103U, // MMX_PSUBSBrm
- 138546887U, // MMX_PSUBSBrr
- 138940111U, // MMX_PSUBSWrm
- 138546895U, // MMX_PSUBSWrr
- 138940119U, // MMX_PSUBUSBrm
- 138546903U, // MMX_PSUBUSBrr
- 138940128U, // MMX_PSUBUSWrm
- 138546912U, // MMX_PSUBUSWrr
- 138940137U, // MMX_PSUBWrm
- 138546921U, // MMX_PSUBWrr
- 138940144U, // MMX_PUNPCKHBWrm
- 138546928U, // MMX_PUNPCKHBWrr
- 138940155U, // MMX_PUNPCKHDQrm
- 138546939U, // MMX_PUNPCKHDQrr
- 138940166U, // MMX_PUNPCKHWDrm
- 138546950U, // MMX_PUNPCKHWDrr
- 138940177U, // MMX_PUNPCKLBWrm
- 138546961U, // MMX_PUNPCKLBWrr
- 138940188U, // MMX_PUNPCKLDQrm
- 138546972U, // MMX_PUNPCKLDQrr
- 138940199U, // MMX_PUNPCKLWDrm
- 138546983U, // MMX_PUNPCKLWDrr
- 138940210U, // MMX_PXORrm
- 138546994U, // MMX_PXORrr
+ 3379U, // MMX_EMMS
+ 3384U, // MMX_FEMMS
+ 139857214U, // MMX_MASKMOVQ
+ 139857214U, // MMX_MASKMOVQ64
+ 139857224U, // MMX_MOVD64from64rr
+ 139857224U, // MMX_MOVD64grr
+ 406850888U, // MMX_MOVD64mr
+ 139988296U, // MMX_MOVD64rm
+ 139857224U, // MMX_MOVD64rr
+ 139857224U, // MMX_MOVD64rrv164
+ 139857224U, // MMX_MOVD64to64rr
+ 139857230U, // MMX_MOVDQ2Qrr
+ 541068631U, // MMX_MOVNTQmr
+ 139857247U, // MMX_MOVQ2DQrr
+ 139857247U, // MMX_MOVQ2FR64rr
+ 541068648U, // MMX_MOVQ64gmr
+ 541068648U, // MMX_MOVQ64mr
+ 140119400U, // MMX_MOVQ64rm
+ 139857256U, // MMX_MOVQ64rr
+ 139988296U, // MMX_MOVZDI2PDIrm
+ 139857224U, // MMX_MOVZDI2PDIrr
+ 138939758U, // MMX_PACKSSDWrm
+ 138546542U, // MMX_PACKSSDWrr
+ 138939768U, // MMX_PACKSSWBrm
+ 138546552U, // MMX_PACKSSWBrr
+ 138939778U, // MMX_PACKUSWBrm
+ 138546562U, // MMX_PACKUSWBrr
+ 138939788U, // MMX_PADDBrm
+ 138546572U, // MMX_PADDBrr
+ 138939795U, // MMX_PADDDrm
+ 138546579U, // MMX_PADDDrr
+ 138939802U, // MMX_PADDQrm
+ 138546586U, // MMX_PADDQrr
+ 138939809U, // MMX_PADDSBrm
+ 138546593U, // MMX_PADDSBrr
+ 138939817U, // MMX_PADDSWrm
+ 138546601U, // MMX_PADDSWrr
+ 138939825U, // MMX_PADDUSBrm
+ 138546609U, // MMX_PADDUSBrr
+ 138939834U, // MMX_PADDUSWrm
+ 138546618U, // MMX_PADDUSWrr
+ 138939843U, // MMX_PADDWrm
+ 138546627U, // MMX_PADDWrr
+ 138939850U, // MMX_PANDNrm
+ 138546634U, // MMX_PANDNrr
+ 138939857U, // MMX_PANDrm
+ 138546641U, // MMX_PANDrr
+ 138939863U, // MMX_PAVGBrm
+ 138546647U, // MMX_PAVGBrr
+ 138939870U, // MMX_PAVGWrm
+ 138546654U, // MMX_PAVGWrr
+ 138939877U, // MMX_PCMPEQBrm
+ 138546661U, // MMX_PCMPEQBrr
+ 138939886U, // MMX_PCMPEQDrm
+ 138546670U, // MMX_PCMPEQDrr
+ 138939895U, // MMX_PCMPEQWrm
+ 138546679U, // MMX_PCMPEQWrr
+ 138939904U, // MMX_PCMPGTBrm
+ 138546688U, // MMX_PCMPGTBrr
+ 138939913U, // MMX_PCMPGTDrm
+ 138546697U, // MMX_PCMPGTDrr
+ 138939922U, // MMX_PCMPGTWrm
+ 138546706U, // MMX_PCMPGTWrr
+ 139873819U, // MMX_PEXTRWri
+ 138694179U, // MMX_PINSRWrmi
+ 138563107U, // MMX_PINSRWrri
+ 138939947U, // MMX_PMADDWDrm
+ 138546731U, // MMX_PMADDWDrr
+ 138939956U, // MMX_PMAXSWrm
+ 138546740U, // MMX_PMAXSWrr
+ 138939964U, // MMX_PMAXUBrm
+ 138546748U, // MMX_PMAXUBrr
+ 138939972U, // MMX_PMINSWrm
+ 138546756U, // MMX_PMINSWrr
+ 138939980U, // MMX_PMINUBrm
+ 138546764U, // MMX_PMINUBrr
+ 139857492U, // MMX_PMOVMSKBrr
+ 138939998U, // MMX_PMULHUWrm
+ 138546782U, // MMX_PMULHUWrr
+ 138940007U, // MMX_PMULHWrm
+ 138546791U, // MMX_PMULHWrr
+ 138940015U, // MMX_PMULLWrm
+ 138546799U, // MMX_PMULLWrr
+ 138940023U, // MMX_PMULUDQrm
+ 138546807U, // MMX_PMULUDQrr
+ 138940032U, // MMX_PORrm
+ 138546816U, // MMX_PORrr
+ 138940037U, // MMX_PSADBWrm
+ 138546821U, // MMX_PSADBWrr
+ 140136077U, // MMX_PSHUFWmi
+ 139873933U, // MMX_PSHUFWri
+ 138546837U, // MMX_PSLLDri
+ 138940053U, // MMX_PSLLDrm
+ 138546837U, // MMX_PSLLDrr
+ 138546844U, // MMX_PSLLQri
+ 138940060U, // MMX_PSLLQrm
+ 138546844U, // MMX_PSLLQrr
+ 138546851U, // MMX_PSLLWri
+ 138940067U, // MMX_PSLLWrm
+ 138546851U, // MMX_PSLLWrr
+ 138546858U, // MMX_PSRADri
+ 138940074U, // MMX_PSRADrm
+ 138546858U, // MMX_PSRADrr
+ 138546865U, // MMX_PSRAWri
+ 138940081U, // MMX_PSRAWrm
+ 138546865U, // MMX_PSRAWrr
+ 138546872U, // MMX_PSRLDri
+ 138940088U, // MMX_PSRLDrm
+ 138546872U, // MMX_PSRLDrr
+ 138546879U, // MMX_PSRLQri
+ 138940095U, // MMX_PSRLQrm
+ 138546879U, // MMX_PSRLQrr
+ 138546886U, // MMX_PSRLWri
+ 138940102U, // MMX_PSRLWrm
+ 138546886U, // MMX_PSRLWrr
+ 138940109U, // MMX_PSUBBrm
+ 138546893U, // MMX_PSUBBrr
+ 138940116U, // MMX_PSUBDrm
+ 138546900U, // MMX_PSUBDrr
+ 138940123U, // MMX_PSUBQrm
+ 138546907U, // MMX_PSUBQrr
+ 138940130U, // MMX_PSUBSBrm
+ 138546914U, // MMX_PSUBSBrr
+ 138940138U, // MMX_PSUBSWrm
+ 138546922U, // MMX_PSUBSWrr
+ 138940146U, // MMX_PSUBUSBrm
+ 138546930U, // MMX_PSUBUSBrr
+ 138940155U, // MMX_PSUBUSWrm
+ 138546939U, // MMX_PSUBUSWrr
+ 138940164U, // MMX_PSUBWrm
+ 138546948U, // MMX_PSUBWrr
+ 138940171U, // MMX_PUNPCKHBWrm
+ 138546955U, // MMX_PUNPCKHBWrr
+ 138940182U, // MMX_PUNPCKHDQrm
+ 138546966U, // MMX_PUNPCKHDQrr
+ 138940193U, // MMX_PUNPCKHWDrm
+ 138546977U, // MMX_PUNPCKHWDrr
+ 138940204U, // MMX_PUNPCKLBWrm
+ 138546988U, // MMX_PUNPCKLBWrr
+ 138940215U, // MMX_PUNPCKLDQrm
+ 138546999U, // MMX_PUNPCKLDQrr
+ 138940226U, // MMX_PUNPCKLWDrm
+ 138547010U, // MMX_PUNPCKLWDrr
+ 138940237U, // MMX_PXORrm
+ 138547021U, // MMX_PXORrr
0U, // MMX_V_SET0
0U, // MMX_V_SETALLONES
- 3896U, // MONITOR
- 1124077376U, // MOV16ao16
- 272633664U, // MOV16mi
- 272633664U, // MOV16mr
- 272633664U, // MOV16ms
- 1073745733U, // MOV16o16a
+ 3923U, // MONITOR
+ 1124077403U, // MOV16ao16
+ 272633691U, // MOV16mi
+ 272633691U, // MOV16mr
+ 272633691U, // MOV16ms
+ 1073745760U, // MOV16o16a
0U, // MOV16r0
- 139857728U, // MOV16ri
- 139726656U, // MOV16rm
- 139857728U, // MOV16rr
- 139857728U, // MOV16rr_REV
- 139857728U, // MOV16rs
- 139726656U, // MOV16sm
- 139857728U, // MOV16sr
- 1128271680U, // MOV32ao32
- 139857728U, // MOV32cr
- 139857728U, // MOV32dr
- 406851392U, // MOV32mi
- 406851392U, // MOV32mr
- 1073745743U, // MOV32o32a
+ 139857755U, // MOV16ri
+ 139726683U, // MOV16rm
+ 139857755U, // MOV16rr
+ 139857755U, // MOV16rr_REV
+ 139857755U, // MOV16rs
+ 139726683U, // MOV16sm
+ 139857755U, // MOV16sr
+ 1128271707U, // MOV32ao32
+ 139857755U, // MOV32cr
+ 139857755U, // MOV32dr
+ 406851419U, // MOV32mi
+ 406851419U, // MOV32mr
+ 1073745770U, // MOV32o32a
0U, // MOV32r0
- 139857728U, // MOV32rc
- 139857728U, // MOV32rd
- 139857728U, // MOV32ri
- 139988800U, // MOV32rm
- 139857728U, // MOV32rr
- 139857728U, // MOV32rr_REV
- 2684358490U, // MOV64FSrm
- 2684358500U, // MOV64GSrm
- 1132465984U, // MOV64ao64
- 1132465984U, // MOV64ao8
- 139857728U, // MOV64cr
- 139857728U, // MOV64dr
- 541069120U, // MOV64mi32
- 541069120U, // MOV64mr
- 541069120U, // MOV64ms
- 1073745774U, // MOV64o64a
- 1073745774U, // MOV64o8a
+ 139857755U, // MOV32rc
+ 139857755U, // MOV32rd
+ 139857755U, // MOV32ri
+ 139988827U, // MOV32rm
+ 139857755U, // MOV32rr
+ 139857755U, // MOV32rr_REV
+ 2684358517U, // MOV64FSrm
+ 2684358527U, // MOV64GSrm
+ 1132466011U, // MOV64ao64
+ 1132466011U, // MOV64ao8
+ 139857755U, // MOV64cr
+ 139857755U, // MOV64dr
+ 541069147U, // MOV64mi32
+ 541069147U, // MOV64mr
+ 541069147U, // MOV64ms
+ 1073745801U, // MOV64o64a
+ 1073745801U, // MOV64o8a
0U, // MOV64r0
- 139857728U, // MOV64rc
- 139857728U, // MOV64rd
- 139857785U, // MOV64ri
- 139857728U, // MOV64ri32
+ 139857755U, // MOV64rc
+ 139857755U, // MOV64rd
+ 139857812U, // MOV64ri
+ 139857755U, // MOV64ri32
0U, // MOV64ri64i32
- 140119872U, // MOV64rm
- 139857728U, // MOV64rr
- 139857728U, // MOV64rr_REV
- 139857728U, // MOV64rs
- 140119872U, // MOV64sm
- 139857728U, // MOV64sr
- 139857229U, // MOV64toPQIrr
- 140119373U, // MOV64toSDrm
- 139857229U, // MOV64toSDrr
- 1136660288U, // MOV8ao8
- 675286848U, // MOV8mi
- 675286848U, // MOV8mr
- 675336000U, // MOV8mr_NOREX
- 1073745793U, // MOV8o8a
+ 140119899U, // MOV64rm
+ 139857755U, // MOV64rr
+ 139857755U, // MOV64rr_REV
+ 139857755U, // MOV64rs
+ 140119899U, // MOV64sm
+ 139857755U, // MOV64sr
+ 139857256U, // MOV64toPQIrr
+ 140119400U, // MOV64toSDrm
+ 139857256U, // MOV64toSDrr
+ 1136660315U, // MOV8ao8
+ 675286875U, // MOV8mi
+ 675286875U, // MOV8mr
+ 675336027U, // MOV8mr_NOREX
+ 1073745820U, // MOV8o8a
0U, // MOV8r0
- 139857728U, // MOV8ri
- 140250944U, // MOV8rm
- 140300096U, // MOV8rm_NOREX
- 139857728U, // MOV8rr
- 139906880U, // MOV8rr_NOREX
- 139857728U, // MOV8rr_REV
+ 139857755U, // MOV8ri
+ 140250971U, // MOV8rm
+ 140300123U, // MOV8rm_NOREX
+ 139857755U, // MOV8rr
+ 139906907U, // MOV8rr_NOREX
+ 139857755U, // MOV8rr_REV
2818574850U, // MOVAPDmr
140380674U, // MOVAPDrm
139856386U, // MOVAPDrr
2818574858U, // MOVAPSmr
140380682U, // MOVAPSrm
139856394U, // MOVAPSrr
- 140513163U, // MOVDDUPrm
- 139857803U, // MOVDDUPrr
- 139988269U, // MOVDI2PDIrm
- 139857197U, // MOVDI2PDIrr
- 139988269U, // MOVDI2SSrm
- 139857197U, // MOVDI2SSrr
- 1480593300U, // MOVDQAmr
- 140775316U, // MOVDQArm
- 139857812U, // MOVDQArr
- 1480593308U, // MOVDQUmr
- 1480593308U, // MOVDQUmr_Int
- 140775324U, // MOVDQUrm
- 140775324U, // MOVDQUrm_Int
- 138547108U, // MOVHLPSrr
- 943722413U, // MOVHPDmr
- 139333549U, // MOVHPDrm
- 943722421U, // MOVHPSmr
- 139333557U, // MOVHPSrm
- 138547133U, // MOVLHPSrr
- 943722438U, // MOVLPDmr
- 139333574U, // MOVLPDrm
- 943722446U, // MOVLPSmr
- 139333582U, // MOVLPSrm
- 541068621U, // MOVLQ128mr
- 139857878U, // MOVMSKPDrr
- 139857888U, // MOVMSKPSrr
- 140775402U, // MOVNTDQArm
- 2818576372U, // MOVNTDQ_64mr
- 2818576372U, // MOVNTDQmr
- 2818576372U, // MOVNTDQmr_Int
- 541069309U, // MOVNTI_64mr
- 406851581U, // MOVNTImr
- 406851581U, // MOVNTImr_Int
- 2818576389U, // MOVNTPDmr
- 1480593413U, // MOVNTPDmr_Int
- 2818576398U, // MOVNTPSmr
- 1480593422U, // MOVNTPSmr_Int
+ 140513190U, // MOVDDUPrm
+ 139857830U, // MOVDDUPrr
+ 139988296U, // MOVDI2PDIrm
+ 139857224U, // MOVDI2PDIrr
+ 139988296U, // MOVDI2SSrm
+ 139857224U, // MOVDI2SSrr
+ 1480593327U, // MOVDQAmr
+ 140775343U, // MOVDQArm
+ 139857839U, // MOVDQArr
+ 1480593335U, // MOVDQUmr
+ 1480593335U, // MOVDQUmr_Int
+ 140775351U, // MOVDQUrm
+ 140775351U, // MOVDQUrm_Int
+ 138547135U, // MOVHLPSrr
+ 943722440U, // MOVHPDmr
+ 139333576U, // MOVHPDrm
+ 943722448U, // MOVHPSmr
+ 139333584U, // MOVHPSrm
+ 138547160U, // MOVLHPSrr
+ 943722465U, // MOVLPDmr
+ 139333601U, // MOVLPDrm
+ 943722473U, // MOVLPSmr
+ 139333609U, // MOVLPSrm
+ 541068648U, // MOVLQ128mr
+ 139857905U, // MOVMSKPDrr
+ 139857915U, // MOVMSKPSrr
+ 140775429U, // MOVNTDQArm
+ 2818576399U, // MOVNTDQ_64mr
+ 2818576399U, // MOVNTDQmr
+ 2818576399U, // MOVNTDQmr_Int
+ 541069336U, // MOVNTI_64mr
+ 406851608U, // MOVNTImr
+ 406851608U, // MOVNTImr_Int
+ 2818576416U, // MOVNTPDmr
+ 1480593440U, // MOVNTPDmr_Int
+ 2818576425U, // MOVNTPSmr
+ 1480593449U, // MOVNTPSmr_Int
0U, // MOVPC32r
- 406850861U, // MOVPDI2DImr
- 139857197U, // MOVPDI2DIrr
- 541068621U, // MOVPQI2QImr
- 139857229U, // MOVPQIto64rr
- 140119373U, // MOVQI2PQIrm
- 139857229U, // MOVQxrxr
- 4119U, // MOVSB
- 4120U, // MOVSD
- 943722526U, // MOVSDmr
- 140513310U, // MOVSDrm
- 138547230U, // MOVSDrr
- 541068621U, // MOVSDto64mr
- 139857229U, // MOVSDto64rr
- 140382245U, // MOVSHDUPrm
- 139857957U, // MOVSHDUPrr
- 140382255U, // MOVSLDUPrm
- 139857967U, // MOVSLDUPrr
- 406850861U, // MOVSS2DImr
- 139857197U, // MOVSS2DIrr
- 809504825U, // MOVSSmr
- 140644409U, // MOVSSrm
- 138547257U, // MOVSSrr
- 4119U, // MOVSW
+ 406850888U, // MOVPDI2DImr
+ 139857224U, // MOVPDI2DIrr
+ 541068648U, // MOVPQI2QImr
+ 139857256U, // MOVPQIto64rr
+ 140119400U, // MOVQI2PQIrm
+ 139857256U, // MOVQxrxr
+ 4146U, // MOVSB
+ 4147U, // MOVSD
+ 943722553U, // MOVSDmr
+ 140513337U, // MOVSDrm
+ 138547257U, // MOVSDrr
+ 541068648U, // MOVSDto64mr
+ 139857256U, // MOVSDto64rr
+ 140382272U, // MOVSHDUPrm
+ 139857984U, // MOVSHDUPrr
+ 140382282U, // MOVSLDUPrm
+ 139857994U, // MOVSLDUPrr
+ 406850888U, // MOVSS2DImr
+ 139857224U, // MOVSS2DIrr
+ 809504852U, // MOVSSmr
+ 140644436U, // MOVSSrm
+ 138547284U, // MOVSSrr
+ 4146U, // MOVSW
0U, // MOVSX16rm8
- 140251200U, // MOVSX16rm8W
+ 140251227U, // MOVSX16rm8W
0U, // MOVSX16rr8
- 139857984U, // MOVSX16rr8W
- 139726912U, // MOVSX32rm16
- 140251200U, // MOVSX32rm8
- 139857984U, // MOVSX32rr16
- 139857984U, // MOVSX32rr8
- 139726912U, // MOVSX64rm16
- 139989063U, // MOVSX64rm32
- 140251200U, // MOVSX64rm8
- 139857984U, // MOVSX64rr16
- 139857991U, // MOVSX64rr32
- 139857984U, // MOVSX64rr8
- 2818576463U, // MOVUPDmr
- 2818576463U, // MOVUPDmr_Int
- 140382287U, // MOVUPDrm
- 140382287U, // MOVUPDrm_Int
- 139857999U, // MOVUPDrr
- 2818576471U, // MOVUPSmr
- 2818576471U, // MOVUPSmr_Int
- 140382295U, // MOVUPSrm
- 140382295U, // MOVUPSrm_Int
- 139858007U, // MOVUPSrr
- 139988269U, // MOVZDI2PDIrm
- 139857197U, // MOVZDI2PDIrr
- 140774733U, // MOVZPQILo2PQIrm
- 139857229U, // MOVZPQILo2PQIrr
- 140119373U, // MOVZQI2PQIrm
- 139857229U, // MOVZQI2PQIrr
+ 139858011U, // MOVSX16rr8W
+ 139726939U, // MOVSX32rm16
+ 140251227U, // MOVSX32rm8
+ 139858011U, // MOVSX32rr16
+ 139858011U, // MOVSX32rr8
+ 139726939U, // MOVSX64rm16
+ 139989090U, // MOVSX64rm32
+ 140251227U, // MOVSX64rm8
+ 139858011U, // MOVSX64rr16
+ 139858018U, // MOVSX64rr32
+ 139858011U, // MOVSX64rr8
+ 2818576490U, // MOVUPDmr
+ 2818576490U, // MOVUPDmr_Int
+ 140382314U, // MOVUPDrm
+ 140382314U, // MOVUPDrm_Int
+ 139858026U, // MOVUPDrr
+ 2818576498U, // MOVUPSmr
+ 2818576498U, // MOVUPSmr_Int
+ 140382322U, // MOVUPSrm
+ 140382322U, // MOVUPSrm_Int
+ 139858034U, // MOVUPSrr
+ 139988296U, // MOVZDI2PDIrm
+ 139857224U, // MOVZDI2PDIrr
+ 140774760U, // MOVZPQILo2PQIrm
+ 139857256U, // MOVZPQILo2PQIrr
+ 140119400U, // MOVZQI2PQIrm
+ 139857256U, // MOVZQI2PQIrr
0U, // MOVZX16rm8
- 140251231U, // MOVZX16rm8W
+ 140251258U, // MOVZX16rm8W
0U, // MOVZX16rr8
- 139858015U, // MOVZX16rr8W
- 140300383U, // MOVZX32_NOREXrm8
- 139907167U, // MOVZX32_NOREXrr8
- 139726943U, // MOVZX32rm16
- 140251231U, // MOVZX32rm8
- 139858015U, // MOVZX32rr16
- 139858015U, // MOVZX32rr8
+ 139858042U, // MOVZX16rr8W
+ 140300410U, // MOVZX32_NOREXrm8
+ 139907194U, // MOVZX32_NOREXrr8
+ 139726970U, // MOVZX32rm16
+ 140251258U, // MOVZX32rm8
+ 139858042U, // MOVZX32rr16
+ 139858042U, // MOVZX32rr8
0U, // MOVZX64rm16
- 139726943U, // MOVZX64rm16_Q
+ 139726970U, // MOVZX64rm16_Q
0U, // MOVZX64rm32
0U, // MOVZX64rm8
- 140251231U, // MOVZX64rm8_Q
+ 140251258U, // MOVZX64rm8_Q
0U, // MOVZX64rr16
- 139858015U, // MOVZX64rr16_Q
+ 139858042U, // MOVZX64rr16_Q
0U, // MOVZX64rr32
0U, // MOVZX64rr8
- 139858015U, // MOVZX64rr8_Q
+ 139858042U, // MOVZX64rr8_Q
0U, // MOV_Fp3232
0U, // MOV_Fp3264
0U, // MOV_Fp3280
@@ -1457,34 +1458,34 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // MOV_Fp8032
0U, // MOV_Fp8064
0U, // MOV_Fp8080
- 139612262U, // MPSADBWrmi
- 138563686U, // MPSADBWrri
- 268439663U, // MUL16m
- 134221935U, // MUL16r
- 402657391U, // MUL32m
- 134221935U, // MUL32r
- 536875119U, // MUL64m
- 134221935U, // MUL64r
- 671092847U, // MUL8m
- 134221935U, // MUL8r
- 139202676U, // MULPDrm
- 138547316U, // MULPDrr
- 139202683U, // MULPSrm
- 138547323U, // MULPSrr
- 139333762U, // MULSDrm
- 139333762U, // MULSDrm_Int
- 138547330U, // MULSDrr
- 138547330U, // MULSDrr_Int
- 139464841U, // MULSSrm
- 139464841U, // MULSSrm_Int
- 138547337U, // MULSSrr
- 138547337U, // MULSSrr_Int
- 805310608U, // MUL_F32m
- 939528336U, // MUL_F64m
- 268439702U, // MUL_FI16m
- 402657430U, // MUL_FI32m
- 134221981U, // MUL_FPrST0
- 134221968U, // MUL_FST0r
+ 139612289U, // MPSADBWrmi
+ 138563713U, // MPSADBWrri
+ 268439690U, // MUL16m
+ 134221962U, // MUL16r
+ 402657418U, // MUL32m
+ 134221962U, // MUL32r
+ 536875146U, // MUL64m
+ 134221962U, // MUL64r
+ 671092874U, // MUL8m
+ 134221962U, // MUL8r
+ 139202703U, // MULPDrm
+ 138547343U, // MULPDrr
+ 139202710U, // MULPSrm
+ 138547350U, // MULPSrr
+ 139333789U, // MULSDrm
+ 139333789U, // MULSDrm_Int
+ 138547357U, // MULSDrr
+ 138547357U, // MULSDrr_Int
+ 139464868U, // MULSSrm
+ 139464868U, // MULSSrm_Int
+ 138547364U, // MULSSrr
+ 138547364U, // MULSSrr_Int
+ 805310635U, // MUL_F32m
+ 939528363U, // MUL_F64m
+ 268439729U, // MUL_FI16m
+ 402657457U, // MUL_FI32m
+ 134222008U, // MUL_FPrST0
+ 134221995U, // MUL_FST0r
0U, // MUL_Fp32
0U, // MUL_Fp32m
0U, // MUL_Fp64
@@ -1499,792 +1500,792 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // MUL_FpI32m32
0U, // MUL_FpI32m64
0U, // MUL_FpI32m80
- 142610576U, // MUL_FrST0
- 4260U, // MWAIT
- 268439722U, // NEG16m
- 134221994U, // NEG16r
- 402657450U, // NEG32m
- 134221994U, // NEG32r
- 536875178U, // NEG64m
- 134221994U, // NEG64r
- 671092906U, // NEG8m
- 134221994U, // NEG8r
- 4271U, // NOOP
- 402657459U, // NOOPL
- 268439731U, // NOOPW
- 268439736U, // NOT16m
- 134222008U, // NOT16r
- 402657464U, // NOT32m
- 134222008U, // NOT32r
- 536875192U, // NOT64m
- 134222008U, // NOT64r
- 671092920U, // NOT8m
- 134222008U, // NOT8r
- 134222013U, // OR16i16
- 272634054U, // OR16mi
- 272634054U, // OR16mi8
- 272634054U, // OR16mr
- 138547398U, // OR16ri
- 138547398U, // OR16ri8
- 138678470U, // OR16rm
- 138547398U, // OR16rr
- 138547398U, // OR16rr_REV
- 134222026U, // OR32i32
- 406851782U, // OR32mi
- 406851782U, // OR32mi8
- 406851782U, // OR32mr
- 138547398U, // OR32ri
- 138547398U, // OR32ri8
- 138809542U, // OR32rm
- 138547398U, // OR32rr
- 138547398U, // OR32rr_REV
- 134222036U, // OR64i32
- 541069510U, // OR64mi32
- 541069510U, // OR64mi8
- 541069510U, // OR64mr
- 138547398U, // OR64ri32
- 138547398U, // OR64ri8
- 138940614U, // OR64rm
- 138547398U, // OR64rr
- 138547398U, // OR64rr_REV
- 134222046U, // OR8i8
- 675287238U, // OR8mi
- 675287238U, // OR8mr
- 138547398U, // OR8ri
- 139071686U, // OR8rm
- 138547398U, // OR8rr
- 138547398U, // OR8rr_REV
+ 142610603U, // MUL_FrST0
+ 4287U, // MWAIT
+ 268439749U, // NEG16m
+ 134222021U, // NEG16r
+ 402657477U, // NEG32m
+ 134222021U, // NEG32r
+ 536875205U, // NEG64m
+ 134222021U, // NEG64r
+ 671092933U, // NEG8m
+ 134222021U, // NEG8r
+ 4298U, // NOOP
+ 402657486U, // NOOPL
+ 268439758U, // NOOPW
+ 268439763U, // NOT16m
+ 134222035U, // NOT16r
+ 402657491U, // NOT32m
+ 134222035U, // NOT32r
+ 536875219U, // NOT64m
+ 134222035U, // NOT64r
+ 671092947U, // NOT8m
+ 134222035U, // NOT8r
+ 134222040U, // OR16i16
+ 272634081U, // OR16mi
+ 272634081U, // OR16mi8
+ 272634081U, // OR16mr
+ 138547425U, // OR16ri
+ 138547425U, // OR16ri8
+ 138678497U, // OR16rm
+ 138547425U, // OR16rr
+ 138547425U, // OR16rr_REV
+ 134222053U, // OR32i32
+ 406851809U, // OR32mi
+ 406851809U, // OR32mi8
+ 406851809U, // OR32mr
+ 138547425U, // OR32ri
+ 138547425U, // OR32ri8
+ 138809569U, // OR32rm
+ 138547425U, // OR32rr
+ 138547425U, // OR32rr_REV
+ 134222063U, // OR64i32
+ 541069537U, // OR64mi32
+ 541069537U, // OR64mi8
+ 541069537U, // OR64mr
+ 138547425U, // OR64ri32
+ 138547425U, // OR64ri8
+ 138940641U, // OR64rm
+ 138547425U, // OR64rr
+ 138547425U, // OR64rr_REV
+ 134222073U, // OR8i8
+ 675287265U, // OR8mi
+ 675287265U, // OR8mr
+ 138547425U, // OR8ri
+ 139071713U, // OR8rm
+ 138547425U, // OR8rr
+ 138547425U, // OR8rr_REV
139201042U, // ORPDrm
138545682U, // ORPDrr
139201048U, // ORPSrm
138545688U, // ORPSrr
- 201330919U, // OUT16ir
- 4332U, // OUT16rr
- 205525223U, // OUT32ir
- 4345U, // OUT32rr
- 209719527U, // OUT8ir
- 4359U, // OUT8rr
- 4372U, // OUTSB
- 4378U, // OUTSD
- 4384U, // OUTSW
- 140775718U, // PABSBrm128
- 140120358U, // PABSBrm64
- 139858214U, // PABSBrr128
- 139858214U, // PABSBrr64
- 140775725U, // PABSDrm128
- 140120365U, // PABSDrm64
- 139858221U, // PABSDrr128
- 139858221U, // PABSDrr64
- 140775732U, // PABSWrm128
- 140120372U, // PABSWrm64
- 139858228U, // PABSWrr128
- 139858228U, // PABSWrr64
- 139595091U, // PACKSSDWrm
- 138546515U, // PACKSSDWrr
- 139595101U, // PACKSSWBrm
- 138546525U, // PACKSSWBrr
- 139596091U, // PACKUSDWrm
- 138547515U, // PACKUSDWrr
- 139595111U, // PACKUSWBrm
- 138546535U, // PACKUSWBrr
- 139595121U, // PADDBrm
- 138546545U, // PADDBrr
- 139595128U, // PADDDrm
- 138546552U, // PADDDrr
- 139595135U, // PADDQrm
- 138546559U, // PADDQrr
- 139595142U, // PADDSBrm
- 138546566U, // PADDSBrr
- 139595150U, // PADDSWrm
- 138546574U, // PADDSWrr
- 139595158U, // PADDUSBrm
- 138546582U, // PADDUSBrr
- 139595167U, // PADDUSWrm
- 138546591U, // PADDUSWrr
- 139595176U, // PADDWrm
- 138546600U, // PADDWrr
- 139612485U, // PALIGNR128rm
- 138563909U, // PALIGNR128rr
- 138957125U, // PALIGNR64rm
- 138563909U, // PALIGNR64rr
- 139595183U, // PANDNrm
- 138546607U, // PANDNrr
- 139595190U, // PANDrm
- 138546614U, // PANDrr
- 139595196U, // PAVGBrm
- 138546620U, // PAVGBrr
- 139595203U, // PAVGWrm
- 138546627U, // PAVGWrr
- 139628878U, // PBLENDVBrm0
- 138580302U, // PBLENDVBrr0
- 139612504U, // PBLENDWrmi
- 138563928U, // PBLENDWrri
- 139595210U, // PCMPEQBrm
- 138546634U, // PCMPEQBrr
- 139595219U, // PCMPEQDrm
- 138546643U, // PCMPEQDrr
- 139596129U, // PCMPEQQrm
- 138547553U, // PCMPEQQrr
- 139595228U, // PCMPEQWrm
- 138546652U, // PCMPEQWrr
- 140792170U, // PCMPESTRIArm
- 139874666U, // PCMPESTRIArr
- 140792170U, // PCMPESTRICrm
- 139874666U, // PCMPESTRICrr
- 140792170U, // PCMPESTRIOrm
- 139874666U, // PCMPESTRIOrr
- 140792170U, // PCMPESTRISrm
- 139874666U, // PCMPESTRISrr
- 140792170U, // PCMPESTRIZrm
- 139874666U, // PCMPESTRIZrr
- 140792170U, // PCMPESTRIrm
- 139874666U, // PCMPESTRIrr
- 4469U, // PCMPESTRM128MEM
- 4493U, // PCMPESTRM128REG
- 140792229U, // PCMPESTRM128rm
- 139874725U, // PCMPESTRM128rr
- 139595237U, // PCMPGTBrm
- 138546661U, // PCMPGTBrr
- 139595246U, // PCMPGTDrm
- 138546670U, // PCMPGTDrr
- 139596208U, // PCMPGTQrm
- 138547632U, // PCMPGTQrr
- 139595255U, // PCMPGTWrm
- 138546679U, // PCMPGTWrr
- 140792249U, // PCMPISTRIArm
- 139874745U, // PCMPISTRIArr
- 140792249U, // PCMPISTRICrm
- 139874745U, // PCMPISTRICrr
- 140792249U, // PCMPISTRIOrm
- 139874745U, // PCMPISTRIOrr
- 140792249U, // PCMPISTRISrm
- 139874745U, // PCMPISTRISrr
- 140792249U, // PCMPISTRIZrm
- 139874745U, // PCMPISTRIZrr
- 140792249U, // PCMPISTRIrm
- 139874745U, // PCMPISTRIrr
- 4548U, // PCMPISTRM128MEM
- 4572U, // PCMPISTRM128REG
- 140792308U, // PCMPISTRM128rm
- 139874804U, // PCMPISTRM128rr
- 675303935U, // PEXTRBmr
- 139874815U, // PEXTRBrr
- 406868487U, // PEXTRDmr
- 139874823U, // PEXTRDrr
- 541086223U, // PEXTRQmr
- 139874831U, // PEXTRQrr
- 272649728U, // PEXTRWmr
- 139873792U, // PEXTRWri
- 139596311U, // PHADDDrm128
- 138940951U, // PHADDDrm64
- 138547735U, // PHADDDrr128
- 138547735U, // PHADDDrr64
- 139596319U, // PHADDSWrm128
- 138940959U, // PHADDSWrm64
- 138547743U, // PHADDSWrr128
- 138547743U, // PHADDSWrr64
- 139596328U, // PHADDWrm128
- 138940968U, // PHADDWrm64
- 138547752U, // PHADDWrr128
- 138547752U, // PHADDWrr64
- 140775984U, // PHMINPOSUWrm128
- 139858480U, // PHMINPOSUWrr128
- 139596348U, // PHSUBDrm128
- 138940988U, // PHSUBDrm64
- 138547772U, // PHSUBDrr128
- 138547772U, // PHSUBDrr64
- 139596356U, // PHSUBSWrm128
- 138940996U, // PHSUBSWrm64
- 138547780U, // PHSUBSWrr128
- 138547780U, // PHSUBSWrr64
- 139596365U, // PHSUBWrm128
- 138941005U, // PHSUBWrm64
- 138547789U, // PHSUBWrr128
- 138547789U, // PHSUBWrr64
- 139088469U, // PINSRBrm
- 138564181U, // PINSRBrr
- 138826333U, // PINSRDrm
- 138564189U, // PINSRDrr
- 138957413U, // PINSRQrm
- 138564197U, // PINSRQrr
- 138694152U, // PINSRWrmi
- 138563080U, // PINSRWrri
- 139596397U, // PMADDUBSWrm128
- 138941037U, // PMADDUBSWrm64
- 138547821U, // PMADDUBSWrr128
- 138547821U, // PMADDUBSWrr64
- 139595280U, // PMADDWDrm
- 138546704U, // PMADDWDrr
- 139596408U, // PMAXSBrm
- 138547832U, // PMAXSBrr
- 139596416U, // PMAXSDrm
- 138547840U, // PMAXSDrr
- 139595289U, // PMAXSWrm
- 138546713U, // PMAXSWrr
- 139595297U, // PMAXUBrm
- 138546721U, // PMAXUBrr
- 139596424U, // PMAXUDrm
- 138547848U, // PMAXUDrr
- 139596432U, // PMAXUWrm
- 138547856U, // PMAXUWrr
- 139596440U, // PMINSBrm
- 138547864U, // PMINSBrr
- 139596448U, // PMINSDrm
- 138547872U, // PMINSDrr
- 139595305U, // PMINSWrm
- 138546729U, // PMINSWrr
- 139595313U, // PMINUBrm
- 138546737U, // PMINUBrr
- 139596456U, // PMINUDrm
- 138547880U, // PMINUDrr
- 139596464U, // PMINUWrm
- 138547888U, // PMINUWrr
- 139857465U, // PMOVMSKBrr
- 139989688U, // PMOVSXBDrm
- 139858616U, // PMOVSXBDrr
- 139727554U, // PMOVSXBQrm
- 139858626U, // PMOVSXBQrr
- 140120780U, // PMOVSXBWrm
- 139858636U, // PMOVSXBWrr
- 140120790U, // PMOVSXDQrm
- 139858646U, // PMOVSXDQrr
- 140120800U, // PMOVSXWDrm
- 139858656U, // PMOVSXWDrr
- 139989738U, // PMOVSXWQrm
- 139858666U, // PMOVSXWQrr
- 139989748U, // PMOVZXBDrm
- 139858676U, // PMOVZXBDrr
- 139727614U, // PMOVZXBQrm
- 139858686U, // PMOVZXBQrr
- 140120840U, // PMOVZXBWrm
- 139858696U, // PMOVZXBWrr
- 140120850U, // PMOVZXDQrm
- 139858706U, // PMOVZXDQrr
- 140120860U, // PMOVZXWDrm
- 139858716U, // PMOVZXWDrr
- 139989798U, // PMOVZXWQrm
- 139858726U, // PMOVZXWQrr
- 139596592U, // PMULDQrm
- 138548016U, // PMULDQrr
- 139596600U, // PMULHRSWrm128
- 138941240U, // PMULHRSWrm64
- 138548024U, // PMULHRSWrr128
- 138548024U, // PMULHRSWrr64
- 139595331U, // PMULHUWrm
- 138546755U, // PMULHUWrr
- 139595340U, // PMULHWrm
- 138546764U, // PMULHWrr
- 139596610U, // PMULLDrm
- 139596610U, // PMULLDrm_int
- 138548034U, // PMULLDrr
- 138548034U, // PMULLDrr_int
- 139595348U, // PMULLWrm
- 138546772U, // PMULLWrr
- 139595356U, // PMULUDQrm
- 138546780U, // PMULUDQrr
- 134222666U, // POP16r
- 268440394U, // POP16rmm
- 134222666U, // POP16rmr
- 134222666U, // POP32r
- 402658122U, // POP32rmm
- 134222666U, // POP32rmr
- 134222666U, // POP64r
- 536875850U, // POP64rmm
- 134222666U, // POP64rmr
- 139727695U, // POPCNT16rm
- 139858767U, // POPCNT16rr
- 139989839U, // POPCNT32rm
- 139858767U, // POPCNT32rr
- 140120911U, // POPCNT64rm
- 139858767U, // POPCNT64rr
- 4951U, // POPF
- 4951U, // POPFD
- 4951U, // POPFQ
- 4956U, // POPFS16
- 4956U, // POPFS32
- 4956U, // POPFS64
- 4964U, // POPGS16
- 4964U, // POPGS32
- 4964U, // POPGS64
- 139595365U, // PORrm
- 138546789U, // PORrr
- 671093612U, // PREFETCHNTA
- 671093625U, // PREFETCHT0
- 671093637U, // PREFETCHT1
- 671093649U, // PREFETCHT2
- 139595370U, // PSADBWrm
- 138546794U, // PSADBWrr
- 139596701U, // PSHUFBrm128
- 138941341U, // PSHUFBrm64
- 138548125U, // PSHUFBrr128
- 138548125U, // PSHUFBrr64
- 140792741U, // PSHUFDmi
- 139875237U, // PSHUFDri
- 140792749U, // PSHUFHWmi
- 139875245U, // PSHUFHWri
- 140792758U, // PSHUFLWmi
- 139875254U, // PSHUFLWri
- 139596735U, // PSIGNBrm128
- 138941375U, // PSIGNBrm64
- 138548159U, // PSIGNBrr128
- 138548159U, // PSIGNBrr64
- 139596743U, // PSIGNDrm128
- 138941383U, // PSIGNDrm64
- 138548167U, // PSIGNDrr128
- 138548167U, // PSIGNDrr64
- 139596751U, // PSIGNWrm128
- 138941391U, // PSIGNWrm64
- 138548175U, // PSIGNWrr128
- 138548175U, // PSIGNWrr64
- 138548183U, // PSLLDQri
- 138546810U, // PSLLDri
- 139595386U, // PSLLDrm
- 138546810U, // PSLLDrr
- 138546817U, // PSLLQri
- 139595393U, // PSLLQrm
- 138546817U, // PSLLQrr
- 138546824U, // PSLLWri
- 139595400U, // PSLLWrm
- 138546824U, // PSLLWrr
- 138546831U, // PSRADri
- 139595407U, // PSRADrm
- 138546831U, // PSRADrr
- 138546838U, // PSRAWri
- 139595414U, // PSRAWrm
- 138546838U, // PSRAWrr
- 138548191U, // PSRLDQri
- 138546845U, // PSRLDri
- 139595421U, // PSRLDrm
- 138546845U, // PSRLDrr
- 138546852U, // PSRLQri
- 139595428U, // PSRLQrm
- 138546852U, // PSRLQrr
- 138546859U, // PSRLWri
- 139595435U, // PSRLWrm
- 138546859U, // PSRLWrr
- 139595442U, // PSUBBrm
- 138546866U, // PSUBBrr
- 139595449U, // PSUBDrm
- 138546873U, // PSUBDrr
- 139595456U, // PSUBQrm
- 138546880U, // PSUBQrr
- 139595463U, // PSUBSBrm
- 138546887U, // PSUBSBrr
- 139595471U, // PSUBSWrm
- 138546895U, // PSUBSWrr
- 139595479U, // PSUBUSBrm
- 138546903U, // PSUBUSBrr
- 139595488U, // PSUBUSWrm
- 138546912U, // PSUBUSWrr
- 139595497U, // PSUBWrm
- 138546921U, // PSUBWrr
- 140776423U, // PTESTrm
- 139858919U, // PTESTrr
- 139595504U, // PUNPCKHBWrm
- 138546928U, // PUNPCKHBWrr
- 139595515U, // PUNPCKHDQrm
- 138546939U, // PUNPCKHDQrr
- 139596783U, // PUNPCKHQDQrm
- 138548207U, // PUNPCKHQDQrr
- 139595526U, // PUNPCKHWDrm
- 138546950U, // PUNPCKHWDrr
- 139595537U, // PUNPCKLBWrm
- 138546961U, // PUNPCKLBWrr
- 139595548U, // PUNPCKLDQrm
- 138546972U, // PUNPCKLDQrr
- 139596795U, // PUNPCKLQDQrm
- 138548219U, // PUNPCKLQDQrr
- 139595559U, // PUNPCKLWDrm
- 138546983U, // PUNPCKLWDrr
- 134222855U, // PUSH16r
- 268440583U, // PUSH16rmm
- 134222855U, // PUSH16rmr
- 134222855U, // PUSH32i16
- 134222855U, // PUSH32i32
- 134222855U, // PUSH32i8
- 134222855U, // PUSH32r
- 402658311U, // PUSH32rmm
- 134222855U, // PUSH32rmr
- 134222855U, // PUSH64i16
- 134222855U, // PUSH64i32
- 134222855U, // PUSH64i8
- 134222855U, // PUSH64r
- 536876039U, // PUSH64rmm
- 134222855U, // PUSH64rmr
- 5133U, // PUSHF
- 5133U, // PUSHFD
- 5133U, // PUSHFQ64
- 5139U, // PUSHFS16
- 5139U, // PUSHFS32
- 5139U, // PUSHFS64
- 5148U, // PUSHGS16
- 5148U, // PUSHGS32
- 5148U, // PUSHGS64
- 139595570U, // PXORrm
- 138546994U, // PXORrr
- 348132389U, // RCL16m1
- 352326693U, // RCL16mCL
- 272634917U, // RCL16mi
- 213914661U, // RCL16r1
- 218108965U, // RCL16rCL
- 138548261U, // RCL16ri
- 482350117U, // RCL32m1
- 486544421U, // RCL32mCL
- 406852645U, // RCL32mi
- 213914661U, // RCL32r1
- 218108965U, // RCL32rCL
- 138548261U, // RCL32ri
- 616567845U, // RCL64m1
- 620762149U, // RCL64mCL
- 541070373U, // RCL64mi
- 213914661U, // RCL64r1
- 218108965U, // RCL64rCL
- 138548261U, // RCL64ri
- 750785573U, // RCL8m1
- 754979877U, // RCL8mCL
- 675288101U, // RCL8mi
- 213914661U, // RCL8r1
- 218108965U, // RCL8rCL
- 138548261U, // RCL8ri
- 140383274U, // RCPPSm
- 140383274U, // RCPPSm_Int
- 139858986U, // RCPPSr
- 139858986U, // RCPPSr_Int
- 140645425U, // RCPSSm
- 140645425U, // RCPSSm_Int
- 139858993U, // RCPSSr
- 139858993U, // RCPSSr_Int
- 348132408U, // RCR16m1
- 352326712U, // RCR16mCL
- 272634936U, // RCR16mi
- 213914680U, // RCR16r1
- 218108984U, // RCR16rCL
- 138548280U, // RCR16ri
- 482350136U, // RCR32m1
- 486544440U, // RCR32mCL
- 406852664U, // RCR32mi
- 213914680U, // RCR32r1
- 218108984U, // RCR32rCL
- 138548280U, // RCR32ri
- 616567864U, // RCR64m1
- 620762168U, // RCR64mCL
- 541070392U, // RCR64mi
- 213914680U, // RCR64r1
- 218108984U, // RCR64rCL
- 138548280U, // RCR64ri
- 750785592U, // RCR8m1
- 754979896U, // RCR8mCL
- 675288120U, // RCR8mi
- 213914680U, // RCR8r1
- 218108984U, // RCR8rCL
- 138548280U, // RCR8ri
- 5181U, // RDMSR
- 5187U, // RDPMC
- 5193U, // RDTSC
- 5199U, // RDTSCP
- 5206U, // REPNE_PREFIX
- 5212U, // REP_MOVSB
- 5222U, // REP_MOVSD
- 5232U, // REP_MOVSQ
- 5242U, // REP_MOVSW
- 5252U, // REP_PREFIX
- 5256U, // REP_STOSB
- 5266U, // REP_STOSD
- 5276U, // REP_STOSQ
- 5286U, // REP_STOSW
- 5296U, // RET
- 134223028U, // RETI
- 268440761U, // ROL16m1
- 352326841U, // ROL16mCL
- 272635065U, // ROL16mi
- 134223033U, // ROL16r1
- 218109113U, // ROL16rCL
- 138548409U, // ROL16ri
- 402658489U, // ROL32m1
- 486544569U, // ROL32mCL
- 406852793U, // ROL32mi
- 134223033U, // ROL32r1
- 218109113U, // ROL32rCL
- 138548409U, // ROL32ri
- 536876217U, // ROL64m1
- 624956601U, // ROL64mCL
- 541070521U, // ROL64mi
- 134223033U, // ROL64r1
- 222303417U, // ROL64rCL
- 138548409U, // ROL64ri
- 671093945U, // ROL8m1
- 754980025U, // ROL8mCL
- 675288249U, // ROL8mi
- 134223033U, // ROL8r1
- 218109113U, // ROL8rCL
- 138548409U, // ROL8ri
- 268440766U, // ROR16m1
- 352326846U, // ROR16mCL
- 272635070U, // ROR16mi
- 134223038U, // ROR16r1
- 218109118U, // ROR16rCL
- 138548414U, // ROR16ri
- 402658494U, // ROR32m1
- 486544574U, // ROR32mCL
- 406852798U, // ROR32mi
- 134223038U, // ROR32r1
- 218109118U, // ROR32rCL
- 138548414U, // ROR32ri
- 536876222U, // ROR64m1
- 624956606U, // ROR64mCL
- 541070526U, // ROR64mi
- 134223038U, // ROR64r1
- 222303422U, // ROR64rCL
- 138548414U, // ROR64ri
- 671093950U, // ROR8m1
- 754980030U, // ROR8mCL
- 675288254U, // ROR8mi
- 134223038U, // ROR8r1
- 218109118U, // ROR8rCL
- 138548414U, // ROR8ri
- 140399811U, // ROUNDPDm_Int
- 139875523U, // ROUNDPDr_Int
- 140399820U, // ROUNDPSm_Int
- 139875532U, // ROUNDPSr_Int
- 139351253U, // ROUNDSDm_Int
- 138564821U, // ROUNDSDr_Int
- 139482334U, // ROUNDSSm_Int
- 138564830U, // ROUNDSSr_Int
- 5351U, // RSM
- 140383467U, // RSQRTPSm
- 140383467U, // RSQRTPSm_Int
- 139859179U, // RSQRTPSr
- 139859179U, // RSQRTPSr_Int
- 140645620U, // RSQRTSSm
- 140645620U, // RSQRTSSm_Int
- 139859188U, // RSQRTSSr
- 139859188U, // RSQRTSSr_Int
- 5373U, // SAHF
- 268440834U, // SAR16m1
- 352326914U, // SAR16mCL
- 272635138U, // SAR16mi
- 134223106U, // SAR16r1
- 218109186U, // SAR16rCL
- 138548482U, // SAR16ri
- 402658562U, // SAR32m1
- 486544642U, // SAR32mCL
- 406852866U, // SAR32mi
- 134223106U, // SAR32r1
- 218109186U, // SAR32rCL
- 138548482U, // SAR32ri
- 536876290U, // SAR64m1
- 624956674U, // SAR64mCL
- 541070594U, // SAR64mi
- 134223106U, // SAR64r1
- 222303490U, // SAR64rCL
- 138548482U, // SAR64ri
- 671094018U, // SAR8m1
- 754980098U, // SAR8mCL
- 675288322U, // SAR8mi
- 134223106U, // SAR8r1
- 218109186U, // SAR8rCL
- 138548482U, // SAR8ri
- 134223111U, // SBB16i16
- 272635153U, // SBB16mi
- 272635153U, // SBB16mi8
- 272635153U, // SBB16mr
- 138548497U, // SBB16ri
- 138548497U, // SBB16ri8
- 138679569U, // SBB16rm
- 138548497U, // SBB16rr
- 138548497U, // SBB16rr_REV
- 134223126U, // SBB32i32
- 406852881U, // SBB32mi
- 406852881U, // SBB32mi8
- 406852881U, // SBB32mr
- 138548497U, // SBB32ri
- 138548497U, // SBB32ri8
- 138810641U, // SBB32rm
- 138548497U, // SBB32rr
- 138548497U, // SBB32rr_REV
- 134223137U, // SBB64i32
- 541070609U, // SBB64mi32
- 541070609U, // SBB64mi8
- 541070609U, // SBB64mr
- 138548497U, // SBB64ri32
- 138548497U, // SBB64ri8
- 138941713U, // SBB64rm
- 138548497U, // SBB64rr
- 138548497U, // SBB64rr_REV
- 134223148U, // SBB8i8
- 675288337U, // SBB8mi
- 675288337U, // SBB8mr
- 138548497U, // SBB8ri
- 139072785U, // SBB8rm
- 138548497U, // SBB8rr
- 138548497U, // SBB8rr_REV
- 5430U, // SCAS16
- 5430U, // SCAS32
- 5430U, // SCAS64
- 5430U, // SCAS8
- 671094075U, // SETAEm
- 134223163U, // SETAEr
- 671094082U, // SETAm
- 134223170U, // SETAr
- 671094088U, // SETBEm
- 134223176U, // SETBEr
+ 201330946U, // OUT16ir
+ 4359U, // OUT16rr
+ 205525250U, // OUT32ir
+ 4372U, // OUT32rr
+ 209719554U, // OUT8ir
+ 4386U, // OUT8rr
+ 4399U, // OUTSB
+ 4405U, // OUTSD
+ 4411U, // OUTSW
+ 140775745U, // PABSBrm128
+ 140120385U, // PABSBrm64
+ 139858241U, // PABSBrr128
+ 139858241U, // PABSBrr64
+ 140775752U, // PABSDrm128
+ 140120392U, // PABSDrm64
+ 139858248U, // PABSDrr128
+ 139858248U, // PABSDrr64
+ 140775759U, // PABSWrm128
+ 140120399U, // PABSWrm64
+ 139858255U, // PABSWrr128
+ 139858255U, // PABSWrr64
+ 139595118U, // PACKSSDWrm
+ 138546542U, // PACKSSDWrr
+ 139595128U, // PACKSSWBrm
+ 138546552U, // PACKSSWBrr
+ 139596118U, // PACKUSDWrm
+ 138547542U, // PACKUSDWrr
+ 139595138U, // PACKUSWBrm
+ 138546562U, // PACKUSWBrr
+ 139595148U, // PADDBrm
+ 138546572U, // PADDBrr
+ 139595155U, // PADDDrm
+ 138546579U, // PADDDrr
+ 139595162U, // PADDQrm
+ 138546586U, // PADDQrr
+ 139595169U, // PADDSBrm
+ 138546593U, // PADDSBrr
+ 139595177U, // PADDSWrm
+ 138546601U, // PADDSWrr
+ 139595185U, // PADDUSBrm
+ 138546609U, // PADDUSBrr
+ 139595194U, // PADDUSWrm
+ 138546618U, // PADDUSWrr
+ 139595203U, // PADDWrm
+ 138546627U, // PADDWrr
+ 139612512U, // PALIGNR128rm
+ 138563936U, // PALIGNR128rr
+ 138957152U, // PALIGNR64rm
+ 138563936U, // PALIGNR64rr
+ 139595210U, // PANDNrm
+ 138546634U, // PANDNrr
+ 139595217U, // PANDrm
+ 138546641U, // PANDrr
+ 139595223U, // PAVGBrm
+ 138546647U, // PAVGBrr
+ 139595230U, // PAVGWrm
+ 138546654U, // PAVGWrr
+ 139628905U, // PBLENDVBrm0
+ 138580329U, // PBLENDVBrr0
+ 139612531U, // PBLENDWrmi
+ 138563955U, // PBLENDWrri
+ 139595237U, // PCMPEQBrm
+ 138546661U, // PCMPEQBrr
+ 139595246U, // PCMPEQDrm
+ 138546670U, // PCMPEQDrr
+ 139596156U, // PCMPEQQrm
+ 138547580U, // PCMPEQQrr
+ 139595255U, // PCMPEQWrm
+ 138546679U, // PCMPEQWrr
+ 140792197U, // PCMPESTRIArm
+ 139874693U, // PCMPESTRIArr
+ 140792197U, // PCMPESTRICrm
+ 139874693U, // PCMPESTRICrr
+ 140792197U, // PCMPESTRIOrm
+ 139874693U, // PCMPESTRIOrr
+ 140792197U, // PCMPESTRISrm
+ 139874693U, // PCMPESTRISrr
+ 140792197U, // PCMPESTRIZrm
+ 139874693U, // PCMPESTRIZrr
+ 140792197U, // PCMPESTRIrm
+ 139874693U, // PCMPESTRIrr
+ 4496U, // PCMPESTRM128MEM
+ 4520U, // PCMPESTRM128REG
+ 140792256U, // PCMPESTRM128rm
+ 139874752U, // PCMPESTRM128rr
+ 139595264U, // PCMPGTBrm
+ 138546688U, // PCMPGTBrr
+ 139595273U, // PCMPGTDrm
+ 138546697U, // PCMPGTDrr
+ 139596235U, // PCMPGTQrm
+ 138547659U, // PCMPGTQrr
+ 139595282U, // PCMPGTWrm
+ 138546706U, // PCMPGTWrr
+ 140792276U, // PCMPISTRIArm
+ 139874772U, // PCMPISTRIArr
+ 140792276U, // PCMPISTRICrm
+ 139874772U, // PCMPISTRICrr
+ 140792276U, // PCMPISTRIOrm
+ 139874772U, // PCMPISTRIOrr
+ 140792276U, // PCMPISTRISrm
+ 139874772U, // PCMPISTRISrr
+ 140792276U, // PCMPISTRIZrm
+ 139874772U, // PCMPISTRIZrr
+ 140792276U, // PCMPISTRIrm
+ 139874772U, // PCMPISTRIrr
+ 4575U, // PCMPISTRM128MEM
+ 4599U, // PCMPISTRM128REG
+ 140792335U, // PCMPISTRM128rm
+ 139874831U, // PCMPISTRM128rr
+ 675303962U, // PEXTRBmr
+ 139874842U, // PEXTRBrr
+ 406868514U, // PEXTRDmr
+ 139874850U, // PEXTRDrr
+ 541086250U, // PEXTRQmr
+ 139874858U, // PEXTRQrr
+ 272649755U, // PEXTRWmr
+ 139873819U, // PEXTRWri
+ 139596338U, // PHADDDrm128
+ 138940978U, // PHADDDrm64
+ 138547762U, // PHADDDrr128
+ 138547762U, // PHADDDrr64
+ 139596346U, // PHADDSWrm128
+ 138940986U, // PHADDSWrm64
+ 138547770U, // PHADDSWrr128
+ 138547770U, // PHADDSWrr64
+ 139596355U, // PHADDWrm128
+ 138940995U, // PHADDWrm64
+ 138547779U, // PHADDWrr128
+ 138547779U, // PHADDWrr64
+ 140776011U, // PHMINPOSUWrm128
+ 139858507U, // PHMINPOSUWrr128
+ 139596375U, // PHSUBDrm128
+ 138941015U, // PHSUBDrm64
+ 138547799U, // PHSUBDrr128
+ 138547799U, // PHSUBDrr64
+ 139596383U, // PHSUBSWrm128
+ 138941023U, // PHSUBSWrm64
+ 138547807U, // PHSUBSWrr128
+ 138547807U, // PHSUBSWrr64
+ 139596392U, // PHSUBWrm128
+ 138941032U, // PHSUBWrm64
+ 138547816U, // PHSUBWrr128
+ 138547816U, // PHSUBWrr64
+ 139088496U, // PINSRBrm
+ 138564208U, // PINSRBrr
+ 138826360U, // PINSRDrm
+ 138564216U, // PINSRDrr
+ 138957440U, // PINSRQrm
+ 138564224U, // PINSRQrr
+ 138694179U, // PINSRWrmi
+ 138563107U, // PINSRWrri
+ 139596424U, // PMADDUBSWrm128
+ 138941064U, // PMADDUBSWrm64
+ 138547848U, // PMADDUBSWrr128
+ 138547848U, // PMADDUBSWrr64
+ 139595307U, // PMADDWDrm
+ 138546731U, // PMADDWDrr
+ 139596435U, // PMAXSBrm
+ 138547859U, // PMAXSBrr
+ 139596443U, // PMAXSDrm
+ 138547867U, // PMAXSDrr
+ 139595316U, // PMAXSWrm
+ 138546740U, // PMAXSWrr
+ 139595324U, // PMAXUBrm
+ 138546748U, // PMAXUBrr
+ 139596451U, // PMAXUDrm
+ 138547875U, // PMAXUDrr
+ 139596459U, // PMAXUWrm
+ 138547883U, // PMAXUWrr
+ 139596467U, // PMINSBrm
+ 138547891U, // PMINSBrr
+ 139596475U, // PMINSDrm
+ 138547899U, // PMINSDrr
+ 139595332U, // PMINSWrm
+ 138546756U, // PMINSWrr
+ 139595340U, // PMINUBrm
+ 138546764U, // PMINUBrr
+ 139596483U, // PMINUDrm
+ 138547907U, // PMINUDrr
+ 139596491U, // PMINUWrm
+ 138547915U, // PMINUWrr
+ 139857492U, // PMOVMSKBrr
+ 139989715U, // PMOVSXBDrm
+ 139858643U, // PMOVSXBDrr
+ 139727581U, // PMOVSXBQrm
+ 139858653U, // PMOVSXBQrr
+ 140120807U, // PMOVSXBWrm
+ 139858663U, // PMOVSXBWrr
+ 140120817U, // PMOVSXDQrm
+ 139858673U, // PMOVSXDQrr
+ 140120827U, // PMOVSXWDrm
+ 139858683U, // PMOVSXWDrr
+ 139989765U, // PMOVSXWQrm
+ 139858693U, // PMOVSXWQrr
+ 139989775U, // PMOVZXBDrm
+ 139858703U, // PMOVZXBDrr
+ 139727641U, // PMOVZXBQrm
+ 139858713U, // PMOVZXBQrr
+ 140120867U, // PMOVZXBWrm
+ 139858723U, // PMOVZXBWrr
+ 140120877U, // PMOVZXDQrm
+ 139858733U, // PMOVZXDQrr
+ 140120887U, // PMOVZXWDrm
+ 139858743U, // PMOVZXWDrr
+ 139989825U, // PMOVZXWQrm
+ 139858753U, // PMOVZXWQrr
+ 139596619U, // PMULDQrm
+ 138548043U, // PMULDQrr
+ 139596627U, // PMULHRSWrm128
+ 138941267U, // PMULHRSWrm64
+ 138548051U, // PMULHRSWrr128
+ 138548051U, // PMULHRSWrr64
+ 139595358U, // PMULHUWrm
+ 138546782U, // PMULHUWrr
+ 139595367U, // PMULHWrm
+ 138546791U, // PMULHWrr
+ 139596637U, // PMULLDrm
+ 139596637U, // PMULLDrm_int
+ 138548061U, // PMULLDrr
+ 138548061U, // PMULLDrr_int
+ 139595375U, // PMULLWrm
+ 138546799U, // PMULLWrr
+ 139595383U, // PMULUDQrm
+ 138546807U, // PMULUDQrr
+ 134222693U, // POP16r
+ 268440421U, // POP16rmm
+ 134222693U, // POP16rmr
+ 134222693U, // POP32r
+ 402658149U, // POP32rmm
+ 134222693U, // POP32rmr
+ 134222693U, // POP64r
+ 536875877U, // POP64rmm
+ 134222693U, // POP64rmr
+ 139727722U, // POPCNT16rm
+ 139858794U, // POPCNT16rr
+ 139989866U, // POPCNT32rm
+ 139858794U, // POPCNT32rr
+ 140120938U, // POPCNT64rm
+ 139858794U, // POPCNT64rr
+ 4978U, // POPF
+ 4978U, // POPFD
+ 4978U, // POPFQ
+ 4983U, // POPFS16
+ 4983U, // POPFS32
+ 4983U, // POPFS64
+ 4991U, // POPGS16
+ 4991U, // POPGS32
+ 4991U, // POPGS64
+ 139595392U, // PORrm
+ 138546816U, // PORrr
+ 671093639U, // PREFETCHNTA
+ 671093652U, // PREFETCHT0
+ 671093664U, // PREFETCHT1
+ 671093676U, // PREFETCHT2
+ 139595397U, // PSADBWrm
+ 138546821U, // PSADBWrr
+ 139596728U, // PSHUFBrm128
+ 138941368U, // PSHUFBrm64
+ 138548152U, // PSHUFBrr128
+ 138548152U, // PSHUFBrr64
+ 140792768U, // PSHUFDmi
+ 139875264U, // PSHUFDri
+ 140792776U, // PSHUFHWmi
+ 139875272U, // PSHUFHWri
+ 140792785U, // PSHUFLWmi
+ 139875281U, // PSHUFLWri
+ 139596762U, // PSIGNBrm128
+ 138941402U, // PSIGNBrm64
+ 138548186U, // PSIGNBrr128
+ 138548186U, // PSIGNBrr64
+ 139596770U, // PSIGNDrm128
+ 138941410U, // PSIGNDrm64
+ 138548194U, // PSIGNDrr128
+ 138548194U, // PSIGNDrr64
+ 139596778U, // PSIGNWrm128
+ 138941418U, // PSIGNWrm64
+ 138548202U, // PSIGNWrr128
+ 138548202U, // PSIGNWrr64
+ 138548210U, // PSLLDQri
+ 138546837U, // PSLLDri
+ 139595413U, // PSLLDrm
+ 138546837U, // PSLLDrr
+ 138546844U, // PSLLQri
+ 139595420U, // PSLLQrm
+ 138546844U, // PSLLQrr
+ 138546851U, // PSLLWri
+ 139595427U, // PSLLWrm
+ 138546851U, // PSLLWrr
+ 138546858U, // PSRADri
+ 139595434U, // PSRADrm
+ 138546858U, // PSRADrr
+ 138546865U, // PSRAWri
+ 139595441U, // PSRAWrm
+ 138546865U, // PSRAWrr
+ 138548218U, // PSRLDQri
+ 138546872U, // PSRLDri
+ 139595448U, // PSRLDrm
+ 138546872U, // PSRLDrr
+ 138546879U, // PSRLQri
+ 139595455U, // PSRLQrm
+ 138546879U, // PSRLQrr
+ 138546886U, // PSRLWri
+ 139595462U, // PSRLWrm
+ 138546886U, // PSRLWrr
+ 139595469U, // PSUBBrm
+ 138546893U, // PSUBBrr
+ 139595476U, // PSUBDrm
+ 138546900U, // PSUBDrr
+ 139595483U, // PSUBQrm
+ 138546907U, // PSUBQrr
+ 139595490U, // PSUBSBrm
+ 138546914U, // PSUBSBrr
+ 139595498U, // PSUBSWrm
+ 138546922U, // PSUBSWrr
+ 139595506U, // PSUBUSBrm
+ 138546930U, // PSUBUSBrr
+ 139595515U, // PSUBUSWrm
+ 138546939U, // PSUBUSWrr
+ 139595524U, // PSUBWrm
+ 138546948U, // PSUBWrr
+ 140776450U, // PTESTrm
+ 139858946U, // PTESTrr
+ 139595531U, // PUNPCKHBWrm
+ 138546955U, // PUNPCKHBWrr
+ 139595542U, // PUNPCKHDQrm
+ 138546966U, // PUNPCKHDQrr
+ 139596810U, // PUNPCKHQDQrm
+ 138548234U, // PUNPCKHQDQrr
+ 139595553U, // PUNPCKHWDrm
+ 138546977U, // PUNPCKHWDrr
+ 139595564U, // PUNPCKLBWrm
+ 138546988U, // PUNPCKLBWrr
+ 139595575U, // PUNPCKLDQrm
+ 138546999U, // PUNPCKLDQrr
+ 139596822U, // PUNPCKLQDQrm
+ 138548246U, // PUNPCKLQDQrr
+ 139595586U, // PUNPCKLWDrm
+ 138547010U, // PUNPCKLWDrr
+ 134222882U, // PUSH16r
+ 268440610U, // PUSH16rmm
+ 134222882U, // PUSH16rmr
+ 134222882U, // PUSH32i16
+ 134222882U, // PUSH32i32
+ 134222882U, // PUSH32i8
+ 134222882U, // PUSH32r
+ 402658338U, // PUSH32rmm
+ 134222882U, // PUSH32rmr
+ 134222882U, // PUSH64i16
+ 134222882U, // PUSH64i32
+ 134222882U, // PUSH64i8
+ 134222882U, // PUSH64r
+ 536876066U, // PUSH64rmm
+ 134222882U, // PUSH64rmr
+ 5160U, // PUSHF
+ 5160U, // PUSHFD
+ 5160U, // PUSHFQ64
+ 5166U, // PUSHFS16
+ 5166U, // PUSHFS32
+ 5166U, // PUSHFS64
+ 5175U, // PUSHGS16
+ 5175U, // PUSHGS32
+ 5175U, // PUSHGS64
+ 139595597U, // PXORrm
+ 138547021U, // PXORrr
+ 348132416U, // RCL16m1
+ 352326720U, // RCL16mCL
+ 272634944U, // RCL16mi
+ 213914688U, // RCL16r1
+ 218108992U, // RCL16rCL
+ 138548288U, // RCL16ri
+ 482350144U, // RCL32m1
+ 486544448U, // RCL32mCL
+ 406852672U, // RCL32mi
+ 213914688U, // RCL32r1
+ 218108992U, // RCL32rCL
+ 138548288U, // RCL32ri
+ 616567872U, // RCL64m1
+ 620762176U, // RCL64mCL
+ 541070400U, // RCL64mi
+ 213914688U, // RCL64r1
+ 218108992U, // RCL64rCL
+ 138548288U, // RCL64ri
+ 750785600U, // RCL8m1
+ 754979904U, // RCL8mCL
+ 675288128U, // RCL8mi
+ 213914688U, // RCL8r1
+ 218108992U, // RCL8rCL
+ 138548288U, // RCL8ri
+ 140383301U, // RCPPSm
+ 140383301U, // RCPPSm_Int
+ 139859013U, // RCPPSr
+ 139859013U, // RCPPSr_Int
+ 140645452U, // RCPSSm
+ 140645452U, // RCPSSm_Int
+ 139859020U, // RCPSSr
+ 139859020U, // RCPSSr_Int
+ 348132435U, // RCR16m1
+ 352326739U, // RCR16mCL
+ 272634963U, // RCR16mi
+ 213914707U, // RCR16r1
+ 218109011U, // RCR16rCL
+ 138548307U, // RCR16ri
+ 482350163U, // RCR32m1
+ 486544467U, // RCR32mCL
+ 406852691U, // RCR32mi
+ 213914707U, // RCR32r1
+ 218109011U, // RCR32rCL
+ 138548307U, // RCR32ri
+ 616567891U, // RCR64m1
+ 620762195U, // RCR64mCL
+ 541070419U, // RCR64mi
+ 213914707U, // RCR64r1
+ 218109011U, // RCR64rCL
+ 138548307U, // RCR64ri
+ 750785619U, // RCR8m1
+ 754979923U, // RCR8mCL
+ 675288147U, // RCR8mi
+ 213914707U, // RCR8r1
+ 218109011U, // RCR8rCL
+ 138548307U, // RCR8ri
+ 5208U, // RDMSR
+ 5214U, // RDPMC
+ 5220U, // RDTSC
+ 5226U, // RDTSCP
+ 5233U, // REPNE_PREFIX
+ 5239U, // REP_MOVSB
+ 5249U, // REP_MOVSD
+ 5259U, // REP_MOVSQ
+ 5269U, // REP_MOVSW
+ 5279U, // REP_PREFIX
+ 5283U, // REP_STOSB
+ 5293U, // REP_STOSD
+ 5303U, // REP_STOSQ
+ 5313U, // REP_STOSW
+ 5323U, // RET
+ 134223055U, // RETI
+ 268440788U, // ROL16m1
+ 352326868U, // ROL16mCL
+ 272635092U, // ROL16mi
+ 134223060U, // ROL16r1
+ 218109140U, // ROL16rCL
+ 138548436U, // ROL16ri
+ 402658516U, // ROL32m1
+ 486544596U, // ROL32mCL
+ 406852820U, // ROL32mi
+ 134223060U, // ROL32r1
+ 218109140U, // ROL32rCL
+ 138548436U, // ROL32ri
+ 536876244U, // ROL64m1
+ 624956628U, // ROL64mCL
+ 541070548U, // ROL64mi
+ 134223060U, // ROL64r1
+ 222303444U, // ROL64rCL
+ 138548436U, // ROL64ri
+ 671093972U, // ROL8m1
+ 754980052U, // ROL8mCL
+ 675288276U, // ROL8mi
+ 134223060U, // ROL8r1
+ 218109140U, // ROL8rCL
+ 138548436U, // ROL8ri
+ 268440793U, // ROR16m1
+ 352326873U, // ROR16mCL
+ 272635097U, // ROR16mi
+ 134223065U, // ROR16r1
+ 218109145U, // ROR16rCL
+ 138548441U, // ROR16ri
+ 402658521U, // ROR32m1
+ 486544601U, // ROR32mCL
+ 406852825U, // ROR32mi
+ 134223065U, // ROR32r1
+ 218109145U, // ROR32rCL
+ 138548441U, // ROR32ri
+ 536876249U, // ROR64m1
+ 624956633U, // ROR64mCL
+ 541070553U, // ROR64mi
+ 134223065U, // ROR64r1
+ 222303449U, // ROR64rCL
+ 138548441U, // ROR64ri
+ 671093977U, // ROR8m1
+ 754980057U, // ROR8mCL
+ 675288281U, // ROR8mi
+ 134223065U, // ROR8r1
+ 218109145U, // ROR8rCL
+ 138548441U, // ROR8ri
+ 140399838U, // ROUNDPDm_Int
+ 139875550U, // ROUNDPDr_Int
+ 140399847U, // ROUNDPSm_Int
+ 139875559U, // ROUNDPSr_Int
+ 139351280U, // ROUNDSDm_Int
+ 138564848U, // ROUNDSDr_Int
+ 139482361U, // ROUNDSSm_Int
+ 138564857U, // ROUNDSSr_Int
+ 5378U, // RSM
+ 140383494U, // RSQRTPSm
+ 140383494U, // RSQRTPSm_Int
+ 139859206U, // RSQRTPSr
+ 139859206U, // RSQRTPSr_Int
+ 140645647U, // RSQRTSSm
+ 140645647U, // RSQRTSSm_Int
+ 139859215U, // RSQRTSSr
+ 139859215U, // RSQRTSSr_Int
+ 5400U, // SAHF
+ 268440861U, // SAR16m1
+ 352326941U, // SAR16mCL
+ 272635165U, // SAR16mi
+ 134223133U, // SAR16r1
+ 218109213U, // SAR16rCL
+ 138548509U, // SAR16ri
+ 402658589U, // SAR32m1
+ 486544669U, // SAR32mCL
+ 406852893U, // SAR32mi
+ 134223133U, // SAR32r1
+ 218109213U, // SAR32rCL
+ 138548509U, // SAR32ri
+ 536876317U, // SAR64m1
+ 624956701U, // SAR64mCL
+ 541070621U, // SAR64mi
+ 134223133U, // SAR64r1
+ 222303517U, // SAR64rCL
+ 138548509U, // SAR64ri
+ 671094045U, // SAR8m1
+ 754980125U, // SAR8mCL
+ 675288349U, // SAR8mi
+ 134223133U, // SAR8r1
+ 218109213U, // SAR8rCL
+ 138548509U, // SAR8ri
+ 134223138U, // SBB16i16
+ 272635180U, // SBB16mi
+ 272635180U, // SBB16mi8
+ 272635180U, // SBB16mr
+ 138548524U, // SBB16ri
+ 138548524U, // SBB16ri8
+ 138679596U, // SBB16rm
+ 138548524U, // SBB16rr
+ 138548524U, // SBB16rr_REV
+ 134223153U, // SBB32i32
+ 406852908U, // SBB32mi
+ 406852908U, // SBB32mi8
+ 406852908U, // SBB32mr
+ 138548524U, // SBB32ri
+ 138548524U, // SBB32ri8
+ 138810668U, // SBB32rm
+ 138548524U, // SBB32rr
+ 138548524U, // SBB32rr_REV
+ 134223164U, // SBB64i32
+ 541070636U, // SBB64mi32
+ 541070636U, // SBB64mi8
+ 541070636U, // SBB64mr
+ 138548524U, // SBB64ri32
+ 138548524U, // SBB64ri8
+ 138941740U, // SBB64rm
+ 138548524U, // SBB64rr
+ 138548524U, // SBB64rr_REV
+ 134223175U, // SBB8i8
+ 675288364U, // SBB8mi
+ 675288364U, // SBB8mr
+ 138548524U, // SBB8ri
+ 139072812U, // SBB8rm
+ 138548524U, // SBB8rr
+ 138548524U, // SBB8rr_REV
+ 5457U, // SCAS16
+ 5457U, // SCAS32
+ 5457U, // SCAS64
+ 5457U, // SCAS8
+ 671094102U, // SETAEm
+ 134223190U, // SETAEr
+ 671094109U, // SETAm
+ 134223197U, // SETAr
+ 671094115U, // SETBEm
+ 134223203U, // SETBEr
0U, // SETB_C16r
0U, // SETB_C32r
0U, // SETB_C64r
0U, // SETB_C8r
- 671094095U, // SETBm
- 134223183U, // SETBr
- 671094101U, // SETEm
- 134223189U, // SETEr
- 671094107U, // SETGEm
- 134223195U, // SETGEr
- 671094114U, // SETGm
- 134223202U, // SETGr
- 671094120U, // SETLEm
- 134223208U, // SETLEr
- 671094127U, // SETLm
- 134223215U, // SETLr
- 671094133U, // SETNEm
- 134223221U, // SETNEr
- 671094140U, // SETNOm
- 134223228U, // SETNOr
- 671094147U, // SETNPm
- 134223235U, // SETNPr
- 671094154U, // SETNSm
- 134223242U, // SETNSr
- 671094161U, // SETOm
- 134223249U, // SETOr
- 671094167U, // SETPm
- 134223255U, // SETPr
- 671094173U, // SETSm
- 134223261U, // SETSr
- 5539U, // SFENCE
- 1744836010U, // SGDTm
- 268441008U, // SHL16m1
- 352327088U, // SHL16mCL
- 272635312U, // SHL16mi
- 134223280U, // SHL16r1
- 218109360U, // SHL16rCL
- 138548656U, // SHL16ri
- 402658736U, // SHL32m1
- 486544816U, // SHL32mCL
- 406853040U, // SHL32mi
- 134223280U, // SHL32r1
- 218109360U, // SHL32rCL
- 138548656U, // SHL32ri
- 536876464U, // SHL64m1
- 624956848U, // SHL64mCL
- 541070768U, // SHL64mi
- 134223280U, // SHL64r1
- 222303664U, // SHL64rCL
- 138548656U, // SHL64ri
- 671094192U, // SHL8m1
- 754980272U, // SHL8mCL
- 675288496U, // SHL8mi
- 134223280U, // SHL8r1
- 218109360U, // SHL8rCL
- 138548656U, // SHL8ri
- 272700853U, // SHLD16mrCL
- 272651701U, // SHLD16mri8
- 138614197U, // SHLD16rrCL
- 138565045U, // SHLD16rri8
- 406918581U, // SHLD32mrCL
- 406869429U, // SHLD32mri8
- 138614197U, // SHLD32rrCL
- 138565045U, // SHLD32rri8
- 541152693U, // SHLD64mrCL
- 541087157U, // SHLD64mri8
- 138630581U, // SHLD64rrCL
- 138565045U, // SHLD64rri8
- 268441019U, // SHR16m1
- 352327099U, // SHR16mCL
- 272635323U, // SHR16mi
- 134223291U, // SHR16r1
- 218109371U, // SHR16rCL
- 138548667U, // SHR16ri
- 402658747U, // SHR32m1
- 486544827U, // SHR32mCL
- 406853051U, // SHR32mi
- 134223291U, // SHR32r1
- 218109371U, // SHR32rCL
- 138548667U, // SHR32ri
- 536876475U, // SHR64m1
- 624956859U, // SHR64mCL
- 541070779U, // SHR64mi
- 134223291U, // SHR64r1
- 222303675U, // SHR64rCL
- 138548667U, // SHR64ri
- 671094203U, // SHR8m1
- 754980283U, // SHR8mCL
- 675288507U, // SHR8mi
- 134223291U, // SHR8r1
- 218109371U, // SHR8rCL
- 138548667U, // SHR8ri
- 272700864U, // SHRD16mrCL
- 272651712U, // SHRD16mri8
- 138614208U, // SHRD16rrCL
- 138565056U, // SHRD16rri8
- 406918592U, // SHRD32mrCL
- 406869440U, // SHRD32mri8
- 138614208U, // SHRD32rrCL
- 138565056U, // SHRD32rri8
- 541152704U, // SHRD64mrCL
- 541087168U, // SHRD64mri8
- 138630592U, // SHRD64rrCL
- 138565056U, // SHRD64rri8
- 139220422U, // SHUFPDrmi
- 138565062U, // SHUFPDrri
- 139220430U, // SHUFPSrmi
- 138565070U, // SHUFPSrri
- 1744836054U, // SIDTm
- 5596U, // SIN_F
+ 671094122U, // SETBm
+ 134223210U, // SETBr
+ 671094128U, // SETEm
+ 134223216U, // SETEr
+ 671094134U, // SETGEm
+ 134223222U, // SETGEr
+ 671094141U, // SETGm
+ 134223229U, // SETGr
+ 671094147U, // SETLEm
+ 134223235U, // SETLEr
+ 671094154U, // SETLm
+ 134223242U, // SETLr
+ 671094160U, // SETNEm
+ 134223248U, // SETNEr
+ 671094167U, // SETNOm
+ 134223255U, // SETNOr
+ 671094174U, // SETNPm
+ 134223262U, // SETNPr
+ 671094181U, // SETNSm
+ 134223269U, // SETNSr
+ 671094188U, // SETOm
+ 134223276U, // SETOr
+ 671094194U, // SETPm
+ 134223282U, // SETPr
+ 671094200U, // SETSm
+ 134223288U, // SETSr
+ 5566U, // SFENCE
+ 1744836037U, // SGDTm
+ 268441035U, // SHL16m1
+ 352327115U, // SHL16mCL
+ 272635339U, // SHL16mi
+ 134223307U, // SHL16r1
+ 218109387U, // SHL16rCL
+ 138548683U, // SHL16ri
+ 402658763U, // SHL32m1
+ 486544843U, // SHL32mCL
+ 406853067U, // SHL32mi
+ 134223307U, // SHL32r1
+ 218109387U, // SHL32rCL
+ 138548683U, // SHL32ri
+ 536876491U, // SHL64m1
+ 624956875U, // SHL64mCL
+ 541070795U, // SHL64mi
+ 134223307U, // SHL64r1
+ 222303691U, // SHL64rCL
+ 138548683U, // SHL64ri
+ 671094219U, // SHL8m1
+ 754980299U, // SHL8mCL
+ 675288523U, // SHL8mi
+ 134223307U, // SHL8r1
+ 218109387U, // SHL8rCL
+ 138548683U, // SHL8ri
+ 272700880U, // SHLD16mrCL
+ 272651728U, // SHLD16mri8
+ 138614224U, // SHLD16rrCL
+ 138565072U, // SHLD16rri8
+ 406918608U, // SHLD32mrCL
+ 406869456U, // SHLD32mri8
+ 138614224U, // SHLD32rrCL
+ 138565072U, // SHLD32rri8
+ 541152720U, // SHLD64mrCL
+ 541087184U, // SHLD64mri8
+ 138630608U, // SHLD64rrCL
+ 138565072U, // SHLD64rri8
+ 268441046U, // SHR16m1
+ 352327126U, // SHR16mCL
+ 272635350U, // SHR16mi
+ 134223318U, // SHR16r1
+ 218109398U, // SHR16rCL
+ 138548694U, // SHR16ri
+ 402658774U, // SHR32m1
+ 486544854U, // SHR32mCL
+ 406853078U, // SHR32mi
+ 134223318U, // SHR32r1
+ 218109398U, // SHR32rCL
+ 138548694U, // SHR32ri
+ 536876502U, // SHR64m1
+ 624956886U, // SHR64mCL
+ 541070806U, // SHR64mi
+ 134223318U, // SHR64r1
+ 222303702U, // SHR64rCL
+ 138548694U, // SHR64ri
+ 671094230U, // SHR8m1
+ 754980310U, // SHR8mCL
+ 675288534U, // SHR8mi
+ 134223318U, // SHR8r1
+ 218109398U, // SHR8rCL
+ 138548694U, // SHR8ri
+ 272700891U, // SHRD16mrCL
+ 272651739U, // SHRD16mri8
+ 138614235U, // SHRD16rrCL
+ 138565083U, // SHRD16rri8
+ 406918619U, // SHRD32mrCL
+ 406869467U, // SHRD32mri8
+ 138614235U, // SHRD32rrCL
+ 138565083U, // SHRD32rri8
+ 541152731U, // SHRD64mrCL
+ 541087195U, // SHRD64mri8
+ 138630619U, // SHRD64rrCL
+ 138565083U, // SHRD64rri8
+ 139220449U, // SHUFPDrmi
+ 138565089U, // SHUFPDrri
+ 139220457U, // SHUFPSrmi
+ 138565097U, // SHUFPSrri
+ 1744836081U, // SIDTm
+ 5623U, // SIN_F
0U, // SIN_Fp32
0U, // SIN_Fp64
0U, // SIN_Fp80
- 268441057U, // SLDT16m
- 134223329U, // SLDT16r
- 268441057U, // SLDT64m
- 134223329U, // SLDT64r
- 268441063U, // SMSW16m
- 134223335U, // SMSW16r
- 134223335U, // SMSW32r
- 134223335U, // SMSW64r
- 140383725U, // SQRTPDm
- 140383725U, // SQRTPDm_Int
- 139859437U, // SQRTPDr
- 139859437U, // SQRTPDr_Int
- 140383733U, // SQRTPSm
- 140383733U, // SQRTPSm_Int
- 139859445U, // SQRTPSr
- 139859445U, // SQRTPSr_Int
- 140514813U, // SQRTSDm
- 140514813U, // SQRTSDm_Int
- 139859453U, // SQRTSDr
- 139859453U, // SQRTSDr_Int
- 140645893U, // SQRTSSm
- 140645893U, // SQRTSSm_Int
- 139859461U, // SQRTSSr
- 139859461U, // SQRTSSr_Int
- 5645U, // SQRT_F
+ 268441084U, // SLDT16m
+ 134223356U, // SLDT16r
+ 268441084U, // SLDT64m
+ 134223356U, // SLDT64r
+ 268441090U, // SMSW16m
+ 134223362U, // SMSW16r
+ 134223362U, // SMSW32r
+ 134223362U, // SMSW64r
+ 140383752U, // SQRTPDm
+ 140383752U, // SQRTPDm_Int
+ 139859464U, // SQRTPDr
+ 139859464U, // SQRTPDr_Int
+ 140383760U, // SQRTPSm
+ 140383760U, // SQRTPSm_Int
+ 139859472U, // SQRTPSr
+ 139859472U, // SQRTPSr_Int
+ 140514840U, // SQRTSDm
+ 140514840U, // SQRTSDm_Int
+ 139859480U, // SQRTSDr
+ 139859480U, // SQRTSDr_Int
+ 140645920U, // SQRTSSm
+ 140645920U, // SQRTSSm_Int
+ 139859488U, // SQRTSSr
+ 139859488U, // SQRTSSr_Int
+ 5672U, // SQRT_F
0U, // SQRT_Fp32
0U, // SQRT_Fp64
0U, // SQRT_Fp80
- 5651U, // SS_PREFIX
- 5654U, // STC
- 5658U, // STD
- 5662U, // STI
- 402658850U, // STMXCSR
- 4119U, // STOSB
- 5675U, // STOSD
- 4119U, // STOSW
- 5681U, // STRm
- 5681U, // STRr
- 805312054U, // ST_F32m
- 939529782U, // ST_F64m
- 805312059U, // ST_FP32m
- 939529787U, // ST_FP64m
- 2147489339U, // ST_FP80m
- 134223419U, // ST_FPrr
+ 5678U, // SS_PREFIX
+ 5681U, // STC
+ 5685U, // STD
+ 5689U, // STI
+ 402658877U, // STMXCSR
+ 4146U, // STOSB
+ 5702U, // STOSD
+ 4146U, // STOSW
+ 5708U, // STRm
+ 5708U, // STRr
+ 805312081U, // ST_F32m
+ 939529809U, // ST_F64m
+ 805312086U, // ST_FP32m
+ 939529814U, // ST_FP64m
+ 2147489366U, // ST_FP80m
+ 134223446U, // ST_FPrr
0U, // ST_Fp32m
0U, // ST_Fp64m
0U, // ST_Fp64m32
@@ -2296,51 +2297,51 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // ST_FpP80m
0U, // ST_FpP80m32
0U, // ST_FpP80m64
- 134223414U, // ST_Frr
- 134223425U, // SUB16i16
- 272635467U, // SUB16mi
- 272635467U, // SUB16mi8
- 272635467U, // SUB16mr
- 138548811U, // SUB16ri
- 138548811U, // SUB16ri8
- 138679883U, // SUB16rm
- 138548811U, // SUB16rr
- 138548811U, // SUB16rr_REV
- 134223440U, // SUB32i32
- 406853195U, // SUB32mi
- 406853195U, // SUB32mi8
- 406853195U, // SUB32mr
- 138548811U, // SUB32ri
- 138548811U, // SUB32ri8
- 138810955U, // SUB32rm
- 138548811U, // SUB32rr
- 138548811U, // SUB32rr_REV
- 134223451U, // SUB64i32
- 541070923U, // SUB64mi32
- 541070923U, // SUB64mi8
- 541070923U, // SUB64mr
- 138548811U, // SUB64ri32
- 138548811U, // SUB64ri8
- 138942027U, // SUB64rm
- 138548811U, // SUB64rr
- 138548811U, // SUB64rr_REV
- 134223462U, // SUB8i8
- 675288651U, // SUB8mi
- 675288651U, // SUB8mr
- 138548811U, // SUB8ri
- 139073099U, // SUB8rm
- 138548811U, // SUB8rr
- 138548811U, // SUB8rr_REV
- 139204208U, // SUBPDrm
- 138548848U, // SUBPDrr
- 139204215U, // SUBPSrm
- 138548855U, // SUBPSrr
- 805312126U, // SUBR_F32m
- 939529854U, // SUBR_F64m
- 268441221U, // SUBR_FI16m
- 402658949U, // SUBR_FI32m
- 134223501U, // SUBR_FPrST0
- 134223486U, // SUBR_FST0r
+ 134223441U, // ST_Frr
+ 134223452U, // SUB16i16
+ 272635494U, // SUB16mi
+ 272635494U, // SUB16mi8
+ 272635494U, // SUB16mr
+ 138548838U, // SUB16ri
+ 138548838U, // SUB16ri8
+ 138679910U, // SUB16rm
+ 138548838U, // SUB16rr
+ 138548838U, // SUB16rr_REV
+ 134223467U, // SUB32i32
+ 406853222U, // SUB32mi
+ 406853222U, // SUB32mi8
+ 406853222U, // SUB32mr
+ 138548838U, // SUB32ri
+ 138548838U, // SUB32ri8
+ 138810982U, // SUB32rm
+ 138548838U, // SUB32rr
+ 138548838U, // SUB32rr_REV
+ 134223478U, // SUB64i32
+ 541070950U, // SUB64mi32
+ 541070950U, // SUB64mi8
+ 541070950U, // SUB64mr
+ 138548838U, // SUB64ri32
+ 138548838U, // SUB64ri8
+ 138942054U, // SUB64rm
+ 138548838U, // SUB64rr
+ 138548838U, // SUB64rr_REV
+ 134223489U, // SUB8i8
+ 675288678U, // SUB8mi
+ 675288678U, // SUB8mr
+ 138548838U, // SUB8ri
+ 139073126U, // SUB8rm
+ 138548838U, // SUB8rr
+ 138548838U, // SUB8rr_REV
+ 139204235U, // SUBPDrm
+ 138548875U, // SUBPDrr
+ 139204242U, // SUBPSrm
+ 138548882U, // SUBPSrr
+ 805312153U, // SUBR_F32m
+ 939529881U, // SUBR_F64m
+ 268441248U, // SUBR_FI16m
+ 402658976U, // SUBR_FI32m
+ 134223528U, // SUBR_FPrST0
+ 134223513U, // SUBR_FST0r
0U, // SUBR_Fp32m
0U, // SUBR_Fp64m
0U, // SUBR_Fp64m32
@@ -2352,21 +2353,21 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // SUBR_FpI32m32
0U, // SUBR_FpI32m64
0U, // SUBR_FpI32m80
- 142612094U, // SUBR_FrST0
- 139335317U, // SUBSDrm
- 139335317U, // SUBSDrm_Int
- 138548885U, // SUBSDrr
- 138548885U, // SUBSDrr_Int
- 139466396U, // SUBSSrm
- 139466396U, // SUBSSrm_Int
- 138548892U, // SUBSSrr
- 138548892U, // SUBSSrr_Int
- 805312163U, // SUB_F32m
- 939529891U, // SUB_F64m
- 268441257U, // SUB_FI16m
- 402658985U, // SUB_FI32m
- 134223536U, // SUB_FPrST0
- 134223523U, // SUB_FST0r
+ 142612121U, // SUBR_FrST0
+ 139335344U, // SUBSDrm
+ 139335344U, // SUBSDrm_Int
+ 138548912U, // SUBSDrr
+ 138548912U, // SUBSDrr_Int
+ 139466423U, // SUBSSrm
+ 139466423U, // SUBSSrm_Int
+ 138548919U, // SUBSSrr
+ 138548919U, // SUBSSrr_Int
+ 805312190U, // SUB_F32m
+ 939529918U, // SUB_F64m
+ 268441284U, // SUB_FI16m
+ 402659012U, // SUB_FI32m
+ 134223563U, // SUB_FPrST0
+ 134223550U, // SUB_FST0r
0U, // SUB_Fp32
0U, // SUB_Fp32m
0U, // SUB_Fp64
@@ -2381,45 +2382,45 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
0U, // SUB_FpI32m32
0U, // SUB_FpI32m64
0U, // SUB_FpI32m80
- 142612131U, // SUB_FrST0
- 5815U, // SWAPGS
- 5822U, // SYSCALL
- 5830U, // SYSENTER
- 5839U, // SYSEXIT
- 5839U, // SYSEXIT64
- 5847U, // SYSRET
+ 142612158U, // SUB_FrST0
+ 5842U, // SWAPGS
+ 5849U, // SYSCALL
+ 5857U, // SYSENTER
+ 5866U, // SYSEXIT
+ 5866U, // SYSEXIT64
+ 5874U, // SYSRET
1166019469U, // TAILJMPd
494930829U, // TAILJMPm
226495373U, // TAILJMPr
226495373U, // TAILJMPr64
- 230692574U, // TCRETURNdi
- 230692574U, // TCRETURNdi64
- 230692574U, // TCRETURNri
- 230692574U, // TCRETURNri64
- 134223594U, // TEST16i16
- 272635637U, // TEST16mi
- 139859701U, // TEST16ri
- 139728629U, // TEST16rm
- 139859701U, // TEST16rr
- 134223611U, // TEST32i32
- 406853365U, // TEST32mi
- 139859701U, // TEST32ri
- 139990773U, // TEST32rm
- 139859701U, // TEST32rr
- 134223623U, // TEST64i32
- 541071093U, // TEST64mi32
- 139859701U, // TEST64ri32
- 140121845U, // TEST64rm
- 139859701U, // TEST64rr
- 134223635U, // TEST8i8
- 675288821U, // TEST8mi
- 139859701U, // TEST8ri
- 140252917U, // TEST8rm
- 139859701U, // TEST8rr
- 2952795934U, // TLS_addr32
- 3087013668U, // TLS_addr64
- 5942U, // TRAP
- 5946U, // TST_F
+ 230692601U, // TCRETURNdi
+ 230692601U, // TCRETURNdi64
+ 230692601U, // TCRETURNri
+ 230692601U, // TCRETURNri64
+ 134223621U, // TEST16i16
+ 272635664U, // TEST16mi
+ 139859728U, // TEST16ri
+ 139728656U, // TEST16rm
+ 139859728U, // TEST16rr
+ 134223638U, // TEST32i32
+ 406853392U, // TEST32mi
+ 139859728U, // TEST32ri
+ 139990800U, // TEST32rm
+ 139859728U, // TEST32rr
+ 134223650U, // TEST64i32
+ 541071120U, // TEST64mi32
+ 139859728U, // TEST64ri32
+ 140121872U, // TEST64rm
+ 139859728U, // TEST64rr
+ 134223662U, // TEST8i8
+ 675288848U, // TEST8mi
+ 139859728U, // TEST8ri
+ 140252944U, // TEST8rm
+ 139859728U, // TEST8rr
+ 2952795961U, // TLS_addr32
+ 3087013695U, // TLS_addr64
+ 5969U, // TRAP
+ 5973U, // TST_F
0U, // TST_Fp32
0U, // TST_Fp64
0U, // TST_Fp80
@@ -2427,109 +2428,109 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
139856717U, // UCOMISDrr
140643158U, // UCOMISSrm
139856726U, // UCOMISSrr
- 134223679U, // UCOM_FIPr
- 134223696U, // UCOM_FIr
- 5984U, // UCOM_FPPr
- 134223720U, // UCOM_FPr
+ 134223706U, // UCOM_FIPr
+ 134223723U, // UCOM_FIr
+ 6011U, // UCOM_FPPr
+ 134223747U, // UCOM_FPr
0U, // UCOM_FpIr32
0U, // UCOM_FpIr64
0U, // UCOM_FpIr80
0U, // UCOM_Fpr32
0U, // UCOM_Fpr64
0U, // UCOM_Fpr80
- 134223728U, // UCOM_Fr
- 139204471U, // UNPCKHPDrm
- 138549111U, // UNPCKHPDrr
- 139204481U, // UNPCKHPSrm
- 138549121U, // UNPCKHPSrr
- 139204491U, // UNPCKLPDrm
- 138549131U, // UNPCKLPDrr
- 139204501U, // UNPCKLPSrm
- 138549141U, // UNPCKLPSrr
- 139876255U, // VASTART_SAVE_XMM_REGS
- 268441527U, // VERRm
- 134223799U, // VERRr
- 268441533U, // VERWm
- 134223805U, // VERWr
- 6083U, // VMCALL
- 536877002U, // VMCLEARm
- 6099U, // VMLAUNCH
- 536877020U, // VMPTRLDm
- 536877029U, // VMPTRSTm
- 406853614U, // VMREAD32rm
- 139859950U, // VMREAD32rr
- 541071342U, // VMREAD64rm
- 139859950U, // VMREAD64rr
- 6134U, // VMRESUME
- 139991039U, // VMWRITE32rm
- 139859967U, // VMWRITE32rr
- 140122111U, // VMWRITE64rm
- 139859967U, // VMWRITE64rr
- 6152U, // VMXOFF
- 6159U, // VMXON
+ 134223755U, // UCOM_Fr
+ 139204498U, // UNPCKHPDrm
+ 138549138U, // UNPCKHPDrr
+ 139204508U, // UNPCKHPSrm
+ 138549148U, // UNPCKHPSrr
+ 139204518U, // UNPCKLPDrm
+ 138549158U, // UNPCKLPDrr
+ 139204528U, // UNPCKLPSrm
+ 138549168U, // UNPCKLPSrr
+ 139876282U, // VASTART_SAVE_XMM_REGS
+ 268441554U, // VERRm
+ 134223826U, // VERRr
+ 268441560U, // VERWm
+ 134223832U, // VERWr
+ 6110U, // VMCALL
+ 536877029U, // VMCLEARm
+ 6126U, // VMLAUNCH
+ 536877047U, // VMPTRLDm
+ 536877056U, // VMPTRSTm
+ 406853641U, // VMREAD32rm
+ 139859977U, // VMREAD32rr
+ 541071369U, // VMREAD64rm
+ 139859977U, // VMREAD64rr
+ 6161U, // VMRESUME
+ 139991066U, // VMWRITE32rm
+ 139859994U, // VMWRITE32rr
+ 140122138U, // VMWRITE64rm
+ 139859994U, // VMWRITE64rr
+ 6179U, // VMXOFF
+ 6186U, // VMXON
0U, // V_SET0
0U, // V_SETALLONES
- 6166U, // WAIT
- 6171U, // WBINVD
+ 6193U, // WAIT
+ 6198U, // WBINVD
536871957U, // WINCALL64m
1073742869U, // WINCALL64pcrel32
134218773U, // WINCALL64r
- 6178U, // WRMSR
- 272635944U, // XADD16rm
- 139860008U, // XADD16rr
- 406853672U, // XADD32rm
- 139860008U, // XADD32rr
- 541071400U, // XADD64rm
- 139860008U, // XADD64rr
- 675289128U, // XADD8rm
- 139860008U, // XADD8rr
- 134223918U, // XCHG16ar
- 2281707577U, // XCHG16rm
- 3221231673U, // XCHG16rr
- 134223935U, // XCHG32ar
- 2415925305U, // XCHG32rm
- 3221231673U, // XCHG32rr
- 134223947U, // XCHG64ar
- 3355449401U, // XCHG64rm
- 3221231673U, // XCHG64rr
- 2550143033U, // XCHG8rm
- 3221231673U, // XCHG8rr
- 134223959U, // XCH_F
- 6237U, // XLAT
- 134223971U, // XOR16i16
- 272636013U, // XOR16mi
- 272636013U, // XOR16mi8
- 272636013U, // XOR16mr
- 138549357U, // XOR16ri
- 138549357U, // XOR16ri8
- 138680429U, // XOR16rm
- 138549357U, // XOR16rr
- 138549357U, // XOR16rr_REV
- 134223986U, // XOR32i32
- 406853741U, // XOR32mi
- 406853741U, // XOR32mi8
- 406853741U, // XOR32mr
- 138549357U, // XOR32ri
- 138549357U, // XOR32ri8
- 138811501U, // XOR32rm
- 138549357U, // XOR32rr
- 138549357U, // XOR32rr_REV
- 134223997U, // XOR64i32
- 541071469U, // XOR64mi32
- 541071469U, // XOR64mi8
- 541071469U, // XOR64mr
- 138549357U, // XOR64ri32
- 138549357U, // XOR64ri8
- 138942573U, // XOR64rm
- 138549357U, // XOR64rr
- 138549357U, // XOR64rr_REV
- 134224008U, // XOR8i8
- 675289197U, // XOR8mi
- 675289197U, // XOR8mr
- 138549357U, // XOR8ri
- 139073645U, // XOR8rm
- 138549357U, // XOR8rr
- 138549357U, // XOR8rr_REV
+ 6205U, // WRMSR
+ 272635971U, // XADD16rm
+ 139860035U, // XADD16rr
+ 406853699U, // XADD32rm
+ 139860035U, // XADD32rr
+ 541071427U, // XADD64rm
+ 139860035U, // XADD64rr
+ 675289155U, // XADD8rm
+ 139860035U, // XADD8rr
+ 134223945U, // XCHG16ar
+ 2281707604U, // XCHG16rm
+ 3221231700U, // XCHG16rr
+ 134223962U, // XCHG32ar
+ 2415925332U, // XCHG32rm
+ 3221231700U, // XCHG32rr
+ 134223974U, // XCHG64ar
+ 3355449428U, // XCHG64rm
+ 3221231700U, // XCHG64rr
+ 2550143060U, // XCHG8rm
+ 3221231700U, // XCHG8rr
+ 134223986U, // XCH_F
+ 6264U, // XLAT
+ 134223998U, // XOR16i16
+ 272636040U, // XOR16mi
+ 272636040U, // XOR16mi8
+ 272636040U, // XOR16mr
+ 138549384U, // XOR16ri
+ 138549384U, // XOR16ri8
+ 138680456U, // XOR16rm
+ 138549384U, // XOR16rr
+ 138549384U, // XOR16rr_REV
+ 134224013U, // XOR32i32
+ 406853768U, // XOR32mi
+ 406853768U, // XOR32mi8
+ 406853768U, // XOR32mr
+ 138549384U, // XOR32ri
+ 138549384U, // XOR32ri8
+ 138811528U, // XOR32rm
+ 138549384U, // XOR32rr
+ 138549384U, // XOR32rr_REV
+ 134224024U, // XOR64i32
+ 541071496U, // XOR64mi32
+ 541071496U, // XOR64mi8
+ 541071496U, // XOR64mr
+ 138549384U, // XOR64ri32
+ 138549384U, // XOR64ri8
+ 138942600U, // XOR64rm
+ 138549384U, // XOR64rr
+ 138549384U, // XOR64rr_REV
+ 134224035U, // XOR8i8
+ 675289224U, // XOR8mi
+ 675289224U, // XOR8mr
+ 138549384U, // XOR8ri
+ 139073672U, // XOR8rm
+ 138549384U, // XOR8rr
+ 138549384U, // XOR8rr_REV
139201054U, // XORPDrm
138545694U, // XORPDrr
139201061U, // XORPSrm
@@ -2601,68 +2602,68 @@ void X86IntelInstPrinter::printInstruction(const MachineInstr *MI) {
"k\n\tadd\t\000lock\n\tdec\t\000lock\n\tinc\t\000lock\000lock\n\tsub\t\000"
"lodsb\000lodsd\000lodsq\000lodsw\000loop\t\000loope\t\000loopne\t\000lr"
"et\000lret\t\000lsl\t\000lss\t\000ltr\t\000lock\n\txadd\t\000maskmovdqu"
- "\t\000maxpd\t\000maxps\t\000maxsd\t\000maxss\t\000mfence\000minpd\t\000"
- "minps\t\000minsd\t\000minss\t\000emms\000femms\000maskmovq\t\000movd\t\000"
- "movdq2q\t\000movntq\t\000movq2dq\t\000movq\t\000packssdw\t\000packsswb\t"
- "\000packuswb\t\000paddb\t\000paddd\t\000paddq\t\000paddsb\t\000paddsw\t"
- "\000paddusb\t\000paddusw\t\000paddw\t\000pandn\t\000pand\t\000pavgb\t\000"
- "pavgw\t\000pcmpeqb\t\000pcmpeqd\t\000pcmpeqw\t\000pcmpgtb\t\000pcmpgtd\t"
- "\000pcmpgtw\t\000pextrw\t\000pinsrw\t\000pmaddwd\t\000pmaxsw\t\000pmaxu"
- "b\t\000pminsw\t\000pminub\t\000pmovmskb\t\000pmulhuw\t\000pmulhw\t\000p"
- "mullw\t\000pmuludq\t\000por\t\000psadbw\t\000pshufw\t\000pslld\t\000psl"
- "lq\t\000psllw\t\000psrad\t\000psraw\t\000psrld\t\000psrlq\t\000psrlw\t\000"
- "psubb\t\000psubd\t\000psubq\t\000psubsb\t\000psubsw\t\000psubusb\t\000p"
- "subusw\t\000psubw\t\000punpckhbw\t\000punpckhdq\t\000punpckhwd\t\000pun"
- "pcklbw\t\000punpckldq\t\000punpcklwd\t\000pxor\t\000monitor\000mov\t\000"
- "mov\t%ax, \000mov\t%eax, \000movq\t%fs:\000movq\t%gs:\000mov\t%rax, \000"
- "movabs\t\000mov\t%al, \000movddup\t\000movdqa\t\000movdqu\t\000movhlps\t"
- "\000movhpd\t\000movhps\t\000movlhps\t\000movlpd\t\000movlps\t\000movmsk"
- "pd\t\000movmskps\t\000movntdqa\t\000movntdq\t\000movnti\t\000movntpd\t\000"
- "movntps\t\000\000movsd\000movsd\t\000movshdup\t\000movsldup\t\000movss\t"
- "\000movsx\t\000movsxd\t\000movupd\t\000movups\t\000movzx\t\000mpsadbw\t"
- "\000mul\t\000mulpd\t\000mulps\t\000mulsd\t\000mulss\t\000fmul\t\000fimu"
- "l\t\000fmulp\t\000mwait\000neg\t\000nop\000nop\t\000not\t\000or\t%ax, \000"
- "or\t\000or\t%eax, \000or\t%rax, \000or\t%al, \000out\t\000out\t%DX, %AX"
- "\000out\t%DX, %EAX\000out\t%DX, %AL\000outsb\000outsd\000outsw\000pabsb"
- "\t\000pabsd\t\000pabsw\t\000packusdw\t\000palignr\t\000pblendvb\t\000pb"
- "lendw\t\000pcmpeqq\t\000pcmpestri\t\000#PCMPESTRM128rm PSEUDO!\000#PCMP"
- "ESTRM128rr PSEUDO!\000pcmpestrm\t\000pcmpgtq\t\000pcmpistri\t\000#PCMPI"
- "STRM128rm PSEUDO!\000#PCMPISTRM128rr PSEUDO!\000pcmpistrm\t\000pextrb\t"
- "\000pextrd\t\000pextrq\t\000phaddd\t\000phaddsw\t\000phaddw\t\000phminp"
- "osuw\t\000phsubd\t\000phsubsw\t\000phsubw\t\000pinsrb\t\000pinsrd\t\000"
- "pinsrq\t\000pmaddubsw\t\000pmaxsb\t\000pmaxsd\t\000pmaxud\t\000pmaxuw\t"
- "\000pminsb\t\000pminsd\t\000pminud\t\000pminuw\t\000pmovsxbd\t\000pmovs"
- "xbq\t\000pmovsxbw\t\000pmovsxdq\t\000pmovsxwd\t\000pmovsxwq\t\000pmovzx"
- "bd\t\000pmovzxbq\t\000pmovzxbw\t\000pmovzxdq\t\000pmovzxwd\t\000pmovzxw"
- "q\t\000pmuldq\t\000pmulhrsw\t\000pmulld\t\000pop\t\000popcnt\t\000popf\000"
- "pop\t%fs\000pop\t%gs\000prefetchnta\t\000prefetcht0\t\000prefetcht1\t\000"
- "prefetcht2\t\000pshufb\t\000pshufd\t\000pshufhw\t\000pshuflw\t\000psign"
- "b\t\000psignd\t\000psignw\t\000pslldq\t\000psrldq\t\000ptest \t\000punp"
- "ckhqdq\t\000punpcklqdq\t\000push\t\000pushf\000push\t%fs\000push\t%gs\000"
- "rcl\t\000rcpps\t\000rcpss\t\000rcr\t\000rdmsr\000rdpmc\000rdtsc\000rdts"
- "cp\000repne\000rep movsb\000rep movsd\000rep movsq\000rep movsw\000rep\000"
- "rep stosb\000rep stosd\000rep stosq\000rep stosw\000ret\000ret\t\000rol"
- "\t\000ror\t\000roundpd\t\000roundps\t\000roundsd\t\000roundss\t\000rsm\000"
- "rsqrtps\t\000rsqrtss\t\000sahf\000sar\t\000sbb\t%ax, \000sbb\t\000sbb\t"
- "%eax, \000sbb\t%rax, \000sbb\t%al, \000scas\000setae\t\000seta\t\000set"
- "be\t\000setb\t\000sete\t\000setge\t\000setg\t\000setle\t\000setl\t\000s"
- "etne\t\000setno\t\000setnp\t\000setns\t\000seto\t\000setp\t\000sets\t\000"
- "sfence\000sgdt\t\000shl\t\000shld\t\000shr\t\000shrd\t\000shufpd\t\000s"
- "hufps\t\000sidt\t\000fsin\000sldt\t\000smsw\t\000sqrtpd\t\000sqrtps\t\000"
- "sqrtsd\t\000sqrtss\t\000fsqrt\000ss\000stc\000std\000sti\000stmxcsr\t\000"
- "stosd\000str\t\000fst\t\000fstp\t\000sub\t%ax, \000sub\t\000sub\t%eax, "
- "\000sub\t%rax, \000sub\t%al, \000subpd\t\000subps\t\000fsubr\t\000fisub"
- "r\t\000fsubrp\t\000subsd\t\000subss\t\000fsub\t\000fisub\t\000fsubp\t\000"
- "swapgs\000syscall\000sysenter\000sysexit\000sysret\000#TC_RETURN \000te"
- "st\t%ax, \000test\t\000test\t%eax, \000test\t%rax, \000test\t%al, \000l"
- "eal\t\000.byte\t0x66; leaq\t\000ud2\000ftst\000fucomip\t%ST(0), \000fuc"
- "omi\t%ST(0), \000fucompp\000fucomp\t\000fucom\t\000unpckhpd\t\000unpckh"
- "ps\t\000unpcklpd\t\000unpcklps\t\000#VASTART_SAVE_XMM_REGS \000verr\t\000"
- "verw\t\000vmcall\000vmclear\t\000vmlaunch\000vmptrld\t\000vmptrst\t\000"
- "vmread\t\000vmresume\000vmwrite\t\000vmxoff\000vmxon\t\000wait\000wbinv"
- "d\000wrmsr\000xadd\t\000xchg\t%ax, \000xchg\t\000xchg\t%eax, \000xchg\t"
- "%rax, \000fxch\t\000xlatb\000xor\t%ax, \000xor\t\000xor\t%eax, \000xor\t"
- "%rax, \000xor\t%al, \000";
+ "\t\000maxpd\t\000maxps\t\000maxsd\t\000maxss\t\000mfence\000# dynamic s"
+ "tack allocation\000minpd\t\000minps\t\000minsd\t\000minss\t\000emms\000"
+ "femms\000maskmovq\t\000movd\t\000movdq2q\t\000movntq\t\000movq2dq\t\000"
+ "movq\t\000packssdw\t\000packsswb\t\000packuswb\t\000paddb\t\000paddd\t\000"
+ "paddq\t\000paddsb\t\000paddsw\t\000paddusb\t\000paddusw\t\000paddw\t\000"
+ "pandn\t\000pand\t\000pavgb\t\000pavgw\t\000pcmpeqb\t\000pcmpeqd\t\000pc"
+ "mpeqw\t\000pcmpgtb\t\000pcmpgtd\t\000pcmpgtw\t\000pextrw\t\000pinsrw\t\000"
+ "pmaddwd\t\000pmaxsw\t\000pmaxub\t\000pminsw\t\000pminub\t\000pmovmskb\t"
+ "\000pmulhuw\t\000pmulhw\t\000pmullw\t\000pmuludq\t\000por\t\000psadbw\t"
+ "\000pshufw\t\000pslld\t\000psllq\t\000psllw\t\000psrad\t\000psraw\t\000"
+ "psrld\t\000psrlq\t\000psrlw\t\000psubb\t\000psubd\t\000psubq\t\000psubs"
+ "b\t\000psubsw\t\000psubusb\t\000psubusw\t\000psubw\t\000punpckhbw\t\000"
+ "punpckhdq\t\000punpckhwd\t\000punpcklbw\t\000punpckldq\t\000punpcklwd\t"
+ "\000pxor\t\000monitor\000mov\t\000mov\t%ax, \000mov\t%eax, \000movq\t%f"
+ "s:\000movq\t%gs:\000mov\t%rax, \000movabs\t\000mov\t%al, \000movddup\t\000"
+ "movdqa\t\000movdqu\t\000movhlps\t\000movhpd\t\000movhps\t\000movlhps\t\000"
+ "movlpd\t\000movlps\t\000movmskpd\t\000movmskps\t\000movntdqa\t\000movnt"
+ "dq\t\000movnti\t\000movntpd\t\000movntps\t\000\000movsd\000movsd\t\000m"
+ "ovshdup\t\000movsldup\t\000movss\t\000movsx\t\000movsxd\t\000movupd\t\000"
+ "movups\t\000movzx\t\000mpsadbw\t\000mul\t\000mulpd\t\000mulps\t\000muls"
+ "d\t\000mulss\t\000fmul\t\000fimul\t\000fmulp\t\000mwait\000neg\t\000nop"
+ "\000nop\t\000not\t\000or\t%ax, \000or\t\000or\t%eax, \000or\t%rax, \000"
+ "or\t%al, \000out\t\000out\t%DX, %AX\000out\t%DX, %EAX\000out\t%DX, %AL\000"
+ "outsb\000outsd\000outsw\000pabsb\t\000pabsd\t\000pabsw\t\000packusdw\t\000"
+ "palignr\t\000pblendvb\t\000pblendw\t\000pcmpeqq\t\000pcmpestri\t\000#PC"
+ "MPESTRM128rm PSEUDO!\000#PCMPESTRM128rr PSEUDO!\000pcmpestrm\t\000pcmpg"
+ "tq\t\000pcmpistri\t\000#PCMPISTRM128rm PSEUDO!\000#PCMPISTRM128rr PSEUD"
+ "O!\000pcmpistrm\t\000pextrb\t\000pextrd\t\000pextrq\t\000phaddd\t\000ph"
+ "addsw\t\000phaddw\t\000phminposuw\t\000phsubd\t\000phsubsw\t\000phsubw\t"
+ "\000pinsrb\t\000pinsrd\t\000pinsrq\t\000pmaddubsw\t\000pmaxsb\t\000pmax"
+ "sd\t\000pmaxud\t\000pmaxuw\t\000pminsb\t\000pminsd\t\000pminud\t\000pmi"
+ "nuw\t\000pmovsxbd\t\000pmovsxbq\t\000pmovsxbw\t\000pmovsxdq\t\000pmovsx"
+ "wd\t\000pmovsxwq\t\000pmovzxbd\t\000pmovzxbq\t\000pmovzxbw\t\000pmovzxd"
+ "q\t\000pmovzxwd\t\000pmovzxwq\t\000pmuldq\t\000pmulhrsw\t\000pmulld\t\000"
+ "pop\t\000popcnt\t\000popf\000pop\t%fs\000pop\t%gs\000prefetchnta\t\000p"
+ "refetcht0\t\000prefetcht1\t\000prefetcht2\t\000pshufb\t\000pshufd\t\000"
+ "pshufhw\t\000pshuflw\t\000psignb\t\000psignd\t\000psignw\t\000pslldq\t\000"
+ "psrldq\t\000ptest \t\000punpckhqdq\t\000punpcklqdq\t\000push\t\000pushf"
+ "\000push\t%fs\000push\t%gs\000rcl\t\000rcpps\t\000rcpss\t\000rcr\t\000r"
+ "dmsr\000rdpmc\000rdtsc\000rdtscp\000repne\000rep movsb\000rep movsd\000"
+ "rep movsq\000rep movsw\000rep\000rep stosb\000rep stosd\000rep stosq\000"
+ "rep stosw\000ret\000ret\t\000rol\t\000ror\t\000roundpd\t\000roundps\t\000"
+ "roundsd\t\000roundss\t\000rsm\000rsqrtps\t\000rsqrtss\t\000sahf\000sar\t"
+ "\000sbb\t%ax, \000sbb\t\000sbb\t%eax, \000sbb\t%rax, \000sbb\t%al, \000"
+ "scas\000setae\t\000seta\t\000setbe\t\000setb\t\000sete\t\000setge\t\000"
+ "setg\t\000setle\t\000setl\t\000setne\t\000setno\t\000setnp\t\000setns\t"
+ "\000seto\t\000setp\t\000sets\t\000sfence\000sgdt\t\000shl\t\000shld\t\000"
+ "shr\t\000shrd\t\000shufpd\t\000shufps\t\000sidt\t\000fsin\000sldt\t\000"
+ "smsw\t\000sqrtpd\t\000sqrtps\t\000sqrtsd\t\000sqrtss\t\000fsqrt\000ss\000"
+ "stc\000std\000sti\000stmxcsr\t\000stosd\000str\t\000fst\t\000fstp\t\000"
+ "sub\t%ax, \000sub\t\000sub\t%eax, \000sub\t%rax, \000sub\t%al, \000subp"
+ "d\t\000subps\t\000fsubr\t\000fisubr\t\000fsubrp\t\000subsd\t\000subss\t"
+ "\000fsub\t\000fisub\t\000fsubp\t\000swapgs\000syscall\000sysenter\000sy"
+ "sexit\000sysret\000#TC_RETURN \000test\t%ax, \000test\t\000test\t%eax, "
+ "\000test\t%rax, \000test\t%al, \000leal\t\000.byte\t0x66; leaq\t\000ud2"
+ "\000ftst\000fucomip\t%ST(0), \000fucomi\t%ST(0), \000fucompp\000fucomp\t"
+ "\000fucom\t\000unpckhpd\t\000unpckhps\t\000unpcklpd\t\000unpcklps\t\000"
+ "#VASTART_SAVE_XMM_REGS \000verr\t\000verw\t\000vmcall\000vmclear\t\000v"
+ "mlaunch\000vmptrld\t\000vmptrst\t\000vmread\t\000vmresume\000vmwrite\t\000"
+ "vmxoff\000vmxon\t\000wait\000wbinvd\000wrmsr\000xadd\t\000xchg\t%ax, \000"
+ "xchg\t\000xchg\t%eax, \000xchg\t%rax, \000fxch\t\000xlatb\000xor\t%ax, "
+ "\000xor\t\000xor\t%eax, \000xor\t%rax, \000xor\t%al, \000";
O << "\t";
@@ -3366,7 +3367,7 @@ const char *X86IntelInstPrinter::getRegisterName(unsigned RegNo) {
/// from the instruction set description. This returns the enum name of the
/// specified instruction.
const char *X86IntelInstPrinter::getInstructionName(unsigned Opcode) {
- assert(Opcode < 2524 && "Invalid instruction number!");
+ assert(Opcode < 2525 && "Invalid instruction number!");
static const unsigned InstAsmOffset[] = {
0, 4, 14, 24, 33, 42, 47, 62, 76, 89, 103, 120, 130, 136,
@@ -3446,110 +3447,110 @@ const char *X86IntelInstPrinter::getInstructionName(unsigned Opcode) {
10305, 10317, 10329, 10335, 10341, 10347, 10353, 10358, 10364, 10371, 10376, 10382, 10390, 10398,
10406, 10414, 10422, 10430, 10438, 10446, 10454, 10459, 10464, 10472, 10480, 10488, 10495, 10506,
10519, 10527, 10539, 10547, 10559, 10567, 10579, 10587, 10599, 10607, 10619, 10627, 10639, 10647,
- 10659, 10667, 10679, 10686, 10694, 10706, 10714, 10726, 10734, 10746, 10754, 10766, 10774, 10786,
- 10794, 10806, 10814, 10826, 10834, 10846, 10861, 10876, 10891, 10906, 10921, 10936, 10951, 10966,
- 10982, 10998, 11014, 11030, 11039, 11049, 11062, 11077, 11096, 11110, 11123, 11136, 11149, 11166,
- 11183, 11197, 11210, 11224, 11240, 11254, 11267, 11280, 11293, 11310, 11327, 11342, 11357, 11372,
- 11387, 11402, 11417, 11429, 11441, 11453, 11465, 11477, 11489, 11502, 11515, 11528, 11541, 11555,
- 11569, 11583, 11597, 11609, 11621, 11633, 11645, 11656, 11667, 11679, 11691, 11703, 11715, 11729,
- 11743, 11757, 11771, 11785, 11799, 11813, 11827, 11841, 11855, 11869, 11883, 11896, 11910, 11924,
- 11938, 11952, 11965, 11978, 11991, 12004, 12017, 12030, 12043, 12056, 12071, 12085, 12099, 12112,
- 12125, 12138, 12151, 12165, 12179, 12189, 12199, 12212, 12225, 12238, 12251, 12263, 12275, 12287,
- 12299, 12311, 12323, 12335, 12347, 12359, 12371, 12383, 12395, 12407, 12419, 12431, 12443, 12455,
- 12467, 12479, 12491, 12503, 12515, 12527, 12539, 12551, 12563, 12575, 12587, 12599, 12611, 12624,
- 12637, 12650, 12663, 12677, 12691, 12705, 12719, 12731, 12743, 12759, 12775, 12791, 12807, 12823,
- 12839, 12855, 12871, 12887, 12903, 12919, 12935, 12946, 12957, 12968, 12985, 12993, 13003, 13011,
- 13019, 13027, 13037, 13045, 13053, 13061, 13069, 13081, 13089, 13097, 13105, 13115, 13123, 13131,
- 13139, 13147, 13157, 13165, 13173, 13181, 13189, 13197, 13205, 13217, 13227, 13237, 13247, 13256,
- 13264, 13272, 13282, 13290, 13298, 13308, 13317, 13325, 13333, 13341, 13349, 13359, 13372, 13380,
- 13388, 13400, 13408, 13416, 13424, 13437, 13449, 13461, 13469, 13476, 13483, 13496, 13504, 13511,
- 13518, 13525, 13538, 13545, 13558, 13569, 13578, 13587, 13596, 13605, 13614, 13623, 13633, 13643,
- 13655, 13667, 13678, 13689, 13698, 13707, 13716, 13725, 13738, 13747, 13760, 13770, 13779, 13788,
- 13797, 13806, 13816, 13825, 13834, 13843, 13852, 13863, 13874, 13885, 13896, 13909, 13919, 13933,
- 13945, 13954, 13967, 13977, 13991, 14001, 14015, 14024, 14036, 14048, 14060, 14073, 14085, 14094,
- 14100, 14106, 14114, 14122, 14130, 14142, 14154, 14165, 14176, 14187, 14198, 14209, 14220, 14228,
- 14236, 14244, 14250, 14261, 14273, 14284, 14296, 14308, 14319, 14331, 14342, 14354, 14366, 14377,
- 14389, 14401, 14412, 14421, 14434, 14443, 14456, 14465, 14474, 14487, 14496, 14509, 14518, 14531,
- 14544, 14560, 14576, 14589, 14602, 14613, 14625, 14636, 14648, 14665, 14682, 14694, 14705, 14717,
- 14728, 14740, 14754, 14766, 14777, 14790, 14802, 14816, 14828, 14839, 14852, 14863, 14874, 14885,
- 14896, 14907, 14918, 14929, 14940, 14951, 14962, 14973, 14980, 14987, 14994, 15001, 15008, 15015,
- 15021, 15027, 15035, 15043, 15051, 15059, 15067, 15079, 15087, 15099, 15107, 15119, 15127, 15139,
- 15148, 15157, 15167, 15177, 15188, 15198, 15207, 15217, 15226, 15236, 15248, 15257, 15269, 15281,
- 15294, 15307, 15320, 15333, 15346, 15359, 15369, 15375, 15382, 15389, 15396, 15403, 15410, 15417,
- 15423, 15429, 15434, 15440, 15446, 15453, 15460, 15467, 15474, 15481, 15488, 15494, 15500, 15508,
- 15515, 15523, 15530, 15537, 15545, 15552, 15559, 15570, 15578, 15585, 15593, 15600, 15607, 15615,
- 15622, 15629, 15640, 15648, 15657, 15665, 15672, 15681, 15689, 15696, 15703, 15714, 15720, 15726,
- 15732, 15738, 15744, 15750, 15760, 15767, 15774, 15781, 15788, 15796, 15804, 15812, 15820, 15827,
- 15834, 15840, 15846, 15852, 15863, 15873, 15884, 15894, 15905, 15915, 15926, 15936, 15947, 15957,
- 15968, 15978, 15989, 16000, 16011, 16022, 16033, 16044, 16055, 16066, 16074, 16082, 16090, 16098,
- 16106, 16114, 16123, 16132, 16141, 16150, 16160, 16170, 16180, 16190, 16198, 16206, 16219, 16232,
- 16244, 16256, 16264, 16272, 16279, 16286, 16294, 16302, 16310, 16318, 16330, 16342, 16353, 16364,
- 16374, 16384, 16394, 16404, 16414, 16424, 16434, 16444, 16457, 16470, 16483, 16496, 16509, 16522,
- 16535, 16548, 16561, 16574, 16586, 16598, 16614, 16630, 16645, 16660, 16670, 16680, 16690, 16700,
- 16710, 16720, 16730, 16740, 16753, 16766, 16779, 16792, 16805, 16818, 16831, 16844, 16857, 16870,
- 16882, 16894, 16910, 16926, 16941, 16956, 16965, 16974, 16983, 16992, 17001, 17010, 17019, 17028,
- 17040, 17051, 17063, 17074, 17087, 17099, 17112, 17124, 17136, 17147, 17159, 17170, 17186, 17202,
- 17214, 17225, 17237, 17248, 17261, 17273, 17286, 17298, 17310, 17321, 17333, 17344, 17353, 17362,
- 17371, 17380, 17389, 17398, 17408, 17418, 17433, 17447, 17462, 17476, 17486, 17496, 17505, 17514,
- 17523, 17532, 17541, 17550, 17559, 17568, 17577, 17586, 17595, 17604, 17613, 17622, 17631, 17640,
- 17649, 17658, 17667, 17676, 17685, 17694, 17703, 17712, 17723, 17734, 17745, 17756, 17767, 17778,
- 17789, 17800, 17811, 17822, 17833, 17844, 17855, 17866, 17877, 17888, 17899, 17910, 17921, 17932,
- 17943, 17954, 17965, 17976, 17987, 17996, 18005, 18019, 18032, 18046, 18059, 18069, 18079, 18088,
- 18097, 18106, 18119, 18128, 18141, 18150, 18159, 18169, 18179, 18186, 18195, 18204, 18211, 18220,
- 18229, 18236, 18245, 18254, 18265, 18276, 18287, 18298, 18309, 18320, 18325, 18331, 18337, 18345,
- 18353, 18361, 18369, 18377, 18385, 18391, 18397, 18409, 18420, 18431, 18442, 18451, 18460, 18472,
- 18483, 18495, 18506, 18515, 18524, 18534, 18544, 18554, 18564, 18576, 18587, 18599, 18610, 18622,
- 18633, 18645, 18656, 18668, 18679, 18691, 18702, 18711, 18719, 18727, 18735, 18743, 18751, 18759,
- 18767, 18775, 18783, 18791, 18799, 18807, 18815, 18823, 18831, 18840, 18848, 18856, 18864, 18872,
- 18880, 18888, 18896, 18904, 18912, 18920, 18928, 18936, 18944, 18952, 18960, 18969, 18978, 18987,
- 18996, 19006, 19016, 19026, 19036, 19044, 19052, 19060, 19068, 19080, 19092, 19104, 19116, 19129,
- 19142, 19154, 19166, 19178, 19190, 19202, 19214, 19227, 19240, 19252, 19264, 19272, 19282, 19292,
- 19302, 19312, 19321, 19329, 19339, 19349, 19359, 19369, 19378, 19386, 19396, 19406, 19412, 19419,
- 19428, 19437, 19446, 19455, 19464, 19473, 19482, 19489, 19496, 19504, 19513, 19521, 19529, 19538,
- 19546, 19554, 19563, 19571, 19579, 19588, 19596, 19604, 19613, 19621, 19629, 19638, 19646, 19653,
- 19661, 19668, 19675, 19683, 19690, 19697, 19708, 19715, 19726, 19733, 19744, 19751, 19762, 19770,
- 19779, 19787, 19795, 19804, 19812, 19820, 19829, 19837, 19845, 19854, 19862, 19870, 19879, 19887,
- 19895, 19904, 19912, 19919, 19927, 19934, 19941, 19949, 19956, 19962, 19968, 19974, 19981, 19994,
- 20004, 20014, 20024, 20034, 20045, 20055, 20065, 20075, 20085, 20089, 20094, 20102, 20111, 20119,
- 20127, 20136, 20144, 20152, 20161, 20169, 20177, 20186, 20194, 20202, 20211, 20219, 20227, 20236,
- 20244, 20251, 20259, 20266, 20273, 20281, 20288, 20296, 20305, 20313, 20321, 20330, 20338, 20346,
- 20355, 20363, 20371, 20380, 20388, 20396, 20405, 20413, 20421, 20430, 20438, 20445, 20453, 20460,
- 20467, 20475, 20482, 20495, 20508, 20521, 20534, 20547, 20560, 20573, 20586, 20590, 20599, 20612,
- 20621, 20634, 20643, 20656, 20665, 20678, 20683, 20691, 20700, 20708, 20716, 20725, 20733, 20741,
- 20750, 20758, 20766, 20775, 20783, 20791, 20800, 20808, 20816, 20825, 20833, 20840, 20848, 20855,
- 20862, 20870, 20877, 20886, 20894, 20903, 20911, 20919, 20928, 20936, 20944, 20956, 20965, 20973,
- 20982, 20990, 20998, 21007, 21015, 21023, 21035, 21044, 21054, 21063, 21071, 21081, 21090, 21098,
- 21106, 21118, 21125, 21132, 21139, 21146, 21153, 21160, 21171, 21178, 21185, 21192, 21198, 21205,
- 21212, 21218, 21224, 21231, 21238, 21248, 21258, 21268, 21277, 21283, 21289, 21295, 21301, 21308,
- 21315, 21321, 21327, 21334, 21341, 21347, 21353, 21360, 21367, 21374, 21381, 21388, 21395, 21402,
- 21409, 21415, 21421, 21427, 21433, 21439, 21445, 21452, 21458, 21466, 21475, 21483, 21491, 21500,
- 21508, 21516, 21525, 21533, 21541, 21550, 21558, 21566, 21575, 21583, 21591, 21600, 21608, 21615,
- 21623, 21630, 21637, 21645, 21652, 21663, 21674, 21685, 21696, 21707, 21718, 21729, 21740, 21751,
- 21762, 21773, 21784, 21792, 21801, 21809, 21817, 21826, 21834, 21842, 21851, 21859, 21867, 21876,
- 21884, 21892, 21901, 21909, 21917, 21926, 21934, 21941, 21949, 21956, 21963, 21971, 21978, 21989,
- 22000, 22011, 22022, 22033, 22044, 22055, 22066, 22077, 22088, 22099, 22110, 22120, 22130, 22140,
- 22150, 22156, 22162, 22171, 22180, 22189, 22197, 22205, 22213, 22221, 22229, 22237, 22245, 22253,
- 22261, 22273, 22281, 22293, 22301, 22313, 22321, 22333, 22341, 22353, 22361, 22373, 22381, 22393,
- 22401, 22413, 22420, 22430, 22440, 22450, 22460, 22464, 22468, 22472, 22480, 22486, 22492, 22498,
- 22503, 22508, 22516, 22524, 22533, 22542, 22551, 22559, 22568, 22577, 22588, 22599, 22610, 22620,
- 22630, 22642, 22652, 22664, 22676, 22683, 22692, 22700, 22709, 22717, 22725, 22734, 22742, 22750,
- 22762, 22771, 22779, 22788, 22796, 22804, 22813, 22821, 22829, 22841, 22850, 22860, 22869, 22877,
- 22887, 22896, 22904, 22912, 22924, 22931, 22938, 22945, 22952, 22959, 22966, 22977, 22985, 22993,
- 23001, 23009, 23019, 23029, 23040, 23051, 23063, 23074, 23085, 23096, 23109, 23122, 23135, 23149,
- 23163, 23177, 23191, 23205, 23219, 23230, 23238, 23250, 23258, 23270, 23278, 23290, 23298, 23310,
- 23319, 23328, 23338, 23348, 23359, 23369, 23378, 23388, 23397, 23407, 23419, 23428, 23440, 23452,
- 23465, 23478, 23491, 23504, 23517, 23530, 23540, 23547, 23555, 23564, 23572, 23582, 23589, 23598,
- 23607, 23616, 23627, 23638, 23651, 23662, 23675, 23685, 23694, 23703, 23712, 23721, 23731, 23740,
- 23749, 23758, 23767, 23777, 23788, 23799, 23808, 23817, 23825, 23833, 23841, 23849, 23857, 23868,
- 23879, 23884, 23890, 23899, 23908, 23917, 23927, 23937, 23947, 23957, 23967, 23976, 23986, 23995,
- 24007, 24019, 24031, 24042, 24053, 24064, 24072, 24083, 24094, 24105, 24116, 24127, 24138, 24149,
- 24160, 24182, 24188, 24194, 24200, 24206, 24213, 24222, 24231, 24240, 24249, 24260, 24271, 24282,
- 24293, 24302, 24314, 24326, 24338, 24350, 24357, 24363, 24370, 24383, 24388, 24395, 24406, 24423,
- 24434, 24440, 24449, 24458, 24467, 24476, 24485, 24494, 24502, 24510, 24519, 24528, 24537, 24546,
- 24555, 24564, 24573, 24582, 24591, 24599, 24607, 24613, 24618, 24627, 24635, 24644, 24652, 24660,
- 24669, 24677, 24685, 24697, 24706, 24714, 24723, 24731, 24739, 24748, 24756, 24764, 24776, 24785,
- 24795, 24804, 24812, 24822, 24831, 24839, 24847, 24859, 24866, 24873, 24880, 24887, 24894, 24901,
- 24912, 24920, 24928, 24936, 0
+ 10659, 10667, 10679, 10686, 10699, 10707, 10719, 10727, 10739, 10747, 10759, 10767, 10779, 10787,
+ 10799, 10807, 10819, 10827, 10839, 10847, 10859, 10874, 10889, 10904, 10919, 10934, 10949, 10964,
+ 10979, 10995, 11011, 11027, 11043, 11052, 11062, 11075, 11090, 11109, 11123, 11136, 11149, 11162,
+ 11179, 11196, 11210, 11223, 11237, 11253, 11267, 11280, 11293, 11306, 11323, 11340, 11355, 11370,
+ 11385, 11400, 11415, 11430, 11442, 11454, 11466, 11478, 11490, 11502, 11515, 11528, 11541, 11554,
+ 11568, 11582, 11596, 11610, 11622, 11634, 11646, 11658, 11669, 11680, 11692, 11704, 11716, 11728,
+ 11742, 11756, 11770, 11784, 11798, 11812, 11826, 11840, 11854, 11868, 11882, 11896, 11909, 11923,
+ 11937, 11951, 11965, 11978, 11991, 12004, 12017, 12030, 12043, 12056, 12069, 12084, 12098, 12112,
+ 12125, 12138, 12151, 12164, 12178, 12192, 12202, 12212, 12225, 12238, 12251, 12264, 12276, 12288,
+ 12300, 12312, 12324, 12336, 12348, 12360, 12372, 12384, 12396, 12408, 12420, 12432, 12444, 12456,
+ 12468, 12480, 12492, 12504, 12516, 12528, 12540, 12552, 12564, 12576, 12588, 12600, 12612, 12624,
+ 12637, 12650, 12663, 12676, 12690, 12704, 12718, 12732, 12744, 12756, 12772, 12788, 12804, 12820,
+ 12836, 12852, 12868, 12884, 12900, 12916, 12932, 12948, 12959, 12970, 12981, 12998, 13006, 13016,
+ 13024, 13032, 13040, 13050, 13058, 13066, 13074, 13082, 13094, 13102, 13110, 13118, 13128, 13136,
+ 13144, 13152, 13160, 13170, 13178, 13186, 13194, 13202, 13210, 13218, 13230, 13240, 13250, 13260,
+ 13269, 13277, 13285, 13295, 13303, 13311, 13321, 13330, 13338, 13346, 13354, 13362, 13372, 13385,
+ 13393, 13401, 13413, 13421, 13429, 13437, 13450, 13462, 13474, 13482, 13489, 13496, 13509, 13517,
+ 13524, 13531, 13538, 13551, 13558, 13571, 13582, 13591, 13600, 13609, 13618, 13627, 13636, 13646,
+ 13656, 13668, 13680, 13691, 13702, 13711, 13720, 13729, 13738, 13751, 13760, 13773, 13783, 13792,
+ 13801, 13810, 13819, 13829, 13838, 13847, 13856, 13865, 13876, 13887, 13898, 13909, 13922, 13932,
+ 13946, 13958, 13967, 13980, 13990, 14004, 14014, 14028, 14037, 14049, 14061, 14073, 14086, 14098,
+ 14107, 14113, 14119, 14127, 14135, 14143, 14155, 14167, 14178, 14189, 14200, 14211, 14222, 14233,
+ 14241, 14249, 14257, 14263, 14274, 14286, 14297, 14309, 14321, 14332, 14344, 14355, 14367, 14379,
+ 14390, 14402, 14414, 14425, 14434, 14447, 14456, 14469, 14478, 14487, 14500, 14509, 14522, 14531,
+ 14544, 14557, 14573, 14589, 14602, 14615, 14626, 14638, 14649, 14661, 14678, 14695, 14707, 14718,
+ 14730, 14741, 14753, 14767, 14779, 14790, 14803, 14815, 14829, 14841, 14852, 14865, 14876, 14887,
+ 14898, 14909, 14920, 14931, 14942, 14953, 14964, 14975, 14986, 14993, 15000, 15007, 15014, 15021,
+ 15028, 15034, 15040, 15048, 15056, 15064, 15072, 15080, 15092, 15100, 15112, 15120, 15132, 15140,
+ 15152, 15161, 15170, 15180, 15190, 15201, 15211, 15220, 15230, 15239, 15249, 15261, 15270, 15282,
+ 15294, 15307, 15320, 15333, 15346, 15359, 15372, 15382, 15388, 15395, 15402, 15409, 15416, 15423,
+ 15430, 15436, 15442, 15447, 15453, 15459, 15466, 15473, 15480, 15487, 15494, 15501, 15507, 15513,
+ 15521, 15528, 15536, 15543, 15550, 15558, 15565, 15572, 15583, 15591, 15598, 15606, 15613, 15620,
+ 15628, 15635, 15642, 15653, 15661, 15670, 15678, 15685, 15694, 15702, 15709, 15716, 15727, 15733,
+ 15739, 15745, 15751, 15757, 15763, 15773, 15780, 15787, 15794, 15801, 15809, 15817, 15825, 15833,
+ 15840, 15847, 15853, 15859, 15865, 15876, 15886, 15897, 15907, 15918, 15928, 15939, 15949, 15960,
+ 15970, 15981, 15991, 16002, 16013, 16024, 16035, 16046, 16057, 16068, 16079, 16087, 16095, 16103,
+ 16111, 16119, 16127, 16136, 16145, 16154, 16163, 16173, 16183, 16193, 16203, 16211, 16219, 16232,
+ 16245, 16257, 16269, 16277, 16285, 16292, 16299, 16307, 16315, 16323, 16331, 16343, 16355, 16366,
+ 16377, 16387, 16397, 16407, 16417, 16427, 16437, 16447, 16457, 16470, 16483, 16496, 16509, 16522,
+ 16535, 16548, 16561, 16574, 16587, 16599, 16611, 16627, 16643, 16658, 16673, 16683, 16693, 16703,
+ 16713, 16723, 16733, 16743, 16753, 16766, 16779, 16792, 16805, 16818, 16831, 16844, 16857, 16870,
+ 16883, 16895, 16907, 16923, 16939, 16954, 16969, 16978, 16987, 16996, 17005, 17014, 17023, 17032,
+ 17041, 17053, 17064, 17076, 17087, 17100, 17112, 17125, 17137, 17149, 17160, 17172, 17183, 17199,
+ 17215, 17227, 17238, 17250, 17261, 17274, 17286, 17299, 17311, 17323, 17334, 17346, 17357, 17366,
+ 17375, 17384, 17393, 17402, 17411, 17421, 17431, 17446, 17460, 17475, 17489, 17499, 17509, 17518,
+ 17527, 17536, 17545, 17554, 17563, 17572, 17581, 17590, 17599, 17608, 17617, 17626, 17635, 17644,
+ 17653, 17662, 17671, 17680, 17689, 17698, 17707, 17716, 17725, 17736, 17747, 17758, 17769, 17780,
+ 17791, 17802, 17813, 17824, 17835, 17846, 17857, 17868, 17879, 17890, 17901, 17912, 17923, 17934,
+ 17945, 17956, 17967, 17978, 17989, 18000, 18009, 18018, 18032, 18045, 18059, 18072, 18082, 18092,
+ 18101, 18110, 18119, 18132, 18141, 18154, 18163, 18172, 18182, 18192, 18199, 18208, 18217, 18224,
+ 18233, 18242, 18249, 18258, 18267, 18278, 18289, 18300, 18311, 18322, 18333, 18338, 18344, 18350,
+ 18358, 18366, 18374, 18382, 18390, 18398, 18404, 18410, 18422, 18433, 18444, 18455, 18464, 18473,
+ 18485, 18496, 18508, 18519, 18528, 18537, 18547, 18557, 18567, 18577, 18589, 18600, 18612, 18623,
+ 18635, 18646, 18658, 18669, 18681, 18692, 18704, 18715, 18724, 18732, 18740, 18748, 18756, 18764,
+ 18772, 18780, 18788, 18796, 18804, 18812, 18820, 18828, 18836, 18844, 18853, 18861, 18869, 18877,
+ 18885, 18893, 18901, 18909, 18917, 18925, 18933, 18941, 18949, 18957, 18965, 18973, 18982, 18991,
+ 19000, 19009, 19019, 19029, 19039, 19049, 19057, 19065, 19073, 19081, 19093, 19105, 19117, 19129,
+ 19142, 19155, 19167, 19179, 19191, 19203, 19215, 19227, 19240, 19253, 19265, 19277, 19285, 19295,
+ 19305, 19315, 19325, 19334, 19342, 19352, 19362, 19372, 19382, 19391, 19399, 19409, 19419, 19425,
+ 19432, 19441, 19450, 19459, 19468, 19477, 19486, 19495, 19502, 19509, 19517, 19526, 19534, 19542,
+ 19551, 19559, 19567, 19576, 19584, 19592, 19601, 19609, 19617, 19626, 19634, 19642, 19651, 19659,
+ 19666, 19674, 19681, 19688, 19696, 19703, 19710, 19721, 19728, 19739, 19746, 19757, 19764, 19775,
+ 19783, 19792, 19800, 19808, 19817, 19825, 19833, 19842, 19850, 19858, 19867, 19875, 19883, 19892,
+ 19900, 19908, 19917, 19925, 19932, 19940, 19947, 19954, 19962, 19969, 19975, 19981, 19987, 19994,
+ 20007, 20017, 20027, 20037, 20047, 20058, 20068, 20078, 20088, 20098, 20102, 20107, 20115, 20124,
+ 20132, 20140, 20149, 20157, 20165, 20174, 20182, 20190, 20199, 20207, 20215, 20224, 20232, 20240,
+ 20249, 20257, 20264, 20272, 20279, 20286, 20294, 20301, 20309, 20318, 20326, 20334, 20343, 20351,
+ 20359, 20368, 20376, 20384, 20393, 20401, 20409, 20418, 20426, 20434, 20443, 20451, 20458, 20466,
+ 20473, 20480, 20488, 20495, 20508, 20521, 20534, 20547, 20560, 20573, 20586, 20599, 20603, 20612,
+ 20625, 20634, 20647, 20656, 20669, 20678, 20691, 20696, 20704, 20713, 20721, 20729, 20738, 20746,
+ 20754, 20763, 20771, 20779, 20788, 20796, 20804, 20813, 20821, 20829, 20838, 20846, 20853, 20861,
+ 20868, 20875, 20883, 20890, 20899, 20907, 20916, 20924, 20932, 20941, 20949, 20957, 20969, 20978,
+ 20986, 20995, 21003, 21011, 21020, 21028, 21036, 21048, 21057, 21067, 21076, 21084, 21094, 21103,
+ 21111, 21119, 21131, 21138, 21145, 21152, 21159, 21166, 21173, 21184, 21191, 21198, 21205, 21211,
+ 21218, 21225, 21231, 21237, 21244, 21251, 21261, 21271, 21281, 21290, 21296, 21302, 21308, 21314,
+ 21321, 21328, 21334, 21340, 21347, 21354, 21360, 21366, 21373, 21380, 21387, 21394, 21401, 21408,
+ 21415, 21422, 21428, 21434, 21440, 21446, 21452, 21458, 21465, 21471, 21479, 21488, 21496, 21504,
+ 21513, 21521, 21529, 21538, 21546, 21554, 21563, 21571, 21579, 21588, 21596, 21604, 21613, 21621,
+ 21628, 21636, 21643, 21650, 21658, 21665, 21676, 21687, 21698, 21709, 21720, 21731, 21742, 21753,
+ 21764, 21775, 21786, 21797, 21805, 21814, 21822, 21830, 21839, 21847, 21855, 21864, 21872, 21880,
+ 21889, 21897, 21905, 21914, 21922, 21930, 21939, 21947, 21954, 21962, 21969, 21976, 21984, 21991,
+ 22002, 22013, 22024, 22035, 22046, 22057, 22068, 22079, 22090, 22101, 22112, 22123, 22133, 22143,
+ 22153, 22163, 22169, 22175, 22184, 22193, 22202, 22210, 22218, 22226, 22234, 22242, 22250, 22258,
+ 22266, 22274, 22286, 22294, 22306, 22314, 22326, 22334, 22346, 22354, 22366, 22374, 22386, 22394,
+ 22406, 22414, 22426, 22433, 22443, 22453, 22463, 22473, 22477, 22481, 22485, 22493, 22499, 22505,
+ 22511, 22516, 22521, 22529, 22537, 22546, 22555, 22564, 22572, 22581, 22590, 22601, 22612, 22623,
+ 22633, 22643, 22655, 22665, 22677, 22689, 22696, 22705, 22713, 22722, 22730, 22738, 22747, 22755,
+ 22763, 22775, 22784, 22792, 22801, 22809, 22817, 22826, 22834, 22842, 22854, 22863, 22873, 22882,
+ 22890, 22900, 22909, 22917, 22925, 22937, 22944, 22951, 22958, 22965, 22972, 22979, 22990, 22998,
+ 23006, 23014, 23022, 23032, 23042, 23053, 23064, 23076, 23087, 23098, 23109, 23122, 23135, 23148,
+ 23162, 23176, 23190, 23204, 23218, 23232, 23243, 23251, 23263, 23271, 23283, 23291, 23303, 23311,
+ 23323, 23332, 23341, 23351, 23361, 23372, 23382, 23391, 23401, 23410, 23420, 23432, 23441, 23453,
+ 23465, 23478, 23491, 23504, 23517, 23530, 23543, 23553, 23560, 23568, 23577, 23585, 23595, 23602,
+ 23611, 23620, 23629, 23640, 23651, 23664, 23675, 23688, 23698, 23707, 23716, 23725, 23734, 23744,
+ 23753, 23762, 23771, 23780, 23790, 23801, 23812, 23821, 23830, 23838, 23846, 23854, 23862, 23870,
+ 23881, 23892, 23897, 23903, 23912, 23921, 23930, 23940, 23950, 23960, 23970, 23980, 23989, 23999,
+ 24008, 24020, 24032, 24044, 24055, 24066, 24077, 24085, 24096, 24107, 24118, 24129, 24140, 24151,
+ 24162, 24173, 24195, 24201, 24207, 24213, 24219, 24226, 24235, 24244, 24253, 24262, 24273, 24284,
+ 24295, 24306, 24315, 24327, 24339, 24351, 24363, 24370, 24376, 24383, 24396, 24401, 24408, 24419,
+ 24436, 24447, 24453, 24462, 24471, 24480, 24489, 24498, 24507, 24515, 24523, 24532, 24541, 24550,
+ 24559, 24568, 24577, 24586, 24595, 24604, 24612, 24620, 24626, 24631, 24640, 24648, 24657, 24665,
+ 24673, 24682, 24690, 24698, 24710, 24719, 24727, 24736, 24744, 24752, 24761, 24769, 24777, 24789,
+ 24798, 24808, 24817, 24825, 24835, 24844, 24852, 24860, 24872, 24879, 24886, 24893, 24900, 24907,
+ 24914, 24925, 24933, 24941, 24949, 0
};
const char *Strs =
@@ -3747,267 +3748,268 @@ const char *X86IntelInstPrinter::getInstructionName(unsigned Opcode) {
"64\000LXADD8\000MASKMOVDQU\000MASKMOVDQU64\000MAXPDrm\000MAXPDrm_Int\000"
"MAXPDrr\000MAXPDrr_Int\000MAXPSrm\000MAXPSrm_Int\000MAXPSrr\000MAXPSrr_"
"Int\000MAXSDrm\000MAXSDrm_Int\000MAXSDrr\000MAXSDrr_Int\000MAXSSrm\000M"
- "AXSSrm_Int\000MAXSSrr\000MAXSSrr_Int\000MFENCE\000MINPDrm\000MINPDrm_In"
- "t\000MINPDrr\000MINPDrr_Int\000MINPSrm\000MINPSrm_Int\000MINPSrr\000MIN"
- "PSrr_Int\000MINSDrm\000MINSDrm_Int\000MINSDrr\000MINSDrr_Int\000MINSSrm"
- "\000MINSSrm_Int\000MINSSrr\000MINSSrr_Int\000MMX_CVTPD2PIrm\000MMX_CVTP"
- "D2PIrr\000MMX_CVTPI2PDrm\000MMX_CVTPI2PDrr\000MMX_CVTPI2PSrm\000MMX_CVT"
- "PI2PSrr\000MMX_CVTPS2PIrm\000MMX_CVTPS2PIrr\000MMX_CVTTPD2PIrm\000MMX_C"
- "VTTPD2PIrr\000MMX_CVTTPS2PIrm\000MMX_CVTTPS2PIrr\000MMX_EMMS\000MMX_FEM"
- "MS\000MMX_MASKMOVQ\000MMX_MASKMOVQ64\000MMX_MOVD64from64rr\000MMX_MOVD6"
- "4grr\000MMX_MOVD64mr\000MMX_MOVD64rm\000MMX_MOVD64rr\000MMX_MOVD64rrv16"
- "4\000MMX_MOVD64to64rr\000MMX_MOVDQ2Qrr\000MMX_MOVNTQmr\000MMX_MOVQ2DQrr"
- "\000MMX_MOVQ2FR64rr\000MMX_MOVQ64gmr\000MMX_MOVQ64mr\000MMX_MOVQ64rm\000"
- "MMX_MOVQ64rr\000MMX_MOVZDI2PDIrm\000MMX_MOVZDI2PDIrr\000MMX_PACKSSDWrm\000"
- "MMX_PACKSSDWrr\000MMX_PACKSSWBrm\000MMX_PACKSSWBrr\000MMX_PACKUSWBrm\000"
- "MMX_PACKUSWBrr\000MMX_PADDBrm\000MMX_PADDBrr\000MMX_PADDDrm\000MMX_PADD"
- "Drr\000MMX_PADDQrm\000MMX_PADDQrr\000MMX_PADDSBrm\000MMX_PADDSBrr\000MM"
- "X_PADDSWrm\000MMX_PADDSWrr\000MMX_PADDUSBrm\000MMX_PADDUSBrr\000MMX_PAD"
- "DUSWrm\000MMX_PADDUSWrr\000MMX_PADDWrm\000MMX_PADDWrr\000MMX_PANDNrm\000"
- "MMX_PANDNrr\000MMX_PANDrm\000MMX_PANDrr\000MMX_PAVGBrm\000MMX_PAVGBrr\000"
- "MMX_PAVGWrm\000MMX_PAVGWrr\000MMX_PCMPEQBrm\000MMX_PCMPEQBrr\000MMX_PCM"
- "PEQDrm\000MMX_PCMPEQDrr\000MMX_PCMPEQWrm\000MMX_PCMPEQWrr\000MMX_PCMPGT"
- "Brm\000MMX_PCMPGTBrr\000MMX_PCMPGTDrm\000MMX_PCMPGTDrr\000MMX_PCMPGTWrm"
- "\000MMX_PCMPGTWrr\000MMX_PEXTRWri\000MMX_PINSRWrmi\000MMX_PINSRWrri\000"
- "MMX_PMADDWDrm\000MMX_PMADDWDrr\000MMX_PMAXSWrm\000MMX_PMAXSWrr\000MMX_P"
- "MAXUBrm\000MMX_PMAXUBrr\000MMX_PMINSWrm\000MMX_PMINSWrr\000MMX_PMINUBrm"
- "\000MMX_PMINUBrr\000MMX_PMOVMSKBrr\000MMX_PMULHUWrm\000MMX_PMULHUWrr\000"
- "MMX_PMULHWrm\000MMX_PMULHWrr\000MMX_PMULLWrm\000MMX_PMULLWrr\000MMX_PMU"
- "LUDQrm\000MMX_PMULUDQrr\000MMX_PORrm\000MMX_PORrr\000MMX_PSADBWrm\000MM"
- "X_PSADBWrr\000MMX_PSHUFWmi\000MMX_PSHUFWri\000MMX_PSLLDri\000MMX_PSLLDr"
- "m\000MMX_PSLLDrr\000MMX_PSLLQri\000MMX_PSLLQrm\000MMX_PSLLQrr\000MMX_PS"
- "LLWri\000MMX_PSLLWrm\000MMX_PSLLWrr\000MMX_PSRADri\000MMX_PSRADrm\000MM"
- "X_PSRADrr\000MMX_PSRAWri\000MMX_PSRAWrm\000MMX_PSRAWrr\000MMX_PSRLDri\000"
- "MMX_PSRLDrm\000MMX_PSRLDrr\000MMX_PSRLQri\000MMX_PSRLQrm\000MMX_PSRLQrr"
- "\000MMX_PSRLWri\000MMX_PSRLWrm\000MMX_PSRLWrr\000MMX_PSUBBrm\000MMX_PSU"
- "BBrr\000MMX_PSUBDrm\000MMX_PSUBDrr\000MMX_PSUBQrm\000MMX_PSUBQrr\000MMX"
- "_PSUBSBrm\000MMX_PSUBSBrr\000MMX_PSUBSWrm\000MMX_PSUBSWrr\000MMX_PSUBUS"
- "Brm\000MMX_PSUBUSBrr\000MMX_PSUBUSWrm\000MMX_PSUBUSWrr\000MMX_PSUBWrm\000"
- "MMX_PSUBWrr\000MMX_PUNPCKHBWrm\000MMX_PUNPCKHBWrr\000MMX_PUNPCKHDQrm\000"
- "MMX_PUNPCKHDQrr\000MMX_PUNPCKHWDrm\000MMX_PUNPCKHWDrr\000MMX_PUNPCKLBWr"
- "m\000MMX_PUNPCKLBWrr\000MMX_PUNPCKLDQrm\000MMX_PUNPCKLDQrr\000MMX_PUNPC"
- "KLWDrm\000MMX_PUNPCKLWDrr\000MMX_PXORrm\000MMX_PXORrr\000MMX_V_SET0\000"
- "MMX_V_SETALLONES\000MONITOR\000MOV16ao16\000MOV16mi\000MOV16mr\000MOV16"
- "ms\000MOV16o16a\000MOV16r0\000MOV16ri\000MOV16rm\000MOV16rr\000MOV16rr_"
- "REV\000MOV16rs\000MOV16sm\000MOV16sr\000MOV32ao32\000MOV32cr\000MOV32dr"
- "\000MOV32mi\000MOV32mr\000MOV32o32a\000MOV32r0\000MOV32rc\000MOV32rd\000"
- "MOV32ri\000MOV32rm\000MOV32rr\000MOV32rr_REV\000MOV64FSrm\000MOV64GSrm\000"
- "MOV64ao64\000MOV64ao8\000MOV64cr\000MOV64dr\000MOV64mi32\000MOV64mr\000"
- "MOV64ms\000MOV64o64a\000MOV64o8a\000MOV64r0\000MOV64rc\000MOV64rd\000MO"
- "V64ri\000MOV64ri32\000MOV64ri64i32\000MOV64rm\000MOV64rr\000MOV64rr_REV"
- "\000MOV64rs\000MOV64sm\000MOV64sr\000MOV64toPQIrr\000MOV64toSDrm\000MOV"
- "64toSDrr\000MOV8ao8\000MOV8mi\000MOV8mr\000MOV8mr_NOREX\000MOV8o8a\000M"
- "OV8r0\000MOV8ri\000MOV8rm\000MOV8rm_NOREX\000MOV8rr\000MOV8rr_NOREX\000"
- "MOV8rr_REV\000MOVAPDmr\000MOVAPDrm\000MOVAPDrr\000MOVAPSmr\000MOVAPSrm\000"
- "MOVAPSrr\000MOVDDUPrm\000MOVDDUPrr\000MOVDI2PDIrm\000MOVDI2PDIrr\000MOV"
- "DI2SSrm\000MOVDI2SSrr\000MOVDQAmr\000MOVDQArm\000MOVDQArr\000MOVDQUmr\000"
- "MOVDQUmr_Int\000MOVDQUrm\000MOVDQUrm_Int\000MOVHLPSrr\000MOVHPDmr\000MO"
- "VHPDrm\000MOVHPSmr\000MOVHPSrm\000MOVLHPSrr\000MOVLPDmr\000MOVLPDrm\000"
- "MOVLPSmr\000MOVLPSrm\000MOVLQ128mr\000MOVMSKPDrr\000MOVMSKPSrr\000MOVNT"
- "DQArm\000MOVNTDQ_64mr\000MOVNTDQmr\000MOVNTDQmr_Int\000MOVNTI_64mr\000M"
- "OVNTImr\000MOVNTImr_Int\000MOVNTPDmr\000MOVNTPDmr_Int\000MOVNTPSmr\000M"
- "OVNTPSmr_Int\000MOVPC32r\000MOVPDI2DImr\000MOVPDI2DIrr\000MOVPQI2QImr\000"
- "MOVPQIto64rr\000MOVQI2PQIrm\000MOVQxrxr\000MOVSB\000MOVSD\000MOVSDmr\000"
- "MOVSDrm\000MOVSDrr\000MOVSDto64mr\000MOVSDto64rr\000MOVSHDUPrm\000MOVSH"
- "DUPrr\000MOVSLDUPrm\000MOVSLDUPrr\000MOVSS2DImr\000MOVSS2DIrr\000MOVSSm"
- "r\000MOVSSrm\000MOVSSrr\000MOVSW\000MOVSX16rm8\000MOVSX16rm8W\000MOVSX1"
- "6rr8\000MOVSX16rr8W\000MOVSX32rm16\000MOVSX32rm8\000MOVSX32rr16\000MOVS"
- "X32rr8\000MOVSX64rm16\000MOVSX64rm32\000MOVSX64rm8\000MOVSX64rr16\000MO"
- "VSX64rr32\000MOVSX64rr8\000MOVUPDmr\000MOVUPDmr_Int\000MOVUPDrm\000MOVU"
- "PDrm_Int\000MOVUPDrr\000MOVUPSmr\000MOVUPSmr_Int\000MOVUPSrm\000MOVUPSr"
- "m_Int\000MOVUPSrr\000MOVZDI2PDIrm\000MOVZDI2PDIrr\000MOVZPQILo2PQIrm\000"
- "MOVZPQILo2PQIrr\000MOVZQI2PQIrm\000MOVZQI2PQIrr\000MOVZX16rm8\000MOVZX1"
- "6rm8W\000MOVZX16rr8\000MOVZX16rr8W\000MOVZX32_NOREXrm8\000MOVZX32_NOREX"
- "rr8\000MOVZX32rm16\000MOVZX32rm8\000MOVZX32rr16\000MOVZX32rr8\000MOVZX6"
- "4rm16\000MOVZX64rm16_Q\000MOVZX64rm32\000MOVZX64rm8\000MOVZX64rm8_Q\000"
- "MOVZX64rr16\000MOVZX64rr16_Q\000MOVZX64rr32\000MOVZX64rr8\000MOVZX64rr8"
- "_Q\000MOV_Fp3232\000MOV_Fp3264\000MOV_Fp3280\000MOV_Fp6432\000MOV_Fp646"
- "4\000MOV_Fp6480\000MOV_Fp8032\000MOV_Fp8064\000MOV_Fp8080\000MPSADBWrmi"
- "\000MPSADBWrri\000MUL16m\000MUL16r\000MUL32m\000MUL32r\000MUL64m\000MUL"
- "64r\000MUL8m\000MUL8r\000MULPDrm\000MULPDrr\000MULPSrm\000MULPSrr\000MU"
- "LSDrm\000MULSDrm_Int\000MULSDrr\000MULSDrr_Int\000MULSSrm\000MULSSrm_In"
- "t\000MULSSrr\000MULSSrr_Int\000MUL_F32m\000MUL_F64m\000MUL_FI16m\000MUL"
- "_FI32m\000MUL_FPrST0\000MUL_FST0r\000MUL_Fp32\000MUL_Fp32m\000MUL_Fp64\000"
- "MUL_Fp64m\000MUL_Fp64m32\000MUL_Fp80\000MUL_Fp80m32\000MUL_Fp80m64\000M"
- "UL_FpI16m32\000MUL_FpI16m64\000MUL_FpI16m80\000MUL_FpI32m32\000MUL_FpI3"
- "2m64\000MUL_FpI32m80\000MUL_FrST0\000MWAIT\000NEG16m\000NEG16r\000NEG32"
- "m\000NEG32r\000NEG64m\000NEG64r\000NEG8m\000NEG8r\000NOOP\000NOOPL\000N"
- "OOPW\000NOT16m\000NOT16r\000NOT32m\000NOT32r\000NOT64m\000NOT64r\000NOT"
- "8m\000NOT8r\000OR16i16\000OR16mi\000OR16mi8\000OR16mr\000OR16ri\000OR16"
- "ri8\000OR16rm\000OR16rr\000OR16rr_REV\000OR32i32\000OR32mi\000OR32mi8\000"
- "OR32mr\000OR32ri\000OR32ri8\000OR32rm\000OR32rr\000OR32rr_REV\000OR64i3"
- "2\000OR64mi32\000OR64mi8\000OR64mr\000OR64ri32\000OR64ri8\000OR64rm\000"
- "OR64rr\000OR64rr_REV\000OR8i8\000OR8mi\000OR8mr\000OR8ri\000OR8rm\000OR"
- "8rr\000OR8rr_REV\000ORPDrm\000ORPDrr\000ORPSrm\000ORPSrr\000OUT16ir\000"
- "OUT16rr\000OUT32ir\000OUT32rr\000OUT8ir\000OUT8rr\000OUTSB\000OUTSD\000"
- "OUTSW\000PABSBrm128\000PABSBrm64\000PABSBrr128\000PABSBrr64\000PABSDrm1"
- "28\000PABSDrm64\000PABSDrr128\000PABSDrr64\000PABSWrm128\000PABSWrm64\000"
- "PABSWrr128\000PABSWrr64\000PACKSSDWrm\000PACKSSDWrr\000PACKSSWBrm\000PA"
- "CKSSWBrr\000PACKUSDWrm\000PACKUSDWrr\000PACKUSWBrm\000PACKUSWBrr\000PAD"
- "DBrm\000PADDBrr\000PADDDrm\000PADDDrr\000PADDQrm\000PADDQrr\000PADDSBrm"
- "\000PADDSBrr\000PADDSWrm\000PADDSWrr\000PADDUSBrm\000PADDUSBrr\000PADDU"
- "SWrm\000PADDUSWrr\000PADDWrm\000PADDWrr\000PALIGNR128rm\000PALIGNR128rr"
- "\000PALIGNR64rm\000PALIGNR64rr\000PANDNrm\000PANDNrr\000PANDrm\000PANDr"
- "r\000PAVGBrm\000PAVGBrr\000PAVGWrm\000PAVGWrr\000PBLENDVBrm0\000PBLENDV"
- "Brr0\000PBLENDWrmi\000PBLENDWrri\000PCMPEQBrm\000PCMPEQBrr\000PCMPEQDrm"
- "\000PCMPEQDrr\000PCMPEQQrm\000PCMPEQQrr\000PCMPEQWrm\000PCMPEQWrr\000PC"
- "MPESTRIArm\000PCMPESTRIArr\000PCMPESTRICrm\000PCMPESTRICrr\000PCMPESTRI"
- "Orm\000PCMPESTRIOrr\000PCMPESTRISrm\000PCMPESTRISrr\000PCMPESTRIZrm\000"
- "PCMPESTRIZrr\000PCMPESTRIrm\000PCMPESTRIrr\000PCMPESTRM128MEM\000PCMPES"
- "TRM128REG\000PCMPESTRM128rm\000PCMPESTRM128rr\000PCMPGTBrm\000PCMPGTBrr"
- "\000PCMPGTDrm\000PCMPGTDrr\000PCMPGTQrm\000PCMPGTQrr\000PCMPGTWrm\000PC"
- "MPGTWrr\000PCMPISTRIArm\000PCMPISTRIArr\000PCMPISTRICrm\000PCMPISTRICrr"
- "\000PCMPISTRIOrm\000PCMPISTRIOrr\000PCMPISTRISrm\000PCMPISTRISrr\000PCM"
- "PISTRIZrm\000PCMPISTRIZrr\000PCMPISTRIrm\000PCMPISTRIrr\000PCMPISTRM128"
- "MEM\000PCMPISTRM128REG\000PCMPISTRM128rm\000PCMPISTRM128rr\000PEXTRBmr\000"
- "PEXTRBrr\000PEXTRDmr\000PEXTRDrr\000PEXTRQmr\000PEXTRQrr\000PEXTRWmr\000"
- "PEXTRWri\000PHADDDrm128\000PHADDDrm64\000PHADDDrr128\000PHADDDrr64\000P"
- "HADDSWrm128\000PHADDSWrm64\000PHADDSWrr128\000PHADDSWrr64\000PHADDWrm12"
- "8\000PHADDWrm64\000PHADDWrr128\000PHADDWrr64\000PHMINPOSUWrm128\000PHMI"
- "NPOSUWrr128\000PHSUBDrm128\000PHSUBDrm64\000PHSUBDrr128\000PHSUBDrr64\000"
- "PHSUBSWrm128\000PHSUBSWrm64\000PHSUBSWrr128\000PHSUBSWrr64\000PHSUBWrm1"
- "28\000PHSUBWrm64\000PHSUBWrr128\000PHSUBWrr64\000PINSRBrm\000PINSRBrr\000"
- "PINSRDrm\000PINSRDrr\000PINSRQrm\000PINSRQrr\000PINSRWrmi\000PINSRWrri\000"
- "PMADDUBSWrm128\000PMADDUBSWrm64\000PMADDUBSWrr128\000PMADDUBSWrr64\000P"
- "MADDWDrm\000PMADDWDrr\000PMAXSBrm\000PMAXSBrr\000PMAXSDrm\000PMAXSDrr\000"
- "PMAXSWrm\000PMAXSWrr\000PMAXUBrm\000PMAXUBrr\000PMAXUDrm\000PMAXUDrr\000"
- "PMAXUWrm\000PMAXUWrr\000PMINSBrm\000PMINSBrr\000PMINSDrm\000PMINSDrr\000"
- "PMINSWrm\000PMINSWrr\000PMINUBrm\000PMINUBrr\000PMINUDrm\000PMINUDrr\000"
- "PMINUWrm\000PMINUWrr\000PMOVMSKBrr\000PMOVSXBDrm\000PMOVSXBDrr\000PMOVS"
- "XBQrm\000PMOVSXBQrr\000PMOVSXBWrm\000PMOVSXBWrr\000PMOVSXDQrm\000PMOVSX"
- "DQrr\000PMOVSXWDrm\000PMOVSXWDrr\000PMOVSXWQrm\000PMOVSXWQrr\000PMOVZXB"
- "Drm\000PMOVZXBDrr\000PMOVZXBQrm\000PMOVZXBQrr\000PMOVZXBWrm\000PMOVZXBW"
- "rr\000PMOVZXDQrm\000PMOVZXDQrr\000PMOVZXWDrm\000PMOVZXWDrr\000PMOVZXWQr"
- "m\000PMOVZXWQrr\000PMULDQrm\000PMULDQrr\000PMULHRSWrm128\000PMULHRSWrm6"
- "4\000PMULHRSWrr128\000PMULHRSWrr64\000PMULHUWrm\000PMULHUWrr\000PMULHWr"
- "m\000PMULHWrr\000PMULLDrm\000PMULLDrm_int\000PMULLDrr\000PMULLDrr_int\000"
- "PMULLWrm\000PMULLWrr\000PMULUDQrm\000PMULUDQrr\000POP16r\000POP16rmm\000"
- "POP16rmr\000POP32r\000POP32rmm\000POP32rmr\000POP64r\000POP64rmm\000POP"
- "64rmr\000POPCNT16rm\000POPCNT16rr\000POPCNT32rm\000POPCNT32rr\000POPCNT"
- "64rm\000POPCNT64rr\000POPF\000POPFD\000POPFQ\000POPFS16\000POPFS32\000P"
- "OPFS64\000POPGS16\000POPGS32\000POPGS64\000PORrm\000PORrr\000PREFETCHNT"
- "A\000PREFETCHT0\000PREFETCHT1\000PREFETCHT2\000PSADBWrm\000PSADBWrr\000"
- "PSHUFBrm128\000PSHUFBrm64\000PSHUFBrr128\000PSHUFBrr64\000PSHUFDmi\000P"
- "SHUFDri\000PSHUFHWmi\000PSHUFHWri\000PSHUFLWmi\000PSHUFLWri\000PSIGNBrm"
- "128\000PSIGNBrm64\000PSIGNBrr128\000PSIGNBrr64\000PSIGNDrm128\000PSIGND"
- "rm64\000PSIGNDrr128\000PSIGNDrr64\000PSIGNWrm128\000PSIGNWrm64\000PSIGN"
- "Wrr128\000PSIGNWrr64\000PSLLDQri\000PSLLDri\000PSLLDrm\000PSLLDrr\000PS"
- "LLQri\000PSLLQrm\000PSLLQrr\000PSLLWri\000PSLLWrm\000PSLLWrr\000PSRADri"
- "\000PSRADrm\000PSRADrr\000PSRAWri\000PSRAWrm\000PSRAWrr\000PSRLDQri\000"
- "PSRLDri\000PSRLDrm\000PSRLDrr\000PSRLQri\000PSRLQrm\000PSRLQrr\000PSRLW"
- "ri\000PSRLWrm\000PSRLWrr\000PSUBBrm\000PSUBBrr\000PSUBDrm\000PSUBDrr\000"
- "PSUBQrm\000PSUBQrr\000PSUBSBrm\000PSUBSBrr\000PSUBSWrm\000PSUBSWrr\000P"
- "SUBUSBrm\000PSUBUSBrr\000PSUBUSWrm\000PSUBUSWrr\000PSUBWrm\000PSUBWrr\000"
- "PTESTrm\000PTESTrr\000PUNPCKHBWrm\000PUNPCKHBWrr\000PUNPCKHDQrm\000PUNP"
- "CKHDQrr\000PUNPCKHQDQrm\000PUNPCKHQDQrr\000PUNPCKHWDrm\000PUNPCKHWDrr\000"
- "PUNPCKLBWrm\000PUNPCKLBWrr\000PUNPCKLDQrm\000PUNPCKLDQrr\000PUNPCKLQDQr"
- "m\000PUNPCKLQDQrr\000PUNPCKLWDrm\000PUNPCKLWDrr\000PUSH16r\000PUSH16rmm"
- "\000PUSH16rmr\000PUSH32i16\000PUSH32i32\000PUSH32i8\000PUSH32r\000PUSH3"
- "2rmm\000PUSH32rmr\000PUSH64i16\000PUSH64i32\000PUSH64i8\000PUSH64r\000P"
- "USH64rmm\000PUSH64rmr\000PUSHF\000PUSHFD\000PUSHFQ64\000PUSHFS16\000PUS"
- "HFS32\000PUSHFS64\000PUSHGS16\000PUSHGS32\000PUSHGS64\000PXORrm\000PXOR"
- "rr\000RCL16m1\000RCL16mCL\000RCL16mi\000RCL16r1\000RCL16rCL\000RCL16ri\000"
- "RCL32m1\000RCL32mCL\000RCL32mi\000RCL32r1\000RCL32rCL\000RCL32ri\000RCL"
- "64m1\000RCL64mCL\000RCL64mi\000RCL64r1\000RCL64rCL\000RCL64ri\000RCL8m1"
- "\000RCL8mCL\000RCL8mi\000RCL8r1\000RCL8rCL\000RCL8ri\000RCPPSm\000RCPPS"
- "m_Int\000RCPPSr\000RCPPSr_Int\000RCPSSm\000RCPSSm_Int\000RCPSSr\000RCPS"
- "Sr_Int\000RCR16m1\000RCR16mCL\000RCR16mi\000RCR16r1\000RCR16rCL\000RCR1"
- "6ri\000RCR32m1\000RCR32mCL\000RCR32mi\000RCR32r1\000RCR32rCL\000RCR32ri"
- "\000RCR64m1\000RCR64mCL\000RCR64mi\000RCR64r1\000RCR64rCL\000RCR64ri\000"
- "RCR8m1\000RCR8mCL\000RCR8mi\000RCR8r1\000RCR8rCL\000RCR8ri\000RDMSR\000"
- "RDPMC\000RDTSC\000RDTSCP\000REPNE_PREFIX\000REP_MOVSB\000REP_MOVSD\000R"
- "EP_MOVSQ\000REP_MOVSW\000REP_PREFIX\000REP_STOSB\000REP_STOSD\000REP_ST"
- "OSQ\000REP_STOSW\000RET\000RETI\000ROL16m1\000ROL16mCL\000ROL16mi\000RO"
- "L16r1\000ROL16rCL\000ROL16ri\000ROL32m1\000ROL32mCL\000ROL32mi\000ROL32"
- "r1\000ROL32rCL\000ROL32ri\000ROL64m1\000ROL64mCL\000ROL64mi\000ROL64r1\000"
- "ROL64rCL\000ROL64ri\000ROL8m1\000ROL8mCL\000ROL8mi\000ROL8r1\000ROL8rCL"
- "\000ROL8ri\000ROR16m1\000ROR16mCL\000ROR16mi\000ROR16r1\000ROR16rCL\000"
- "ROR16ri\000ROR32m1\000ROR32mCL\000ROR32mi\000ROR32r1\000ROR32rCL\000ROR"
- "32ri\000ROR64m1\000ROR64mCL\000ROR64mi\000ROR64r1\000ROR64rCL\000ROR64r"
- "i\000ROR8m1\000ROR8mCL\000ROR8mi\000ROR8r1\000ROR8rCL\000ROR8ri\000ROUN"
- "DPDm_Int\000ROUNDPDr_Int\000ROUNDPSm_Int\000ROUNDPSr_Int\000ROUNDSDm_In"
- "t\000ROUNDSDr_Int\000ROUNDSSm_Int\000ROUNDSSr_Int\000RSM\000RSQRTPSm\000"
- "RSQRTPSm_Int\000RSQRTPSr\000RSQRTPSr_Int\000RSQRTSSm\000RSQRTSSm_Int\000"
- "RSQRTSSr\000RSQRTSSr_Int\000SAHF\000SAR16m1\000SAR16mCL\000SAR16mi\000S"
- "AR16r1\000SAR16rCL\000SAR16ri\000SAR32m1\000SAR32mCL\000SAR32mi\000SAR3"
- "2r1\000SAR32rCL\000SAR32ri\000SAR64m1\000SAR64mCL\000SAR64mi\000SAR64r1"
- "\000SAR64rCL\000SAR64ri\000SAR8m1\000SAR8mCL\000SAR8mi\000SAR8r1\000SAR"
- "8rCL\000SAR8ri\000SBB16i16\000SBB16mi\000SBB16mi8\000SBB16mr\000SBB16ri"
- "\000SBB16ri8\000SBB16rm\000SBB16rr\000SBB16rr_REV\000SBB32i32\000SBB32m"
- "i\000SBB32mi8\000SBB32mr\000SBB32ri\000SBB32ri8\000SBB32rm\000SBB32rr\000"
- "SBB32rr_REV\000SBB64i32\000SBB64mi32\000SBB64mi8\000SBB64mr\000SBB64ri3"
- "2\000SBB64ri8\000SBB64rm\000SBB64rr\000SBB64rr_REV\000SBB8i8\000SBB8mi\000"
- "SBB8mr\000SBB8ri\000SBB8rm\000SBB8rr\000SBB8rr_REV\000SCAS16\000SCAS32\000"
- "SCAS64\000SCAS8\000SETAEm\000SETAEr\000SETAm\000SETAr\000SETBEm\000SETB"
- "Er\000SETB_C16r\000SETB_C32r\000SETB_C64r\000SETB_C8r\000SETBm\000SETBr"
- "\000SETEm\000SETEr\000SETGEm\000SETGEr\000SETGm\000SETGr\000SETLEm\000S"
- "ETLEr\000SETLm\000SETLr\000SETNEm\000SETNEr\000SETNOm\000SETNOr\000SETN"
- "Pm\000SETNPr\000SETNSm\000SETNSr\000SETOm\000SETOr\000SETPm\000SETPr\000"
- "SETSm\000SETSr\000SFENCE\000SGDTm\000SHL16m1\000SHL16mCL\000SHL16mi\000"
- "SHL16r1\000SHL16rCL\000SHL16ri\000SHL32m1\000SHL32mCL\000SHL32mi\000SHL"
- "32r1\000SHL32rCL\000SHL32ri\000SHL64m1\000SHL64mCL\000SHL64mi\000SHL64r"
- "1\000SHL64rCL\000SHL64ri\000SHL8m1\000SHL8mCL\000SHL8mi\000SHL8r1\000SH"
- "L8rCL\000SHL8ri\000SHLD16mrCL\000SHLD16mri8\000SHLD16rrCL\000SHLD16rri8"
- "\000SHLD32mrCL\000SHLD32mri8\000SHLD32rrCL\000SHLD32rri8\000SHLD64mrCL\000"
- "SHLD64mri8\000SHLD64rrCL\000SHLD64rri8\000SHR16m1\000SHR16mCL\000SHR16m"
- "i\000SHR16r1\000SHR16rCL\000SHR16ri\000SHR32m1\000SHR32mCL\000SHR32mi\000"
- "SHR32r1\000SHR32rCL\000SHR32ri\000SHR64m1\000SHR64mCL\000SHR64mi\000SHR"
- "64r1\000SHR64rCL\000SHR64ri\000SHR8m1\000SHR8mCL\000SHR8mi\000SHR8r1\000"
- "SHR8rCL\000SHR8ri\000SHRD16mrCL\000SHRD16mri8\000SHRD16rrCL\000SHRD16rr"
- "i8\000SHRD32mrCL\000SHRD32mri8\000SHRD32rrCL\000SHRD32rri8\000SHRD64mrC"
- "L\000SHRD64mri8\000SHRD64rrCL\000SHRD64rri8\000SHUFPDrmi\000SHUFPDrri\000"
- "SHUFPSrmi\000SHUFPSrri\000SIDTm\000SIN_F\000SIN_Fp32\000SIN_Fp64\000SIN"
- "_Fp80\000SLDT16m\000SLDT16r\000SLDT64m\000SLDT64r\000SMSW16m\000SMSW16r"
- "\000SMSW32r\000SMSW64r\000SQRTPDm\000SQRTPDm_Int\000SQRTPDr\000SQRTPDr_"
- "Int\000SQRTPSm\000SQRTPSm_Int\000SQRTPSr\000SQRTPSr_Int\000SQRTSDm\000S"
- "QRTSDm_Int\000SQRTSDr\000SQRTSDr_Int\000SQRTSSm\000SQRTSSm_Int\000SQRTS"
- "Sr\000SQRTSSr_Int\000SQRT_F\000SQRT_Fp32\000SQRT_Fp64\000SQRT_Fp80\000S"
- "S_PREFIX\000STC\000STD\000STI\000STMXCSR\000STOSB\000STOSD\000STOSW\000"
- "STRm\000STRr\000ST_F32m\000ST_F64m\000ST_FP32m\000ST_FP64m\000ST_FP80m\000"
- "ST_FPrr\000ST_Fp32m\000ST_Fp64m\000ST_Fp64m32\000ST_Fp80m32\000ST_Fp80m"
- "64\000ST_FpP32m\000ST_FpP64m\000ST_FpP64m32\000ST_FpP80m\000ST_FpP80m32"
- "\000ST_FpP80m64\000ST_Frr\000SUB16i16\000SUB16mi\000SUB16mi8\000SUB16mr"
- "\000SUB16ri\000SUB16ri8\000SUB16rm\000SUB16rr\000SUB16rr_REV\000SUB32i3"
- "2\000SUB32mi\000SUB32mi8\000SUB32mr\000SUB32ri\000SUB32ri8\000SUB32rm\000"
- "SUB32rr\000SUB32rr_REV\000SUB64i32\000SUB64mi32\000SUB64mi8\000SUB64mr\000"
- "SUB64ri32\000SUB64ri8\000SUB64rm\000SUB64rr\000SUB64rr_REV\000SUB8i8\000"
- "SUB8mi\000SUB8mr\000SUB8ri\000SUB8rm\000SUB8rr\000SUB8rr_REV\000SUBPDrm"
- "\000SUBPDrr\000SUBPSrm\000SUBPSrr\000SUBR_F32m\000SUBR_F64m\000SUBR_FI1"
- "6m\000SUBR_FI32m\000SUBR_FPrST0\000SUBR_FST0r\000SUBR_Fp32m\000SUBR_Fp6"
- "4m\000SUBR_Fp64m32\000SUBR_Fp80m32\000SUBR_Fp80m64\000SUBR_FpI16m32\000"
- "SUBR_FpI16m64\000SUBR_FpI16m80\000SUBR_FpI32m32\000SUBR_FpI32m64\000SUB"
- "R_FpI32m80\000SUBR_FrST0\000SUBSDrm\000SUBSDrm_Int\000SUBSDrr\000SUBSDr"
- "r_Int\000SUBSSrm\000SUBSSrm_Int\000SUBSSrr\000SUBSSrr_Int\000SUB_F32m\000"
- "SUB_F64m\000SUB_FI16m\000SUB_FI32m\000SUB_FPrST0\000SUB_FST0r\000SUB_Fp"
- "32\000SUB_Fp32m\000SUB_Fp64\000SUB_Fp64m\000SUB_Fp64m32\000SUB_Fp80\000"
- "SUB_Fp80m32\000SUB_Fp80m64\000SUB_FpI16m32\000SUB_FpI16m64\000SUB_FpI16"
- "m80\000SUB_FpI32m32\000SUB_FpI32m64\000SUB_FpI32m80\000SUB_FrST0\000SWA"
- "PGS\000SYSCALL\000SYSENTER\000SYSEXIT\000SYSEXIT64\000SYSRET\000TAILJMP"
- "d\000TAILJMPm\000TAILJMPr\000TAILJMPr64\000TCRETURNdi\000TCRETURNdi64\000"
- "TCRETURNri\000TCRETURNri64\000TEST16i16\000TEST16mi\000TEST16ri\000TEST"
- "16rm\000TEST16rr\000TEST32i32\000TEST32mi\000TEST32ri\000TEST32rm\000TE"
- "ST32rr\000TEST64i32\000TEST64mi32\000TEST64ri32\000TEST64rm\000TEST64rr"
- "\000TEST8i8\000TEST8mi\000TEST8ri\000TEST8rm\000TEST8rr\000TLS_addr32\000"
- "TLS_addr64\000TRAP\000TST_F\000TST_Fp32\000TST_Fp64\000TST_Fp80\000UCOM"
- "ISDrm\000UCOMISDrr\000UCOMISSrm\000UCOMISSrr\000UCOM_FIPr\000UCOM_FIr\000"
- "UCOM_FPPr\000UCOM_FPr\000UCOM_FpIr32\000UCOM_FpIr64\000UCOM_FpIr80\000U"
- "COM_Fpr32\000UCOM_Fpr64\000UCOM_Fpr80\000UCOM_Fr\000UNPCKHPDrm\000UNPCK"
- "HPDrr\000UNPCKHPSrm\000UNPCKHPSrr\000UNPCKLPDrm\000UNPCKLPDrr\000UNPCKL"
- "PSrm\000UNPCKLPSrr\000VASTART_SAVE_XMM_REGS\000VERRm\000VERRr\000VERWm\000"
- "VERWr\000VMCALL\000VMCLEARm\000VMLAUNCH\000VMPTRLDm\000VMPTRSTm\000VMRE"
- "AD32rm\000VMREAD32rr\000VMREAD64rm\000VMREAD64rr\000VMRESUME\000VMWRITE"
- "32rm\000VMWRITE32rr\000VMWRITE64rm\000VMWRITE64rr\000VMXOFF\000VMXON\000"
- "V_SET0\000V_SETALLONES\000WAIT\000WBINVD\000WINCALL64m\000WINCALL64pcre"
- "l32\000WINCALL64r\000WRMSR\000XADD16rm\000XADD16rr\000XADD32rm\000XADD3"
- "2rr\000XADD64rm\000XADD64rr\000XADD8rm\000XADD8rr\000XCHG16ar\000XCHG16"
- "rm\000XCHG16rr\000XCHG32ar\000XCHG32rm\000XCHG32rr\000XCHG64ar\000XCHG6"
- "4rm\000XCHG64rr\000XCHG8rm\000XCHG8rr\000XCH_F\000XLAT\000XOR16i16\000X"
- "OR16mi\000XOR16mi8\000XOR16mr\000XOR16ri\000XOR16ri8\000XOR16rm\000XOR1"
- "6rr\000XOR16rr_REV\000XOR32i32\000XOR32mi\000XOR32mi8\000XOR32mr\000XOR"
- "32ri\000XOR32ri8\000XOR32rm\000XOR32rr\000XOR32rr_REV\000XOR64i32\000XO"
- "R64mi32\000XOR64mi8\000XOR64mr\000XOR64ri32\000XOR64ri8\000XOR64rm\000X"
- "OR64rr\000XOR64rr_REV\000XOR8i8\000XOR8mi\000XOR8mr\000XOR8ri\000XOR8rm"
- "\000XOR8rr\000XOR8rr_REV\000XORPDrm\000XORPDrr\000XORPSrm\000XORPSrr\000";
+ "AXSSrm_Int\000MAXSSrr\000MAXSSrr_Int\000MFENCE\000MINGW_ALLOCA\000MINPD"
+ "rm\000MINPDrm_Int\000MINPDrr\000MINPDrr_Int\000MINPSrm\000MINPSrm_Int\000"
+ "MINPSrr\000MINPSrr_Int\000MINSDrm\000MINSDrm_Int\000MINSDrr\000MINSDrr_"
+ "Int\000MINSSrm\000MINSSrm_Int\000MINSSrr\000MINSSrr_Int\000MMX_CVTPD2PI"
+ "rm\000MMX_CVTPD2PIrr\000MMX_CVTPI2PDrm\000MMX_CVTPI2PDrr\000MMX_CVTPI2P"
+ "Srm\000MMX_CVTPI2PSrr\000MMX_CVTPS2PIrm\000MMX_CVTPS2PIrr\000MMX_CVTTPD"
+ "2PIrm\000MMX_CVTTPD2PIrr\000MMX_CVTTPS2PIrm\000MMX_CVTTPS2PIrr\000MMX_E"
+ "MMS\000MMX_FEMMS\000MMX_MASKMOVQ\000MMX_MASKMOVQ64\000MMX_MOVD64from64r"
+ "r\000MMX_MOVD64grr\000MMX_MOVD64mr\000MMX_MOVD64rm\000MMX_MOVD64rr\000M"
+ "MX_MOVD64rrv164\000MMX_MOVD64to64rr\000MMX_MOVDQ2Qrr\000MMX_MOVNTQmr\000"
+ "MMX_MOVQ2DQrr\000MMX_MOVQ2FR64rr\000MMX_MOVQ64gmr\000MMX_MOVQ64mr\000MM"
+ "X_MOVQ64rm\000MMX_MOVQ64rr\000MMX_MOVZDI2PDIrm\000MMX_MOVZDI2PDIrr\000M"
+ "MX_PACKSSDWrm\000MMX_PACKSSDWrr\000MMX_PACKSSWBrm\000MMX_PACKSSWBrr\000"
+ "MMX_PACKUSWBrm\000MMX_PACKUSWBrr\000MMX_PADDBrm\000MMX_PADDBrr\000MMX_P"
+ "ADDDrm\000MMX_PADDDrr\000MMX_PADDQrm\000MMX_PADDQrr\000MMX_PADDSBrm\000"
+ "MMX_PADDSBrr\000MMX_PADDSWrm\000MMX_PADDSWrr\000MMX_PADDUSBrm\000MMX_PA"
+ "DDUSBrr\000MMX_PADDUSWrm\000MMX_PADDUSWrr\000MMX_PADDWrm\000MMX_PADDWrr"
+ "\000MMX_PANDNrm\000MMX_PANDNrr\000MMX_PANDrm\000MMX_PANDrr\000MMX_PAVGB"
+ "rm\000MMX_PAVGBrr\000MMX_PAVGWrm\000MMX_PAVGWrr\000MMX_PCMPEQBrm\000MMX"
+ "_PCMPEQBrr\000MMX_PCMPEQDrm\000MMX_PCMPEQDrr\000MMX_PCMPEQWrm\000MMX_PC"
+ "MPEQWrr\000MMX_PCMPGTBrm\000MMX_PCMPGTBrr\000MMX_PCMPGTDrm\000MMX_PCMPG"
+ "TDrr\000MMX_PCMPGTWrm\000MMX_PCMPGTWrr\000MMX_PEXTRWri\000MMX_PINSRWrmi"
+ "\000MMX_PINSRWrri\000MMX_PMADDWDrm\000MMX_PMADDWDrr\000MMX_PMAXSWrm\000"
+ "MMX_PMAXSWrr\000MMX_PMAXUBrm\000MMX_PMAXUBrr\000MMX_PMINSWrm\000MMX_PMI"
+ "NSWrr\000MMX_PMINUBrm\000MMX_PMINUBrr\000MMX_PMOVMSKBrr\000MMX_PMULHUWr"
+ "m\000MMX_PMULHUWrr\000MMX_PMULHWrm\000MMX_PMULHWrr\000MMX_PMULLWrm\000M"
+ "MX_PMULLWrr\000MMX_PMULUDQrm\000MMX_PMULUDQrr\000MMX_PORrm\000MMX_PORrr"
+ "\000MMX_PSADBWrm\000MMX_PSADBWrr\000MMX_PSHUFWmi\000MMX_PSHUFWri\000MMX"
+ "_PSLLDri\000MMX_PSLLDrm\000MMX_PSLLDrr\000MMX_PSLLQri\000MMX_PSLLQrm\000"
+ "MMX_PSLLQrr\000MMX_PSLLWri\000MMX_PSLLWrm\000MMX_PSLLWrr\000MMX_PSRADri"
+ "\000MMX_PSRADrm\000MMX_PSRADrr\000MMX_PSRAWri\000MMX_PSRAWrm\000MMX_PSR"
+ "AWrr\000MMX_PSRLDri\000MMX_PSRLDrm\000MMX_PSRLDrr\000MMX_PSRLQri\000MMX"
+ "_PSRLQrm\000MMX_PSRLQrr\000MMX_PSRLWri\000MMX_PSRLWrm\000MMX_PSRLWrr\000"
+ "MMX_PSUBBrm\000MMX_PSUBBrr\000MMX_PSUBDrm\000MMX_PSUBDrr\000MMX_PSUBQrm"
+ "\000MMX_PSUBQrr\000MMX_PSUBSBrm\000MMX_PSUBSBrr\000MMX_PSUBSWrm\000MMX_"
+ "PSUBSWrr\000MMX_PSUBUSBrm\000MMX_PSUBUSBrr\000MMX_PSUBUSWrm\000MMX_PSUB"
+ "USWrr\000MMX_PSUBWrm\000MMX_PSUBWrr\000MMX_PUNPCKHBWrm\000MMX_PUNPCKHBW"
+ "rr\000MMX_PUNPCKHDQrm\000MMX_PUNPCKHDQrr\000MMX_PUNPCKHWDrm\000MMX_PUNP"
+ "CKHWDrr\000MMX_PUNPCKLBWrm\000MMX_PUNPCKLBWrr\000MMX_PUNPCKLDQrm\000MMX"
+ "_PUNPCKLDQrr\000MMX_PUNPCKLWDrm\000MMX_PUNPCKLWDrr\000MMX_PXORrm\000MMX"
+ "_PXORrr\000MMX_V_SET0\000MMX_V_SETALLONES\000MONITOR\000MOV16ao16\000MO"
+ "V16mi\000MOV16mr\000MOV16ms\000MOV16o16a\000MOV16r0\000MOV16ri\000MOV16"
+ "rm\000MOV16rr\000MOV16rr_REV\000MOV16rs\000MOV16sm\000MOV16sr\000MOV32a"
+ "o32\000MOV32cr\000MOV32dr\000MOV32mi\000MOV32mr\000MOV32o32a\000MOV32r0"
+ "\000MOV32rc\000MOV32rd\000MOV32ri\000MOV32rm\000MOV32rr\000MOV32rr_REV\000"
+ "MOV64FSrm\000MOV64GSrm\000MOV64ao64\000MOV64ao8\000MOV64cr\000MOV64dr\000"
+ "MOV64mi32\000MOV64mr\000MOV64ms\000MOV64o64a\000MOV64o8a\000MOV64r0\000"
+ "MOV64rc\000MOV64rd\000MOV64ri\000MOV64ri32\000MOV64ri64i32\000MOV64rm\000"
+ "MOV64rr\000MOV64rr_REV\000MOV64rs\000MOV64sm\000MOV64sr\000MOV64toPQIrr"
+ "\000MOV64toSDrm\000MOV64toSDrr\000MOV8ao8\000MOV8mi\000MOV8mr\000MOV8mr"
+ "_NOREX\000MOV8o8a\000MOV8r0\000MOV8ri\000MOV8rm\000MOV8rm_NOREX\000MOV8"
+ "rr\000MOV8rr_NOREX\000MOV8rr_REV\000MOVAPDmr\000MOVAPDrm\000MOVAPDrr\000"
+ "MOVAPSmr\000MOVAPSrm\000MOVAPSrr\000MOVDDUPrm\000MOVDDUPrr\000MOVDI2PDI"
+ "rm\000MOVDI2PDIrr\000MOVDI2SSrm\000MOVDI2SSrr\000MOVDQAmr\000MOVDQArm\000"
+ "MOVDQArr\000MOVDQUmr\000MOVDQUmr_Int\000MOVDQUrm\000MOVDQUrm_Int\000MOV"
+ "HLPSrr\000MOVHPDmr\000MOVHPDrm\000MOVHPSmr\000MOVHPSrm\000MOVLHPSrr\000"
+ "MOVLPDmr\000MOVLPDrm\000MOVLPSmr\000MOVLPSrm\000MOVLQ128mr\000MOVMSKPDr"
+ "r\000MOVMSKPSrr\000MOVNTDQArm\000MOVNTDQ_64mr\000MOVNTDQmr\000MOVNTDQmr"
+ "_Int\000MOVNTI_64mr\000MOVNTImr\000MOVNTImr_Int\000MOVNTPDmr\000MOVNTPD"
+ "mr_Int\000MOVNTPSmr\000MOVNTPSmr_Int\000MOVPC32r\000MOVPDI2DImr\000MOVP"
+ "DI2DIrr\000MOVPQI2QImr\000MOVPQIto64rr\000MOVQI2PQIrm\000MOVQxrxr\000MO"
+ "VSB\000MOVSD\000MOVSDmr\000MOVSDrm\000MOVSDrr\000MOVSDto64mr\000MOVSDto"
+ "64rr\000MOVSHDUPrm\000MOVSHDUPrr\000MOVSLDUPrm\000MOVSLDUPrr\000MOVSS2D"
+ "Imr\000MOVSS2DIrr\000MOVSSmr\000MOVSSrm\000MOVSSrr\000MOVSW\000MOVSX16r"
+ "m8\000MOVSX16rm8W\000MOVSX16rr8\000MOVSX16rr8W\000MOVSX32rm16\000MOVSX3"
+ "2rm8\000MOVSX32rr16\000MOVSX32rr8\000MOVSX64rm16\000MOVSX64rm32\000MOVS"
+ "X64rm8\000MOVSX64rr16\000MOVSX64rr32\000MOVSX64rr8\000MOVUPDmr\000MOVUP"
+ "Dmr_Int\000MOVUPDrm\000MOVUPDrm_Int\000MOVUPDrr\000MOVUPSmr\000MOVUPSmr"
+ "_Int\000MOVUPSrm\000MOVUPSrm_Int\000MOVUPSrr\000MOVZDI2PDIrm\000MOVZDI2"
+ "PDIrr\000MOVZPQILo2PQIrm\000MOVZPQILo2PQIrr\000MOVZQI2PQIrm\000MOVZQI2P"
+ "QIrr\000MOVZX16rm8\000MOVZX16rm8W\000MOVZX16rr8\000MOVZX16rr8W\000MOVZX"
+ "32_NOREXrm8\000MOVZX32_NOREXrr8\000MOVZX32rm16\000MOVZX32rm8\000MOVZX32"
+ "rr16\000MOVZX32rr8\000MOVZX64rm16\000MOVZX64rm16_Q\000MOVZX64rm32\000MO"
+ "VZX64rm8\000MOVZX64rm8_Q\000MOVZX64rr16\000MOVZX64rr16_Q\000MOVZX64rr32"
+ "\000MOVZX64rr8\000MOVZX64rr8_Q\000MOV_Fp3232\000MOV_Fp3264\000MOV_Fp328"
+ "0\000MOV_Fp6432\000MOV_Fp6464\000MOV_Fp6480\000MOV_Fp8032\000MOV_Fp8064"
+ "\000MOV_Fp8080\000MPSADBWrmi\000MPSADBWrri\000MUL16m\000MUL16r\000MUL32"
+ "m\000MUL32r\000MUL64m\000MUL64r\000MUL8m\000MUL8r\000MULPDrm\000MULPDrr"
+ "\000MULPSrm\000MULPSrr\000MULSDrm\000MULSDrm_Int\000MULSDrr\000MULSDrr_"
+ "Int\000MULSSrm\000MULSSrm_Int\000MULSSrr\000MULSSrr_Int\000MUL_F32m\000"
+ "MUL_F64m\000MUL_FI16m\000MUL_FI32m\000MUL_FPrST0\000MUL_FST0r\000MUL_Fp"
+ "32\000MUL_Fp32m\000MUL_Fp64\000MUL_Fp64m\000MUL_Fp64m32\000MUL_Fp80\000"
+ "MUL_Fp80m32\000MUL_Fp80m64\000MUL_FpI16m32\000MUL_FpI16m64\000MUL_FpI16"
+ "m80\000MUL_FpI32m32\000MUL_FpI32m64\000MUL_FpI32m80\000MUL_FrST0\000MWA"
+ "IT\000NEG16m\000NEG16r\000NEG32m\000NEG32r\000NEG64m\000NEG64r\000NEG8m"
+ "\000NEG8r\000NOOP\000NOOPL\000NOOPW\000NOT16m\000NOT16r\000NOT32m\000NO"
+ "T32r\000NOT64m\000NOT64r\000NOT8m\000NOT8r\000OR16i16\000OR16mi\000OR16"
+ "mi8\000OR16mr\000OR16ri\000OR16ri8\000OR16rm\000OR16rr\000OR16rr_REV\000"
+ "OR32i32\000OR32mi\000OR32mi8\000OR32mr\000OR32ri\000OR32ri8\000OR32rm\000"
+ "OR32rr\000OR32rr_REV\000OR64i32\000OR64mi32\000OR64mi8\000OR64mr\000OR6"
+ "4ri32\000OR64ri8\000OR64rm\000OR64rr\000OR64rr_REV\000OR8i8\000OR8mi\000"
+ "OR8mr\000OR8ri\000OR8rm\000OR8rr\000OR8rr_REV\000ORPDrm\000ORPDrr\000OR"
+ "PSrm\000ORPSrr\000OUT16ir\000OUT16rr\000OUT32ir\000OUT32rr\000OUT8ir\000"
+ "OUT8rr\000OUTSB\000OUTSD\000OUTSW\000PABSBrm128\000PABSBrm64\000PABSBrr"
+ "128\000PABSBrr64\000PABSDrm128\000PABSDrm64\000PABSDrr128\000PABSDrr64\000"
+ "PABSWrm128\000PABSWrm64\000PABSWrr128\000PABSWrr64\000PACKSSDWrm\000PAC"
+ "KSSDWrr\000PACKSSWBrm\000PACKSSWBrr\000PACKUSDWrm\000PACKUSDWrr\000PACK"
+ "USWBrm\000PACKUSWBrr\000PADDBrm\000PADDBrr\000PADDDrm\000PADDDrr\000PAD"
+ "DQrm\000PADDQrr\000PADDSBrm\000PADDSBrr\000PADDSWrm\000PADDSWrr\000PADD"
+ "USBrm\000PADDUSBrr\000PADDUSWrm\000PADDUSWrr\000PADDWrm\000PADDWrr\000P"
+ "ALIGNR128rm\000PALIGNR128rr\000PALIGNR64rm\000PALIGNR64rr\000PANDNrm\000"
+ "PANDNrr\000PANDrm\000PANDrr\000PAVGBrm\000PAVGBrr\000PAVGWrm\000PAVGWrr"
+ "\000PBLENDVBrm0\000PBLENDVBrr0\000PBLENDWrmi\000PBLENDWrri\000PCMPEQBrm"
+ "\000PCMPEQBrr\000PCMPEQDrm\000PCMPEQDrr\000PCMPEQQrm\000PCMPEQQrr\000PC"
+ "MPEQWrm\000PCMPEQWrr\000PCMPESTRIArm\000PCMPESTRIArr\000PCMPESTRICrm\000"
+ "PCMPESTRICrr\000PCMPESTRIOrm\000PCMPESTRIOrr\000PCMPESTRISrm\000PCMPEST"
+ "RISrr\000PCMPESTRIZrm\000PCMPESTRIZrr\000PCMPESTRIrm\000PCMPESTRIrr\000"
+ "PCMPESTRM128MEM\000PCMPESTRM128REG\000PCMPESTRM128rm\000PCMPESTRM128rr\000"
+ "PCMPGTBrm\000PCMPGTBrr\000PCMPGTDrm\000PCMPGTDrr\000PCMPGTQrm\000PCMPGT"
+ "Qrr\000PCMPGTWrm\000PCMPGTWrr\000PCMPISTRIArm\000PCMPISTRIArr\000PCMPIS"
+ "TRICrm\000PCMPISTRICrr\000PCMPISTRIOrm\000PCMPISTRIOrr\000PCMPISTRISrm\000"
+ "PCMPISTRISrr\000PCMPISTRIZrm\000PCMPISTRIZrr\000PCMPISTRIrm\000PCMPISTR"
+ "Irr\000PCMPISTRM128MEM\000PCMPISTRM128REG\000PCMPISTRM128rm\000PCMPISTR"
+ "M128rr\000PEXTRBmr\000PEXTRBrr\000PEXTRDmr\000PEXTRDrr\000PEXTRQmr\000P"
+ "EXTRQrr\000PEXTRWmr\000PEXTRWri\000PHADDDrm128\000PHADDDrm64\000PHADDDr"
+ "r128\000PHADDDrr64\000PHADDSWrm128\000PHADDSWrm64\000PHADDSWrr128\000PH"
+ "ADDSWrr64\000PHADDWrm128\000PHADDWrm64\000PHADDWrr128\000PHADDWrr64\000"
+ "PHMINPOSUWrm128\000PHMINPOSUWrr128\000PHSUBDrm128\000PHSUBDrm64\000PHSU"
+ "BDrr128\000PHSUBDrr64\000PHSUBSWrm128\000PHSUBSWrm64\000PHSUBSWrr128\000"
+ "PHSUBSWrr64\000PHSUBWrm128\000PHSUBWrm64\000PHSUBWrr128\000PHSUBWrr64\000"
+ "PINSRBrm\000PINSRBrr\000PINSRDrm\000PINSRDrr\000PINSRQrm\000PINSRQrr\000"
+ "PINSRWrmi\000PINSRWrri\000PMADDUBSWrm128\000PMADDUBSWrm64\000PMADDUBSWr"
+ "r128\000PMADDUBSWrr64\000PMADDWDrm\000PMADDWDrr\000PMAXSBrm\000PMAXSBrr"
+ "\000PMAXSDrm\000PMAXSDrr\000PMAXSWrm\000PMAXSWrr\000PMAXUBrm\000PMAXUBr"
+ "r\000PMAXUDrm\000PMAXUDrr\000PMAXUWrm\000PMAXUWrr\000PMINSBrm\000PMINSB"
+ "rr\000PMINSDrm\000PMINSDrr\000PMINSWrm\000PMINSWrr\000PMINUBrm\000PMINU"
+ "Brr\000PMINUDrm\000PMINUDrr\000PMINUWrm\000PMINUWrr\000PMOVMSKBrr\000PM"
+ "OVSXBDrm\000PMOVSXBDrr\000PMOVSXBQrm\000PMOVSXBQrr\000PMOVSXBWrm\000PMO"
+ "VSXBWrr\000PMOVSXDQrm\000PMOVSXDQrr\000PMOVSXWDrm\000PMOVSXWDrr\000PMOV"
+ "SXWQrm\000PMOVSXWQrr\000PMOVZXBDrm\000PMOVZXBDrr\000PMOVZXBQrm\000PMOVZ"
+ "XBQrr\000PMOVZXBWrm\000PMOVZXBWrr\000PMOVZXDQrm\000PMOVZXDQrr\000PMOVZX"
+ "WDrm\000PMOVZXWDrr\000PMOVZXWQrm\000PMOVZXWQrr\000PMULDQrm\000PMULDQrr\000"
+ "PMULHRSWrm128\000PMULHRSWrm64\000PMULHRSWrr128\000PMULHRSWrr64\000PMULH"
+ "UWrm\000PMULHUWrr\000PMULHWrm\000PMULHWrr\000PMULLDrm\000PMULLDrm_int\000"
+ "PMULLDrr\000PMULLDrr_int\000PMULLWrm\000PMULLWrr\000PMULUDQrm\000PMULUD"
+ "Qrr\000POP16r\000POP16rmm\000POP16rmr\000POP32r\000POP32rmm\000POP32rmr"
+ "\000POP64r\000POP64rmm\000POP64rmr\000POPCNT16rm\000POPCNT16rr\000POPCN"
+ "T32rm\000POPCNT32rr\000POPCNT64rm\000POPCNT64rr\000POPF\000POPFD\000POP"
+ "FQ\000POPFS16\000POPFS32\000POPFS64\000POPGS16\000POPGS32\000POPGS64\000"
+ "PORrm\000PORrr\000PREFETCHNTA\000PREFETCHT0\000PREFETCHT1\000PREFETCHT2"
+ "\000PSADBWrm\000PSADBWrr\000PSHUFBrm128\000PSHUFBrm64\000PSHUFBrr128\000"
+ "PSHUFBrr64\000PSHUFDmi\000PSHUFDri\000PSHUFHWmi\000PSHUFHWri\000PSHUFLW"
+ "mi\000PSHUFLWri\000PSIGNBrm128\000PSIGNBrm64\000PSIGNBrr128\000PSIGNBrr"
+ "64\000PSIGNDrm128\000PSIGNDrm64\000PSIGNDrr128\000PSIGNDrr64\000PSIGNWr"
+ "m128\000PSIGNWrm64\000PSIGNWrr128\000PSIGNWrr64\000PSLLDQri\000PSLLDri\000"
+ "PSLLDrm\000PSLLDrr\000PSLLQri\000PSLLQrm\000PSLLQrr\000PSLLWri\000PSLLW"
+ "rm\000PSLLWrr\000PSRADri\000PSRADrm\000PSRADrr\000PSRAWri\000PSRAWrm\000"
+ "PSRAWrr\000PSRLDQri\000PSRLDri\000PSRLDrm\000PSRLDrr\000PSRLQri\000PSRL"
+ "Qrm\000PSRLQrr\000PSRLWri\000PSRLWrm\000PSRLWrr\000PSUBBrm\000PSUBBrr\000"
+ "PSUBDrm\000PSUBDrr\000PSUBQrm\000PSUBQrr\000PSUBSBrm\000PSUBSBrr\000PSU"
+ "BSWrm\000PSUBSWrr\000PSUBUSBrm\000PSUBUSBrr\000PSUBUSWrm\000PSUBUSWrr\000"
+ "PSUBWrm\000PSUBWrr\000PTESTrm\000PTESTrr\000PUNPCKHBWrm\000PUNPCKHBWrr\000"
+ "PUNPCKHDQrm\000PUNPCKHDQrr\000PUNPCKHQDQrm\000PUNPCKHQDQrr\000PUNPCKHWD"
+ "rm\000PUNPCKHWDrr\000PUNPCKLBWrm\000PUNPCKLBWrr\000PUNPCKLDQrm\000PUNPC"
+ "KLDQrr\000PUNPCKLQDQrm\000PUNPCKLQDQrr\000PUNPCKLWDrm\000PUNPCKLWDrr\000"
+ "PUSH16r\000PUSH16rmm\000PUSH16rmr\000PUSH32i16\000PUSH32i32\000PUSH32i8"
+ "\000PUSH32r\000PUSH32rmm\000PUSH32rmr\000PUSH64i16\000PUSH64i32\000PUSH"
+ "64i8\000PUSH64r\000PUSH64rmm\000PUSH64rmr\000PUSHF\000PUSHFD\000PUSHFQ6"
+ "4\000PUSHFS16\000PUSHFS32\000PUSHFS64\000PUSHGS16\000PUSHGS32\000PUSHGS"
+ "64\000PXORrm\000PXORrr\000RCL16m1\000RCL16mCL\000RCL16mi\000RCL16r1\000"
+ "RCL16rCL\000RCL16ri\000RCL32m1\000RCL32mCL\000RCL32mi\000RCL32r1\000RCL"
+ "32rCL\000RCL32ri\000RCL64m1\000RCL64mCL\000RCL64mi\000RCL64r1\000RCL64r"
+ "CL\000RCL64ri\000RCL8m1\000RCL8mCL\000RCL8mi\000RCL8r1\000RCL8rCL\000RC"
+ "L8ri\000RCPPSm\000RCPPSm_Int\000RCPPSr\000RCPPSr_Int\000RCPSSm\000RCPSS"
+ "m_Int\000RCPSSr\000RCPSSr_Int\000RCR16m1\000RCR16mCL\000RCR16mi\000RCR1"
+ "6r1\000RCR16rCL\000RCR16ri\000RCR32m1\000RCR32mCL\000RCR32mi\000RCR32r1"
+ "\000RCR32rCL\000RCR32ri\000RCR64m1\000RCR64mCL\000RCR64mi\000RCR64r1\000"
+ "RCR64rCL\000RCR64ri\000RCR8m1\000RCR8mCL\000RCR8mi\000RCR8r1\000RCR8rCL"
+ "\000RCR8ri\000RDMSR\000RDPMC\000RDTSC\000RDTSCP\000REPNE_PREFIX\000REP_"
+ "MOVSB\000REP_MOVSD\000REP_MOVSQ\000REP_MOVSW\000REP_PREFIX\000REP_STOSB"
+ "\000REP_STOSD\000REP_STOSQ\000REP_STOSW\000RET\000RETI\000ROL16m1\000RO"
+ "L16mCL\000ROL16mi\000ROL16r1\000ROL16rCL\000ROL16ri\000ROL32m1\000ROL32"
+ "mCL\000ROL32mi\000ROL32r1\000ROL32rCL\000ROL32ri\000ROL64m1\000ROL64mCL"
+ "\000ROL64mi\000ROL64r1\000ROL64rCL\000ROL64ri\000ROL8m1\000ROL8mCL\000R"
+ "OL8mi\000ROL8r1\000ROL8rCL\000ROL8ri\000ROR16m1\000ROR16mCL\000ROR16mi\000"
+ "ROR16r1\000ROR16rCL\000ROR16ri\000ROR32m1\000ROR32mCL\000ROR32mi\000ROR"
+ "32r1\000ROR32rCL\000ROR32ri\000ROR64m1\000ROR64mCL\000ROR64mi\000ROR64r"
+ "1\000ROR64rCL\000ROR64ri\000ROR8m1\000ROR8mCL\000ROR8mi\000ROR8r1\000RO"
+ "R8rCL\000ROR8ri\000ROUNDPDm_Int\000ROUNDPDr_Int\000ROUNDPSm_Int\000ROUN"
+ "DPSr_Int\000ROUNDSDm_Int\000ROUNDSDr_Int\000ROUNDSSm_Int\000ROUNDSSr_In"
+ "t\000RSM\000RSQRTPSm\000RSQRTPSm_Int\000RSQRTPSr\000RSQRTPSr_Int\000RSQ"
+ "RTSSm\000RSQRTSSm_Int\000RSQRTSSr\000RSQRTSSr_Int\000SAHF\000SAR16m1\000"
+ "SAR16mCL\000SAR16mi\000SAR16r1\000SAR16rCL\000SAR16ri\000SAR32m1\000SAR"
+ "32mCL\000SAR32mi\000SAR32r1\000SAR32rCL\000SAR32ri\000SAR64m1\000SAR64m"
+ "CL\000SAR64mi\000SAR64r1\000SAR64rCL\000SAR64ri\000SAR8m1\000SAR8mCL\000"
+ "SAR8mi\000SAR8r1\000SAR8rCL\000SAR8ri\000SBB16i16\000SBB16mi\000SBB16mi"
+ "8\000SBB16mr\000SBB16ri\000SBB16ri8\000SBB16rm\000SBB16rr\000SBB16rr_RE"
+ "V\000SBB32i32\000SBB32mi\000SBB32mi8\000SBB32mr\000SBB32ri\000SBB32ri8\000"
+ "SBB32rm\000SBB32rr\000SBB32rr_REV\000SBB64i32\000SBB64mi32\000SBB64mi8\000"
+ "SBB64mr\000SBB64ri32\000SBB64ri8\000SBB64rm\000SBB64rr\000SBB64rr_REV\000"
+ "SBB8i8\000SBB8mi\000SBB8mr\000SBB8ri\000SBB8rm\000SBB8rr\000SBB8rr_REV\000"
+ "SCAS16\000SCAS32\000SCAS64\000SCAS8\000SETAEm\000SETAEr\000SETAm\000SET"
+ "Ar\000SETBEm\000SETBEr\000SETB_C16r\000SETB_C32r\000SETB_C64r\000SETB_C"
+ "8r\000SETBm\000SETBr\000SETEm\000SETEr\000SETGEm\000SETGEr\000SETGm\000"
+ "SETGr\000SETLEm\000SETLEr\000SETLm\000SETLr\000SETNEm\000SETNEr\000SETN"
+ "Om\000SETNOr\000SETNPm\000SETNPr\000SETNSm\000SETNSr\000SETOm\000SETOr\000"
+ "SETPm\000SETPr\000SETSm\000SETSr\000SFENCE\000SGDTm\000SHL16m1\000SHL16"
+ "mCL\000SHL16mi\000SHL16r1\000SHL16rCL\000SHL16ri\000SHL32m1\000SHL32mCL"
+ "\000SHL32mi\000SHL32r1\000SHL32rCL\000SHL32ri\000SHL64m1\000SHL64mCL\000"
+ "SHL64mi\000SHL64r1\000SHL64rCL\000SHL64ri\000SHL8m1\000SHL8mCL\000SHL8m"
+ "i\000SHL8r1\000SHL8rCL\000SHL8ri\000SHLD16mrCL\000SHLD16mri8\000SHLD16r"
+ "rCL\000SHLD16rri8\000SHLD32mrCL\000SHLD32mri8\000SHLD32rrCL\000SHLD32rr"
+ "i8\000SHLD64mrCL\000SHLD64mri8\000SHLD64rrCL\000SHLD64rri8\000SHR16m1\000"
+ "SHR16mCL\000SHR16mi\000SHR16r1\000SHR16rCL\000SHR16ri\000SHR32m1\000SHR"
+ "32mCL\000SHR32mi\000SHR32r1\000SHR32rCL\000SHR32ri\000SHR64m1\000SHR64m"
+ "CL\000SHR64mi\000SHR64r1\000SHR64rCL\000SHR64ri\000SHR8m1\000SHR8mCL\000"
+ "SHR8mi\000SHR8r1\000SHR8rCL\000SHR8ri\000SHRD16mrCL\000SHRD16mri8\000SH"
+ "RD16rrCL\000SHRD16rri8\000SHRD32mrCL\000SHRD32mri8\000SHRD32rrCL\000SHR"
+ "D32rri8\000SHRD64mrCL\000SHRD64mri8\000SHRD64rrCL\000SHRD64rri8\000SHUF"
+ "PDrmi\000SHUFPDrri\000SHUFPSrmi\000SHUFPSrri\000SIDTm\000SIN_F\000SIN_F"
+ "p32\000SIN_Fp64\000SIN_Fp80\000SLDT16m\000SLDT16r\000SLDT64m\000SLDT64r"
+ "\000SMSW16m\000SMSW16r\000SMSW32r\000SMSW64r\000SQRTPDm\000SQRTPDm_Int\000"
+ "SQRTPDr\000SQRTPDr_Int\000SQRTPSm\000SQRTPSm_Int\000SQRTPSr\000SQRTPSr_"
+ "Int\000SQRTSDm\000SQRTSDm_Int\000SQRTSDr\000SQRTSDr_Int\000SQRTSSm\000S"
+ "QRTSSm_Int\000SQRTSSr\000SQRTSSr_Int\000SQRT_F\000SQRT_Fp32\000SQRT_Fp6"
+ "4\000SQRT_Fp80\000SS_PREFIX\000STC\000STD\000STI\000STMXCSR\000STOSB\000"
+ "STOSD\000STOSW\000STRm\000STRr\000ST_F32m\000ST_F64m\000ST_FP32m\000ST_"
+ "FP64m\000ST_FP80m\000ST_FPrr\000ST_Fp32m\000ST_Fp64m\000ST_Fp64m32\000S"
+ "T_Fp80m32\000ST_Fp80m64\000ST_FpP32m\000ST_FpP64m\000ST_FpP64m32\000ST_"
+ "FpP80m\000ST_FpP80m32\000ST_FpP80m64\000ST_Frr\000SUB16i16\000SUB16mi\000"
+ "SUB16mi8\000SUB16mr\000SUB16ri\000SUB16ri8\000SUB16rm\000SUB16rr\000SUB"
+ "16rr_REV\000SUB32i32\000SUB32mi\000SUB32mi8\000SUB32mr\000SUB32ri\000SU"
+ "B32ri8\000SUB32rm\000SUB32rr\000SUB32rr_REV\000SUB64i32\000SUB64mi32\000"
+ "SUB64mi8\000SUB64mr\000SUB64ri32\000SUB64ri8\000SUB64rm\000SUB64rr\000S"
+ "UB64rr_REV\000SUB8i8\000SUB8mi\000SUB8mr\000SUB8ri\000SUB8rm\000SUB8rr\000"
+ "SUB8rr_REV\000SUBPDrm\000SUBPDrr\000SUBPSrm\000SUBPSrr\000SUBR_F32m\000"
+ "SUBR_F64m\000SUBR_FI16m\000SUBR_FI32m\000SUBR_FPrST0\000SUBR_FST0r\000S"
+ "UBR_Fp32m\000SUBR_Fp64m\000SUBR_Fp64m32\000SUBR_Fp80m32\000SUBR_Fp80m64"
+ "\000SUBR_FpI16m32\000SUBR_FpI16m64\000SUBR_FpI16m80\000SUBR_FpI32m32\000"
+ "SUBR_FpI32m64\000SUBR_FpI32m80\000SUBR_FrST0\000SUBSDrm\000SUBSDrm_Int\000"
+ "SUBSDrr\000SUBSDrr_Int\000SUBSSrm\000SUBSSrm_Int\000SUBSSrr\000SUBSSrr_"
+ "Int\000SUB_F32m\000SUB_F64m\000SUB_FI16m\000SUB_FI32m\000SUB_FPrST0\000"
+ "SUB_FST0r\000SUB_Fp32\000SUB_Fp32m\000SUB_Fp64\000SUB_Fp64m\000SUB_Fp64"
+ "m32\000SUB_Fp80\000SUB_Fp80m32\000SUB_Fp80m64\000SUB_FpI16m32\000SUB_Fp"
+ "I16m64\000SUB_FpI16m80\000SUB_FpI32m32\000SUB_FpI32m64\000SUB_FpI32m80\000"
+ "SUB_FrST0\000SWAPGS\000SYSCALL\000SYSENTER\000SYSEXIT\000SYSEXIT64\000S"
+ "YSRET\000TAILJMPd\000TAILJMPm\000TAILJMPr\000TAILJMPr64\000TCRETURNdi\000"
+ "TCRETURNdi64\000TCRETURNri\000TCRETURNri64\000TEST16i16\000TEST16mi\000"
+ "TEST16ri\000TEST16rm\000TEST16rr\000TEST32i32\000TEST32mi\000TEST32ri\000"
+ "TEST32rm\000TEST32rr\000TEST64i32\000TEST64mi32\000TEST64ri32\000TEST64"
+ "rm\000TEST64rr\000TEST8i8\000TEST8mi\000TEST8ri\000TEST8rm\000TEST8rr\000"
+ "TLS_addr32\000TLS_addr64\000TRAP\000TST_F\000TST_Fp32\000TST_Fp64\000TS"
+ "T_Fp80\000UCOMISDrm\000UCOMISDrr\000UCOMISSrm\000UCOMISSrr\000UCOM_FIPr"
+ "\000UCOM_FIr\000UCOM_FPPr\000UCOM_FPr\000UCOM_FpIr32\000UCOM_FpIr64\000"
+ "UCOM_FpIr80\000UCOM_Fpr32\000UCOM_Fpr64\000UCOM_Fpr80\000UCOM_Fr\000UNP"
+ "CKHPDrm\000UNPCKHPDrr\000UNPCKHPSrm\000UNPCKHPSrr\000UNPCKLPDrm\000UNPC"
+ "KLPDrr\000UNPCKLPSrm\000UNPCKLPSrr\000VASTART_SAVE_XMM_REGS\000VERRm\000"
+ "VERRr\000VERWm\000VERWr\000VMCALL\000VMCLEARm\000VMLAUNCH\000VMPTRLDm\000"
+ "VMPTRSTm\000VMREAD32rm\000VMREAD32rr\000VMREAD64rm\000VMREAD64rr\000VMR"
+ "ESUME\000VMWRITE32rm\000VMWRITE32rr\000VMWRITE64rm\000VMWRITE64rr\000VM"
+ "XOFF\000VMXON\000V_SET0\000V_SETALLONES\000WAIT\000WBINVD\000WINCALL64m"
+ "\000WINCALL64pcrel32\000WINCALL64r\000WRMSR\000XADD16rm\000XADD16rr\000"
+ "XADD32rm\000XADD32rr\000XADD64rm\000XADD64rr\000XADD8rm\000XADD8rr\000X"
+ "CHG16ar\000XCHG16rm\000XCHG16rr\000XCHG32ar\000XCHG32rm\000XCHG32rr\000"
+ "XCHG64ar\000XCHG64rm\000XCHG64rr\000XCHG8rm\000XCHG8rr\000XCH_F\000XLAT"
+ "\000XOR16i16\000XOR16mi\000XOR16mi8\000XOR16mr\000XOR16ri\000XOR16ri8\000"
+ "XOR16rm\000XOR16rr\000XOR16rr_REV\000XOR32i32\000XOR32mi\000XOR32mi8\000"
+ "XOR32mr\000XOR32ri\000XOR32ri8\000XOR32rm\000XOR32rr\000XOR32rr_REV\000"
+ "XOR64i32\000XOR64mi32\000XOR64mi8\000XOR64mr\000XOR64ri32\000XOR64ri8\000"
+ "XOR64rm\000XOR64rr\000XOR64rr_REV\000XOR8i8\000XOR8mi\000XOR8mr\000XOR8"
+ "ri\000XOR8rm\000XOR8rr\000XOR8rr_REV\000XORPDrm\000XORPDrr\000XORPSrm\000"
+ "XORPSrr\000";
return Strs+InstAsmOffset[Opcode];
}
diff --git a/libclamav/c++/X86GenCallingConv.inc b/libclamav/c++/X86GenCallingConv.inc
index d9ee7d6..ec2d76e 100644
--- a/libclamav/c++/X86GenCallingConv.inc
+++ b/libclamav/c++/X86GenCallingConv.inc
@@ -18,9 +18,15 @@ static bool CC_X86_32_FastCC(unsigned ValNo, EVT ValVT,
static bool CC_X86_32_FastCall(unsigned ValNo, EVT ValVT,
EVT LocVT, CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool CC_X86_32_GHC(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
static bool CC_X86_64_C(unsigned ValNo, EVT ValVT,
EVT LocVT, CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State);
+static bool CC_X86_64_GHC(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State);
static bool CC_X86_Win64_C(unsigned ValNo, EVT ValVT,
EVT LocVT, CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State);
@@ -299,6 +305,35 @@ static bool CC_X86_32_FastCall(unsigned ValNo, EVT ValVT,
}
+static bool CC_X86_32_GHC(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (LocVT == MVT::i8 ||
+ LocVT == MVT::i16) {
+ LocVT = MVT::i32;
+ if (ArgFlags.isSExt())
+ LocInfo = CCValAssign::SExt;
+ else if (ArgFlags.isZExt())
+ LocInfo = CCValAssign::ZExt;
+ else
+ LocInfo = CCValAssign::AExt;
+ }
+
+ if (LocVT == MVT::i32) {
+ static const unsigned RegList1[] = {
+ X86::EBX, X86::EBP, X86::EDI, X86::ESI
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1, 4)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ return true; // CC didn't match.
+}
+
+
static bool CC_X86_64_C(unsigned ValNo, EVT ValVT,
EVT LocVT, CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State) {
@@ -431,6 +466,55 @@ static bool CC_X86_64_C(unsigned ValNo, EVT ValVT,
}
+static bool CC_X86_64_GHC(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+ if (LocVT == MVT::i8 ||
+ LocVT == MVT::i16 ||
+ LocVT == MVT::i32) {
+ LocVT = MVT::i64;
+ if (ArgFlags.isSExt())
+ LocInfo = CCValAssign::SExt;
+ else if (ArgFlags.isZExt())
+ LocInfo = CCValAssign::ZExt;
+ else
+ LocInfo = CCValAssign::AExt;
+ }
+
+ if (LocVT == MVT::i64) {
+ static const unsigned RegList1[] = {
+ X86::R13, X86::RBP, X86::R12, X86::RBX, X86::R14, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R15
+ };
+ if (unsigned Reg = State.AllocateReg(RegList1, 10)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+
+ if (LocVT == MVT::f32 ||
+ LocVT == MVT::f64 ||
+ LocVT == MVT::v16i8 ||
+ LocVT == MVT::v8i16 ||
+ LocVT == MVT::v4i32 ||
+ LocVT == MVT::v2i64 ||
+ LocVT == MVT::v4f32 ||
+ LocVT == MVT::v2f64) {
+ if (State.getTarget().getSubtarget<X86Subtarget>().hasSSE1()) {
+ static const unsigned RegList2[] = {
+ X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6
+ };
+ if (unsigned Reg = State.AllocateReg(RegList2, 6)) {
+ State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+ return false;
+ }
+ }
+ }
+
+ return true; // CC didn't match.
+}
+
+
static bool CC_X86_Win64_C(unsigned ValNo, EVT ValVT,
EVT LocVT, CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State) {
diff --git a/libclamav/c++/X86GenDAGISel.inc b/libclamav/c++/X86GenDAGISel.inc
index 72257cd..ee2a218 100644
--- a/libclamav/c++/X86GenDAGISel.inc
+++ b/libclamav/c++/X86GenDAGISel.inc
@@ -891,4534 +891,1201 @@ SDNode *SelectCode(SDNode *N) {
// Opcodes are emitted as 2 bytes, TARGET_OPCODE handles this.
#define TARGET_OPCODE(X) X & 255, unsigned(X) >> 8
static const unsigned char MatcherTable[] = {
- OPC_SwitchOpcode , 105|128,2|128,1, ISD::STORE,
- OPC_Scope, 77,
- OPC_CheckPredicate, 0,
- OPC_RecordMemRef,
- OPC_RecordNode,
+ OPC_SwitchOpcode , 117|128,6|128,1, ISD::STORE,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_Scope, 43|128,1,
OPC_RecordChild1,
- OPC_Scope, 23,
+ OPC_Scope, 49,
OPC_CheckChild1Type, MVT::v4f32,
OPC_RecordChild2,
- OPC_CheckPatternPredicate, 0,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVNTPSmr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 23,
+ OPC_CheckPredicate, 0,
+ OPC_Scope, 20,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVNTPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 20,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVNTDQmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 41,
OPC_CheckChild1Type, MVT::v2f64,
OPC_RecordChild2,
+ OPC_CheckPredicate, 0,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVNTDQ_64mr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 21,
- OPC_CheckChild1Type, MVT::v2i64,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVNTDQ_64mr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 1, 3, 4, 5, 6, 7,
- 0,
- 55,
- OPC_CheckPredicate, 1,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_Scope, 23,
+ OPC_Scope, 12,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVNTDQ_64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 12,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVNTPDmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 25,
OPC_CheckChild1Type, MVT::i32,
OPC_RecordChild2,
+ OPC_CheckPredicate, 1,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVNTImr), 0|OPFL_Chain|OPFL_MemRefs,
0, 6, 3, 4, 5, 6, 7, 1,
- 23,
+ 25,
OPC_CheckChild1Type, MVT::i64,
OPC_RecordChild2,
+ OPC_CheckPredicate, 1,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVNTI_64mr), 0|OPFL_Chain|OPFL_MemRefs,
0, 6, 3, 4, 5, 6, 7, 1,
- 0,
- 77,
- OPC_CheckPredicate, 0,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_Scope, 23,
- OPC_CheckChild1Type, MVT::v2f64,
- OPC_RecordChild2,
- OPC_CheckPatternPredicate, 1,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVNTPDmr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
23,
- OPC_CheckChild1Type, MVT::v4f32,
- OPC_RecordChild2,
- OPC_CheckPatternPredicate, 1,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVNTDQmr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 21,
OPC_CheckChild1Type, MVT::v4i32,
OPC_RecordChild2,
+ OPC_CheckPredicate, 0,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVNTDQmr), 0|OPFL_Chain|OPFL_MemRefs,
0, 6, 1, 3, 4, 5, 6, 7,
0,
- 16|128,1|128,1,
- OPC_CheckPredicate, 2,
- OPC_Scope, 54|128,121,
- OPC_CheckPredicate, 3,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_Scope, 64|128,120,
- OPC_MoveChild, 1,
- OPC_SwitchOpcode , 94|128,20, ISD::OR,
- OPC_Scope, 82|128,9,
- OPC_MoveChild, 0,
- OPC_SwitchOpcode , 100|128,4, ISD::SRL,
- OPC_Scope, 40|128,1,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 79,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::TRUNCATE,
- OPC_RecordChild0,
- OPC_RecordChild0,
- OPC_CheckChild0Type, MVT::i32,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SHL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::TRUNCATE,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SUB,
- OPC_MoveChild, 0,
- OPC_CheckInteger, 32,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 4, X86::ECX,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 6, 6, 7, 8, 9, 10, 5,
- 79,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::TRUNCATE,
- OPC_RecordChild0,
- OPC_RecordChild0,
- OPC_CheckChild0Type, MVT::i16,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SHL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::TRUNCATE,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SUB,
- OPC_MoveChild, 0,
- OPC_CheckInteger, 16,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 4, X86::CX,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 6, 6, 7, 8, 9, 10, 5,
- 0,
- 31|128,1,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::TRUNCATE,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SUB,
- OPC_MoveChild, 0,
- OPC_Scope, 72,
- OPC_CheckInteger, 32,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SHL,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::TRUNCATE,
- OPC_MoveChild, 0,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 5,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/5,
- OPC_EmitMergeInputChains, 2, 0, 4,
- OPC_EmitCopyToReg, 3, X86::ECX,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 6, 6, 7, 8, 9, 10, 1,
- 72,
- OPC_CheckInteger, 16,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SHL,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::TRUNCATE,
- OPC_MoveChild, 0,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 5,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/5,
- OPC_EmitMergeInputChains, 2, 0, 4,
- OPC_EmitCopyToReg, 3, X86::CX,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 6, 6, 7, 8, 9, 10, 1,
- 0,
- 12|128,1,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 65,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SHL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SUB,
- OPC_MoveChild, 0,
- OPC_CheckInteger, 32,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 4, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 6, 6, 7, 8, 9, 10, 5,
- 65,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SHL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SUB,
- OPC_MoveChild, 0,
- OPC_CheckInteger, 16,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 4, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 6, 6, 7, 8, 9, 10, 5,
- 0,
- 7|128,1,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SUB,
- OPC_MoveChild, 0,
- OPC_Scope, 62,
- OPC_CheckInteger, 32,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SHL,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 5,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/5,
- OPC_EmitMergeInputChains, 2, 0, 4,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 6, 6, 7, 8, 9, 10, 1,
- 62,
- OPC_CheckInteger, 16,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SHL,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 5,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/5,
- OPC_EmitMergeInputChains, 2, 0, 4,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 6, 6, 7, 8, 9, 10, 1,
- 0,
- 0,
- 100|128,4, ISD::SHL,
- OPC_Scope, 40|128,1,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 79,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::TRUNCATE,
- OPC_RecordChild0,
- OPC_RecordChild0,
- OPC_CheckChild0Type, MVT::i32,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SRL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::TRUNCATE,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SUB,
- OPC_MoveChild, 0,
- OPC_CheckInteger, 32,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 4, X86::ECX,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 6, 6, 7, 8, 9, 10, 5,
- 79,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::TRUNCATE,
- OPC_RecordChild0,
- OPC_RecordChild0,
- OPC_CheckChild0Type, MVT::i16,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SRL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::TRUNCATE,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SUB,
- OPC_MoveChild, 0,
- OPC_CheckInteger, 16,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 4, X86::CX,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 6, 6, 7, 8, 9, 10, 5,
- 0,
- 31|128,1,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::TRUNCATE,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SUB,
- OPC_MoveChild, 0,
- OPC_Scope, 72,
- OPC_CheckInteger, 32,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SRL,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::TRUNCATE,
- OPC_MoveChild, 0,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 5,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/5,
- OPC_EmitMergeInputChains, 2, 0, 4,
- OPC_EmitCopyToReg, 3, X86::ECX,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 6, 6, 7, 8, 9, 10, 1,
- 72,
- OPC_CheckInteger, 16,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SRL,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::TRUNCATE,
- OPC_MoveChild, 0,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 5,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/5,
- OPC_EmitMergeInputChains, 2, 0, 4,
- OPC_EmitCopyToReg, 3, X86::CX,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 6, 6, 7, 8, 9, 10, 1,
- 0,
- 12|128,1,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 65,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SRL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SUB,
- OPC_MoveChild, 0,
- OPC_CheckInteger, 32,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 4, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 6, 6, 7, 8, 9, 10, 5,
- 65,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SRL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SUB,
- OPC_MoveChild, 0,
- OPC_CheckInteger, 16,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 4, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 6, 6, 7, 8, 9, 10, 5,
- 0,
- 7|128,1,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SUB,
- OPC_MoveChild, 0,
- OPC_Scope, 62,
- OPC_CheckInteger, 32,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SRL,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 5,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/5,
- OPC_EmitMergeInputChains, 2, 0, 4,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 6, 6, 7, 8, 9, 10, 1,
- 62,
- OPC_CheckInteger, 16,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SRL,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 5,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/5,
- OPC_EmitMergeInputChains, 2, 0, 4,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 6, 6, 7, 8, 9, 10, 1,
- 0,
- 0,
- 0,
- 71,
- OPC_CheckPredicate, 7,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SRL,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SHL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32mri8), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 7, 5, 6, 7, 8, 9, 4, 10,
- 71,
- OPC_CheckPredicate, 8,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SHL,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SRL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32mri8), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 7, 5, 6, 7, 8, 9, 4, 10,
- 71,
- OPC_CheckPredicate, 7,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SRL,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SHL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16mri8), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 7, 5, 6, 7, 8, 9, 4, 10,
- 71,
- OPC_CheckPredicate, 8,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SHL,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SRL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16mri8), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 7, 5, 6, 7, 8, 9, 4, 10,
- 73,
- OPC_CheckPredicate, 7,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SRL,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SHL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD64mri8), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 7, 5, 6, 7, 8, 9, 4, 10,
- 73,
- OPC_CheckPredicate, 8,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SHL,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SRL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD64mri8), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 7, 5, 6, 7, 8, 9, 4, 10,
- 71,
- OPC_CheckPredicate, 7,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SHL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SRL,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_EmitConvertToTarget, 4,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32mri8), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 7, 5, 6, 7, 8, 9, 1, 10,
- 71,
- OPC_CheckPredicate, 8,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SRL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SHL,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_EmitConvertToTarget, 4,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32mri8), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 7, 5, 6, 7, 8, 9, 1, 10,
- 71,
- OPC_CheckPredicate, 7,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SHL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SRL,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_EmitConvertToTarget, 4,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16mri8), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 7, 5, 6, 7, 8, 9, 1, 10,
- 71,
- OPC_CheckPredicate, 8,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SRL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SHL,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_EmitConvertToTarget, 4,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16mri8), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 7, 5, 6, 7, 8, 9, 1, 10,
- 73,
- OPC_CheckPredicate, 7,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SHL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SRL,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_EmitConvertToTarget, 4,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD64mri8), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 7, 5, 6, 7, 8, 9, 1, 10,
- 73,
- OPC_CheckPredicate, 8,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SRL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SHL,
+ 104|128,124,
+ OPC_MoveChild, 1,
+ OPC_SwitchOpcode , 68|128,20, ISD::OR,
+ OPC_Scope, 46|128,19,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 118|128,7, ISD::SRL,
+ OPC_Scope, 44|128,1,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_EmitConvertToTarget, 4,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD64mri8), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 7, 5, 6, 7, 8, 9, 1, 10,
- 28|128,3,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 63|128,1,
- OPC_CheckPredicate, 9,
- OPC_Scope, 105,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckPredicate, 11,
- OPC_MoveParent,
- OPC_SwitchType , 28, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16mi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 28, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32mi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 28, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64mi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 0,
- 80,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_Scope, 33,
- OPC_CheckPredicate, 12,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64mi32), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 31,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR8mi), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 0,
- 0,
- 43,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 79,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
- OPC_RecordChild1,
OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_RecordChild0,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::i32,
+ OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16mi), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 43,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
- OPC_RecordChild1,
OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32mi), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 122,
- OPC_CheckPredicate, 9,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_SwitchType , 26, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR8mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 26, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 26, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 26, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 0,
- 0,
- 0|128,1,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_SwitchType , 26, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR8mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
- 26, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
- 26, MVT::i32,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 32,
OPC_MoveParent,
- OPC_MoveChild, 2,
+ OPC_MoveChild, 1,
OPC_CheckSame, 3,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
- 26, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
+ OPC_CheckType, MVT::i32,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
- 0,
- 0,
- 47|128,5, ISD::SHL,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 46,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckAndImm, 31,
- OPC_RecordChild0,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL8mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
- 44,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckAndImm, 31,
- OPC_RecordChild0,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL16mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
- 44,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckAndImm, 31,
- OPC_RecordChild0,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL32mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
- 81,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_Scope, 35,
- OPC_CheckAndImm, 63,
- OPC_RecordChild0,
OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL64mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
- 31,
- OPC_CheckInteger, 1,
- OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_CheckType, MVT::i8,
+ OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL8m1), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 0,
- 40,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 1,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL16m1), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 40,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 1,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL32m1), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 83,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_Scope, 33,
+ OPC_EmitCopyToReg, 4, X86::ECX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 5,
+ 79,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
OPC_MoveChild, 1,
- OPC_CheckInteger, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_RecordChild0,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::i16,
OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL64m1), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 37,
- OPC_RecordChild1,
OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 16,
OPC_MoveParent,
- OPC_CheckType, MVT::i8,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 3,
OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
+ OPC_CheckType, MVT::i16,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL8mi), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 4, 5, 6, 7, 8, 9,
- 0,
- 44,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL16mi), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 4, 5, 6, 7, 8, 9,
- 44,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL32mi), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 4, 5, 6, 7, 8, 9,
- 81,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_Scope, 36,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL64mi), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 4, 5, 6, 7, 8, 9,
- 31,
- OPC_CheckChild1Type, MVT::i8,
- OPC_CheckType, MVT::i8,
+ OPC_CheckType, MVT::i16,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL8mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
+ OPC_EmitCopyToReg, 4, X86::CX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 5,
0,
- 39,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i8,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL16mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
- 39,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i8,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL32mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
- 41,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i8,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL64mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
- 0,
- 47|128,5, ISD::SRL,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 46,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckAndImm, 31,
+ 39|128,1,
OPC_RecordChild0,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR8mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
- 44,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckAndImm, 31,
- OPC_RecordChild0,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR16mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
- 44,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckAndImm, 31,
- OPC_RecordChild0,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR32mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
- 81,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
OPC_MoveChild, 1,
- OPC_Scope, 35,
- OPC_CheckAndImm, 63,
- OPC_RecordChild0,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_Scope, 76,
+ OPC_CheckInteger, 32,
OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
+ OPC_RecordChild1,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR64mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
- 31,
- OPC_CheckInteger, 1,
OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR8m1), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 0,
- 40,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 1,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR16m1), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 40,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 1,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR32m1), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 83,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_Scope, 33,
OPC_MoveChild, 1,
- OPC_CheckInteger, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_MoveChild, 2,
- OPC_CheckSame, 2,
+ OPC_CheckSame, 5,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/5,
+ OPC_EmitMergeInputChains, 2, 0, 4,
+ OPC_EmitCopyToReg, 3, X86::ECX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 1,
+ 76,
+ OPC_CheckInteger, 16,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR64m1), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 37,
OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
OPC_MoveParent,
OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR8mi), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 4, 5, 6, 7, 8, 9,
- 0,
- 44,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR16mi), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 4, 5, 6, 7, 8, 9,
- 44,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR32mi), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 4, 5, 6, 7, 8, 9,
- 81,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_Scope, 36,
OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 6,
OPC_MoveParent,
- OPC_MoveChild, 2,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_MoveChild, 0,
OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR64mi), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 4, 5, 6, 7, 8, 9,
- 31,
- OPC_CheckChild1Type, MVT::i8,
OPC_CheckType, MVT::i8,
OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
OPC_MoveChild, 2,
- OPC_CheckSame, 2,
+ OPC_CheckSame, 5,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR8mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/5,
+ OPC_EmitMergeInputChains, 2, 0, 4,
+ OPC_EmitCopyToReg, 3, X86::CX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 1,
0,
- 39,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i8,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR16mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
- 39,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i8,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR32mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
- 41,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i8,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR64mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
- 0,
- 47|128,5, ISD::SRA,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 46,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckAndImm, 31,
- OPC_RecordChild0,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR8mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
- 44,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckAndImm, 31,
- OPC_RecordChild0,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR16mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
- 44,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckAndImm, 31,
- OPC_RecordChild0,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR32mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
- 81,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
+ 16|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_Scope, 35,
- OPC_CheckAndImm, 63,
- OPC_RecordChild0,
- OPC_CheckType, MVT::i8,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 65,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
- OPC_CheckType, MVT::i64,
+ OPC_RecordChild1,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 32,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR64mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
- 31,
- OPC_CheckInteger, 1,
- OPC_CheckType, MVT::i8,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 3,
OPC_MoveParent,
OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR8m1), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 0,
- 40,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 1,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR16m1), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 40,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 1,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR32m1), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 83,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_Scope, 33,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 1,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
+ OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR64m1), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 37,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
+ OPC_EmitCopyToReg, 4, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 5,
+ 65,
+ OPC_CheckPredicate, 6,
OPC_MoveParent,
- OPC_CheckType, MVT::i8,
+ OPC_RecordChild1,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 16,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR8mi), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 4, 5, 6, 7, 8, 9,
- 0,
- 44,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR16mi), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 4, 5, 6, 7, 8, 9,
- 44,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR32mi), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 4, 5, 6, 7, 8, 9,
- 81,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_Scope, 36,
OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_CheckType, MVT::i64,
OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR64mi), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 4, 5, 6, 7, 8, 9,
- 31,
- OPC_CheckChild1Type, MVT::i8,
- OPC_CheckType, MVT::i8,
+ OPC_CheckType, MVT::i16,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR8mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
+ OPC_EmitCopyToReg, 4, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 5,
0,
- 39,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i8,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR16mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
- 39,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i8,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR32mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
- 41,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i8,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR64mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
- 0,
- 62|128,4, ISD::SUB,
- OPC_MoveChild, 0,
- OPC_Scope, 27|128,1,
- OPC_CheckInteger, 0,
- OPC_MoveParent,
+ 15|128,1,
+ OPC_RecordChild0,
OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 36,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_Scope, 66,
+ OPC_CheckInteger, 32,
OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild1,
OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::NEG8m), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 3, 4, 5, 6, 7,
- 34,
- OPC_CheckPredicate, 6,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
+ OPC_MoveChild, 1,
OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::NEG16m), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 3, 4, 5, 6, 7,
- 34,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_MoveChild, 2,
- OPC_CheckSame, 2,
+ OPC_CheckSame, 5,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::NEG32m), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 3, 4, 5, 6, 7,
- 36,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/5,
+ OPC_EmitMergeInputChains, 2, 0, 4,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 1,
+ 66,
+ OPC_CheckInteger, 16,
OPC_MoveParent,
- OPC_CheckType, MVT::i64,
+ OPC_RecordChild1,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::NEG64m), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 3, 4, 5, 6, 7,
- 0,
- 27|128,3,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 64|128,1,
- OPC_CheckPredicate, 9,
- OPC_Scope, 14|128,1,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_Scope, 95,
- OPC_CheckPredicate, 11,
- OPC_MoveParent,
- OPC_SwitchType , 28, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16mi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 28, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32mi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 28, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64mi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 0,
- 33,
- OPC_CheckPredicate, 12,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64mi32), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 0,
- 43,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB8mi), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 0,
- 43,
- OPC_CheckPredicate, 6,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 6,
OPC_MoveParent,
- OPC_RecordChild1,
OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
OPC_MoveParent,
OPC_CheckType, MVT::i16,
OPC_MoveParent,
OPC_MoveChild, 2,
- OPC_CheckSame, 2,
+ OPC_CheckSame, 5,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16mi), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 43,
+ OPC_CheckPredicate, 4,
OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/5,
+ OPC_EmitMergeInputChains, 2, 0, 4,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 1,
+ 0,
+ 72|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 61,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
OPC_MoveParent,
+ OPC_CheckPredicate, 7,
OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32mi), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 122,
- OPC_CheckPredicate, 9,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 4, 10,
+ 61,
+ OPC_CheckPredicate, 6,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_SwitchType , 26, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB8mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 26, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 26, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 26, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 0,
- 0,
- 0,
- 100|128,5, ISD::XOR,
- OPC_Scope, 94|128,4,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 49,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
OPC_MoveChild, 1,
- OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
- OPC_MoveParent,
+ OPC_CheckOpcode, ISD::Constant,
OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::NOT8m), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 47,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_MoveChild, 1,
- OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
OPC_MoveParent,
+ OPC_CheckPredicate, 7,
OPC_CheckType, MVT::i16,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::NOT16m), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 47,
+ OPC_CheckPredicate, 4,
OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::NOT32m), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 111|128,1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 4, 10,
+ 63,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_Scope, 47,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::NOT64m), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 105,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckPredicate, 11,
- OPC_MoveParent,
- OPC_SwitchType , 28, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16mi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 28, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32mi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 28, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64mi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 0,
- 80,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_Scope, 33,
- OPC_CheckPredicate, 12,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64mi32), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 31,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR8mi), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 0,
- 0,
- 43,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16mi), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 43,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
- OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 7,
+ OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32mi), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 122,
- OPC_CheckPredicate, 9,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_SwitchType , 26, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR8mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 26, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 26, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 26, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD64mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 4, 10,
0,
- 0|128,1,
+ 46|128,1,
OPC_RecordChild0,
OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
- OPC_MoveParent,
- OPC_SwitchType , 26, MVT::i8,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 48,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR8mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
- 26, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 10,
+ OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 3,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/3,
OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
- 26, MVT::i32,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 1, 10,
+ 48,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 10,
+ OPC_CheckType, MVT::i16,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 3,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/3,
OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
- 26, MVT::i64,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 1, 10,
+ 50,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 10,
+ OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 3,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/3,
OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD64mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 1, 10,
0,
0,
- 27|128,10, ISD::ADD,
- OPC_Scope, 21|128,9,
+ 118|128,7, ISD::SHL,
+ OPC_Scope, 44|128,1,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 41,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 79,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_MoveChild, 1,
- OPC_CheckInteger, 1,
- OPC_MoveParent,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_RecordChild0,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::i32,
OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::INC8m), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 3, 4, 5, 6, 7,
- 41,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_MoveChild, 1,
- OPC_CheckInteger, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 32,
OPC_MoveParent,
- OPC_CheckType, MVT::i16,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 3,
OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
+ OPC_CheckType, MVT::i32,
OPC_MoveParent,
- OPC_CheckPatternPredicate, 2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::INC16m), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 3, 4, 5, 6, 7,
- 41,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 1,
OPC_MoveParent,
OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckPatternPredicate, 2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::INC32m), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 3, 4, 5, 6, 7,
- 50,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_EmitCopyToReg, 4, X86::ECX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 5,
+ 79,
+ OPC_CheckPredicate, 6,
OPC_MoveParent,
OPC_MoveChild, 1,
- OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
- OPC_MoveParent,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_RecordChild0,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::i16,
OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC8m), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 3, 4, 5, 6, 7,
- 50,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 16,
OPC_MoveParent,
OPC_MoveChild, 1,
- OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_CheckSame, 3,
OPC_MoveParent,
OPC_CheckType, MVT::i16,
OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckPatternPredicate, 2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC16m), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 3, 4, 5, 6, 7,
- 50,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
OPC_MoveParent,
- OPC_CheckType, MVT::i32,
+ OPC_CheckType, MVT::i16,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckPatternPredicate, 2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC32m), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 3, 4, 5, 6, 7,
- 84,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
+ OPC_EmitCopyToReg, 4, X86::CX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 5,
+ 0,
+ 39|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_Scope, 76,
+ OPC_CheckInteger, 32,
+ OPC_MoveParent,
+ OPC_RecordChild1,
OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
OPC_MoveParent,
OPC_MoveChild, 1,
- OPC_Scope, 30,
- OPC_CheckInteger, 1,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::INC64m), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 3, 4, 5, 6, 7,
- 39,
- OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC64m), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 3, 4, 5, 6, 7,
- 0,
- 41,
- OPC_CheckPredicate, 6,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_MoveChild, 1,
- OPC_CheckInteger, 1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_MoveChild, 2,
- OPC_CheckSame, 2,
+ OPC_CheckSame, 5,
OPC_MoveParent,
- OPC_CheckPatternPredicate, 3,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::INC64_16m), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 3, 4, 5, 6, 7,
- 41,
+ OPC_CheckPredicate, 4,
OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/5,
+ OPC_EmitMergeInputChains, 2, 0, 4,
+ OPC_EmitCopyToReg, 3, X86::ECX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 1,
+ 76,
+ OPC_CheckInteger, 16,
OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 1,
+ OPC_RecordChild1,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
OPC_MoveParent,
- OPC_CheckType, MVT::i32,
+ OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckPatternPredicate, 3,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::INC64_32m), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 3, 4, 5, 6, 7,
- 50,
- OPC_CheckPredicate, 6,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 6,
OPC_MoveParent,
OPC_MoveChild, 1,
- OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_CheckOpcode, ISD::TRUNCATE,
+ OPC_MoveChild, 0,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
OPC_MoveParent,
OPC_CheckType, MVT::i16,
OPC_MoveParent,
OPC_MoveChild, 2,
- OPC_CheckSame, 2,
+ OPC_CheckSame, 5,
OPC_MoveParent,
- OPC_CheckPatternPredicate, 3,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC64_16m), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 3, 4, 5, 6, 7,
- 50,
+ OPC_CheckPredicate, 4,
OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/5,
+ OPC_EmitMergeInputChains, 2, 0, 4,
+ OPC_EmitCopyToReg, 3, X86::CX,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 1,
+ 0,
+ 16|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 65,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
OPC_MoveParent,
OPC_MoveChild, 1,
- OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
OPC_MoveParent,
OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckPatternPredicate, 3,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC64_32m), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 3, 4, 5, 6, 7,
- 52,
+ OPC_EmitCopyToReg, 4, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 5,
+ 65,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
+ OPC_MoveParent,
OPC_RecordChild1,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
OPC_MoveParent,
OPC_MoveChild, 1,
- OPC_CheckInteger, 0|128,1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckInteger, 16,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
OPC_MoveParent,
OPC_CheckType, MVT::i16,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitInteger, MVT::i16, 0|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16mi8), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 8,
- 52,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 0|128,1,
+ OPC_EmitCopyToReg, 4, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 5,
+ 0,
+ 15|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_Scope, 66,
+ OPC_CheckInteger, 32,
OPC_MoveParent,
- OPC_CheckType, MVT::i32,
+ OPC_RecordChild1,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitInteger, MVT::i32, 0|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32mi8), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 8,
- 40|128,2,
- OPC_CheckPredicate, 9,
- OPC_Scope, 103,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_Scope, 43,
- OPC_CheckInteger, 0|128,1,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitInteger, MVT::i64, 0|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64mi8), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 8,
- 47,
- OPC_CheckInteger, 0|128,0|128,0|128,0|128,0|128,1,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitInteger, MVT::i64, 0|128,0|128,0|128,0|128,120|128,127|128,127|128,127|128,127|128,1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64mi32), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 8,
- 0,
- 14|128,1,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_Scope, 95,
- OPC_CheckPredicate, 11,
- OPC_MoveParent,
- OPC_SwitchType , 28, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16mi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 28, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32mi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 28, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64mi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 0,
- 33,
- OPC_CheckPredicate, 12,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64mi32), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 0,
- 43,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8mi), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 0,
- 43,
- OPC_CheckPredicate, 6,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
- OPC_RecordChild1,
OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_MoveChild, 2,
- OPC_CheckSame, 2,
+ OPC_CheckSame, 5,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16mi), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 43,
+ OPC_CheckPredicate, 4,
OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/5,
+ OPC_EmitMergeInputChains, 2, 0, 4,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 1,
+ 66,
+ OPC_CheckInteger, 16,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_CheckType, MVT::i32,
OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32mi), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 122,
- OPC_CheckPredicate, 9,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 6,
OPC_MoveParent,
- OPC_RecordChild1,
- OPC_SwitchType , 26, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 26, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 26, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 26, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 0,
- 0,
- 0|128,1,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_SwitchType , 26, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
- 26, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
- 26, MVT::i32,
+ OPC_MoveChild, 1,
+ OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
- 26, MVT::i64,
+ OPC_CheckType, MVT::i16,
OPC_MoveParent,
OPC_MoveChild, 2,
- OPC_CheckSame, 3,
+ OPC_CheckSame, 5,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/5,
+ OPC_EmitMergeInputChains, 2, 0, 4,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 6, 7, 8, 9, 10, 1,
0,
- 0,
- 127|128,3, ISD::ROTL,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 42,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 1,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL8m1), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 40,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 1,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL16m1), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 40,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 1,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL32m1), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 83,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
+ 72|128,1,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
- OPC_MoveParent,
- OPC_Scope, 33,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 1,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 61,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL64m1), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 37,
OPC_RecordChild1,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::Constant,
OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL8mi), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 4, 5, 6, 7, 8, 9,
- 0,
- 44,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL16mi), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 4, 5, 6, 7, 8, 9,
- 44,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL32mi), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 4, 5, 6, 7, 8, 9,
- 81,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_Scope, 36,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::Constant,
OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL64mi), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 4, 5, 6, 7, 8, 9,
- 31,
- OPC_CheckChild1Type, MVT::i8,
- OPC_CheckType, MVT::i8,
+ OPC_CheckPredicate, 10,
+ OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL8mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
- 0,
- 39,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i8,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL16mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
- 39,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i8,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL32mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
- 41,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i8,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL64mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
- 0,
- 127|128,3, ISD::ROTR,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 42,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 1,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR8m1), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 40,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 1,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR16m1), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 40,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 1,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR32m1), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 83,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_Scope, 33,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 1,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 4, 10,
+ 61,
+ OPC_CheckPredicate, 6,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR64m1), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 37,
OPC_RecordChild1,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::Constant,
OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR8mi), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 4, 5, 6, 7, 8, 9,
- 0,
- 44,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR16mi), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 4, 5, 6, 7, 8, 9,
- 44,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR32mi), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 4, 5, 6, 7, 8, 9,
- 81,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_Scope, 36,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::Constant,
OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR64mi), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 4, 5, 6, 7, 8, 9,
- 31,
- OPC_CheckChild1Type, MVT::i8,
- OPC_CheckType, MVT::i8,
+ OPC_CheckPredicate, 10,
+ OPC_CheckType, MVT::i16,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR8mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
- 0,
- 39,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i8,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR16mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
- 39,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i8,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR32mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
- 41,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::i8,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 3, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR64mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 4, 5, 6, 7, 8,
- 0,
- 34|128,4, ISD::AND,
- OPC_Scope, 28|128,3,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 63|128,1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 4, 10,
+ 63,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_Scope, 105,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckPredicate, 11,
- OPC_MoveParent,
- OPC_SwitchType , 28, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16mi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 28, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32mi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 28, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64mi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 0,
- 80,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_Scope, 33,
- OPC_CheckPredicate, 12,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64mi32), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 31,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8mi), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 0,
- 0,
- 43,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16mi), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 43,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
- OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 10,
+ OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32mi), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 122,
- OPC_CheckPredicate, 9,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_SwitchType , 26, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 26, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 26, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 26, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD64mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 4, 10,
0,
- 0|128,1,
+ 46|128,1,
OPC_RecordChild0,
OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
- OPC_MoveParent,
- OPC_SwitchType , 26, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
- 26, MVT::i16,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 48,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
- 26, MVT::i32,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
- 26, MVT::i64,
+ OPC_CheckPredicate, 7,
+ OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 3,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/3,
OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
- 0,
- 0,
- 68|128,4, ISD::ADDE,
- OPC_RecordNode,
- OPC_CaptureFlagInput,
- OPC_Scope, 52|128,3,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 74|128,1,
- OPC_CheckPredicate, 9,
- OPC_Scope, 22|128,1,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_Scope, 101,
- OPC_CheckPredicate, 11,
- OPC_MoveParent,
- OPC_SwitchType , 30, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_EmitConvertToTarget, 4,
- OPC_MarkFlagResults, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC16mi8), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 10,
- 30, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_EmitConvertToTarget, 4,
- OPC_MarkFlagResults, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC32mi8), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 10,
- 30, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_EmitConvertToTarget, 4,
- OPC_MarkFlagResults, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC64mi8), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 10,
- 0,
- 35,
- OPC_CheckPredicate, 12,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_EmitConvertToTarget, 4,
- OPC_MarkFlagResults, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC64mi32), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 10,
- 0,
- 45,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_EmitConvertToTarget, 4,
- OPC_MarkFlagResults, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC8mi), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 10,
- 0,
- 45,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 1, 10,
+ 48,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
OPC_MoveParent,
+ OPC_CheckPredicate, 7,
OPC_CheckType, MVT::i16,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 3,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/3,
OPC_EmitMergeInputChains, 2, 0, 2,
OPC_EmitConvertToTarget, 4,
- OPC_MarkFlagResults, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC16mi), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 10,
- 45,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 1, 10,
+ 50,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 7,
+ OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 3,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/3,
OPC_EmitMergeInputChains, 2, 0, 2,
OPC_EmitConvertToTarget, 4,
- OPC_MarkFlagResults, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC32mi), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 10,
- 2|128,1,
- OPC_CheckPredicate, 9,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD64mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 1, 10,
+ 0,
+ 0,
+ 53|128,3, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 75|128,1,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 113,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_SwitchType , 28, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MarkFlagResults, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC8mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 4,
- 28, MVT::i16,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 32, MVT::i16,
OPC_MoveParent,
OPC_MoveChild, 2,
- OPC_CheckSame, 3,
+ OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MarkFlagResults, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC16mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 4,
- 28, MVT::i32,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 32, MVT::i32,
OPC_MoveParent,
OPC_MoveChild, 2,
- OPC_CheckSame, 3,
+ OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MarkFlagResults, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC32mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 4,
- 28, MVT::i64,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 32, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 2,
- OPC_CheckSame, 3,
+ OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MarkFlagResults, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC64mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 4,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
0,
- 0,
- 8|128,1,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_SwitchType , 28, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 4,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/4,
- OPC_EmitMergeInputChains, 2, 0, 3,
- OPC_MarkFlagResults, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC8mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 2,
- 28, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 4,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/4,
- OPC_EmitMergeInputChains, 2, 0, 3,
- OPC_MarkFlagResults, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC16mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 2,
- 28, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 4,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/4,
- OPC_EmitMergeInputChains, 2, 0, 3,
- OPC_MarkFlagResults, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC32mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 2,
- 28, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 4,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/4,
- OPC_EmitMergeInputChains, 2, 0, 3,
- OPC_MarkFlagResults, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC64mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 2,
- 0,
- 0,
- 54|128,3, ISD::SUBE,
- OPC_RecordNode,
- OPC_CaptureFlagInput,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 74|128,1,
- OPC_CheckPredicate, 9,
- OPC_Scope, 22|128,1,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 84,
+ OPC_CheckPredicate, 9,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::Constant,
- OPC_Scope, 101,
- OPC_CheckPredicate, 11,
- OPC_MoveParent,
- OPC_SwitchType , 30, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_EmitConvertToTarget, 4,
- OPC_MarkFlagResults, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB16mi8), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 10,
- 30, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_EmitConvertToTarget, 4,
- OPC_MarkFlagResults, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB32mi8), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 10,
- 30, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_EmitConvertToTarget, 4,
- OPC_MarkFlagResults, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB64mi8), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 10,
- 0,
- 35,
+ OPC_Scope, 37,
OPC_CheckPredicate, 12,
OPC_MoveParent,
OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 2,
- OPC_CheckSame, 3,
+ OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_EmitConvertToTarget, 4,
- OPC_MarkFlagResults, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB64mi32), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 10,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 35,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
0,
- 45,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_EmitConvertToTarget, 4,
- OPC_MarkFlagResults, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB8mi), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 10,
0,
- 45,
+ 43,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 1,
@@ -5427,20 +2094,17 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckType, MVT::i16,
OPC_MoveParent,
OPC_MoveChild, 2,
- OPC_CheckSame, 3,
+ OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_EmitConvertToTarget, 4,
- OPC_MarkFlagResults, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB16mi), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 10,
- 45,
+ OPC_CheckPredicate, 4,
OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 43,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 1,
@@ -5449,422 +2113,1437 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_MoveChild, 2,
- OPC_CheckSame, 3,
+ OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_EmitConvertToTarget, 4,
- OPC_MarkFlagResults, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB32mi), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 10,
- 2|128,1,
- OPC_CheckPredicate, 9,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 6|128,1,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_SwitchType , 28, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MarkFlagResults, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB8mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 4,
- 28, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MarkFlagResults, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB16mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 4,
- 28, MVT::i32,
+ OPC_SwitchType , 30, MVT::i8,
OPC_MoveParent,
OPC_MoveChild, 2,
- OPC_CheckSame, 3,
+ OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MarkFlagResults, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB32mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 4,
- 28, MVT::i64,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 30, MVT::i16,
OPC_MoveParent,
OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MarkFlagResults, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB64mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 4,
- 0,
- 0,
- 108|128,4, X86ISD::ADD,
- OPC_Scope, 73|128,3,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 45,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckPredicate, 11,
+ OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckType, MVT::i16,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 30, MVT::i32,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16mi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 45,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckPredicate, 11,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 30, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32mi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 116,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 0,
+ 0,
+ 0,
+ 16|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_MoveParent,
+ OPC_SwitchType , 30, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 30, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 30, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 30, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 0,
+ 0,
+ 61|128,5, ISD::SHL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 46,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 31,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL8mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 44,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 31,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL16mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 44,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 31,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL32mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 83,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_Scope, 37,
+ OPC_CheckAndImm, 63,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL64mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 33,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL8m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 0,
+ 40,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL16m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 40,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL32m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 87,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_Scope, 37,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL64m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 41,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 44,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 44,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 85,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 40,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL64mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 35,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL8mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 0,
+ 39,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL16mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 39,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL32mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 41,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL64mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 0,
+ 61|128,5, ISD::SRL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 46,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 31,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR8mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 44,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 31,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR16mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 44,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 31,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR32mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 83,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_Scope, 37,
+ OPC_CheckAndImm, 63,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR64mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 33,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR8m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 0,
+ 40,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR16m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 40,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR32m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 87,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_Scope, 37,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR64m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 41,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 44,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 44,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 85,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 40,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR64mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 35,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR8mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 0,
+ 39,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR16mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 39,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR32mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 41,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR64mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 0,
+ 61|128,5, ISD::SRA,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 46,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 31,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR8mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 44,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 31,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR16mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 44,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckAndImm, 31,
+ OPC_RecordChild0,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR32mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 83,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_Scope, 37,
+ OPC_CheckAndImm, 63,
+ OPC_RecordChild0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR64mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 33,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR8m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 0,
+ 40,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR16m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 40,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR32m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 87,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_Scope, 37,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR64m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 41,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 44,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 44,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 85,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 40,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR64mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 35,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR8mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 0,
+ 39,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR16mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 39,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR32mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 41,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR64mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 0,
+ 95|128,4, ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_Scope, 31|128,1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 36,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::NEG8m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 34,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::NEG16m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 34,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::NEG32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 36,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::NEG64m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 0,
+ 56|128,3,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 76|128,1,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 26|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 107,
+ OPC_CheckPredicate, 11,
OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_Scope, 33,
- OPC_CheckPredicate, 11,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
+ OPC_SwitchType , 32, MVT::i16,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16mi8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 33,
- OPC_CheckPredicate, 12,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
+ 32, MVT::i32,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32mi8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 31,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
+ 32, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64mi8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
0,
- 43,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
+ 37,
+ OPC_CheckPredicate, 12,
OPC_MoveParent,
- OPC_CheckType, MVT::i16,
+ OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16mi), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 43,
+ OPC_CheckPredicate, 4,
OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64mi32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 38,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 36,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 36,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 38,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 0,
- 29|128,1,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 37,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
- 35,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
- 35,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
- 37,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
0,
- 0,
- 73|128,3, X86ISD::SUB,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 45,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 43,
+ OPC_CheckPredicate, 9,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::Constant,
- OPC_CheckPredicate, 11,
OPC_MoveParent,
- OPC_CheckType, MVT::i16,
+ OPC_CheckType, MVT::i8,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB8mi), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 45,
+ 0,
+ 43,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 43,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 6|128,1,
+ OPC_CheckPredicate, 8,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 30, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 30, MVT::i16,
OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckPredicate, 11,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckType, MVT::i32,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 30, MVT::i32,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32mi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 116,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 30, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 0,
+ 0,
+ 0,
+ 17|128,6, ISD::XOR,
+ OPC_Scope, 123|128,4,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 49,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::NOT8m), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 47,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::NOT16m), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 47,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::NOT32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 123|128,1,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 47,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::NOT64m), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 113,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::Constant,
- OPC_Scope, 33,
- OPC_CheckPredicate, 11,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 32, MVT::i16,
OPC_MoveParent,
- OPC_CheckType, MVT::i64,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 32, MVT::i32,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32mi8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 33,
+ 32, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 84,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 37,
OPC_CheckPredicate, 12,
OPC_MoveParent,
OPC_CheckType, MVT::i64,
@@ -5872,1798 +3551,2979 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64mi32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 31,
+ 35,
OPC_MoveParent,
OPC_CheckType, MVT::i8,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR8mi), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
0,
- 43,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
+ 0,
+ 43,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 43,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 6|128,1,
+ OPC_CheckPredicate, 8,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 30, MVT::i8,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16mi), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 43,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 30, MVT::i16,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32mi), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 38,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 30, MVT::i32,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32mr), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 36,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i16,
+ 30, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64mr), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 36,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 0,
+ 0,
+ 16|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_MoveParent,
+ OPC_SwitchType , 30, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 30, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 30, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 30, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 0,
+ 0,
+ 80|128,10, ISD::ADD,
+ OPC_Scope, 58|128,9,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 41,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC8m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 41,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC16m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 41,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 50,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC8m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 50,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC16m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 50,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 88,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_Scope, 34,
+ OPC_CheckInteger, 1,
OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
+ OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 38,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC64m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 43,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
OPC_MoveParent,
- OPC_RecordChild1,
OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC64m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
0,
- 108|128,4, X86ISD::OR,
- OPC_Scope, 73|128,3,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 45,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckPredicate, 11,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16mi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 45,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckPredicate, 11,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32mi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 116,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_Scope, 33,
- OPC_CheckPredicate, 11,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64mi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 33,
- OPC_CheckPredicate, 12,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64mi32), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 31,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR8mi), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 0,
- 43,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16mi), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 43,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32mi), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 38,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR8mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 36,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 41,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC64_16m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 41,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC64_32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 50,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC64_16m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 50,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC64_32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 52,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitInteger, MVT::i16, 0|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 8,
+ 52,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0|128,1,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitInteger, MVT::i32, 0|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 8,
+ 56|128,2,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 107,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_Scope, 47,
+ OPC_CheckInteger, 0|128,1,
OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i16,
+ OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 36,
+ OPC_CheckPredicate, 4,
OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 38,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_EmitInteger, MVT::i64, 0|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,127|128,1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 8,
+ 51,
+ OPC_CheckInteger, 0|128,0|128,0|128,0|128,0|128,1,
OPC_MoveParent,
- OPC_RecordChild1,
OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ OPC_EmitInteger, MVT::i64, 0|128,0|128,0|128,0|128,120|128,127|128,127|128,127|128,127|128,1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 8,
0,
- 29|128,1,
- OPC_RecordChild0,
+ 26|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 37,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR8mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
- 35,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
- 35,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
- 37,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
- 0,
- 0,
- 108|128,4, X86ISD::XOR,
- OPC_Scope, 73|128,3,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 45,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckPredicate, 11,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16mi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 45,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 107,
OPC_CheckPredicate, 11,
OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32mi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 116,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_Scope, 33,
- OPC_CheckPredicate, 11,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
+ OPC_SwitchType , 32, MVT::i16,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16mi8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 33,
- OPC_CheckPredicate, 12,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
+ 32, MVT::i32,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32mi8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 31,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
+ 32, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64mi8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
0,
- 43,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
+ 37,
+ OPC_CheckPredicate, 12,
OPC_MoveParent,
- OPC_CheckType, MVT::i16,
+ OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16mi), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 43,
+ OPC_CheckPredicate, 4,
OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64mi32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 38,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR8mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 36,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 36,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 38,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
0,
- 29|128,1,
- OPC_RecordChild0,
+ 43,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::LOAD,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
OPC_CheckPredicate, 4,
- OPC_Scope, 37,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR8mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
- 35,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
- 35,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
- 37,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
- 0,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
0,
- 108|128,4, X86ISD::AND,
- OPC_Scope, 73|128,3,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
+ 43,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 43,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 6|128,1,
+ OPC_CheckPredicate, 8,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 30, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
OPC_CheckPredicate, 4,
- OPC_Scope, 45,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckPredicate, 11,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 30, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 30, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 30, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 0,
+ 0,
+ 16|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_MoveParent,
+ OPC_SwitchType , 30, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 30, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 30, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 30, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 0,
+ 0,
+ 11|128,4, ISD::ROTL,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 42,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL8m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 40,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL16m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 40,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL32m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 87,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_Scope, 37,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL64m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 41,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 44,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 44,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 85,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 40,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL64mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 35,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL8mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 0,
+ 39,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL16mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 39,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL32mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 41,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROL64mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 0,
+ 11|128,4, ISD::ROTR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 42,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR8m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 40,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR16m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 40,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR32m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 87,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_Scope, 37,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR64m1), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 41,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 44,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 44,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 85,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_Scope, 40,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR64mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 9,
+ 35,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR8mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 0,
+ 39,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR16mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 39,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR32mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 41,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 3, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ROR64mCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 4, 5, 6, 7, 8,
+ 0,
+ 79|128,4, ISD::AND,
+ OPC_Scope, 57|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 75|128,1,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 113,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 32, MVT::i16,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
OPC_EmitConvertToTarget, 3,
OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16mi8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 45,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckPredicate, 11,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
+ 32, MVT::i32,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
OPC_EmitConvertToTarget, 3,
OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32mi8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 116,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_Scope, 33,
- OPC_CheckPredicate, 11,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64mi8), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 33,
- OPC_CheckPredicate, 12,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64mi32), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 31,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8mi), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 0,
- 43,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
+ 32, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16mi), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 43,
+ OPC_CheckPredicate, 4,
OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
OPC_EmitConvertToTarget, 3,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64mi8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
- 38,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 36,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 36,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
- 38,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
0,
- 29|128,1,
- OPC_RecordChild0,
+ 84,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
+ OPC_CheckOpcode, ISD::Constant,
OPC_Scope, 37,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
- 35,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
- 35,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
- 37,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_CheckPredicate, 12,
OPC_MoveParent,
OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 2,
- OPC_CheckSame, 3,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 2, 0, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64mr), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
- 0,
- 0,
- 19|128,1, ISD::VECTOR_SHUFFLE,
- OPC_CheckPredicate, 13,
- OPC_MoveChild, 0,
- OPC_SwitchOpcode , 44, ISD::BIT_CONVERT,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v2i64,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v4i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPSmr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 4, 5, 6, 7, 8, 3,
- 93, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_SwitchType , 25, MVT::v4f32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPSmr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 4, 5, 6, 7, 8, 3,
- 25, MVT::v2f64,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 35,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPDmr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 4, 5, 6, 7, 8, 3,
- 25, MVT::v2i64,
+ OPC_CheckType, MVT::i8,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPDmr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 4, 5, 6, 7, 8, 3,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
0,
0,
- 23|128,2, X86ISD::SHLD,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
+ 43,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
OPC_CheckPredicate, 4,
- OPC_Scope, 46,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_MoveChild, 2,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 4,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32mri8), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 7, 5, 6, 7, 8, 9, 3, 10,
- 46,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_MoveChild, 2,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 43,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 6|128,1,
+ OPC_CheckPredicate, 8,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 30, MVT::i8,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 4,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16mri8), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 7, 5, 6, 7, 8, 9, 3, 10,
- 48,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_MoveChild, 2,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 30, MVT::i16,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 4,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD64mri8), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 7, 5, 6, 7, 8, 9, 3, 10,
- 41,
+ OPC_CheckPredicate, 4,
OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::i8,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 4, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 3,
- 41,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::i8,
- OPC_CheckType, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 30, MVT::i32,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 4, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 3,
- 43,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::i8,
- OPC_CheckType, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 30, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 4, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD64mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
0,
- 23|128,2, X86ISD::SHRD,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
+ 0,
+ 16|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_MoveParent,
+ OPC_SwitchType , 30, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
OPC_CheckPredicate, 4,
- OPC_Scope, 46,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 30, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 30, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 30, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 0,
+ 0,
+ 112|128,4, ISD::ADDE,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_Scope, 80|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 86|128,1,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 34|128,1,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_MoveChild, 2,
+ OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 4,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32mri8), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 7, 5, 6, 7, 8, 9, 3, 10,
- 46,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_Scope, 113,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 34, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC16mi8), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 10,
+ 34, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC32mi8), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 10,
+ 34, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC64mi8), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 10,
+ 0,
+ 39,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC64mi32), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 10,
+ 0,
+ 45,
+ OPC_CheckPredicate, 9,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_MoveChild, 2,
+ OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_CheckType, MVT::i16,
+ OPC_CheckType, MVT::i8,
OPC_MoveParent,
OPC_MoveChild, 2,
- OPC_CheckSame, 2,
+ OPC_CheckSame, 3,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
OPC_EmitConvertToTarget, 4,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16mri8), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 7, 5, 6, 7, 8, 9, 3, 10,
- 48,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC8mi), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 10,
+ 0,
+ 45,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC16mi), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 10,
+ 45,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC32mi), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 10,
+ 14|128,1,
+ OPC_CheckPredicate, 8,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 32, MVT::i8,
OPC_MoveParent,
- OPC_RecordChild1,
- OPC_RecordChild2,
OPC_MoveChild, 2,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
+ OPC_CheckSame, 3,
OPC_MoveParent,
- OPC_CheckType, MVT::i64,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC8mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 4,
+ 32, MVT::i16,
OPC_MoveParent,
OPC_MoveChild, 2,
- OPC_CheckSame, 2,
+ OPC_CheckSame, 3,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitConvertToTarget, 4,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD64mri8), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 7, 5, 6, 7, 8, 9, 3, 10,
- 41,
+ OPC_CheckPredicate, 4,
OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::i8,
- OPC_CheckType, MVT::i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC16mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 4,
+ 32, MVT::i32,
OPC_MoveParent,
OPC_MoveChild, 2,
- OPC_CheckSame, 2,
- OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 4, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 3,
- 41,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_CheckSame, 3,
OPC_MoveParent,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::i8,
- OPC_CheckType, MVT::i16,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC32mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 4,
+ 32, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 2,
- OPC_CheckSame, 2,
+ OPC_CheckSame, 3,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 4, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 3,
- 43,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC64mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 4,
+ 0,
+ 0,
+ 24|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_MoveParent,
+ OPC_SwitchType , 32, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 4,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/4,
+ OPC_EmitMergeInputChains, 2, 0, 3,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC8mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 2,
+ 32, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 4,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/4,
+ OPC_EmitMergeInputChains, 2, 0, 3,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC16mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 2,
+ 32, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 4,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/4,
+ OPC_EmitMergeInputChains, 2, 0, 3,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC32mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 2,
+ 32, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 4,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/4,
+ OPC_EmitMergeInputChains, 2, 0, 3,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADC64mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 2,
+ 0,
+ 0,
+ 82|128,3, ISD::SUBE,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 86|128,1,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 34|128,1,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 113,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_SwitchType , 34, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB16mi8), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 10,
+ 34, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB32mi8), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 10,
+ 34, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB64mi8), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 10,
+ 0,
+ 39,
+ OPC_CheckPredicate, 12,
OPC_MoveParent,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckChild2Type, MVT::i8,
OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 2,
- OPC_CheckSame, 2,
+ OPC_CheckSame, 3,
OPC_MoveParent,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_EmitCopyToReg, 4, X86::CL,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD64mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 6, 5, 6, 7, 8, 9, 3,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB64mi32), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 10,
0,
- 114|128,1, X86ISD::INC,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
+ 45,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
OPC_CheckPredicate, 4,
- OPC_Scope, 38,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i8,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB8mi), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 10,
+ 0,
+ 45,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB16mi), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 10,
+ 45,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB32mi), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 10,
+ 14|128,1,
+ OPC_CheckPredicate, 8,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_SwitchType , 32, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB8mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 4,
+ 32, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB16mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 4,
+ 32, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB32mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 4,
+ 32, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MarkFlagResults, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SBB64mr), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 4,
+ 0,
+ 0,
+ 124|128,4, X86ISD::ADD,
+ OPC_Scope, 85|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 45,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 45,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 124,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 37,
+ OPC_CheckPredicate, 11,
OPC_MoveParent,
- OPC_CheckType, MVT::i8,
+ OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::INC8m), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 3, 4, 5, 6, 7,
- 38,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i16,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 37,
+ OPC_CheckPredicate, 12,
OPC_MoveParent,
- OPC_CheckType, MVT::i16,
+ OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckPatternPredicate, 2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::INC16m), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 3, 4, 5, 6, 7,
- 38,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 35,
OPC_MoveParent,
- OPC_CheckType, MVT::i32,
+ OPC_CheckType, MVT::i8,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckPatternPredicate, 2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::INC32m), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 3, 4, 5, 6, 7,
- 38,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i16,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 43,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 43,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 38,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 36,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 36,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 38,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 0,
+ 33|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 37,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 35,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 35,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 37,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 0,
+ 0,
+ 85|128,3, X86ISD::SUB,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 45,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 45,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 124,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 37,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 37,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 35,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 43,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 43,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 38,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 36,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 36,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 38,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 0,
+ 124|128,4, X86ISD::OR,
+ OPC_Scope, 85|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 45,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 45,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 124,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 37,
+ OPC_CheckPredicate, 11,
OPC_MoveParent,
- OPC_CheckType, MVT::i16,
+ OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckPatternPredicate, 3,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::INC64_16m), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 3, 4, 5, 6, 7,
- 38,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 37,
+ OPC_CheckPredicate, 12,
OPC_MoveParent,
- OPC_CheckType, MVT::i32,
+ OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckPatternPredicate, 3,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::INC64_32m), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 3, 4, 5, 6, 7,
- 38,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 35,
OPC_MoveParent,
- OPC_CheckType, MVT::i64,
+ OPC_CheckType, MVT::i8,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::INC64m), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
0,
- 114|128,1, X86ISD::DEC,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
+ 43,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
OPC_CheckPredicate, 4,
- OPC_Scope, 38,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i8,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 43,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 38,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 36,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 36,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 38,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 0,
+ 33|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 37,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 35,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 35,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 37,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 0,
+ 0,
+ 124|128,4, X86ISD::XOR,
+ OPC_Scope, 85|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 45,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 45,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 124,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 37,
+ OPC_CheckPredicate, 11,
OPC_MoveParent,
- OPC_CheckType, MVT::i8,
+ OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC8m), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 3, 4, 5, 6, 7,
- 38,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i16,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 37,
+ OPC_CheckPredicate, 12,
OPC_MoveParent,
- OPC_CheckType, MVT::i16,
+ OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckPatternPredicate, 2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC16m), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 3, 4, 5, 6, 7,
- 38,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 35,
OPC_MoveParent,
- OPC_CheckType, MVT::i32,
+ OPC_CheckType, MVT::i8,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckPatternPredicate, 2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC32m), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 3, 4, 5, 6, 7,
- 38,
- OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i16,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 0,
+ 43,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 43,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 38,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 36,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 36,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 38,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 0,
+ 33|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 37,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 35,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 35,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 37,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 0,
+ 0,
+ 124|128,4, X86ISD::AND,
+ OPC_Scope, 85|128,3,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 45,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 45,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckPredicate, 11,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 124,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_Scope, 37,
+ OPC_CheckPredicate, 11,
OPC_MoveParent,
- OPC_CheckType, MVT::i16,
+ OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckPatternPredicate, 3,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC64_16m), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 3, 4, 5, 6, 7,
- 38,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64mi8), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 37,
+ OPC_CheckPredicate, 12,
OPC_MoveParent,
- OPC_CheckType, MVT::i32,
+ OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_CheckPatternPredicate, 3,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC64_32m), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 3, 4, 5, 6, 7,
- 38,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 35,
OPC_MoveParent,
- OPC_CheckType, MVT::i64,
+ OPC_CheckType, MVT::i8,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckSame, 2,
OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC64m), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::i32, 5, 3, 4, 5, 6, 7,
- 0,
- 41|128,3, ISD::EXTRACT_VECTOR_ELT,
- OPC_Scope, 42|128,1,
- OPC_MoveChild, 0,
- OPC_SwitchOpcode , 89, ISD::VECTOR_SHUFFLE,
- OPC_CheckPredicate, 14,
- OPC_Scope, 45,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::BIT_CONVERT,
- OPC_RecordChild0,
- OPC_CheckChild0Type, MVT::v4f32,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_CheckType, MVT::v2f64,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 0,
- OPC_MoveParent,
- OPC_CheckType, MVT::f64,
- OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckPatternPredicate, 0,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVHPSmr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 38,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_CheckType, MVT::v2f64,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 0,
- OPC_MoveParent,
- OPC_CheckType, MVT::f64,
- OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckPatternPredicate, 1,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVHPDmr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 0,
- 73, ISD::BIT_CONVERT,
- OPC_RecordChild0,
- OPC_CheckChild0Type, MVT::v4f32,
- OPC_SwitchType , 30, MVT::v2f64,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 0,
- OPC_MoveParent,
- OPC_CheckType, MVT::f64,
- OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckPatternPredicate, 0,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPSmr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 34, MVT::v4i32,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckPatternPredicate, 4,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitConvertToTarget, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::EXTRACTPSmr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 7, 4, 5, 6, 7, 8, 1, 9,
- 0,
- 0,
- 121|128,1,
- OPC_RecordChild0,
- OPC_Scope, 65,
- OPC_CheckChild0Type, MVT::v2f64,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 0,
- OPC_MoveParent,
- OPC_CheckType, MVT::f64,
- OPC_MoveParent,
- OPC_RecordChild2,
- OPC_Scope, 20,
- OPC_CheckPatternPredicate, 1,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPDmr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 30,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 2,
- OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
- 1, MVT::f64, 2, 1, 8,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSDmr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 9,
- 0,
- 68,
- OPC_CheckChild0Type, MVT::v2i64,
- OPC_Scope, 29,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 0,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckPatternPredicate, 1,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVPQI2QImr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 33,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckPatternPredicate, 4,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitConvertToTarget, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::PEXTRQmr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 7, 4, 5, 6, 7, 8, 1, 9,
- 0,
- 68,
- OPC_CheckChild0Type, MVT::v4i32,
- OPC_Scope, 29,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 0,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckPatternPredicate, 1,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVPDI2DImr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 33,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckPatternPredicate, 4,
- OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitConvertToTarget, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::PEXTRDmr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 7, 4, 5, 6, 7, 8, 1, 9,
- 0,
- 41,
- OPC_CheckChild0Type, MVT::v4f32,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 0,
- OPC_MoveParent,
- OPC_CheckType, MVT::f32,
- OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, 1,
- OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
- 1, MVT::f32, 2, 1, 8,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSSmr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 9,
- 0,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
0,
- 41|128,1, ISD::TRUNCATE,
- OPC_CheckPredicate, 15,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SRL,
- OPC_CheckPredicate, 16,
- OPC_RecordChild0,
+ 43,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
OPC_MoveChild, 1,
- OPC_CheckInteger, 8,
- OPC_CheckType, MVT::i8,
+ OPC_CheckOpcode, ISD::Constant,
OPC_MoveParent,
- OPC_SwitchType , 47, MVT::i64,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, X86::GR64_ABCDRegClassID,
- OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
- 1, MVT::i64, 2, 1, 8,
- OPC_EmitInteger, MVT::i32, 2,
- OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
- 1, MVT::i8, 2, 9, 10,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV8mr_NOREX), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 11,
- 49, MVT::i32,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckPatternPredicate, 3,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, X86::GR32_ABCDRegClassID,
- OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
- 1, MVT::i32, 2, 1, 8,
- OPC_EmitInteger, MVT::i32, 2,
- OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
- 1, MVT::i8, 2, 9, 10,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV8mr_NOREX), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 11,
- 49, MVT::i16,
- OPC_MoveParent,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckPatternPredicate, 3,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitInteger, MVT::i32, X86::GR16_ABCDRegClassID,
- OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
- 1, MVT::i16, 2, 1, 8,
- OPC_EmitInteger, MVT::i32, 2,
- OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
- 1, MVT::i8, 2, 9, 10,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV8mr_NOREX), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 11,
- 0,
- 50, ISD::BIT_CONVERT,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::EXTRACT_VECTOR_ELT,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::BIT_CONVERT,
- OPC_RecordChild0,
- OPC_CheckChild0Type, MVT::v4f32,
- OPC_CheckType, MVT::v4i32,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 43,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 1,
@@ -7671,667 +6531,1486 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveParent,
OPC_CheckType, MVT::i32,
OPC_MoveParent,
- OPC_CheckType, MVT::f32,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckPatternPredicate, 4,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 3,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 9,
+ 38,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 36,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 36,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 38,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 3,
+ 0,
+ 33|128,1,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 37,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/3,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitConvertToTarget, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::EXTRACTPSmr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 7, 4, 5, 6, 7, 8, 1, 9,
- 52|128,3, X86ISD::SETCC,
- OPC_MoveChild, 0,
- OPC_Scope, 26,
- OPC_CheckInteger, 4,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitCopyToReg, 1, X86::EFLAGS,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SETEm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 26,
- OPC_CheckInteger, 9,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitCopyToReg, 1, X86::EFLAGS,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SETNEm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 26,
- OPC_CheckInteger, 7,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitCopyToReg, 1, X86::EFLAGS,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SETLm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 26,
- OPC_CheckInteger, 6,
- OPC_MoveParent,
- OPC_RecordChild1,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 35,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 35,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 37,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 3,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
+ OPC_EmitMergeInputChains, 2, 0, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 6, 4, 5, 6, 7, 8, 1,
+ 0,
+ 0,
+ 37|128,1, ISD::VECTOR_SHUFFLE,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 50, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 13,
+ OPC_CheckType, MVT::v4i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 3,
+ 107, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 13,
+ OPC_SwitchType , 29, MVT::v4f32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 3,
+ 29, MVT::v2f64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPDmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 3,
+ 29, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPDmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 4, 5, 6, 7, 8, 3,
+ 0,
+ 0,
+ 27|128,2, X86ISD::SHLD,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 46,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 3, 10,
+ 46,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 3, 10,
+ 48,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD64mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 3, 10,
+ 41,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 4, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 3,
+ 41,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i8,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 4, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 3,
+ 43,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i8,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 4, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD64mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 3,
+ 0,
+ 27|128,2, X86ISD::SHRD,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 46,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 3, 10,
+ 46,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 3, 10,
+ 48,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_MoveChild, 2,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitConvertToTarget, 4,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD64mri8), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 5, 6, 7, 8, 9, 3, 10,
+ 41,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i8,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 4, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 3,
+ 41,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i8,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 4, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 3,
+ 43,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_CheckChild2Type, MVT::i8,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_EmitCopyToReg, 4, X86::CL,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD64mrCL), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 6, 5, 6, 7, 8, 9, 3,
+ 0,
+ 116|128,1, X86ISD::INC,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_SwitchType , 36, MVT::i8,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC8m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 76, MVT::i16,
+ OPC_Scope, 36,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC16m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 36,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC64_16m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 0,
+ 76, MVT::i32,
+ OPC_Scope, 36,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 36,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC64_32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 0,
+ 36, MVT::i64,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::INC64m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 0,
+ 116|128,1, X86ISD::DEC,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_SwitchType , 36, MVT::i8,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC8m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 76, MVT::i16,
+ OPC_Scope, 36,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC16m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 36,
+ OPC_CheckPredicate, 6,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC64_16m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 0,
+ 76, MVT::i32,
+ OPC_Scope, 36,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 2,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 36,
+ OPC_CheckPredicate, 3,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC64_32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 0,
+ 36, MVT::i64,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_MoveChild, 2,
+ OPC_CheckSame, 2,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC64m), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::i32, 5, 3, 4, 5, 6, 7,
+ 0,
+ 83|128,3, ISD::EXTRACT_VECTOR_ELT,
+ OPC_Scope, 60|128,1,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 99, ISD::VECTOR_SHUFFLE,
+ OPC_Scope, 51,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4f32,
OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitCopyToReg, 1, X86::EFLAGS,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SETGEm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 26,
- OPC_CheckInteger, 8,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
OPC_MoveParent,
- OPC_RecordChild1,
+ OPC_CheckPredicate, 14,
+ OPC_CheckType, MVT::v2f64,
OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitCopyToReg, 1, X86::EFLAGS,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SETLEm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 26,
- OPC_CheckInteger, 5,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
OPC_MoveParent,
- OPC_RecordChild1,
+ OPC_CheckType, MVT::f64,
OPC_MoveParent,
OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 0,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitCopyToReg, 1, X86::EFLAGS,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SETGm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 26,
- OPC_CheckInteger, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVHPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 44,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
OPC_MoveParent,
- OPC_RecordChild1,
+ OPC_CheckPredicate, 14,
+ OPC_CheckType, MVT::v2f64,
OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitCopyToReg, 1, X86::EFLAGS,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SETBm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 26,
- OPC_CheckInteger, 1,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
OPC_MoveParent,
- OPC_RecordChild1,
+ OPC_CheckType, MVT::f64,
OPC_MoveParent,
OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitCopyToReg, 1, X86::EFLAGS,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SETAEm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 26,
- OPC_CheckInteger, 3,
- OPC_MoveParent,
- OPC_RecordChild1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVHPDmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 81, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_SwitchType , 34, MVT::v2f64,
OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitCopyToReg, 1, X86::EFLAGS,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SETBEm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 26,
+ OPC_MoveChild, 1,
OPC_CheckInteger, 0,
OPC_MoveParent,
- OPC_RecordChild1,
+ OPC_CheckType, MVT::f64,
OPC_MoveParent,
OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 0,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitCopyToReg, 1, X86::EFLAGS,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SETAm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 26,
- OPC_CheckInteger, 15,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 38, MVT::v4i32,
OPC_MoveParent,
OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitCopyToReg, 1, X86::EFLAGS,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SETSm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 26,
- OPC_CheckInteger, 12,
- OPC_MoveParent,
- OPC_RecordChild1,
+ OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitCopyToReg, 1, X86::EFLAGS,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SETNSm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 26,
- OPC_CheckInteger, 14,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild2,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::EXTRACTPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 4, 5, 6, 7, 8, 1, 9,
+ 0,
+ 0,
+ 17|128,2,
+ OPC_RecordChild0,
+ OPC_Scope, 69,
+ OPC_CheckChild0Type, MVT::v2f64,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_Scope, 20,
+ OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitCopyToReg, 1, X86::EFLAGS,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SETPm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 26,
- OPC_CheckInteger, 11,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_RecordChild2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPDmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 30,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitCopyToReg, 1, X86::EFLAGS,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SETNPm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 26,
- OPC_CheckInteger, 13,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f64, 2, 1, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSDmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 9,
+ 0,
+ 76,
+ OPC_CheckChild0Type, MVT::v2i64,
+ OPC_Scope, 33,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
OPC_MoveParent,
- OPC_RecordChild1,
+ OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitCopyToReg, 1, X86::EFLAGS,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SETOm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
- 26,
- OPC_CheckInteger, 10,
- OPC_MoveParent,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVPQI2QImr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 37,
OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitCopyToReg, 1, X86::EFLAGS,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SETNOm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
- 0, 5, 3, 4, 5, 6, 7,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PEXTRQmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 4, 5, 6, 7, 8, 1, 9,
0,
- 84|128,1, X86ISD::Wrapper,
- OPC_RecordChild0,
- OPC_MoveChild, 0,
- OPC_SwitchOpcode , 49, ISD::TargetGlobalAddress,
- OPC_MoveParent,
- OPC_SwitchType , 20, MVT::i32,
- OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV32mi), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 22, MVT::i64,
- OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64mi32), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 0,
- 49, ISD::TargetExternalSymbol,
- OPC_MoveParent,
- OPC_SwitchType , 20, MVT::i32,
- OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV32mi), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 22, MVT::i64,
- OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64mi32), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 0,
- 49, ISD::TargetBlockAddress,
- OPC_MoveParent,
- OPC_SwitchType , 20, MVT::i32,
- OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV32mi), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 22, MVT::i64,
- OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64mi32), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 0,
- 25, ISD::TargetConstantPool,
+ 76,
+ OPC_CheckChild0Type, MVT::v4i32,
+ OPC_Scope, 33,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
OPC_MoveParent,
- OPC_CheckType, MVT::i64,
+ OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_RecordChild2,
- OPC_CheckPatternPredicate, 5,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVPDI2DImr), 0|OPFL_Chain|OPFL_MemRefs,
0, 6, 3, 4, 5, 6, 7, 1,
- 25, ISD::TargetJumpTable,
+ 37,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
OPC_MoveParent,
- OPC_CheckType, MVT::i64,
+ OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_RecordChild2,
- OPC_CheckPatternPredicate, 5,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64mi32), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PEXTRDmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 4, 5, 6, 7, 8, 1, 9,
0,
- 0,
- 109,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_Scope, 26,
- OPC_CheckPredicate, 12,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitConvertToTarget, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64mi32), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 8,
- 24,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitConvertToTarget, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV8mi), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 8,
- 24,
- OPC_CheckType, MVT::i16,
+ 45,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitConvertToTarget, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV16mi), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 8,
- 24,
- OPC_CheckType, MVT::i32,
+ OPC_CheckType, MVT::f32,
OPC_MoveParent,
OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitConvertToTarget, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV32mi), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 8,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f32, 2, 1, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 9,
0,
0,
- 35,
- OPC_CheckPredicate, 17,
- OPC_CheckPredicate, 18,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
+ 57|128,1, ISD::TRUNCATE,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i32,
+ OPC_CheckInteger, 8,
+ OPC_CheckType, MVT::i8,
OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitConvertToTarget, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV16mi), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 8,
- 35,
- OPC_CheckPredicate, 3,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_MoveChild, 1,
+ OPC_CheckPredicate, 15,
+ OPC_SwitchType , 53, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 16,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, X86::GR64_ABCDRegClassID,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
+ 1, MVT::i64, 2, 1, 8,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 9, 10,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV8mr_NOREX), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 11,
+ 55, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 16,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, X86::GR32_ABCDRegClassID,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
+ 1, MVT::i32, 2, 1, 8,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 9, 10,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV8mr_NOREX), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 11,
+ 55, MVT::i16,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 16,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 3,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitInteger, MVT::i32, X86::GR16_ABCDRegClassID,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::COPY_TO_REGCLASS), 0,
+ 1, MVT::i16, 2, 1, 8,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i8, 2, 9, 10,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV8mr_NOREX), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 11,
+ 0,
+ 54, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::EXTRACT_VECTOR_ELT,
+ OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_RecordChild0,
- OPC_CheckChild0Type, MVT::f64,
- OPC_CheckType, MVT::i64,
+ OPC_CheckChild0Type, MVT::v4f32,
+ OPC_CheckType, MVT::v4i32,
OPC_MoveParent,
- OPC_RecordChild2,
- OPC_CheckPatternPredicate, 1,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSDto64mr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 35,
- OPC_CheckPredicate, 17,
- OPC_CheckPredicate, 18,
- OPC_RecordMemRef,
- OPC_RecordNode,
OPC_RecordChild1,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::f32,
OPC_MoveParent,
OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 4,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/3,
OPC_EmitMergeInputChains, 1, 0,
- OPC_EmitConvertToTarget, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV16mi), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 8,
- 63,
- OPC_CheckPredicate, 3,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_Scope, 31,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::BIT_CONVERT,
- OPC_RecordChild0,
- OPC_CheckChild0Type, MVT::f32,
- OPC_CheckType, MVT::i32,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::EXTRACTPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 7, 4, 5, 6, 7, 8, 1, 9,
+ 116|128,3, X86ISD::SETCC,
+ OPC_MoveChild, 0,
+ OPC_Scope, 30,
+ OPC_CheckInteger, 4,
+ OPC_MoveParent,
+ OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild2,
- OPC_CheckPatternPredicate, 1,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSS2DImr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 24,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETEm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckInteger, 9,
+ OPC_MoveParent,
OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::f32,
+ OPC_MoveParent,
OPC_RecordChild2,
- OPC_CheckPatternPredicate, 6,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ST_Fp32m), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 0,
- 30,
- OPC_CheckPredicate, 17,
- OPC_CheckPredicate, 19,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::f64,
- OPC_RecordChild2,
- OPC_CheckPatternPredicate, 7,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ST_Fp64m32), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 28,
- OPC_CheckPredicate, 3,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::f64,
- OPC_RecordChild2,
- OPC_CheckPatternPredicate, 7,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ST_Fp64m), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 58,
- OPC_CheckPredicate, 17,
- OPC_Scope, 26,
- OPC_CheckPredicate, 19,
- OPC_RecordMemRef,
- OPC_RecordNode,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETNEm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckInteger, 7,
+ OPC_MoveParent,
OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::f80,
+ OPC_MoveParent,
OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ST_Fp80m32), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 26,
- OPC_CheckPredicate, 20,
- OPC_RecordMemRef,
- OPC_RecordNode,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETLm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckInteger, 6,
+ OPC_MoveParent,
OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::f80,
+ OPC_MoveParent,
OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ST_Fp80m64), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 0,
- 97|128,4,
- OPC_CheckPredicate, 3,
- OPC_Scope, 11|128,1,
- OPC_RecordMemRef,
- OPC_RecordNode,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETGEm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckInteger, 8,
+ OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 21,
- OPC_CheckChild1Type, MVT::f80,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ST_FpP80m), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 21,
- OPC_CheckChild1Type, MVT::i8,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV8mr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 21,
- OPC_CheckChild1Type, MVT::i16,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV16mr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 21,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV32mr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 21,
- OPC_CheckChild1Type, MVT::i64,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64mr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 23,
- OPC_CheckChild1Type, MVT::f32,
- OPC_RecordChild2,
- OPC_CheckPatternPredicate, 0,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSSmr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 0,
- 28,
- OPC_CheckPredicate, 21,
- OPC_RecordMemRef,
- OPC_RecordNode,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETLEm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckInteger, 5,
+ OPC_MoveParent,
OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::v4f32,
+ OPC_MoveParent,
OPC_RecordChild2,
- OPC_CheckPatternPredicate, 0,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVAPSmr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 53,
- OPC_RecordMemRef,
- OPC_RecordNode,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETGm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckInteger, 2,
+ OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 23,
- OPC_CheckChild1Type, MVT::v4f32,
- OPC_RecordChild2,
- OPC_CheckPatternPredicate, 0,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPSmr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 23,
- OPC_CheckChild1Type, MVT::f64,
- OPC_RecordChild2,
- OPC_CheckPatternPredicate, 1,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSDmr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 0,
- 28,
- OPC_CheckPredicate, 21,
- OPC_RecordMemRef,
- OPC_RecordNode,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETBm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckInteger, 1,
+ OPC_MoveParent,
OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::v2f64,
+ OPC_MoveParent,
OPC_RecordChild2,
- OPC_CheckPatternPredicate, 1,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVAPDmr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 26,
- OPC_RecordMemRef,
- OPC_RecordNode,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETAEm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckInteger, 3,
+ OPC_MoveParent,
OPC_RecordChild1,
- OPC_CheckChild1Type, MVT::v2f64,
+ OPC_MoveParent,
OPC_RecordChild2,
- OPC_CheckPatternPredicate, 1,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPDmr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 95,
- OPC_CheckPredicate, 21,
- OPC_RecordMemRef,
- OPC_RecordNode,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETBEm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
OPC_RecordChild1,
- OPC_Scope, 21,
- OPC_CheckChild1Type, MVT::v2i64,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVAPSmr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 21,
- OPC_CheckChild1Type, MVT::v4i32,
- OPC_RecordChild2,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVAPSmr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 21,
- OPC_CheckChild1Type, MVT::v8i16,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETAm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckInteger, 15,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETSm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckInteger, 12,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETNSm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckInteger, 14,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETPm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckInteger, 11,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETNPm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckInteger, 13,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETOm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 30,
+ OPC_CheckInteger, 10,
+ OPC_MoveParent,
+ OPC_RecordChild1,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitCopyToReg, 1, X86::EFLAGS,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SETNOm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
+ 0, 5, 3, 4, 5, 6, 7,
+ 0,
+ 116|128,1, X86ISD::Wrapper,
+ OPC_RecordChild0,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 57, ISD::TargetGlobalAddress,
+ OPC_MoveParent,
+ OPC_SwitchType , 24, MVT::i32,
+ OPC_MoveParent,
OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVAPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV32mi), 0|OPFL_Chain|OPFL_MemRefs,
0, 6, 3, 4, 5, 6, 7, 1,
- 21,
- OPC_CheckChild1Type, MVT::v16i8,
+ 26, MVT::i64,
+ OPC_MoveParent,
OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVAPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64mi32), 0|OPFL_Chain|OPFL_MemRefs,
0, 6, 3, 4, 5, 6, 7, 1,
0,
- 99|128,1,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_Scope, 21,
- OPC_CheckChild1Type, MVT::v2i64,
+ 57, ISD::TargetExternalSymbol,
+ OPC_MoveParent,
+ OPC_SwitchType , 24, MVT::i32,
+ OPC_MoveParent,
OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV32mi), 0|OPFL_Chain|OPFL_MemRefs,
0, 6, 3, 4, 5, 6, 7, 1,
- 21,
- OPC_CheckChild1Type, MVT::v4i32,
+ 26, MVT::i64,
+ OPC_MoveParent,
OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64mi32), 0|OPFL_Chain|OPFL_MemRefs,
0, 6, 3, 4, 5, 6, 7, 1,
- 21,
- OPC_CheckChild1Type, MVT::v8i16,
+ 0,
+ 57, ISD::TargetBlockAddress,
+ OPC_MoveParent,
+ OPC_SwitchType , 24, MVT::i32,
+ OPC_MoveParent,
OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV32mi), 0|OPFL_Chain|OPFL_MemRefs,
0, 6, 3, 4, 5, 6, 7, 1,
- 21,
- OPC_CheckChild1Type, MVT::v16i8,
+ 26, MVT::i64,
+ OPC_MoveParent,
OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 5,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64mi32), 0|OPFL_Chain|OPFL_MemRefs,
0, 6, 3, 4, 5, 6, 7, 1,
- 45,
- OPC_CheckChild1Type, MVT::v1i64,
- OPC_RecordChild2,
- OPC_Scope, 20,
- OPC_CheckPatternPredicate, 8,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ64mr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 18,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ64mr), 0|OPFL_Chain|OPFL_MemRefs,
- 0, 6, 3, 4, 5, 6, 7, 1,
- 0,
- 21,
- OPC_CheckChild1Type, MVT::v8i8,
- OPC_RecordChild2,
+ 0,
+ 29, ISD::TargetConstantPool,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 29, ISD::TargetJumpTable,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 0,
+ 21|128,1,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_SwitchType , 28, MVT::i64,
+ OPC_CheckPredicate, 12,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64mi32), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 8,
+ 26, MVT::i8,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV8mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 8,
+ 26, MVT::i16,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 8,
+ 54, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 22,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV32mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 8,
+ 24,
+ OPC_CheckPredicate, 17,
+ OPC_CheckPredicate, 18,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 8,
+ 0,
+ 0,
+ 35,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::f64,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSDto64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 35,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i64,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 17,
+ OPC_CheckPredicate, 18,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV16mi), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 8,
+ 35,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_RecordChild0,
+ OPC_CheckChild0Type, MVT::f32,
+ OPC_CheckType, MVT::i32,
+ OPC_MoveParent,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSS2DImr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 85|128,6,
+ OPC_RecordChild1,
+ OPC_Scope, 51,
+ OPC_CheckChild1Type, MVT::f32,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_Scope, 20,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ST_Fp32m), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 20,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 79,
+ OPC_CheckChild1Type, MVT::f64,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 24,
+ OPC_CheckPredicate, 17,
+ OPC_CheckPredicate, 19,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ST_Fp64m32), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 46,
+ OPC_CheckPredicate, 5,
+ OPC_Scope, 20,
+ OPC_CheckPatternPredicate, 7,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ST_Fp64m), 0|OPFL_Chain|OPFL_MemRefs,
0, 6, 3, 4, 5, 6, 7, 1,
- 21,
- OPC_CheckChild1Type, MVT::v4i16,
- OPC_RecordChild2,
+ 20,
+ OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSDmr), 0|OPFL_Chain|OPFL_MemRefs,
0, 6, 3, 4, 5, 6, 7, 1,
- 21,
- OPC_CheckChild1Type, MVT::v2i32,
- OPC_RecordChild2,
+ 0,
+ 0,
+ 75,
+ OPC_CheckChild1Type, MVT::f80,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 46,
+ OPC_CheckPredicate, 17,
+ OPC_Scope, 20,
+ OPC_CheckPredicate, 19,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ST_Fp80m32), 0|OPFL_Chain|OPFL_MemRefs,
0, 6, 3, 4, 5, 6, 7, 1,
- 21,
- OPC_CheckChild1Type, MVT::v2f32,
- OPC_RecordChild2,
+ 20,
+ OPC_CheckPredicate, 20,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ST_Fp80m64), 0|OPFL_Chain|OPFL_MemRefs,
0, 6, 3, 4, 5, 6, 7, 1,
0,
+ 20,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ST_FpP80m), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
0,
- 77,
- OPC_CheckPredicate, 17,
- OPC_CheckPredicate, 18,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_Scope, 33,
- OPC_CheckChild1Type, MVT::i32,
- OPC_RecordChild2,
+ 25,
+ OPC_CheckChild1Type, MVT::i8,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV8mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 25,
+ OPC_CheckChild1Type, MVT::i16,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV16mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 63,
+ OPC_CheckChild1Type, MVT::i32,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 20,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV32mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 34,
+ OPC_CheckPredicate, 17,
+ OPC_CheckPredicate, 18,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 3,
@@ -8339,9 +8018,20 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::i16, 2, 1, 8,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV16mr), 0|OPFL_Chain|OPFL_MemRefs,
0, 6, 3, 4, 5, 6, 7, 9,
- 33,
- OPC_CheckChild1Type, MVT::i64,
- OPC_RecordChild2,
+ 0,
+ 63,
+ OPC_CheckChild1Type, MVT::i64,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_Scope, 20,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 34,
+ OPC_CheckPredicate, 17,
+ OPC_CheckPredicate, 18,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i32, 3,
@@ -8350,11 +8040,169 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV16mr), 0|OPFL_Chain|OPFL_MemRefs,
0, 6, 3, 4, 5, 6, 7, 9,
0,
+ 53,
+ OPC_CheckChild1Type, MVT::v4f32,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_Scope, 22,
+ OPC_CheckPredicate, 21,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVAPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 20,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 53,
+ OPC_CheckChild1Type, MVT::v2f64,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_Scope, 22,
+ OPC_CheckPredicate, 21,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVAPDmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 20,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPDmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 49,
+ OPC_CheckChild1Type, MVT::v2i64,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_Scope, 20,
+ OPC_CheckPredicate, 21,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVAPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 18,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 49,
+ OPC_CheckChild1Type, MVT::v4i32,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_Scope, 20,
+ OPC_CheckPredicate, 21,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVAPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 18,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 49,
+ OPC_CheckChild1Type, MVT::v8i16,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_Scope, 20,
+ OPC_CheckPredicate, 21,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVAPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 18,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 49,
+ OPC_CheckChild1Type, MVT::v16i8,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_Scope, 20,
+ OPC_CheckPredicate, 21,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVAPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 18,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPSmr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 49,
+ OPC_CheckChild1Type, MVT::v1i64,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_Scope, 20,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 18,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 0,
+ 25,
+ OPC_CheckChild1Type, MVT::v8i8,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 25,
+ OPC_CheckChild1Type, MVT::v4i16,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 25,
+ OPC_CheckChild1Type, MVT::v2i32,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
+ 25,
+ OPC_CheckChild1Type, MVT::v2f32,
+ OPC_RecordChild2,
+ OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 5,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ64mr), 0|OPFL_Chain|OPFL_MemRefs,
+ 0, 6, 3, 4, 5, 6, 7, 1,
0,
0,
- 66|128,26, ISD::VECTOR_SHUFFLE,
- OPC_Scope, 55,
- OPC_CheckPredicate, 13,
+ 7|128,24, ISD::VECTOR_SHUFFLE,
+ OPC_Scope, 82,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::BIT_CONVERT,
@@ -8362,89 +8210,46 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
- OPC_CheckType, MVT::f64,
- OPC_MoveParent,
- OPC_CheckType, MVT::v2f64,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::v4f32,
- OPC_CheckPatternPredicate, 0,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPSrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
- 55,
- OPC_CheckPredicate, 22,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::BIT_CONVERT,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::f64,
OPC_MoveParent,
OPC_CheckType, MVT::v2f64,
OPC_MoveParent,
OPC_MoveParent,
OPC_CheckType, MVT::v4f32,
- OPC_CheckPatternPredicate, 0,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVHPSrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
- 51,
- OPC_CheckPredicate, 23,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::BIT_CONVERT,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v2i64,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_CheckType, MVT::v4i32,
- OPC_CheckPatternPredicate, 9,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSHDUPrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
- 51,
- OPC_CheckPredicate, 25,
+ OPC_Scope, 23,
+ OPC_CheckPredicate, 13,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
+ 23,
+ OPC_CheckPredicate, 22,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVHPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 77,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -8452,110 +8257,104 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::UNDEF,
OPC_MoveParent,
OPC_CheckType, MVT::v4i32,
- OPC_CheckPatternPredicate, 9,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSLDUPrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
- 48,
- OPC_CheckPredicate, 13,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::f64,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::v2f64,
- OPC_CheckPatternPredicate, 1,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPDrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
- 48,
- OPC_CheckPredicate, 22,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::f64,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::v2f64,
- OPC_CheckPatternPredicate, 1,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVHPDrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
- 102,
- OPC_CheckPredicate, 13,
+ OPC_Scope, 22,
+ OPC_CheckPredicate, 24,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSHDUPrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
+ 22,
+ OPC_CheckPredicate, 25,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSLDUPrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 48|128,1,
OPC_RecordChild0,
OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_SwitchType , 19, MVT::v4f32,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPSrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
- 19, MVT::v2f64,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPDrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
- 19, MVT::v4i32,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPSrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
- 19, MVT::v2i64,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPDrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ OPC_SwitchOpcode , 70, ISD::SCALAR_TO_VECTOR,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
+ OPC_CheckType, MVT::f64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2f64,
+ OPC_Scope, 23,
+ OPC_CheckPredicate, 13,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
+ 23,
+ OPC_CheckPredicate, 22,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVHPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 97, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 13,
+ OPC_SwitchType , 19, MVT::v4f32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
+ 19, MVT::v2f64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
+ 19, MVT::v4i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
+ 19, MVT::v2i64,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
0,
56,
OPC_RecordNode,
- OPC_CheckPredicate, 26,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::UNDEF,
OPC_MoveParent,
+ OPC_CheckPredicate, 26,
OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -8563,37 +8362,38 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitNodeXForm, 0, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::PSHUFDmi), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v4i32, 6, 3, 4, 5, 6, 7, 8,
- 84,
- OPC_CheckPredicate, 27,
+ 86,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
- OPC_SwitchType , 29, MVT::v2f64,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
+ OPC_SwitchType , 31, MVT::v2f64,
OPC_MoveParent,
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::UNDEF,
OPC_MoveParent,
+ OPC_CheckPredicate, 27,
OPC_CheckType, MVT::v4f32,
OPC_CheckPatternPredicate, 9,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVDDUPrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v4f32, 5, 2, 3, 4, 5, 6,
- 29, MVT::v2i64,
+ 31, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::UNDEF,
OPC_MoveParent,
+ OPC_CheckPredicate, 27,
OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 9,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -8601,97 +8401,65 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVDDUPrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
0,
- 41,
- OPC_CheckPredicate, 14,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_CheckType, MVT::v4f32,
- OPC_CheckPatternPredicate, 0,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKHPSrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
- 41,
- OPC_CheckPredicate, 28,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_CheckType, MVT::v4f32,
- OPC_CheckPatternPredicate, 0,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKLPSrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
- 41,
- OPC_CheckPredicate, 14,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_CheckType, MVT::v2f64,
- OPC_CheckPatternPredicate, 1,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKHPDrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
- 41,
- OPC_CheckPredicate, 28,
+ 122,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
- OPC_CheckType, MVT::v2f64,
- OPC_CheckPatternPredicate, 1,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKLPDrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
- 124,
- OPC_CheckPredicate, 27,
+ OPC_SwitchType , 50, MVT::v4f32,
+ OPC_Scope, 23,
+ OPC_CheckPredicate, 14,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKHPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
+ 23,
+ OPC_CheckPredicate, 28,
+ OPC_CheckPatternPredicate, 0,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKLPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 50, MVT::v2f64,
+ OPC_Scope, 23,
+ OPC_CheckPredicate, 14,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKHPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
+ 23,
+ OPC_CheckPredicate, 28,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKLPDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 0,
+ 126,
OPC_MoveChild, 0,
- OPC_SwitchOpcode , 52, ISD::BIT_CONVERT,
+ OPC_SwitchOpcode , 54, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
@@ -8700,24 +8468,26 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::UNDEF,
OPC_MoveParent,
+ OPC_CheckPredicate, 27,
OPC_CheckType, MVT::v2f64,
OPC_CheckPatternPredicate, 9,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVDDUPrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2f64, 5, 2, 3, 4, 5, 6,
- 62, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
+ 64, ISD::LOAD,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::UNDEF,
OPC_MoveParent,
+ OPC_CheckPredicate, 27,
OPC_SwitchType , 20, MVT::v2f64,
OPC_CheckPatternPredicate, 9,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -8732,54 +8502,36 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
0,
0,
- 115,
+ 86,
+ OPC_RecordNode,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
OPC_RecordNode,
- OPC_Scope, 55,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_Scope, 26,
OPC_CheckPredicate, 29,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::BIT_CONVERT,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v2i64,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 1,
OPC_EmitNodeXForm, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::PSHUFHWmi), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v8i16, 6, 3, 4, 5, 6, 7, 8,
- 55,
+ 26,
OPC_CheckPredicate, 30,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::BIT_CONVERT,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v2i64,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 1,
@@ -8788,51 +8540,50 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v8i16, 6, 3, 4, 5, 6, 7, 8,
0,
51,
- OPC_CheckPredicate, 27,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
OPC_CheckType, MVT::f64,
OPC_MoveParent,
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::UNDEF,
OPC_MoveParent,
+ OPC_CheckPredicate, 27,
OPC_CheckType, MVT::v2f64,
OPC_CheckPatternPredicate, 9,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVDDUPrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2f64, 5, 2, 3, 4, 5, 6,
- 113,
+ 95,
OPC_RecordNode,
- OPC_Scope, 55,
- OPC_CheckPredicate, 26,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::BIT_CONVERT,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v4f32,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_SwitchType , 37, MVT::v4f32,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::UNDEF,
OPC_MoveParent,
+ OPC_CheckPredicate, 26,
OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -8840,24 +8591,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitNodeXForm, 0, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::PSHUFDmi), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v4i32, 6, 3, 4, 5, 6, 7, 8,
- 53,
- OPC_CheckPredicate, 31,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::BIT_CONVERT,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v1i64,
+ 35, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::UNDEF,
OPC_MoveParent,
+ OPC_CheckPredicate, 31,
OPC_CheckType, MVT::v4i16,
OPC_CheckPatternPredicate, 8,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -8866,138 +8606,113 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSHUFWmi), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v4i16, 6, 3, 4, 5, 6, 7, 8,
0,
- 96,
- OPC_CheckPredicate, 28,
+ 45|128,1,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
- OPC_SwitchType , 21, MVT::v16i8,
- OPC_CheckPatternPredicate, 1,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLBWrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v16i8, 6, 0, 3, 4, 5, 6, 7,
- 21, MVT::v8i16,
- OPC_CheckPatternPredicate, 1,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLWDrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
- 21, MVT::v4i32,
- OPC_CheckPatternPredicate, 1,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLDQrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
+ OPC_Scope, 73,
+ OPC_CheckPredicate, 28,
+ OPC_SwitchType , 21, MVT::v16i8,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLBWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::v8i16,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLWDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLDQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 73,
+ OPC_CheckPredicate, 14,
+ OPC_SwitchType , 21, MVT::v16i8,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHBWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v16i8, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::v8i16,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHWDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHDQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
0,
- 96,
- OPC_CheckPredicate, 14,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::BIT_CONVERT,
+ 70,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
- OPC_CheckType, MVT::v2i64,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_SwitchType , 21, MVT::v16i8,
- OPC_CheckPatternPredicate, 1,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHBWrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v16i8, 6, 0, 3, 4, 5, 6, 7,
- 21, MVT::v8i16,
- OPC_CheckPatternPredicate, 1,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHWDrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
- 21, MVT::v4i32,
- OPC_CheckPatternPredicate, 1,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHDQrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
- 0,
- 44,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 23,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_CheckType, MVT::v4f32,
- OPC_CheckPatternPredicate, 9,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSHDUPrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v4f32, 5, 2, 3, 4, 5, 6,
- 44,
- OPC_CheckPredicate, 25,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::UNDEF,
OPC_MoveParent,
OPC_CheckType, MVT::v4f32,
- OPC_CheckPatternPredicate, 9,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSLDUPrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v4f32, 5, 2, 3, 4, 5, 6,
+ OPC_Scope, 22,
+ OPC_CheckPredicate, 24,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSHDUPrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 5, 2, 3, 4, 5, 6,
+ 22,
+ OPC_CheckPredicate, 25,
+ OPC_CheckPatternPredicate, 9,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSLDUPrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4f32, 5, 2, 3, 4, 5, 6,
+ 0,
53,
OPC_RecordNode,
- OPC_CheckPredicate, 32,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
+ OPC_CheckPredicate, 32,
OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/3,
@@ -9005,134 +8720,114 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitNodeXForm, 0, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::SHUFPSrmi), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v4i32, 7, 1, 4, 5, 6, 7, 8, 9,
- 94,
- OPC_CheckPredicate, 33,
+ 12|128,2,
OPC_RecordChild0,
OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::BIT_CONVERT,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v1i64,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_SwitchType , 21, MVT::v8i8,
- OPC_CheckPatternPredicate, 8,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKHBWrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v8i8, 6, 0, 3, 4, 5, 6, 7,
- 21, MVT::v4i16,
- OPC_CheckPatternPredicate, 8,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKHWDrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
- 21, MVT::v2i32,
- OPC_CheckPatternPredicate, 8,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKHDQrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v2i32, 6, 0, 3, 4, 5, 6, 7,
- 0,
- 94,
- OPC_CheckPredicate, 34,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::BIT_CONVERT,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v1i64,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_SwitchType , 21, MVT::v8i8,
- OPC_CheckPatternPredicate, 8,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKLBWrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v8i8, 6, 0, 3, 4, 5, 6, 7,
- 21, MVT::v4i16,
- OPC_CheckPatternPredicate, 8,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKLWDrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
- 21, MVT::v2i32,
- OPC_CheckPatternPredicate, 8,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKLDQrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v2i32, 6, 0, 3, 4, 5, 6, 7,
- 0,
- 39,
- OPC_CheckPredicate, 22,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::BIT_CONVERT,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, X86ISD::VZEXT_LOAD,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v2i64,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::v4i32,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVHPSrm), 0|OPFL_Chain,
- 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
- 32,
- OPC_CheckPredicate, 27,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_SwitchType , 9, MVT::v4f32,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLHPSrr), 0,
- 1, MVT::v4f32, 2, 0, 0,
- 9, MVT::v2i64,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLHPSrr), 0,
- 1, MVT::v2i64, 2, 0, 0,
- 0,
- 32,
- OPC_CheckPredicate, 35,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_SwitchType , 9, MVT::v4f32,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVHLPSrr), 0,
- 1, MVT::v4f32, 2, 0, 0,
- 9, MVT::v4i32,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVHLPSrr), 0,
- 1, MVT::v4i32, 2, 0, 0,
+ OPC_SwitchOpcode , 73|128,1, ISD::BIT_CONVERT,
+ OPC_MoveChild, 0,
+ OPC_SwitchOpcode , 34|128,1, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckType, MVT::v1i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_Scope, 73,
+ OPC_CheckPredicate, 33,
+ OPC_SwitchType , 21, MVT::v8i8,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKHBWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i8, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::v4i16,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKHWDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::v2i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKHDQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 73,
+ OPC_CheckPredicate, 34,
+ OPC_SwitchType , 21, MVT::v8i8,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKLBWrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v8i8, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::v4i16,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKLWDrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::v2i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKLDQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 0,
+ 30, X86ISD::VZEXT_LOAD,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckType, MVT::v2i64,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 22,
+ OPC_CheckType, MVT::v4i32,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVHPSrm), 0|OPFL_Chain,
+ 1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 57, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_Scope, 26,
+ OPC_CheckPredicate, 27,
+ OPC_SwitchType , 9, MVT::v4f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLHPSrr), 0,
+ 1, MVT::v4f32, 2, 0, 0,
+ 9, MVT::v2i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLHPSrr), 0,
+ 1, MVT::v2i64, 2, 0, 0,
+ 0,
+ 26,
+ OPC_CheckPredicate, 35,
+ OPC_SwitchType , 9, MVT::v4f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVHLPSrr), 0,
+ 1, MVT::v4f32, 2, 0, 0,
+ 9, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVHLPSrr), 0,
+ 1, MVT::v4i32, 2, 0, 0,
+ 0,
+ 0,
0,
75,
OPC_RecordNode,
- OPC_CheckPredicate, 32,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
+ OPC_CheckPredicate, 32,
OPC_SwitchType , 25, MVT::v4f32,
OPC_CheckPatternPredicate, 0,
OPC_CheckComplexPat, /*CP*/0, /*#*/3,
@@ -9148,113 +8843,97 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::SHUFPDrmi), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2f64, 7, 1, 4, 5, 6, 7, 8, 9,
0,
- 41,
- OPC_CheckPredicate, 28,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_CheckType, MVT::v2i64,
- OPC_CheckPatternPredicate, 1,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLQDQrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
- 41,
- OPC_CheckPredicate, 14,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_MoveParent,
- OPC_CheckType, MVT::v2i64,
- OPC_CheckPatternPredicate, 1,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHQDQrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
- 17,
- OPC_CheckPredicate, 22,
+ 7|128,1,
OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v4f32,
- OPC_CheckPatternPredicate, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLHPSrr), 0,
- 1, MVT::v4f32, 2, 0, 1,
- 17,
- OPC_CheckPredicate, 36,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v4f32,
- OPC_CheckPatternPredicate, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVHLPSrr), 0,
- 1, MVT::v4f32, 2, 0, 1,
- 15,
- OPC_CheckPredicate, 22,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v4i32,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLHPSrr), 0,
- 1, MVT::v4i32, 2, 0, 1,
- 15,
- OPC_CheckPredicate, 36,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v4i32,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVHLPSrr), 0,
- 1, MVT::v4i32, 2, 0, 1,
+ OPC_Scope, 67,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v2i64,
+ OPC_Scope, 23,
+ OPC_CheckPredicate, 28,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLQDQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 23,
+ OPC_CheckPredicate, 14,
+ OPC_CheckPatternPredicate, 1,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHQDQrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 63,
+ OPC_RecordChild1,
+ OPC_SwitchType , 30, MVT::v4f32,
+ OPC_Scope, 13,
+ OPC_CheckPredicate, 22,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLHPSrr), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 13,
+ OPC_CheckPredicate, 36,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVHLPSrr), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 0,
+ 26, MVT::v4i32,
+ OPC_Scope, 11,
+ OPC_CheckPredicate, 22,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVLHPSrr), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 11,
+ OPC_CheckPredicate, 36,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVHLPSrr), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 0,
+ 0,
+ 0,
22,
- OPC_CheckPredicate, 37,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::BIT_CONVERT,
- OPC_CheckPredicate, 38,
+ OPC_CheckPredicate, 37,
OPC_MoveParent,
OPC_RecordChild1,
+ OPC_CheckPredicate, 38,
OPC_CheckType, MVT::v2f64,
OPC_CheckPatternPredicate, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZPQILo2PQIrr), 0,
1, MVT::v2f64, 1, 0,
- 20,
- OPC_CheckPredicate, 23,
+ 36,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::UNDEF,
OPC_MoveParent,
OPC_CheckType, MVT::v4i32,
- OPC_CheckPatternPredicate, 9,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSHDUPrr), 0,
- 1, MVT::v4i32, 1, 0,
- 20,
- OPC_CheckPredicate, 25,
+ OPC_Scope, 12,
+ OPC_CheckPredicate, 24,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSHDUPrr), 0,
+ 1, MVT::v4i32, 1, 0,
+ 12,
+ OPC_CheckPredicate, 25,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSLDUPrr), 0,
+ 1, MVT::v4i32, 1, 0,
+ 0,
+ 83,
+ OPC_RecordNode,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::UNDEF,
OPC_MoveParent,
- OPC_CheckType, MVT::v4i32,
- OPC_CheckPatternPredicate, 9,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSLDUPrr), 0,
- 1, MVT::v4i32, 1, 0,
- 89,
- OPC_RecordNode,
- OPC_Scope, 42,
+ OPC_Scope, 36,
OPC_CheckPredicate, 39,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
OPC_SwitchType , 14, MVT::v4i32,
OPC_CheckPatternPredicate, 10,
OPC_EmitNodeXForm, 0, 0,
@@ -9266,12 +8945,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::PSHUFDri), 0,
1, MVT::v4f32, 2, 1, 2,
0,
- 42,
+ 36,
OPC_CheckPredicate, 40,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
OPC_SwitchType , 14, MVT::v4i32,
OPC_CheckPatternPredicate, 10,
OPC_EmitNodeXForm, 0, 0,
@@ -9284,198 +8959,167 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v4f32, 2, 1, 2,
0,
0,
- 98,
- OPC_CheckPredicate, 37,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_SwitchType , 21, MVT::v4f32,
- OPC_EmitInteger, MVT::i32, 1,
- OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
- 1, MVT::f32, 2, 1, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSSrr), 0,
- 1, MVT::v4f32, 2, 0, 3,
- 21, MVT::v2f64,
- OPC_EmitInteger, MVT::i32, 2,
- OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
- 1, MVT::f64, 2, 1, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSDrr), 0,
- 1, MVT::v2f64, 2, 0, 3,
- 21, MVT::v4i32,
- OPC_EmitInteger, MVT::i32, 1,
- OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
- 1, MVT::f32, 2, 1, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSSrr), 0,
- 1, MVT::v4i32, 2, 0, 3,
- 21, MVT::v2i64,
- OPC_EmitInteger, MVT::i32, 2,
- OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
- 1, MVT::f64, 2, 1, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSDrr), 0,
- 1, MVT::v2i64, 2, 0, 3,
- 0,
- 56,
- OPC_CheckPredicate, 13,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_SwitchType , 23, MVT::v4f32,
- OPC_CheckPatternPredicate, 1,
- OPC_EmitInteger, MVT::i32, 2,
- OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
- 1, MVT::f64, 2, 1, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSDrr), 0,
- 1, MVT::v4f32, 2, 0, 3,
- 23, MVT::v4i32,
- OPC_CheckPatternPredicate, 1,
- OPC_EmitInteger, MVT::i32, 2,
- OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
- 1, MVT::f64, 2, 1, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSDrr), 0,
- 1, MVT::v4i32, 2, 0, 3,
- 0,
- 21,
- OPC_CheckPredicate, 41,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_CheckType, MVT::v2f64,
- OPC_CheckPatternPredicate, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKLPDrr), 0,
- 1, MVT::v2f64, 2, 0, 0,
- 21,
- OPC_CheckPredicate, 14,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_CheckType, MVT::v2f64,
- OPC_CheckPatternPredicate, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKHPDrr), 0,
- 1, MVT::v2f64, 2, 0, 0,
- 21,
- OPC_CheckPredicate, 41,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_CheckType, MVT::v2i64,
- OPC_CheckPatternPredicate, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLQDQrr), 0,
- 1, MVT::v2i64, 2, 0, 0,
- 21,
- OPC_CheckPredicate, 14,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_CheckType, MVT::v2i64,
- OPC_CheckPatternPredicate, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHQDQrr), 0,
- 1, MVT::v2i64, 2, 0, 0,
- 54,
- OPC_CheckPredicate, 39,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_SwitchType , 9, MVT::v4f32,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKLPSrr), 0,
- 1, MVT::v4f32, 2, 0, 0,
- 9, MVT::v16i8,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLBWrr), 0,
- 1, MVT::v16i8, 2, 0, 0,
- 9, MVT::v8i16,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLWDrr), 0,
- 1, MVT::v8i16, 2, 0, 0,
- 9, MVT::v4i32,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLDQrr), 0,
- 1, MVT::v4i32, 2, 0, 0,
- 0,
- 54,
- OPC_CheckPredicate, 40,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_SwitchType , 9, MVT::v4f32,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKHPSrr), 0,
- 1, MVT::v4f32, 2, 0, 0,
- 9, MVT::v16i8,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHBWrr), 0,
- 1, MVT::v16i8, 2, 0, 0,
- 9, MVT::v8i16,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHWDrr), 0,
- 1, MVT::v8i16, 2, 0, 0,
- 9, MVT::v4i32,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHDQrr), 0,
- 1, MVT::v4i32, 2, 0, 0,
- 0,
- 43,
- OPC_CheckPredicate, 42,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_SwitchType , 9, MVT::v8i8,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKLBWrr), 0,
- 1, MVT::v8i8, 2, 0, 0,
- 9, MVT::v4i16,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKLWDrr), 0,
- 1, MVT::v4i16, 2, 0, 0,
- 9, MVT::v2i32,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKLDQrr), 0,
- 1, MVT::v2i32, 2, 0, 0,
- 0,
- 43,
- OPC_CheckPredicate, 43,
+ 91|128,3,
OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_SwitchType , 9, MVT::v8i8,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKHBWrr), 0,
- 1, MVT::v8i8, 2, 0, 0,
- 9, MVT::v4i16,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKHWDrr), 0,
- 1, MVT::v4i16, 2, 0, 0,
- 9, MVT::v2i32,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKHDQrr), 0,
- 1, MVT::v2i32, 2, 0, 0,
+ OPC_Scope, 27|128,1,
+ OPC_RecordChild1,
+ OPC_Scope, 96,
+ OPC_CheckPredicate, 38,
+ OPC_SwitchType , 21, MVT::v4f32,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f32, 2, 1, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSSrr), 0,
+ 1, MVT::v4f32, 2, 0, 3,
+ 21, MVT::v2f64,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f64, 2, 1, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSDrr), 0,
+ 1, MVT::v2f64, 2, 0, 3,
+ 21, MVT::v4i32,
+ OPC_EmitInteger, MVT::i32, 1,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f32, 2, 1, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSSrr), 0,
+ 1, MVT::v4i32, 2, 0, 3,
+ 21, MVT::v2i64,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f64, 2, 1, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSDrr), 0,
+ 1, MVT::v2i64, 2, 0, 3,
+ 0,
+ 54,
+ OPC_CheckPredicate, 13,
+ OPC_SwitchType , 23, MVT::v4f32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f64, 2, 1, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSDrr), 0,
+ 1, MVT::v4f32, 2, 0, 3,
+ 23, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitInteger, MVT::i32, 2,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::f64, 2, 1, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSDrr), 0,
+ 1, MVT::v4i32, 2, 0, 3,
+ 0,
+ 0,
+ 117|128,1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_Scope, 15,
+ OPC_CheckPredicate, 41,
+ OPC_CheckType, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKLPDrr), 0,
+ 1, MVT::v2f64, 2, 0, 0,
+ 15,
+ OPC_CheckPredicate, 14,
+ OPC_CheckType, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKHPDrr), 0,
+ 1, MVT::v2f64, 2, 0, 0,
+ 15,
+ OPC_CheckPredicate, 41,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLQDQrr), 0,
+ 1, MVT::v2i64, 2, 0, 0,
+ 15,
+ OPC_CheckPredicate, 14,
+ OPC_CheckType, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHQDQrr), 0,
+ 1, MVT::v2i64, 2, 0, 0,
+ 48,
+ OPC_CheckPredicate, 39,
+ OPC_SwitchType , 9, MVT::v4f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKLPSrr), 0,
+ 1, MVT::v4f32, 2, 0, 0,
+ 9, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLBWrr), 0,
+ 1, MVT::v16i8, 2, 0, 0,
+ 9, MVT::v8i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLWDrr), 0,
+ 1, MVT::v8i16, 2, 0, 0,
+ 9, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLDQrr), 0,
+ 1, MVT::v4i32, 2, 0, 0,
+ 0,
+ 48,
+ OPC_CheckPredicate, 40,
+ OPC_SwitchType , 9, MVT::v4f32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKHPSrr), 0,
+ 1, MVT::v4f32, 2, 0, 0,
+ 9, MVT::v16i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHBWrr), 0,
+ 1, MVT::v16i8, 2, 0, 0,
+ 9, MVT::v8i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHWDrr), 0,
+ 1, MVT::v8i16, 2, 0, 0,
+ 9, MVT::v4i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHDQrr), 0,
+ 1, MVT::v4i32, 2, 0, 0,
+ 0,
+ 37,
+ OPC_CheckPredicate, 42,
+ OPC_SwitchType , 9, MVT::v8i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKLBWrr), 0,
+ 1, MVT::v8i8, 2, 0, 0,
+ 9, MVT::v4i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKLWDrr), 0,
+ 1, MVT::v4i16, 2, 0, 0,
+ 9, MVT::v2i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKLDQrr), 0,
+ 1, MVT::v2i32, 2, 0, 0,
+ 0,
+ 37,
+ OPC_CheckPredicate, 43,
+ OPC_SwitchType , 9, MVT::v8i8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKHBWrr), 0,
+ 1, MVT::v8i8, 2, 0, 0,
+ 9, MVT::v4i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKHWDrr), 0,
+ 1, MVT::v4i16, 2, 0, 0,
+ 9, MVT::v2i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKHDQrr), 0,
+ 1, MVT::v2i32, 2, 0, 0,
+ 0,
+ 0,
+ 67,
+ OPC_RecordChild1,
+ OPC_SwitchType , 30, MVT::v4f32,
+ OPC_Scope, 13,
+ OPC_CheckPredicate, 14,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKHPSrr), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 13,
+ OPC_CheckPredicate, 28,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKLPSrr), 0,
+ 1, MVT::v4f32, 2, 0, 1,
+ 0,
+ 30, MVT::v2f64,
+ OPC_Scope, 13,
+ OPC_CheckPredicate, 14,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKHPDrr), 0,
+ 1, MVT::v2f64, 2, 0, 1,
+ 13,
+ OPC_CheckPredicate, 28,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKLPDrr), 0,
+ 1, MVT::v2f64, 2, 0, 1,
+ 0,
+ 0,
0,
- 17,
- OPC_CheckPredicate, 14,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v4f32,
- OPC_CheckPatternPredicate, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKHPSrr), 0,
- 1, MVT::v4f32, 2, 0, 1,
- 17,
- OPC_CheckPredicate, 28,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v4f32,
- OPC_CheckPatternPredicate, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKLPSrr), 0,
- 1, MVT::v4f32, 2, 0, 1,
- 17,
- OPC_CheckPredicate, 14,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v2f64,
- OPC_CheckPatternPredicate, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKHPDrr), 0,
- 1, MVT::v2f64, 2, 0, 1,
- 17,
- OPC_CheckPredicate, 28,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v2f64,
- OPC_CheckPatternPredicate, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::UNPCKLPDrr), 0,
- 1, MVT::v2f64, 2, 0, 1,
36,
- OPC_CheckPredicate, 37,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::BUILD_VECTOR,
OPC_CheckPredicate, 44,
@@ -9489,18 +9133,19 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveParent,
+ OPC_CheckPredicate, 38,
OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ2DQrr), 0,
1, MVT::v2i64, 1, 0,
- 121,
+ 120,
OPC_RecordNode,
- OPC_Scope, 42,
- OPC_CheckPredicate, 26,
- OPC_RecordChild0,
+ OPC_RecordChild0,
+ OPC_Scope, 41,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::UNDEF,
OPC_MoveParent,
+ OPC_CheckPredicate, 26,
OPC_SwitchType , 14, MVT::v4i32,
OPC_CheckPatternPredicate, 1,
OPC_EmitNodeXForm, 0, 0,
@@ -9512,10 +9157,9 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::PSHUFDri), 0,
1, MVT::v4f32, 2, 1, 2,
0,
- 74,
- OPC_CheckPredicate, 45,
- OPC_RecordChild0,
+ 73,
OPC_RecordChild1,
+ OPC_CheckPredicate, 45,
OPC_SwitchType , 15, MVT::v4i32,
OPC_CheckPatternPredicate, 11,
OPC_EmitNodeXForm, 4, 0,
@@ -9538,120 +9182,106 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v16i8, 3, 2, 1, 3,
0,
0,
- 44,
- OPC_CheckPredicate, 37,
+ 46,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
OPC_RecordChild0,
- OPC_Scope, 16,
+ OPC_Scope, 18,
OPC_CheckChild0Type, MVT::f32,
OPC_MoveParent,
+ OPC_CheckPredicate, 38,
OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSSrr), 0,
1, MVT::v16i8, 2, 0, 1,
- 16,
+ 18,
OPC_CheckChild0Type, MVT::f64,
OPC_MoveParent,
+ OPC_CheckPredicate, 38,
OPC_CheckType, MVT::v16i8,
OPC_CheckPatternPredicate, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSDrr), 0,
1, MVT::v16i8, 2, 0, 1,
0,
- 53,
+ 45,
OPC_RecordNode,
- OPC_Scope, 24,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::UNDEF,
+ OPC_MoveParent,
+ OPC_CheckType, MVT::v8i16,
+ OPC_Scope, 16,
OPC_CheckPredicate, 29,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 1,
OPC_EmitNodeXForm, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::PSHUFHWri), 0,
1, MVT::v8i16, 2, 1, 2,
- 24,
+ 16,
OPC_CheckPredicate, 30,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_CheckType, MVT::v8i16,
OPC_CheckPatternPredicate, 1,
OPC_EmitNodeXForm, 2, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::PSHUFLWri), 0,
1, MVT::v8i16, 2, 1, 2,
0,
- 20,
- OPC_CheckPredicate, 23,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_CheckType, MVT::v4f32,
- OPC_CheckPatternPredicate, 9,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSHDUPrr), 0,
- 1, MVT::v4f32, 1, 0,
- 20,
- OPC_CheckPredicate, 25,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_CheckType, MVT::v4f32,
- OPC_CheckPatternPredicate, 9,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSLDUPrr), 0,
- 1, MVT::v4f32, 1, 0,
- 20,
- OPC_CheckPredicate, 27,
+ 52,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::UNDEF,
OPC_MoveParent,
- OPC_CheckType, MVT::v2f64,
- OPC_CheckPatternPredicate, 9,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVDDUPrr), 0,
- 1, MVT::v2f64, 1, 0,
- 1|128,1,
+ OPC_SwitchType , 28, MVT::v4f32,
+ OPC_Scope, 12,
+ OPC_CheckPredicate, 24,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSHDUPrr), 0,
+ 1, MVT::v4f32, 1, 0,
+ 12,
+ OPC_CheckPredicate, 25,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSLDUPrr), 0,
+ 1, MVT::v4f32, 1, 0,
+ 0,
+ 12, MVT::v2f64,
+ OPC_CheckPredicate, 27,
+ OPC_CheckPatternPredicate, 9,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVDDUPrr), 0,
+ 1, MVT::v2f64, 1, 0,
+ 0,
+ 125,
OPC_RecordNode,
- OPC_Scope, 59,
- OPC_CheckPredicate, 26,
- OPC_RecordChild0,
+ OPC_RecordChild0,
+ OPC_Scope, 80,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::UNDEF,
OPC_MoveParent,
- OPC_SwitchType , 13, MVT::v4f32,
- OPC_EmitNodeXForm, 0, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHUFPSrri), 0,
- 1, MVT::v4f32, 3, 1, 1, 2,
- 15, MVT::v2i64,
- OPC_CheckPatternPredicate, 1,
- OPC_EmitNodeXForm, 0, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHUFPDrri), 0,
- 1, MVT::v2i64, 3, 1, 1, 2,
- 15, MVT::v2f64,
- OPC_CheckPatternPredicate, 1,
- OPC_EmitNodeXForm, 0, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHUFPDrri), 0,
- 1, MVT::v2f64, 3, 1, 1, 2,
+ OPC_Scope, 53,
+ OPC_CheckPredicate, 26,
+ OPC_SwitchType , 13, MVT::v4f32,
+ OPC_EmitNodeXForm, 0, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHUFPSrri), 0,
+ 1, MVT::v4f32, 3, 1, 1, 2,
+ 15, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitNodeXForm, 0, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHUFPDrri), 0,
+ 1, MVT::v2i64, 3, 1, 1, 2,
+ 15, MVT::v2f64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_EmitNodeXForm, 0, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHUFPDrri), 0,
+ 1, MVT::v2f64, 3, 1, 1, 2,
+ 0,
+ 18,
+ OPC_CheckPredicate, 31,
+ OPC_CheckType, MVT::v4i16,
+ OPC_CheckPatternPredicate, 8,
+ OPC_EmitNodeXForm, 3, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSHUFWri), 0,
+ 1, MVT::v4i16, 2, 1, 2,
0,
- 24,
- OPC_CheckPredicate, 31,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::UNDEF,
- OPC_MoveParent,
- OPC_CheckType, MVT::v4i16,
- OPC_CheckPatternPredicate, 8,
- OPC_EmitNodeXForm, 3, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PSHUFWri), 0,
- 1, MVT::v4i16, 2, 1, 2,
- 40,
- OPC_CheckPredicate, 32,
- OPC_RecordChild0,
+ 39,
OPC_RecordChild1,
+ OPC_CheckPredicate, 32,
OPC_SwitchType , 15, MVT::v4f32,
OPC_CheckPatternPredicate, 0,
OPC_EmitNodeXForm, 0, 0,
@@ -9664,54 +9294,54 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v2f64, 3, 1, 2, 3,
0,
0,
- 58,
- OPC_CheckPredicate, 28,
+ 118,
OPC_RecordChild0,
OPC_RecordChild1,
- OPC_SwitchType , 11, MVT::v16i8,
- OPC_CheckPatternPredicate, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLBWrr), 0,
- 1, MVT::v16i8, 2, 0, 1,
- 11, MVT::v8i16,
- OPC_CheckPatternPredicate, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLWDrr), 0,
- 1, MVT::v8i16, 2, 0, 1,
- 11, MVT::v4i32,
- OPC_CheckPatternPredicate, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLDQrr), 0,
- 1, MVT::v4i32, 2, 0, 1,
- 11, MVT::v2i64,
- OPC_CheckPatternPredicate, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLQDQrr), 0,
- 1, MVT::v2i64, 2, 0, 1,
+ OPC_Scope, 56,
+ OPC_CheckPredicate, 28,
+ OPC_SwitchType , 11, MVT::v16i8,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLBWrr), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 11, MVT::v8i16,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLWDrr), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 11, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLDQrr), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 11, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKLQDQrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 0,
+ 56,
+ OPC_CheckPredicate, 14,
+ OPC_SwitchType , 11, MVT::v16i8,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHBWrr), 0,
+ 1, MVT::v16i8, 2, 0, 1,
+ 11, MVT::v8i16,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHWDrr), 0,
+ 1, MVT::v8i16, 2, 0, 1,
+ 11, MVT::v4i32,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHDQrr), 0,
+ 1, MVT::v4i32, 2, 0, 1,
+ 11, MVT::v2i64,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHQDQrr), 0,
+ 1, MVT::v2i64, 2, 0, 1,
+ 0,
0,
- 58,
- OPC_CheckPredicate, 14,
+ 62,
+ OPC_RecordNode,
OPC_RecordChild0,
OPC_RecordChild1,
- OPC_SwitchType , 11, MVT::v16i8,
- OPC_CheckPatternPredicate, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHBWrr), 0,
- 1, MVT::v16i8, 2, 0, 1,
- 11, MVT::v8i16,
- OPC_CheckPatternPredicate, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHWDrr), 0,
- 1, MVT::v8i16, 2, 0, 1,
- 11, MVT::v4i32,
- OPC_CheckPatternPredicate, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHDQrr), 0,
- 1, MVT::v4i32, 2, 0, 1,
- 11, MVT::v2i64,
- OPC_CheckPatternPredicate, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::PUNPCKHQDQrr), 0,
- 1, MVT::v2i64, 2, 0, 1,
- 0,
- 64,
- OPC_RecordNode,
- OPC_Scope, 40,
+ OPC_Scope, 38,
OPC_CheckPredicate, 32,
- OPC_RecordChild0,
- OPC_RecordChild1,
OPC_SwitchType , 15, MVT::v4i32,
OPC_CheckPatternPredicate, 1,
OPC_EmitNodeXForm, 0, 0,
@@ -9723,64 +9353,62 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::SHUFPDrri), 0,
1, MVT::v2i64, 3, 1, 2, 3,
0,
- 19,
+ 17,
OPC_CheckPredicate, 13,
- OPC_RecordChild0,
- OPC_RecordChild1,
OPC_CheckType, MVT::v4f32,
OPC_EmitNodeXForm, 0, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::SHUFPSrri), 0,
1, MVT::v4f32, 3, 2, 1, 3,
0,
- 45,
- OPC_CheckPredicate, 33,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_SwitchType , 11, MVT::v8i8,
- OPC_CheckPatternPredicate, 8,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKHBWrr), 0,
- 1, MVT::v8i8, 2, 0, 1,
- 11, MVT::v4i16,
- OPC_CheckPatternPredicate, 8,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKHWDrr), 0,
- 1, MVT::v4i16, 2, 0, 1,
- 11, MVT::v2i32,
- OPC_CheckPatternPredicate, 8,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKHDQrr), 0,
- 1, MVT::v2i32, 2, 0, 1,
- 0,
- 45,
- OPC_CheckPredicate, 34,
+ 92,
OPC_RecordChild0,
OPC_RecordChild1,
- OPC_SwitchType , 11, MVT::v8i8,
- OPC_CheckPatternPredicate, 8,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKLBWrr), 0,
- 1, MVT::v8i8, 2, 0, 1,
- 11, MVT::v4i16,
- OPC_CheckPatternPredicate, 8,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKLWDrr), 0,
- 1, MVT::v4i16, 2, 0, 1,
- 11, MVT::v2i32,
- OPC_CheckPatternPredicate, 8,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKLDQrr), 0,
- 1, MVT::v2i32, 2, 0, 1,
+ OPC_Scope, 43,
+ OPC_CheckPredicate, 33,
+ OPC_SwitchType , 11, MVT::v8i8,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKHBWrr), 0,
+ 1, MVT::v8i8, 2, 0, 1,
+ 11, MVT::v4i16,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKHWDrr), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 11, MVT::v2i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKHDQrr), 0,
+ 1, MVT::v2i32, 2, 0, 1,
+ 0,
+ 43,
+ OPC_CheckPredicate, 34,
+ OPC_SwitchType , 11, MVT::v8i8,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKLBWrr), 0,
+ 1, MVT::v8i8, 2, 0, 1,
+ 11, MVT::v4i16,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKLWDrr), 0,
+ 1, MVT::v4i16, 2, 0, 1,
+ 11, MVT::v2i32,
+ OPC_CheckPatternPredicate, 8,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PUNPCKLDQrr), 0,
+ 1, MVT::v2i32, 2, 0, 1,
+ 0,
0,
0,
- 95|128,5, X86ISD::VZEXT_MOVL,
- OPC_Scope, 113|128,4,
+ 83|128,5, X86ISD::VZEXT_MOVL,
+ OPC_Scope, 101|128,4,
OPC_MoveChild, 0,
- OPC_SwitchOpcode , 42|128,2, ISD::SCALAR_TO_VECTOR,
- OPC_Scope, 72|128,1,
+ OPC_SwitchOpcode , 30|128,2, ISD::SCALAR_TO_VECTOR,
+ OPC_Scope, 60|128,1,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 32,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 28,
+ OPC_CheckPredicate, 3,
OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_MoveParent,
@@ -9790,13 +9418,9 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZDI2PDIrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
- 34,
+ 30,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -9806,12 +9430,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZQI2PQIrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
- 32,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 28,
+ OPC_CheckPredicate, 3,
OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_MoveParent,
@@ -9821,13 +9441,9 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVZDI2PDIrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2i32, 5, 2, 3, 4, 5, 6,
- 90,
+ 86,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_SwitchType , 38, MVT::f32,
OPC_MoveParent,
OPC_MoveParent,
@@ -9896,12 +9512,12 @@ SDNode *SelectCode(SDNode *N) {
40|128,1, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_SwitchType , 80, MVT::v4f32,
OPC_MoveParent,
OPC_MoveParent,
@@ -9951,11 +9567,11 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v2i32, 5, 2, 3, 4, 5, 6,
0,
18|128,1, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_SwitchType , 18, MVT::v4i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -10028,17 +9644,17 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v2f64, 1, 0,
0,
0,
- 123|128,2, ISD::SCALAR_TO_VECTOR,
- OPC_Scope, 7|128,2,
+ 108|128,2, ISD::SCALAR_TO_VECTOR,
+ OPC_Scope, 120|128,1,
OPC_MoveChild, 0,
- OPC_SwitchOpcode , 59|128,1, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 87,
+ OPC_SwitchOpcode , 50|128,1, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 84,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_SwitchType , 37, MVT::f32,
OPC_MoveParent,
OPC_CheckType, MVT::v4f32,
@@ -10062,11 +9678,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::SUBREG_TO_REG), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2f64, 3, 7, 8, 9,
0,
- 30,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
+ 27,
+ OPC_CheckPredicate, 3,
OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_CheckType, MVT::v4i32,
@@ -10075,12 +9688,9 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVDI2PDIrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
- 32,
+ 29,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
@@ -10089,11 +9699,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVQI2PQIrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
- 30,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
+ 27,
+ OPC_CheckPredicate, 3,
OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_CheckType, MVT::v2i32,
@@ -10103,32 +9710,29 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVD64rm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2i32, 5, 2, 3, 4, 5, 6,
0,
- 67, ISD::BIT_CONVERT,
+ 61, ISD::BIT_CONVERT,
OPC_RecordChild0,
- OPC_Scope, 15,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 13,
OPC_CheckChild0Type, MVT::v8i8,
- OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ2DQrr), 0,
1, MVT::v2i64, 1, 0,
- 15,
+ 13,
OPC_CheckChild0Type, MVT::v4i16,
- OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ2DQrr), 0,
1, MVT::v2i64, 1, 0,
- 15,
+ 13,
OPC_CheckChild0Type, MVT::v2i32,
- OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ2DQrr), 0,
1, MVT::v2i64, 1, 0,
- 15,
+ 13,
OPC_CheckChild0Type, MVT::v1i64,
- OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ2DQrr), 0,
@@ -10177,66 +9781,51 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v2f64, 3, 1, 0, 2,
0,
0,
- 122|128,12, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 80|128,1,
- OPC_CheckPredicate, 9,
- OPC_Scope, 27,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
+ 90|128,11, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 62|128,1,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 24,
+ OPC_CheckPredicate, 9,
OPC_CheckType, MVT::f64,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSDrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f64, 5, 2, 3, 4, 5, 6,
- 25,
+ 22,
OPC_CheckPredicate, 46,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::GS_MOV32rm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 25,
+ 22,
OPC_CheckPredicate, 47,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::FS_MOV32rm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 25,
+ 22,
OPC_CheckPredicate, 46,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64GSrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 5, 2, 3, 4, 5, 6,
- 25,
+ 22,
OPC_CheckPredicate, 47,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64FSrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 5, 2, 3, 4, 5, 6,
- 71,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
+ 68,
+ OPC_CheckPredicate, 9,
OPC_SwitchType , 20, MVT::f32,
OPC_CheckPatternPredicate, 6,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -10256,78 +9845,56 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::f80, 5, 2, 3, 4, 5, 6,
0,
0,
- 84,
+ 74,
OPC_CheckPredicate, 48,
- OPC_Scope, 27,
+ OPC_SwitchType , 22, MVT::f64,
OPC_CheckPredicate, 49,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::f64,
OPC_CheckPatternPredicate, 7,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp32m64), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f64, 5, 2, 3, 4, 5, 6,
- 25,
- OPC_CheckPredicate, 50,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::f80,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp64m80), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::f80, 5, 2, 3, 4, 5, 6,
- 25,
- OPC_CheckPredicate, 49,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::f80,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp32m80), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::f80, 5, 2, 3, 4, 5, 6,
+ 44, MVT::f80,
+ OPC_Scope, 20,
+ OPC_CheckPredicate, 50,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp64m80), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f80, 5, 2, 3, 4, 5, 6,
+ 20,
+ OPC_CheckPredicate, 49,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp32m80), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::f80, 5, 2, 3, 4, 5, 6,
+ 0,
0,
- 27,
+ 24,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i8,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV8rm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i8, 5, 2, 3, 4, 5, 6,
- 25,
+ 22,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i16,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV16rm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i16, 5, 2, 3, 4, 5, 6,
- 25,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
+ 22,
+ OPC_CheckPredicate, 3,
OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV32rm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 78,
+ 72,
OPC_CheckPredicate, 51,
- OPC_Scope, 47,
+ OPC_Scope, 44,
OPC_CheckPredicate, 52,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_SwitchType , 18, MVT::i16,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
@@ -10339,24 +9906,18 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX32rm8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 5, 2, 3, 4, 5, 6,
0,
- 25,
+ 22,
OPC_CheckPredicate, 53,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX32rm16), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 5, 2, 3, 4, 5, 6,
0,
- 18|128,1,
+ 9|128,1,
OPC_CheckPredicate, 54,
- OPC_Scope, 47,
+ OPC_Scope, 44,
OPC_CheckPredicate, 55,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_SwitchType , 18, MVT::i16,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
@@ -10368,21 +9929,15 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX32rm8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 5, 2, 3, 4, 5, 6,
0,
- 25,
+ 22,
OPC_CheckPredicate, 56,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX32rm16), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 67,
+ 64,
OPC_CheckPredicate, 57,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_SwitchType , 18, MVT::i8,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
@@ -10400,13 +9955,10 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::i32, 5, 2, 3, 4, 5, 6,
0,
0,
- 18|128,1,
+ 9|128,1,
OPC_CheckPredicate, 48,
- OPC_Scope, 67,
+ OPC_Scope, 64,
OPC_CheckPredicate, 58,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_SwitchType , 18, MVT::i8,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
@@ -10423,11 +9975,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX32rm8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 5, 2, 3, 4, 5, 6,
0,
- 47,
+ 44,
OPC_CheckPredicate, 59,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_SwitchType , 18, MVT::i16,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
@@ -10439,220 +9988,153 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX32rm8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 5, 2, 3, 4, 5, 6,
0,
- 25,
+ 22,
OPC_CheckPredicate, 60,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX32rm16), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 5, 2, 3, 4, 5, 6,
0,
- 27,
+ 24,
OPC_CheckPredicate, 51,
OPC_CheckPredicate, 53,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX32rm16), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 27,
+ 24,
OPC_CheckPredicate, 54,
OPC_CheckPredicate, 56,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX32rm16), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 27,
+ 24,
OPC_CheckPredicate, 48,
OPC_CheckPredicate, 60,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX32rm16), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 5, 2, 3, 4, 5, 6,
- 25,
- OPC_CheckPredicate, 9,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
+ 22,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64rm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 5, 2, 3, 4, 5, 6,
- 82,
+ 69,
OPC_CheckPredicate, 51,
- OPC_Scope, 25,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 20,
OPC_CheckPredicate, 52,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX64rm8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 5, 2, 3, 4, 5, 6,
- 25,
+ 20,
OPC_CheckPredicate, 53,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX64rm16), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 5, 2, 3, 4, 5, 6,
- 25,
+ 20,
OPC_CheckPredicate, 61,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX64rm32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 5, 2, 3, 4, 5, 6,
0,
- 108,
+ 90,
OPC_CheckPredicate, 54,
- OPC_Scope, 25,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 20,
OPC_CheckPredicate, 55,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX64rm8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 5, 2, 3, 4, 5, 6,
- 25,
+ 20,
OPC_CheckPredicate, 56,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX64rm16), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 5, 2, 3, 4, 5, 6,
- 25,
+ 20,
OPC_CheckPredicate, 62,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX64rm32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 5, 2, 3, 4, 5, 6,
- 25,
+ 20,
OPC_CheckPredicate, 57,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX64rm8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 5, 2, 3, 4, 5, 6,
0,
- 82,
+ 69,
OPC_CheckPredicate, 48,
- OPC_Scope, 25,
+ OPC_CheckType, MVT::i64,
+ OPC_Scope, 20,
OPC_CheckPredicate, 58,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX64rm8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 5, 2, 3, 4, 5, 6,
- 25,
+ 20,
OPC_CheckPredicate, 59,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX64rm8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 5, 2, 3, 4, 5, 6,
- 25,
+ 20,
OPC_CheckPredicate, 60,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX64rm16), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 5, 2, 3, 4, 5, 6,
0,
- 27,
+ 24,
OPC_CheckPredicate, 51,
OPC_CheckPredicate, 53,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX64rm16), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 5, 2, 3, 4, 5, 6,
- 27,
+ 24,
OPC_CheckPredicate, 54,
OPC_CheckPredicate, 56,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX64rm16), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 5, 2, 3, 4, 5, 6,
- 27,
+ 24,
OPC_CheckPredicate, 48,
OPC_CheckPredicate, 60,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVZX64rm16), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 5, 2, 3, 4, 5, 6,
- 110,
- OPC_CheckPredicate, 9,
- OPC_Scope, 27,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
+ 101,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 24,
+ OPC_CheckPredicate, 9,
OPC_CheckType, MVT::f32,
OPC_CheckPatternPredicate, 0,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSSrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f32, 5, 2, 3, 4, 5, 6,
- 51,
+ 48,
OPC_CheckPredicate, 63,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_SwitchType , 20, MVT::f32,
OPC_CheckPatternPredicate, 0,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -10666,10 +10148,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVAPSrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v4f32, 5, 2, 3, 4, 5, 6,
0,
- 25,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
+ 22,
OPC_CheckType, MVT::v4f32,
OPC_CheckPatternPredicate, 0,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -10677,25 +10156,19 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPSrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v4f32, 5, 2, 3, 4, 5, 6,
0,
- 29,
+ 26,
OPC_CheckPredicate, 48,
OPC_CheckPredicate, 49,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::f64,
OPC_CheckPatternPredicate, 12,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CVTSS2SDrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f64, 5, 2, 3, 4, 5, 6,
- 78|128,1,
- OPC_CheckPredicate, 9,
- OPC_Scope, 51,
+ 61|128,1,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 48,
OPC_CheckPredicate, 63,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_SwitchType , 20, MVT::f64,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -10709,70 +10182,53 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVAPDrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2f64, 5, 2, 3, 4, 5, 6,
0,
- 25,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
+ 22,
OPC_CheckType, MVT::v2f64,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPDrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2f64, 5, 2, 3, 4, 5, 6,
- 25,
- OPC_CheckPredicate, 63,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v4i32,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVAPSrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
- 23,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
+ 44,
OPC_CheckType, MVT::v4i32,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPSrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
- 25,
- OPC_CheckPredicate, 63,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v2i64,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVAPSrm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
- 47,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_SwitchType , 18, MVT::v2i64,
+ OPC_Scope, 20,
+ OPC_CheckPredicate, 63,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVAPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
+ 18,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v4i32, 5, 2, 3, 4, 5, 6,
+ 0,
+ 44,
+ OPC_CheckType, MVT::v2i64,
+ OPC_Scope, 20,
+ OPC_CheckPredicate, 63,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVAPSrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
- 20, MVT::v1i64,
- OPC_CheckPatternPredicate, 8,
+ 18,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ64rm), 0|OPFL_Chain|OPFL_MemRefs,
- 1, MVT::v1i64, 5, 2, 3, 4, 5, 6,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVUPSrm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
0,
+ 22,
+ OPC_CheckType, MVT::v1i64,
+ OPC_CheckPatternPredicate, 8,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ64rm), 0|OPFL_Chain|OPFL_MemRefs,
+ 1, MVT::v1i64, 5, 2, 3, 4, 5, 6,
0,
- 85,
+ 77,
OPC_CheckPredicate, 48,
- OPC_Scope, 41,
+ OPC_SwitchType , 36, MVT::i64,
OPC_CheckPredicate, 64,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_EmitInteger, MVT::i64, 0,
@@ -10781,12 +10237,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitInteger, MVT::i32, 4,
OPC_MorphNodeTo, TARGET_OPCODE(TargetOpcode::SUBREG_TO_REG), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 3, 7, 8, 9,
- 38,
+ 33, MVT::f64,
OPC_CheckPredicate, 49,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::f64,
OPC_CheckPatternPredicate, 13,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
@@ -10830,13 +10282,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -10851,13 +10303,13 @@ SDNode *SelectCode(SDNode *N) {
41, ISD::SCALAR_TO_VECTOR,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
@@ -10899,13 +10351,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -10920,13 +10372,13 @@ SDNode *SelectCode(SDNode *N) {
41, ISD::SCALAR_TO_VECTOR,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
@@ -10968,13 +10420,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -10989,13 +10441,13 @@ SDNode *SelectCode(SDNode *N) {
41, ISD::SCALAR_TO_VECTOR,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
@@ -11037,13 +10489,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -11058,13 +10510,13 @@ SDNode *SelectCode(SDNode *N) {
41, ISD::SCALAR_TO_VECTOR,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
@@ -11106,13 +10558,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -11127,13 +10579,13 @@ SDNode *SelectCode(SDNode *N) {
41, ISD::SCALAR_TO_VECTOR,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
@@ -11175,13 +10627,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -11196,13 +10648,13 @@ SDNode *SelectCode(SDNode *N) {
41, ISD::SCALAR_TO_VECTOR,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
@@ -11244,12 +10696,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 5,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 3,
OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_MoveParent,
@@ -11264,12 +10716,12 @@ SDNode *SelectCode(SDNode *N) {
39, ISD::SCALAR_TO_VECTOR,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 5,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 3,
OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_CheckType, MVT::v4i32,
@@ -11299,12 +10751,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 5,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 3,
OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_MoveParent,
@@ -11319,12 +10771,12 @@ SDNode *SelectCode(SDNode *N) {
39, ISD::SCALAR_TO_VECTOR,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 5,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 3,
OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_CheckType, MVT::v4i32,
@@ -11354,12 +10806,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 5,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 3,
OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_MoveParent,
@@ -11374,12 +10826,12 @@ SDNode *SelectCode(SDNode *N) {
39, ISD::SCALAR_TO_VECTOR,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 5,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 3,
OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_CheckType, MVT::v4i32,
@@ -11409,12 +10861,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 5,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 3,
OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_MoveParent,
@@ -11429,12 +10881,12 @@ SDNode *SelectCode(SDNode *N) {
39, ISD::SCALAR_TO_VECTOR,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 5,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 3,
OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_CheckType, MVT::v4i32,
@@ -11464,12 +10916,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 5,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 3,
OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_MoveParent,
@@ -11484,12 +10936,12 @@ SDNode *SelectCode(SDNode *N) {
39, ISD::SCALAR_TO_VECTOR,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 65,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 65,
OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_CheckType, MVT::v4i32,
@@ -11519,12 +10971,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 5,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 3,
OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_MoveParent,
@@ -11539,12 +10991,12 @@ SDNode *SelectCode(SDNode *N) {
39, ISD::SCALAR_TO_VECTOR,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 65,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 65,
OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_CheckType, MVT::v4i32,
@@ -11571,13 +11023,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -11611,13 +11063,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -11651,13 +11103,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -11691,13 +11143,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -11716,13 +11168,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -11758,13 +11210,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -11783,13 +11235,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -11825,13 +11277,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -11850,13 +11302,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -11890,12 +11342,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 43,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_RecordChild3,
OPC_MoveChild, 3,
@@ -11925,13 +11377,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 45,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_RecordChild3,
OPC_MoveChild, 3,
@@ -11961,12 +11413,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 43,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_RecordChild3,
OPC_MoveChild, 3,
@@ -11997,13 +11449,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12026,13 +11478,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12054,13 +11506,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 45,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_RecordChild3,
OPC_MoveChild, 3,
@@ -12092,13 +11544,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12112,13 +11564,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12144,13 +11596,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12164,13 +11616,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12196,13 +11648,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12216,13 +11668,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12248,13 +11700,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12268,13 +11720,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12300,13 +11752,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12330,13 +11782,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12360,13 +11812,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12390,13 +11842,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12420,13 +11872,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12440,13 +11892,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12472,13 +11924,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12492,13 +11944,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12524,13 +11976,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12544,13 +11996,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12576,13 +12028,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12596,13 +12048,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12628,13 +12080,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12648,13 +12100,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12680,13 +12132,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12700,13 +12152,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12732,13 +12184,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12752,13 +12204,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12784,13 +12236,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12804,13 +12256,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12836,13 +12288,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12856,13 +12308,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12888,13 +12340,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12908,13 +12360,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12940,13 +12392,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12960,13 +12412,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -12992,13 +12444,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -13022,13 +12474,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -13052,13 +12504,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -13082,13 +12534,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -13112,13 +12564,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -13142,13 +12594,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -13172,13 +12624,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -13202,13 +12654,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -13232,13 +12684,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -13262,13 +12714,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -13292,13 +12744,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -13322,13 +12774,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -13352,13 +12804,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -13382,13 +12834,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -13412,13 +12864,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -13442,13 +12894,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -13472,13 +12924,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -13501,13 +12953,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 66,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 66,
OPC_CheckType, MVT::v8i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -13530,13 +12982,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -13559,13 +13011,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 66,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 66,
OPC_CheckType, MVT::v4i16,
OPC_MoveParent,
OPC_MoveParent,
@@ -13588,13 +13040,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 66,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 66,
OPC_CheckType, MVT::v8i16,
OPC_MoveParent,
OPC_MoveParent,
@@ -13617,13 +13069,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 66,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 66,
OPC_CheckType, MVT::v2i32,
OPC_MoveParent,
OPC_MoveParent,
@@ -13646,13 +13098,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v4i32,
OPC_MoveParent,
OPC_MoveParent,
@@ -13676,13 +13128,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 66,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 66,
OPC_CheckType, MVT::v4i16,
OPC_MoveParent,
OPC_MoveParent,
@@ -13706,13 +13158,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 66,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 66,
OPC_CheckType, MVT::v8i16,
OPC_MoveParent,
OPC_MoveParent,
@@ -13736,13 +13188,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 66,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 66,
OPC_CheckType, MVT::v2i32,
OPC_MoveParent,
OPC_MoveParent,
@@ -13766,13 +13218,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v4i32,
OPC_MoveParent,
OPC_MoveParent,
@@ -13796,13 +13248,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 66,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 66,
OPC_CheckType, MVT::v4i16,
OPC_MoveParent,
OPC_MoveParent,
@@ -13826,13 +13278,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 66,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 66,
OPC_CheckType, MVT::v8i16,
OPC_MoveParent,
OPC_MoveParent,
@@ -13856,13 +13308,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 66,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 66,
OPC_CheckType, MVT::v4i16,
OPC_MoveParent,
OPC_MoveParent,
@@ -13886,13 +13338,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 66,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 66,
OPC_CheckType, MVT::v8i16,
OPC_MoveParent,
OPC_MoveParent,
@@ -13916,13 +13368,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 66,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 66,
OPC_CheckType, MVT::v2i32,
OPC_MoveParent,
OPC_MoveParent,
@@ -13946,13 +13398,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v4i32,
OPC_MoveParent,
OPC_MoveParent,
@@ -13976,13 +13428,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 66,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 66,
OPC_CheckType, MVT::v4i16,
OPC_MoveParent,
OPC_MoveParent,
@@ -14006,13 +13458,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 66,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 66,
OPC_CheckType, MVT::v8i16,
OPC_MoveParent,
OPC_MoveParent,
@@ -14036,13 +13488,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 66,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 66,
OPC_CheckType, MVT::v8i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -14066,13 +13518,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -14096,13 +13548,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 66,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 66,
OPC_CheckType, MVT::v4i16,
OPC_MoveParent,
OPC_MoveParent,
@@ -14116,13 +13568,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 66,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 66,
OPC_CheckType, MVT::v4i16,
OPC_MoveParent,
OPC_MoveParent,
@@ -14148,13 +13600,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 66,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 66,
OPC_CheckType, MVT::v8i16,
OPC_MoveParent,
OPC_MoveParent,
@@ -14168,13 +13620,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 66,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 66,
OPC_CheckType, MVT::v8i16,
OPC_MoveParent,
OPC_MoveParent,
@@ -14200,13 +13652,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 66,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 66,
OPC_CheckType, MVT::v8i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -14230,13 +13682,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -14260,13 +13712,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 66,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 66,
OPC_CheckType, MVT::v8i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -14290,13 +13742,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -14320,13 +13772,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 66,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 66,
OPC_CheckType, MVT::v4i16,
OPC_MoveParent,
OPC_MoveParent,
@@ -14350,13 +13802,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 66,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 66,
OPC_CheckType, MVT::v8i16,
OPC_MoveParent,
OPC_MoveParent,
@@ -14380,13 +13832,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 66,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 66,
OPC_CheckType, MVT::v2i32,
OPC_MoveParent,
OPC_MoveParent,
@@ -14410,13 +13862,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v4i32,
OPC_MoveParent,
OPC_MoveParent,
@@ -14438,13 +13890,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 48,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 66,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 66,
OPC_MoveParent,
OPC_RecordChild3,
OPC_MoveChild, 3,
@@ -14476,13 +13928,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 48,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_RecordChild3,
OPC_MoveChild, 3,
@@ -14513,13 +13965,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 44,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_RecordChild2,
OPC_MoveChild, 2,
@@ -14548,13 +14000,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 44,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_RecordChild2,
OPC_MoveChild, 2,
@@ -14585,13 +14037,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 66,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 66,
OPC_CheckType, MVT::v8i16,
OPC_MoveParent,
OPC_MoveParent,
@@ -14615,13 +14067,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -14635,13 +14087,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -14667,13 +14119,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -14697,13 +14149,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -14717,13 +14169,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -14749,13 +14201,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -14769,13 +14221,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -14801,13 +14253,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -14821,13 +14273,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -14853,13 +14305,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -14873,13 +14325,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -14905,13 +14357,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -14925,13 +14377,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -14957,13 +14409,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -14977,13 +14429,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -15009,13 +14461,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -15029,13 +14481,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -15061,13 +14513,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -15081,13 +14533,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -15113,13 +14565,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -15133,13 +14585,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -15165,13 +14617,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -15199,13 +14651,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -15233,13 +14685,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -15267,13 +14719,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v16i8,
OPC_MoveParent,
OPC_MoveParent,
@@ -15295,12 +14747,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 44,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_RecordChild3,
OPC_MoveChild, 3,
@@ -15330,12 +14782,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 44,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_RecordChild3,
OPC_MoveChild, 3,
@@ -15365,12 +14817,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 44,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_RecordChild3,
OPC_MoveChild, 3,
@@ -15400,12 +14852,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 44,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_RecordChild3,
OPC_MoveChild, 3,
@@ -15435,12 +14887,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 44,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_RecordChild3,
OPC_MoveChild, 3,
@@ -15470,12 +14922,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 44,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_RecordChild3,
OPC_MoveChild, 3,
@@ -15506,12 +14958,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 51,
OPC_MoveChild, 3,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_RecordChild4,
OPC_RecordChild5,
@@ -15548,12 +15000,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 51,
OPC_MoveChild, 3,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_RecordChild4,
OPC_RecordChild5,
@@ -15590,12 +15042,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 51,
OPC_MoveChild, 3,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_RecordChild4,
OPC_RecordChild5,
@@ -15632,12 +15084,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 51,
OPC_MoveChild, 3,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_RecordChild4,
OPC_RecordChild5,
@@ -15674,12 +15126,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 51,
OPC_MoveChild, 3,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_RecordChild4,
OPC_RecordChild5,
@@ -15716,12 +15168,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 51,
OPC_MoveChild, 3,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_RecordChild4,
OPC_RecordChild5,
@@ -15759,12 +15211,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -15778,12 +15230,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -15809,12 +15261,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -15828,12 +15280,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -15859,12 +15311,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -15878,12 +15330,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -15909,12 +15361,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -15928,12 +15380,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -15959,12 +15411,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -15988,12 +15440,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16017,12 +15469,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16046,12 +15498,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16075,12 +15527,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16094,12 +15546,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16125,12 +15577,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16144,12 +15596,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16175,12 +15627,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16194,12 +15646,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16225,12 +15677,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16244,12 +15696,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16275,12 +15727,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16294,12 +15746,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16325,12 +15777,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16344,12 +15796,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16375,12 +15827,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16394,12 +15846,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16425,12 +15877,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16444,12 +15896,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16475,12 +15927,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16494,12 +15946,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16525,12 +15977,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16544,12 +15996,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16575,12 +16027,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16594,12 +16046,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16625,12 +16077,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16654,12 +16106,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16683,12 +16135,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16712,12 +16164,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16741,12 +16193,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16770,12 +16222,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16799,12 +16251,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16828,12 +16280,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16857,12 +16309,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16886,12 +16338,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16915,12 +16367,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16944,12 +16396,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -16973,12 +16425,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -17002,12 +16454,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -17031,12 +16483,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -17060,12 +16512,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -17089,12 +16541,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -17116,12 +16568,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 43,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_RecordChild3,
OPC_MoveChild, 3,
@@ -17152,12 +16604,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 50,
OPC_MoveChild, 3,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_RecordChild4,
OPC_RecordChild5,
@@ -17192,12 +16644,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 33,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -17216,12 +16668,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 33,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -17241,13 +16693,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 36,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
OPC_MoveParent,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -17267,13 +16719,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 36,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
OPC_MoveParent,
OPC_CheckPatternPredicate, 0,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -17292,12 +16744,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 33,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckPatternPredicate, 0,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -17316,12 +16768,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 33,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckPatternPredicate, 0,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -17340,12 +16792,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 33,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckPatternPredicate, 0,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -17364,12 +16816,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 33,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckPatternPredicate, 0,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -17388,12 +16840,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 33,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckPatternPredicate, 0,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -17413,12 +16865,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 34,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckPatternPredicate, 0,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -17437,12 +16889,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 33,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckPatternPredicate, 0,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -17462,12 +16914,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 34,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 5,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_CheckPatternPredicate, 0,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -17487,13 +16939,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 36,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckPatternPredicate, 0,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -17513,13 +16965,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 36,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckPatternPredicate, 0,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -17538,13 +16990,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 35,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckPatternPredicate, 0,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -17563,13 +17015,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 35,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckPatternPredicate, 0,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -17588,13 +17040,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 35,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckPatternPredicate, 0,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -17613,12 +17065,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 33,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -17637,13 +17089,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 35,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -17662,13 +17114,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 35,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -17687,12 +17139,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 33,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -17711,12 +17163,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 33,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -17736,13 +17188,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 36,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -17762,13 +17214,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 36,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -17787,13 +17239,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 35,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -17812,13 +17264,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 35,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -17837,13 +17289,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 35,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -17862,13 +17314,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 35,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -17887,12 +17339,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 33,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -17911,13 +17363,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 35,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -17937,12 +17389,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 34,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 5,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -17962,12 +17414,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 34,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -17987,12 +17439,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 34,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -18011,13 +17463,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 35,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -18037,13 +17489,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 36,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckPatternPredicate, 9,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -18063,13 +17515,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 36,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckPatternPredicate, 9,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -18089,13 +17541,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 36,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckPatternPredicate, 9,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -18115,13 +17567,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 36,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckPatternPredicate, 9,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -18141,13 +17593,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 36,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckPatternPredicate, 9,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -18167,13 +17619,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 36,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckPatternPredicate, 9,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -18193,13 +17645,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_RecordChild1,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckPatternPredicate, 4,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -18209,13 +17661,13 @@ SDNode *SelectCode(SDNode *N) {
37,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_RecordChild2,
OPC_CheckPatternPredicate, 4,
@@ -18237,12 +17689,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 34,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckPatternPredicate, 14,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -18262,12 +17714,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 34,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckPatternPredicate, 14,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -18287,12 +17739,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 34,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckPatternPredicate, 14,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -18312,12 +17764,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 34,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckPatternPredicate, 14,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -18891,10 +18343,10 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMOVMSKBrr), 0,
1, MVT::i32, 1, 0,
0,
- 1|128,33, ISD::AND,
- OPC_Scope, 14|128,15,
+ 65|128,32, ISD::AND,
+ OPC_Scope, 118|128,14,
OPC_MoveChild, 0,
- OPC_SwitchOpcode , 41|128,7, ISD::XOR,
+ OPC_SwitchOpcode , 33|128,7, ISD::XOR,
OPC_Scope, 45|128,1,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::BIT_CONVERT,
@@ -18913,13 +18365,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 0,
@@ -18942,13 +18394,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 0,
@@ -18967,13 +18419,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 1,
@@ -18995,13 +18447,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 1,
@@ -19015,13 +18467,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 1,
@@ -19035,13 +18487,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 1,
@@ -19055,12 +18507,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckType, MVT::v1i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -19076,12 +18528,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckType, MVT::v1i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -19094,12 +18546,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckType, MVT::v1i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -19121,13 +18573,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 1,
@@ -19146,13 +18598,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 1,
@@ -19167,13 +18619,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 1,
@@ -19188,13 +18640,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 1,
@@ -19209,12 +18661,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckType, MVT::v1i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -19231,12 +18683,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckType, MVT::v1i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -19250,12 +18702,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckType, MVT::v1i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -19265,7 +18717,7 @@ SDNode *SelectCode(SDNode *N) {
0,
0,
0,
- 79,
+ 75,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::BUILD_VECTOR,
@@ -19274,14 +18726,14 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_Scope, 30,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 26,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 1,
@@ -19289,11 +18741,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
- 28,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 24,
OPC_MoveParent,
OPC_CheckType, MVT::v1i64,
OPC_CheckPatternPredicate, 8,
@@ -19302,7 +18750,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v1i64, 6, 0, 3, 4, 5, 6, 7,
0,
- 79,
+ 75,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::BUILD_VECTOR,
OPC_CheckPredicate, 67,
@@ -19311,14 +18759,14 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_Scope, 30,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 26,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 1,
@@ -19326,11 +18774,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
- 28,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 24,
OPC_MoveParent,
OPC_CheckType, MVT::v1i64,
OPC_CheckPatternPredicate, 8,
@@ -19340,15 +18784,15 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v1i64, 6, 0, 3, 4, 5, 6, 7,
0,
0,
- 2|128,7, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_Scope, 38|128,3,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 114|128,6, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 34|128,3,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::XOR,
@@ -19528,11 +18972,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
0,
- 111|128,1,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 107|128,1,
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::XOR,
@@ -19633,12 +19073,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v1i64, 6, 2, 3, 4, 5, 6, 7,
0,
- 79,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 75,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::XOR,
@@ -19669,11 +19105,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
0,
- 77,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 73,
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::XOR,
@@ -19704,12 +19136,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PANDNrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v1i64, 6, 2, 3, 4, 5, 6, 7,
0,
- 68,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 64,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::BIT_CONVERT,
@@ -19741,13 +19169,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 0,
@@ -19760,13 +19188,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 1,
@@ -19776,67 +19204,51 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
0,
0,
- 66|128,1,
+ 46|128,1,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 31,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::i8,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i8, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
- 29,
+ 25,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::i16,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i16, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
- 29,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 25,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i32, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
- 92,
- OPC_CheckPredicate, 9,
- OPC_Scope, 27,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 80,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 23,
OPC_MoveParent,
OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i64, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
- 30,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 26,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 1,
@@ -19844,11 +19256,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
- 28,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 24,
OPC_MoveParent,
OPC_CheckType, MVT::v1i64,
OPC_CheckPatternPredicate, 8,
@@ -19858,17 +19266,17 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v1i64, 6, 0, 3, 4, 5, 6, 7,
0,
0,
- 71|128,1,
+ 51|128,1,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 32,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 28,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::i8,
@@ -19876,12 +19284,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i8, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
- 30,
+ 26,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::i16,
@@ -19889,12 +19293,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i16, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
- 30,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 26,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::i32,
@@ -19902,13 +19302,9 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i32, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
- 95,
- OPC_CheckPredicate, 9,
- OPC_Scope, 28,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 83,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 24,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::i64,
@@ -19916,12 +19312,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i64, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
- 31,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 27,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::v2i64,
@@ -19930,11 +19322,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::PANDrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
- 29,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 25,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::v1i64,
@@ -19949,12 +19337,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckAndImm, 127|128,1,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::SRL,
- OPC_CheckPredicate, 16,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckInteger, 8,
OPC_CheckType, MVT::i8,
OPC_MoveParent,
+ OPC_CheckPredicate, 15,
OPC_MoveParent,
OPC_SwitchType , 72, MVT::i32,
OPC_Scope, 34,
@@ -20784,21 +20172,21 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v1i64, 2, 0, 1,
0,
0,
- 109|128,12, X86ISD::CMP,
- OPC_Scope, 83|128,6,
+ 42|128,12, X86ISD::CMP,
+ OPC_Scope, 23|128,6,
OPC_MoveChild, 0,
- OPC_SwitchOpcode , 108|128,3, ISD::AND,
- OPC_Scope, 47|128,1,
+ OPC_SwitchOpcode , 76|128,3, ISD::AND,
+ OPC_Scope, 39|128,1,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 80,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 76,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 1,
@@ -20829,12 +20217,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST8mi), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
0,
- 42,
+ 38,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 1,
@@ -20850,12 +20234,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitConvertToTarget, 2,
OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST16mi), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
- 42,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 38,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 1,
@@ -20872,18 +20252,18 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST32mi), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
0,
- 25|128,1,
+ 13|128,1,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 36,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 32,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::i8,
OPC_MoveParent,
@@ -20894,12 +20274,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST8rm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
- 34,
+ 30,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::i16,
OPC_MoveParent,
@@ -20910,12 +20286,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST16rm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
- 34,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 30,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_CheckType, MVT::i32,
OPC_MoveParent,
@@ -20926,13 +20298,9 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST32rm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
- 36,
+ 32,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::i64,
OPC_MoveParent,
@@ -20944,17 +20312,17 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST64rm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
0,
- 28|128,1,
+ 16|128,1,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 37,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 33,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::i8,
@@ -20966,12 +20334,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST8rm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
- 35,
+ 31,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::i16,
@@ -20983,12 +20347,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST16rm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
- 35,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 31,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::i32,
@@ -21000,13 +20360,9 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST32rm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
- 37,
+ 33,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::i64,
@@ -21020,14 +20376,14 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
0,
0,
- 93|128,2, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 38,
+ 65|128,2, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 34,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i16,
OPC_MoveParent,
OPC_RecordChild1,
@@ -21040,12 +20396,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitConvertToTarget, 2,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP16mi8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
- 38,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 34,
+ OPC_CheckPredicate, 3,
OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_RecordChild1,
@@ -21058,13 +20410,9 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitConvertToTarget, 2,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP32mi8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
- 100,
+ 96,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_SwitchType , 58, MVT::i64,
OPC_MoveParent,
OPC_RecordChild1,
@@ -21099,12 +20447,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP8mi), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
0,
- 36,
+ 32,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i16,
OPC_MoveParent,
OPC_RecordChild1,
@@ -21116,12 +20460,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitConvertToTarget, 2,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP16mi), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
- 36,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 32,
+ OPC_CheckPredicate, 3,
OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_RecordChild1,
@@ -21133,13 +20473,9 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitConvertToTarget, 2,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP32mi), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
- 31,
+ 27,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i8,
OPC_MoveParent,
OPC_RecordChild1,
@@ -21147,12 +20483,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP8mr), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 3, 4, 5, 6, 7, 2,
- 29,
+ 25,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_CheckType, MVT::i16,
OPC_MoveParent,
OPC_RecordChild1,
@@ -21160,12 +20492,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMP16mr), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 3, 4, 5, 6, 7, 2,
- 29,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 25,
+ OPC_CheckPredicate, 3,
OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_RecordChild1,
@@ -21181,13 +20509,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckChild0Type, MVT::i8,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
OPC_MoveParent,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 1,
@@ -21197,12 +20525,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckChild0Type, MVT::i16,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 6,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 6,
OPC_MoveParent,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 1,
@@ -21212,12 +20540,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckChild0Type, MVT::i32,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 5,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 1,
@@ -21227,13 +20555,13 @@ SDNode *SelectCode(SDNode *N) {
37,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_RecordChild1,
@@ -21247,13 +20575,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckChild0Type, MVT::i64,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
OPC_MoveParent,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 1,
@@ -21263,13 +20591,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckChild0Type, MVT::f32,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
OPC_MoveParent,
OPC_CheckPatternPredicate, 0,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -21280,13 +20608,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckChild0Type, MVT::f64,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
OPC_MoveParent,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -21294,60 +20622,56 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::UCOMISDrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
0,
- 54|128,1,
+ 47|128,1,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::AND,
- OPC_Scope, 68,
- OPC_CheckPredicate, 70,
- OPC_RecordChild0,
- OPC_RecordChild1,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_Scope, 92,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::Constant,
- OPC_MoveParent,
- OPC_SwitchType , 17, MVT::i8,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 0,
- OPC_MoveParent,
- OPC_EmitConvertToTarget, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST8ri), 0,
- 1, MVT::i32, 2, 0, 2,
- 17, MVT::i16,
+ OPC_Scope, 62,
OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 0,
+ OPC_CheckPredicate, 70,
+ OPC_SwitchType , 17, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST8ri), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 17, MVT::i16,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST16ri), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 17, MVT::i32,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckInteger, 0,
+ OPC_MoveParent,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST32ri), 0,
+ 1, MVT::i32, 2, 0, 2,
+ 0,
+ 22,
+ OPC_CheckPredicate, 12,
OPC_MoveParent,
- OPC_EmitConvertToTarget, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST16ri), 0,
- 1, MVT::i32, 2, 0, 2,
- 17, MVT::i32,
+ OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckInteger, 0,
OPC_MoveParent,
OPC_EmitConvertToTarget, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST32ri), 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST64ri32), 0,
1, MVT::i32, 2, 0, 2,
0,
- 28,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckPredicate, 12,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckInteger, 0,
- OPC_MoveParent,
- OPC_EmitConvertToTarget, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST64ri32), 0,
- 1, MVT::i32, 2, 0, 2,
- 57,
+ 55,
OPC_CheckPredicate, 70,
- OPC_RecordChild0,
- OPC_RecordChild1,
OPC_SwitchType , 15, MVT::i8,
OPC_MoveParent,
OPC_MoveChild, 1,
@@ -21370,9 +20694,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::TEST32rr), 0,
1, MVT::i32, 2, 0, 1,
0,
- 19,
- OPC_RecordChild0,
- OPC_RecordChild1,
+ 17,
OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_MoveChild, 1,
@@ -21534,13 +20856,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
OPC_CheckType, MVT::f32,
OPC_MoveParent,
OPC_MoveParent,
@@ -21572,12 +20894,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::ANY_EXTEND,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 6,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 6,
OPC_CheckType, MVT::i16,
OPC_MoveParent,
OPC_MoveParent,
@@ -21610,12 +20932,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::SCALAR_TO_VECTOR,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 5,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 3,
OPC_CheckType, MVT::i32,
OPC_MoveParent,
OPC_CheckType, MVT::v2i32,
@@ -21626,11 +20948,11 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVDI2PDIrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2i64, 5, 2, 3, 4, 5, 6,
26, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
@@ -21642,18 +20964,18 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_MOVQ2DQrr), 0,
1, MVT::v2i64, 1, 0,
0,
- 17|128,37, X86ISD::CMOV,
- OPC_Scope, 73|128,9,
+ 25|128,35, X86ISD::CMOV,
+ OPC_Scope, 77|128,8,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 37,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 33,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 2,
@@ -21665,12 +20987,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVB16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
- 37,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 33,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 2,
@@ -21682,12 +21000,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVB32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
- 37,
+ 33,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 1,
@@ -21699,12 +21013,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVAE16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
- 37,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 33,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 1,
@@ -21716,12 +21026,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVAE32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
- 37,
+ 33,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 4,
@@ -21733,12 +21039,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVE16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
- 37,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 33,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 4,
@@ -21750,12 +21052,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVE32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
- 37,
+ 33,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 9,
@@ -21767,12 +21065,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNE16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
- 37,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 33,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 9,
@@ -21784,12 +21078,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNE32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
- 37,
+ 33,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 3,
@@ -21801,12 +21091,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVBE16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
- 37,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 33,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 3,
@@ -21818,12 +21104,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVBE32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
- 37,
+ 33,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 0,
@@ -21835,12 +21117,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVA16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
- 37,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 33,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 0,
@@ -21852,12 +21130,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVA32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
- 37,
+ 33,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 7,
@@ -21869,12 +21143,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVL16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
- 37,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 33,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 7,
@@ -21886,12 +21156,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVL32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
- 37,
+ 33,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 6,
@@ -21903,12 +21169,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVGE16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
- 37,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 33,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 6,
@@ -21920,12 +21182,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVGE32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
- 37,
+ 33,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 8,
@@ -21937,12 +21195,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVLE16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
- 37,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 33,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 8,
@@ -21954,12 +21208,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVLE32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
- 37,
+ 33,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 5,
@@ -21971,12 +21221,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVG16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
- 37,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 33,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 5,
@@ -21988,12 +21234,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVG32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
- 37,
+ 33,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 15,
@@ -22005,12 +21247,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVS16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
- 37,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 33,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 15,
@@ -22022,12 +21260,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVS32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
- 37,
+ 33,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 12,
@@ -22039,12 +21273,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNS16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
- 37,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 33,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 12,
@@ -22056,12 +21286,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNS32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
- 37,
+ 33,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 14,
@@ -22073,12 +21299,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVP16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
- 37,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 33,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 14,
@@ -22090,12 +21312,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVP32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
- 37,
+ 33,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 11,
@@ -22107,12 +21325,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNP16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
- 37,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 33,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 11,
@@ -22124,12 +21338,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNP32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
- 37,
+ 33,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 13,
@@ -22141,12 +21351,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVO16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
- 37,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 33,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 13,
@@ -22158,12 +21364,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVO32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
- 37,
+ 33,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 10,
@@ -22175,12 +21377,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNO16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 0, 4, 5, 6, 7, 8,
- 37,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 33,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 10,
@@ -22193,16 +21391,16 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNO32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 0, 4, 5, 6, 7, 8,
0,
- 104|128,9,
+ 108|128,8,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 38,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 34,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22215,12 +21413,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVAE16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
- 38,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 34,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22233,12 +21427,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVAE32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
- 38,
+ 34,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22251,12 +21441,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVB16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
- 38,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 34,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22269,12 +21455,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVB32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
- 38,
+ 34,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22287,12 +21469,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNE16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
- 38,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 34,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22305,12 +21483,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNE32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
- 38,
+ 34,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22323,12 +21497,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVE16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
- 38,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 34,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22341,12 +21511,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVE32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
- 38,
+ 34,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22359,12 +21525,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVA16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
- 38,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 34,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22377,12 +21539,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVA32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
- 38,
+ 34,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22395,12 +21553,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVBE16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
- 38,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 34,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22413,12 +21567,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVBE32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
- 38,
+ 34,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22431,12 +21581,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVGE16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
- 38,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 34,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22449,12 +21595,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVGE32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
- 38,
+ 34,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22467,12 +21609,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVL16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
- 38,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 34,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22485,12 +21623,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVL32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
- 38,
+ 34,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22503,12 +21637,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVG16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
- 38,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 34,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22521,12 +21651,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVG32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
- 38,
+ 34,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22539,12 +21665,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVLE16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
- 38,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 34,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22557,12 +21679,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVLE32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
- 38,
+ 34,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22575,12 +21693,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNP16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
- 38,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 34,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22593,12 +21707,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNP32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
- 38,
+ 34,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22611,12 +21721,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVP16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
- 38,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 34,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22629,12 +21735,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVP32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
- 38,
+ 34,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22647,12 +21749,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNS16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
- 38,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 34,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22665,12 +21763,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNS32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
- 38,
+ 34,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22683,12 +21777,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVS16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
- 38,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 34,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22701,12 +21791,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVS32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
- 38,
+ 34,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22719,12 +21805,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNO16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
- 38,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 34,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22737,12 +21819,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVNO32rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i32, 6, 2, 4, 5, 6, 7, 8,
- 38,
+ 34,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22755,12 +21833,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 3, X86::EFLAGS,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMOVO16rm), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
1, MVT::i16, 6, 2, 4, 5, 6, 7, 8,
- 38,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 34,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -22778,13 +21852,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_Scope, 28,
@@ -22951,13 +22025,13 @@ SDNode *SelectCode(SDNode *N) {
100|128,3,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 2,
@@ -23556,16 +22630,16 @@ SDNode *SelectCode(SDNode *N) {
0,
0,
0,
- 112|128,6, ISD::MUL,
+ 88|128,6, ISD::MUL,
OPC_Scope, 50|128,1,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 1,
@@ -23617,21 +22691,20 @@ SDNode *SelectCode(SDNode *N) {
2, MVT::i32, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
0,
0,
- 81,
+ 75,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_Scope, 33,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v2i64,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_SwitchType , 27, MVT::v2i64,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_MoveParent,
OPC_CheckType, MVT::v8i16,
@@ -23640,12 +22713,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULLWrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v8i16, 6, 0, 3, 4, 5, 6, 7,
- 31,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v1i64,
+ 25, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
OPC_CheckType, MVT::v4i16,
@@ -23655,20 +22723,19 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMULLWrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
0,
- 82,
+ 76,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_Scope, 34,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v2i64,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_SwitchType , 28, MVT::v2i64,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_MoveParent,
OPC_RecordChild1,
@@ -23678,12 +22745,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULLWrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v8i16, 6, 2, 3, 4, 5, 6, 7,
- 32,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v1i64,
+ 26, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
OPC_RecordChild1,
@@ -23694,18 +22756,18 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PMULLWrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v4i16, 6, 2, 3, 4, 5, 6, 7,
0,
- 20|128,1,
+ 12|128,1,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_Scope, 31,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 9,
OPC_MoveParent,
OPC_CheckType, MVT::i8,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -23713,11 +22775,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 0, X86::AL,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL8m), 0|OPFL_Chain|OPFL_FlagInput|OPFL_MemRefs,
2, MVT::i8, MVT::i32, 5, 3, 4, 5, 6, 7,
- 73,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 69,
OPC_MoveParent,
OPC_SwitchType , 20, MVT::i16,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -23735,12 +22793,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL64rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i64, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
0,
- 30,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 26,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v4i32,
OPC_CheckPatternPredicate, 4,
@@ -23749,16 +22803,16 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::PMULLDrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
0,
- 117,
+ 113,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_Scope, 74,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 70,
OPC_MoveParent,
OPC_RecordChild1,
OPC_SwitchType , 20, MVT::i16,
@@ -23777,12 +22831,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL64rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i64, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
0,
- 31,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 27,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::v4i32,
@@ -23886,18 +22936,17 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v4i16, 2, 0, 1,
0,
0,
- 111|128,1, X86ISD::BT,
- OPC_Scope, 127,
+ 100|128,1, X86ISD::BT,
+ OPC_Scope, 116,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 38,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_SwitchType , 32, MVT::i16,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i16,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 1,
@@ -23909,13 +22958,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitConvertToTarget, 2,
OPC_MorphNodeTo, TARGET_OPCODE(X86::BT16mi8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
- 38,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
+ 32, MVT::i32,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 1,
@@ -23927,14 +22971,9 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitConvertToTarget, 2,
OPC_MorphNodeTo, TARGET_OPCODE(X86::BT32mi8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
- 40,
+ 34, MVT::i64,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 1,
@@ -23996,17 +23035,17 @@ SDNode *SelectCode(SDNode *N) {
0,
0,
0,
- 121|128,4, X86ISD::SMUL,
- OPC_Scope, 109|128,1,
+ 89|128,4, X86ISD::SMUL,
+ OPC_Scope, 93|128,1,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 39,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 35,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 1,
@@ -24019,12 +23058,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitConvertToTarget, 2,
OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL16rmi8), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i16, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
- 39,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 35,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 1,
@@ -24037,13 +23072,9 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitConvertToTarget, 2,
OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL32rmi8), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i32, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
- 72,
+ 68,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 1,
@@ -24067,12 +23098,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL64rmi32), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i64, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
0,
- 37,
+ 33,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 1,
@@ -24084,12 +23111,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitConvertToTarget, 2,
OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL16rmi), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i16, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
- 37,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 33,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_MoveChild, 1,
@@ -24102,42 +23125,34 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL32rmi), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i32, MVT::i32, 6, 3, 4, 5, 6, 7, 8,
0,
- 101,
+ 93,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 29,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 25,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::i16,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL16rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i16, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
- 29,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 25,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL32rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i32, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
- 31,
+ 27,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -24145,16 +23160,16 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL64rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i64, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
0,
- 103,
+ 95,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 30,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 26,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::i16,
@@ -24162,12 +23177,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL16rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i16, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
- 30,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 26,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::i32,
@@ -24175,13 +23186,9 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::IMUL32rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i32, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
- 32,
+ 28,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::i64,
@@ -24299,19 +23306,19 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::PREFETCHNTA), 0|OPFL_Chain,
0, 5, 2, 3, 4, 5, 6,
0,
- 8|128,1, ISD::INSERT_VECTOR_ELT,
+ 4|128,1, ISD::INSERT_VECTOR_ELT,
OPC_RecordChild0,
- OPC_Scope, 90,
+ OPC_Scope, 86,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 41,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 37,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild2,
OPC_MoveChild, 2,
@@ -24324,12 +23331,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitConvertToTarget, 3,
OPC_MorphNodeTo, TARGET_OPCODE(X86::PINSRQrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2i64, 7, 0, 4, 5, 6, 7, 8, 9,
- 39,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 35,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild2,
OPC_MoveChild, 2,
@@ -24361,7 +23364,7 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v4i32, 3, 0, 1, 3,
0,
0,
- 70|128,17, ISD::OR,
+ 60|128,15, ISD::OR,
OPC_Scope, 39|128,1,
OPC_MoveChild, 0,
OPC_SwitchOpcode , 87, ISD::BIT_CONVERT,
@@ -24371,13 +23374,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 0,
@@ -24390,13 +23393,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 1,
@@ -24406,13 +23409,13 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
0,
72, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::BIT_CONVERT,
@@ -24437,17 +23440,17 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
0,
0,
- 39|128,1,
+ 31|128,1,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_Scope, 95,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 91,
OPC_MoveParent,
OPC_SwitchType , 20, MVT::i8,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -24470,12 +23473,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i64, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
0,
- 30,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 26,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 1,
@@ -24483,11 +23482,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::PORrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
- 28,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 24,
OPC_MoveParent,
OPC_CheckType, MVT::v1i64,
OPC_CheckPatternPredicate, 8,
@@ -24496,16 +23491,16 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PORrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v1i64, 6, 0, 3, 4, 5, 6, 7,
0,
- 20|128,7,
+ 28|128,9,
OPC_MoveChild, 0,
- OPC_SwitchOpcode , 37|128,1, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_Scope, 96,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_SwitchOpcode , 29|128,1, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 92,
OPC_MoveParent,
OPC_RecordChild1,
OPC_SwitchType , 20, MVT::i8,
@@ -24529,12 +23524,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i64, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
0,
- 31,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 27,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::v2i64,
@@ -24543,11 +23534,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::PORrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
- 29,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 25,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::v1i64,
@@ -24557,17 +23544,17 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PORrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v1i64, 6, 2, 3, 4, 5, 6, 7,
0,
- 113|128,2, ISD::SRL,
+ 121|128,3, ISD::SRL,
OPC_RecordChild0,
- OPC_Scope, 84|128,1,
+ OPC_Scope, 82|128,1,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::TRUNCATE,
- OPC_Scope, 106,
+ OPC_Scope, 104,
OPC_RecordChild0,
OPC_RecordChild0,
- OPC_Scope, 50,
+ OPC_CheckType, MVT::i8,
+ OPC_Scope, 48,
OPC_CheckChild0Type, MVT::i32,
- OPC_CheckType, MVT::i8,
OPC_MoveParent,
OPC_MoveParent,
OPC_MoveChild, 1,
@@ -24592,9 +23579,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 2, X86::ECX,
OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32rrCL), 0|OPFL_FlagInput,
1, MVT::i32, 2, 0, 3,
- 50,
+ 48,
OPC_CheckChild0Type, MVT::i16,
- OPC_CheckType, MVT::i8,
OPC_MoveParent,
OPC_MoveParent,
OPC_MoveChild, 1,
@@ -24757,18 +23743,76 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16rrCL), 0|OPFL_FlagInput,
1, MVT::i16, 2, 3, 0,
0,
+ 68,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 7,
+ OPC_SwitchType , 12, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32rri8), 0,
+ 1, MVT::i32, 3, 0, 2, 3,
+ 12, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16rri8), 0,
+ 1, MVT::i16, 3, 0, 2, 3,
+ 12, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD64rri8), 0,
+ 1, MVT::i64, 3, 0, 2, 3,
+ 0,
+ 68,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SHL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 10,
+ OPC_SwitchType , 12, MVT::i32,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32rri8), 0,
+ 1, MVT::i32, 3, 1, 0, 3,
+ 12, MVT::i16,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16rri8), 0,
+ 1, MVT::i16, 3, 1, 0, 3,
+ 12, MVT::i64,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD64rri8), 0,
+ 1, MVT::i64, 3, 1, 0, 3,
+ 0,
0,
- 113|128,2, ISD::SHL,
+ 121|128,3, ISD::SHL,
OPC_RecordChild0,
- OPC_Scope, 84|128,1,
+ OPC_Scope, 82|128,1,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::TRUNCATE,
- OPC_Scope, 106,
+ OPC_Scope, 104,
OPC_RecordChild0,
OPC_RecordChild0,
- OPC_Scope, 50,
+ OPC_CheckType, MVT::i8,
+ OPC_Scope, 48,
OPC_CheckChild0Type, MVT::i32,
- OPC_CheckType, MVT::i8,
OPC_MoveParent,
OPC_MoveParent,
OPC_MoveChild, 1,
@@ -24793,9 +23837,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitCopyToReg, 2, X86::ECX,
OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32rrCL), 0|OPFL_FlagInput,
1, MVT::i32, 2, 0, 3,
- 50,
+ 48,
OPC_CheckChild0Type, MVT::i16,
- OPC_CheckType, MVT::i8,
OPC_MoveParent,
OPC_MoveParent,
OPC_MoveChild, 1,
@@ -24958,284 +24001,66 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16rrCL), 0|OPFL_FlagInput,
1, MVT::i16, 2, 3, 0,
0,
+ 68,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 10,
+ OPC_SwitchType , 12, MVT::i32,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32rri8), 0,
+ 1, MVT::i32, 3, 0, 2, 3,
+ 12, MVT::i16,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16rri8), 0,
+ 1, MVT::i16, 3, 0, 2, 3,
+ 12, MVT::i64,
+ OPC_EmitConvertToTarget, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD64rri8), 0,
+ 1, MVT::i64, 3, 0, 2, 3,
+ 0,
+ 68,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::SRL,
+ OPC_RecordChild0,
+ OPC_RecordChild1,
+ OPC_MoveChild, 1,
+ OPC_CheckOpcode, ISD::Constant,
+ OPC_CheckType, MVT::i8,
+ OPC_MoveParent,
+ OPC_MoveParent,
+ OPC_CheckPredicate, 7,
+ OPC_SwitchType , 12, MVT::i32,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32rri8), 0,
+ 1, MVT::i32, 3, 1, 0, 3,
+ 12, MVT::i16,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16rri8), 0,
+ 1, MVT::i16, 3, 1, 0, 3,
+ 12, MVT::i64,
+ OPC_EmitConvertToTarget, 2,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD64rri8), 0,
+ 1, MVT::i64, 3, 1, 0, 3,
+ 0,
0,
0,
- 43,
- OPC_CheckPredicate, 7,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SRL,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SHL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_EmitConvertToTarget, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32rri8), 0,
- 1, MVT::i32, 3, 0, 2, 3,
- 43,
- OPC_CheckPredicate, 8,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SHL,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SRL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_EmitConvertToTarget, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32rri8), 0,
- 1, MVT::i32, 3, 0, 2, 3,
- 43,
- OPC_CheckPredicate, 7,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SRL,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SHL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_EmitConvertToTarget, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16rri8), 0,
- 1, MVT::i16, 3, 0, 2, 3,
- 43,
- OPC_CheckPredicate, 8,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SHL,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SRL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_EmitConvertToTarget, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16rri8), 0,
- 1, MVT::i16, 3, 0, 2, 3,
- 43,
- OPC_CheckPredicate, 7,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SRL,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SHL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_EmitConvertToTarget, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD64rri8), 0,
- 1, MVT::i64, 3, 0, 2, 3,
- 43,
- OPC_CheckPredicate, 8,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SHL,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SRL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_EmitConvertToTarget, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD64rri8), 0,
- 1, MVT::i64, 3, 0, 2, 3,
- 43,
- OPC_CheckPredicate, 7,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SHL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SRL,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_EmitConvertToTarget, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD32rri8), 0,
- 1, MVT::i32, 3, 1, 0, 3,
- 43,
- OPC_CheckPredicate, 8,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SRL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SHL,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_EmitConvertToTarget, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD32rri8), 0,
- 1, MVT::i32, 3, 1, 0, 3,
- 43,
- OPC_CheckPredicate, 7,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SHL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SRL,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_EmitConvertToTarget, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD16rri8), 0,
- 1, MVT::i16, 3, 1, 0, 3,
- 43,
- OPC_CheckPredicate, 8,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SRL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SHL,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i16,
- OPC_EmitConvertToTarget, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD16rri8), 0,
- 1, MVT::i16, 3, 1, 0, 3,
- 43,
- OPC_CheckPredicate, 7,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SHL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SRL,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_EmitConvertToTarget, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHRD64rri8), 0,
- 1, MVT::i64, 3, 1, 0, 3,
- 43,
- OPC_CheckPredicate, 8,
- OPC_MoveChild, 0,
- OPC_CheckOpcode, ISD::SRL,
- OPC_RecordChild0,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::SHL,
- OPC_RecordChild0,
- OPC_RecordChild1,
- OPC_MoveChild, 1,
- OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_EmitConvertToTarget, 2,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SHLD64rri8), 0,
- 1, MVT::i64, 3, 1, 0, 3,
57,
OPC_RecordNode,
OPC_SwitchType , 36, MVT::i32,
@@ -25255,16 +24080,16 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::LEA64r), 0,
1, MVT::i64, 4, 1, 2, 3, 4,
0,
- 22|128,1,
- OPC_CheckPredicate, 71,
+ 28|128,1,
OPC_RecordChild0,
OPC_RecordChild1,
- OPC_Scope, 104,
+ OPC_Scope, 110,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::Constant,
- OPC_Scope, 47,
+ OPC_Scope, 49,
OPC_CheckPredicate, 11,
OPC_MoveParent,
+ OPC_CheckPredicate, 71,
OPC_SwitchType , 12, MVT::i16,
OPC_EmitConvertToTarget, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16ri8), 0,
@@ -25278,15 +24103,17 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64ri8), 0,
2, MVT::i64, MVT::i32, 2, 0, 2,
0,
- 17,
+ 19,
OPC_CheckPredicate, 12,
OPC_MoveParent,
+ OPC_CheckPredicate, 71,
OPC_CheckType, MVT::i64,
OPC_EmitConvertToTarget, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64ri32), 0,
2, MVT::i64, MVT::i32, 2, 0, 2,
- 31,
+ 33,
OPC_MoveParent,
+ OPC_CheckPredicate, 71,
OPC_SwitchType , 12, MVT::i16,
OPC_EmitConvertToTarget, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16ri), 0,
@@ -25297,18 +24124,18 @@ SDNode *SelectCode(SDNode *N) {
2, MVT::i32, MVT::i32, 2, 0, 2,
0,
0,
- 12,
- OPC_CheckType, MVT::i16,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16rr), 0,
- 2, MVT::i16, MVT::i32, 2, 0, 1,
- 12,
- OPC_CheckType, MVT::i32,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32rr), 0,
- 2, MVT::i32, MVT::i32, 2, 0, 1,
- 12,
- OPC_CheckType, MVT::i64,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64rr), 0,
- 2, MVT::i64, MVT::i32, 2, 0, 1,
+ 40,
+ OPC_CheckPredicate, 71,
+ OPC_SwitchType , 10, MVT::i16,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16rr), 0,
+ 2, MVT::i16, MVT::i32, 2, 0, 1,
+ 10, MVT::i32,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32rr), 0,
+ 2, MVT::i32, MVT::i32, 2, 0, 1,
+ 10, MVT::i64,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64rr), 0,
+ 2, MVT::i64, MVT::i32, 2, 0, 1,
+ 0,
0,
29,
OPC_MoveChild, 0,
@@ -25404,7 +24231,7 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v1i64, 2, 0, 1,
0,
0,
- 51|128,6, ISD::XOR,
+ 35|128,6, ISD::XOR,
OPC_Scope, 39|128,1,
OPC_MoveChild, 0,
OPC_SwitchOpcode , 87, ISD::BIT_CONVERT,
@@ -25414,13 +24241,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 0,
@@ -25433,13 +24260,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 1,
@@ -25449,13 +24276,13 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
0,
72, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::BIT_CONVERT,
@@ -25480,17 +24307,17 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
0,
0,
- 39|128,1,
+ 31|128,1,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_Scope, 95,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 91,
OPC_MoveParent,
OPC_SwitchType , 20, MVT::i8,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -25513,12 +24340,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i64, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
0,
- 30,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 26,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 1,
@@ -25526,11 +24349,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::PXORrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
- 28,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 24,
OPC_MoveParent,
OPC_CheckType, MVT::v1i64,
OPC_CheckPatternPredicate, 8,
@@ -25539,16 +24358,16 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PXORrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v1i64, 6, 0, 3, 4, 5, 6, 7,
0,
- 41|128,1,
+ 33|128,1,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_Scope, 96,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 92,
OPC_MoveParent,
OPC_RecordChild1,
OPC_SwitchType , 20, MVT::i8,
@@ -25572,12 +24391,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i64, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
0,
- 31,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 27,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::v2i64,
@@ -25586,11 +24401,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::PXORrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2i64, 6, 2, 3, 4, 5, 6, 7,
- 29,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 25,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::v1i64,
@@ -25718,13 +24529,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 45,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_RecordChild2,
OPC_MoveChild, 2,
@@ -25753,13 +24564,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 45,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_RecordChild2,
OPC_MoveChild, 2,
@@ -25782,22 +24593,21 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::CMPPDrri), 0,
1, MVT::v2i64, 3, 0, 1, 3,
0,
- 97|128,11, ISD::ADD,
- OPC_Scope, 72|128,1,
+ 77|128,11, ISD::ADD,
+ OPC_Scope, 66|128,1,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_Scope, 81,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v2i64,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_SwitchType , 75, MVT::v2i64,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_MoveParent,
OPC_SwitchType , 21, MVT::v16i8,
@@ -25819,12 +24629,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::PADDDrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
0,
- 102,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v1i64,
+ 96, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
OPC_SwitchType , 21, MVT::v8i8,
@@ -25853,20 +24658,19 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v1i64, 6, 0, 3, 4, 5, 6, 7,
0,
0,
- 73|128,1,
+ 67|128,1,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_Scope, 82,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v2i64,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_SwitchType , 76, MVT::v2i64,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_MoveParent,
OPC_RecordChild1,
@@ -25889,12 +24693,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::PADDDrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v4i32, 6, 2, 3, 4, 5, 6, 7,
0,
- 103,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v1i64,
+ 97, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
OPC_RecordChild1,
@@ -25924,17 +24723,17 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v1i64, 6, 2, 3, 4, 5, 6, 7,
0,
0,
- 10|128,1,
+ 6|128,1,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_Scope, 95,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 91,
OPC_MoveParent,
OPC_SwitchType , 20, MVT::i8,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -25957,12 +24756,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i64, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
0,
- 30,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 26,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 1,
@@ -25971,16 +24766,16 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::PADDQrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2i64, 6, 0, 3, 4, 5, 6, 7,
0,
- 11|128,1,
+ 7|128,1,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_Scope, 96,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 92,
OPC_MoveParent,
OPC_RecordChild1,
OPC_SwitchType , 20, MVT::i8,
@@ -26004,12 +24799,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i64, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
0,
- 31,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 27,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::v2i64,
@@ -26307,22 +25098,21 @@ SDNode *SelectCode(SDNode *N) {
0,
0,
0,
- 103|128,5, ISD::SUB,
- OPC_Scope, 83|128,2,
+ 93|128,5, ISD::SUB,
+ OPC_Scope, 73|128,2,
OPC_RecordChild0,
OPC_MoveChild, 1,
- OPC_SwitchOpcode , 67|128,1, ISD::BIT_CONVERT,
+ OPC_SwitchOpcode , 61|128,1, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_Scope, 81,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v2i64,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_SwitchType , 75, MVT::v2i64,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_MoveParent,
OPC_SwitchType , 21, MVT::v16i8,
@@ -26344,12 +25134,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::PSUBDrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v4i32, 6, 0, 3, 4, 5, 6, 7,
0,
- 102,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::v1i64,
+ 96, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
OPC_SwitchType , 21, MVT::v8i8,
@@ -26378,14 +25163,14 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v1i64, 6, 0, 3, 4, 5, 6, 7,
0,
0,
- 5|128,1, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_Scope, 95,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 1|128,1, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 91,
OPC_MoveParent,
OPC_SwitchType , 20, MVT::i8,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -26408,12 +25193,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB64rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i64, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
0,
- 30,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 26,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
OPC_CheckPatternPredicate, 1,
@@ -26568,13 +25349,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 45,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 48,
- OPC_CheckPredicate, 60,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 48,
+ OPC_CheckPredicate, 60,
OPC_MoveParent,
OPC_RecordChild2,
OPC_MoveChild, 2,
@@ -26597,12 +25378,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::PINSRWrri), 0,
1, MVT::v8i16, 3, 0, 1, 3,
0,
- 126, ISD::MEMBARRIER,
+ 122, ISD::MEMBARRIER,
OPC_RecordNode,
OPC_MoveChild, 1,
- OPC_Scope, 34,
+ OPC_CheckType, MVT::i8,
+ OPC_Scope, 32,
OPC_CheckInteger, 0,
- OPC_CheckType, MVT::i8,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 0,
@@ -26619,9 +25400,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::SFENCE), 0|OPFL_Chain,
0, 0,
- 34,
+ 32,
OPC_CheckInteger, 1,
- OPC_CheckType, MVT::i8,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckInteger, 0,
@@ -26638,9 +25418,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::LFENCE), 0|OPFL_Chain,
0, 0,
- 50,
+ 48,
OPC_CheckOpcode, ISD::Constant,
- OPC_CheckType, MVT::i8,
OPC_MoveParent,
OPC_MoveChild, 2,
OPC_CheckOpcode, ISD::Constant,
@@ -26673,13 +25452,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_CheckType, MVT::v2i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -26699,13 +25478,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 45,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 48,
- OPC_CheckPredicate, 59,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 48,
+ OPC_CheckPredicate, 59,
OPC_MoveParent,
OPC_RecordChild2,
OPC_MoveChild, 2,
@@ -26735,12 +25514,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -26754,12 +25533,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -26773,13 +25552,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v16i8,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -26789,13 +25568,13 @@ SDNode *SelectCode(SDNode *N) {
37,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::v16i8,
@@ -26821,12 +25600,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -26840,12 +25619,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -26859,13 +25638,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v8i16,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -26875,13 +25654,13 @@ SDNode *SelectCode(SDNode *N) {
37,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::v8i16,
@@ -26907,12 +25686,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -26926,12 +25705,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckOpcode, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -26945,13 +25724,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v4i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -26961,13 +25740,13 @@ SDNode *SelectCode(SDNode *N) {
37,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::v4i32,
@@ -26993,12 +25772,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_SwitchOpcode , 37, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -27008,13 +25787,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPGTBrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v8i8, 6, 0, 3, 4, 5, 6, 7,
32, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v16i8,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -27039,12 +25818,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_SwitchOpcode , 37, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -27054,13 +25833,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPGTWrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v4i16, 6, 0, 3, 4, 5, 6, 7,
32, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v8i16,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -27085,12 +25864,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_SwitchOpcode , 37, ISD::BIT_CONVERT,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_CheckType, MVT::v1i64,
OPC_MoveParent,
OPC_MoveParent,
@@ -27100,13 +25879,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MMX_PCMPGTDrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2i32, 6, 0, 3, 4, 5, 6, 7,
32, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v4i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -27438,19 +26217,19 @@ SDNode *SelectCode(SDNode *N) {
0, 2, 1, 2,
0,
0,
- 22|128,8, ISD::FADD,
- OPC_Scope, 27|128,1,
+ 72|128,7, ISD::FADD,
+ OPC_Scope, 19|128,1,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 57,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 53,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_SwitchType , 21, MVT::f32,
OPC_CheckPatternPredicate, 6,
@@ -27465,14 +26244,10 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_Fp64m), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
0,
- 87,
+ 79,
OPC_CheckPredicate, 48,
- OPC_Scope, 53,
+ OPC_Scope, 49,
OPC_CheckPredicate, 49,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_SwitchType , 21, MVT::f64,
OPC_CheckPatternPredicate, 7,
@@ -27486,12 +26261,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_Fp80m32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
0,
- 28,
+ 24,
OPC_CheckPredicate, 50,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::f80,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -27500,17 +26271,17 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
0,
0,
- 29|128,1,
+ 21|128,1,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 58,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 54,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_SwitchType , 21, MVT::f32,
@@ -27526,14 +26297,10 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_Fp64m), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f64, 6, 2, 3, 4, 5, 6, 7,
0,
- 89,
+ 81,
OPC_CheckPredicate, 48,
- OPC_Scope, 54,
+ OPC_Scope, 50,
OPC_CheckPredicate, 49,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_SwitchType , 21, MVT::f64,
@@ -27548,12 +26315,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_Fp80m32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f80, 6, 2, 3, 4, 5, 6, 7,
0,
- 29,
+ 25,
OPC_CheckPredicate, 50,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::f80,
@@ -27563,17 +26326,17 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::f80, 6, 2, 3, 4, 5, 6, 7,
0,
0,
- 3|128,1,
+ 119,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_Scope, 28,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 24,
OPC_MoveParent,
OPC_CheckType, MVT::f32,
OPC_CheckPatternPredicate, 0,
@@ -27581,12 +26344,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ADDSSrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
- 30,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 26,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v4f32,
OPC_CheckPatternPredicate, 0,
@@ -27594,11 +26353,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ADDPSrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
- 28,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 24,
OPC_MoveParent,
OPC_CheckType, MVT::f64,
OPC_CheckPatternPredicate, 1,
@@ -27606,12 +26361,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ADDSDrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
- 30,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 26,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2f64,
OPC_CheckPatternPredicate, 1,
@@ -27620,16 +26371,16 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::ADDPDrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
0,
- 6|128,1,
+ 122,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_Scope, 29,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 25,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::f32,
@@ -27638,12 +26389,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ADDSSrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f32, 6, 2, 3, 4, 5, 6, 7,
- 31,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 27,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::v4f32,
@@ -27652,11 +26399,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ADDPSrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v4f32, 6, 2, 3, 4, 5, 6, 7,
- 29,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 25,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::f64,
@@ -27665,12 +26408,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ADDSDrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f64, 6, 2, 3, 4, 5, 6, 7,
- 31,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 27,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::v2f64,
@@ -27680,7 +26419,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::ADDPDrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2f64, 6, 2, 3, 4, 5, 6, 7,
0,
- 48|128,1,
+ 32|128,1,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, X86ISD::FILD,
@@ -27688,136 +26427,104 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
OPC_MoveChild, 2,
- OPC_Scope, 27,
- OPC_CheckValueType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::f32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI16m32), 0|OPFL_Chain,
- 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
- 27,
- OPC_CheckValueType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::f32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI32m32), 0|OPFL_Chain,
- 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
- 27,
- OPC_CheckValueType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::f64,
- OPC_CheckPatternPredicate, 7,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI16m64), 0|OPFL_Chain,
- 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
- 27,
- OPC_CheckValueType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::f64,
- OPC_CheckPatternPredicate, 7,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI32m64), 0|OPFL_Chain,
- 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
- 25,
+ OPC_Scope, 73,
OPC_CheckValueType, MVT::i16,
OPC_MoveParent,
OPC_MoveParent,
- OPC_CheckType, MVT::f80,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI16m80), 0|OPFL_Chain,
- 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
- 25,
+ OPC_SwitchType , 21, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI16m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI16m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 19, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI16m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 73,
OPC_CheckValueType, MVT::i32,
OPC_MoveParent,
OPC_MoveParent,
- OPC_CheckType, MVT::f80,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI32m80), 0|OPFL_Chain,
- 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ OPC_SwitchType , 21, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI32m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI32m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 19, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI32m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 0,
0,
- 53|128,1,
+ 33|128,1,
OPC_MoveChild, 0,
OPC_CheckOpcode, X86ISD::FILD,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
OPC_MoveChild, 2,
- OPC_Scope, 28,
- OPC_CheckValueType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckType, MVT::f32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI16m32), 0|OPFL_Chain,
- 1, MVT::f32, 6, 2, 3, 4, 5, 6, 7,
- 28,
- OPC_CheckValueType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckType, MVT::f32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI32m32), 0|OPFL_Chain,
- 1, MVT::f32, 6, 2, 3, 4, 5, 6, 7,
- 28,
- OPC_CheckValueType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckType, MVT::f64,
- OPC_CheckPatternPredicate, 7,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI16m64), 0|OPFL_Chain,
- 1, MVT::f64, 6, 2, 3, 4, 5, 6, 7,
- 28,
- OPC_CheckValueType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckType, MVT::f64,
- OPC_CheckPatternPredicate, 7,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI32m64), 0|OPFL_Chain,
- 1, MVT::f64, 6, 2, 3, 4, 5, 6, 7,
- 26,
+ OPC_Scope, 74,
OPC_CheckValueType, MVT::i16,
OPC_MoveParent,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_CheckType, MVT::f80,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI16m80), 0|OPFL_Chain,
- 1, MVT::f80, 6, 2, 3, 4, 5, 6, 7,
- 26,
+ OPC_SwitchType , 21, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI16m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 2, 3, 4, 5, 6, 7,
+ 21, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI16m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 2, 3, 4, 5, 6, 7,
+ 19, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI16m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 74,
OPC_CheckValueType, MVT::i32,
OPC_MoveParent,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_CheckType, MVT::f80,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI32m80), 0|OPFL_Chain,
- 1, MVT::f80, 6, 2, 3, 4, 5, 6, 7,
+ OPC_SwitchType , 21, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI32m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 2, 3, 4, 5, 6, 7,
+ 21, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI32m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 2, 3, 4, 5, 6, 7,
+ 19, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD_FpI32m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 2, 3, 4, 5, 6, 7,
+ 0,
0,
97,
OPC_RecordChild0,
@@ -27855,19 +26562,19 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v2f64, 2, 0, 1,
0,
0,
- 100|128,6, ISD::FSUB,
+ 114|128,5, ISD::FSUB,
OPC_RecordChild0,
- OPC_Scope, 126|128,5,
+ OPC_Scope, 12|128,5,
OPC_MoveChild, 1,
- OPC_SwitchOpcode , 37|128,3, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 57,
+ OPC_SwitchOpcode , 1|128,3, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 53,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_SwitchType , 21, MVT::f32,
OPC_CheckPatternPredicate, 6,
@@ -27882,14 +26589,10 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB_Fp64m), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
0,
- 87,
+ 79,
OPC_CheckPredicate, 48,
- OPC_Scope, 53,
+ OPC_Scope, 49,
OPC_CheckPredicate, 49,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_SwitchType , 21, MVT::f64,
OPC_CheckPatternPredicate, 7,
@@ -27903,12 +26606,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB_Fp80m32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
0,
- 28,
+ 24,
OPC_CheckPredicate, 50,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::f80,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -27916,13 +26615,9 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB_Fp80m64), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
0,
- 57,
+ 53,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_SwitchType , 21, MVT::f32,
OPC_CheckPatternPredicate, 6,
@@ -27937,14 +26632,10 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBR_Fp64m), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
0,
- 87,
+ 79,
OPC_CheckPredicate, 48,
- OPC_Scope, 53,
+ OPC_Scope, 49,
OPC_CheckPredicate, 49,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_SwitchType , 21, MVT::f64,
OPC_CheckPatternPredicate, 7,
@@ -27958,12 +26649,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBR_Fp80m32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
0,
- 28,
+ 24,
OPC_CheckPredicate, 50,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::f80,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -27971,13 +26658,9 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBR_Fp80m64), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
0,
- 124,
- OPC_CheckPredicate, 9,
- OPC_Scope, 28,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 108,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 24,
OPC_MoveParent,
OPC_CheckType, MVT::f32,
OPC_CheckPatternPredicate, 0,
@@ -27985,12 +26668,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBSSrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
- 30,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 26,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v4f32,
OPC_CheckPatternPredicate, 0,
@@ -27998,11 +26677,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBPSrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
- 28,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 24,
OPC_MoveParent,
OPC_CheckType, MVT::f64,
OPC_CheckPatternPredicate, 1,
@@ -28010,12 +26685,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBSDrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
- 30,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 26,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2f64,
OPC_CheckPatternPredicate, 1,
@@ -28025,127 +26696,85 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
0,
0,
- 79|128,2, X86ISD::FILD,
+ 1|128,2, X86ISD::FILD,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
OPC_MoveChild, 2,
- OPC_Scope, 27,
- OPC_CheckValueType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::f32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB_FpI16m32), 0|OPFL_Chain,
- 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
- 27,
- OPC_CheckValueType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::f32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB_FpI32m32), 0|OPFL_Chain,
- 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
- 27,
- OPC_CheckValueType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::f64,
- OPC_CheckPatternPredicate, 7,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB_FpI16m64), 0|OPFL_Chain,
- 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
- 27,
- OPC_CheckValueType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::f64,
- OPC_CheckPatternPredicate, 7,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB_FpI32m64), 0|OPFL_Chain,
- 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
- 25,
- OPC_CheckValueType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::f80,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB_FpI16m80), 0|OPFL_Chain,
- 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
- 25,
- OPC_CheckValueType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::f80,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB_FpI32m80), 0|OPFL_Chain,
- 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
- 27,
- OPC_CheckValueType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::f32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBR_FpI16m32), 0|OPFL_Chain,
- 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
- 27,
- OPC_CheckValueType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::f32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBR_FpI32m32), 0|OPFL_Chain,
- 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
- 27,
- OPC_CheckValueType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::f64,
- OPC_CheckPatternPredicate, 7,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBR_FpI16m64), 0|OPFL_Chain,
- 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
- 27,
- OPC_CheckValueType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::f64,
- OPC_CheckPatternPredicate, 7,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBR_FpI32m64), 0|OPFL_Chain,
- 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
- 25,
+ OPC_Scope, 124,
OPC_CheckValueType, MVT::i16,
OPC_MoveParent,
OPC_MoveParent,
- OPC_CheckType, MVT::f80,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBR_FpI16m80), 0|OPFL_Chain,
- 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
- 25,
+ OPC_SwitchType , 38, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_Scope, 13,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB_FpI16m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 13,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBR_FpI16m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 38, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_Scope, 13,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB_FpI16m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 13,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBR_FpI16m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 36, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_Scope, 13,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB_FpI16m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 13,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBR_FpI16m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 0,
+ 124,
OPC_CheckValueType, MVT::i32,
OPC_MoveParent,
OPC_MoveParent,
- OPC_CheckType, MVT::f80,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBR_FpI32m80), 0|OPFL_Chain,
- 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ OPC_SwitchType , 38, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_Scope, 13,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB_FpI32m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 13,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBR_FpI32m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 38, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_Scope, 13,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB_FpI32m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 13,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBR_FpI32m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 36, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_Scope, 13,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB_FpI32m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 13,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::SUBR_FpI32m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 0,
0,
0,
96,
@@ -28183,19 +26812,19 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v2f64, 2, 0, 1,
0,
0,
- 22|128,8, ISD::FMUL,
- OPC_Scope, 27|128,1,
+ 72|128,7, ISD::FMUL,
+ OPC_Scope, 19|128,1,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 57,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 53,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_SwitchType , 21, MVT::f32,
OPC_CheckPatternPredicate, 6,
@@ -28210,14 +26839,10 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_Fp64m), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
0,
- 87,
+ 79,
OPC_CheckPredicate, 48,
- OPC_Scope, 53,
+ OPC_Scope, 49,
OPC_CheckPredicate, 49,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_SwitchType , 21, MVT::f64,
OPC_CheckPatternPredicate, 7,
@@ -28231,12 +26856,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_Fp80m32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
0,
- 28,
+ 24,
OPC_CheckPredicate, 50,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::f80,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -28245,17 +26866,17 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
0,
0,
- 29|128,1,
+ 21|128,1,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 58,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 54,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_SwitchType , 21, MVT::f32,
@@ -28271,14 +26892,10 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_Fp64m), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f64, 6, 2, 3, 4, 5, 6, 7,
0,
- 89,
+ 81,
OPC_CheckPredicate, 48,
- OPC_Scope, 54,
+ OPC_Scope, 50,
OPC_CheckPredicate, 49,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_SwitchType , 21, MVT::f64,
@@ -28293,12 +26910,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_Fp80m32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f80, 6, 2, 3, 4, 5, 6, 7,
0,
- 29,
+ 25,
OPC_CheckPredicate, 50,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::f80,
@@ -28308,17 +26921,17 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::f80, 6, 2, 3, 4, 5, 6, 7,
0,
0,
- 3|128,1,
+ 119,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_Scope, 28,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 24,
OPC_MoveParent,
OPC_CheckType, MVT::f32,
OPC_CheckPatternPredicate, 0,
@@ -28326,12 +26939,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MULSSrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
- 30,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 26,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v4f32,
OPC_CheckPatternPredicate, 0,
@@ -28339,11 +26948,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MULPSrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
- 28,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 24,
OPC_MoveParent,
OPC_CheckType, MVT::f64,
OPC_CheckPatternPredicate, 1,
@@ -28351,12 +26956,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MULSDrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
- 30,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 26,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2f64,
OPC_CheckPatternPredicate, 1,
@@ -28365,16 +26966,16 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MULPDrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
0,
- 6|128,1,
+ 122,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_Scope, 29,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 25,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::f32,
@@ -28383,12 +26984,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MULSSrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f32, 6, 2, 3, 4, 5, 6, 7,
- 31,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 27,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::v4f32,
@@ -28397,11 +26994,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MULPSrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v4f32, 6, 2, 3, 4, 5, 6, 7,
- 29,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 25,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::f64,
@@ -28410,12 +27003,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MULSDrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f64, 6, 2, 3, 4, 5, 6, 7,
- 31,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 27,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::v2f64,
@@ -28425,7 +27014,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MULPDrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v2f64, 6, 2, 3, 4, 5, 6, 7,
0,
- 48|128,1,
+ 32|128,1,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, X86ISD::FILD,
@@ -28433,136 +27022,104 @@ SDNode *SelectCode(SDNode *N) {
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
OPC_MoveChild, 2,
- OPC_Scope, 27,
- OPC_CheckValueType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::f32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI16m32), 0|OPFL_Chain,
- 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
- 27,
- OPC_CheckValueType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::f32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI32m32), 0|OPFL_Chain,
- 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
- 27,
+ OPC_Scope, 73,
OPC_CheckValueType, MVT::i16,
OPC_MoveParent,
OPC_MoveParent,
- OPC_CheckType, MVT::f64,
- OPC_CheckPatternPredicate, 7,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI16m64), 0|OPFL_Chain,
- 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
- 27,
- OPC_CheckValueType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::f64,
- OPC_CheckPatternPredicate, 7,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI32m64), 0|OPFL_Chain,
- 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
- 25,
- OPC_CheckValueType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::f80,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI16m80), 0|OPFL_Chain,
- 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
- 25,
+ OPC_SwitchType , 21, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI16m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI16m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 19, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI16m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 73,
OPC_CheckValueType, MVT::i32,
OPC_MoveParent,
OPC_MoveParent,
- OPC_CheckType, MVT::f80,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI32m80), 0|OPFL_Chain,
- 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ OPC_SwitchType , 21, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI32m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 21, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI32m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 19, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI32m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 0,
0,
- 53|128,1,
+ 33|128,1,
OPC_MoveChild, 0,
OPC_CheckOpcode, X86ISD::FILD,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
OPC_MoveChild, 2,
- OPC_Scope, 28,
- OPC_CheckValueType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckType, MVT::f32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI16m32), 0|OPFL_Chain,
- 1, MVT::f32, 6, 2, 3, 4, 5, 6, 7,
- 28,
- OPC_CheckValueType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckType, MVT::f32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI32m32), 0|OPFL_Chain,
- 1, MVT::f32, 6, 2, 3, 4, 5, 6, 7,
- 28,
- OPC_CheckValueType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckType, MVT::f64,
- OPC_CheckPatternPredicate, 7,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI16m64), 0|OPFL_Chain,
- 1, MVT::f64, 6, 2, 3, 4, 5, 6, 7,
- 28,
- OPC_CheckValueType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_RecordChild1,
- OPC_CheckType, MVT::f64,
- OPC_CheckPatternPredicate, 7,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI32m64), 0|OPFL_Chain,
- 1, MVT::f64, 6, 2, 3, 4, 5, 6, 7,
- 26,
+ OPC_Scope, 74,
OPC_CheckValueType, MVT::i16,
OPC_MoveParent,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_CheckType, MVT::f80,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI16m80), 0|OPFL_Chain,
- 1, MVT::f80, 6, 2, 3, 4, 5, 6, 7,
- 26,
+ OPC_SwitchType , 21, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI16m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 2, 3, 4, 5, 6, 7,
+ 21, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI16m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 2, 3, 4, 5, 6, 7,
+ 19, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI16m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 2, 3, 4, 5, 6, 7,
+ 0,
+ 74,
OPC_CheckValueType, MVT::i32,
OPC_MoveParent,
OPC_MoveParent,
OPC_RecordChild1,
- OPC_CheckType, MVT::f80,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI32m80), 0|OPFL_Chain,
- 1, MVT::f80, 6, 2, 3, 4, 5, 6, 7,
+ OPC_SwitchType , 21, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI32m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 2, 3, 4, 5, 6, 7,
+ 21, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI32m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 2, 3, 4, 5, 6, 7,
+ 19, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MUL_FpI32m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 2, 3, 4, 5, 6, 7,
+ 0,
0,
97,
OPC_RecordChild0,
@@ -28600,19 +27157,19 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v2f64, 2, 0, 1,
0,
0,
- 100|128,6, ISD::FDIV,
+ 114|128,5, ISD::FDIV,
OPC_RecordChild0,
- OPC_Scope, 126|128,5,
+ OPC_Scope, 12|128,5,
OPC_MoveChild, 1,
- OPC_SwitchOpcode , 37|128,3, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 57,
+ OPC_SwitchOpcode , 1|128,3, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 53,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_SwitchType , 21, MVT::f32,
OPC_CheckPatternPredicate, 6,
@@ -28627,14 +27184,10 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::DIV_Fp64m), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
0,
- 87,
+ 79,
OPC_CheckPredicate, 48,
- OPC_Scope, 53,
+ OPC_Scope, 49,
OPC_CheckPredicate, 49,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_SwitchType , 21, MVT::f64,
OPC_CheckPatternPredicate, 7,
@@ -28648,12 +27201,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::DIV_Fp80m32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
0,
- 28,
+ 24,
OPC_CheckPredicate, 50,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::f80,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -28661,13 +27210,9 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::DIV_Fp80m64), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
0,
- 57,
+ 53,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_SwitchType , 21, MVT::f32,
OPC_CheckPatternPredicate, 6,
@@ -28682,14 +27227,10 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVR_Fp64m), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
0,
- 87,
+ 79,
OPC_CheckPredicate, 48,
- OPC_Scope, 53,
+ OPC_Scope, 49,
OPC_CheckPredicate, 49,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_SwitchType , 21, MVT::f64,
OPC_CheckPatternPredicate, 7,
@@ -28703,12 +27244,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVR_Fp80m32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
0,
- 28,
+ 24,
OPC_CheckPredicate, 50,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::f80,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -28716,13 +27253,9 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVR_Fp80m64), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
0,
- 124,
- OPC_CheckPredicate, 9,
- OPC_Scope, 28,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 108,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 24,
OPC_MoveParent,
OPC_CheckType, MVT::f32,
OPC_CheckPatternPredicate, 0,
@@ -28730,12 +27263,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVSSrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
- 30,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 26,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v4f32,
OPC_CheckPatternPredicate, 0,
@@ -28743,11 +27272,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVPSrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
- 28,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 24,
OPC_MoveParent,
OPC_CheckType, MVT::f64,
OPC_CheckPatternPredicate, 1,
@@ -28755,12 +27280,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVSDrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
- 30,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 26,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2f64,
OPC_CheckPatternPredicate, 1,
@@ -28770,127 +27291,85 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v2f64, 6, 0, 3, 4, 5, 6, 7,
0,
0,
- 79|128,2, X86ISD::FILD,
+ 1|128,2, X86ISD::FILD,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
OPC_MoveChild, 2,
- OPC_Scope, 27,
- OPC_CheckValueType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::f32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::DIV_FpI16m32), 0|OPFL_Chain,
- 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
- 27,
- OPC_CheckValueType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::f32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::DIV_FpI32m32), 0|OPFL_Chain,
- 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
- 27,
- OPC_CheckValueType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::f64,
- OPC_CheckPatternPredicate, 7,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::DIV_FpI16m64), 0|OPFL_Chain,
- 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
- 27,
- OPC_CheckValueType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::f64,
- OPC_CheckPatternPredicate, 7,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::DIV_FpI32m64), 0|OPFL_Chain,
- 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
- 25,
- OPC_CheckValueType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::f80,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::DIV_FpI16m80), 0|OPFL_Chain,
- 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
- 25,
- OPC_CheckValueType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::f80,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::DIV_FpI32m80), 0|OPFL_Chain,
- 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
- 27,
- OPC_CheckValueType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::f32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVR_FpI16m32), 0|OPFL_Chain,
- 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
- 27,
- OPC_CheckValueType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::f32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVR_FpI32m32), 0|OPFL_Chain,
- 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
- 27,
- OPC_CheckValueType, MVT::i16,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::f64,
- OPC_CheckPatternPredicate, 7,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVR_FpI16m64), 0|OPFL_Chain,
- 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
- 27,
- OPC_CheckValueType, MVT::i32,
- OPC_MoveParent,
- OPC_MoveParent,
- OPC_CheckType, MVT::f64,
- OPC_CheckPatternPredicate, 7,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVR_FpI32m64), 0|OPFL_Chain,
- 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
- 25,
+ OPC_Scope, 124,
OPC_CheckValueType, MVT::i16,
OPC_MoveParent,
OPC_MoveParent,
- OPC_CheckType, MVT::f80,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVR_FpI16m80), 0|OPFL_Chain,
- 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
- 25,
+ OPC_SwitchType , 38, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_Scope, 13,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIV_FpI16m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 13,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVR_FpI16m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 38, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_Scope, 13,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIV_FpI16m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 13,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVR_FpI16m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 36, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_Scope, 13,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIV_FpI16m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 13,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVR_FpI16m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 0,
+ 124,
OPC_CheckValueType, MVT::i32,
OPC_MoveParent,
OPC_MoveParent,
- OPC_CheckType, MVT::f80,
- OPC_CheckComplexPat, /*CP*/0, /*#*/2,
- OPC_EmitMergeInputChains, 1, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVR_FpI32m80), 0|OPFL_Chain,
- 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ OPC_SwitchType , 38, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_Scope, 13,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIV_FpI32m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 13,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVR_FpI32m32), 0|OPFL_Chain,
+ 1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 38, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_Scope, 13,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIV_FpI32m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 13,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVR_FpI32m64), 0|OPFL_Chain,
+ 1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 36, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/2,
+ OPC_EmitMergeInputChains, 1, 1,
+ OPC_Scope, 13,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIV_FpI32m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 13,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::DIVR_FpI32m80), 0|OPFL_Chain,
+ 1, MVT::f80, 6, 0, 3, 4, 5, 6, 7,
+ 0,
+ 0,
0,
0,
96,
@@ -28928,32 +27407,26 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v2f64, 2, 0, 1,
0,
0,
- 100, ISD::BRIND,
+ 94, ISD::BRIND,
OPC_RecordNode,
- OPC_Scope, 66,
+ OPC_Scope, 60,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 27,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_SwitchType , 21, MVT::i32,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::JMP32m), 0|OPFL_Chain|OPFL_MemRefs,
0, 5, 3, 4, 5, 6, 7,
- 29,
+ 23, MVT::i64,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
@@ -28974,33 +27447,27 @@ SDNode *SelectCode(SDNode *N) {
0, 1, 1,
0,
0,
- 10|128,2, X86ISD::CALL,
+ 4|128,2, X86ISD::CALL,
OPC_RecordNode,
OPC_CaptureFlagInput,
- OPC_Scope, 92,
+ OPC_Scope, 86,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 27,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_SwitchType , 21, MVT::i32,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 2, 0, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::CALL32m), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput|OPFL_MemRefs|OPFL_Variadic1,
0, 5, 3, 4, 5, 6, 7,
- 55,
+ 49, MVT::i64,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_Scope, 20,
OPC_CheckPatternPredicate, 16,
@@ -29089,39 +27556,33 @@ SDNode *SelectCode(SDNode *N) {
0,
0,
0,
- 6|128,1, X86ISD::BSF,
- OPC_Scope, 94,
+ 0|128,1, X86ISD::BSF,
+ OPC_Scope, 88,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 27,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 24,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::i16,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::BSF16rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i16, MVT::i32, 5, 2, 3, 4, 5, 6,
- 27,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
+ 24,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::BSF32rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i32, MVT::i32, 5, 2, 3, 4, 5, 6,
- 29,
+ 26,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -29142,39 +27603,33 @@ SDNode *SelectCode(SDNode *N) {
2, MVT::i64, MVT::i32, 1, 0,
0,
0,
- 6|128,1, X86ISD::BSR,
- OPC_Scope, 94,
+ 0|128,1, X86ISD::BSR,
+ OPC_Scope, 88,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 27,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 24,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::i16,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::BSR16rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i16, MVT::i32, 5, 2, 3, 4, 5, 6,
- 27,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
+ 24,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::BSR32rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i32, MVT::i32, 5, 2, 3, 4, 5, 6,
- 29,
+ 26,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
@@ -29201,12 +27656,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_SwitchType , 19, MVT::i8,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -29232,12 +27687,12 @@ SDNode *SelectCode(SDNode *N) {
100,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_RecordChild1,
OPC_SwitchType , 19, MVT::i8,
@@ -29330,12 +27785,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 99,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_SwitchType , 19, MVT::i8,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -29425,12 +27880,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_SwitchType , 19, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -29446,12 +27901,12 @@ SDNode *SelectCode(SDNode *N) {
58,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_RecordChild1,
OPC_SwitchType , 19, MVT::i64,
@@ -29512,12 +27967,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 57,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_SwitchType , 19, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -29569,56 +28024,44 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::i64, 2, 0, 1,
0,
0,
- 68|128,3, X86ISD::ADD,
- OPC_Scope, 5|128,1,
+ 42|128,3, X86ISD::ADD,
+ OPC_Scope, 121,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 31,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::i8,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i8, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
- 29,
+ 25,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::i16,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i16, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
- 29,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 25,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i32, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
- 31,
+ 27,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -29626,17 +28069,17 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD64rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i64, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
0,
- 8|128,1,
+ 124,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 32,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 28,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::i8,
@@ -29644,12 +28087,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i8, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
- 30,
+ 26,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::i16,
@@ -29657,12 +28096,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD16rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i16, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
- 30,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 26,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::i32,
@@ -29670,13 +28105,9 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD32rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i32, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
- 32,
+ 28,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::i64,
@@ -29748,56 +28179,44 @@ SDNode *SelectCode(SDNode *N) {
2, MVT::i64, MVT::i32, 2, 0, 1,
0,
0,
- 57|128,2, X86ISD::SUB,
+ 44|128,2, X86ISD::SUB,
OPC_RecordChild0,
- OPC_Scope, 4|128,1,
+ OPC_Scope, 120,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 31,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::i8,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB8rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i8, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
- 29,
+ 25,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::i16,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB16rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i16, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
- 29,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 25,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::SUB32rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i32, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
- 31,
+ 27,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -29867,56 +28286,44 @@ SDNode *SelectCode(SDNode *N) {
2, MVT::i64, MVT::i32, 2, 0, 1,
0,
0,
- 68|128,3, X86ISD::OR,
- OPC_Scope, 5|128,1,
+ 42|128,3, X86ISD::OR,
+ OPC_Scope, 121,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 31,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::i8,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::OR8rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i8, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
- 29,
+ 25,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::i16,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i16, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
- 29,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 25,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i32, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
- 31,
+ 27,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -29924,17 +28331,17 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::OR64rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i64, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
0,
- 8|128,1,
+ 124,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 32,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 28,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::i8,
@@ -29942,12 +28349,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::OR8rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i8, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
- 30,
+ 26,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::i16,
@@ -29955,12 +28358,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::OR16rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i16, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
- 30,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 26,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::i32,
@@ -29968,13 +28367,9 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::OR32rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i32, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
- 32,
+ 28,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::i64,
@@ -30046,56 +28441,44 @@ SDNode *SelectCode(SDNode *N) {
2, MVT::i64, MVT::i32, 2, 0, 1,
0,
0,
- 68|128,3, X86ISD::XOR,
- OPC_Scope, 5|128,1,
+ 42|128,3, X86ISD::XOR,
+ OPC_Scope, 121,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 31,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::i8,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR8rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i8, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
- 29,
+ 25,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::i16,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i16, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
- 29,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 25,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i32, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
- 31,
+ 27,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -30103,17 +28486,17 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR64rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i64, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
0,
- 8|128,1,
+ 124,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 32,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 28,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::i8,
@@ -30121,12 +28504,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR8rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i8, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
- 30,
+ 26,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::i16,
@@ -30134,12 +28513,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR16rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i16, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
- 30,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 26,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::i32,
@@ -30147,13 +28522,9 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::XOR32rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i32, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
- 32,
+ 28,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::i64,
@@ -30225,56 +28596,44 @@ SDNode *SelectCode(SDNode *N) {
2, MVT::i64, MVT::i32, 2, 0, 1,
0,
0,
- 68|128,3, X86ISD::AND,
- OPC_Scope, 5|128,1,
+ 42|128,3, X86ISD::AND,
+ OPC_Scope, 121,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 31,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 27,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::i8,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i8, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
- 29,
+ 25,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::i16,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i16, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
- 29,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 25,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i32, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
- 31,
+ 27,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -30282,17 +28641,17 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::AND64rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i64, MVT::i32, 6, 0, 3, 4, 5, 6, 7,
0,
- 8|128,1,
+ 124,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 32,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_Scope, 28,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::i8,
@@ -30300,12 +28659,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::AND8rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i8, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
- 30,
+ 26,
OPC_CheckPredicate, 6,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::i16,
@@ -30313,12 +28668,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::AND16rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i16, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
- 30,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 26,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::i32,
@@ -30326,13 +28677,9 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::AND32rm), 0|OPFL_Chain|OPFL_MemRefs,
2, MVT::i32, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
- 32,
+ 28,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::i64,
@@ -30408,12 +28755,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 113,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
OPC_SwitchType , 47, MVT::f64,
OPC_MoveParent,
OPC_SwitchType , 20, MVT::i64,
@@ -30483,18 +28830,17 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v2i32, 1, 0,
0,
0,
- 87|128,1, ISD::SINT_TO_FP,
- OPC_Scope, 120,
+ 82|128,1, ISD::SINT_TO_FP,
+ OPC_Scope, 115,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 56,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_SwitchType , 51, MVT::i64,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_SwitchType , 20, MVT::f64,
OPC_CheckPatternPredicate, 1,
@@ -30509,12 +28855,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::CVTSI2SS64rm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f32, 5, 2, 3, 4, 5, 6,
0,
- 54,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
+ 49, MVT::i32,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_SwitchType , 20, MVT::f32,
OPC_CheckPatternPredicate, 0,
@@ -30568,18 +28910,17 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v2f64, 1, 0,
0,
0,
- 67|128,5, ISD::BIT_CONVERT,
- OPC_Scope, 3|128,1,
+ 61|128,5, ISD::BIT_CONVERT,
+ OPC_Scope, 126,
OPC_MoveChild, 0,
- OPC_SwitchOpcode , 68, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_Scope, 32,
+ OPC_SwitchOpcode , 63, ISD::LOAD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_SwitchType , 27, MVT::i64,
+ OPC_CheckPredicate, 8,
OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i64,
OPC_MoveParent,
OPC_CheckType, MVT::f64,
OPC_CheckPatternPredicate, 1,
@@ -30587,12 +28928,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64toSDrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f64, 5, 2, 3, 4, 5, 6,
- 30,
- OPC_CheckPredicate, 5,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_CheckType, MVT::i32,
+ 25, MVT::i32,
+ OPC_CheckPredicate, 3,
OPC_MoveParent,
OPC_CheckType, MVT::f32,
OPC_CheckPatternPredicate, 1,
@@ -30915,12 +29252,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 34,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckPatternPredicate, 0,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -30938,12 +29275,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 34,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -30964,12 +29301,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 34,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckPatternPredicate, 0,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -30987,12 +29324,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 34,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckPatternPredicate, 1,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -31011,13 +29348,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_SwitchType , 21, MVT::f32,
OPC_CheckPatternPredicate, 0,
@@ -31035,13 +29372,13 @@ SDNode *SelectCode(SDNode *N) {
64,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_RecordChild1,
OPC_SwitchType , 21, MVT::f32,
@@ -31075,13 +29412,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_SwitchType , 21, MVT::f32,
OPC_CheckPatternPredicate, 0,
@@ -31099,13 +29436,13 @@ SDNode *SelectCode(SDNode *N) {
64,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_RecordChild1,
OPC_SwitchType , 21, MVT::f32,
@@ -31139,13 +29476,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_SwitchType , 21, MVT::f32,
OPC_CheckPatternPredicate, 0,
@@ -31163,13 +29500,13 @@ SDNode *SelectCode(SDNode *N) {
64,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_RecordChild1,
OPC_SwitchType , 21, MVT::f32,
@@ -31198,18 +29535,18 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::f64, 2, 0, 1,
0,
0,
- 63|128,1, X86ISD::FMAX,
+ 50|128,1, X86ISD::FMAX,
OPC_RecordChild0,
- OPC_Scope, 2|128,1,
+ OPC_Scope, 118,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_Scope, 28,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 24,
OPC_MoveParent,
OPC_CheckType, MVT::f32,
OPC_CheckPatternPredicate, 0,
@@ -31217,12 +29554,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MAXSSrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
- 30,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 26,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v4f32,
OPC_CheckPatternPredicate, 0,
@@ -31230,11 +29563,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MAXPSrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
- 28,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 24,
OPC_MoveParent,
OPC_CheckType, MVT::f64,
OPC_CheckPatternPredicate, 1,
@@ -31242,12 +29571,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MAXSDrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
- 30,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 26,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2f64,
OPC_CheckPatternPredicate, 1,
@@ -31276,18 +29601,18 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v2f64, 2, 0, 1,
0,
0,
- 63|128,1, X86ISD::FMIN,
+ 50|128,1, X86ISD::FMIN,
OPC_RecordChild0,
- OPC_Scope, 2|128,1,
+ OPC_Scope, 118,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_Scope, 28,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_CheckFoldableChainNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 24,
OPC_MoveParent,
OPC_CheckType, MVT::f32,
OPC_CheckPatternPredicate, 0,
@@ -31295,12 +29620,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MINSSrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f32, 6, 0, 3, 4, 5, 6, 7,
- 30,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 26,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v4f32,
OPC_CheckPatternPredicate, 0,
@@ -31308,11 +29629,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MINPSrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v4f32, 6, 0, 3, 4, 5, 6, 7,
- 28,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 24,
OPC_MoveParent,
OPC_CheckType, MVT::f64,
OPC_CheckPatternPredicate, 1,
@@ -31320,12 +29637,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MINSDrm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f64, 6, 0, 3, 4, 5, 6, 7,
- 30,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_CheckFoldableChainNode,
- OPC_RecordChild1,
+ 26,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2f64,
OPC_CheckPatternPredicate, 1,
@@ -31354,16 +29667,16 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v2f64, 2, 0, 1,
0,
0,
- 87|128,1, ISD::FSQRT,
- OPC_Scope, 122,
+ 78|128,1, ISD::FSQRT,
+ OPC_Scope, 113,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_Scope, 26,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 23,
OPC_MoveParent,
OPC_CheckType, MVT::f32,
OPC_CheckPatternPredicate, 19,
@@ -31371,11 +29684,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::SQRTSSm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f32, 5, 2, 3, 4, 5, 6,
- 28,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
+ 25,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v4f32,
OPC_CheckPatternPredicate, 0,
@@ -31383,10 +29693,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::SQRTPSm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::v4f32, 5, 2, 3, 4, 5, 6,
- 26,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
+ 23,
OPC_MoveParent,
OPC_CheckType, MVT::f64,
OPC_CheckPatternPredicate, 1,
@@ -31394,11 +29701,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::SQRTSDm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f64, 5, 2, 3, 4, 5, 6,
- 28,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
+ 25,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2f64,
OPC_CheckPatternPredicate, 1,
@@ -31442,16 +29746,16 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v2f64, 1, 0,
0,
0,
- 97, X86ISD::FRSQRT,
- OPC_Scope, 66,
+ 94, X86ISD::FRSQRT,
+ OPC_Scope, 63,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_Scope, 26,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 23,
OPC_MoveParent,
OPC_CheckType, MVT::f32,
OPC_CheckPatternPredicate, 19,
@@ -31459,11 +29763,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::RSQRTSSm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f32, 5, 2, 3, 4, 5, 6,
- 28,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
+ 25,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v4f32,
OPC_CheckPatternPredicate, 0,
@@ -31484,16 +29785,16 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::v4f32, 1, 0,
0,
0,
- 97, X86ISD::FRCP,
- OPC_Scope, 66,
+ 94, X86ISD::FRCP,
+ OPC_Scope, 63,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_Scope, 26,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_Scope, 23,
OPC_MoveParent,
OPC_CheckType, MVT::f32,
OPC_CheckPatternPredicate, 19,
@@ -31501,11 +29802,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::RCPSSm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::f32, 5, 2, 3, 4, 5, 6,
- 28,
- OPC_CheckPredicate, 24,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
+ 25,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v4f32,
OPC_CheckPatternPredicate, 0,
@@ -31530,12 +29828,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 38,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
OPC_CheckType, MVT::f64,
OPC_MoveParent,
OPC_CheckType, MVT::f32,
@@ -31575,12 +29873,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 38,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 10,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 9,
OPC_CheckType, MVT::f32,
OPC_MoveParent,
OPC_CheckType, MVT::f64,
@@ -31621,13 +29919,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -31637,13 +29935,13 @@ SDNode *SelectCode(SDNode *N) {
37,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_RecordChild1,
OPC_CheckType, MVT::v2i64,
@@ -31663,12 +29961,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 34,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
OPC_MoveParent,
OPC_CheckPatternPredicate, 4,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -31686,13 +29984,13 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 36,
OPC_MoveChild, 1,
OPC_CheckOpcode, ISD::LOAD,
- OPC_CheckPredicate, 4,
- OPC_CheckPredicate, 9,
- OPC_CheckPredicate, 24,
OPC_RecordMemRef,
OPC_RecordNode,
OPC_CheckFoldableChainNode,
OPC_RecordChild1,
+ OPC_CheckPredicate, 2,
+ OPC_CheckPredicate, 8,
+ OPC_CheckPredicate, 23,
OPC_MoveParent,
OPC_CheckType, MVT::v2i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/2,
@@ -31705,504 +30003,349 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::PCMPGTQrr), 0,
1, MVT::v2i64, 2, 0, 1,
0,
- 114, ISD::ATOMIC_SWAP,
- OPC_Scope, 27,
+ 98, ISD::ATOMIC_SWAP,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_SwitchType , 21, MVT::i32,
OPC_CheckPredicate, 72,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::XCHG32rm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
- 27,
+ 21, MVT::i16,
OPC_CheckPredicate, 73,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i16,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::XCHG16rm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i16, 6, 2, 3, 4, 5, 6, 7,
- 27,
+ 21, MVT::i8,
OPC_CheckPredicate, 74,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i8,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::XCHG8rm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i8, 6, 2, 3, 4, 5, 6, 7,
- 27,
+ 21, MVT::i64,
OPC_CheckPredicate, 75,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::XCHG64rm), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 6, 2, 3, 4, 5, 6, 7,
0,
- 114, ISD::ATOMIC_LOAD_ADD,
- OPC_Scope, 27,
+ 98, ISD::ATOMIC_LOAD_ADD,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_SwitchType , 21, MVT::i32,
OPC_CheckPredicate, 76,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::LXADD32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 2, 3, 4, 5, 6, 7,
- 27,
+ 21, MVT::i16,
OPC_CheckPredicate, 77,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i16,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::LXADD16), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i16, 6, 2, 3, 4, 5, 6, 7,
- 27,
+ 21, MVT::i8,
OPC_CheckPredicate, 78,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i8,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::LXADD8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i8, 6, 2, 3, 4, 5, 6, 7,
- 27,
+ 21, MVT::i64,
OPC_CheckPredicate, 79,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::LXADD64), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 6, 2, 3, 4, 5, 6, 7,
0,
- 114, ISD::ATOMIC_LOAD_AND,
- OPC_Scope, 27,
+ 98, ISD::ATOMIC_LOAD_AND,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_SwitchType , 21, MVT::i32,
OPC_CheckPredicate, 80,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMAND32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 3, 4, 5, 6, 7, 2,
- 27,
+ 21, MVT::i16,
OPC_CheckPredicate, 81,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i16,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMAND16), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i16, 6, 3, 4, 5, 6, 7, 2,
- 27,
+ 21, MVT::i8,
OPC_CheckPredicate, 82,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i8,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMAND8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i8, 6, 3, 4, 5, 6, 7, 2,
- 27,
+ 21, MVT::i64,
OPC_CheckPredicate, 83,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMAND64), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 6, 3, 4, 5, 6, 7, 2,
0,
- 114, ISD::ATOMIC_LOAD_OR,
- OPC_Scope, 27,
+ 98, ISD::ATOMIC_LOAD_OR,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_SwitchType , 21, MVT::i32,
OPC_CheckPredicate, 84,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMOR32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 3, 4, 5, 6, 7, 2,
- 27,
+ 21, MVT::i16,
OPC_CheckPredicate, 85,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i16,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMOR16), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i16, 6, 3, 4, 5, 6, 7, 2,
- 27,
+ 21, MVT::i8,
OPC_CheckPredicate, 86,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i8,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMOR8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i8, 6, 3, 4, 5, 6, 7, 2,
- 27,
+ 21, MVT::i64,
OPC_CheckPredicate, 87,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMOR64), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 6, 3, 4, 5, 6, 7, 2,
0,
- 114, ISD::ATOMIC_LOAD_XOR,
- OPC_Scope, 27,
+ 98, ISD::ATOMIC_LOAD_XOR,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_SwitchType , 21, MVT::i32,
OPC_CheckPredicate, 88,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMXOR32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 3, 4, 5, 6, 7, 2,
- 27,
+ 21, MVT::i16,
OPC_CheckPredicate, 89,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i16,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMXOR16), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i16, 6, 3, 4, 5, 6, 7, 2,
- 27,
+ 21, MVT::i8,
OPC_CheckPredicate, 90,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i8,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMXOR8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i8, 6, 3, 4, 5, 6, 7, 2,
- 27,
+ 21, MVT::i64,
OPC_CheckPredicate, 91,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMXOR64), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 6, 3, 4, 5, 6, 7, 2,
0,
- 114, ISD::ATOMIC_LOAD_NAND,
- OPC_Scope, 27,
+ 98, ISD::ATOMIC_LOAD_NAND,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_SwitchType , 21, MVT::i32,
OPC_CheckPredicate, 92,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMNAND32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 3, 4, 5, 6, 7, 2,
- 27,
+ 21, MVT::i16,
OPC_CheckPredicate, 93,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i16,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMNAND16), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i16, 6, 3, 4, 5, 6, 7, 2,
- 27,
+ 21, MVT::i8,
OPC_CheckPredicate, 94,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i8,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMNAND8), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i8, 6, 3, 4, 5, 6, 7, 2,
- 27,
+ 21, MVT::i64,
OPC_CheckPredicate, 95,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMNAND64), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 6, 3, 4, 5, 6, 7, 2,
0,
- 86, ISD::ATOMIC_LOAD_MIN,
- OPC_Scope, 27,
+ 75, ISD::ATOMIC_LOAD_MIN,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_SwitchType , 21, MVT::i32,
OPC_CheckPredicate, 96,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMMIN32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 3, 4, 5, 6, 7, 2,
- 27,
+ 21, MVT::i16,
OPC_CheckPredicate, 97,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i16,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMMIN16), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i16, 6, 3, 4, 5, 6, 7, 2,
- 27,
+ 21, MVT::i64,
OPC_CheckPredicate, 98,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMMIN64), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 6, 3, 4, 5, 6, 7, 2,
0,
- 86, ISD::ATOMIC_LOAD_MAX,
- OPC_Scope, 27,
+ 75, ISD::ATOMIC_LOAD_MAX,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_SwitchType , 21, MVT::i32,
OPC_CheckPredicate, 99,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMMAX32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 3, 4, 5, 6, 7, 2,
- 27,
+ 21, MVT::i16,
OPC_CheckPredicate, 100,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i16,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMMAX16), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i16, 6, 3, 4, 5, 6, 7, 2,
- 27,
+ 21, MVT::i64,
OPC_CheckPredicate, 101,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMMAX64), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 6, 3, 4, 5, 6, 7, 2,
0,
- 86, ISD::ATOMIC_LOAD_UMIN,
- OPC_Scope, 27,
+ 75, ISD::ATOMIC_LOAD_UMIN,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_SwitchType , 21, MVT::i32,
OPC_CheckPredicate, 102,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMUMIN32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 3, 4, 5, 6, 7, 2,
- 27,
+ 21, MVT::i16,
OPC_CheckPredicate, 103,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i16,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMUMIN16), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i16, 6, 3, 4, 5, 6, 7, 2,
- 27,
+ 21, MVT::i64,
OPC_CheckPredicate, 104,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMUMIN64), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 6, 3, 4, 5, 6, 7, 2,
0,
- 86, ISD::ATOMIC_LOAD_UMAX,
- OPC_Scope, 27,
+ 75, ISD::ATOMIC_LOAD_UMAX,
+ OPC_RecordMemRef,
+ OPC_RecordNode,
+ OPC_RecordChild1,
+ OPC_RecordChild2,
+ OPC_SwitchType , 21, MVT::i32,
OPC_CheckPredicate, 105,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i32,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMUMAX32), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i32, 6, 3, 4, 5, 6, 7, 2,
- 27,
+ 21, MVT::i16,
OPC_CheckPredicate, 106,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i16,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMUMAX16), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i16, 6, 3, 4, 5, 6, 7, 2,
- 27,
+ 21, MVT::i64,
OPC_CheckPredicate, 107,
- OPC_RecordMemRef,
- OPC_RecordNode,
- OPC_RecordChild1,
- OPC_RecordChild2,
- OPC_CheckType, MVT::i64,
OPC_CheckComplexPat, /*CP*/0, /*#*/1,
OPC_EmitMergeInputChains, 1, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ATOMUMAX64), 0|OPFL_Chain|OPFL_MemRefs,
1, MVT::i64, 6, 3, 4, 5, 6, 7, 2,
0,
- 106|128,1, X86ISD::FILD,
+ 88|128,1, X86ISD::FILD,
OPC_RecordNode,
OPC_RecordChild1,
OPC_MoveChild, 2,
- OPC_Scope, 25,
- OPC_CheckValueType, MVT::i16,
- OPC_MoveParent,
- OPC_CheckType, MVT::f32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ILD_Fp16m32), 0|OPFL_Chain,
- 1, MVT::f32, 5, 2, 3, 4, 5, 6,
- 25,
- OPC_CheckValueType, MVT::i32,
- OPC_MoveParent,
- OPC_CheckType, MVT::f32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ILD_Fp32m32), 0|OPFL_Chain,
- 1, MVT::f32, 5, 2, 3, 4, 5, 6,
- 25,
- OPC_CheckValueType, MVT::i64,
- OPC_MoveParent,
- OPC_CheckType, MVT::f32,
- OPC_CheckPatternPredicate, 6,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ILD_Fp64m32), 0|OPFL_Chain,
- 1, MVT::f32, 5, 2, 3, 4, 5, 6,
- 25,
+ OPC_Scope, 69,
OPC_CheckValueType, MVT::i16,
OPC_MoveParent,
- OPC_CheckType, MVT::f64,
- OPC_CheckPatternPredicate, 7,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ILD_Fp16m64), 0|OPFL_Chain,
- 1, MVT::f64, 5, 2, 3, 4, 5, 6,
- 25,
- OPC_CheckValueType, MVT::i32,
- OPC_MoveParent,
- OPC_CheckType, MVT::f64,
- OPC_CheckPatternPredicate, 7,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ILD_Fp32m64), 0|OPFL_Chain,
- 1, MVT::f64, 5, 2, 3, 4, 5, 6,
- 25,
- OPC_CheckValueType, MVT::i64,
- OPC_MoveParent,
- OPC_CheckType, MVT::f64,
- OPC_CheckPatternPredicate, 7,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ILD_Fp64m64), 0|OPFL_Chain,
- 1, MVT::f64, 5, 2, 3, 4, 5, 6,
- 23,
- OPC_CheckValueType, MVT::i16,
- OPC_MoveParent,
- OPC_CheckType, MVT::f80,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ILD_Fp16m80), 0|OPFL_Chain,
- 1, MVT::f80, 5, 2, 3, 4, 5, 6,
- 23,
+ OPC_SwitchType , 20, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ILD_Fp16m32), 0|OPFL_Chain,
+ 1, MVT::f32, 5, 2, 3, 4, 5, 6,
+ 20, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ILD_Fp16m64), 0|OPFL_Chain,
+ 1, MVT::f64, 5, 2, 3, 4, 5, 6,
+ 18, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ILD_Fp16m80), 0|OPFL_Chain,
+ 1, MVT::f80, 5, 2, 3, 4, 5, 6,
+ 0,
+ 69,
OPC_CheckValueType, MVT::i32,
OPC_MoveParent,
- OPC_CheckType, MVT::f80,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ILD_Fp32m80), 0|OPFL_Chain,
- 1, MVT::f80, 5, 2, 3, 4, 5, 6,
- 23,
+ OPC_SwitchType , 20, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ILD_Fp32m32), 0|OPFL_Chain,
+ 1, MVT::f32, 5, 2, 3, 4, 5, 6,
+ 20, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ILD_Fp32m64), 0|OPFL_Chain,
+ 1, MVT::f64, 5, 2, 3, 4, 5, 6,
+ 18, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ILD_Fp32m80), 0|OPFL_Chain,
+ 1, MVT::f80, 5, 2, 3, 4, 5, 6,
+ 0,
+ 69,
OPC_CheckValueType, MVT::i64,
OPC_MoveParent,
- OPC_CheckType, MVT::f80,
- OPC_CheckComplexPat, /*CP*/0, /*#*/1,
- OPC_EmitMergeInputChains, 1, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::ILD_Fp64m80), 0|OPFL_Chain,
- 1, MVT::f80, 5, 2, 3, 4, 5, 6,
+ OPC_SwitchType , 20, MVT::f32,
+ OPC_CheckPatternPredicate, 6,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ILD_Fp64m32), 0|OPFL_Chain,
+ 1, MVT::f32, 5, 2, 3, 4, 5, 6,
+ 20, MVT::f64,
+ OPC_CheckPatternPredicate, 7,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ILD_Fp64m64), 0|OPFL_Chain,
+ 1, MVT::f64, 5, 2, 3, 4, 5, 6,
+ 18, MVT::f80,
+ OPC_CheckComplexPat, /*CP*/0, /*#*/1,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::ILD_Fp64m80), 0|OPFL_Chain,
+ 1, MVT::f80, 5, 2, 3, 4, 5, 6,
+ 0,
0,
14|128,1, X86ISD::FP_TO_INT16_IN_MEM,
OPC_RecordNode,
@@ -32504,7 +30647,7 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::LEA64r), 0,
1, MVT::i64, 4, 1, 2, 3, 4,
0,
- 57|128,2, ISD::SHL,
+ 53|128,2, ISD::SHL,
OPC_Scope, 57,
OPC_RecordNode,
OPC_SwitchType , 36, MVT::i32,
@@ -32524,14 +30667,14 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::LEA64r), 0,
1, MVT::i64, 4, 1, 2, 3, 4,
0,
- 123|128,1,
+ 119|128,1,
OPC_RecordChild0,
- OPC_Scope, 124,
+ OPC_Scope, 120,
OPC_MoveChild, 1,
- OPC_Scope, 47,
+ OPC_CheckType, MVT::i8,
+ OPC_Scope, 45,
OPC_CheckAndImm, 31,
OPC_RecordChild0,
- OPC_CheckType, MVT::i8,
OPC_MoveParent,
OPC_SwitchType , 11, MVT::i8,
OPC_EmitCopyToReg, 1, X86::CL,
@@ -32546,18 +30689,16 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL32rCL), 0|OPFL_FlagInput,
1, MVT::i32, 1, 0,
0,
- 19,
+ 17,
OPC_CheckAndImm, 63,
OPC_RecordChild0,
- OPC_CheckType, MVT::i8,
OPC_MoveParent,
OPC_CheckType, MVT::i64,
OPC_EmitCopyToReg, 1, X86::CL,
OPC_MorphNodeTo, TARGET_OPCODE(X86::SHL64rCL), 0|OPFL_FlagInput,
1, MVT::i64, 1, 0,
- 51,
+ 49,
OPC_CheckInteger, 1,
- OPC_CheckType, MVT::i8,
OPC_MoveParent,
OPC_SwitchType , 9, MVT::i8,
OPC_MorphNodeTo, TARGET_OPCODE(X86::ADD8rr), 0,
@@ -32648,12 +30789,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 78,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::SRL,
- OPC_CheckPredicate, 16,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckInteger, 8,
OPC_CheckType, MVT::i8,
OPC_MoveParent,
+ OPC_CheckPredicate, 15,
OPC_SwitchType , 29, MVT::i16,
OPC_MoveParent,
OPC_CheckType, MVT::i8,
@@ -32737,12 +30878,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 15|128,1,
OPC_MoveChild, 0,
OPC_CheckOpcode, ISD::SRL,
- OPC_CheckPredicate, 16,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckInteger, 8,
OPC_CheckType, MVT::i8,
OPC_MoveParent,
+ OPC_CheckPredicate, 15,
OPC_CheckType, MVT::i16,
OPC_MoveParent,
OPC_SwitchType , 72, MVT::i32,
@@ -32825,12 +30966,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_Scope, 67|128,1,
OPC_MoveChild, 0,
OPC_SwitchOpcode , 11|128,1, ISD::SRL,
- OPC_CheckPredicate, 16,
OPC_RecordChild0,
OPC_MoveChild, 1,
OPC_CheckInteger, 8,
OPC_CheckType, MVT::i8,
OPC_MoveParent,
+ OPC_CheckPredicate, 15,
OPC_CheckType, MVT::i16,
OPC_MoveParent,
OPC_SwitchType , 72, MVT::i32,
@@ -32922,14 +31063,14 @@ SDNode *SelectCode(SDNode *N) {
0,
0,
0,
- 96|128,2, ISD::SRL,
+ 90|128,2, ISD::SRL,
OPC_RecordChild0,
- OPC_Scope, 96|128,1,
+ OPC_Scope, 90|128,1,
OPC_MoveChild, 1,
- OPC_Scope, 47,
+ OPC_CheckType, MVT::i8,
+ OPC_Scope, 45,
OPC_CheckAndImm, 31,
OPC_RecordChild0,
- OPC_CheckType, MVT::i8,
OPC_MoveParent,
OPC_SwitchType , 11, MVT::i8,
OPC_EmitCopyToReg, 1, X86::CL,
@@ -32944,18 +31085,16 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR32rCL), 0|OPFL_FlagInput,
1, MVT::i32, 1, 0,
0,
- 19,
+ 17,
OPC_CheckAndImm, 63,
OPC_RecordChild0,
- OPC_CheckType, MVT::i8,
OPC_MoveParent,
OPC_CheckType, MVT::i64,
OPC_EmitCopyToReg, 1, X86::CL,
OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR64rCL), 0|OPFL_FlagInput,
1, MVT::i64, 1, 0,
- 47,
+ 45,
OPC_CheckInteger, 1,
- OPC_CheckType, MVT::i8,
OPC_MoveParent,
OPC_SwitchType , 8, MVT::i8,
OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR8r1), 0,
@@ -32970,9 +31109,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::SHR64r1), 0,
1, MVT::i64, 1, 0,
0,
- 103,
+ 101,
OPC_CheckInteger, 8,
- OPC_CheckType, MVT::i8,
OPC_MoveParent,
OPC_CheckType, MVT::i16,
OPC_Scope, 46,
@@ -33048,14 +31186,14 @@ SDNode *SelectCode(SDNode *N) {
0,
0,
0,
- 119|128,1, ISD::SRA,
+ 115|128,1, ISD::SRA,
OPC_RecordChild0,
- OPC_Scope, 120,
+ OPC_Scope, 116,
OPC_MoveChild, 1,
- OPC_Scope, 47,
+ OPC_CheckType, MVT::i8,
+ OPC_Scope, 45,
OPC_CheckAndImm, 31,
OPC_RecordChild0,
- OPC_CheckType, MVT::i8,
OPC_MoveParent,
OPC_SwitchType , 11, MVT::i8,
OPC_EmitCopyToReg, 1, X86::CL,
@@ -33070,18 +31208,16 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR32rCL), 0|OPFL_FlagInput,
1, MVT::i32, 1, 0,
0,
- 19,
+ 17,
OPC_CheckAndImm, 63,
OPC_RecordChild0,
- OPC_CheckType, MVT::i8,
OPC_MoveParent,
OPC_CheckType, MVT::i64,
OPC_EmitCopyToReg, 1, X86::CL,
OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR64rCL), 0|OPFL_FlagInput,
1, MVT::i64, 1, 0,
- 47,
+ 45,
OPC_CheckInteger, 1,
- OPC_CheckType, MVT::i8,
OPC_MoveParent,
OPC_SwitchType , 8, MVT::i8,
OPC_MorphNodeTo, TARGET_OPCODE(X86::SAR8r1), 0,
@@ -33971,7 +32107,7 @@ SDNode *SelectCode(SDNode *N) {
0,
0,
0,
- 1|128,1, ISD::Constant,
+ 124, ISD::Constant,
OPC_Scope, 40,
OPC_CheckInteger, 0,
OPC_SwitchType , 7, MVT::i64,
@@ -33987,40 +32123,36 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV32r0), 0,
1, MVT::i32, 0,
0,
- 85,
+ 80,
OPC_RecordNode,
- OPC_Scope, 14,
- OPC_CheckPredicate, 69,
- OPC_CheckType, MVT::i64,
- OPC_EmitConvertToTarget, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64ri64i32), 0,
- 1, MVT::i64, 1, 1,
- 14,
- OPC_CheckPredicate, 12,
- OPC_CheckType, MVT::i64,
- OPC_EmitConvertToTarget, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64ri32), 0,
- 1, MVT::i64, 1, 1,
- 12,
- OPC_CheckType, MVT::i8,
+ OPC_SwitchType , 39, MVT::i64,
+ OPC_Scope, 12,
+ OPC_CheckPredicate, 69,
+ OPC_EmitConvertToTarget, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64ri64i32), 0,
+ 1, MVT::i64, 1, 1,
+ 12,
+ OPC_CheckPredicate, 12,
+ OPC_EmitConvertToTarget, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64ri32), 0,
+ 1, MVT::i64, 1, 1,
+ 10,
+ OPC_EmitConvertToTarget, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64ri), 0,
+ 1, MVT::i64, 1, 1,
+ 0,
+ 10, MVT::i8,
OPC_EmitConvertToTarget, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV8ri), 0,
1, MVT::i8, 1, 1,
- 12,
- OPC_CheckType, MVT::i16,
+ 10, MVT::i16,
OPC_EmitConvertToTarget, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV16ri), 0,
1, MVT::i16, 1, 1,
- 12,
- OPC_CheckType, MVT::i32,
+ 10, MVT::i32,
OPC_EmitConvertToTarget, 0,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV32ri), 0,
1, MVT::i32, 1, 1,
- 12,
- OPC_CheckType, MVT::i64,
- OPC_EmitConvertToTarget, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOV64ri), 0,
- 1, MVT::i64, 1, 1,
0,
0,
42, X86ISD::VSHL,
@@ -34093,99 +32225,91 @@ SDNode *SelectCode(SDNode *N) {
OPC_EmitConvertToTarget, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::PEXTRBrr), 0,
1, MVT::i32, 2, 0, 2,
- 110|128,1, ISD::ConstantFP,
- OPC_Scope, 13,
- OPC_CheckPredicate, 109,
- OPC_CheckType, MVT::f32,
- OPC_CheckPatternPredicate, 6,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp032), 0,
- 1, MVT::f32, 0,
- 13,
- OPC_CheckPredicate, 110,
- OPC_CheckType, MVT::f32,
- OPC_CheckPatternPredicate, 6,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp132), 0,
- 1, MVT::f32, 0,
- 13,
- OPC_CheckPredicate, 109,
- OPC_CheckType, MVT::f64,
- OPC_CheckPatternPredicate, 7,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp064), 0,
- 1, MVT::f64, 0,
- 13,
- OPC_CheckPredicate, 110,
- OPC_CheckType, MVT::f64,
- OPC_CheckPatternPredicate, 7,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp164), 0,
- 1, MVT::f64, 0,
- 11,
- OPC_CheckPredicate, 109,
- OPC_CheckType, MVT::f80,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp080), 0,
- 1, MVT::f80, 0,
- 11,
- OPC_CheckPredicate, 110,
- OPC_CheckType, MVT::f80,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp180), 0,
- 1, MVT::f80, 0,
- 13,
- OPC_CheckPredicate, 111,
- OPC_CheckType, MVT::f32,
- OPC_CheckPatternPredicate, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::FsFLD0SS), 0,
- 1, MVT::f32, 0,
- 13,
- OPC_CheckPredicate, 109,
- OPC_CheckType, MVT::f64,
- OPC_CheckPatternPredicate, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::FsFLD0SD), 0,
- 1, MVT::f64, 0,
- 21,
- OPC_CheckPredicate, 112,
- OPC_CheckType, MVT::f32,
- OPC_CheckPatternPredicate, 6,
- OPC_EmitNode, TARGET_OPCODE(X86::LD_Fp032), 0,
- 1, MVT::f32, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::CHS_Fp32), 0,
- 1, MVT::f32, 1, 0,
- 21,
- OPC_CheckPredicate, 113,
- OPC_CheckType, MVT::f32,
- OPC_CheckPatternPredicate, 6,
- OPC_EmitNode, TARGET_OPCODE(X86::LD_Fp132), 0,
- 1, MVT::f32, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::CHS_Fp32), 0,
- 1, MVT::f32, 1, 0,
- 21,
- OPC_CheckPredicate, 112,
- OPC_CheckType, MVT::f64,
- OPC_CheckPatternPredicate, 7,
- OPC_EmitNode, TARGET_OPCODE(X86::LD_Fp064), 0,
- 1, MVT::f64, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::CHS_Fp64), 0,
- 1, MVT::f64, 1, 0,
- 21,
- OPC_CheckPredicate, 113,
- OPC_CheckType, MVT::f64,
- OPC_CheckPatternPredicate, 7,
- OPC_EmitNode, TARGET_OPCODE(X86::LD_Fp164), 0,
- 1, MVT::f64, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::CHS_Fp64), 0,
- 1, MVT::f64, 1, 0,
- 19,
- OPC_CheckPredicate, 112,
- OPC_CheckType, MVT::f80,
- OPC_EmitNode, TARGET_OPCODE(X86::LD_Fp080), 0,
- 1, MVT::f80, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::CHS_Fp80), 0,
- 1, MVT::f80, 1, 0,
- 19,
- OPC_CheckPredicate, 113,
- OPC_CheckType, MVT::f80,
- OPC_EmitNode, TARGET_OPCODE(X86::LD_Fp180), 0,
- 1, MVT::f80, 0,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::CHS_Fp80), 0,
- 1, MVT::f80, 1, 0,
+ 94|128,1, ISD::ConstantFP,
+ OPC_SwitchType , 78, MVT::f32,
+ OPC_Scope, 11,
+ OPC_CheckPredicate, 109,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp032), 0,
+ 1, MVT::f32, 0,
+ 11,
+ OPC_CheckPredicate, 110,
+ OPC_CheckPatternPredicate, 6,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp132), 0,
+ 1, MVT::f32, 0,
+ 11,
+ OPC_CheckPredicate, 111,
+ OPC_CheckPatternPredicate, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FsFLD0SS), 0,
+ 1, MVT::f32, 0,
+ 19,
+ OPC_CheckPredicate, 112,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitNode, TARGET_OPCODE(X86::LD_Fp032), 0,
+ 1, MVT::f32, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CHS_Fp32), 0,
+ 1, MVT::f32, 1, 0,
+ 19,
+ OPC_CheckPredicate, 113,
+ OPC_CheckPatternPredicate, 6,
+ OPC_EmitNode, TARGET_OPCODE(X86::LD_Fp132), 0,
+ 1, MVT::f32, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CHS_Fp32), 0,
+ 1, MVT::f32, 1, 0,
+ 0,
+ 78, MVT::f64,
+ OPC_Scope, 11,
+ OPC_CheckPredicate, 109,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp064), 0,
+ 1, MVT::f64, 0,
+ 11,
+ OPC_CheckPredicate, 110,
+ OPC_CheckPatternPredicate, 7,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp164), 0,
+ 1, MVT::f64, 0,
+ 11,
+ OPC_CheckPredicate, 109,
+ OPC_CheckPatternPredicate, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::FsFLD0SD), 0,
+ 1, MVT::f64, 0,
+ 19,
+ OPC_CheckPredicate, 112,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitNode, TARGET_OPCODE(X86::LD_Fp064), 0,
+ 1, MVT::f64, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CHS_Fp64), 0,
+ 1, MVT::f64, 1, 0,
+ 19,
+ OPC_CheckPredicate, 113,
+ OPC_CheckPatternPredicate, 7,
+ OPC_EmitNode, TARGET_OPCODE(X86::LD_Fp164), 0,
+ 1, MVT::f64, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CHS_Fp64), 0,
+ 1, MVT::f64, 1, 0,
+ 0,
+ 58, MVT::f80,
+ OPC_Scope, 9,
+ OPC_CheckPredicate, 109,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp080), 0,
+ 1, MVT::f80, 0,
+ 9,
+ OPC_CheckPredicate, 110,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::LD_Fp180), 0,
+ 1, MVT::f80, 0,
+ 17,
+ OPC_CheckPredicate, 112,
+ OPC_EmitNode, TARGET_OPCODE(X86::LD_Fp080), 0,
+ 1, MVT::f80, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CHS_Fp80), 0,
+ 1, MVT::f80, 1, 0,
+ 17,
+ OPC_CheckPredicate, 113,
+ OPC_EmitNode, TARGET_OPCODE(X86::LD_Fp180), 0,
+ 1, MVT::f80, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::CHS_Fp80), 0,
+ 1, MVT::f80, 1, 0,
+ 0,
0,
15|128,1, ISD::BUILD_VECTOR,
OPC_Scope, 60,
@@ -34300,11 +32424,10 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::COS_Fp80), 0,
1, MVT::f80, 1, 0,
0,
- 93, X86ISD::INC,
+ 89, X86ISD::INC,
OPC_RecordChild0,
- OPC_Scope, 30,
+ OPC_SwitchType , 28, MVT::i16,
OPC_CheckChild0Type, MVT::i16,
- OPC_CheckType, MVT::i16,
OPC_Scope, 11,
OPC_CheckPatternPredicate, 2,
OPC_MorphNodeTo, TARGET_OPCODE(X86::INC16r), 0,
@@ -34314,9 +32437,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::INC64_16r), 0,
2, MVT::i16, MVT::i32, 1, 0,
0,
- 30,
+ 28, MVT::i32,
OPC_CheckChild0Type, MVT::i32,
- OPC_CheckType, MVT::i32,
OPC_Scope, 11,
OPC_CheckPatternPredicate, 2,
OPC_MorphNodeTo, TARGET_OPCODE(X86::INC32r), 0,
@@ -34326,22 +32448,19 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::INC64_32r), 0,
2, MVT::i32, MVT::i32, 1, 0,
0,
- 13,
+ 11, MVT::i8,
OPC_CheckChild0Type, MVT::i8,
- OPC_CheckType, MVT::i8,
OPC_MorphNodeTo, TARGET_OPCODE(X86::INC8r), 0,
2, MVT::i8, MVT::i32, 1, 0,
- 13,
+ 11, MVT::i64,
OPC_CheckChild0Type, MVT::i64,
- OPC_CheckType, MVT::i64,
OPC_MorphNodeTo, TARGET_OPCODE(X86::INC64r), 0,
2, MVT::i64, MVT::i32, 1, 0,
0,
- 93, X86ISD::DEC,
+ 89, X86ISD::DEC,
OPC_RecordChild0,
- OPC_Scope, 30,
+ OPC_SwitchType , 28, MVT::i16,
OPC_CheckChild0Type, MVT::i16,
- OPC_CheckType, MVT::i16,
OPC_Scope, 11,
OPC_CheckPatternPredicate, 2,
OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC16r), 0,
@@ -34351,9 +32470,8 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC64_16r), 0,
2, MVT::i16, MVT::i32, 1, 0,
0,
- 30,
+ 28, MVT::i32,
OPC_CheckChild0Type, MVT::i32,
- OPC_CheckType, MVT::i32,
OPC_Scope, 11,
OPC_CheckPatternPredicate, 2,
OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC32r), 0,
@@ -34363,14 +32481,12 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC64_32r), 0,
2, MVT::i32, MVT::i32, 1, 0,
0,
- 13,
+ 11, MVT::i8,
OPC_CheckChild0Type, MVT::i8,
- OPC_CheckType, MVT::i8,
OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC8r), 0,
2, MVT::i8, MVT::i32, 1, 0,
- 13,
+ 11, MVT::i64,
OPC_CheckChild0Type, MVT::i64,
- OPC_CheckType, MVT::i64,
OPC_MorphNodeTo, TARGET_OPCODE(X86::DEC64r), 0,
2, MVT::i64, MVT::i32, 1, 0,
0,
@@ -34503,18 +32619,25 @@ SDNode *SelectCode(SDNode *N) {
OPC_MorphNodeTo, TARGET_OPCODE(X86::EH_RETURN64), 0|OPFL_Chain,
0, 1, 1,
0,
- 108|128,1, ISD::SIGN_EXTEND_INREG,
+ 106|128,1, ISD::SIGN_EXTEND_INREG,
OPC_RecordChild0,
OPC_MoveChild, 1,
- OPC_Scope, 25,
+ OPC_Scope, 49,
OPC_CheckValueType, MVT::i16,
OPC_MoveParent,
- OPC_CheckType, MVT::i32,
- OPC_EmitInteger, MVT::i32, 3,
- OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
- 1, MVT::i16, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX32rr16), 0,
- 1, MVT::i32, 1, 2,
+ OPC_SwitchType , 20, MVT::i32,
+ OPC_EmitInteger, MVT::i32, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i16, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX32rr16), 0,
+ 1, MVT::i32, 1, 2,
+ 20, MVT::i64,
+ OPC_EmitInteger, MVT::i32, 3,
+ OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
+ 1, MVT::i16, 2, 0, 1,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX64rr16), 0,
+ 1, MVT::i64, 1, 2,
+ 0,
25,
OPC_CheckValueType, MVT::i32,
OPC_MoveParent,
@@ -34524,15 +32647,6 @@ SDNode *SelectCode(SDNode *N) {
1, MVT::i32, 2, 0, 1,
OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX64rr32), 0,
1, MVT::i64, 1, 2,
- 25,
- OPC_CheckValueType, MVT::i16,
- OPC_MoveParent,
- OPC_CheckType, MVT::i64,
- OPC_EmitInteger, MVT::i32, 3,
- OPC_EmitNode, TARGET_OPCODE(TargetOpcode::EXTRACT_SUBREG), 0,
- 1, MVT::i16, 2, 0, 1,
- OPC_MorphNodeTo, TARGET_OPCODE(X86::MOVSX64rr16), 0,
- 1, MVT::i64, 1, 2,
23|128,1,
OPC_CheckValueType, MVT::i8,
OPC_MoveParent,
@@ -34582,9 +32696,15 @@ SDNode *SelectCode(SDNode *N) {
0,
0,
0,
+ 11, X86ISD::MINGW_ALLOCA,
+ OPC_RecordNode,
+ OPC_CaptureFlagInput,
+ OPC_EmitMergeInputChains, 1, 0,
+ OPC_MorphNodeTo, TARGET_OPCODE(X86::MINGW_ALLOCA), 0|OPFL_Chain|OPFL_FlagInput|OPFL_FlagOutput,
+ 0, 0,
0,
0
- }; // Total Array size is 79144 bytes
+ }; // Total Array size is 77632 bytes
#undef TARGET_OPCODE
return SelectCodeCommon(N, MatcherTable,sizeof(MatcherTable));
@@ -34640,25 +32760,13 @@ bool CheckNodePredicate(SDNode *Node, unsigned PredNo) const {
return false;
}
- case 2: { // Predicate_unindexedstore
- SDNode *N = Node;
-
- return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
-
- }
- case 3: { // Predicate_store
- SDNode *N = Node;
-
- return !cast<StoreSDNode>(N)->isTruncatingStore();
-
- }
- case 4: { // Predicate_unindexedload
+ case 2: { // Predicate_unindexedload
SDNode *N = Node;
return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
}
- case 5: { // Predicate_loadi32
+ case 3: { // Predicate_loadi32
SDNode *N = Node;
LoadSDNode *LD = cast<LoadSDNode>(N);
@@ -34674,6 +32782,18 @@ bool CheckNodePredicate(SDNode *Node, unsigned PredNo) const {
return false;
}
+ case 4: { // Predicate_unindexedstore
+ SDNode *N = Node;
+
+ return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
+
+ }
+ case 5: { // Predicate_store
+ SDNode *N = Node;
+
+ return !cast<StoreSDNode>(N)->isTruncatingStore();
+
+ }
case 6: { // Predicate_loadi16
SDNode *N = Node;
@@ -34702,25 +32822,13 @@ bool CheckNodePredicate(SDNode *Node, unsigned PredNo) const {
N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
}
- case 8: { // Predicate_shld
- SDNode *N = Node;
-
- assert(N->getOpcode() == ISD::OR);
- return N->getOperand(0).getOpcode() == ISD::SHL &&
- N->getOperand(1).getOpcode() == ISD::SRL &&
- isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
- isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
- N->getOperand(0).getConstantOperandVal(1) ==
- N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
-
- }
- case 9: { // Predicate_load
+ case 8: { // Predicate_load
SDNode *N = Node;
return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
}
- case 10: { // Predicate_dsload
+ case 9: { // Predicate_dsload
SDNode *N = Node;
if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
@@ -34730,6 +32838,18 @@ bool CheckNodePredicate(SDNode *Node, unsigned PredNo) const {
return true;
}
+ case 10: { // Predicate_shld
+ SDNode *N = Node;
+
+ assert(N->getOpcode() == ISD::OR);
+ return N->getOperand(0).getOpcode() == ISD::SHL &&
+ N->getOperand(1).getOpcode() == ISD::SRL &&
+ isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
+ isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
+ N->getOperand(0).getConstantOperandVal(1) ==
+ N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
+
+ }
case 11: { // Predicate_immSext8
ConstantSDNode*N = cast<ConstantSDNode>(Node);
@@ -34756,13 +32876,13 @@ bool CheckNodePredicate(SDNode *Node, unsigned PredNo) const {
return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
}
- case 15: { // Predicate_trunc_su
+ case 15: { // Predicate_srl_su
SDNode *N = Node;
return N->hasOneUse();
}
- case 16: { // Predicate_srl_su
+ case 16: { // Predicate_trunc_su
SDNode *N = Node;
return N->hasOneUse();
@@ -34804,17 +32924,17 @@ bool CheckNodePredicate(SDNode *Node, unsigned PredNo) const {
return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));
}
- case 23: { // Predicate_movshdup
+ case 23: { // Predicate_memop
SDNode *N = Node;
- return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
+ return Subtarget->hasVectorUAMem()
+ || cast<LoadSDNode>(N)->getAlignment() >= 16;
}
- case 24: { // Predicate_memop
+ case 24: { // Predicate_movshdup
SDNode *N = Node;
- return Subtarget->hasVectorUAMem()
- || cast<LoadSDNode>(N)->getAlignment() >= 16;
+ return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
}
case 25: { // Predicate_movsldup
@@ -34889,16 +33009,16 @@ bool CheckNodePredicate(SDNode *Node, unsigned PredNo) const {
return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
}
- case 37: { // Predicate_movl
+ case 37: { // Predicate_immAllZerosV_bc
SDNode *N = Node;
- return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
+ return ISD::isBuildVectorAllZeros(N);
}
- case 38: { // Predicate_immAllZerosV_bc
+ case 38: { // Predicate_movl
SDNode *N = Node;
- return ISD::isBuildVectorAllZeros(N);
+ return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
}
case 39: { // Predicate_unpckl_undef
diff --git a/libclamav/c++/X86GenInstrInfo.inc b/libclamav/c++/X86GenInstrInfo.inc
index 98269ea..33e0003 100644
--- a/libclamav/c++/X86GenInstrInfo.inc
+++ b/libclamav/c++/X86GenInstrInfo.inc
@@ -1356,1448 +1356,1449 @@ static const TargetInstrDesc X86Insts[] = {
{ 1078, 3, 1, 0, "MAXSSrr", 0, 0|5|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1078 = MAXSSrr
{ 1079, 3, 1, 0, "MAXSSrr_Int", 0, 0|5|(12<<8)|(95<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1079 = MAXSSrr_Int
{ 1080, 0, 0, 0, "MFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|40|(1<<8)|(174<<24), NULL, NULL, NULL, 0 }, // Inst #1080 = MFENCE
- { 1081, 7, 1, 0, "MINPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1081 = MINPDrm
- { 1082, 7, 1, 0, "MINPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1082 = MINPDrm_Int
- { 1083, 3, 1, 0, "MINPDrr", 0, 0|5|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1083 = MINPDrr
- { 1084, 3, 1, 0, "MINPDrr_Int", 0, 0|5|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1084 = MINPDrr_Int
- { 1085, 7, 1, 0, "MINPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1085 = MINPSrm
- { 1086, 7, 1, 0, "MINPSrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1086 = MINPSrm_Int
- { 1087, 3, 1, 0, "MINPSrr", 0, 0|5|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1087 = MINPSrr
- { 1088, 3, 1, 0, "MINPSrr_Int", 0, 0|5|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1088 = MINPSrr_Int
- { 1089, 7, 1, 0, "MINSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #1089 = MINSDrm
- { 1090, 7, 1, 0, "MINSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1090 = MINSDrm_Int
- { 1091, 3, 1, 0, "MINSDrr", 0, 0|5|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #1091 = MINSDrr
- { 1092, 3, 1, 0, "MINSDrr_Int", 0, 0|5|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1092 = MINSDrr_Int
- { 1093, 7, 1, 0, "MINSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #1093 = MINSSrm
- { 1094, 7, 1, 0, "MINSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1094 = MINSSrm_Int
- { 1095, 3, 1, 0, "MINSSrr", 0, 0|5|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1095 = MINSSrr
- { 1096, 3, 1, 0, "MINSSrr_Int", 0, 0|5|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1096 = MINSSrr_Int
- { 1097, 6, 1, 0, "MMX_CVTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1097 = MMX_CVTPD2PIrm
- { 1098, 2, 1, 0, "MMX_CVTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1098 = MMX_CVTPD2PIrr
- { 1099, 6, 1, 0, "MMX_CVTPI2PDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1099 = MMX_CVTPI2PDrm
- { 1100, 2, 1, 0, "MMX_CVTPI2PDrr", 0, 0|5|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #1100 = MMX_CVTPI2PDrr
- { 1101, 6, 1, 0, "MMX_CVTPI2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1101 = MMX_CVTPI2PSrm
- { 1102, 2, 1, 0, "MMX_CVTPI2PSrr", 0, 0|5|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #1102 = MMX_CVTPI2PSrr
- { 1103, 6, 1, 0, "MMX_CVTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1103 = MMX_CVTPS2PIrm
- { 1104, 2, 1, 0, "MMX_CVTPS2PIrr", 0, 0|5|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1104 = MMX_CVTPS2PIrr
- { 1105, 6, 1, 0, "MMX_CVTTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1105 = MMX_CVTTPD2PIrm
- { 1106, 2, 1, 0, "MMX_CVTTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1106 = MMX_CVTTPD2PIrr
- { 1107, 6, 1, 0, "MMX_CVTTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1107 = MMX_CVTTPS2PIrm
- { 1108, 2, 1, 0, "MMX_CVTTPS2PIrr", 0, 0|5|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1108 = MMX_CVTTPS2PIrr
- { 1109, 0, 0, 0, "MMX_EMMS", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(119<<24), NULL, NULL, NULL, 0 }, // Inst #1109 = MMX_EMMS
- { 1110, 0, 0, 0, "MMX_FEMMS", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(14<<24), NULL, NULL, NULL, 0 }, // Inst #1110 = MMX_FEMMS
- { 1111, 2, 0, 0, "MMX_MASKMOVQ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(247<<24), ImplicitList35, NULL, NULL, OperandInfo129 }, // Inst #1111 = MMX_MASKMOVQ
- { 1112, 2, 0, 0, "MMX_MASKMOVQ64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(247<<24), ImplicitList36, NULL, NULL, OperandInfo129 }, // Inst #1112 = MMX_MASKMOVQ64
- { 1113, 2, 1, 0, "MMX_MOVD64from64rr", 0, 0|3|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo130 }, // Inst #1113 = MMX_MOVD64from64rr
- { 1114, 2, 0, 0, "MMX_MOVD64grr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo131 }, // Inst #1114 = MMX_MOVD64grr
- { 1115, 6, 0, 0, "MMX_MOVD64mr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1115 = MMX_MOVD64mr
- { 1116, 6, 1, 0, "MMX_MOVD64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1116 = MMX_MOVD64rm
- { 1117, 2, 1, 0, "MMX_MOVD64rr", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo133 }, // Inst #1117 = MMX_MOVD64rr
- { 1118, 2, 1, 0, "MMX_MOVD64rrv164", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1118 = MMX_MOVD64rrv164
- { 1119, 2, 1, 0, "MMX_MOVD64to64rr", 0, 0|5|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1119 = MMX_MOVD64to64rr
- { 1120, 2, 1, 0, "MMX_MOVDQ2Qrr", 0, 0|5|(11<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1120 = MMX_MOVDQ2Qrr
- { 1121, 6, 0, 0, "MMX_MOVNTQmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1121 = MMX_MOVNTQmr
- { 1122, 2, 1, 0, "MMX_MOVQ2DQrr", 0, 0|5|(12<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #1122 = MMX_MOVQ2DQrr
- { 1123, 2, 1, 0, "MMX_MOVQ2FR64rr", 0, 0|5|(12<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1123 = MMX_MOVQ2FR64rr
- { 1124, 6, 0, 0, "MMX_MOVQ64gmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1124 = MMX_MOVQ64gmr
- { 1125, 6, 0, 0, "MMX_MOVQ64mr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(127<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1125 = MMX_MOVQ64mr
- { 1126, 6, 1, 0, "MMX_MOVQ64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1126 = MMX_MOVQ64rm
- { 1127, 2, 1, 0, "MMX_MOVQ64rr", 0, 0|5|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1127 = MMX_MOVQ64rr
- { 1128, 6, 1, 0, "MMX_MOVZDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1128 = MMX_MOVZDI2PDIrm
- { 1129, 2, 1, 0, "MMX_MOVZDI2PDIrr", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo133 }, // Inst #1129 = MMX_MOVZDI2PDIrr
- { 1130, 7, 1, 0, "MMX_PACKSSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1130 = MMX_PACKSSDWrm
- { 1131, 3, 1, 0, "MMX_PACKSSDWrr", 0, 0|5|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1131 = MMX_PACKSSDWrr
- { 1132, 7, 1, 0, "MMX_PACKSSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1132 = MMX_PACKSSWBrm
- { 1133, 3, 1, 0, "MMX_PACKSSWBrr", 0, 0|5|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1133 = MMX_PACKSSWBrr
- { 1134, 7, 1, 0, "MMX_PACKUSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1134 = MMX_PACKUSWBrm
- { 1135, 3, 1, 0, "MMX_PACKUSWBrr", 0, 0|5|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1135 = MMX_PACKUSWBrr
- { 1136, 7, 1, 0, "MMX_PADDBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1136 = MMX_PADDBrm
- { 1137, 3, 1, 0, "MMX_PADDBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1137 = MMX_PADDBrr
- { 1138, 7, 1, 0, "MMX_PADDDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1138 = MMX_PADDDrm
- { 1139, 3, 1, 0, "MMX_PADDDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1139 = MMX_PADDDrr
- { 1140, 7, 1, 0, "MMX_PADDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1140 = MMX_PADDQrm
- { 1141, 3, 1, 0, "MMX_PADDQrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1141 = MMX_PADDQrr
- { 1142, 7, 1, 0, "MMX_PADDSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1142 = MMX_PADDSBrm
- { 1143, 3, 1, 0, "MMX_PADDSBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1143 = MMX_PADDSBrr
- { 1144, 7, 1, 0, "MMX_PADDSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1144 = MMX_PADDSWrm
- { 1145, 3, 1, 0, "MMX_PADDSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1145 = MMX_PADDSWrr
- { 1146, 7, 1, 0, "MMX_PADDUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1146 = MMX_PADDUSBrm
- { 1147, 3, 1, 0, "MMX_PADDUSBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1147 = MMX_PADDUSBrr
- { 1148, 7, 1, 0, "MMX_PADDUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1148 = MMX_PADDUSWrm
- { 1149, 3, 1, 0, "MMX_PADDUSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1149 = MMX_PADDUSWrr
- { 1150, 7, 1, 0, "MMX_PADDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1150 = MMX_PADDWrm
- { 1151, 3, 1, 0, "MMX_PADDWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1151 = MMX_PADDWrr
- { 1152, 7, 1, 0, "MMX_PANDNrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1152 = MMX_PANDNrm
- { 1153, 3, 1, 0, "MMX_PANDNrr", 0, 0|5|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1153 = MMX_PANDNrr
- { 1154, 7, 1, 0, "MMX_PANDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1154 = MMX_PANDrm
- { 1155, 3, 1, 0, "MMX_PANDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1155 = MMX_PANDrr
- { 1156, 7, 1, 0, "MMX_PAVGBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1156 = MMX_PAVGBrm
- { 1157, 3, 1, 0, "MMX_PAVGBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1157 = MMX_PAVGBrr
- { 1158, 7, 1, 0, "MMX_PAVGWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1158 = MMX_PAVGWrm
- { 1159, 3, 1, 0, "MMX_PAVGWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1159 = MMX_PAVGWrr
- { 1160, 7, 1, 0, "MMX_PCMPEQBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1160 = MMX_PCMPEQBrm
- { 1161, 3, 1, 0, "MMX_PCMPEQBrr", 0, 0|5|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1161 = MMX_PCMPEQBrr
- { 1162, 7, 1, 0, "MMX_PCMPEQDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1162 = MMX_PCMPEQDrm
- { 1163, 3, 1, 0, "MMX_PCMPEQDrr", 0, 0|5|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1163 = MMX_PCMPEQDrr
- { 1164, 7, 1, 0, "MMX_PCMPEQWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1164 = MMX_PCMPEQWrm
- { 1165, 3, 1, 0, "MMX_PCMPEQWrr", 0, 0|5|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1165 = MMX_PCMPEQWrr
- { 1166, 7, 1, 0, "MMX_PCMPGTBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1166 = MMX_PCMPGTBrm
- { 1167, 3, 1, 0, "MMX_PCMPGTBrr", 0, 0|5|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1167 = MMX_PCMPGTBrr
- { 1168, 7, 1, 0, "MMX_PCMPGTDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1168 = MMX_PCMPGTDrm
- { 1169, 3, 1, 0, "MMX_PCMPGTDrr", 0, 0|5|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1169 = MMX_PCMPGTDrr
- { 1170, 7, 1, 0, "MMX_PCMPGTWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1170 = MMX_PCMPGTWrm
- { 1171, 3, 1, 0, "MMX_PCMPGTWrr", 0, 0|5|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1171 = MMX_PCMPGTWrr
- { 1172, 3, 1, 0, "MMX_PEXTRWri", 0, 0|5|(1<<8)|(1<<13)|(197<<24), NULL, NULL, NULL, OperandInfo138 }, // Inst #1172 = MMX_PEXTRWri
- { 1173, 8, 1, 0, "MMX_PINSRWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo139 }, // Inst #1173 = MMX_PINSRWrmi
- { 1174, 4, 1, 0, "MMX_PINSRWrri", 0, 0|5|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo140 }, // Inst #1174 = MMX_PINSRWrri
- { 1175, 7, 1, 0, "MMX_PMADDWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1175 = MMX_PMADDWDrm
- { 1176, 3, 1, 0, "MMX_PMADDWDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1176 = MMX_PMADDWDrr
- { 1177, 7, 1, 0, "MMX_PMAXSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1177 = MMX_PMAXSWrm
- { 1178, 3, 1, 0, "MMX_PMAXSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1178 = MMX_PMAXSWrr
- { 1179, 7, 1, 0, "MMX_PMAXUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1179 = MMX_PMAXUBrm
- { 1180, 3, 1, 0, "MMX_PMAXUBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1180 = MMX_PMAXUBrr
- { 1181, 7, 1, 0, "MMX_PMINSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1181 = MMX_PMINSWrm
- { 1182, 3, 1, 0, "MMX_PMINSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1182 = MMX_PMINSWrr
- { 1183, 7, 1, 0, "MMX_PMINUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1183 = MMX_PMINUBrm
- { 1184, 3, 1, 0, "MMX_PMINUBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1184 = MMX_PMINUBrr
- { 1185, 2, 1, 0, "MMX_PMOVMSKBrr", 0, 0|5|(1<<8)|(215<<24), NULL, NULL, NULL, OperandInfo131 }, // Inst #1185 = MMX_PMOVMSKBrr
- { 1186, 7, 1, 0, "MMX_PMULHUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1186 = MMX_PMULHUWrm
- { 1187, 3, 1, 0, "MMX_PMULHUWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1187 = MMX_PMULHUWrr
- { 1188, 7, 1, 0, "MMX_PMULHWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1188 = MMX_PMULHWrm
- { 1189, 3, 1, 0, "MMX_PMULHWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1189 = MMX_PMULHWrr
- { 1190, 7, 1, 0, "MMX_PMULLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1190 = MMX_PMULLWrm
- { 1191, 3, 1, 0, "MMX_PMULLWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1191 = MMX_PMULLWrr
- { 1192, 7, 1, 0, "MMX_PMULUDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1192 = MMX_PMULUDQrm
- { 1193, 3, 1, 0, "MMX_PMULUDQrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1193 = MMX_PMULUDQrr
- { 1194, 7, 1, 0, "MMX_PORrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1194 = MMX_PORrm
- { 1195, 3, 1, 0, "MMX_PORrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1195 = MMX_PORrr
- { 1196, 7, 1, 0, "MMX_PSADBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1196 = MMX_PSADBWrm
- { 1197, 3, 1, 0, "MMX_PSADBWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1197 = MMX_PSADBWrr
- { 1198, 7, 1, 0, "MMX_PSHUFWmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo141 }, // Inst #1198 = MMX_PSHUFWmi
- { 1199, 3, 1, 0, "MMX_PSHUFWri", 0, 0|5|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo142 }, // Inst #1199 = MMX_PSHUFWri
- { 1200, 3, 1, 0, "MMX_PSLLDri", 0, 0|22|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1200 = MMX_PSLLDri
- { 1201, 7, 1, 0, "MMX_PSLLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1201 = MMX_PSLLDrm
- { 1202, 3, 1, 0, "MMX_PSLLDrr", 0, 0|5|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1202 = MMX_PSLLDrr
- { 1203, 3, 1, 0, "MMX_PSLLQri", 0, 0|22|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1203 = MMX_PSLLQri
- { 1204, 7, 1, 0, "MMX_PSLLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1204 = MMX_PSLLQrm
- { 1205, 3, 1, 0, "MMX_PSLLQrr", 0, 0|5|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1205 = MMX_PSLLQrr
- { 1206, 3, 1, 0, "MMX_PSLLWri", 0, 0|22|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1206 = MMX_PSLLWri
- { 1207, 7, 1, 0, "MMX_PSLLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1207 = MMX_PSLLWrm
- { 1208, 3, 1, 0, "MMX_PSLLWrr", 0, 0|5|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1208 = MMX_PSLLWrr
- { 1209, 3, 1, 0, "MMX_PSRADri", 0, 0|20|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1209 = MMX_PSRADri
- { 1210, 7, 1, 0, "MMX_PSRADrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1210 = MMX_PSRADrm
- { 1211, 3, 1, 0, "MMX_PSRADrr", 0, 0|5|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1211 = MMX_PSRADrr
- { 1212, 3, 1, 0, "MMX_PSRAWri", 0, 0|20|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1212 = MMX_PSRAWri
- { 1213, 7, 1, 0, "MMX_PSRAWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1213 = MMX_PSRAWrm
- { 1214, 3, 1, 0, "MMX_PSRAWrr", 0, 0|5|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1214 = MMX_PSRAWrr
- { 1215, 3, 1, 0, "MMX_PSRLDri", 0, 0|18|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1215 = MMX_PSRLDri
- { 1216, 7, 1, 0, "MMX_PSRLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1216 = MMX_PSRLDrm
- { 1217, 3, 1, 0, "MMX_PSRLDrr", 0, 0|5|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1217 = MMX_PSRLDrr
- { 1218, 3, 1, 0, "MMX_PSRLQri", 0, 0|18|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1218 = MMX_PSRLQri
- { 1219, 7, 1, 0, "MMX_PSRLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1219 = MMX_PSRLQrm
- { 1220, 3, 1, 0, "MMX_PSRLQrr", 0, 0|5|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1220 = MMX_PSRLQrr
- { 1221, 3, 1, 0, "MMX_PSRLWri", 0, 0|18|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1221 = MMX_PSRLWri
- { 1222, 7, 1, 0, "MMX_PSRLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1222 = MMX_PSRLWrm
- { 1223, 3, 1, 0, "MMX_PSRLWrr", 0, 0|5|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1223 = MMX_PSRLWrr
- { 1224, 7, 1, 0, "MMX_PSUBBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1224 = MMX_PSUBBrm
- { 1225, 3, 1, 0, "MMX_PSUBBrr", 0, 0|5|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1225 = MMX_PSUBBrr
- { 1226, 7, 1, 0, "MMX_PSUBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1226 = MMX_PSUBDrm
- { 1227, 3, 1, 0, "MMX_PSUBDrr", 0, 0|5|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1227 = MMX_PSUBDrr
- { 1228, 7, 1, 0, "MMX_PSUBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1228 = MMX_PSUBQrm
- { 1229, 3, 1, 0, "MMX_PSUBQrr", 0, 0|5|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1229 = MMX_PSUBQrr
- { 1230, 7, 1, 0, "MMX_PSUBSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1230 = MMX_PSUBSBrm
- { 1231, 3, 1, 0, "MMX_PSUBSBrr", 0, 0|5|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1231 = MMX_PSUBSBrr
- { 1232, 7, 1, 0, "MMX_PSUBSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1232 = MMX_PSUBSWrm
- { 1233, 3, 1, 0, "MMX_PSUBSWrr", 0, 0|5|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1233 = MMX_PSUBSWrr
- { 1234, 7, 1, 0, "MMX_PSUBUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1234 = MMX_PSUBUSBrm
- { 1235, 3, 1, 0, "MMX_PSUBUSBrr", 0, 0|5|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1235 = MMX_PSUBUSBrr
- { 1236, 7, 1, 0, "MMX_PSUBUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1236 = MMX_PSUBUSWrm
- { 1237, 3, 1, 0, "MMX_PSUBUSWrr", 0, 0|5|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1237 = MMX_PSUBUSWrr
- { 1238, 7, 1, 0, "MMX_PSUBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1238 = MMX_PSUBWrm
- { 1239, 3, 1, 0, "MMX_PSUBWrr", 0, 0|5|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1239 = MMX_PSUBWrr
- { 1240, 7, 1, 0, "MMX_PUNPCKHBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1240 = MMX_PUNPCKHBWrm
- { 1241, 3, 1, 0, "MMX_PUNPCKHBWrr", 0, 0|5|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1241 = MMX_PUNPCKHBWrr
- { 1242, 7, 1, 0, "MMX_PUNPCKHDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1242 = MMX_PUNPCKHDQrm
- { 1243, 3, 1, 0, "MMX_PUNPCKHDQrr", 0, 0|5|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1243 = MMX_PUNPCKHDQrr
- { 1244, 7, 1, 0, "MMX_PUNPCKHWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1244 = MMX_PUNPCKHWDrm
- { 1245, 3, 1, 0, "MMX_PUNPCKHWDrr", 0, 0|5|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1245 = MMX_PUNPCKHWDrr
- { 1246, 7, 1, 0, "MMX_PUNPCKLBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1246 = MMX_PUNPCKLBWrm
- { 1247, 3, 1, 0, "MMX_PUNPCKLBWrr", 0, 0|5|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1247 = MMX_PUNPCKLBWrr
- { 1248, 7, 1, 0, "MMX_PUNPCKLDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1248 = MMX_PUNPCKLDQrm
- { 1249, 3, 1, 0, "MMX_PUNPCKLDQrr", 0, 0|5|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1249 = MMX_PUNPCKLDQrr
- { 1250, 7, 1, 0, "MMX_PUNPCKLWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1250 = MMX_PUNPCKLWDrm
- { 1251, 3, 1, 0, "MMX_PUNPCKLWDrr", 0, 0|5|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1251 = MMX_PUNPCKLWDrr
- { 1252, 7, 1, 0, "MMX_PXORrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1252 = MMX_PXORrm
- { 1253, 3, 1, 0, "MMX_PXORrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1253 = MMX_PXORrr
- { 1254, 1, 1, 0, "MMX_V_SET0", 0|(1<<TID::Rematerializable), 0|32|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo144 }, // Inst #1254 = MMX_V_SET0
- { 1255, 1, 1, 0, "MMX_V_SETALLONES", 0|(1<<TID::Rematerializable), 0|32|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo144 }, // Inst #1255 = MMX_V_SETALLONES
- { 1256, 0, 0, 0, "MONITOR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|37|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #1256 = MONITOR
- { 1257, 1, 1, 0, "MOV16ao16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1257 = MOV16ao16
- { 1258, 6, 0, 0, "MOV16mi", 0|(1<<TID::MayStore), 0|24|(1<<6)|(3<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1258 = MOV16mi
- { 1259, 6, 0, 0, "MOV16mr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(137<<24), NULL, NULL, NULL, OperandInfo7 }, // Inst #1259 = MOV16mr
- { 1260, 6, 1, 0, "MOV16ms", 0|(1<<TID::UnmodeledSideEffects), 0|4|(140<<24), NULL, NULL, NULL, OperandInfo145 }, // Inst #1260 = MOV16ms
- { 1261, 1, 0, 0, "MOV16o16a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1261 = MOV16o16a
- { 1262, 1, 1, 0, "MOV16r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo93 }, // Inst #1262 = MOV16r0
- { 1263, 2, 1, 0, "MOV16ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<6)|(3<<13)|(184<<24), NULL, NULL, NULL, OperandInfo54 }, // Inst #1263 = MOV16ri
- { 1264, 6, 1, 0, "MOV16rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<6)|(139<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1264 = MOV16rm
- { 1265, 2, 1, 0, "MOV16rr", 0, 0|3|(1<<6)|(137<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1265 = MOV16rr
- { 1266, 2, 1, 0, "MOV16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(139<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1266 = MOV16rr_REV
- { 1267, 2, 1, 0, "MOV16rs", 0|(1<<TID::UnmodeledSideEffects), 0|3|(140<<24), NULL, NULL, NULL, OperandInfo146 }, // Inst #1267 = MOV16rs
- { 1268, 6, 1, 0, "MOV16sm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(142<<24), NULL, NULL, NULL, OperandInfo147 }, // Inst #1268 = MOV16sm
- { 1269, 2, 1, 0, "MOV16sr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(142<<24), NULL, NULL, NULL, OperandInfo148 }, // Inst #1269 = MOV16sr
- { 1270, 1, 1, 0, "MOV32ao32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1270 = MOV32ao32
- { 1271, 2, 1, 0, "MOV32cr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(34<<24), NULL, NULL, NULL, OperandInfo149 }, // Inst #1271 = MOV32cr
- { 1272, 2, 1, 0, "MOV32dr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(35<<24), NULL, NULL, NULL, OperandInfo150 }, // Inst #1272 = MOV32dr
- { 1273, 6, 0, 0, "MOV32mi", 0|(1<<TID::MayStore), 0|24|(4<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1273 = MOV32mi
- { 1274, 6, 0, 0, "MOV32mr", 0|(1<<TID::MayStore), 0|4|(137<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #1274 = MOV32mr
- { 1275, 1, 0, 0, "MOV32o32a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1275 = MOV32o32a
- { 1276, 1, 1, 0, "MOV32r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo57 }, // Inst #1276 = MOV32r0
- { 1277, 2, 1, 0, "MOV32rc", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(32<<24), NULL, NULL, NULL, OperandInfo151 }, // Inst #1277 = MOV32rc
- { 1278, 2, 1, 0, "MOV32rd", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(33<<24), NULL, NULL, NULL, OperandInfo152 }, // Inst #1278 = MOV32rd
- { 1279, 2, 1, 0, "MOV32ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(4<<13)|(184<<24), NULL, NULL, NULL, OperandInfo55 }, // Inst #1279 = MOV32ri
- { 1280, 6, 1, 0, "MOV32rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(139<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1280 = MOV32rm
- { 1281, 2, 1, 0, "MOV32rr", 0, 0|3|(137<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1281 = MOV32rr
- { 1282, 2, 1, 0, "MOV32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(139<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1282 = MOV32rr_REV
- { 1283, 6, 1, 0, "MOV64FSrm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(1<<20)|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1283 = MOV64FSrm
- { 1284, 6, 1, 0, "MOV64GSrm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(2<<20)|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1284 = MOV64GSrm
- { 1285, 1, 1, 0, "MOV64ao64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(4<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1285 = MOV64ao64
- { 1286, 1, 1, 0, "MOV64ao8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(1<<13)|(162<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1286 = MOV64ao8
- { 1287, 2, 1, 0, "MOV64cr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(34<<24), NULL, NULL, NULL, OperandInfo153 }, // Inst #1287 = MOV64cr
- { 1288, 2, 1, 0, "MOV64dr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(35<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1288 = MOV64dr
- { 1289, 6, 0, 0, "MOV64mi32", 0|(1<<TID::MayStore), 0|24|(1<<12)|(4<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1289 = MOV64mi32
- { 1290, 6, 0, 0, "MOV64mr", 0|(1<<TID::MayStore), 0|4|(1<<12)|(137<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #1290 = MOV64mr
- { 1291, 6, 1, 0, "MOV64ms", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<12)|(140<<24), NULL, NULL, NULL, OperandInfo145 }, // Inst #1291 = MOV64ms
- { 1292, 1, 0, 0, "MOV64o64a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(4<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1292 = MOV64o64a
- { 1293, 1, 0, 0, "MOV64o8a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(1<<13)|(160<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1293 = MOV64o8a
- { 1294, 1, 1, 0, "MOV64r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo58 }, // Inst #1294 = MOV64r0
- { 1295, 2, 1, 0, "MOV64rc", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(32<<24), NULL, NULL, NULL, OperandInfo155 }, // Inst #1295 = MOV64rc
- { 1296, 2, 1, 0, "MOV64rd", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(33<<24), NULL, NULL, NULL, OperandInfo156 }, // Inst #1296 = MOV64rd
- { 1297, 2, 1, 0, "MOV64ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<12)|(6<<13)|(184<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #1297 = MOV64ri
- { 1298, 2, 1, 0, "MOV64ri32", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|16|(1<<12)|(4<<13)|(199<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #1298 = MOV64ri32
- { 1299, 2, 1, 0, "MOV64ri64i32", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(4<<13)|(184<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #1299 = MOV64ri64i32
- { 1300, 6, 1, 0, "MOV64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<12)|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1300 = MOV64rm
- { 1301, 2, 1, 0, "MOV64rr", 0, 0|3|(1<<12)|(137<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1301 = MOV64rr
- { 1302, 2, 1, 0, "MOV64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(139<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1302 = MOV64rr_REV
- { 1303, 2, 1, 0, "MOV64rs", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<12)|(140<<24), NULL, NULL, NULL, OperandInfo157 }, // Inst #1303 = MOV64rs
- { 1304, 6, 1, 0, "MOV64sm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<12)|(142<<24), NULL, NULL, NULL, OperandInfo147 }, // Inst #1304 = MOV64sm
- { 1305, 2, 1, 0, "MOV64sr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(142<<24), NULL, NULL, NULL, OperandInfo158 }, // Inst #1305 = MOV64sr
- { 1306, 2, 1, 0, "MOV64toPQIrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo159 }, // Inst #1306 = MOV64toPQIrr
- { 1307, 6, 1, 0, "MOV64toSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #1307 = MOV64toSDrm
- { 1308, 2, 1, 0, "MOV64toSDrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo83 }, // Inst #1308 = MOV64toSDrr
- { 1309, 1, 1, 0, "MOV8ao8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(162<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1309 = MOV8ao8
- { 1310, 6, 0, 0, "MOV8mi", 0|(1<<TID::MayStore), 0|24|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1310 = MOV8mi
- { 1311, 6, 0, 0, "MOV8mr", 0|(1<<TID::MayStore), 0|4|(136<<24), NULL, NULL, NULL, OperandInfo20 }, // Inst #1311 = MOV8mr
- { 1312, 6, 0, 0, "MOV8mr_NOREX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(136<<24), NULL, NULL, NULL, OperandInfo160 }, // Inst #1312 = MOV8mr_NOREX
- { 1313, 1, 0, 0, "MOV8o8a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(160<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1313 = MOV8o8a
- { 1314, 1, 1, 0, "MOV8r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo94 }, // Inst #1314 = MOV8r0
- { 1315, 2, 1, 0, "MOV8ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<13)|(176<<24), NULL, NULL, NULL, OperandInfo68 }, // Inst #1315 = MOV8ri
- { 1316, 6, 1, 0, "MOV8rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(138<<24), NULL, NULL, NULL, OperandInfo69 }, // Inst #1316 = MOV8rm
- { 1317, 6, 1, 0, "MOV8rm_NOREX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|6|(138<<24), NULL, NULL, NULL, OperandInfo161 }, // Inst #1317 = MOV8rm_NOREX
- { 1318, 2, 1, 0, "MOV8rr", 0, 0|3|(136<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #1318 = MOV8rr
- { 1319, 2, 1, 0, "MOV8rr_NOREX", 0, 0|3|(136<<24), NULL, NULL, NULL, OperandInfo162 }, // Inst #1319 = MOV8rr_NOREX
- { 1320, 2, 1, 0, "MOV8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(138<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #1320 = MOV8rr_REV
- { 1321, 6, 0, 0, "MOVAPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(41<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1321 = MOVAPDmr
- { 1322, 6, 1, 0, "MOVAPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1322 = MOVAPDrm
- { 1323, 2, 1, 0, "MOVAPDrr", 0, 0|5|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1323 = MOVAPDrr
- { 1324, 6, 0, 0, "MOVAPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(41<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1324 = MOVAPSmr
- { 1325, 6, 1, 0, "MOVAPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1325 = MOVAPSrm
- { 1326, 2, 1, 0, "MOVAPSrr", 0, 0|5|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1326 = MOVAPSrr
- { 1327, 6, 1, 0, "MOVDDUPrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(18<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1327 = MOVDDUPrm
- { 1328, 2, 1, 0, "MOVDDUPrr", 0, 0|5|(11<<8)|(18<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1328 = MOVDDUPrr
- { 1329, 6, 1, 0, "MOVDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1329 = MOVDI2PDIrm
- { 1330, 2, 1, 0, "MOVDI2PDIrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo164 }, // Inst #1330 = MOVDI2PDIrr
- { 1331, 6, 1, 0, "MOVDI2SSrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1331 = MOVDI2SSrm
- { 1332, 2, 1, 0, "MOVDI2SSrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo86 }, // Inst #1332 = MOVDI2SSrr
- { 1333, 6, 0, 0, "MOVDQAmr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(127<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1333 = MOVDQAmr
- { 1334, 6, 1, 0, "MOVDQArm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1334 = MOVDQArm
- { 1335, 2, 1, 0, "MOVDQArr", 0, 0|5|(1<<6)|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1335 = MOVDQArr
- { 1336, 6, 0, 0, "MOVDQUmr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(12<<8)|(127<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1336 = MOVDQUmr
- { 1337, 6, 0, 0, "MOVDQUmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(12<<8)|(127<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1337 = MOVDQUmr_Int
- { 1338, 6, 1, 0, "MOVDQUrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(111<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1338 = MOVDQUrm
- { 1339, 6, 1, 0, "MOVDQUrm_Int", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|6|(12<<8)|(111<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1339 = MOVDQUrm_Int
- { 1340, 3, 1, 0, "MOVHLPSrr", 0, 0|5|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1340 = MOVHLPSrr
- { 1341, 6, 0, 0, "MOVHPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(23<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1341 = MOVHPDmr
- { 1342, 7, 1, 0, "MOVHPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1342 = MOVHPDrm
- { 1343, 6, 0, 0, "MOVHPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(23<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1343 = MOVHPSmr
- { 1344, 7, 1, 0, "MOVHPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1344 = MOVHPSrm
- { 1345, 3, 1, 0, "MOVLHPSrr", 0, 0|5|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1345 = MOVLHPSrr
- { 1346, 6, 0, 0, "MOVLPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(19<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1346 = MOVLPDmr
- { 1347, 7, 1, 0, "MOVLPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1347 = MOVLPDrm
- { 1348, 6, 0, 0, "MOVLPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(19<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1348 = MOVLPSmr
- { 1349, 7, 1, 0, "MOVLPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1349 = MOVLPSrm
- { 1350, 6, 0, 0, "MOVLQ128mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(214<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1350 = MOVLQ128mr
- { 1351, 2, 1, 0, "MOVMSKPDrr", 0, 0|5|(1<<6)|(1<<8)|(80<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1351 = MOVMSKPDrr
- { 1352, 2, 1, 0, "MOVMSKPSrr", 0, 0|5|(1<<8)|(80<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1352 = MOVMSKPSrr
- { 1353, 6, 1, 0, "MOVNTDQArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1353 = MOVNTDQArm
- { 1354, 6, 0, 0, "MOVNTDQ_64mr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1354 = MOVNTDQ_64mr
- { 1355, 6, 0, 0, "MOVNTDQmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1355 = MOVNTDQmr
- { 1356, 6, 0, 0, "MOVNTDQmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1356 = MOVNTDQmr_Int
- { 1357, 6, 0, 0, "MOVNTI_64mr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(195<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #1357 = MOVNTI_64mr
- { 1358, 6, 0, 0, "MOVNTImr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(195<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #1358 = MOVNTImr
- { 1359, 6, 0, 0, "MOVNTImr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(195<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #1359 = MOVNTImr_Int
- { 1360, 6, 0, 0, "MOVNTPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1360 = MOVNTPDmr
- { 1361, 6, 0, 0, "MOVNTPDmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1361 = MOVNTPDmr_Int
- { 1362, 6, 0, 0, "MOVNTPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1362 = MOVNTPSmr
- { 1363, 6, 0, 0, "MOVNTPSmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1363 = MOVNTPSmr_Int
- { 1364, 2, 1, 0, "MOVPC32r", 0|(1<<TID::NotDuplicable), 0|(4<<13)|(232<<24), ImplicitList2, NULL, NULL, OperandInfo55 }, // Inst #1364 = MOVPC32r
- { 1365, 6, 0, 0, "MOVPDI2DImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1365 = MOVPDI2DImr
- { 1366, 2, 1, 0, "MOVPDI2DIrr", 0, 0|3|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1366 = MOVPDI2DIrr
- { 1367, 6, 0, 0, "MOVPQI2QImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(214<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1367 = MOVPQI2QImr
- { 1368, 2, 1, 0, "MOVPQIto64rr", 0, 0|3|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #1368 = MOVPQIto64rr
- { 1369, 6, 1, 0, "MOVQI2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1369 = MOVQI2PQIrm
- { 1370, 2, 1, 0, "MOVQxrxr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1370 = MOVQxrxr
- { 1371, 0, 0, 0, "MOVSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(164<<24), ImplicitList37, ImplicitList38, NULL, 0 }, // Inst #1371 = MOVSB
- { 1372, 0, 0, 0, "MOVSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(165<<24), ImplicitList37, ImplicitList38, NULL, 0 }, // Inst #1372 = MOVSD
- { 1373, 6, 0, 0, "MOVSDmr", 0|(1<<TID::MayStore), 0|4|(11<<8)|(17<<24), NULL, NULL, NULL, OperandInfo165 }, // Inst #1373 = MOVSDmr
- { 1374, 6, 1, 0, "MOVSDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #1374 = MOVSDrm
- { 1375, 3, 1, 0, "MOVSDrr", 0, 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo166 }, // Inst #1375 = MOVSDrr
- { 1376, 6, 0, 0, "MOVSDto64mr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo165 }, // Inst #1376 = MOVSDto64mr
- { 1377, 2, 1, 0, "MOVSDto64rr", 0, 0|3|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo79 }, // Inst #1377 = MOVSDto64rr
- { 1378, 6, 1, 0, "MOVSHDUPrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(22<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1378 = MOVSHDUPrm
- { 1379, 2, 1, 0, "MOVSHDUPrr", 0, 0|5|(12<<8)|(22<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1379 = MOVSHDUPrr
- { 1380, 6, 1, 0, "MOVSLDUPrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(18<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1380 = MOVSLDUPrm
- { 1381, 2, 1, 0, "MOVSLDUPrr", 0, 0|5|(12<<8)|(18<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1381 = MOVSLDUPrr
- { 1382, 6, 0, 0, "MOVSS2DImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo167 }, // Inst #1382 = MOVSS2DImr
- { 1383, 2, 1, 0, "MOVSS2DIrr", 0, 0|3|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo89 }, // Inst #1383 = MOVSS2DIrr
- { 1384, 6, 0, 0, "MOVSSmr", 0|(1<<TID::MayStore), 0|4|(12<<8)|(17<<24), NULL, NULL, NULL, OperandInfo167 }, // Inst #1384 = MOVSSmr
- { 1385, 6, 1, 0, "MOVSSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1385 = MOVSSrm
- { 1386, 3, 1, 0, "MOVSSrr", 0, 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo168 }, // Inst #1386 = MOVSSrr
- { 1387, 0, 0, 0, "MOVSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(165<<24), ImplicitList37, ImplicitList38, NULL, 0 }, // Inst #1387 = MOVSW
- { 1388, 6, 1, 0, "MOVSX16rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1388 = MOVSX16rm8
- { 1389, 6, 1, 0, "MOVSX16rm8W", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1389 = MOVSX16rm8W
- { 1390, 2, 1, 0, "MOVSX16rr8", 0, 0|5|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo169 }, // Inst #1390 = MOVSX16rr8
- { 1391, 2, 1, 0, "MOVSX16rr8W", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo169 }, // Inst #1391 = MOVSX16rr8W
- { 1392, 6, 1, 0, "MOVSX32rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(191<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1392 = MOVSX32rm16
- { 1393, 6, 1, 0, "MOVSX32rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1393 = MOVSX32rm8
- { 1394, 2, 1, 0, "MOVSX32rr16", 0, 0|5|(1<<8)|(191<<24), NULL, NULL, NULL, OperandInfo170 }, // Inst #1394 = MOVSX32rr16
- { 1395, 2, 1, 0, "MOVSX32rr8", 0, 0|5|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo171 }, // Inst #1395 = MOVSX32rr8
- { 1396, 6, 1, 0, "MOVSX64rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(191<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1396 = MOVSX64rm16
- { 1397, 6, 1, 0, "MOVSX64rm32", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(99<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1397 = MOVSX64rm32
- { 1398, 6, 1, 0, "MOVSX64rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(190<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1398 = MOVSX64rm8
- { 1399, 2, 1, 0, "MOVSX64rr16", 0, 0|5|(1<<8)|(1<<12)|(191<<24), NULL, NULL, NULL, OperandInfo172 }, // Inst #1399 = MOVSX64rr16
- { 1400, 2, 1, 0, "MOVSX64rr32", 0, 0|5|(1<<12)|(99<<24), NULL, NULL, NULL, OperandInfo125 }, // Inst #1400 = MOVSX64rr32
- { 1401, 2, 1, 0, "MOVSX64rr8", 0, 0|5|(1<<8)|(1<<12)|(190<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1401 = MOVSX64rr8
- { 1402, 6, 0, 0, "MOVUPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1402 = MOVUPDmr
- { 1403, 6, 0, 0, "MOVUPDmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1403 = MOVUPDmr_Int
- { 1404, 6, 1, 0, "MOVUPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1404 = MOVUPDrm
- { 1405, 6, 1, 0, "MOVUPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1405 = MOVUPDrm_Int
- { 1406, 2, 1, 0, "MOVUPDrr", 0, 0|5|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1406 = MOVUPDrr
- { 1407, 6, 0, 0, "MOVUPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1407 = MOVUPSmr
- { 1408, 6, 0, 0, "MOVUPSmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1408 = MOVUPSmr_Int
- { 1409, 6, 1, 0, "MOVUPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1409 = MOVUPSrm
- { 1410, 6, 1, 0, "MOVUPSrm_Int", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1410 = MOVUPSrm_Int
- { 1411, 2, 1, 0, "MOVUPSrr", 0, 0|5|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1411 = MOVUPSrr
- { 1412, 6, 1, 0, "MOVZDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1412 = MOVZDI2PDIrm
- { 1413, 2, 1, 0, "MOVZDI2PDIrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo164 }, // Inst #1413 = MOVZDI2PDIrr
- { 1414, 6, 1, 0, "MOVZPQILo2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1414 = MOVZPQILo2PQIrm
- { 1415, 2, 1, 0, "MOVZPQILo2PQIrr", 0, 0|5|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1415 = MOVZPQILo2PQIrr
- { 1416, 6, 1, 0, "MOVZQI2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1416 = MOVZQI2PQIrm
- { 1417, 2, 1, 0, "MOVZQI2PQIrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo159 }, // Inst #1417 = MOVZQI2PQIrr
- { 1418, 6, 1, 0, "MOVZX16rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1418 = MOVZX16rm8
- { 1419, 6, 1, 0, "MOVZX16rm8W", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1419 = MOVZX16rm8W
- { 1420, 2, 1, 0, "MOVZX16rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo169 }, // Inst #1420 = MOVZX16rr8
- { 1421, 2, 1, 0, "MOVZX16rr8W", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo169 }, // Inst #1421 = MOVZX16rr8W
- { 1422, 6, 1, 0, "MOVZX32_NOREXrm8", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo174 }, // Inst #1422 = MOVZX32_NOREXrm8
- { 1423, 2, 1, 0, "MOVZX32_NOREXrr8", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo175 }, // Inst #1423 = MOVZX32_NOREXrr8
- { 1424, 6, 1, 0, "MOVZX32rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1424 = MOVZX32rm16
- { 1425, 6, 1, 0, "MOVZX32rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1425 = MOVZX32rm8
- { 1426, 2, 1, 0, "MOVZX32rr16", 0, 0|5|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo170 }, // Inst #1426 = MOVZX32rr16
- { 1427, 2, 1, 0, "MOVZX32rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo171 }, // Inst #1427 = MOVZX32rr8
- { 1428, 6, 1, 0, "MOVZX64rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1428 = MOVZX64rm16
- { 1429, 6, 1, 0, "MOVZX64rm16_Q", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(183<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1429 = MOVZX64rm16_Q
- { 1430, 6, 1, 0, "MOVZX64rm32", 0|(1<<TID::MayLoad), 0|6|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1430 = MOVZX64rm32
- { 1431, 6, 1, 0, "MOVZX64rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1431 = MOVZX64rm8
- { 1432, 6, 1, 0, "MOVZX64rm8_Q", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(182<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1432 = MOVZX64rm8_Q
- { 1433, 2, 1, 0, "MOVZX64rr16", 0, 0|5|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo172 }, // Inst #1433 = MOVZX64rr16
- { 1434, 2, 1, 0, "MOVZX64rr16_Q", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(183<<24), NULL, NULL, NULL, OperandInfo172 }, // Inst #1434 = MOVZX64rr16_Q
- { 1435, 2, 1, 0, "MOVZX64rr32", 0, 0|3|(137<<24), NULL, NULL, NULL, OperandInfo125 }, // Inst #1435 = MOVZX64rr32
- { 1436, 2, 1, 0, "MOVZX64rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1436 = MOVZX64rr8
- { 1437, 2, 1, 0, "MOVZX64rr8_Q", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(182<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1437 = MOVZX64rr8_Q
- { 1438, 2, 1, 0, "MOV_Fp3232", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #1438 = MOV_Fp3232
- { 1439, 2, 1, 0, "MOV_Fp3264", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo176 }, // Inst #1439 = MOV_Fp3264
- { 1440, 2, 1, 0, "MOV_Fp3280", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo177 }, // Inst #1440 = MOV_Fp3280
- { 1441, 2, 1, 0, "MOV_Fp6432", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo178 }, // Inst #1441 = MOV_Fp6432
- { 1442, 2, 1, 0, "MOV_Fp6464", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #1442 = MOV_Fp6464
- { 1443, 2, 1, 0, "MOV_Fp6480", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo179 }, // Inst #1443 = MOV_Fp6480
- { 1444, 2, 1, 0, "MOV_Fp8032", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo180 }, // Inst #1444 = MOV_Fp8032
- { 1445, 2, 1, 0, "MOV_Fp8064", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo181 }, // Inst #1445 = MOV_Fp8064
- { 1446, 2, 1, 0, "MOV_Fp8080", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #1446 = MOV_Fp8080
- { 1447, 8, 1, 0, "MPSADBWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(66<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1447 = MPSADBWrmi
- { 1448, 4, 1, 0, "MPSADBWrri", 0|(1<<TID::Commutable), 0|5|(1<<6)|(14<<8)|(1<<13)|(66<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1448 = MPSADBWrri
- { 1449, 5, 0, 0, "MUL16m", 0|(1<<TID::MayLoad), 0|28|(1<<6)|(247<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo30 }, // Inst #1449 = MUL16m
- { 1450, 1, 0, 0, "MUL16r", 0, 0|20|(1<<6)|(247<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo93 }, // Inst #1450 = MUL16r
- { 1451, 5, 0, 0, "MUL32m", 0|(1<<TID::MayLoad), 0|28|(247<<24), ImplicitList13, ImplicitList18, Barriers6, OperandInfo30 }, // Inst #1451 = MUL32m
- { 1452, 1, 0, 0, "MUL32r", 0, 0|20|(247<<24), ImplicitList13, ImplicitList18, Barriers6, OperandInfo57 }, // Inst #1452 = MUL32r
- { 1453, 5, 0, 0, "MUL64m", 0|(1<<TID::MayLoad), 0|28|(1<<12)|(247<<24), ImplicitList15, ImplicitList17, Barriers1, OperandInfo30 }, // Inst #1453 = MUL64m
- { 1454, 1, 0, 0, "MUL64r", 0, 0|20|(1<<12)|(247<<24), ImplicitList15, ImplicitList17, Barriers1, OperandInfo58 }, // Inst #1454 = MUL64r
- { 1455, 5, 0, 0, "MUL8m", 0|(1<<TID::MayLoad), 0|28|(246<<24), ImplicitList11, ImplicitList22, Barriers1, OperandInfo30 }, // Inst #1455 = MUL8m
- { 1456, 1, 0, 0, "MUL8r", 0, 0|20|(246<<24), ImplicitList11, ImplicitList22, Barriers1, OperandInfo94 }, // Inst #1456 = MUL8r
- { 1457, 7, 1, 0, "MULPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1457 = MULPDrm
- { 1458, 3, 1, 0, "MULPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1458 = MULPDrr
- { 1459, 7, 1, 0, "MULPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1459 = MULPSrm
- { 1460, 3, 1, 0, "MULPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1460 = MULPSrr
- { 1461, 7, 1, 0, "MULSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #1461 = MULSDrm
- { 1462, 7, 1, 0, "MULSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1462 = MULSDrm_Int
- { 1463, 3, 1, 0, "MULSDrr", 0|(1<<TID::Commutable), 0|5|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #1463 = MULSDrr
- { 1464, 3, 1, 0, "MULSDrr_Int", 0, 0|5|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1464 = MULSDrr_Int
- { 1465, 7, 1, 0, "MULSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #1465 = MULSSrm
- { 1466, 7, 1, 0, "MULSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1466 = MULSSrm_Int
- { 1467, 3, 1, 0, "MULSSrr", 0|(1<<TID::Commutable), 0|5|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1467 = MULSSrr
- { 1468, 3, 1, 0, "MULSSrr_Int", 0, 0|5|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1468 = MULSSrr_Int
- { 1469, 5, 0, 0, "MUL_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1469 = MUL_F32m
- { 1470, 5, 0, 0, "MUL_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1470 = MUL_F64m
- { 1471, 5, 0, 0, "MUL_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1471 = MUL_FI16m
- { 1472, 5, 0, 0, "MUL_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1472 = MUL_FI32m
- { 1473, 1, 0, 0, "MUL_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1473 = MUL_FPrST0
- { 1474, 1, 0, 0, "MUL_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1474 = MUL_FST0r
- { 1475, 3, 1, 0, "MUL_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #1475 = MUL_Fp32
- { 1476, 7, 1, 0, "MUL_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1476 = MUL_Fp32m
- { 1477, 3, 1, 0, "MUL_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #1477 = MUL_Fp64
- { 1478, 7, 1, 0, "MUL_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1478 = MUL_Fp64m
- { 1479, 7, 1, 0, "MUL_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1479 = MUL_Fp64m32
- { 1480, 3, 1, 0, "MUL_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #1480 = MUL_Fp80
- { 1481, 7, 1, 0, "MUL_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1481 = MUL_Fp80m32
- { 1482, 7, 1, 0, "MUL_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1482 = MUL_Fp80m64
- { 1483, 7, 1, 0, "MUL_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1483 = MUL_FpI16m32
- { 1484, 7, 1, 0, "MUL_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1484 = MUL_FpI16m64
- { 1485, 7, 1, 0, "MUL_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1485 = MUL_FpI16m80
- { 1486, 7, 1, 0, "MUL_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1486 = MUL_FpI32m32
- { 1487, 7, 1, 0, "MUL_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1487 = MUL_FpI32m64
- { 1488, 7, 1, 0, "MUL_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1488 = MUL_FpI32m80
- { 1489, 1, 0, 0, "MUL_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1489 = MUL_FrST0
- { 1490, 0, 0, 0, "MWAIT", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|38|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #1490 = MWAIT
- { 1491, 5, 0, 0, "NEG16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1491 = NEG16m
- { 1492, 2, 1, 0, "NEG16r", 0, 0|19|(1<<6)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1492 = NEG16r
- { 1493, 5, 0, 0, "NEG32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1493 = NEG32m
- { 1494, 2, 1, 0, "NEG32r", 0, 0|19|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1494 = NEG32r
- { 1495, 5, 0, 0, "NEG64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1495 = NEG64m
- { 1496, 2, 1, 0, "NEG64r", 0, 0|19|(1<<12)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1496 = NEG64r
- { 1497, 5, 0, 0, "NEG8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1497 = NEG8m
- { 1498, 2, 1, 0, "NEG8r", 0, 0|19|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1498 = NEG8r
- { 1499, 0, 0, 0, "NOOP", 0, 0|1|(144<<24), NULL, NULL, NULL, 0 }, // Inst #1499 = NOOP
- { 1500, 5, 0, 0, "NOOPL", 0, 0|24|(1<<8)|(31<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1500 = NOOPL
- { 1501, 5, 0, 0, "NOOPW", 0, 0|24|(1<<6)|(1<<8)|(31<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1501 = NOOPW
- { 1502, 5, 0, 0, "NOT16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<6)|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1502 = NOT16m
- { 1503, 2, 1, 0, "NOT16r", 0, 0|18|(1<<6)|(247<<24), NULL, NULL, NULL, OperandInfo91 }, // Inst #1503 = NOT16r
- { 1504, 5, 0, 0, "NOT32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1504 = NOT32m
- { 1505, 2, 1, 0, "NOT32r", 0, 0|18|(247<<24), NULL, NULL, NULL, OperandInfo52 }, // Inst #1505 = NOT32r
- { 1506, 5, 0, 0, "NOT64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<12)|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1506 = NOT64m
- { 1507, 2, 1, 0, "NOT64r", 0, 0|18|(1<<12)|(247<<24), NULL, NULL, NULL, OperandInfo53 }, // Inst #1507 = NOT64r
- { 1508, 5, 0, 0, "NOT8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(246<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1508 = NOT8m
- { 1509, 2, 1, 0, "NOT8r", 0, 0|18|(246<<24), NULL, NULL, NULL, OperandInfo92 }, // Inst #1509 = NOT8r
- { 1510, 1, 0, 0, "OR16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1510 = OR16i16
- { 1511, 6, 0, 0, "OR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1511 = OR16mi
- { 1512, 6, 0, 0, "OR16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1512 = OR16mi8
- { 1513, 6, 0, 0, "OR16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #1513 = OR16mr
- { 1514, 3, 1, 0, "OR16ri", 0, 0|17|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1514 = OR16ri
- { 1515, 3, 1, 0, "OR16ri8", 0, 0|17|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1515 = OR16ri8
- { 1516, 7, 1, 0, "OR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1516 = OR16rm
- { 1517, 3, 1, 0, "OR16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #1517 = OR16rr
- { 1518, 3, 1, 0, "OR16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #1518 = OR16rr_REV
- { 1519, 1, 0, 0, "OR32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1519 = OR32i32
- { 1520, 6, 0, 0, "OR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1520 = OR32mi
- { 1521, 6, 0, 0, "OR32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1521 = OR32mi8
- { 1522, 6, 0, 0, "OR32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #1522 = OR32mr
- { 1523, 3, 1, 0, "OR32ri", 0, 0|17|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1523 = OR32ri
- { 1524, 3, 1, 0, "OR32ri8", 0, 0|17|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1524 = OR32ri8
- { 1525, 7, 1, 0, "OR32rm", 0|(1<<TID::MayLoad), 0|6|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #1525 = OR32rm
- { 1526, 3, 1, 0, "OR32rr", 0|(1<<TID::Commutable), 0|3|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #1526 = OR32rr
- { 1527, 3, 1, 0, "OR32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #1527 = OR32rr_REV
- { 1528, 1, 0, 0, "OR64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(4<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1528 = OR64i32
- { 1529, 6, 0, 0, "OR64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1529 = OR64mi32
- { 1530, 6, 0, 0, "OR64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1530 = OR64mi8
- { 1531, 6, 0, 0, "OR64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #1531 = OR64mr
- { 1532, 3, 1, 0, "OR64ri32", 0, 0|17|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1532 = OR64ri32
- { 1533, 3, 1, 0, "OR64ri8", 0, 0|17|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1533 = OR64ri8
- { 1534, 7, 1, 0, "OR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #1534 = OR64rm
- { 1535, 3, 1, 0, "OR64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #1535 = OR64rr
- { 1536, 3, 1, 0, "OR64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #1536 = OR64rr_REV
- { 1537, 1, 0, 0, "OR8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(12<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1537 = OR8i8
- { 1538, 6, 0, 0, "OR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1538 = OR8mi
- { 1539, 6, 0, 0, "OR8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(8<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1539 = OR8mr
- { 1540, 3, 1, 0, "OR8ri", 0, 0|17|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1540 = OR8ri
- { 1541, 7, 1, 0, "OR8rm", 0|(1<<TID::MayLoad), 0|6|(10<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1541 = OR8rm
- { 1542, 3, 1, 0, "OR8rr", 0|(1<<TID::Commutable), 0|3|(8<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #1542 = OR8rr
- { 1543, 3, 1, 0, "OR8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(10<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #1543 = OR8rr_REV
- { 1544, 7, 1, 0, "ORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1544 = ORPDrm
- { 1545, 3, 1, 0, "ORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1545 = ORPDrr
- { 1546, 7, 1, 0, "ORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1546 = ORPSrm
- { 1547, 3, 1, 0, "ORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1547 = ORPSrr
- { 1548, 1, 0, 0, "OUT16ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<13)|(231<<24), ImplicitList12, NULL, NULL, OperandInfo5 }, // Inst #1548 = OUT16ir
- { 1549, 0, 0, 0, "OUT16rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(239<<24), ImplicitList39, NULL, NULL, 0 }, // Inst #1549 = OUT16rr
- { 1550, 1, 0, 0, "OUT32ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(231<<24), ImplicitList13, NULL, NULL, OperandInfo5 }, // Inst #1550 = OUT32ir
- { 1551, 0, 0, 0, "OUT32rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(239<<24), ImplicitList40, NULL, NULL, 0 }, // Inst #1551 = OUT32rr
- { 1552, 1, 0, 0, "OUT8ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(230<<24), ImplicitList11, NULL, NULL, OperandInfo5 }, // Inst #1552 = OUT8ir
- { 1553, 0, 0, 0, "OUT8rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(238<<24), ImplicitList41, NULL, NULL, 0 }, // Inst #1553 = OUT8rr
- { 1554, 0, 0, 0, "OUTSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(110<<24), NULL, NULL, NULL, 0 }, // Inst #1554 = OUTSB
- { 1555, 0, 0, 0, "OUTSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(111<<24), NULL, NULL, NULL, 0 }, // Inst #1555 = OUTSD
- { 1556, 0, 0, 0, "OUTSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(111<<24), NULL, NULL, NULL, 0 }, // Inst #1556 = OUTSW
- { 1557, 6, 1, 0, "PABSBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1557 = PABSBrm128
- { 1558, 6, 1, 0, "PABSBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1558 = PABSBrm64
- { 1559, 2, 1, 0, "PABSBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1559 = PABSBrr128
- { 1560, 2, 1, 0, "PABSBrr64", 0, 0|5|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1560 = PABSBrr64
- { 1561, 6, 1, 0, "PABSDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1561 = PABSDrm128
- { 1562, 6, 1, 0, "PABSDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1562 = PABSDrm64
- { 1563, 2, 1, 0, "PABSDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1563 = PABSDrr128
- { 1564, 2, 1, 0, "PABSDrr64", 0, 0|5|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1564 = PABSDrr64
- { 1565, 6, 1, 0, "PABSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1565 = PABSWrm128
- { 1566, 6, 1, 0, "PABSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1566 = PABSWrm64
- { 1567, 2, 1, 0, "PABSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1567 = PABSWrr128
- { 1568, 2, 1, 0, "PABSWrr64", 0, 0|5|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1568 = PABSWrr64
- { 1569, 7, 1, 0, "PACKSSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1569 = PACKSSDWrm
- { 1570, 3, 1, 0, "PACKSSDWrr", 0, 0|5|(1<<6)|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1570 = PACKSSDWrr
- { 1571, 7, 1, 0, "PACKSSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1571 = PACKSSWBrm
- { 1572, 3, 1, 0, "PACKSSWBrr", 0, 0|5|(1<<6)|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1572 = PACKSSWBrr
- { 1573, 7, 1, 0, "PACKUSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(43<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1573 = PACKUSDWrm
- { 1574, 3, 1, 0, "PACKUSDWrr", 0, 0|5|(1<<6)|(13<<8)|(43<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1574 = PACKUSDWrr
- { 1575, 7, 1, 0, "PACKUSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1575 = PACKUSWBrm
- { 1576, 3, 1, 0, "PACKUSWBrr", 0, 0|5|(1<<6)|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1576 = PACKUSWBrr
- { 1577, 7, 1, 0, "PADDBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1577 = PADDBrm
- { 1578, 3, 1, 0, "PADDBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1578 = PADDBrr
- { 1579, 7, 1, 0, "PADDDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1579 = PADDDrm
- { 1580, 3, 1, 0, "PADDDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1580 = PADDDrr
- { 1581, 7, 1, 0, "PADDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1581 = PADDQrm
- { 1582, 3, 1, 0, "PADDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1582 = PADDQrr
- { 1583, 7, 1, 0, "PADDSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1583 = PADDSBrm
- { 1584, 3, 1, 0, "PADDSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1584 = PADDSBrr
- { 1585, 7, 1, 0, "PADDSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1585 = PADDSWrm
- { 1586, 3, 1, 0, "PADDSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1586 = PADDSWrr
- { 1587, 7, 1, 0, "PADDUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1587 = PADDUSBrm
- { 1588, 3, 1, 0, "PADDUSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1588 = PADDUSBrr
- { 1589, 7, 1, 0, "PADDUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1589 = PADDUSWrm
- { 1590, 3, 1, 0, "PADDUSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1590 = PADDUSWrr
- { 1591, 7, 1, 0, "PADDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1591 = PADDWrm
- { 1592, 3, 1, 0, "PADDWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1592 = PADDWrr
- { 1593, 8, 1, 0, "PALIGNR128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1593 = PALIGNR128rm
- { 1594, 4, 1, 0, "PALIGNR128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1594 = PALIGNR128rr
- { 1595, 8, 1, 0, "PALIGNR64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo139 }, // Inst #1595 = PALIGNR64rm
- { 1596, 4, 1, 0, "PALIGNR64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo182 }, // Inst #1596 = PALIGNR64rr
- { 1597, 7, 1, 0, "PANDNrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1597 = PANDNrm
- { 1598, 3, 1, 0, "PANDNrr", 0, 0|5|(1<<6)|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1598 = PANDNrr
- { 1599, 7, 1, 0, "PANDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1599 = PANDrm
- { 1600, 3, 1, 0, "PANDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1600 = PANDrr
- { 1601, 7, 1, 0, "PAVGBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1601 = PAVGBrm
- { 1602, 3, 1, 0, "PAVGBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1602 = PAVGBrr
- { 1603, 7, 1, 0, "PAVGWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1603 = PAVGWrm
- { 1604, 3, 1, 0, "PAVGWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1604 = PAVGWrr
- { 1605, 7, 1, 0, "PBLENDVBrm0", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(16<<24), ImplicitList8, NULL, NULL, OperandInfo24 }, // Inst #1605 = PBLENDVBrm0
- { 1606, 3, 1, 0, "PBLENDVBrr0", 0, 0|5|(1<<6)|(13<<8)|(16<<24), ImplicitList8, NULL, NULL, OperandInfo25 }, // Inst #1606 = PBLENDVBrr0
- { 1607, 8, 1, 0, "PBLENDWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(14<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1607 = PBLENDWrmi
- { 1608, 4, 1, 0, "PBLENDWrri", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(14<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1608 = PBLENDWrri
- { 1609, 7, 1, 0, "PCMPEQBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1609 = PCMPEQBrm
- { 1610, 3, 1, 0, "PCMPEQBrr", 0, 0|5|(1<<6)|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1610 = PCMPEQBrr
- { 1611, 7, 1, 0, "PCMPEQDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1611 = PCMPEQDrm
- { 1612, 3, 1, 0, "PCMPEQDrr", 0, 0|5|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1612 = PCMPEQDrr
- { 1613, 7, 1, 0, "PCMPEQQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(41<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1613 = PCMPEQQrm
- { 1614, 3, 1, 0, "PCMPEQQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(41<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1614 = PCMPEQQrr
- { 1615, 7, 1, 0, "PCMPEQWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1615 = PCMPEQWrm
- { 1616, 3, 1, 0, "PCMPEQWrr", 0, 0|5|(1<<6)|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1616 = PCMPEQWrr
- { 1617, 7, 0, 0, "PCMPESTRIArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1617 = PCMPESTRIArm
- { 1618, 3, 0, 0, "PCMPESTRIArr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1618 = PCMPESTRIArr
- { 1619, 7, 0, 0, "PCMPESTRICrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1619 = PCMPESTRICrm
- { 1620, 3, 0, 0, "PCMPESTRICrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1620 = PCMPESTRICrr
- { 1621, 7, 0, 0, "PCMPESTRIOrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1621 = PCMPESTRIOrm
- { 1622, 3, 0, 0, "PCMPESTRIOrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1622 = PCMPESTRIOrr
- { 1623, 7, 0, 0, "PCMPESTRISrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1623 = PCMPESTRISrm
- { 1624, 3, 0, 0, "PCMPESTRISrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1624 = PCMPESTRISrr
- { 1625, 7, 0, 0, "PCMPESTRIZrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1625 = PCMPESTRIZrm
- { 1626, 3, 0, 0, "PCMPESTRIZrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1626 = PCMPESTRIZrr
- { 1627, 7, 0, 0, "PCMPESTRIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1627 = PCMPESTRIrm
- { 1628, 3, 0, 0, "PCMPESTRIrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1628 = PCMPESTRIrr
- { 1629, 8, 1, 0, "PCMPESTRM128MEM", 0|(1<<TID::MayLoad)|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), ImplicitList14, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1629 = PCMPESTRM128MEM
- { 1630, 4, 1, 0, "PCMPESTRM128REG", 0|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), ImplicitList14, ImplicitList1, Barriers1, OperandInfo66 }, // Inst #1630 = PCMPESTRM128REG
- { 1631, 7, 0, 0, "PCMPESTRM128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(96<<24), ImplicitList14, ImplicitList43, Barriers1, OperandInfo183 }, // Inst #1631 = PCMPESTRM128rm
- { 1632, 3, 0, 0, "PCMPESTRM128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(96<<24), ImplicitList14, ImplicitList43, Barriers1, OperandInfo184 }, // Inst #1632 = PCMPESTRM128rr
- { 1633, 7, 1, 0, "PCMPGTBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1633 = PCMPGTBrm
- { 1634, 3, 1, 0, "PCMPGTBrr", 0, 0|5|(1<<6)|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1634 = PCMPGTBrr
- { 1635, 7, 1, 0, "PCMPGTDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1635 = PCMPGTDrm
- { 1636, 3, 1, 0, "PCMPGTDrr", 0, 0|5|(1<<6)|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1636 = PCMPGTDrr
- { 1637, 7, 1, 0, "PCMPGTQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(55<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1637 = PCMPGTQrm
- { 1638, 3, 1, 0, "PCMPGTQrr", 0, 0|5|(1<<6)|(13<<8)|(55<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1638 = PCMPGTQrr
- { 1639, 7, 1, 0, "PCMPGTWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1639 = PCMPGTWrm
- { 1640, 3, 1, 0, "PCMPGTWrr", 0, 0|5|(1<<6)|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1640 = PCMPGTWrr
- { 1641, 7, 0, 0, "PCMPISTRIArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1641 = PCMPISTRIArm
- { 1642, 3, 0, 0, "PCMPISTRIArr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1642 = PCMPISTRIArr
- { 1643, 7, 0, 0, "PCMPISTRICrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1643 = PCMPISTRICrm
- { 1644, 3, 0, 0, "PCMPISTRICrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1644 = PCMPISTRICrr
- { 1645, 7, 0, 0, "PCMPISTRIOrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1645 = PCMPISTRIOrm
- { 1646, 3, 0, 0, "PCMPISTRIOrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1646 = PCMPISTRIOrr
- { 1647, 7, 0, 0, "PCMPISTRISrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1647 = PCMPISTRISrm
- { 1648, 3, 0, 0, "PCMPISTRISrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1648 = PCMPISTRISrr
- { 1649, 7, 0, 0, "PCMPISTRIZrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1649 = PCMPISTRIZrm
- { 1650, 3, 0, 0, "PCMPISTRIZrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1650 = PCMPISTRIZrr
- { 1651, 7, 0, 0, "PCMPISTRIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1651 = PCMPISTRIrm
- { 1652, 3, 0, 0, "PCMPISTRIrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1652 = PCMPISTRIrr
- { 1653, 8, 1, 0, "PCMPISTRM128MEM", 0|(1<<TID::MayLoad)|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), NULL, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1653 = PCMPISTRM128MEM
- { 1654, 4, 1, 0, "PCMPISTRM128REG", 0|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), NULL, ImplicitList1, Barriers1, OperandInfo66 }, // Inst #1654 = PCMPISTRM128REG
- { 1655, 7, 0, 0, "PCMPISTRM128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(98<<24), NULL, ImplicitList43, Barriers1, OperandInfo183 }, // Inst #1655 = PCMPISTRM128rm
- { 1656, 3, 0, 0, "PCMPISTRM128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(98<<24), NULL, ImplicitList43, Barriers1, OperandInfo184 }, // Inst #1656 = PCMPISTRM128rr
- { 1657, 7, 0, 0, "PEXTRBmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(14<<8)|(1<<13)|(20<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1657 = PEXTRBmr
- { 1658, 3, 1, 0, "PEXTRBrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(20<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1658 = PEXTRBrr
- { 1659, 7, 0, 0, "PEXTRDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1659 = PEXTRDmr
- { 1660, 3, 1, 0, "PEXTRDrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1660 = PEXTRDrr
- { 1661, 7, 0, 0, "PEXTRQmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1661 = PEXTRQmr
- { 1662, 3, 1, 0, "PEXTRQrr", 0, 0|3|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo186 }, // Inst #1662 = PEXTRQrr
- { 1663, 7, 0, 0, "PEXTRWmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(14<<8)|(1<<13)|(21<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1663 = PEXTRWmr
- { 1664, 3, 1, 0, "PEXTRWri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(197<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1664 = PEXTRWri
- { 1665, 7, 1, 0, "PHADDDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1665 = PHADDDrm128
- { 1666, 7, 1, 0, "PHADDDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1666 = PHADDDrm64
- { 1667, 3, 1, 0, "PHADDDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1667 = PHADDDrr128
- { 1668, 3, 1, 0, "PHADDDrr64", 0, 0|5|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1668 = PHADDDrr64
- { 1669, 7, 1, 0, "PHADDSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1669 = PHADDSWrm128
- { 1670, 7, 1, 0, "PHADDSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1670 = PHADDSWrm64
- { 1671, 3, 1, 0, "PHADDSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1671 = PHADDSWrr128
- { 1672, 3, 1, 0, "PHADDSWrr64", 0, 0|5|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1672 = PHADDSWrr64
- { 1673, 7, 1, 0, "PHADDWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1673 = PHADDWrm128
- { 1674, 7, 1, 0, "PHADDWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1674 = PHADDWrm64
- { 1675, 3, 1, 0, "PHADDWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1675 = PHADDWrr128
- { 1676, 3, 1, 0, "PHADDWrr64", 0, 0|5|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1676 = PHADDWrr64
- { 1677, 6, 1, 0, "PHMINPOSUWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(65<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1677 = PHMINPOSUWrm128
- { 1678, 2, 1, 0, "PHMINPOSUWrr128", 0, 0|5|(1<<6)|(13<<8)|(65<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1678 = PHMINPOSUWrr128
- { 1679, 7, 1, 0, "PHSUBDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1679 = PHSUBDrm128
- { 1680, 7, 1, 0, "PHSUBDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1680 = PHSUBDrm64
- { 1681, 3, 1, 0, "PHSUBDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1681 = PHSUBDrr128
- { 1682, 3, 1, 0, "PHSUBDrr64", 0, 0|5|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1682 = PHSUBDrr64
- { 1683, 7, 1, 0, "PHSUBSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1683 = PHSUBSWrm128
- { 1684, 7, 1, 0, "PHSUBSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1684 = PHSUBSWrm64
- { 1685, 3, 1, 0, "PHSUBSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1685 = PHSUBSWrr128
- { 1686, 3, 1, 0, "PHSUBSWrr64", 0, 0|5|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1686 = PHSUBSWrr64
- { 1687, 7, 1, 0, "PHSUBWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1687 = PHSUBWrm128
- { 1688, 7, 1, 0, "PHSUBWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1688 = PHSUBWrm64
- { 1689, 3, 1, 0, "PHSUBWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1689 = PHSUBWrr128
- { 1690, 3, 1, 0, "PHSUBWrr64", 0, 0|5|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1690 = PHSUBWrr64
- { 1691, 8, 1, 0, "PINSRBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(32<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1691 = PINSRBrm
- { 1692, 4, 1, 0, "PINSRBrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(32<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1692 = PINSRBrr
- { 1693, 8, 1, 0, "PINSRDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1693 = PINSRDrm
- { 1694, 4, 1, 0, "PINSRDrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1694 = PINSRDrr
- { 1695, 8, 1, 0, "PINSRQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1695 = PINSRQrm
- { 1696, 4, 1, 0, "PINSRQrr", 0, 0|5|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #1696 = PINSRQrr
- { 1697, 8, 1, 0, "PINSRWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1697 = PINSRWrmi
- { 1698, 4, 1, 0, "PINSRWrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1698 = PINSRWrri
- { 1699, 7, 1, 0, "PMADDUBSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1699 = PMADDUBSWrm128
- { 1700, 7, 1, 0, "PMADDUBSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1700 = PMADDUBSWrm64
- { 1701, 3, 1, 0, "PMADDUBSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1701 = PMADDUBSWrr128
- { 1702, 3, 1, 0, "PMADDUBSWrr64", 0, 0|5|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1702 = PMADDUBSWrr64
- { 1703, 7, 1, 0, "PMADDWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1703 = PMADDWDrm
- { 1704, 3, 1, 0, "PMADDWDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1704 = PMADDWDrr
- { 1705, 7, 1, 0, "PMAXSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(60<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1705 = PMAXSBrm
- { 1706, 3, 1, 0, "PMAXSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(60<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1706 = PMAXSBrr
- { 1707, 7, 1, 0, "PMAXSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(61<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1707 = PMAXSDrm
- { 1708, 3, 1, 0, "PMAXSDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(61<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1708 = PMAXSDrr
- { 1709, 7, 1, 0, "PMAXSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1709 = PMAXSWrm
- { 1710, 3, 1, 0, "PMAXSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1710 = PMAXSWrr
- { 1711, 7, 1, 0, "PMAXUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1711 = PMAXUBrm
- { 1712, 3, 1, 0, "PMAXUBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1712 = PMAXUBrr
- { 1713, 7, 1, 0, "PMAXUDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(63<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1713 = PMAXUDrm
- { 1714, 3, 1, 0, "PMAXUDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(63<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1714 = PMAXUDrr
- { 1715, 7, 1, 0, "PMAXUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(62<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1715 = PMAXUWrm
- { 1716, 3, 1, 0, "PMAXUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(62<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1716 = PMAXUWrr
- { 1717, 7, 1, 0, "PMINSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(56<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1717 = PMINSBrm
- { 1718, 3, 1, 0, "PMINSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(56<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1718 = PMINSBrr
- { 1719, 7, 1, 0, "PMINSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(57<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1719 = PMINSDrm
- { 1720, 3, 1, 0, "PMINSDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(57<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1720 = PMINSDrr
- { 1721, 7, 1, 0, "PMINSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1721 = PMINSWrm
- { 1722, 3, 1, 0, "PMINSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1722 = PMINSWrr
- { 1723, 7, 1, 0, "PMINUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1723 = PMINUBrm
- { 1724, 3, 1, 0, "PMINUBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1724 = PMINUBrr
- { 1725, 7, 1, 0, "PMINUDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(59<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1725 = PMINUDrm
- { 1726, 3, 1, 0, "PMINUDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(59<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1726 = PMINUDrr
- { 1727, 7, 1, 0, "PMINUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(58<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1727 = PMINUWrm
- { 1728, 3, 1, 0, "PMINUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(58<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1728 = PMINUWrr
- { 1729, 2, 1, 0, "PMOVMSKBrr", 0, 0|5|(1<<6)|(1<<8)|(215<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1729 = PMOVMSKBrr
- { 1730, 6, 1, 0, "PMOVSXBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(33<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1730 = PMOVSXBDrm
- { 1731, 2, 1, 0, "PMOVSXBDrr", 0, 0|5|(1<<6)|(13<<8)|(33<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1731 = PMOVSXBDrr
- { 1732, 6, 1, 0, "PMOVSXBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(34<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1732 = PMOVSXBQrm
- { 1733, 2, 1, 0, "PMOVSXBQrr", 0, 0|5|(1<<6)|(13<<8)|(34<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1733 = PMOVSXBQrr
- { 1734, 6, 1, 0, "PMOVSXBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(32<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1734 = PMOVSXBWrm
- { 1735, 2, 1, 0, "PMOVSXBWrr", 0, 0|5|(1<<6)|(13<<8)|(32<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1735 = PMOVSXBWrr
- { 1736, 6, 1, 0, "PMOVSXDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(37<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1736 = PMOVSXDQrm
- { 1737, 2, 1, 0, "PMOVSXDQrr", 0, 0|5|(1<<6)|(13<<8)|(37<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1737 = PMOVSXDQrr
- { 1738, 6, 1, 0, "PMOVSXWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(35<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1738 = PMOVSXWDrm
- { 1739, 2, 1, 0, "PMOVSXWDrr", 0, 0|5|(1<<6)|(13<<8)|(35<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1739 = PMOVSXWDrr
- { 1740, 6, 1, 0, "PMOVSXWQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(36<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1740 = PMOVSXWQrm
- { 1741, 2, 1, 0, "PMOVSXWQrr", 0, 0|5|(1<<6)|(13<<8)|(36<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1741 = PMOVSXWQrr
- { 1742, 6, 1, 0, "PMOVZXBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(49<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1742 = PMOVZXBDrm
- { 1743, 2, 1, 0, "PMOVZXBDrr", 0, 0|5|(1<<6)|(13<<8)|(49<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1743 = PMOVZXBDrr
- { 1744, 6, 1, 0, "PMOVZXBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(50<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1744 = PMOVZXBQrm
- { 1745, 2, 1, 0, "PMOVZXBQrr", 0, 0|5|(1<<6)|(13<<8)|(50<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1745 = PMOVZXBQrr
- { 1746, 6, 1, 0, "PMOVZXBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(48<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1746 = PMOVZXBWrm
- { 1747, 2, 1, 0, "PMOVZXBWrr", 0, 0|5|(1<<6)|(13<<8)|(48<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1747 = PMOVZXBWrr
- { 1748, 6, 1, 0, "PMOVZXDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(53<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1748 = PMOVZXDQrm
- { 1749, 2, 1, 0, "PMOVZXDQrr", 0, 0|5|(1<<6)|(13<<8)|(53<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1749 = PMOVZXDQrr
- { 1750, 6, 1, 0, "PMOVZXWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(51<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1750 = PMOVZXWDrm
- { 1751, 2, 1, 0, "PMOVZXWDrr", 0, 0|5|(1<<6)|(13<<8)|(51<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1751 = PMOVZXWDrr
- { 1752, 6, 1, 0, "PMOVZXWQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(52<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1752 = PMOVZXWQrm
- { 1753, 2, 1, 0, "PMOVZXWQrr", 0, 0|5|(1<<6)|(13<<8)|(52<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1753 = PMOVZXWQrr
- { 1754, 7, 1, 0, "PMULDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(40<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1754 = PMULDQrm
- { 1755, 3, 1, 0, "PMULDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(40<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1755 = PMULDQrr
- { 1756, 7, 1, 0, "PMULHRSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1756 = PMULHRSWrm128
- { 1757, 7, 1, 0, "PMULHRSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1757 = PMULHRSWrm64
- { 1758, 3, 1, 0, "PMULHRSWrr128", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1758 = PMULHRSWrr128
- { 1759, 3, 1, 0, "PMULHRSWrr64", 0|(1<<TID::Commutable), 0|5|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1759 = PMULHRSWrr64
- { 1760, 7, 1, 0, "PMULHUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1760 = PMULHUWrm
- { 1761, 3, 1, 0, "PMULHUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1761 = PMULHUWrr
- { 1762, 7, 1, 0, "PMULHWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1762 = PMULHWrm
- { 1763, 3, 1, 0, "PMULHWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1763 = PMULHWrr
- { 1764, 7, 1, 0, "PMULLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1764 = PMULLDrm
- { 1765, 7, 1, 0, "PMULLDrm_int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1765 = PMULLDrm_int
- { 1766, 3, 1, 0, "PMULLDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1766 = PMULLDrr
- { 1767, 3, 1, 0, "PMULLDrr_int", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1767 = PMULLDrr_int
- { 1768, 7, 1, 0, "PMULLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1768 = PMULLWrm
- { 1769, 3, 1, 0, "PMULLWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1769 = PMULLWrr
- { 1770, 7, 1, 0, "PMULUDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1770 = PMULUDQrm
- { 1771, 3, 1, 0, "PMULUDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1771 = PMULUDQrr
- { 1772, 1, 1, 0, "POP16r", 0|(1<<TID::MayLoad), 0|2|(1<<6)|(88<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1772 = POP16r
- { 1773, 5, 1, 0, "POP16rmm", 0|(1<<TID::MayLoad), 0|24|(1<<6)|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1773 = POP16rmm
- { 1774, 1, 1, 0, "POP16rmr", 0|(1<<TID::MayLoad), 0|16|(1<<6)|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1774 = POP16rmr
- { 1775, 1, 1, 0, "POP32r", 0|(1<<TID::MayLoad), 0|2|(88<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1775 = POP32r
- { 1776, 5, 1, 0, "POP32rmm", 0|(1<<TID::MayLoad), 0|24|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1776 = POP32rmm
- { 1777, 1, 1, 0, "POP32rmr", 0|(1<<TID::MayLoad), 0|16|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1777 = POP32rmr
- { 1778, 1, 1, 0, "POP64r", 0|(1<<TID::MayLoad), 0|2|(88<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1778 = POP64r
- { 1779, 5, 1, 0, "POP64rmm", 0|(1<<TID::MayLoad), 0|24|(143<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo30 }, // Inst #1779 = POP64rmm
- { 1780, 1, 1, 0, "POP64rmr", 0|(1<<TID::MayLoad), 0|16|(143<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1780 = POP64rmr
- { 1781, 6, 1, 0, "POPCNT16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1781 = POPCNT16rm
- { 1782, 2, 1, 0, "POPCNT16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1782 = POPCNT16rr
- { 1783, 6, 1, 0, "POPCNT32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1783 = POPCNT32rm
- { 1784, 2, 1, 0, "POPCNT32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1784 = POPCNT32rr
- { 1785, 6, 1, 0, "POPCNT64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(1<<12)|(184<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1785 = POPCNT64rm
- { 1786, 2, 1, 0, "POPCNT64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(1<<12)|(184<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1786 = POPCNT64rr
- { 1787, 0, 0, 0, "POPF", 0|(1<<TID::MayLoad), 0|1|(1<<6)|(157<<24), ImplicitList2, ImplicitList3, Barriers1, 0 }, // Inst #1787 = POPF
- { 1788, 0, 0, 0, "POPFD", 0|(1<<TID::MayLoad), 0|1|(157<<24), ImplicitList2, ImplicitList3, Barriers1, 0 }, // Inst #1788 = POPFD
- { 1789, 0, 0, 0, "POPFQ", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(157<<24), ImplicitList4, ImplicitList5, Barriers1, 0 }, // Inst #1789 = POPFQ
- { 1790, 0, 0, 0, "POPFS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1790 = POPFS16
- { 1791, 0, 0, 0, "POPFS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1791 = POPFS32
- { 1792, 0, 0, 0, "POPFS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1792 = POPFS64
- { 1793, 0, 0, 0, "POPGS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1793 = POPGS16
- { 1794, 0, 0, 0, "POPGS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1794 = POPGS32
- { 1795, 0, 0, 0, "POPGS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1795 = POPGS64
- { 1796, 7, 1, 0, "PORrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1796 = PORrm
- { 1797, 3, 1, 0, "PORrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1797 = PORrr
- { 1798, 5, 0, 0, "PREFETCHNTA", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1798 = PREFETCHNTA
- { 1799, 5, 0, 0, "PREFETCHT0", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1799 = PREFETCHT0
- { 1800, 5, 0, 0, "PREFETCHT1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1800 = PREFETCHT1
- { 1801, 5, 0, 0, "PREFETCHT2", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1801 = PREFETCHT2
- { 1802, 7, 1, 0, "PSADBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1802 = PSADBWrm
- { 1803, 3, 1, 0, "PSADBWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1803 = PSADBWrr
- { 1804, 7, 1, 0, "PSHUFBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo24 }, // Inst #1804 = PSHUFBrm128
- { 1805, 7, 1, 0, "PSHUFBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo136 }, // Inst #1805 = PSHUFBrm64
- { 1806, 3, 1, 0, "PSHUFBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo25 }, // Inst #1806 = PSHUFBrr128
- { 1807, 3, 1, 0, "PSHUFBrr64", 0, 0|5|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo137 }, // Inst #1807 = PSHUFBrr64
- { 1808, 7, 1, 0, "PSHUFDmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo183 }, // Inst #1808 = PSHUFDmi
- { 1809, 3, 1, 0, "PSHUFDri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1809 = PSHUFDri
- { 1810, 7, 1, 0, "PSHUFHWmi", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo183 }, // Inst #1810 = PSHUFHWmi
- { 1811, 3, 1, 0, "PSHUFHWri", 0, 0|5|(12<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1811 = PSHUFHWri
- { 1812, 7, 1, 0, "PSHUFLWmi", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo183 }, // Inst #1812 = PSHUFLWmi
- { 1813, 3, 1, 0, "PSHUFLWri", 0, 0|5|(11<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1813 = PSHUFLWri
- { 1814, 7, 1, 0, "PSIGNBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1814 = PSIGNBrm128
- { 1815, 7, 1, 0, "PSIGNBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1815 = PSIGNBrm64
- { 1816, 3, 1, 0, "PSIGNBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1816 = PSIGNBrr128
- { 1817, 3, 1, 0, "PSIGNBrr64", 0, 0|5|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1817 = PSIGNBrr64
- { 1818, 7, 1, 0, "PSIGNDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1818 = PSIGNDrm128
- { 1819, 7, 1, 0, "PSIGNDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1819 = PSIGNDrm64
- { 1820, 3, 1, 0, "PSIGNDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1820 = PSIGNDrr128
- { 1821, 3, 1, 0, "PSIGNDrr64", 0, 0|5|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1821 = PSIGNDrr64
- { 1822, 7, 1, 0, "PSIGNWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1822 = PSIGNWrm128
- { 1823, 7, 1, 0, "PSIGNWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1823 = PSIGNWrm64
- { 1824, 3, 1, 0, "PSIGNWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1824 = PSIGNWrr128
- { 1825, 3, 1, 0, "PSIGNWrr64", 0, 0|5|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1825 = PSIGNWrr64
- { 1826, 3, 1, 0, "PSLLDQri", 0, 0|23|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1826 = PSLLDQri
- { 1827, 3, 1, 0, "PSLLDri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1827 = PSLLDri
- { 1828, 7, 1, 0, "PSLLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1828 = PSLLDrm
- { 1829, 3, 1, 0, "PSLLDrr", 0, 0|5|(1<<6)|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1829 = PSLLDrr
- { 1830, 3, 1, 0, "PSLLQri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1830 = PSLLQri
- { 1831, 7, 1, 0, "PSLLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1831 = PSLLQrm
- { 1832, 3, 1, 0, "PSLLQrr", 0, 0|5|(1<<6)|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1832 = PSLLQrr
- { 1833, 3, 1, 0, "PSLLWri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1833 = PSLLWri
- { 1834, 7, 1, 0, "PSLLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1834 = PSLLWrm
- { 1835, 3, 1, 0, "PSLLWrr", 0, 0|5|(1<<6)|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1835 = PSLLWrr
- { 1836, 3, 1, 0, "PSRADri", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1836 = PSRADri
- { 1837, 7, 1, 0, "PSRADrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1837 = PSRADrm
- { 1838, 3, 1, 0, "PSRADrr", 0, 0|5|(1<<6)|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1838 = PSRADrr
- { 1839, 3, 1, 0, "PSRAWri", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1839 = PSRAWri
- { 1840, 7, 1, 0, "PSRAWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1840 = PSRAWrm
- { 1841, 3, 1, 0, "PSRAWrr", 0, 0|5|(1<<6)|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1841 = PSRAWrr
- { 1842, 3, 1, 0, "PSRLDQri", 0, 0|19|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1842 = PSRLDQri
- { 1843, 3, 1, 0, "PSRLDri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1843 = PSRLDri
- { 1844, 7, 1, 0, "PSRLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1844 = PSRLDrm
- { 1845, 3, 1, 0, "PSRLDrr", 0, 0|5|(1<<6)|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1845 = PSRLDrr
- { 1846, 3, 1, 0, "PSRLQri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1846 = PSRLQri
- { 1847, 7, 1, 0, "PSRLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1847 = PSRLQrm
- { 1848, 3, 1, 0, "PSRLQrr", 0, 0|5|(1<<6)|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1848 = PSRLQrr
- { 1849, 3, 1, 0, "PSRLWri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1849 = PSRLWri
- { 1850, 7, 1, 0, "PSRLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1850 = PSRLWrm
- { 1851, 3, 1, 0, "PSRLWrr", 0, 0|5|(1<<6)|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1851 = PSRLWrr
- { 1852, 7, 1, 0, "PSUBBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1852 = PSUBBrm
- { 1853, 3, 1, 0, "PSUBBrr", 0, 0|5|(1<<6)|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1853 = PSUBBrr
- { 1854, 7, 1, 0, "PSUBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1854 = PSUBDrm
- { 1855, 3, 1, 0, "PSUBDrr", 0, 0|5|(1<<6)|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1855 = PSUBDrr
- { 1856, 7, 1, 0, "PSUBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1856 = PSUBQrm
- { 1857, 3, 1, 0, "PSUBQrr", 0, 0|5|(1<<6)|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1857 = PSUBQrr
- { 1858, 7, 1, 0, "PSUBSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1858 = PSUBSBrm
- { 1859, 3, 1, 0, "PSUBSBrr", 0, 0|5|(1<<6)|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1859 = PSUBSBrr
- { 1860, 7, 1, 0, "PSUBSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1860 = PSUBSWrm
- { 1861, 3, 1, 0, "PSUBSWrr", 0, 0|5|(1<<6)|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1861 = PSUBSWrr
- { 1862, 7, 1, 0, "PSUBUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1862 = PSUBUSBrm
- { 1863, 3, 1, 0, "PSUBUSBrr", 0, 0|5|(1<<6)|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1863 = PSUBUSBrr
- { 1864, 7, 1, 0, "PSUBUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1864 = PSUBUSWrm
- { 1865, 3, 1, 0, "PSUBUSWrr", 0, 0|5|(1<<6)|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1865 = PSUBUSWrr
- { 1866, 7, 1, 0, "PSUBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1866 = PSUBWrm
- { 1867, 3, 1, 0, "PSUBWrr", 0, 0|5|(1<<6)|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1867 = PSUBWrr
- { 1868, 6, 0, 0, "PTESTrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(23<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #1868 = PTESTrm
- { 1869, 2, 0, 0, "PTESTrr", 0, 0|5|(1<<6)|(13<<8)|(23<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #1869 = PTESTrr
- { 1870, 7, 1, 0, "PUNPCKHBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1870 = PUNPCKHBWrm
- { 1871, 3, 1, 0, "PUNPCKHBWrr", 0, 0|5|(1<<6)|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1871 = PUNPCKHBWrr
- { 1872, 7, 1, 0, "PUNPCKHDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1872 = PUNPCKHDQrm
- { 1873, 3, 1, 0, "PUNPCKHDQrr", 0, 0|5|(1<<6)|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1873 = PUNPCKHDQrr
- { 1874, 7, 1, 0, "PUNPCKHQDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(109<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1874 = PUNPCKHQDQrm
- { 1875, 3, 1, 0, "PUNPCKHQDQrr", 0, 0|5|(1<<6)|(1<<8)|(109<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1875 = PUNPCKHQDQrr
- { 1876, 7, 1, 0, "PUNPCKHWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1876 = PUNPCKHWDrm
- { 1877, 3, 1, 0, "PUNPCKHWDrr", 0, 0|5|(1<<6)|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1877 = PUNPCKHWDrr
- { 1878, 7, 1, 0, "PUNPCKLBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1878 = PUNPCKLBWrm
- { 1879, 3, 1, 0, "PUNPCKLBWrr", 0, 0|5|(1<<6)|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1879 = PUNPCKLBWrr
- { 1880, 7, 1, 0, "PUNPCKLDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1880 = PUNPCKLDQrm
- { 1881, 3, 1, 0, "PUNPCKLDQrr", 0, 0|5|(1<<6)|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1881 = PUNPCKLDQrr
- { 1882, 7, 1, 0, "PUNPCKLQDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(108<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1882 = PUNPCKLQDQrm
- { 1883, 3, 1, 0, "PUNPCKLQDQrr", 0, 0|5|(1<<6)|(1<<8)|(108<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1883 = PUNPCKLQDQrr
- { 1884, 7, 1, 0, "PUNPCKLWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1884 = PUNPCKLWDrm
- { 1885, 3, 1, 0, "PUNPCKLWDrr", 0, 0|5|(1<<6)|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1885 = PUNPCKLWDrr
- { 1886, 1, 0, 0, "PUSH16r", 0|(1<<TID::MayStore), 0|2|(1<<6)|(80<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1886 = PUSH16r
- { 1887, 5, 0, 0, "PUSH16rmm", 0|(1<<TID::MayStore), 0|30|(1<<6)|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1887 = PUSH16rmm
- { 1888, 1, 0, 0, "PUSH16rmr", 0|(1<<TID::MayStore), 0|22|(1<<6)|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1888 = PUSH16rmr
- { 1889, 1, 0, 0, "PUSH32i16", 0|(1<<TID::MayStore), 0|1|(3<<13)|(104<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1889 = PUSH32i16
- { 1890, 1, 0, 0, "PUSH32i32", 0|(1<<TID::MayStore), 0|1|(4<<13)|(104<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1890 = PUSH32i32
- { 1891, 1, 0, 0, "PUSH32i8", 0|(1<<TID::MayStore), 0|1|(1<<13)|(106<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1891 = PUSH32i8
- { 1892, 1, 0, 0, "PUSH32r", 0|(1<<TID::MayStore), 0|2|(80<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1892 = PUSH32r
- { 1893, 5, 0, 0, "PUSH32rmm", 0|(1<<TID::MayStore), 0|30|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1893 = PUSH32rmm
- { 1894, 1, 0, 0, "PUSH32rmr", 0|(1<<TID::MayStore), 0|22|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1894 = PUSH32rmr
- { 1895, 1, 0, 0, "PUSH64i16", 0|(1<<TID::MayStore), 0|1|(3<<13)|(104<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1895 = PUSH64i16
- { 1896, 1, 0, 0, "PUSH64i32", 0|(1<<TID::MayStore), 0|1|(4<<13)|(104<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1896 = PUSH64i32
- { 1897, 1, 0, 0, "PUSH64i8", 0|(1<<TID::MayStore), 0|1|(1<<13)|(106<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1897 = PUSH64i8
- { 1898, 1, 0, 0, "PUSH64r", 0|(1<<TID::MayStore), 0|2|(80<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1898 = PUSH64r
- { 1899, 5, 0, 0, "PUSH64rmm", 0|(1<<TID::MayStore), 0|30|(255<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo30 }, // Inst #1899 = PUSH64rmm
- { 1900, 1, 0, 0, "PUSH64rmr", 0|(1<<TID::MayStore), 0|22|(255<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1900 = PUSH64rmr
- { 1901, 0, 0, 0, "PUSHF", 0|(1<<TID::MayStore), 0|1|(1<<6)|(156<<24), ImplicitList3, ImplicitList2, NULL, 0 }, // Inst #1901 = PUSHF
- { 1902, 0, 0, 0, "PUSHFD", 0|(1<<TID::MayStore), 0|1|(156<<24), ImplicitList3, ImplicitList2, NULL, 0 }, // Inst #1902 = PUSHFD
- { 1903, 0, 0, 0, "PUSHFQ64", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(156<<24), ImplicitList5, ImplicitList4, NULL, 0 }, // Inst #1903 = PUSHFQ64
- { 1904, 0, 0, 0, "PUSHFS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1904 = PUSHFS16
- { 1905, 0, 0, 0, "PUSHFS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1905 = PUSHFS32
- { 1906, 0, 0, 0, "PUSHFS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1906 = PUSHFS64
- { 1907, 0, 0, 0, "PUSHGS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1907 = PUSHGS16
- { 1908, 0, 0, 0, "PUSHGS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1908 = PUSHGS32
- { 1909, 0, 0, 0, "PUSHGS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1909 = PUSHGS64
- { 1910, 7, 1, 0, "PXORrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1910 = PXORrm
- { 1911, 3, 1, 0, "PXORrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1911 = PXORrr
- { 1912, 5, 0, 0, "RCL16m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1912 = RCL16m1
- { 1913, 5, 0, 0, "RCL16mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1913 = RCL16mCL
- { 1914, 6, 0, 0, "RCL16mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1914 = RCL16mi
- { 1915, 2, 1, 0, "RCL16r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1915 = RCL16r1
- { 1916, 2, 1, 0, "RCL16rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1916 = RCL16rCL
- { 1917, 3, 1, 0, "RCL16ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1917 = RCL16ri
- { 1918, 5, 0, 0, "RCL32m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1918 = RCL32m1
- { 1919, 5, 0, 0, "RCL32mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1919 = RCL32mCL
- { 1920, 6, 0, 0, "RCL32mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1920 = RCL32mi
- { 1921, 2, 1, 0, "RCL32r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1921 = RCL32r1
- { 1922, 2, 1, 0, "RCL32rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1922 = RCL32rCL
- { 1923, 3, 1, 0, "RCL32ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1923 = RCL32ri
- { 1924, 5, 0, 0, "RCL64m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1924 = RCL64m1
- { 1925, 5, 0, 0, "RCL64mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1925 = RCL64mCL
- { 1926, 6, 0, 0, "RCL64mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1926 = RCL64mi
- { 1927, 2, 1, 0, "RCL64r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1927 = RCL64r1
- { 1928, 2, 1, 0, "RCL64rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1928 = RCL64rCL
- { 1929, 3, 1, 0, "RCL64ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1929 = RCL64ri
- { 1930, 5, 0, 0, "RCL8m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1930 = RCL8m1
- { 1931, 5, 0, 0, "RCL8mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1931 = RCL8mCL
- { 1932, 6, 0, 0, "RCL8mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1932 = RCL8mi
- { 1933, 2, 1, 0, "RCL8r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1933 = RCL8r1
- { 1934, 2, 1, 0, "RCL8rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1934 = RCL8rCL
- { 1935, 3, 1, 0, "RCL8ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1935 = RCL8ri
- { 1936, 6, 1, 0, "RCPPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1936 = RCPPSm
- { 1937, 6, 1, 0, "RCPPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1937 = RCPPSm_Int
- { 1938, 2, 1, 0, "RCPPSr", 0, 0|5|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1938 = RCPPSr
- { 1939, 2, 1, 0, "RCPPSr_Int", 0, 0|5|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1939 = RCPPSr_Int
- { 1940, 6, 1, 0, "RCPSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1940 = RCPSSm
- { 1941, 6, 1, 0, "RCPSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1941 = RCPSSm_Int
- { 1942, 2, 1, 0, "RCPSSr", 0, 0|5|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #1942 = RCPSSr
- { 1943, 2, 1, 0, "RCPSSr_Int", 0, 0|5|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1943 = RCPSSr_Int
- { 1944, 5, 0, 0, "RCR16m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1944 = RCR16m1
- { 1945, 5, 0, 0, "RCR16mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1945 = RCR16mCL
- { 1946, 6, 0, 0, "RCR16mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1946 = RCR16mi
- { 1947, 2, 1, 0, "RCR16r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1947 = RCR16r1
- { 1948, 2, 1, 0, "RCR16rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1948 = RCR16rCL
- { 1949, 3, 1, 0, "RCR16ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1949 = RCR16ri
- { 1950, 5, 0, 0, "RCR32m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1950 = RCR32m1
- { 1951, 5, 0, 0, "RCR32mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1951 = RCR32mCL
- { 1952, 6, 0, 0, "RCR32mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1952 = RCR32mi
- { 1953, 2, 1, 0, "RCR32r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1953 = RCR32r1
- { 1954, 2, 1, 0, "RCR32rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1954 = RCR32rCL
- { 1955, 3, 1, 0, "RCR32ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1955 = RCR32ri
- { 1956, 5, 0, 0, "RCR64m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1956 = RCR64m1
- { 1957, 5, 0, 0, "RCR64mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1957 = RCR64mCL
- { 1958, 6, 0, 0, "RCR64mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1958 = RCR64mi
- { 1959, 2, 1, 0, "RCR64r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1959 = RCR64r1
- { 1960, 2, 1, 0, "RCR64rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1960 = RCR64rCL
- { 1961, 3, 1, 0, "RCR64ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1961 = RCR64ri
- { 1962, 5, 0, 0, "RCR8m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1962 = RCR8m1
- { 1963, 5, 0, 0, "RCR8mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1963 = RCR8mCL
- { 1964, 6, 0, 0, "RCR8mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1964 = RCR8mi
- { 1965, 2, 1, 0, "RCR8r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1965 = RCR8r1
- { 1966, 2, 1, 0, "RCR8rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1966 = RCR8rCL
- { 1967, 3, 1, 0, "RCR8ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1967 = RCR8ri
- { 1968, 0, 0, 0, "RDMSR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(50<<24), NULL, NULL, NULL, 0 }, // Inst #1968 = RDMSR
- { 1969, 0, 0, 0, "RDPMC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(51<<24), NULL, NULL, NULL, 0 }, // Inst #1969 = RDPMC
- { 1970, 0, 0, 0, "RDTSC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(49<<24), NULL, ImplicitList19, NULL, 0 }, // Inst #1970 = RDTSC
- { 1971, 0, 0, 0, "RDTSCP", 0|(1<<TID::UnmodeledSideEffects), 0|42|(1<<8)|(1<<24), NULL, ImplicitList45, NULL, 0 }, // Inst #1971 = RDTSCP
- { 1972, 0, 0, 0, "REPNE_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(242<<24), ImplicitList42, ImplicitList27, NULL, 0 }, // Inst #1972 = REPNE_PREFIX
- { 1973, 0, 0, 0, "REP_MOVSB", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(164<<24), ImplicitList46, ImplicitList46, NULL, 0 }, // Inst #1973 = REP_MOVSB
- { 1974, 0, 0, 0, "REP_MOVSD", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(165<<24), ImplicitList46, ImplicitList46, NULL, 0 }, // Inst #1974 = REP_MOVSD
- { 1975, 0, 0, 0, "REP_MOVSQ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(1<<12)|(165<<24), ImplicitList47, ImplicitList47, NULL, 0 }, // Inst #1975 = REP_MOVSQ
- { 1976, 0, 0, 0, "REP_MOVSW", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(1<<6)|(2<<8)|(165<<24), ImplicitList46, ImplicitList46, NULL, 0 }, // Inst #1976 = REP_MOVSW
- { 1977, 0, 0, 0, "REP_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(243<<24), ImplicitList42, ImplicitList27, NULL, 0 }, // Inst #1977 = REP_PREFIX
- { 1978, 0, 0, 0, "REP_STOSB", 0|(1<<TID::MayStore), 0|1|(2<<8)|(170<<24), ImplicitList48, ImplicitList49, NULL, 0 }, // Inst #1978 = REP_STOSB
- { 1979, 0, 0, 0, "REP_STOSD", 0|(1<<TID::MayStore), 0|1|(2<<8)|(171<<24), ImplicitList50, ImplicitList49, NULL, 0 }, // Inst #1979 = REP_STOSD
- { 1980, 0, 0, 0, "REP_STOSQ", 0|(1<<TID::MayStore), 0|1|(2<<8)|(1<<12)|(171<<24), ImplicitList51, ImplicitList52, NULL, 0 }, // Inst #1980 = REP_STOSQ
- { 1981, 0, 0, 0, "REP_STOSW", 0|(1<<TID::MayStore), 0|1|(1<<6)|(2<<8)|(171<<24), ImplicitList53, ImplicitList49, NULL, 0 }, // Inst #1981 = REP_STOSW
- { 1982, 0, 0, 0, "RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::Variadic), 0|1|(7<<16)|(195<<24), NULL, NULL, NULL, 0 }, // Inst #1982 = RET
- { 1983, 1, 0, 0, "RETI", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::Variadic), 0|1|(3<<13)|(7<<16)|(194<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1983 = RETI
- { 1984, 5, 0, 0, "ROL16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1984 = ROL16m1
- { 1985, 5, 0, 0, "ROL16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1985 = ROL16mCL
- { 1986, 6, 0, 0, "ROL16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1986 = ROL16mi
- { 1987, 2, 1, 0, "ROL16r1", 0, 0|16|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1987 = ROL16r1
- { 1988, 2, 1, 0, "ROL16rCL", 0, 0|16|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1988 = ROL16rCL
- { 1989, 3, 1, 0, "ROL16ri", 0, 0|16|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1989 = ROL16ri
- { 1990, 5, 0, 0, "ROL32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1990 = ROL32m1
- { 1991, 5, 0, 0, "ROL32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1991 = ROL32mCL
- { 1992, 6, 0, 0, "ROL32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1992 = ROL32mi
- { 1993, 2, 1, 0, "ROL32r1", 0, 0|16|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1993 = ROL32r1
- { 1994, 2, 1, 0, "ROL32rCL", 0, 0|16|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1994 = ROL32rCL
- { 1995, 3, 1, 0, "ROL32ri", 0, 0|16|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1995 = ROL32ri
- { 1996, 5, 0, 0, "ROL64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1996 = ROL64m1
- { 1997, 5, 0, 0, "ROL64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1997 = ROL64mCL
- { 1998, 6, 0, 0, "ROL64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1998 = ROL64mi
- { 1999, 2, 1, 0, "ROL64r1", 0, 0|16|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1999 = ROL64r1
- { 2000, 2, 1, 0, "ROL64rCL", 0, 0|16|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2000 = ROL64rCL
- { 2001, 3, 1, 0, "ROL64ri", 0, 0|16|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2001 = ROL64ri
- { 2002, 5, 0, 0, "ROL8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2002 = ROL8m1
- { 2003, 5, 0, 0, "ROL8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2003 = ROL8mCL
- { 2004, 6, 0, 0, "ROL8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2004 = ROL8mi
- { 2005, 2, 1, 0, "ROL8r1", 0, 0|16|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2005 = ROL8r1
- { 2006, 2, 1, 0, "ROL8rCL", 0, 0|16|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2006 = ROL8rCL
- { 2007, 3, 1, 0, "ROL8ri", 0, 0|16|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2007 = ROL8ri
- { 2008, 5, 0, 0, "ROR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2008 = ROR16m1
- { 2009, 5, 0, 0, "ROR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2009 = ROR16mCL
- { 2010, 6, 0, 0, "ROR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2010 = ROR16mi
- { 2011, 2, 1, 0, "ROR16r1", 0, 0|17|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2011 = ROR16r1
- { 2012, 2, 1, 0, "ROR16rCL", 0, 0|17|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2012 = ROR16rCL
- { 2013, 3, 1, 0, "ROR16ri", 0, 0|17|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2013 = ROR16ri
- { 2014, 5, 0, 0, "ROR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2014 = ROR32m1
- { 2015, 5, 0, 0, "ROR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2015 = ROR32mCL
- { 2016, 6, 0, 0, "ROR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2016 = ROR32mi
- { 2017, 2, 1, 0, "ROR32r1", 0, 0|17|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2017 = ROR32r1
- { 2018, 2, 1, 0, "ROR32rCL", 0, 0|17|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2018 = ROR32rCL
- { 2019, 3, 1, 0, "ROR32ri", 0, 0|17|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2019 = ROR32ri
- { 2020, 5, 0, 0, "ROR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2020 = ROR64m1
- { 2021, 5, 0, 0, "ROR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2021 = ROR64mCL
- { 2022, 6, 0, 0, "ROR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2022 = ROR64mi
- { 2023, 2, 1, 0, "ROR64r1", 0, 0|17|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2023 = ROR64r1
- { 2024, 2, 1, 0, "ROR64rCL", 0, 0|17|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2024 = ROR64rCL
- { 2025, 3, 1, 0, "ROR64ri", 0, 0|17|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2025 = ROR64ri
- { 2026, 5, 0, 0, "ROR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2026 = ROR8m1
- { 2027, 5, 0, 0, "ROR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2027 = ROR8mCL
- { 2028, 6, 0, 0, "ROR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2028 = ROR8mi
- { 2029, 2, 1, 0, "ROR8r1", 0, 0|17|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2029 = ROR8r1
- { 2030, 2, 1, 0, "ROR8rCL", 0, 0|17|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2030 = ROR8rCL
- { 2031, 3, 1, 0, "ROR8ri", 0, 0|17|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2031 = ROR8ri
- { 2032, 7, 1, 0, "ROUNDPDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo183 }, // Inst #2032 = ROUNDPDm_Int
- { 2033, 3, 1, 0, "ROUNDPDr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #2033 = ROUNDPDr_Int
- { 2034, 7, 1, 0, "ROUNDPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo183 }, // Inst #2034 = ROUNDPSm_Int
- { 2035, 3, 1, 0, "ROUNDPSr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #2035 = ROUNDPSr_Int
- { 2036, 8, 1, 0, "ROUNDSDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2036 = ROUNDSDm_Int
- { 2037, 4, 1, 0, "ROUNDSDr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2037 = ROUNDSDr_Int
- { 2038, 8, 1, 0, "ROUNDSSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2038 = ROUNDSSm_Int
- { 2039, 4, 1, 0, "ROUNDSSr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2039 = ROUNDSSr_Int
- { 2040, 0, 0, 0, "RSM", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(170<<24), NULL, NULL, NULL, 0 }, // Inst #2040 = RSM
- { 2041, 6, 1, 0, "RSQRTPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2041 = RSQRTPSm
- { 2042, 6, 1, 0, "RSQRTPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2042 = RSQRTPSm_Int
- { 2043, 2, 1, 0, "RSQRTPSr", 0, 0|5|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2043 = RSQRTPSr
- { 2044, 2, 1, 0, "RSQRTPSr_Int", 0, 0|5|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2044 = RSQRTPSr_Int
- { 2045, 6, 1, 0, "RSQRTSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #2045 = RSQRTSSm
- { 2046, 6, 1, 0, "RSQRTSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2046 = RSQRTSSm_Int
- { 2047, 2, 1, 0, "RSQRTSSr", 0, 0|5|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #2047 = RSQRTSSr
- { 2048, 2, 1, 0, "RSQRTSSr_Int", 0, 0|5|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2048 = RSQRTSSr_Int
- { 2049, 0, 0, 0, "SAHF", 0, 0|1|(158<<24), ImplicitList28, ImplicitList1, Barriers1, 0 }, // Inst #2049 = SAHF
- { 2050, 5, 0, 0, "SAR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2050 = SAR16m1
- { 2051, 5, 0, 0, "SAR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2051 = SAR16mCL
- { 2052, 6, 0, 0, "SAR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2052 = SAR16mi
- { 2053, 2, 1, 0, "SAR16r1", 0, 0|23|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2053 = SAR16r1
- { 2054, 2, 1, 0, "SAR16rCL", 0, 0|23|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2054 = SAR16rCL
- { 2055, 3, 1, 0, "SAR16ri", 0, 0|23|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2055 = SAR16ri
- { 2056, 5, 0, 0, "SAR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2056 = SAR32m1
- { 2057, 5, 0, 0, "SAR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2057 = SAR32mCL
- { 2058, 6, 0, 0, "SAR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2058 = SAR32mi
- { 2059, 2, 1, 0, "SAR32r1", 0, 0|23|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2059 = SAR32r1
- { 2060, 2, 1, 0, "SAR32rCL", 0, 0|23|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2060 = SAR32rCL
- { 2061, 3, 1, 0, "SAR32ri", 0, 0|23|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2061 = SAR32ri
- { 2062, 5, 0, 0, "SAR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2062 = SAR64m1
- { 2063, 5, 0, 0, "SAR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2063 = SAR64mCL
- { 2064, 6, 0, 0, "SAR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2064 = SAR64mi
- { 2065, 2, 1, 0, "SAR64r1", 0, 0|23|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2065 = SAR64r1
- { 2066, 2, 1, 0, "SAR64rCL", 0, 0|23|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2066 = SAR64rCL
- { 2067, 3, 1, 0, "SAR64ri", 0, 0|23|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2067 = SAR64ri
- { 2068, 5, 0, 0, "SAR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2068 = SAR8m1
- { 2069, 5, 0, 0, "SAR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2069 = SAR8mCL
- { 2070, 6, 0, 0, "SAR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2070 = SAR8mi
- { 2071, 2, 1, 0, "SAR8r1", 0, 0|23|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2071 = SAR8r1
- { 2072, 2, 1, 0, "SAR8rCL", 0, 0|23|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2072 = SAR8rCL
- { 2073, 3, 1, 0, "SAR8ri", 0, 0|23|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2073 = SAR8ri
- { 2074, 1, 0, 0, "SBB16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2074 = SBB16i16
- { 2075, 6, 0, 0, "SBB16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2075 = SBB16mi
- { 2076, 6, 0, 0, "SBB16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2076 = SBB16mi8
- { 2077, 6, 0, 0, "SBB16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2077 = SBB16mr
- { 2078, 3, 1, 0, "SBB16ri", 0, 0|19|(1<<6)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2078 = SBB16ri
- { 2079, 3, 1, 0, "SBB16ri8", 0, 0|19|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2079 = SBB16ri8
- { 2080, 7, 1, 0, "SBB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2080 = SBB16rm
- { 2081, 3, 1, 0, "SBB16rr", 0, 0|3|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2081 = SBB16rr
- { 2082, 3, 1, 0, "SBB16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2082 = SBB16rr_REV
- { 2083, 1, 0, 0, "SBB32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2083 = SBB32i32
- { 2084, 6, 0, 0, "SBB32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2084 = SBB32mi
- { 2085, 6, 0, 0, "SBB32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2085 = SBB32mi8
- { 2086, 6, 0, 0, "SBB32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2086 = SBB32mr
- { 2087, 3, 1, 0, "SBB32ri", 0, 0|19|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2087 = SBB32ri
- { 2088, 3, 1, 0, "SBB32ri8", 0, 0|19|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2088 = SBB32ri8
- { 2089, 7, 1, 0, "SBB32rm", 0|(1<<TID::MayLoad), 0|6|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2089 = SBB32rm
- { 2090, 3, 1, 0, "SBB32rr", 0, 0|3|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2090 = SBB32rr
- { 2091, 3, 1, 0, "SBB32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2091 = SBB32rr_REV
- { 2092, 1, 0, 0, "SBB64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2092 = SBB64i32
- { 2093, 6, 0, 0, "SBB64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2093 = SBB64mi32
- { 2094, 6, 0, 0, "SBB64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2094 = SBB64mi8
- { 2095, 6, 0, 0, "SBB64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2095 = SBB64mr
- { 2096, 3, 1, 0, "SBB64ri32", 0, 0|19|(1<<12)|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2096 = SBB64ri32
- { 2097, 3, 1, 0, "SBB64ri8", 0, 0|19|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2097 = SBB64ri8
- { 2098, 7, 1, 0, "SBB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2098 = SBB64rm
- { 2099, 3, 1, 0, "SBB64rr", 0, 0|3|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2099 = SBB64rr
- { 2100, 3, 1, 0, "SBB64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2100 = SBB64rr_REV
- { 2101, 1, 0, 0, "SBB8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(28<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2101 = SBB8i8
- { 2102, 6, 0, 0, "SBB8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2102 = SBB8mi
- { 2103, 6, 0, 0, "SBB8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2103 = SBB8mr
- { 2104, 3, 1, 0, "SBB8ri", 0, 0|19|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2104 = SBB8ri
- { 2105, 7, 1, 0, "SBB8rm", 0|(1<<TID::MayLoad), 0|6|(26<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2105 = SBB8rm
- { 2106, 3, 1, 0, "SBB8rr", 0, 0|3|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2106 = SBB8rr
- { 2107, 3, 1, 0, "SBB8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(26<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2107 = SBB8rr_REV
- { 2108, 0, 0, 0, "SCAS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2108 = SCAS16
- { 2109, 0, 0, 0, "SCAS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2109 = SCAS32
- { 2110, 0, 0, 0, "SCAS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2110 = SCAS64
- { 2111, 0, 0, 0, "SCAS8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(174<<24), NULL, NULL, NULL, 0 }, // Inst #2111 = SCAS8
- { 2112, 5, 0, 0, "SETAEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(147<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2112 = SETAEm
- { 2113, 1, 1, 0, "SETAEr", 0, 0|16|(1<<8)|(147<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2113 = SETAEr
- { 2114, 5, 0, 0, "SETAm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(151<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2114 = SETAm
- { 2115, 1, 1, 0, "SETAr", 0, 0|16|(1<<8)|(151<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2115 = SETAr
- { 2116, 5, 0, 0, "SETBEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(150<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2116 = SETBEm
- { 2117, 1, 1, 0, "SETBEr", 0, 0|16|(1<<8)|(150<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2117 = SETBEr
- { 2118, 1, 1, 0, "SETB_C16r", 0, 0|32|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo93 }, // Inst #2118 = SETB_C16r
- { 2119, 1, 1, 0, "SETB_C32r", 0, 0|32|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo57 }, // Inst #2119 = SETB_C32r
- { 2120, 1, 1, 0, "SETB_C64r", 0, 0|32|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo58 }, // Inst #2120 = SETB_C64r
- { 2121, 1, 1, 0, "SETB_C8r", 0, 0|32|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo94 }, // Inst #2121 = SETB_C8r
- { 2122, 5, 0, 0, "SETBm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(146<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2122 = SETBm
- { 2123, 1, 1, 0, "SETBr", 0, 0|16|(1<<8)|(146<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2123 = SETBr
- { 2124, 5, 0, 0, "SETEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(148<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2124 = SETEm
- { 2125, 1, 1, 0, "SETEr", 0, 0|16|(1<<8)|(148<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2125 = SETEr
- { 2126, 5, 0, 0, "SETGEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(157<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2126 = SETGEm
- { 2127, 1, 1, 0, "SETGEr", 0, 0|16|(1<<8)|(157<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2127 = SETGEr
- { 2128, 5, 0, 0, "SETGm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(159<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2128 = SETGm
- { 2129, 1, 1, 0, "SETGr", 0, 0|16|(1<<8)|(159<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2129 = SETGr
- { 2130, 5, 0, 0, "SETLEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(158<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2130 = SETLEm
- { 2131, 1, 1, 0, "SETLEr", 0, 0|16|(1<<8)|(158<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2131 = SETLEr
- { 2132, 5, 0, 0, "SETLm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(156<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2132 = SETLm
- { 2133, 1, 1, 0, "SETLr", 0, 0|16|(1<<8)|(156<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2133 = SETLr
- { 2134, 5, 0, 0, "SETNEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(149<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2134 = SETNEm
- { 2135, 1, 1, 0, "SETNEr", 0, 0|16|(1<<8)|(149<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2135 = SETNEr
- { 2136, 5, 0, 0, "SETNOm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(145<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2136 = SETNOm
- { 2137, 1, 1, 0, "SETNOr", 0, 0|16|(1<<8)|(145<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2137 = SETNOr
- { 2138, 5, 0, 0, "SETNPm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(155<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2138 = SETNPm
- { 2139, 1, 1, 0, "SETNPr", 0, 0|16|(1<<8)|(155<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2139 = SETNPr
- { 2140, 5, 0, 0, "SETNSm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(153<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2140 = SETNSm
- { 2141, 1, 1, 0, "SETNSr", 0, 0|16|(1<<8)|(153<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2141 = SETNSr
- { 2142, 5, 0, 0, "SETOm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(144<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2142 = SETOm
- { 2143, 1, 1, 0, "SETOr", 0, 0|16|(1<<8)|(144<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2143 = SETOr
- { 2144, 5, 0, 0, "SETPm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(154<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2144 = SETPm
- { 2145, 1, 1, 0, "SETPr", 0, 0|16|(1<<8)|(154<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2145 = SETPr
- { 2146, 5, 0, 0, "SETSm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(152<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2146 = SETSm
- { 2147, 1, 1, 0, "SETSr", 0, 0|16|(1<<8)|(152<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2147 = SETSr
- { 2148, 0, 0, 0, "SFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|23|(1<<8)|(174<<24), NULL, NULL, NULL, 0 }, // Inst #2148 = SFENCE
- { 2149, 5, 1, 0, "SGDTm", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2149 = SGDTm
- { 2150, 5, 0, 0, "SHL16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2150 = SHL16m1
- { 2151, 5, 0, 0, "SHL16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2151 = SHL16mCL
- { 2152, 6, 0, 0, "SHL16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2152 = SHL16mi
- { 2153, 2, 1, 0, "SHL16r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2153 = SHL16r1
- { 2154, 2, 1, 0, "SHL16rCL", 0, 0|20|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2154 = SHL16rCL
- { 2155, 3, 1, 0, "SHL16ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2155 = SHL16ri
- { 2156, 5, 0, 0, "SHL32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2156 = SHL32m1
- { 2157, 5, 0, 0, "SHL32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2157 = SHL32mCL
- { 2158, 6, 0, 0, "SHL32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2158 = SHL32mi
- { 2159, 2, 1, 0, "SHL32r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2159 = SHL32r1
- { 2160, 2, 1, 0, "SHL32rCL", 0, 0|20|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2160 = SHL32rCL
- { 2161, 3, 1, 0, "SHL32ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2161 = SHL32ri
- { 2162, 5, 0, 0, "SHL64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2162 = SHL64m1
- { 2163, 5, 0, 0, "SHL64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2163 = SHL64mCL
- { 2164, 6, 0, 0, "SHL64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2164 = SHL64mi
- { 2165, 2, 1, 0, "SHL64r1", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2165 = SHL64r1
- { 2166, 2, 1, 0, "SHL64rCL", 0, 0|20|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2166 = SHL64rCL
- { 2167, 3, 1, 0, "SHL64ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2167 = SHL64ri
- { 2168, 5, 0, 0, "SHL8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2168 = SHL8m1
- { 2169, 5, 0, 0, "SHL8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2169 = SHL8mCL
- { 2170, 6, 0, 0, "SHL8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2170 = SHL8mi
- { 2171, 2, 1, 0, "SHL8r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2171 = SHL8r1
- { 2172, 2, 1, 0, "SHL8rCL", 0, 0|20|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2172 = SHL8rCL
- { 2173, 3, 1, 0, "SHL8ri", 0, 0|20|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2173 = SHL8ri
- { 2174, 6, 0, 0, "SHLD16mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2174 = SHLD16mrCL
- { 2175, 7, 0, 0, "SHLD16mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo190 }, // Inst #2175 = SHLD16mri8
- { 2176, 3, 1, 0, "SHLD16rrCL", 0, 0|3|(1<<6)|(1<<8)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2176 = SHLD16rrCL
- { 2177, 4, 1, 0, "SHLD16rri8", 0|(1<<TID::Commutable), 0|3|(1<<6)|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo191 }, // Inst #2177 = SHLD16rri8
- { 2178, 6, 0, 0, "SHLD32mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2178 = SHLD32mrCL
- { 2179, 7, 0, 0, "SHLD32mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo192 }, // Inst #2179 = SHLD32mri8
- { 2180, 3, 1, 0, "SHLD32rrCL", 0, 0|3|(1<<8)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2180 = SHLD32rrCL
- { 2181, 4, 1, 0, "SHLD32rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo193 }, // Inst #2181 = SHLD32rri8
- { 2182, 6, 0, 0, "SHLD64mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2182 = SHLD64mrCL
- { 2183, 7, 0, 0, "SHLD64mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #2183 = SHLD64mri8
- { 2184, 3, 1, 0, "SHLD64rrCL", 0, 0|3|(1<<8)|(1<<12)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2184 = SHLD64rrCL
- { 2185, 4, 1, 0, "SHLD64rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<12)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #2185 = SHLD64rri8
- { 2186, 5, 0, 0, "SHR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2186 = SHR16m1
- { 2187, 5, 0, 0, "SHR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2187 = SHR16mCL
- { 2188, 6, 0, 0, "SHR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2188 = SHR16mi
- { 2189, 2, 1, 0, "SHR16r1", 0, 0|21|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2189 = SHR16r1
- { 2190, 2, 1, 0, "SHR16rCL", 0, 0|21|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2190 = SHR16rCL
- { 2191, 3, 1, 0, "SHR16ri", 0, 0|21|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2191 = SHR16ri
- { 2192, 5, 0, 0, "SHR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2192 = SHR32m1
- { 2193, 5, 0, 0, "SHR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2193 = SHR32mCL
- { 2194, 6, 0, 0, "SHR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2194 = SHR32mi
- { 2195, 2, 1, 0, "SHR32r1", 0, 0|21|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2195 = SHR32r1
- { 2196, 2, 1, 0, "SHR32rCL", 0, 0|21|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2196 = SHR32rCL
- { 2197, 3, 1, 0, "SHR32ri", 0, 0|21|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2197 = SHR32ri
- { 2198, 5, 0, 0, "SHR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2198 = SHR64m1
- { 2199, 5, 0, 0, "SHR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2199 = SHR64mCL
- { 2200, 6, 0, 0, "SHR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2200 = SHR64mi
- { 2201, 2, 1, 0, "SHR64r1", 0, 0|21|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2201 = SHR64r1
- { 2202, 2, 1, 0, "SHR64rCL", 0, 0|21|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2202 = SHR64rCL
- { 2203, 3, 1, 0, "SHR64ri", 0, 0|21|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2203 = SHR64ri
- { 2204, 5, 0, 0, "SHR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2204 = SHR8m1
- { 2205, 5, 0, 0, "SHR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2205 = SHR8mCL
- { 2206, 6, 0, 0, "SHR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2206 = SHR8mi
- { 2207, 2, 1, 0, "SHR8r1", 0, 0|21|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2207 = SHR8r1
- { 2208, 2, 1, 0, "SHR8rCL", 0, 0|21|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2208 = SHR8rCL
- { 2209, 3, 1, 0, "SHR8ri", 0, 0|21|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2209 = SHR8ri
- { 2210, 6, 0, 0, "SHRD16mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2210 = SHRD16mrCL
- { 2211, 7, 0, 0, "SHRD16mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo190 }, // Inst #2211 = SHRD16mri8
- { 2212, 3, 1, 0, "SHRD16rrCL", 0, 0|3|(1<<6)|(1<<8)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2212 = SHRD16rrCL
- { 2213, 4, 1, 0, "SHRD16rri8", 0|(1<<TID::Commutable), 0|3|(1<<6)|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo191 }, // Inst #2213 = SHRD16rri8
- { 2214, 6, 0, 0, "SHRD32mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2214 = SHRD32mrCL
- { 2215, 7, 0, 0, "SHRD32mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo192 }, // Inst #2215 = SHRD32mri8
- { 2216, 3, 1, 0, "SHRD32rrCL", 0, 0|3|(1<<8)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2216 = SHRD32rrCL
- { 2217, 4, 1, 0, "SHRD32rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo193 }, // Inst #2217 = SHRD32rri8
- { 2218, 6, 0, 0, "SHRD64mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2218 = SHRD64mrCL
- { 2219, 7, 0, 0, "SHRD64mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #2219 = SHRD64mri8
- { 2220, 3, 1, 0, "SHRD64rrCL", 0, 0|3|(1<<8)|(1<<12)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2220 = SHRD64rrCL
- { 2221, 4, 1, 0, "SHRD64rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<12)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #2221 = SHRD64rri8
- { 2222, 8, 1, 0, "SHUFPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2222 = SHUFPDrmi
- { 2223, 4, 1, 0, "SHUFPDrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2223 = SHUFPDrri
- { 2224, 8, 1, 0, "SHUFPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2224 = SHUFPSrmi
- { 2225, 4, 1, 0, "SHUFPSrri", 0|(1<<TID::ConvertibleTo3Addr), 0|5|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2225 = SHUFPSrri
- { 2226, 5, 1, 0, "SIDTm", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2226 = SIDTm
- { 2227, 0, 0, 0, "SIN_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(254<<24), NULL, NULL, NULL, 0 }, // Inst #2227 = SIN_F
- { 2228, 2, 1, 0, "SIN_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #2228 = SIN_Fp32
- { 2229, 2, 1, 0, "SIN_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #2229 = SIN_Fp64
- { 2230, 2, 1, 0, "SIN_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #2230 = SIN_Fp80
- { 2231, 5, 1, 0, "SLDT16m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2231 = SLDT16m
- { 2232, 1, 1, 0, "SLDT16r", 0|(1<<TID::UnmodeledSideEffects), 0|16|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2232 = SLDT16r
- { 2233, 5, 1, 0, "SLDT64m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8)|(1<<12), NULL, NULL, NULL, OperandInfo30 }, // Inst #2233 = SLDT64m
- { 2234, 1, 1, 0, "SLDT64r", 0|(1<<TID::UnmodeledSideEffects), 0|16|(1<<8)|(1<<12), NULL, NULL, NULL, OperandInfo58 }, // Inst #2234 = SLDT64r
- { 2235, 5, 1, 0, "SMSW16m", 0|(1<<TID::UnmodeledSideEffects), 0|28|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2235 = SMSW16m
- { 2236, 1, 1, 0, "SMSW16r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<6)|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo93 }, // Inst #2236 = SMSW16r
- { 2237, 1, 1, 0, "SMSW32r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2237 = SMSW32r
- { 2238, 1, 1, 0, "SMSW64r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8)|(1<<12)|(1<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2238 = SMSW64r
- { 2239, 6, 1, 0, "SQRTPDm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2239 = SQRTPDm
- { 2240, 6, 1, 0, "SQRTPDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2240 = SQRTPDm_Int
- { 2241, 2, 1, 0, "SQRTPDr", 0, 0|5|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2241 = SQRTPDr
- { 2242, 2, 1, 0, "SQRTPDr_Int", 0, 0|5|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2242 = SQRTPDr_Int
- { 2243, 6, 1, 0, "SQRTPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2243 = SQRTPSm
- { 2244, 6, 1, 0, "SQRTPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2244 = SQRTPSm_Int
- { 2245, 2, 1, 0, "SQRTPSr", 0, 0|5|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2245 = SQRTPSr
- { 2246, 2, 1, 0, "SQRTPSr_Int", 0, 0|5|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2246 = SQRTPSr_Int
- { 2247, 6, 1, 0, "SQRTSDm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #2247 = SQRTSDm
- { 2248, 6, 1, 0, "SQRTSDm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2248 = SQRTSDm_Int
- { 2249, 2, 1, 0, "SQRTSDr", 0, 0|5|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #2249 = SQRTSDr
- { 2250, 2, 1, 0, "SQRTSDr_Int", 0, 0|5|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2250 = SQRTSDr_Int
- { 2251, 6, 1, 0, "SQRTSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #2251 = SQRTSSm
- { 2252, 6, 1, 0, "SQRTSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2252 = SQRTSSm_Int
- { 2253, 2, 1, 0, "SQRTSSr", 0, 0|5|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #2253 = SQRTSSr
- { 2254, 2, 1, 0, "SQRTSSr_Int", 0, 0|5|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2254 = SQRTSSr_Int
- { 2255, 0, 0, 0, "SQRT_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(250<<24), NULL, NULL, NULL, 0 }, // Inst #2255 = SQRT_F
- { 2256, 2, 1, 0, "SQRT_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #2256 = SQRT_Fp32
- { 2257, 2, 1, 0, "SQRT_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #2257 = SQRT_Fp64
- { 2258, 2, 1, 0, "SQRT_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #2258 = SQRT_Fp80
- { 2259, 0, 0, 0, "SS_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(54<<24), NULL, NULL, NULL, 0 }, // Inst #2259 = SS_PREFIX
- { 2260, 0, 0, 0, "STC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(249<<24), NULL, NULL, NULL, 0 }, // Inst #2260 = STC
- { 2261, 0, 0, 0, "STD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(253<<24), NULL, NULL, NULL, 0 }, // Inst #2261 = STD
- { 2262, 0, 0, 0, "STI", 0|(1<<TID::UnmodeledSideEffects), 0|1|(251<<24), NULL, NULL, NULL, 0 }, // Inst #2262 = STI
- { 2263, 5, 0, 0, "STMXCSR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2263 = STMXCSR
- { 2264, 0, 0, 0, "STOSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(170<<24), ImplicitList54, ImplicitList35, NULL, 0 }, // Inst #2264 = STOSB
- { 2265, 0, 0, 0, "STOSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(171<<24), ImplicitList55, ImplicitList35, NULL, 0 }, // Inst #2265 = STOSD
- { 2266, 0, 0, 0, "STOSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(171<<24), ImplicitList56, ImplicitList35, NULL, 0 }, // Inst #2266 = STOSW
- { 2267, 5, 1, 0, "STRm", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2267 = STRm
- { 2268, 1, 1, 0, "STRr", 0|(1<<TID::UnmodeledSideEffects), 0|17|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2268 = STRr
- { 2269, 5, 0, 0, "ST_F32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2269 = ST_F32m
- { 2270, 5, 0, 0, "ST_F64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2270 = ST_F64m
- { 2271, 5, 0, 0, "ST_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2271 = ST_FP32m
- { 2272, 5, 0, 0, "ST_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2272 = ST_FP64m
- { 2273, 5, 0, 0, "ST_FP80m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2273 = ST_FP80m
- { 2274, 1, 0, 0, "ST_FPrr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(216<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2274 = ST_FPrr
- { 2275, 6, 0, 0, "ST_Fp32m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #2275 = ST_Fp32m
- { 2276, 6, 0, 0, "ST_Fp64m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2276 = ST_Fp64m
- { 2277, 6, 0, 0, "ST_Fp64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2277 = ST_Fp64m32
- { 2278, 6, 0, 0, "ST_Fp80m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2278 = ST_Fp80m32
- { 2279, 6, 0, 0, "ST_Fp80m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2279 = ST_Fp80m64
- { 2280, 6, 0, 0, "ST_FpP32m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #2280 = ST_FpP32m
- { 2281, 6, 0, 0, "ST_FpP64m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2281 = ST_FpP64m
- { 2282, 6, 0, 0, "ST_FpP64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2282 = ST_FpP64m32
- { 2283, 6, 0, 0, "ST_FpP80m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2283 = ST_FpP80m
- { 2284, 6, 0, 0, "ST_FpP80m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2284 = ST_FpP80m32
- { 2285, 6, 0, 0, "ST_FpP80m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2285 = ST_FpP80m64
- { 2286, 1, 0, 0, "ST_Frr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(208<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2286 = ST_Frr
- { 2287, 1, 0, 0, "SUB16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2287 = SUB16i16
- { 2288, 6, 0, 0, "SUB16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2288 = SUB16mi
- { 2289, 6, 0, 0, "SUB16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2289 = SUB16mi8
- { 2290, 6, 0, 0, "SUB16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2290 = SUB16mr
- { 2291, 3, 1, 0, "SUB16ri", 0, 0|21|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2291 = SUB16ri
- { 2292, 3, 1, 0, "SUB16ri8", 0, 0|21|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2292 = SUB16ri8
- { 2293, 7, 1, 0, "SUB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2293 = SUB16rm
- { 2294, 3, 1, 0, "SUB16rr", 0, 0|3|(1<<6)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2294 = SUB16rr
- { 2295, 3, 1, 0, "SUB16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2295 = SUB16rr_REV
- { 2296, 1, 0, 0, "SUB32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2296 = SUB32i32
- { 2297, 6, 0, 0, "SUB32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2297 = SUB32mi
- { 2298, 6, 0, 0, "SUB32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2298 = SUB32mi8
- { 2299, 6, 0, 0, "SUB32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2299 = SUB32mr
- { 2300, 3, 1, 0, "SUB32ri", 0, 0|21|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2300 = SUB32ri
- { 2301, 3, 1, 0, "SUB32ri8", 0, 0|21|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2301 = SUB32ri8
- { 2302, 7, 1, 0, "SUB32rm", 0|(1<<TID::MayLoad), 0|6|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2302 = SUB32rm
- { 2303, 3, 1, 0, "SUB32rr", 0, 0|3|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2303 = SUB32rr
- { 2304, 3, 1, 0, "SUB32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2304 = SUB32rr_REV
- { 2305, 1, 0, 0, "SUB64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2305 = SUB64i32
- { 2306, 6, 0, 0, "SUB64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2306 = SUB64mi32
- { 2307, 6, 0, 0, "SUB64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2307 = SUB64mi8
- { 2308, 6, 0, 0, "SUB64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2308 = SUB64mr
- { 2309, 3, 1, 0, "SUB64ri32", 0, 0|21|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2309 = SUB64ri32
- { 2310, 3, 1, 0, "SUB64ri8", 0, 0|21|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2310 = SUB64ri8
- { 2311, 7, 1, 0, "SUB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2311 = SUB64rm
- { 2312, 3, 1, 0, "SUB64rr", 0, 0|3|(1<<12)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2312 = SUB64rr
- { 2313, 3, 1, 0, "SUB64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2313 = SUB64rr_REV
- { 2314, 1, 0, 0, "SUB8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(44<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2314 = SUB8i8
- { 2315, 6, 0, 0, "SUB8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2315 = SUB8mi
- { 2316, 6, 0, 0, "SUB8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2316 = SUB8mr
- { 2317, 3, 1, 0, "SUB8ri", 0, 0|21|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2317 = SUB8ri
- { 2318, 7, 1, 0, "SUB8rm", 0|(1<<TID::MayLoad), 0|6|(42<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2318 = SUB8rm
- { 2319, 3, 1, 0, "SUB8rr", 0, 0|3|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2319 = SUB8rr
- { 2320, 3, 1, 0, "SUB8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(42<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2320 = SUB8rr_REV
- { 2321, 7, 1, 0, "SUBPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2321 = SUBPDrm
- { 2322, 3, 1, 0, "SUBPDrr", 0, 0|5|(1<<6)|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2322 = SUBPDrr
- { 2323, 7, 1, 0, "SUBPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2323 = SUBPSrm
- { 2324, 3, 1, 0, "SUBPSrr", 0, 0|5|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2324 = SUBPSrr
- { 2325, 5, 0, 0, "SUBR_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2325 = SUBR_F32m
- { 2326, 5, 0, 0, "SUBR_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2326 = SUBR_F64m
- { 2327, 5, 0, 0, "SUBR_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2327 = SUBR_FI16m
- { 2328, 5, 0, 0, "SUBR_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2328 = SUBR_FI32m
- { 2329, 1, 0, 0, "SUBR_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2329 = SUBR_FPrST0
- { 2330, 1, 0, 0, "SUBR_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2330 = SUBR_FST0r
- { 2331, 7, 1, 0, "SUBR_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2331 = SUBR_Fp32m
- { 2332, 7, 1, 0, "SUBR_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2332 = SUBR_Fp64m
- { 2333, 7, 1, 0, "SUBR_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2333 = SUBR_Fp64m32
- { 2334, 7, 1, 0, "SUBR_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2334 = SUBR_Fp80m32
- { 2335, 7, 1, 0, "SUBR_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2335 = SUBR_Fp80m64
- { 2336, 7, 1, 0, "SUBR_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2336 = SUBR_FpI16m32
- { 2337, 7, 1, 0, "SUBR_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2337 = SUBR_FpI16m64
- { 2338, 7, 1, 0, "SUBR_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2338 = SUBR_FpI16m80
- { 2339, 7, 1, 0, "SUBR_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2339 = SUBR_FpI32m32
- { 2340, 7, 1, 0, "SUBR_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2340 = SUBR_FpI32m64
- { 2341, 7, 1, 0, "SUBR_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2341 = SUBR_FpI32m80
- { 2342, 1, 0, 0, "SUBR_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2342 = SUBR_FrST0
- { 2343, 7, 1, 0, "SUBSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #2343 = SUBSDrm
- { 2344, 7, 1, 0, "SUBSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2344 = SUBSDrm_Int
- { 2345, 3, 1, 0, "SUBSDrr", 0, 0|5|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #2345 = SUBSDrr
- { 2346, 3, 1, 0, "SUBSDrr_Int", 0, 0|5|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2346 = SUBSDrr_Int
- { 2347, 7, 1, 0, "SUBSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #2347 = SUBSSrm
- { 2348, 7, 1, 0, "SUBSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2348 = SUBSSrm_Int
- { 2349, 3, 1, 0, "SUBSSrr", 0, 0|5|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2349 = SUBSSrr
- { 2350, 3, 1, 0, "SUBSSrr_Int", 0, 0|5|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2350 = SUBSSrr_Int
- { 2351, 5, 0, 0, "SUB_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2351 = SUB_F32m
- { 2352, 5, 0, 0, "SUB_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2352 = SUB_F64m
- { 2353, 5, 0, 0, "SUB_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2353 = SUB_FI16m
- { 2354, 5, 0, 0, "SUB_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2354 = SUB_FI32m
- { 2355, 1, 0, 0, "SUB_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2355 = SUB_FPrST0
- { 2356, 1, 0, 0, "SUB_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2356 = SUB_FST0r
- { 2357, 3, 1, 0, "SUB_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #2357 = SUB_Fp32
- { 2358, 7, 1, 0, "SUB_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2358 = SUB_Fp32m
- { 2359, 3, 1, 0, "SUB_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #2359 = SUB_Fp64
- { 2360, 7, 1, 0, "SUB_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2360 = SUB_Fp64m
- { 2361, 7, 1, 0, "SUB_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2361 = SUB_Fp64m32
- { 2362, 3, 1, 0, "SUB_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #2362 = SUB_Fp80
- { 2363, 7, 1, 0, "SUB_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2363 = SUB_Fp80m32
- { 2364, 7, 1, 0, "SUB_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2364 = SUB_Fp80m64
- { 2365, 7, 1, 0, "SUB_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2365 = SUB_FpI16m32
- { 2366, 7, 1, 0, "SUB_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2366 = SUB_FpI16m64
- { 2367, 7, 1, 0, "SUB_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2367 = SUB_FpI16m80
- { 2368, 7, 1, 0, "SUB_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2368 = SUB_FpI32m32
- { 2369, 7, 1, 0, "SUB_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2369 = SUB_FpI32m64
- { 2370, 7, 1, 0, "SUB_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2370 = SUB_FpI32m80
- { 2371, 1, 0, 0, "SUB_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2371 = SUB_FrST0
- { 2372, 0, 0, 0, "SWAPGS", 0|(1<<TID::UnmodeledSideEffects), 0|41|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2372 = SWAPGS
- { 2373, 0, 0, 0, "SYSCALL", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(5<<24), NULL, NULL, NULL, 0 }, // Inst #2373 = SYSCALL
- { 2374, 0, 0, 0, "SYSENTER", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(52<<24), NULL, NULL, NULL, 0 }, // Inst #2374 = SYSENTER
- { 2375, 0, 0, 0, "SYSEXIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(53<<24), NULL, NULL, NULL, 0 }, // Inst #2375 = SYSEXIT
- { 2376, 0, 0, 0, "SYSEXIT64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<12)|(53<<24), NULL, NULL, NULL, 0 }, // Inst #2376 = SYSEXIT64
- { 2377, 0, 0, 0, "SYSRET", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(7<<24), NULL, NULL, NULL, 0 }, // Inst #2377 = SYSRET
- { 2378, 1, 0, 0, "TAILJMPd", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(233<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #2378 = TAILJMPd
- { 2379, 5, 0, 0, "TAILJMPm", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|28|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2379 = TAILJMPm
- { 2380, 1, 0, 0, "TAILJMPr", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2380 = TAILJMPr
- { 2381, 1, 0, 0, "TAILJMPr64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2381 = TAILJMPr64
- { 2382, 2, 0, 0, "TCRETURNdi", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo38 }, // Inst #2382 = TCRETURNdi
- { 2383, 2, 0, 0, "TCRETURNdi64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo38 }, // Inst #2383 = TCRETURNdi64
- { 2384, 2, 0, 0, "TCRETURNri", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo55 }, // Inst #2384 = TCRETURNri
- { 2385, 2, 0, 0, "TCRETURNri64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo56 }, // Inst #2385 = TCRETURNri64
- { 2386, 1, 0, 0, "TEST16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2386 = TEST16i16
- { 2387, 6, 0, 0, "TEST16mi", 0|(1<<TID::MayLoad), 0|24|(1<<6)|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2387 = TEST16mi
- { 2388, 2, 0, 0, "TEST16ri", 0, 0|16|(1<<6)|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #2388 = TEST16ri
- { 2389, 6, 0, 0, "TEST16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #2389 = TEST16rm
- { 2390, 2, 0, 0, "TEST16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #2390 = TEST16rr
- { 2391, 1, 0, 0, "TEST32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2391 = TEST32i32
- { 2392, 6, 0, 0, "TEST32mi", 0|(1<<TID::MayLoad), 0|24|(4<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2392 = TEST32mi
- { 2393, 2, 0, 0, "TEST32ri", 0, 0|16|(4<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #2393 = TEST32ri
- { 2394, 6, 0, 0, "TEST32rm", 0|(1<<TID::MayLoad), 0|6|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #2394 = TEST32rm
- { 2395, 2, 0, 0, "TEST32rr", 0|(1<<TID::Commutable), 0|3|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #2395 = TEST32rr
- { 2396, 1, 0, 0, "TEST64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2396 = TEST64i32
- { 2397, 6, 0, 0, "TEST64mi32", 0|(1<<TID::MayLoad), 0|24|(1<<12)|(4<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2397 = TEST64mi32
- { 2398, 2, 0, 0, "TEST64ri32", 0, 0|16|(1<<12)|(4<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #2398 = TEST64ri32
- { 2399, 6, 0, 0, "TEST64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #2399 = TEST64rm
- { 2400, 2, 0, 0, "TEST64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #2400 = TEST64rr
- { 2401, 1, 0, 0, "TEST8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(168<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2401 = TEST8i8
- { 2402, 6, 0, 0, "TEST8mi", 0|(1<<TID::MayLoad), 0|24|(1<<13)|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2402 = TEST8mi
- { 2403, 2, 0, 0, "TEST8ri", 0, 0|16|(1<<13)|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo68 }, // Inst #2403 = TEST8ri
- { 2404, 6, 0, 0, "TEST8rm", 0|(1<<TID::MayLoad), 0|6|(132<<24), NULL, ImplicitList1, Barriers1, OperandInfo69 }, // Inst #2404 = TEST8rm
- { 2405, 2, 0, 0, "TEST8rr", 0|(1<<TID::Commutable), 0|3|(132<<24), NULL, ImplicitList1, Barriers1, OperandInfo67 }, // Inst #2405 = TEST8rr
- { 2406, 4, 0, 0, "TLS_addr32", 0, 0, ImplicitList2, ImplicitList9, Barriers3, OperandInfo197 }, // Inst #2406 = TLS_addr32
- { 2407, 4, 0, 0, "TLS_addr64", 0, 0, ImplicitList4, ImplicitList10, Barriers4, OperandInfo198 }, // Inst #2407 = TLS_addr64
- { 2408, 0, 0, 0, "TRAP", 0|(1<<TID::Barrier)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(11<<24), NULL, NULL, NULL, 0 }, // Inst #2408 = TRAP
- { 2409, 0, 0, 0, "TST_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(228<<24), NULL, NULL, NULL, 0 }, // Inst #2409 = TST_F
- { 2410, 1, 0, 0, "TST_Fp32", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #2410 = TST_Fp32
- { 2411, 1, 0, 0, "TST_Fp64", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #2411 = TST_Fp64
- { 2412, 1, 0, 0, "TST_Fp80", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #2412 = TST_Fp80
- { 2413, 6, 0, 0, "UCOMISDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo82 }, // Inst #2413 = UCOMISDrm
- { 2414, 2, 0, 0, "UCOMISDrr", 0, 0|5|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo105 }, // Inst #2414 = UCOMISDrr
- { 2415, 6, 0, 0, "UCOMISSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo80 }, // Inst #2415 = UCOMISSrm
- { 2416, 2, 0, 0, "UCOMISSrr", 0, 0|5|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo106 }, // Inst #2416 = UCOMISSrr
- { 2417, 1, 0, 0, "UCOM_FIPr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(10<<8)|(232<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2417 = UCOM_FIPr
- { 2418, 1, 0, 0, "UCOM_FIr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(232<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2418 = UCOM_FIr
- { 2419, 0, 0, 0, "UCOM_FPPr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(5<<8)|(233<<24), ImplicitList24, ImplicitList1, Barriers1, 0 }, // Inst #2419 = UCOM_FPPr
- { 2420, 1, 0, 0, "UCOM_FPr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(232<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2420 = UCOM_FPr
- { 2421, 2, 0, 0, "UCOM_FpIr32", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #2421 = UCOM_FpIr32
- { 2422, 2, 0, 0, "UCOM_FpIr64", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #2422 = UCOM_FpIr64
- { 2423, 2, 0, 0, "UCOM_FpIr80", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #2423 = UCOM_FpIr80
- { 2424, 2, 0, 0, "UCOM_Fpr32", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #2424 = UCOM_Fpr32
- { 2425, 2, 0, 0, "UCOM_Fpr64", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #2425 = UCOM_Fpr64
- { 2426, 2, 0, 0, "UCOM_Fpr80", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #2426 = UCOM_Fpr80
- { 2427, 1, 0, 0, "UCOM_Fr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(224<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2427 = UCOM_Fr
- { 2428, 7, 1, 0, "UNPCKHPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2428 = UNPCKHPDrm
- { 2429, 3, 1, 0, "UNPCKHPDrr", 0, 0|5|(1<<6)|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2429 = UNPCKHPDrr
- { 2430, 7, 1, 0, "UNPCKHPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2430 = UNPCKHPSrm
- { 2431, 3, 1, 0, "UNPCKHPSrr", 0, 0|5|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2431 = UNPCKHPSrr
- { 2432, 7, 1, 0, "UNPCKLPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2432 = UNPCKLPDrm
- { 2433, 3, 1, 0, "UNPCKLPDrr", 0, 0|5|(1<<6)|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2433 = UNPCKLPDrr
- { 2434, 7, 1, 0, "UNPCKLPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2434 = UNPCKLPSrm
- { 2435, 3, 1, 0, "UNPCKLPSrr", 0, 0|5|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2435 = UNPCKLPSrr
- { 2436, 3, 0, 0, "VASTART_SAVE_XMM_REGS", 0|(1<<TID::UsesCustomInserter)|(1<<TID::Variadic), 0, NULL, NULL, NULL, OperandInfo199 }, // Inst #2436 = VASTART_SAVE_XMM_REGS
- { 2437, 5, 0, 0, "VERRm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2437 = VERRm
- { 2438, 1, 0, 0, "VERRr", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2438 = VERRr
- { 2439, 5, 0, 0, "VERWm", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2439 = VERWm
- { 2440, 1, 0, 0, "VERWr", 0|(1<<TID::UnmodeledSideEffects), 0|21|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2440 = VERWr
- { 2441, 0, 0, 0, "VMCALL", 0|(1<<TID::UnmodeledSideEffects), 0|33|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2441 = VMCALL
- { 2442, 5, 0, 0, "VMCLEARm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<6)|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2442 = VMCLEARm
- { 2443, 0, 0, 0, "VMLAUNCH", 0|(1<<TID::UnmodeledSideEffects), 0|34|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2443 = VMLAUNCH
- { 2444, 5, 0, 0, "VMPTRLDm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2444 = VMPTRLDm
- { 2445, 5, 1, 0, "VMPTRSTm", 0|(1<<TID::UnmodeledSideEffects), 0|31|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2445 = VMPTRSTm
- { 2446, 6, 1, 0, "VMREAD32rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #2446 = VMREAD32rm
- { 2447, 2, 1, 0, "VMREAD32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2447 = VMREAD32rr
- { 2448, 6, 1, 0, "VMREAD64rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #2448 = VMREAD64rm
- { 2449, 2, 1, 0, "VMREAD64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2449 = VMREAD64rr
- { 2450, 0, 0, 0, "VMRESUME", 0|(1<<TID::UnmodeledSideEffects), 0|35|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2450 = VMRESUME
- { 2451, 6, 1, 0, "VMWRITE32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #2451 = VMWRITE32rm
- { 2452, 2, 1, 0, "VMWRITE32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2452 = VMWRITE32rr
- { 2453, 6, 1, 0, "VMWRITE64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #2453 = VMWRITE64rm
- { 2454, 2, 1, 0, "VMWRITE64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2454 = VMWRITE64rr
- { 2455, 0, 0, 0, "VMXOFF", 0|(1<<TID::UnmodeledSideEffects), 0|36|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2455 = VMXOFF
- { 2456, 5, 0, 0, "VMXON", 0|(1<<TID::UnmodeledSideEffects), 0|30|(11<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2456 = VMXON
- { 2457, 1, 1, 0, "V_SET0", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo200 }, // Inst #2457 = V_SET0
- { 2458, 1, 1, 0, "V_SETALLONES", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo200 }, // Inst #2458 = V_SETALLONES
- { 2459, 0, 0, 0, "WAIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(155<<24), NULL, NULL, NULL, 0 }, // Inst #2459 = WAIT
- { 2460, 0, 0, 0, "WBINVD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(9<<24), NULL, NULL, NULL, 0 }, // Inst #2460 = WBINVD
- { 2461, 5, 0, 0, "WINCALL64m", 0|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Variadic), 0|26|(255<<24), ImplicitList4, ImplicitList57, Barriers8, OperandInfo30 }, // Inst #2461 = WINCALL64m
- { 2462, 1, 0, 0, "WINCALL64pcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(232<<24), ImplicitList4, ImplicitList57, Barriers8, OperandInfo5 }, // Inst #2462 = WINCALL64pcrel32
- { 2463, 1, 0, 0, "WINCALL64r", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|18|(255<<24), ImplicitList4, ImplicitList57, Barriers8, OperandInfo58 }, // Inst #2463 = WINCALL64r
- { 2464, 0, 0, 0, "WRMSR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(48<<24), NULL, NULL, NULL, 0 }, // Inst #2464 = WRMSR
- { 2465, 6, 0, 0, "XADD16rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo7 }, // Inst #2465 = XADD16rm
- { 2466, 2, 1, 0, "XADD16rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<6)|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #2466 = XADD16rr
- { 2467, 6, 0, 0, "XADD32rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #2467 = XADD32rm
- { 2468, 2, 1, 0, "XADD32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2468 = XADD32rr
- { 2469, 6, 0, 0, "XADD64rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(193<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #2469 = XADD64rm
- { 2470, 2, 1, 0, "XADD64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(1<<12)|(193<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2470 = XADD64rr
- { 2471, 6, 0, 0, "XADD8rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(192<<24), NULL, NULL, NULL, OperandInfo20 }, // Inst #2471 = XADD8rm
- { 2472, 2, 1, 0, "XADD8rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(192<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #2472 = XADD8rr
- { 2473, 1, 0, 0, "XCHG16ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(1<<6)|(144<<24), NULL, NULL, NULL, OperandInfo93 }, // Inst #2473 = XCHG16ar
- { 2474, 7, 1, 0, "XCHG16rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<6)|(135<<24), NULL, NULL, NULL, OperandInfo9 }, // Inst #2474 = XCHG16rm
- { 2475, 3, 1, 0, "XCHG16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(135<<24), NULL, NULL, NULL, OperandInfo10 }, // Inst #2475 = XCHG16rr
- { 2476, 1, 0, 0, "XCHG32ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(144<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2476 = XCHG32ar
- { 2477, 7, 1, 0, "XCHG32rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(135<<24), NULL, NULL, NULL, OperandInfo13 }, // Inst #2477 = XCHG32rm
- { 2478, 3, 1, 0, "XCHG32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(135<<24), NULL, NULL, NULL, OperandInfo14 }, // Inst #2478 = XCHG32rr
- { 2479, 1, 0, 0, "XCHG64ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(1<<12)|(144<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2479 = XCHG64ar
- { 2480, 7, 1, 0, "XCHG64rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<12)|(135<<24), NULL, NULL, NULL, OperandInfo17 }, // Inst #2480 = XCHG64rm
- { 2481, 3, 1, 0, "XCHG64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(135<<24), NULL, NULL, NULL, OperandInfo18 }, // Inst #2481 = XCHG64rr
- { 2482, 7, 1, 0, "XCHG8rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(134<<24), NULL, NULL, NULL, OperandInfo22 }, // Inst #2482 = XCHG8rm
- { 2483, 3, 1, 0, "XCHG8rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(134<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2483 = XCHG8rr
- { 2484, 1, 0, 0, "XCH_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(4<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2484 = XCH_F
- { 2485, 0, 0, 0, "XLAT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(215<<24), NULL, NULL, NULL, 0 }, // Inst #2485 = XLAT
- { 2486, 1, 0, 0, "XOR16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2486 = XOR16i16
- { 2487, 6, 0, 0, "XOR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2487 = XOR16mi
- { 2488, 6, 0, 0, "XOR16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2488 = XOR16mi8
- { 2489, 6, 0, 0, "XOR16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2489 = XOR16mr
- { 2490, 3, 1, 0, "XOR16ri", 0, 0|22|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2490 = XOR16ri
- { 2491, 3, 1, 0, "XOR16ri8", 0, 0|22|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2491 = XOR16ri8
- { 2492, 7, 1, 0, "XOR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2492 = XOR16rm
- { 2493, 3, 1, 0, "XOR16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2493 = XOR16rr
- { 2494, 3, 1, 0, "XOR16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2494 = XOR16rr_REV
- { 2495, 1, 0, 0, "XOR32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2495 = XOR32i32
- { 2496, 6, 0, 0, "XOR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2496 = XOR32mi
- { 2497, 6, 0, 0, "XOR32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2497 = XOR32mi8
- { 2498, 6, 0, 0, "XOR32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2498 = XOR32mr
- { 2499, 3, 1, 0, "XOR32ri", 0, 0|22|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2499 = XOR32ri
- { 2500, 3, 1, 0, "XOR32ri8", 0, 0|22|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2500 = XOR32ri8
- { 2501, 7, 1, 0, "XOR32rm", 0|(1<<TID::MayLoad), 0|6|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2501 = XOR32rm
- { 2502, 3, 1, 0, "XOR32rr", 0|(1<<TID::Commutable), 0|3|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2502 = XOR32rr
- { 2503, 3, 1, 0, "XOR32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2503 = XOR32rr_REV
- { 2504, 1, 0, 0, "XOR64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(4<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2504 = XOR64i32
- { 2505, 6, 0, 0, "XOR64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2505 = XOR64mi32
- { 2506, 6, 0, 0, "XOR64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2506 = XOR64mi8
- { 2507, 6, 0, 0, "XOR64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2507 = XOR64mr
- { 2508, 3, 1, 0, "XOR64ri32", 0, 0|22|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2508 = XOR64ri32
- { 2509, 3, 1, 0, "XOR64ri8", 0, 0|22|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2509 = XOR64ri8
- { 2510, 7, 1, 0, "XOR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2510 = XOR64rm
- { 2511, 3, 1, 0, "XOR64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2511 = XOR64rr
- { 2512, 3, 1, 0, "XOR64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2512 = XOR64rr_REV
- { 2513, 1, 0, 0, "XOR8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(52<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2513 = XOR8i8
- { 2514, 6, 0, 0, "XOR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2514 = XOR8mi
- { 2515, 6, 0, 0, "XOR8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2515 = XOR8mr
- { 2516, 3, 1, 0, "XOR8ri", 0, 0|22|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2516 = XOR8ri
- { 2517, 7, 1, 0, "XOR8rm", 0|(1<<TID::MayLoad), 0|6|(50<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2517 = XOR8rm
- { 2518, 3, 1, 0, "XOR8rr", 0|(1<<TID::Commutable), 0|3|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2518 = XOR8rr
- { 2519, 3, 1, 0, "XOR8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(50<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2519 = XOR8rr_REV
- { 2520, 7, 1, 0, "XORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2520 = XORPDrm
- { 2521, 3, 1, 0, "XORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2521 = XORPDrr
- { 2522, 7, 1, 0, "XORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2522 = XORPSrm
- { 2523, 3, 1, 0, "XORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2523 = XORPSrr
+ { 1081, 0, 0, 0, "MINGW_ALLOCA", 0|(1<<TID::UsesCustomInserter), 0, NULL, NULL, NULL, 0 }, // Inst #1081 = MINGW_ALLOCA
+ { 1082, 7, 1, 0, "MINPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1082 = MINPDrm
+ { 1083, 7, 1, 0, "MINPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1083 = MINPDrm_Int
+ { 1084, 3, 1, 0, "MINPDrr", 0, 0|5|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1084 = MINPDrr
+ { 1085, 3, 1, 0, "MINPDrr_Int", 0, 0|5|(1<<6)|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1085 = MINPDrr_Int
+ { 1086, 7, 1, 0, "MINPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1086 = MINPSrm
+ { 1087, 7, 1, 0, "MINPSrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1087 = MINPSrm_Int
+ { 1088, 3, 1, 0, "MINPSrr", 0, 0|5|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1088 = MINPSrr
+ { 1089, 3, 1, 0, "MINPSrr_Int", 0, 0|5|(1<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1089 = MINPSrr_Int
+ { 1090, 7, 1, 0, "MINSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #1090 = MINSDrm
+ { 1091, 7, 1, 0, "MINSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1091 = MINSDrm_Int
+ { 1092, 3, 1, 0, "MINSDrr", 0, 0|5|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #1092 = MINSDrr
+ { 1093, 3, 1, 0, "MINSDrr_Int", 0, 0|5|(11<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1093 = MINSDrr_Int
+ { 1094, 7, 1, 0, "MINSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #1094 = MINSSrm
+ { 1095, 7, 1, 0, "MINSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1095 = MINSSrm_Int
+ { 1096, 3, 1, 0, "MINSSrr", 0, 0|5|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1096 = MINSSrr
+ { 1097, 3, 1, 0, "MINSSrr_Int", 0, 0|5|(12<<8)|(93<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1097 = MINSSrr_Int
+ { 1098, 6, 1, 0, "MMX_CVTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1098 = MMX_CVTPD2PIrm
+ { 1099, 2, 1, 0, "MMX_CVTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1099 = MMX_CVTPD2PIrr
+ { 1100, 6, 1, 0, "MMX_CVTPI2PDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1100 = MMX_CVTPI2PDrm
+ { 1101, 2, 1, 0, "MMX_CVTPI2PDrr", 0, 0|5|(1<<6)|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #1101 = MMX_CVTPI2PDrr
+ { 1102, 6, 1, 0, "MMX_CVTPI2PSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1102 = MMX_CVTPI2PSrm
+ { 1103, 2, 1, 0, "MMX_CVTPI2PSrr", 0, 0|5|(1<<8)|(42<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #1103 = MMX_CVTPI2PSrr
+ { 1104, 6, 1, 0, "MMX_CVTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1104 = MMX_CVTPS2PIrm
+ { 1105, 2, 1, 0, "MMX_CVTPS2PIrr", 0, 0|5|(1<<8)|(45<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1105 = MMX_CVTPS2PIrr
+ { 1106, 6, 1, 0, "MMX_CVTTPD2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1106 = MMX_CVTTPD2PIrm
+ { 1107, 2, 1, 0, "MMX_CVTTPD2PIrr", 0, 0|5|(1<<6)|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1107 = MMX_CVTTPD2PIrr
+ { 1108, 6, 1, 0, "MMX_CVTTPS2PIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1108 = MMX_CVTTPS2PIrm
+ { 1109, 2, 1, 0, "MMX_CVTTPS2PIrr", 0, 0|5|(1<<8)|(44<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1109 = MMX_CVTTPS2PIrr
+ { 1110, 0, 0, 0, "MMX_EMMS", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(119<<24), NULL, NULL, NULL, 0 }, // Inst #1110 = MMX_EMMS
+ { 1111, 0, 0, 0, "MMX_FEMMS", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(14<<24), NULL, NULL, NULL, 0 }, // Inst #1111 = MMX_FEMMS
+ { 1112, 2, 0, 0, "MMX_MASKMOVQ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(247<<24), ImplicitList35, NULL, NULL, OperandInfo129 }, // Inst #1112 = MMX_MASKMOVQ
+ { 1113, 2, 0, 0, "MMX_MASKMOVQ64", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(247<<24), ImplicitList36, NULL, NULL, OperandInfo129 }, // Inst #1113 = MMX_MASKMOVQ64
+ { 1114, 2, 1, 0, "MMX_MOVD64from64rr", 0, 0|3|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo130 }, // Inst #1114 = MMX_MOVD64from64rr
+ { 1115, 2, 0, 0, "MMX_MOVD64grr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo131 }, // Inst #1115 = MMX_MOVD64grr
+ { 1116, 6, 0, 0, "MMX_MOVD64mr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1116 = MMX_MOVD64mr
+ { 1117, 6, 1, 0, "MMX_MOVD64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1117 = MMX_MOVD64rm
+ { 1118, 2, 1, 0, "MMX_MOVD64rr", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo133 }, // Inst #1118 = MMX_MOVD64rr
+ { 1119, 2, 1, 0, "MMX_MOVD64rrv164", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1119 = MMX_MOVD64rrv164
+ { 1120, 2, 1, 0, "MMX_MOVD64to64rr", 0, 0|5|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo134 }, // Inst #1120 = MMX_MOVD64to64rr
+ { 1121, 2, 1, 0, "MMX_MOVDQ2Qrr", 0, 0|5|(11<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo118 }, // Inst #1121 = MMX_MOVDQ2Qrr
+ { 1122, 6, 0, 0, "MMX_MOVNTQmr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1122 = MMX_MOVNTQmr
+ { 1123, 2, 1, 0, "MMX_MOVQ2DQrr", 0, 0|5|(12<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo119 }, // Inst #1123 = MMX_MOVQ2DQrr
+ { 1124, 2, 1, 0, "MMX_MOVQ2FR64rr", 0, 0|5|(12<<8)|(1<<13)|(214<<24), NULL, NULL, NULL, OperandInfo135 }, // Inst #1124 = MMX_MOVQ2FR64rr
+ { 1125, 6, 0, 0, "MMX_MOVQ64gmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1125 = MMX_MOVQ64gmr
+ { 1126, 6, 0, 0, "MMX_MOVQ64mr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(127<<24), NULL, NULL, NULL, OperandInfo132 }, // Inst #1126 = MMX_MOVQ64mr
+ { 1127, 6, 1, 0, "MMX_MOVQ64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1127 = MMX_MOVQ64rm
+ { 1128, 2, 1, 0, "MMX_MOVQ64rr", 0, 0|5|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1128 = MMX_MOVQ64rr
+ { 1129, 6, 1, 0, "MMX_MOVZDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1129 = MMX_MOVZDI2PDIrm
+ { 1130, 2, 1, 0, "MMX_MOVZDI2PDIrr", 0, 0|5|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo133 }, // Inst #1130 = MMX_MOVZDI2PDIrr
+ { 1131, 7, 1, 0, "MMX_PACKSSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1131 = MMX_PACKSSDWrm
+ { 1132, 3, 1, 0, "MMX_PACKSSDWrr", 0, 0|5|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1132 = MMX_PACKSSDWrr
+ { 1133, 7, 1, 0, "MMX_PACKSSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1133 = MMX_PACKSSWBrm
+ { 1134, 3, 1, 0, "MMX_PACKSSWBrr", 0, 0|5|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1134 = MMX_PACKSSWBrr
+ { 1135, 7, 1, 0, "MMX_PACKUSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1135 = MMX_PACKUSWBrm
+ { 1136, 3, 1, 0, "MMX_PACKUSWBrr", 0, 0|5|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1136 = MMX_PACKUSWBrr
+ { 1137, 7, 1, 0, "MMX_PADDBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1137 = MMX_PADDBrm
+ { 1138, 3, 1, 0, "MMX_PADDBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1138 = MMX_PADDBrr
+ { 1139, 7, 1, 0, "MMX_PADDDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1139 = MMX_PADDDrm
+ { 1140, 3, 1, 0, "MMX_PADDDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1140 = MMX_PADDDrr
+ { 1141, 7, 1, 0, "MMX_PADDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1141 = MMX_PADDQrm
+ { 1142, 3, 1, 0, "MMX_PADDQrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1142 = MMX_PADDQrr
+ { 1143, 7, 1, 0, "MMX_PADDSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1143 = MMX_PADDSBrm
+ { 1144, 3, 1, 0, "MMX_PADDSBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1144 = MMX_PADDSBrr
+ { 1145, 7, 1, 0, "MMX_PADDSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1145 = MMX_PADDSWrm
+ { 1146, 3, 1, 0, "MMX_PADDSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1146 = MMX_PADDSWrr
+ { 1147, 7, 1, 0, "MMX_PADDUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1147 = MMX_PADDUSBrm
+ { 1148, 3, 1, 0, "MMX_PADDUSBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1148 = MMX_PADDUSBrr
+ { 1149, 7, 1, 0, "MMX_PADDUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1149 = MMX_PADDUSWrm
+ { 1150, 3, 1, 0, "MMX_PADDUSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1150 = MMX_PADDUSWrr
+ { 1151, 7, 1, 0, "MMX_PADDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1151 = MMX_PADDWrm
+ { 1152, 3, 1, 0, "MMX_PADDWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1152 = MMX_PADDWrr
+ { 1153, 7, 1, 0, "MMX_PANDNrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1153 = MMX_PANDNrm
+ { 1154, 3, 1, 0, "MMX_PANDNrr", 0, 0|5|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1154 = MMX_PANDNrr
+ { 1155, 7, 1, 0, "MMX_PANDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1155 = MMX_PANDrm
+ { 1156, 3, 1, 0, "MMX_PANDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1156 = MMX_PANDrr
+ { 1157, 7, 1, 0, "MMX_PAVGBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1157 = MMX_PAVGBrm
+ { 1158, 3, 1, 0, "MMX_PAVGBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1158 = MMX_PAVGBrr
+ { 1159, 7, 1, 0, "MMX_PAVGWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1159 = MMX_PAVGWrm
+ { 1160, 3, 1, 0, "MMX_PAVGWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1160 = MMX_PAVGWrr
+ { 1161, 7, 1, 0, "MMX_PCMPEQBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1161 = MMX_PCMPEQBrm
+ { 1162, 3, 1, 0, "MMX_PCMPEQBrr", 0, 0|5|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1162 = MMX_PCMPEQBrr
+ { 1163, 7, 1, 0, "MMX_PCMPEQDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1163 = MMX_PCMPEQDrm
+ { 1164, 3, 1, 0, "MMX_PCMPEQDrr", 0, 0|5|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1164 = MMX_PCMPEQDrr
+ { 1165, 7, 1, 0, "MMX_PCMPEQWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1165 = MMX_PCMPEQWrm
+ { 1166, 3, 1, 0, "MMX_PCMPEQWrr", 0, 0|5|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1166 = MMX_PCMPEQWrr
+ { 1167, 7, 1, 0, "MMX_PCMPGTBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1167 = MMX_PCMPGTBrm
+ { 1168, 3, 1, 0, "MMX_PCMPGTBrr", 0, 0|5|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1168 = MMX_PCMPGTBrr
+ { 1169, 7, 1, 0, "MMX_PCMPGTDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1169 = MMX_PCMPGTDrm
+ { 1170, 3, 1, 0, "MMX_PCMPGTDrr", 0, 0|5|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1170 = MMX_PCMPGTDrr
+ { 1171, 7, 1, 0, "MMX_PCMPGTWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1171 = MMX_PCMPGTWrm
+ { 1172, 3, 1, 0, "MMX_PCMPGTWrr", 0, 0|5|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1172 = MMX_PCMPGTWrr
+ { 1173, 3, 1, 0, "MMX_PEXTRWri", 0, 0|5|(1<<8)|(1<<13)|(197<<24), NULL, NULL, NULL, OperandInfo138 }, // Inst #1173 = MMX_PEXTRWri
+ { 1174, 8, 1, 0, "MMX_PINSRWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo139 }, // Inst #1174 = MMX_PINSRWrmi
+ { 1175, 4, 1, 0, "MMX_PINSRWrri", 0, 0|5|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo140 }, // Inst #1175 = MMX_PINSRWrri
+ { 1176, 7, 1, 0, "MMX_PMADDWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1176 = MMX_PMADDWDrm
+ { 1177, 3, 1, 0, "MMX_PMADDWDrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1177 = MMX_PMADDWDrr
+ { 1178, 7, 1, 0, "MMX_PMAXSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1178 = MMX_PMAXSWrm
+ { 1179, 3, 1, 0, "MMX_PMAXSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1179 = MMX_PMAXSWrr
+ { 1180, 7, 1, 0, "MMX_PMAXUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1180 = MMX_PMAXUBrm
+ { 1181, 3, 1, 0, "MMX_PMAXUBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1181 = MMX_PMAXUBrr
+ { 1182, 7, 1, 0, "MMX_PMINSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1182 = MMX_PMINSWrm
+ { 1183, 3, 1, 0, "MMX_PMINSWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1183 = MMX_PMINSWrr
+ { 1184, 7, 1, 0, "MMX_PMINUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1184 = MMX_PMINUBrm
+ { 1185, 3, 1, 0, "MMX_PMINUBrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1185 = MMX_PMINUBrr
+ { 1186, 2, 1, 0, "MMX_PMOVMSKBrr", 0, 0|5|(1<<8)|(215<<24), NULL, NULL, NULL, OperandInfo131 }, // Inst #1186 = MMX_PMOVMSKBrr
+ { 1187, 7, 1, 0, "MMX_PMULHUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1187 = MMX_PMULHUWrm
+ { 1188, 3, 1, 0, "MMX_PMULHUWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1188 = MMX_PMULHUWrr
+ { 1189, 7, 1, 0, "MMX_PMULHWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1189 = MMX_PMULHWrm
+ { 1190, 3, 1, 0, "MMX_PMULHWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1190 = MMX_PMULHWrr
+ { 1191, 7, 1, 0, "MMX_PMULLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1191 = MMX_PMULLWrm
+ { 1192, 3, 1, 0, "MMX_PMULLWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1192 = MMX_PMULLWrr
+ { 1193, 7, 1, 0, "MMX_PMULUDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1193 = MMX_PMULUDQrm
+ { 1194, 3, 1, 0, "MMX_PMULUDQrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1194 = MMX_PMULUDQrr
+ { 1195, 7, 1, 0, "MMX_PORrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1195 = MMX_PORrm
+ { 1196, 3, 1, 0, "MMX_PORrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1196 = MMX_PORrr
+ { 1197, 7, 1, 0, "MMX_PSADBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1197 = MMX_PSADBWrm
+ { 1198, 3, 1, 0, "MMX_PSADBWrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1198 = MMX_PSADBWrr
+ { 1199, 7, 1, 0, "MMX_PSHUFWmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo141 }, // Inst #1199 = MMX_PSHUFWmi
+ { 1200, 3, 1, 0, "MMX_PSHUFWri", 0, 0|5|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo142 }, // Inst #1200 = MMX_PSHUFWri
+ { 1201, 3, 1, 0, "MMX_PSLLDri", 0, 0|22|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1201 = MMX_PSLLDri
+ { 1202, 7, 1, 0, "MMX_PSLLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1202 = MMX_PSLLDrm
+ { 1203, 3, 1, 0, "MMX_PSLLDrr", 0, 0|5|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1203 = MMX_PSLLDrr
+ { 1204, 3, 1, 0, "MMX_PSLLQri", 0, 0|22|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1204 = MMX_PSLLQri
+ { 1205, 7, 1, 0, "MMX_PSLLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1205 = MMX_PSLLQrm
+ { 1206, 3, 1, 0, "MMX_PSLLQrr", 0, 0|5|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1206 = MMX_PSLLQrr
+ { 1207, 3, 1, 0, "MMX_PSLLWri", 0, 0|22|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1207 = MMX_PSLLWri
+ { 1208, 7, 1, 0, "MMX_PSLLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1208 = MMX_PSLLWrm
+ { 1209, 3, 1, 0, "MMX_PSLLWrr", 0, 0|5|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1209 = MMX_PSLLWrr
+ { 1210, 3, 1, 0, "MMX_PSRADri", 0, 0|20|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1210 = MMX_PSRADri
+ { 1211, 7, 1, 0, "MMX_PSRADrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1211 = MMX_PSRADrm
+ { 1212, 3, 1, 0, "MMX_PSRADrr", 0, 0|5|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1212 = MMX_PSRADrr
+ { 1213, 3, 1, 0, "MMX_PSRAWri", 0, 0|20|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1213 = MMX_PSRAWri
+ { 1214, 7, 1, 0, "MMX_PSRAWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1214 = MMX_PSRAWrm
+ { 1215, 3, 1, 0, "MMX_PSRAWrr", 0, 0|5|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1215 = MMX_PSRAWrr
+ { 1216, 3, 1, 0, "MMX_PSRLDri", 0, 0|18|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1216 = MMX_PSRLDri
+ { 1217, 7, 1, 0, "MMX_PSRLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1217 = MMX_PSRLDrm
+ { 1218, 3, 1, 0, "MMX_PSRLDrr", 0, 0|5|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1218 = MMX_PSRLDrr
+ { 1219, 3, 1, 0, "MMX_PSRLQri", 0, 0|18|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1219 = MMX_PSRLQri
+ { 1220, 7, 1, 0, "MMX_PSRLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1220 = MMX_PSRLQrm
+ { 1221, 3, 1, 0, "MMX_PSRLQrr", 0, 0|5|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1221 = MMX_PSRLQrr
+ { 1222, 3, 1, 0, "MMX_PSRLWri", 0, 0|18|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo143 }, // Inst #1222 = MMX_PSRLWri
+ { 1223, 7, 1, 0, "MMX_PSRLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1223 = MMX_PSRLWrm
+ { 1224, 3, 1, 0, "MMX_PSRLWrr", 0, 0|5|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1224 = MMX_PSRLWrr
+ { 1225, 7, 1, 0, "MMX_PSUBBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1225 = MMX_PSUBBrm
+ { 1226, 3, 1, 0, "MMX_PSUBBrr", 0, 0|5|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1226 = MMX_PSUBBrr
+ { 1227, 7, 1, 0, "MMX_PSUBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1227 = MMX_PSUBDrm
+ { 1228, 3, 1, 0, "MMX_PSUBDrr", 0, 0|5|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1228 = MMX_PSUBDrr
+ { 1229, 7, 1, 0, "MMX_PSUBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1229 = MMX_PSUBQrm
+ { 1230, 3, 1, 0, "MMX_PSUBQrr", 0, 0|5|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1230 = MMX_PSUBQrr
+ { 1231, 7, 1, 0, "MMX_PSUBSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1231 = MMX_PSUBSBrm
+ { 1232, 3, 1, 0, "MMX_PSUBSBrr", 0, 0|5|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1232 = MMX_PSUBSBrr
+ { 1233, 7, 1, 0, "MMX_PSUBSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1233 = MMX_PSUBSWrm
+ { 1234, 3, 1, 0, "MMX_PSUBSWrr", 0, 0|5|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1234 = MMX_PSUBSWrr
+ { 1235, 7, 1, 0, "MMX_PSUBUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1235 = MMX_PSUBUSBrm
+ { 1236, 3, 1, 0, "MMX_PSUBUSBrr", 0, 0|5|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1236 = MMX_PSUBUSBrr
+ { 1237, 7, 1, 0, "MMX_PSUBUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1237 = MMX_PSUBUSWrm
+ { 1238, 3, 1, 0, "MMX_PSUBUSWrr", 0, 0|5|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1238 = MMX_PSUBUSWrr
+ { 1239, 7, 1, 0, "MMX_PSUBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1239 = MMX_PSUBWrm
+ { 1240, 3, 1, 0, "MMX_PSUBWrr", 0, 0|5|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1240 = MMX_PSUBWrr
+ { 1241, 7, 1, 0, "MMX_PUNPCKHBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1241 = MMX_PUNPCKHBWrm
+ { 1242, 3, 1, 0, "MMX_PUNPCKHBWrr", 0, 0|5|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1242 = MMX_PUNPCKHBWrr
+ { 1243, 7, 1, 0, "MMX_PUNPCKHDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1243 = MMX_PUNPCKHDQrm
+ { 1244, 3, 1, 0, "MMX_PUNPCKHDQrr", 0, 0|5|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1244 = MMX_PUNPCKHDQrr
+ { 1245, 7, 1, 0, "MMX_PUNPCKHWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1245 = MMX_PUNPCKHWDrm
+ { 1246, 3, 1, 0, "MMX_PUNPCKHWDrr", 0, 0|5|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1246 = MMX_PUNPCKHWDrr
+ { 1247, 7, 1, 0, "MMX_PUNPCKLBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1247 = MMX_PUNPCKLBWrm
+ { 1248, 3, 1, 0, "MMX_PUNPCKLBWrr", 0, 0|5|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1248 = MMX_PUNPCKLBWrr
+ { 1249, 7, 1, 0, "MMX_PUNPCKLDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1249 = MMX_PUNPCKLDQrm
+ { 1250, 3, 1, 0, "MMX_PUNPCKLDQrr", 0, 0|5|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1250 = MMX_PUNPCKLDQrr
+ { 1251, 7, 1, 0, "MMX_PUNPCKLWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1251 = MMX_PUNPCKLWDrm
+ { 1252, 3, 1, 0, "MMX_PUNPCKLWDrr", 0, 0|5|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1252 = MMX_PUNPCKLWDrr
+ { 1253, 7, 1, 0, "MMX_PXORrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1253 = MMX_PXORrm
+ { 1254, 3, 1, 0, "MMX_PXORrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1254 = MMX_PXORrr
+ { 1255, 1, 1, 0, "MMX_V_SET0", 0|(1<<TID::Rematerializable), 0|32|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo144 }, // Inst #1255 = MMX_V_SET0
+ { 1256, 1, 1, 0, "MMX_V_SETALLONES", 0|(1<<TID::Rematerializable), 0|32|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo144 }, // Inst #1256 = MMX_V_SETALLONES
+ { 1257, 0, 0, 0, "MONITOR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|37|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #1257 = MONITOR
+ { 1258, 1, 1, 0, "MOV16ao16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1258 = MOV16ao16
+ { 1259, 6, 0, 0, "MOV16mi", 0|(1<<TID::MayStore), 0|24|(1<<6)|(3<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1259 = MOV16mi
+ { 1260, 6, 0, 0, "MOV16mr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(137<<24), NULL, NULL, NULL, OperandInfo7 }, // Inst #1260 = MOV16mr
+ { 1261, 6, 1, 0, "MOV16ms", 0|(1<<TID::UnmodeledSideEffects), 0|4|(140<<24), NULL, NULL, NULL, OperandInfo145 }, // Inst #1261 = MOV16ms
+ { 1262, 1, 0, 0, "MOV16o16a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1262 = MOV16o16a
+ { 1263, 1, 1, 0, "MOV16r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo93 }, // Inst #1263 = MOV16r0
+ { 1264, 2, 1, 0, "MOV16ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<6)|(3<<13)|(184<<24), NULL, NULL, NULL, OperandInfo54 }, // Inst #1264 = MOV16ri
+ { 1265, 6, 1, 0, "MOV16rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<6)|(139<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1265 = MOV16rm
+ { 1266, 2, 1, 0, "MOV16rr", 0, 0|3|(1<<6)|(137<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1266 = MOV16rr
+ { 1267, 2, 1, 0, "MOV16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(139<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1267 = MOV16rr_REV
+ { 1268, 2, 1, 0, "MOV16rs", 0|(1<<TID::UnmodeledSideEffects), 0|3|(140<<24), NULL, NULL, NULL, OperandInfo146 }, // Inst #1268 = MOV16rs
+ { 1269, 6, 1, 0, "MOV16sm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(142<<24), NULL, NULL, NULL, OperandInfo147 }, // Inst #1269 = MOV16sm
+ { 1270, 2, 1, 0, "MOV16sr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(142<<24), NULL, NULL, NULL, OperandInfo148 }, // Inst #1270 = MOV16sr
+ { 1271, 1, 1, 0, "MOV32ao32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1271 = MOV32ao32
+ { 1272, 2, 1, 0, "MOV32cr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(34<<24), NULL, NULL, NULL, OperandInfo149 }, // Inst #1272 = MOV32cr
+ { 1273, 2, 1, 0, "MOV32dr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(35<<24), NULL, NULL, NULL, OperandInfo150 }, // Inst #1273 = MOV32dr
+ { 1274, 6, 0, 0, "MOV32mi", 0|(1<<TID::MayStore), 0|24|(4<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1274 = MOV32mi
+ { 1275, 6, 0, 0, "MOV32mr", 0|(1<<TID::MayStore), 0|4|(137<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #1275 = MOV32mr
+ { 1276, 1, 0, 0, "MOV32o32a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1276 = MOV32o32a
+ { 1277, 1, 1, 0, "MOV32r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo57 }, // Inst #1277 = MOV32r0
+ { 1278, 2, 1, 0, "MOV32rc", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(32<<24), NULL, NULL, NULL, OperandInfo151 }, // Inst #1278 = MOV32rc
+ { 1279, 2, 1, 0, "MOV32rd", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(33<<24), NULL, NULL, NULL, OperandInfo152 }, // Inst #1279 = MOV32rd
+ { 1280, 2, 1, 0, "MOV32ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(4<<13)|(184<<24), NULL, NULL, NULL, OperandInfo55 }, // Inst #1280 = MOV32ri
+ { 1281, 6, 1, 0, "MOV32rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(139<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1281 = MOV32rm
+ { 1282, 2, 1, 0, "MOV32rr", 0, 0|3|(137<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1282 = MOV32rr
+ { 1283, 2, 1, 0, "MOV32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(139<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1283 = MOV32rr_REV
+ { 1284, 6, 1, 0, "MOV64FSrm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(1<<20)|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1284 = MOV64FSrm
+ { 1285, 6, 1, 0, "MOV64GSrm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(2<<20)|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1285 = MOV64GSrm
+ { 1286, 1, 1, 0, "MOV64ao64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(4<<13)|(163<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1286 = MOV64ao64
+ { 1287, 1, 1, 0, "MOV64ao8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(1<<13)|(162<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1287 = MOV64ao8
+ { 1288, 2, 1, 0, "MOV64cr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(34<<24), NULL, NULL, NULL, OperandInfo153 }, // Inst #1288 = MOV64cr
+ { 1289, 2, 1, 0, "MOV64dr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(35<<24), NULL, NULL, NULL, OperandInfo154 }, // Inst #1289 = MOV64dr
+ { 1290, 6, 0, 0, "MOV64mi32", 0|(1<<TID::MayStore), 0|24|(1<<12)|(4<<13)|(199<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1290 = MOV64mi32
+ { 1291, 6, 0, 0, "MOV64mr", 0|(1<<TID::MayStore), 0|4|(1<<12)|(137<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #1291 = MOV64mr
+ { 1292, 6, 1, 0, "MOV64ms", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<12)|(140<<24), NULL, NULL, NULL, OperandInfo145 }, // Inst #1292 = MOV64ms
+ { 1293, 1, 0, 0, "MOV64o64a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(4<<13)|(161<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1293 = MOV64o64a
+ { 1294, 1, 0, 0, "MOV64o8a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(1<<13)|(160<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1294 = MOV64o8a
+ { 1295, 1, 1, 0, "MOV64r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo58 }, // Inst #1295 = MOV64r0
+ { 1296, 2, 1, 0, "MOV64rc", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(32<<24), NULL, NULL, NULL, OperandInfo155 }, // Inst #1296 = MOV64rc
+ { 1297, 2, 1, 0, "MOV64rd", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(33<<24), NULL, NULL, NULL, OperandInfo156 }, // Inst #1297 = MOV64rd
+ { 1298, 2, 1, 0, "MOV64ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<12)|(6<<13)|(184<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #1298 = MOV64ri
+ { 1299, 2, 1, 0, "MOV64ri32", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|16|(1<<12)|(4<<13)|(199<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #1299 = MOV64ri32
+ { 1300, 2, 1, 0, "MOV64ri64i32", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(4<<13)|(184<<24), NULL, NULL, NULL, OperandInfo56 }, // Inst #1300 = MOV64ri64i32
+ { 1301, 6, 1, 0, "MOV64rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<12)|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1301 = MOV64rm
+ { 1302, 2, 1, 0, "MOV64rr", 0, 0|3|(1<<12)|(137<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1302 = MOV64rr
+ { 1303, 2, 1, 0, "MOV64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(139<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1303 = MOV64rr_REV
+ { 1304, 2, 1, 0, "MOV64rs", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<12)|(140<<24), NULL, NULL, NULL, OperandInfo157 }, // Inst #1304 = MOV64rs
+ { 1305, 6, 1, 0, "MOV64sm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<12)|(142<<24), NULL, NULL, NULL, OperandInfo147 }, // Inst #1305 = MOV64sm
+ { 1306, 2, 1, 0, "MOV64sr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(142<<24), NULL, NULL, NULL, OperandInfo158 }, // Inst #1306 = MOV64sr
+ { 1307, 2, 1, 0, "MOV64toPQIrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo159 }, // Inst #1307 = MOV64toPQIrr
+ { 1308, 6, 1, 0, "MOV64toSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #1308 = MOV64toSDrm
+ { 1309, 2, 1, 0, "MOV64toSDrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo83 }, // Inst #1309 = MOV64toSDrr
+ { 1310, 1, 1, 0, "MOV8ao8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(162<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1310 = MOV8ao8
+ { 1311, 6, 0, 0, "MOV8mi", 0|(1<<TID::MayStore), 0|24|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo6 }, // Inst #1311 = MOV8mi
+ { 1312, 6, 0, 0, "MOV8mr", 0|(1<<TID::MayStore), 0|4|(136<<24), NULL, NULL, NULL, OperandInfo20 }, // Inst #1312 = MOV8mr
+ { 1313, 6, 0, 0, "MOV8mr_NOREX", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(136<<24), NULL, NULL, NULL, OperandInfo160 }, // Inst #1313 = MOV8mr_NOREX
+ { 1314, 1, 0, 0, "MOV8o8a", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(160<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1314 = MOV8o8a
+ { 1315, 1, 1, 0, "MOV8r0", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo94 }, // Inst #1315 = MOV8r0
+ { 1316, 2, 1, 0, "MOV8ri", 0|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|2|(1<<13)|(176<<24), NULL, NULL, NULL, OperandInfo68 }, // Inst #1316 = MOV8ri
+ { 1317, 6, 1, 0, "MOV8rm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(138<<24), NULL, NULL, NULL, OperandInfo69 }, // Inst #1317 = MOV8rm
+ { 1318, 6, 1, 0, "MOV8rm_NOREX", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable)|(1<<TID::UnmodeledSideEffects), 0|6|(138<<24), NULL, NULL, NULL, OperandInfo161 }, // Inst #1318 = MOV8rm_NOREX
+ { 1319, 2, 1, 0, "MOV8rr", 0, 0|3|(136<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #1319 = MOV8rr
+ { 1320, 2, 1, 0, "MOV8rr_NOREX", 0, 0|3|(136<<24), NULL, NULL, NULL, OperandInfo162 }, // Inst #1320 = MOV8rr_NOREX
+ { 1321, 2, 1, 0, "MOV8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(138<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #1321 = MOV8rr_REV
+ { 1322, 6, 0, 0, "MOVAPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(41<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1322 = MOVAPDmr
+ { 1323, 6, 1, 0, "MOVAPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1323 = MOVAPDrm
+ { 1324, 2, 1, 0, "MOVAPDrr", 0, 0|5|(1<<6)|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1324 = MOVAPDrr
+ { 1325, 6, 0, 0, "MOVAPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(41<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1325 = MOVAPSmr
+ { 1326, 6, 1, 0, "MOVAPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1326 = MOVAPSrm
+ { 1327, 2, 1, 0, "MOVAPSrr", 0, 0|5|(1<<8)|(40<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1327 = MOVAPSrr
+ { 1328, 6, 1, 0, "MOVDDUPrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(18<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1328 = MOVDDUPrm
+ { 1329, 2, 1, 0, "MOVDDUPrr", 0, 0|5|(11<<8)|(18<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1329 = MOVDDUPrr
+ { 1330, 6, 1, 0, "MOVDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1330 = MOVDI2PDIrm
+ { 1331, 2, 1, 0, "MOVDI2PDIrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo164 }, // Inst #1331 = MOVDI2PDIrr
+ { 1332, 6, 1, 0, "MOVDI2SSrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1332 = MOVDI2SSrm
+ { 1333, 2, 1, 0, "MOVDI2SSrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo86 }, // Inst #1333 = MOVDI2SSrr
+ { 1334, 6, 0, 0, "MOVDQAmr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(127<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1334 = MOVDQAmr
+ { 1335, 6, 1, 0, "MOVDQArm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1335 = MOVDQArm
+ { 1336, 2, 1, 0, "MOVDQArr", 0, 0|5|(1<<6)|(1<<8)|(111<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1336 = MOVDQArr
+ { 1337, 6, 0, 0, "MOVDQUmr", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(12<<8)|(127<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1337 = MOVDQUmr
+ { 1338, 6, 0, 0, "MOVDQUmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(12<<8)|(127<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1338 = MOVDQUmr_Int
+ { 1339, 6, 1, 0, "MOVDQUrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(111<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1339 = MOVDQUrm
+ { 1340, 6, 1, 0, "MOVDQUrm_Int", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|6|(12<<8)|(111<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1340 = MOVDQUrm_Int
+ { 1341, 3, 1, 0, "MOVHLPSrr", 0, 0|5|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1341 = MOVHLPSrr
+ { 1342, 6, 0, 0, "MOVHPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(23<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1342 = MOVHPDmr
+ { 1343, 7, 1, 0, "MOVHPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1343 = MOVHPDrm
+ { 1344, 6, 0, 0, "MOVHPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(23<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1344 = MOVHPSmr
+ { 1345, 7, 1, 0, "MOVHPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1345 = MOVHPSrm
+ { 1346, 3, 1, 0, "MOVLHPSrr", 0, 0|5|(1<<8)|(22<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1346 = MOVLHPSrr
+ { 1347, 6, 0, 0, "MOVLPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(19<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1347 = MOVLPDmr
+ { 1348, 7, 1, 0, "MOVLPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1348 = MOVLPDrm
+ { 1349, 6, 0, 0, "MOVLPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(19<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1349 = MOVLPSmr
+ { 1350, 7, 1, 0, "MOVLPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(18<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1350 = MOVLPSrm
+ { 1351, 6, 0, 0, "MOVLQ128mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(214<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1351 = MOVLQ128mr
+ { 1352, 2, 1, 0, "MOVMSKPDrr", 0, 0|5|(1<<6)|(1<<8)|(80<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1352 = MOVMSKPDrr
+ { 1353, 2, 1, 0, "MOVMSKPSrr", 0, 0|5|(1<<8)|(80<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1353 = MOVMSKPSrr
+ { 1354, 6, 1, 0, "MOVNTDQArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(42<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1354 = MOVNTDQArm
+ { 1355, 6, 0, 0, "MOVNTDQ_64mr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1355 = MOVNTDQ_64mr
+ { 1356, 6, 0, 0, "MOVNTDQmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1356 = MOVNTDQmr
+ { 1357, 6, 0, 0, "MOVNTDQmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(231<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1357 = MOVNTDQmr_Int
+ { 1358, 6, 0, 0, "MOVNTI_64mr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(195<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #1358 = MOVNTI_64mr
+ { 1359, 6, 0, 0, "MOVNTImr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(195<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #1359 = MOVNTImr
+ { 1360, 6, 0, 0, "MOVNTImr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(195<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #1360 = MOVNTImr_Int
+ { 1361, 6, 0, 0, "MOVNTPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1361 = MOVNTPDmr
+ { 1362, 6, 0, 0, "MOVNTPDmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1362 = MOVNTPDmr_Int
+ { 1363, 6, 0, 0, "MOVNTPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1363 = MOVNTPSmr
+ { 1364, 6, 0, 0, "MOVNTPSmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(43<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1364 = MOVNTPSmr_Int
+ { 1365, 2, 1, 0, "MOVPC32r", 0|(1<<TID::NotDuplicable), 0|(4<<13)|(232<<24), ImplicitList2, NULL, NULL, OperandInfo55 }, // Inst #1365 = MOVPC32r
+ { 1366, 6, 0, 0, "MOVPDI2DImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1366 = MOVPDI2DImr
+ { 1367, 2, 1, 0, "MOVPDI2DIrr", 0, 0|3|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1367 = MOVPDI2DIrr
+ { 1368, 6, 0, 0, "MOVPQI2QImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(214<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1368 = MOVPQI2QImr
+ { 1369, 2, 1, 0, "MOVPQIto64rr", 0, 0|3|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo121 }, // Inst #1369 = MOVPQIto64rr
+ { 1370, 6, 1, 0, "MOVQI2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1370 = MOVQI2PQIrm
+ { 1371, 2, 1, 0, "MOVQxrxr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1371 = MOVQxrxr
+ { 1372, 0, 0, 0, "MOVSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(164<<24), ImplicitList37, ImplicitList38, NULL, 0 }, // Inst #1372 = MOVSB
+ { 1373, 0, 0, 0, "MOVSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(165<<24), ImplicitList37, ImplicitList38, NULL, 0 }, // Inst #1373 = MOVSD
+ { 1374, 6, 0, 0, "MOVSDmr", 0|(1<<TID::MayStore), 0|4|(11<<8)|(17<<24), NULL, NULL, NULL, OperandInfo165 }, // Inst #1374 = MOVSDmr
+ { 1375, 6, 1, 0, "MOVSDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #1375 = MOVSDrm
+ { 1376, 3, 1, 0, "MOVSDrr", 0, 0|5|(11<<8)|(16<<24), NULL, NULL, NULL, OperandInfo166 }, // Inst #1376 = MOVSDrr
+ { 1377, 6, 0, 0, "MOVSDto64mr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo165 }, // Inst #1377 = MOVSDto64mr
+ { 1378, 2, 1, 0, "MOVSDto64rr", 0, 0|3|(1<<6)|(1<<8)|(1<<12)|(126<<24), NULL, NULL, NULL, OperandInfo79 }, // Inst #1378 = MOVSDto64rr
+ { 1379, 6, 1, 0, "MOVSHDUPrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(22<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1379 = MOVSHDUPrm
+ { 1380, 2, 1, 0, "MOVSHDUPrr", 0, 0|5|(12<<8)|(22<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1380 = MOVSHDUPrr
+ { 1381, 6, 1, 0, "MOVSLDUPrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(18<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1381 = MOVSLDUPrm
+ { 1382, 2, 1, 0, "MOVSLDUPrr", 0, 0|5|(12<<8)|(18<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1382 = MOVSLDUPrr
+ { 1383, 6, 0, 0, "MOVSS2DImr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo167 }, // Inst #1383 = MOVSS2DImr
+ { 1384, 2, 1, 0, "MOVSS2DIrr", 0, 0|3|(1<<6)|(1<<8)|(126<<24), NULL, NULL, NULL, OperandInfo89 }, // Inst #1384 = MOVSS2DIrr
+ { 1385, 6, 0, 0, "MOVSSmr", 0|(1<<TID::MayStore), 0|4|(12<<8)|(17<<24), NULL, NULL, NULL, OperandInfo167 }, // Inst #1385 = MOVSSmr
+ { 1386, 6, 1, 0, "MOVSSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1386 = MOVSSrm
+ { 1387, 3, 1, 0, "MOVSSrr", 0, 0|5|(12<<8)|(16<<24), NULL, NULL, NULL, OperandInfo168 }, // Inst #1387 = MOVSSrr
+ { 1388, 0, 0, 0, "MOVSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(165<<24), ImplicitList37, ImplicitList38, NULL, 0 }, // Inst #1388 = MOVSW
+ { 1389, 6, 1, 0, "MOVSX16rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1389 = MOVSX16rm8
+ { 1390, 6, 1, 0, "MOVSX16rm8W", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1390 = MOVSX16rm8W
+ { 1391, 2, 1, 0, "MOVSX16rr8", 0, 0|5|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo169 }, // Inst #1391 = MOVSX16rr8
+ { 1392, 2, 1, 0, "MOVSX16rr8W", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo169 }, // Inst #1392 = MOVSX16rr8W
+ { 1393, 6, 1, 0, "MOVSX32rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(191<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1393 = MOVSX32rm16
+ { 1394, 6, 1, 0, "MOVSX32rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1394 = MOVSX32rm8
+ { 1395, 2, 1, 0, "MOVSX32rr16", 0, 0|5|(1<<8)|(191<<24), NULL, NULL, NULL, OperandInfo170 }, // Inst #1395 = MOVSX32rr16
+ { 1396, 2, 1, 0, "MOVSX32rr8", 0, 0|5|(1<<8)|(190<<24), NULL, NULL, NULL, OperandInfo171 }, // Inst #1396 = MOVSX32rr8
+ { 1397, 6, 1, 0, "MOVSX64rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(191<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1397 = MOVSX64rm16
+ { 1398, 6, 1, 0, "MOVSX64rm32", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(99<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1398 = MOVSX64rm32
+ { 1399, 6, 1, 0, "MOVSX64rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<12)|(190<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1399 = MOVSX64rm8
+ { 1400, 2, 1, 0, "MOVSX64rr16", 0, 0|5|(1<<8)|(1<<12)|(191<<24), NULL, NULL, NULL, OperandInfo172 }, // Inst #1400 = MOVSX64rr16
+ { 1401, 2, 1, 0, "MOVSX64rr32", 0, 0|5|(1<<12)|(99<<24), NULL, NULL, NULL, OperandInfo125 }, // Inst #1401 = MOVSX64rr32
+ { 1402, 2, 1, 0, "MOVSX64rr8", 0, 0|5|(1<<8)|(1<<12)|(190<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1402 = MOVSX64rr8
+ { 1403, 6, 0, 0, "MOVUPDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1403 = MOVUPDmr
+ { 1404, 6, 0, 0, "MOVUPDmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1404 = MOVUPDmr_Int
+ { 1405, 6, 1, 0, "MOVUPDrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1405 = MOVUPDrm
+ { 1406, 6, 1, 0, "MOVUPDrm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1406 = MOVUPDrm_Int
+ { 1407, 2, 1, 0, "MOVUPDrr", 0, 0|5|(1<<6)|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1407 = MOVUPDrr
+ { 1408, 6, 0, 0, "MOVUPSmr", 0|(1<<TID::MayStore), 0|4|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1408 = MOVUPSmr
+ { 1409, 6, 0, 0, "MOVUPSmr_Int", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(17<<24), NULL, NULL, NULL, OperandInfo163 }, // Inst #1409 = MOVUPSmr_Int
+ { 1410, 6, 1, 0, "MOVUPSrm", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1410 = MOVUPSrm
+ { 1411, 6, 1, 0, "MOVUPSrm_Int", 0|(1<<TID::FoldableAsLoad)|(1<<TID::MayLoad)|(1<<TID::Rematerializable), 0|6|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1411 = MOVUPSrm_Int
+ { 1412, 2, 1, 0, "MOVUPSrr", 0, 0|5|(1<<8)|(16<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1412 = MOVUPSrr
+ { 1413, 6, 1, 0, "MOVZDI2PDIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1413 = MOVZDI2PDIrm
+ { 1414, 2, 1, 0, "MOVZDI2PDIrr", 0, 0|5|(1<<6)|(1<<8)|(110<<24), NULL, NULL, NULL, OperandInfo164 }, // Inst #1414 = MOVZDI2PDIrr
+ { 1415, 6, 1, 0, "MOVZPQILo2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1415 = MOVZPQILo2PQIrm
+ { 1416, 2, 1, 0, "MOVZPQILo2PQIrr", 0, 0|5|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1416 = MOVZPQILo2PQIrr
+ { 1417, 6, 1, 0, "MOVZQI2PQIrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(126<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1417 = MOVZQI2PQIrm
+ { 1418, 2, 1, 0, "MOVZQI2PQIrr", 0, 0|5|(1<<6)|(1<<8)|(1<<12)|(110<<24), NULL, NULL, NULL, OperandInfo159 }, // Inst #1418 = MOVZQI2PQIrr
+ { 1419, 6, 1, 0, "MOVZX16rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1419 = MOVZX16rm8
+ { 1420, 6, 1, 0, "MOVZX16rm8W", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1420 = MOVZX16rm8W
+ { 1421, 2, 1, 0, "MOVZX16rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo169 }, // Inst #1421 = MOVZX16rr8
+ { 1422, 2, 1, 0, "MOVZX16rr8W", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo169 }, // Inst #1422 = MOVZX16rr8W
+ { 1423, 6, 1, 0, "MOVZX32_NOREXrm8", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo174 }, // Inst #1423 = MOVZX32_NOREXrm8
+ { 1424, 2, 1, 0, "MOVZX32_NOREXrr8", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo175 }, // Inst #1424 = MOVZX32_NOREXrr8
+ { 1425, 6, 1, 0, "MOVZX32rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1425 = MOVZX32rm16
+ { 1426, 6, 1, 0, "MOVZX32rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1426 = MOVZX32rm8
+ { 1427, 2, 1, 0, "MOVZX32rr16", 0, 0|5|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo170 }, // Inst #1427 = MOVZX32rr16
+ { 1428, 2, 1, 0, "MOVZX32rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo171 }, // Inst #1428 = MOVZX32rr8
+ { 1429, 6, 1, 0, "MOVZX64rm16", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1429 = MOVZX64rm16
+ { 1430, 6, 1, 0, "MOVZX64rm16_Q", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(183<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1430 = MOVZX64rm16_Q
+ { 1431, 6, 1, 0, "MOVZX64rm32", 0|(1<<TID::MayLoad), 0|6|(139<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1431 = MOVZX64rm32
+ { 1432, 6, 1, 0, "MOVZX64rm8", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1432 = MOVZX64rm8
+ { 1433, 6, 1, 0, "MOVZX64rm8_Q", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(1<<12)|(182<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1433 = MOVZX64rm8_Q
+ { 1434, 2, 1, 0, "MOVZX64rr16", 0, 0|5|(1<<8)|(183<<24), NULL, NULL, NULL, OperandInfo172 }, // Inst #1434 = MOVZX64rr16
+ { 1435, 2, 1, 0, "MOVZX64rr16_Q", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(183<<24), NULL, NULL, NULL, OperandInfo172 }, // Inst #1435 = MOVZX64rr16_Q
+ { 1436, 2, 1, 0, "MOVZX64rr32", 0, 0|3|(137<<24), NULL, NULL, NULL, OperandInfo125 }, // Inst #1436 = MOVZX64rr32
+ { 1437, 2, 1, 0, "MOVZX64rr8", 0, 0|5|(1<<8)|(182<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1437 = MOVZX64rr8
+ { 1438, 2, 1, 0, "MOVZX64rr8_Q", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(1<<12)|(182<<24), NULL, NULL, NULL, OperandInfo173 }, // Inst #1438 = MOVZX64rr8_Q
+ { 1439, 2, 1, 0, "MOV_Fp3232", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #1439 = MOV_Fp3232
+ { 1440, 2, 1, 0, "MOV_Fp3264", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo176 }, // Inst #1440 = MOV_Fp3264
+ { 1441, 2, 1, 0, "MOV_Fp3280", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo177 }, // Inst #1441 = MOV_Fp3280
+ { 1442, 2, 1, 0, "MOV_Fp6432", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo178 }, // Inst #1442 = MOV_Fp6432
+ { 1443, 2, 1, 0, "MOV_Fp6464", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #1443 = MOV_Fp6464
+ { 1444, 2, 1, 0, "MOV_Fp6480", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo179 }, // Inst #1444 = MOV_Fp6480
+ { 1445, 2, 1, 0, "MOV_Fp8032", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo180 }, // Inst #1445 = MOV_Fp8032
+ { 1446, 2, 1, 0, "MOV_Fp8064", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo181 }, // Inst #1446 = MOV_Fp8064
+ { 1447, 2, 1, 0, "MOV_Fp8080", 0, 0|(7<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #1447 = MOV_Fp8080
+ { 1448, 8, 1, 0, "MPSADBWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(66<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1448 = MPSADBWrmi
+ { 1449, 4, 1, 0, "MPSADBWrri", 0|(1<<TID::Commutable), 0|5|(1<<6)|(14<<8)|(1<<13)|(66<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1449 = MPSADBWrri
+ { 1450, 5, 0, 0, "MUL16m", 0|(1<<TID::MayLoad), 0|28|(1<<6)|(247<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo30 }, // Inst #1450 = MUL16m
+ { 1451, 1, 0, 0, "MUL16r", 0, 0|20|(1<<6)|(247<<24), ImplicitList12, ImplicitList21, Barriers1, OperandInfo93 }, // Inst #1451 = MUL16r
+ { 1452, 5, 0, 0, "MUL32m", 0|(1<<TID::MayLoad), 0|28|(247<<24), ImplicitList13, ImplicitList18, Barriers6, OperandInfo30 }, // Inst #1452 = MUL32m
+ { 1453, 1, 0, 0, "MUL32r", 0, 0|20|(247<<24), ImplicitList13, ImplicitList18, Barriers6, OperandInfo57 }, // Inst #1453 = MUL32r
+ { 1454, 5, 0, 0, "MUL64m", 0|(1<<TID::MayLoad), 0|28|(1<<12)|(247<<24), ImplicitList15, ImplicitList17, Barriers1, OperandInfo30 }, // Inst #1454 = MUL64m
+ { 1455, 1, 0, 0, "MUL64r", 0, 0|20|(1<<12)|(247<<24), ImplicitList15, ImplicitList17, Barriers1, OperandInfo58 }, // Inst #1455 = MUL64r
+ { 1456, 5, 0, 0, "MUL8m", 0|(1<<TID::MayLoad), 0|28|(246<<24), ImplicitList11, ImplicitList22, Barriers1, OperandInfo30 }, // Inst #1456 = MUL8m
+ { 1457, 1, 0, 0, "MUL8r", 0, 0|20|(246<<24), ImplicitList11, ImplicitList22, Barriers1, OperandInfo94 }, // Inst #1457 = MUL8r
+ { 1458, 7, 1, 0, "MULPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1458 = MULPDrm
+ { 1459, 3, 1, 0, "MULPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1459 = MULPDrr
+ { 1460, 7, 1, 0, "MULPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1460 = MULPSrm
+ { 1461, 3, 1, 0, "MULPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1461 = MULPSrr
+ { 1462, 7, 1, 0, "MULSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #1462 = MULSDrm
+ { 1463, 7, 1, 0, "MULSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1463 = MULSDrm_Int
+ { 1464, 3, 1, 0, "MULSDrr", 0|(1<<TID::Commutable), 0|5|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #1464 = MULSDrr
+ { 1465, 3, 1, 0, "MULSDrr_Int", 0, 0|5|(11<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1465 = MULSDrr_Int
+ { 1466, 7, 1, 0, "MULSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #1466 = MULSSrm
+ { 1467, 7, 1, 0, "MULSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1467 = MULSSrm_Int
+ { 1468, 3, 1, 0, "MULSSrr", 0|(1<<TID::Commutable), 0|5|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #1468 = MULSSrr
+ { 1469, 3, 1, 0, "MULSSrr_Int", 0, 0|5|(12<<8)|(89<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1469 = MULSSrr_Int
+ { 1470, 5, 0, 0, "MUL_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1470 = MUL_F32m
+ { 1471, 5, 0, 0, "MUL_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1471 = MUL_F64m
+ { 1472, 5, 0, 0, "MUL_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1472 = MUL_FI16m
+ { 1473, 5, 0, 0, "MUL_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|25|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1473 = MUL_FI32m
+ { 1474, 1, 0, 0, "MUL_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1474 = MUL_FPrST0
+ { 1475, 1, 0, 0, "MUL_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1475 = MUL_FST0r
+ { 1476, 3, 1, 0, "MUL_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #1476 = MUL_Fp32
+ { 1477, 7, 1, 0, "MUL_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1477 = MUL_Fp32m
+ { 1478, 3, 1, 0, "MUL_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #1478 = MUL_Fp64
+ { 1479, 7, 1, 0, "MUL_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1479 = MUL_Fp64m
+ { 1480, 7, 1, 0, "MUL_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1480 = MUL_Fp64m32
+ { 1481, 3, 1, 0, "MUL_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #1481 = MUL_Fp80
+ { 1482, 7, 1, 0, "MUL_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1482 = MUL_Fp80m32
+ { 1483, 7, 1, 0, "MUL_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1483 = MUL_Fp80m64
+ { 1484, 7, 1, 0, "MUL_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1484 = MUL_FpI16m32
+ { 1485, 7, 1, 0, "MUL_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1485 = MUL_FpI16m64
+ { 1486, 7, 1, 0, "MUL_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1486 = MUL_FpI16m80
+ { 1487, 7, 1, 0, "MUL_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #1487 = MUL_FpI32m32
+ { 1488, 7, 1, 0, "MUL_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #1488 = MUL_FpI32m64
+ { 1489, 7, 1, 0, "MUL_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #1489 = MUL_FpI32m80
+ { 1490, 1, 0, 0, "MUL_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #1490 = MUL_FrST0
+ { 1491, 0, 0, 0, "MWAIT", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|38|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #1491 = MWAIT
+ { 1492, 5, 0, 0, "NEG16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1492 = NEG16m
+ { 1493, 2, 1, 0, "NEG16r", 0, 0|19|(1<<6)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1493 = NEG16r
+ { 1494, 5, 0, 0, "NEG32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1494 = NEG32m
+ { 1495, 2, 1, 0, "NEG32r", 0, 0|19|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1495 = NEG32r
+ { 1496, 5, 0, 0, "NEG64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1496 = NEG64m
+ { 1497, 2, 1, 0, "NEG64r", 0, 0|19|(1<<12)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1497 = NEG64r
+ { 1498, 5, 0, 0, "NEG8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1498 = NEG8m
+ { 1499, 2, 1, 0, "NEG8r", 0, 0|19|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1499 = NEG8r
+ { 1500, 0, 0, 0, "NOOP", 0, 0|1|(144<<24), NULL, NULL, NULL, 0 }, // Inst #1500 = NOOP
+ { 1501, 5, 0, 0, "NOOPL", 0, 0|24|(1<<8)|(31<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1501 = NOOPL
+ { 1502, 5, 0, 0, "NOOPW", 0, 0|24|(1<<6)|(1<<8)|(31<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1502 = NOOPW
+ { 1503, 5, 0, 0, "NOT16m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<6)|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1503 = NOT16m
+ { 1504, 2, 1, 0, "NOT16r", 0, 0|18|(1<<6)|(247<<24), NULL, NULL, NULL, OperandInfo91 }, // Inst #1504 = NOT16r
+ { 1505, 5, 0, 0, "NOT32m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1505 = NOT32m
+ { 1506, 2, 1, 0, "NOT32r", 0, 0|18|(247<<24), NULL, NULL, NULL, OperandInfo52 }, // Inst #1506 = NOT32r
+ { 1507, 5, 0, 0, "NOT64m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<12)|(247<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1507 = NOT64m
+ { 1508, 2, 1, 0, "NOT64r", 0, 0|18|(1<<12)|(247<<24), NULL, NULL, NULL, OperandInfo53 }, // Inst #1508 = NOT64r
+ { 1509, 5, 0, 0, "NOT8m", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(246<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1509 = NOT8m
+ { 1510, 2, 1, 0, "NOT8r", 0, 0|18|(246<<24), NULL, NULL, NULL, OperandInfo92 }, // Inst #1510 = NOT8r
+ { 1511, 1, 0, 0, "OR16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1511 = OR16i16
+ { 1512, 6, 0, 0, "OR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1512 = OR16mi
+ { 1513, 6, 0, 0, "OR16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1513 = OR16mi8
+ { 1514, 6, 0, 0, "OR16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #1514 = OR16mr
+ { 1515, 3, 1, 0, "OR16ri", 0, 0|17|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1515 = OR16ri
+ { 1516, 3, 1, 0, "OR16ri8", 0, 0|17|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1516 = OR16ri8
+ { 1517, 7, 1, 0, "OR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #1517 = OR16rm
+ { 1518, 3, 1, 0, "OR16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #1518 = OR16rr
+ { 1519, 3, 1, 0, "OR16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #1519 = OR16rr_REV
+ { 1520, 1, 0, 0, "OR32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1520 = OR32i32
+ { 1521, 6, 0, 0, "OR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1521 = OR32mi
+ { 1522, 6, 0, 0, "OR32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1522 = OR32mi8
+ { 1523, 6, 0, 0, "OR32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #1523 = OR32mr
+ { 1524, 3, 1, 0, "OR32ri", 0, 0|17|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1524 = OR32ri
+ { 1525, 3, 1, 0, "OR32ri8", 0, 0|17|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1525 = OR32ri8
+ { 1526, 7, 1, 0, "OR32rm", 0|(1<<TID::MayLoad), 0|6|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #1526 = OR32rm
+ { 1527, 3, 1, 0, "OR32rr", 0|(1<<TID::Commutable), 0|3|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #1527 = OR32rr
+ { 1528, 3, 1, 0, "OR32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #1528 = OR32rr_REV
+ { 1529, 1, 0, 0, "OR64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(4<<13)|(13<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1529 = OR64i32
+ { 1530, 6, 0, 0, "OR64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1530 = OR64mi32
+ { 1531, 6, 0, 0, "OR64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1531 = OR64mi8
+ { 1532, 6, 0, 0, "OR64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #1532 = OR64mr
+ { 1533, 3, 1, 0, "OR64ri32", 0, 0|17|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1533 = OR64ri32
+ { 1534, 3, 1, 0, "OR64ri8", 0, 0|17|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1534 = OR64ri8
+ { 1535, 7, 1, 0, "OR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #1535 = OR64rm
+ { 1536, 3, 1, 0, "OR64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(9<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #1536 = OR64rr
+ { 1537, 3, 1, 0, "OR64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(11<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #1537 = OR64rr_REV
+ { 1538, 1, 0, 0, "OR8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(12<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #1538 = OR8i8
+ { 1539, 6, 0, 0, "OR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1539 = OR8mi
+ { 1540, 6, 0, 0, "OR8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(8<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #1540 = OR8mr
+ { 1541, 3, 1, 0, "OR8ri", 0, 0|17|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1541 = OR8ri
+ { 1542, 7, 1, 0, "OR8rm", 0|(1<<TID::MayLoad), 0|6|(10<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #1542 = OR8rm
+ { 1543, 3, 1, 0, "OR8rr", 0|(1<<TID::Commutable), 0|3|(8<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #1543 = OR8rr
+ { 1544, 3, 1, 0, "OR8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(10<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #1544 = OR8rr_REV
+ { 1545, 7, 1, 0, "ORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1545 = ORPDrm
+ { 1546, 3, 1, 0, "ORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1546 = ORPDrr
+ { 1547, 7, 1, 0, "ORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1547 = ORPSrm
+ { 1548, 3, 1, 0, "ORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(86<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1548 = ORPSrr
+ { 1549, 1, 0, 0, "OUT16ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<13)|(231<<24), ImplicitList12, NULL, NULL, OperandInfo5 }, // Inst #1549 = OUT16ir
+ { 1550, 0, 0, 0, "OUT16rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(239<<24), ImplicitList39, NULL, NULL, 0 }, // Inst #1550 = OUT16rr
+ { 1551, 1, 0, 0, "OUT32ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(231<<24), ImplicitList13, NULL, NULL, OperandInfo5 }, // Inst #1551 = OUT32ir
+ { 1552, 0, 0, 0, "OUT32rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(239<<24), ImplicitList40, NULL, NULL, 0 }, // Inst #1552 = OUT32rr
+ { 1553, 1, 0, 0, "OUT8ir", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(230<<24), ImplicitList11, NULL, NULL, OperandInfo5 }, // Inst #1553 = OUT8ir
+ { 1554, 0, 0, 0, "OUT8rr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(238<<24), ImplicitList41, NULL, NULL, 0 }, // Inst #1554 = OUT8rr
+ { 1555, 0, 0, 0, "OUTSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(110<<24), NULL, NULL, NULL, 0 }, // Inst #1555 = OUTSB
+ { 1556, 0, 0, 0, "OUTSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(111<<24), NULL, NULL, NULL, 0 }, // Inst #1556 = OUTSD
+ { 1557, 0, 0, 0, "OUTSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(111<<24), NULL, NULL, NULL, 0 }, // Inst #1557 = OUTSW
+ { 1558, 6, 1, 0, "PABSBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1558 = PABSBrm128
+ { 1559, 6, 1, 0, "PABSBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1559 = PABSBrm64
+ { 1560, 2, 1, 0, "PABSBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1560 = PABSBrr128
+ { 1561, 2, 1, 0, "PABSBrr64", 0, 0|5|(13<<8)|(1<<13)|(28<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1561 = PABSBrr64
+ { 1562, 6, 1, 0, "PABSDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1562 = PABSDrm128
+ { 1563, 6, 1, 0, "PABSDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1563 = PABSDrm64
+ { 1564, 2, 1, 0, "PABSDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1564 = PABSDrr128
+ { 1565, 2, 1, 0, "PABSDrr64", 0, 0|5|(13<<8)|(1<<13)|(30<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1565 = PABSDrr64
+ { 1566, 6, 1, 0, "PABSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1566 = PABSWrm128
+ { 1567, 6, 1, 0, "PABSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo117 }, // Inst #1567 = PABSWrm64
+ { 1568, 2, 1, 0, "PABSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1568 = PABSWrr128
+ { 1569, 2, 1, 0, "PABSWrr64", 0, 0|5|(13<<8)|(1<<13)|(29<<24), NULL, NULL, NULL, OperandInfo129 }, // Inst #1569 = PABSWrr64
+ { 1570, 7, 1, 0, "PACKSSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1570 = PACKSSDWrm
+ { 1571, 3, 1, 0, "PACKSSDWrr", 0, 0|5|(1<<6)|(1<<8)|(107<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1571 = PACKSSDWrr
+ { 1572, 7, 1, 0, "PACKSSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1572 = PACKSSWBrm
+ { 1573, 3, 1, 0, "PACKSSWBrr", 0, 0|5|(1<<6)|(1<<8)|(99<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1573 = PACKSSWBrr
+ { 1574, 7, 1, 0, "PACKUSDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(43<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1574 = PACKUSDWrm
+ { 1575, 3, 1, 0, "PACKUSDWrr", 0, 0|5|(1<<6)|(13<<8)|(43<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1575 = PACKUSDWrr
+ { 1576, 7, 1, 0, "PACKUSWBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1576 = PACKUSWBrm
+ { 1577, 3, 1, 0, "PACKUSWBrr", 0, 0|5|(1<<6)|(1<<8)|(103<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1577 = PACKUSWBrr
+ { 1578, 7, 1, 0, "PADDBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1578 = PADDBrm
+ { 1579, 3, 1, 0, "PADDBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(252<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1579 = PADDBrr
+ { 1580, 7, 1, 0, "PADDDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1580 = PADDDrm
+ { 1581, 3, 1, 0, "PADDDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(254<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1581 = PADDDrr
+ { 1582, 7, 1, 0, "PADDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1582 = PADDQrm
+ { 1583, 3, 1, 0, "PADDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(212<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1583 = PADDQrr
+ { 1584, 7, 1, 0, "PADDSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1584 = PADDSBrm
+ { 1585, 3, 1, 0, "PADDSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(236<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1585 = PADDSBrr
+ { 1586, 7, 1, 0, "PADDSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1586 = PADDSWrm
+ { 1587, 3, 1, 0, "PADDSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(237<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1587 = PADDSWrr
+ { 1588, 7, 1, 0, "PADDUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1588 = PADDUSBrm
+ { 1589, 3, 1, 0, "PADDUSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(220<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1589 = PADDUSBrr
+ { 1590, 7, 1, 0, "PADDUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1590 = PADDUSWrm
+ { 1591, 3, 1, 0, "PADDUSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(221<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1591 = PADDUSWrr
+ { 1592, 7, 1, 0, "PADDWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1592 = PADDWrm
+ { 1593, 3, 1, 0, "PADDWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(253<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1593 = PADDWrr
+ { 1594, 8, 1, 0, "PALIGNR128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1594 = PALIGNR128rm
+ { 1595, 4, 1, 0, "PALIGNR128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1595 = PALIGNR128rr
+ { 1596, 8, 1, 0, "PALIGNR64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo139 }, // Inst #1596 = PALIGNR64rm
+ { 1597, 4, 1, 0, "PALIGNR64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(14<<8)|(1<<13)|(15<<24), NULL, NULL, NULL, OperandInfo182 }, // Inst #1597 = PALIGNR64rr
+ { 1598, 7, 1, 0, "PANDNrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1598 = PANDNrm
+ { 1599, 3, 1, 0, "PANDNrr", 0, 0|5|(1<<6)|(1<<8)|(223<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1599 = PANDNrr
+ { 1600, 7, 1, 0, "PANDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1600 = PANDrm
+ { 1601, 3, 1, 0, "PANDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(219<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1601 = PANDrr
+ { 1602, 7, 1, 0, "PAVGBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1602 = PAVGBrm
+ { 1603, 3, 1, 0, "PAVGBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(224<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1603 = PAVGBrr
+ { 1604, 7, 1, 0, "PAVGWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1604 = PAVGWrm
+ { 1605, 3, 1, 0, "PAVGWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(227<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1605 = PAVGWrr
+ { 1606, 7, 1, 0, "PBLENDVBrm0", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(16<<24), ImplicitList8, NULL, NULL, OperandInfo24 }, // Inst #1606 = PBLENDVBrm0
+ { 1607, 3, 1, 0, "PBLENDVBrr0", 0, 0|5|(1<<6)|(13<<8)|(16<<24), ImplicitList8, NULL, NULL, OperandInfo25 }, // Inst #1607 = PBLENDVBrr0
+ { 1608, 8, 1, 0, "PBLENDWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(14<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1608 = PBLENDWrmi
+ { 1609, 4, 1, 0, "PBLENDWrri", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(14<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #1609 = PBLENDWrri
+ { 1610, 7, 1, 0, "PCMPEQBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1610 = PCMPEQBrm
+ { 1611, 3, 1, 0, "PCMPEQBrr", 0, 0|5|(1<<6)|(1<<8)|(116<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1611 = PCMPEQBrr
+ { 1612, 7, 1, 0, "PCMPEQDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1612 = PCMPEQDrm
+ { 1613, 3, 1, 0, "PCMPEQDrr", 0, 0|5|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1613 = PCMPEQDrr
+ { 1614, 7, 1, 0, "PCMPEQQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(41<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1614 = PCMPEQQrm
+ { 1615, 3, 1, 0, "PCMPEQQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(41<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1615 = PCMPEQQrr
+ { 1616, 7, 1, 0, "PCMPEQWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1616 = PCMPEQWrm
+ { 1617, 3, 1, 0, "PCMPEQWrr", 0, 0|5|(1<<6)|(1<<8)|(117<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1617 = PCMPEQWrr
+ { 1618, 7, 0, 0, "PCMPESTRIArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1618 = PCMPESTRIArm
+ { 1619, 3, 0, 0, "PCMPESTRIArr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1619 = PCMPESTRIArr
+ { 1620, 7, 0, 0, "PCMPESTRICrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1620 = PCMPESTRICrm
+ { 1621, 3, 0, 0, "PCMPESTRICrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1621 = PCMPESTRICrr
+ { 1622, 7, 0, 0, "PCMPESTRIOrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1622 = PCMPESTRIOrm
+ { 1623, 3, 0, 0, "PCMPESTRIOrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1623 = PCMPESTRIOrr
+ { 1624, 7, 0, 0, "PCMPESTRISrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1624 = PCMPESTRISrm
+ { 1625, 3, 0, 0, "PCMPESTRISrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1625 = PCMPESTRISrr
+ { 1626, 7, 0, 0, "PCMPESTRIZrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1626 = PCMPESTRIZrm
+ { 1627, 3, 0, 0, "PCMPESTRIZrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1627 = PCMPESTRIZrr
+ { 1628, 7, 0, 0, "PCMPESTRIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1628 = PCMPESTRIrm
+ { 1629, 3, 0, 0, "PCMPESTRIrr", 0, 0|5|(1<<6)|(14<<8)|(97<<24), ImplicitList14, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1629 = PCMPESTRIrr
+ { 1630, 8, 1, 0, "PCMPESTRM128MEM", 0|(1<<TID::MayLoad)|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), ImplicitList14, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1630 = PCMPESTRM128MEM
+ { 1631, 4, 1, 0, "PCMPESTRM128REG", 0|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), ImplicitList14, ImplicitList1, Barriers1, OperandInfo66 }, // Inst #1631 = PCMPESTRM128REG
+ { 1632, 7, 0, 0, "PCMPESTRM128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(96<<24), ImplicitList14, ImplicitList43, Barriers1, OperandInfo183 }, // Inst #1632 = PCMPESTRM128rm
+ { 1633, 3, 0, 0, "PCMPESTRM128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(96<<24), ImplicitList14, ImplicitList43, Barriers1, OperandInfo184 }, // Inst #1633 = PCMPESTRM128rr
+ { 1634, 7, 1, 0, "PCMPGTBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1634 = PCMPGTBrm
+ { 1635, 3, 1, 0, "PCMPGTBrr", 0, 0|5|(1<<6)|(1<<8)|(100<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1635 = PCMPGTBrr
+ { 1636, 7, 1, 0, "PCMPGTDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1636 = PCMPGTDrm
+ { 1637, 3, 1, 0, "PCMPGTDrr", 0, 0|5|(1<<6)|(1<<8)|(102<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1637 = PCMPGTDrr
+ { 1638, 7, 1, 0, "PCMPGTQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(55<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1638 = PCMPGTQrm
+ { 1639, 3, 1, 0, "PCMPGTQrr", 0, 0|5|(1<<6)|(13<<8)|(55<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1639 = PCMPGTQrr
+ { 1640, 7, 1, 0, "PCMPGTWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1640 = PCMPGTWrm
+ { 1641, 3, 1, 0, "PCMPGTWrr", 0, 0|5|(1<<6)|(1<<8)|(101<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1641 = PCMPGTWrr
+ { 1642, 7, 0, 0, "PCMPISTRIArm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1642 = PCMPISTRIArm
+ { 1643, 3, 0, 0, "PCMPISTRIArr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1643 = PCMPISTRIArr
+ { 1644, 7, 0, 0, "PCMPISTRICrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1644 = PCMPISTRICrm
+ { 1645, 3, 0, 0, "PCMPISTRICrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1645 = PCMPISTRICrr
+ { 1646, 7, 0, 0, "PCMPISTRIOrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1646 = PCMPISTRIOrm
+ { 1647, 3, 0, 0, "PCMPISTRIOrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1647 = PCMPISTRIOrr
+ { 1648, 7, 0, 0, "PCMPISTRISrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1648 = PCMPISTRISrm
+ { 1649, 3, 0, 0, "PCMPISTRISrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1649 = PCMPISTRISrr
+ { 1650, 7, 0, 0, "PCMPISTRIZrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1650 = PCMPISTRIZrm
+ { 1651, 3, 0, 0, "PCMPISTRIZrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1651 = PCMPISTRIZrr
+ { 1652, 7, 0, 0, "PCMPISTRIrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo183 }, // Inst #1652 = PCMPISTRIrm
+ { 1653, 3, 0, 0, "PCMPISTRIrr", 0, 0|5|(1<<6)|(14<<8)|(99<<24), NULL, ImplicitList42, Barriers1, OperandInfo184 }, // Inst #1653 = PCMPISTRIrr
+ { 1654, 8, 1, 0, "PCMPISTRM128MEM", 0|(1<<TID::MayLoad)|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), NULL, ImplicitList1, Barriers1, OperandInfo185 }, // Inst #1654 = PCMPISTRM128MEM
+ { 1655, 4, 1, 0, "PCMPISTRM128REG", 0|(1<<TID::UsesCustomInserter), 0|(1<<6)|(14<<8), NULL, ImplicitList1, Barriers1, OperandInfo66 }, // Inst #1655 = PCMPISTRM128REG
+ { 1656, 7, 0, 0, "PCMPISTRM128rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(14<<8)|(98<<24), NULL, ImplicitList43, Barriers1, OperandInfo183 }, // Inst #1656 = PCMPISTRM128rm
+ { 1657, 3, 0, 0, "PCMPISTRM128rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(14<<8)|(98<<24), NULL, ImplicitList43, Barriers1, OperandInfo184 }, // Inst #1657 = PCMPISTRM128rr
+ { 1658, 7, 0, 0, "PEXTRBmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(14<<8)|(1<<13)|(20<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1658 = PEXTRBmr
+ { 1659, 3, 1, 0, "PEXTRBrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(20<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1659 = PEXTRBrr
+ { 1660, 7, 0, 0, "PEXTRDmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1660 = PEXTRDmr
+ { 1661, 3, 1, 0, "PEXTRDrr", 0, 0|3|(1<<6)|(14<<8)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1661 = PEXTRDrr
+ { 1662, 7, 0, 0, "PEXTRQmr", 0|(1<<TID::MayStore), 0|4|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1662 = PEXTRQmr
+ { 1663, 3, 1, 0, "PEXTRQrr", 0, 0|3|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(22<<24), NULL, NULL, NULL, OperandInfo186 }, // Inst #1663 = PEXTRQrr
+ { 1664, 7, 0, 0, "PEXTRWmr", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(14<<8)|(1<<13)|(21<<24), NULL, NULL, NULL, OperandInfo95 }, // Inst #1664 = PEXTRWmr
+ { 1665, 3, 1, 0, "PEXTRWri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(197<<24), NULL, NULL, NULL, OperandInfo96 }, // Inst #1665 = PEXTRWri
+ { 1666, 7, 1, 0, "PHADDDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1666 = PHADDDrm128
+ { 1667, 7, 1, 0, "PHADDDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1667 = PHADDDrm64
+ { 1668, 3, 1, 0, "PHADDDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1668 = PHADDDrr128
+ { 1669, 3, 1, 0, "PHADDDrr64", 0, 0|5|(13<<8)|(1<<13)|(2<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1669 = PHADDDrr64
+ { 1670, 7, 1, 0, "PHADDSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1670 = PHADDSWrm128
+ { 1671, 7, 1, 0, "PHADDSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1671 = PHADDSWrm64
+ { 1672, 3, 1, 0, "PHADDSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1672 = PHADDSWrr128
+ { 1673, 3, 1, 0, "PHADDSWrr64", 0, 0|5|(13<<8)|(1<<13)|(3<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1673 = PHADDSWrr64
+ { 1674, 7, 1, 0, "PHADDWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1674 = PHADDWrm128
+ { 1675, 7, 1, 0, "PHADDWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1675 = PHADDWrm64
+ { 1676, 3, 1, 0, "PHADDWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1676 = PHADDWrr128
+ { 1677, 3, 1, 0, "PHADDWrr64", 0, 0|5|(13<<8)|(1<<13)|(1<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1677 = PHADDWrr64
+ { 1678, 6, 1, 0, "PHMINPOSUWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(65<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1678 = PHMINPOSUWrm128
+ { 1679, 2, 1, 0, "PHMINPOSUWrr128", 0, 0|5|(1<<6)|(13<<8)|(65<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1679 = PHMINPOSUWrr128
+ { 1680, 7, 1, 0, "PHSUBDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1680 = PHSUBDrm128
+ { 1681, 7, 1, 0, "PHSUBDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1681 = PHSUBDrm64
+ { 1682, 3, 1, 0, "PHSUBDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1682 = PHSUBDrr128
+ { 1683, 3, 1, 0, "PHSUBDrr64", 0, 0|5|(13<<8)|(1<<13)|(6<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1683 = PHSUBDrr64
+ { 1684, 7, 1, 0, "PHSUBSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1684 = PHSUBSWrm128
+ { 1685, 7, 1, 0, "PHSUBSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1685 = PHSUBSWrm64
+ { 1686, 3, 1, 0, "PHSUBSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1686 = PHSUBSWrr128
+ { 1687, 3, 1, 0, "PHSUBSWrr64", 0, 0|5|(13<<8)|(1<<13)|(7<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1687 = PHSUBSWrr64
+ { 1688, 7, 1, 0, "PHSUBWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1688 = PHSUBWrm128
+ { 1689, 7, 1, 0, "PHSUBWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1689 = PHSUBWrm64
+ { 1690, 3, 1, 0, "PHSUBWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1690 = PHSUBWrr128
+ { 1691, 3, 1, 0, "PHSUBWrr64", 0, 0|5|(13<<8)|(1<<13)|(5<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1691 = PHSUBWrr64
+ { 1692, 8, 1, 0, "PINSRBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(32<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1692 = PINSRBrm
+ { 1693, 4, 1, 0, "PINSRBrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(32<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1693 = PINSRBrr
+ { 1694, 8, 1, 0, "PINSRDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1694 = PINSRDrm
+ { 1695, 4, 1, 0, "PINSRDrr", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1695 = PINSRDrr
+ { 1696, 8, 1, 0, "PINSRQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1696 = PINSRQrm
+ { 1697, 4, 1, 0, "PINSRQrr", 0, 0|5|(1<<6)|(14<<8)|(1<<12)|(1<<13)|(34<<24), NULL, NULL, NULL, OperandInfo188 }, // Inst #1697 = PINSRQrr
+ { 1698, 8, 1, 0, "PINSRWrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #1698 = PINSRWrmi
+ { 1699, 4, 1, 0, "PINSRWrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(196<<24), NULL, NULL, NULL, OperandInfo187 }, // Inst #1699 = PINSRWrri
+ { 1700, 7, 1, 0, "PMADDUBSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1700 = PMADDUBSWrm128
+ { 1701, 7, 1, 0, "PMADDUBSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1701 = PMADDUBSWrm64
+ { 1702, 3, 1, 0, "PMADDUBSWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1702 = PMADDUBSWrr128
+ { 1703, 3, 1, 0, "PMADDUBSWrr64", 0, 0|5|(13<<8)|(1<<13)|(4<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1703 = PMADDUBSWrr64
+ { 1704, 7, 1, 0, "PMADDWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1704 = PMADDWDrm
+ { 1705, 3, 1, 0, "PMADDWDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(245<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1705 = PMADDWDrr
+ { 1706, 7, 1, 0, "PMAXSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(60<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1706 = PMAXSBrm
+ { 1707, 3, 1, 0, "PMAXSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(60<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1707 = PMAXSBrr
+ { 1708, 7, 1, 0, "PMAXSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(61<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1708 = PMAXSDrm
+ { 1709, 3, 1, 0, "PMAXSDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(61<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1709 = PMAXSDrr
+ { 1710, 7, 1, 0, "PMAXSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1710 = PMAXSWrm
+ { 1711, 3, 1, 0, "PMAXSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(238<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1711 = PMAXSWrr
+ { 1712, 7, 1, 0, "PMAXUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1712 = PMAXUBrm
+ { 1713, 3, 1, 0, "PMAXUBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(222<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1713 = PMAXUBrr
+ { 1714, 7, 1, 0, "PMAXUDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(63<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1714 = PMAXUDrm
+ { 1715, 3, 1, 0, "PMAXUDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(63<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1715 = PMAXUDrr
+ { 1716, 7, 1, 0, "PMAXUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(62<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1716 = PMAXUWrm
+ { 1717, 3, 1, 0, "PMAXUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(62<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1717 = PMAXUWrr
+ { 1718, 7, 1, 0, "PMINSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(56<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1718 = PMINSBrm
+ { 1719, 3, 1, 0, "PMINSBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(56<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1719 = PMINSBrr
+ { 1720, 7, 1, 0, "PMINSDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(57<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1720 = PMINSDrm
+ { 1721, 3, 1, 0, "PMINSDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(57<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1721 = PMINSDrr
+ { 1722, 7, 1, 0, "PMINSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1722 = PMINSWrm
+ { 1723, 3, 1, 0, "PMINSWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(234<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1723 = PMINSWrr
+ { 1724, 7, 1, 0, "PMINUBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1724 = PMINUBrm
+ { 1725, 3, 1, 0, "PMINUBrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(218<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1725 = PMINUBrr
+ { 1726, 7, 1, 0, "PMINUDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(59<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1726 = PMINUDrm
+ { 1727, 3, 1, 0, "PMINUDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(59<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1727 = PMINUDrr
+ { 1728, 7, 1, 0, "PMINUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(58<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1728 = PMINUWrm
+ { 1729, 3, 1, 0, "PMINUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(58<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1729 = PMINUWrr
+ { 1730, 2, 1, 0, "PMOVMSKBrr", 0, 0|5|(1<<6)|(1<<8)|(215<<24), NULL, NULL, NULL, OperandInfo122 }, // Inst #1730 = PMOVMSKBrr
+ { 1731, 6, 1, 0, "PMOVSXBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(33<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1731 = PMOVSXBDrm
+ { 1732, 2, 1, 0, "PMOVSXBDrr", 0, 0|5|(1<<6)|(13<<8)|(33<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1732 = PMOVSXBDrr
+ { 1733, 6, 1, 0, "PMOVSXBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(34<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1733 = PMOVSXBQrm
+ { 1734, 2, 1, 0, "PMOVSXBQrr", 0, 0|5|(1<<6)|(13<<8)|(34<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1734 = PMOVSXBQrr
+ { 1735, 6, 1, 0, "PMOVSXBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(32<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1735 = PMOVSXBWrm
+ { 1736, 2, 1, 0, "PMOVSXBWrr", 0, 0|5|(1<<6)|(13<<8)|(32<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1736 = PMOVSXBWrr
+ { 1737, 6, 1, 0, "PMOVSXDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(37<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1737 = PMOVSXDQrm
+ { 1738, 2, 1, 0, "PMOVSXDQrr", 0, 0|5|(1<<6)|(13<<8)|(37<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1738 = PMOVSXDQrr
+ { 1739, 6, 1, 0, "PMOVSXWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(35<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1739 = PMOVSXWDrm
+ { 1740, 2, 1, 0, "PMOVSXWDrr", 0, 0|5|(1<<6)|(13<<8)|(35<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1740 = PMOVSXWDrr
+ { 1741, 6, 1, 0, "PMOVSXWQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(36<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1741 = PMOVSXWQrm
+ { 1742, 2, 1, 0, "PMOVSXWQrr", 0, 0|5|(1<<6)|(13<<8)|(36<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1742 = PMOVSXWQrr
+ { 1743, 6, 1, 0, "PMOVZXBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(49<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1743 = PMOVZXBDrm
+ { 1744, 2, 1, 0, "PMOVZXBDrr", 0, 0|5|(1<<6)|(13<<8)|(49<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1744 = PMOVZXBDrr
+ { 1745, 6, 1, 0, "PMOVZXBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(50<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1745 = PMOVZXBQrm
+ { 1746, 2, 1, 0, "PMOVZXBQrr", 0, 0|5|(1<<6)|(13<<8)|(50<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1746 = PMOVZXBQrr
+ { 1747, 6, 1, 0, "PMOVZXBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(48<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1747 = PMOVZXBWrm
+ { 1748, 2, 1, 0, "PMOVZXBWrr", 0, 0|5|(1<<6)|(13<<8)|(48<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1748 = PMOVZXBWrr
+ { 1749, 6, 1, 0, "PMOVZXDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(53<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1749 = PMOVZXDQrm
+ { 1750, 2, 1, 0, "PMOVZXDQrr", 0, 0|5|(1<<6)|(13<<8)|(53<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1750 = PMOVZXDQrr
+ { 1751, 6, 1, 0, "PMOVZXWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(51<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1751 = PMOVZXWDrm
+ { 1752, 2, 1, 0, "PMOVZXWDrr", 0, 0|5|(1<<6)|(13<<8)|(51<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1752 = PMOVZXWDrr
+ { 1753, 6, 1, 0, "PMOVZXWQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(52<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1753 = PMOVZXWQrm
+ { 1754, 2, 1, 0, "PMOVZXWQrr", 0, 0|5|(1<<6)|(13<<8)|(52<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1754 = PMOVZXWQrr
+ { 1755, 7, 1, 0, "PMULDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(40<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1755 = PMULDQrm
+ { 1756, 3, 1, 0, "PMULDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(40<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1756 = PMULDQrr
+ { 1757, 7, 1, 0, "PMULHRSWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1757 = PMULHRSWrm128
+ { 1758, 7, 1, 0, "PMULHRSWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1758 = PMULHRSWrm64
+ { 1759, 3, 1, 0, "PMULHRSWrr128", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1759 = PMULHRSWrr128
+ { 1760, 3, 1, 0, "PMULHRSWrr64", 0|(1<<TID::Commutable), 0|5|(13<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1760 = PMULHRSWrr64
+ { 1761, 7, 1, 0, "PMULHUWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1761 = PMULHUWrm
+ { 1762, 3, 1, 0, "PMULHUWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(228<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1762 = PMULHUWrr
+ { 1763, 7, 1, 0, "PMULHWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1763 = PMULHWrm
+ { 1764, 3, 1, 0, "PMULHWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(229<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1764 = PMULHWrr
+ { 1765, 7, 1, 0, "PMULLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1765 = PMULLDrm
+ { 1766, 7, 1, 0, "PMULLDrm_int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1766 = PMULLDrm_int
+ { 1767, 3, 1, 0, "PMULLDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1767 = PMULLDrr
+ { 1768, 3, 1, 0, "PMULLDrr_int", 0|(1<<TID::Commutable), 0|5|(1<<6)|(13<<8)|(64<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1768 = PMULLDrr_int
+ { 1769, 7, 1, 0, "PMULLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1769 = PMULLWrm
+ { 1770, 3, 1, 0, "PMULLWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(213<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1770 = PMULLWrr
+ { 1771, 7, 1, 0, "PMULUDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1771 = PMULUDQrm
+ { 1772, 3, 1, 0, "PMULUDQrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(244<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1772 = PMULUDQrr
+ { 1773, 1, 1, 0, "POP16r", 0|(1<<TID::MayLoad), 0|2|(1<<6)|(88<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1773 = POP16r
+ { 1774, 5, 1, 0, "POP16rmm", 0|(1<<TID::MayLoad), 0|24|(1<<6)|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1774 = POP16rmm
+ { 1775, 1, 1, 0, "POP16rmr", 0|(1<<TID::MayLoad), 0|16|(1<<6)|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1775 = POP16rmr
+ { 1776, 1, 1, 0, "POP32r", 0|(1<<TID::MayLoad), 0|2|(88<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1776 = POP32r
+ { 1777, 5, 1, 0, "POP32rmm", 0|(1<<TID::MayLoad), 0|24|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1777 = POP32rmm
+ { 1778, 1, 1, 0, "POP32rmr", 0|(1<<TID::MayLoad), 0|16|(143<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1778 = POP32rmr
+ { 1779, 1, 1, 0, "POP64r", 0|(1<<TID::MayLoad), 0|2|(88<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1779 = POP64r
+ { 1780, 5, 1, 0, "POP64rmm", 0|(1<<TID::MayLoad), 0|24|(143<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo30 }, // Inst #1780 = POP64rmm
+ { 1781, 1, 1, 0, "POP64rmr", 0|(1<<TID::MayLoad), 0|16|(143<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1781 = POP64rmr
+ { 1782, 6, 1, 0, "POPCNT16rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<6)|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo46 }, // Inst #1782 = POPCNT16rm
+ { 1783, 2, 1, 0, "POPCNT16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #1783 = POPCNT16rr
+ { 1784, 6, 1, 0, "POPCNT32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #1784 = POPCNT32rm
+ { 1785, 2, 1, 0, "POPCNT32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(184<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #1785 = POPCNT32rr
+ { 1786, 6, 1, 0, "POPCNT64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(12<<8)|(1<<12)|(184<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #1786 = POPCNT64rm
+ { 1787, 2, 1, 0, "POPCNT64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(12<<8)|(1<<12)|(184<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #1787 = POPCNT64rr
+ { 1788, 0, 0, 0, "POPF", 0|(1<<TID::MayLoad), 0|1|(1<<6)|(157<<24), ImplicitList2, ImplicitList3, Barriers1, 0 }, // Inst #1788 = POPF
+ { 1789, 0, 0, 0, "POPFD", 0|(1<<TID::MayLoad), 0|1|(157<<24), ImplicitList2, ImplicitList3, Barriers1, 0 }, // Inst #1789 = POPFD
+ { 1790, 0, 0, 0, "POPFQ", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(157<<24), ImplicitList4, ImplicitList5, Barriers1, 0 }, // Inst #1790 = POPFQ
+ { 1791, 0, 0, 0, "POPFS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1791 = POPFS16
+ { 1792, 0, 0, 0, "POPFS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1792 = POPFS32
+ { 1793, 0, 0, 0, "POPFS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(161<<24), NULL, NULL, NULL, 0 }, // Inst #1793 = POPFS64
+ { 1794, 0, 0, 0, "POPGS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1794 = POPGS16
+ { 1795, 0, 0, 0, "POPGS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1795 = POPGS32
+ { 1796, 0, 0, 0, "POPGS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(169<<24), NULL, NULL, NULL, 0 }, // Inst #1796 = POPGS64
+ { 1797, 7, 1, 0, "PORrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1797 = PORrm
+ { 1798, 3, 1, 0, "PORrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(235<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1798 = PORrr
+ { 1799, 5, 0, 0, "PREFETCHNTA", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1799 = PREFETCHNTA
+ { 1800, 5, 0, 0, "PREFETCHT0", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1800 = PREFETCHT0
+ { 1801, 5, 0, 0, "PREFETCHT1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|26|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1801 = PREFETCHT1
+ { 1802, 5, 0, 0, "PREFETCHT2", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<8)|(24<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #1802 = PREFETCHT2
+ { 1803, 7, 1, 0, "PSADBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1803 = PSADBWrm
+ { 1804, 3, 1, 0, "PSADBWrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(246<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1804 = PSADBWrr
+ { 1805, 7, 1, 0, "PSHUFBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo24 }, // Inst #1805 = PSHUFBrm128
+ { 1806, 7, 1, 0, "PSHUFBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo136 }, // Inst #1806 = PSHUFBrm64
+ { 1807, 3, 1, 0, "PSHUFBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo25 }, // Inst #1807 = PSHUFBrr128
+ { 1808, 3, 1, 0, "PSHUFBrr64", 0, 0|5|(13<<8)|(1<<13), NULL, NULL, NULL, OperandInfo137 }, // Inst #1808 = PSHUFBrr64
+ { 1809, 7, 1, 0, "PSHUFDmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo183 }, // Inst #1809 = PSHUFDmi
+ { 1810, 3, 1, 0, "PSHUFDri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1810 = PSHUFDri
+ { 1811, 7, 1, 0, "PSHUFHWmi", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo183 }, // Inst #1811 = PSHUFHWmi
+ { 1812, 3, 1, 0, "PSHUFHWri", 0, 0|5|(12<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1812 = PSHUFHWri
+ { 1813, 7, 1, 0, "PSHUFLWmi", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo183 }, // Inst #1813 = PSHUFLWmi
+ { 1814, 3, 1, 0, "PSHUFLWri", 0, 0|5|(11<<8)|(1<<13)|(112<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #1814 = PSHUFLWri
+ { 1815, 7, 1, 0, "PSIGNBrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1815 = PSIGNBrm128
+ { 1816, 7, 1, 0, "PSIGNBrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1816 = PSIGNBrm64
+ { 1817, 3, 1, 0, "PSIGNBrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1817 = PSIGNBrr128
+ { 1818, 3, 1, 0, "PSIGNBrr64", 0, 0|5|(13<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1818 = PSIGNBrr64
+ { 1819, 7, 1, 0, "PSIGNDrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1819 = PSIGNDrm128
+ { 1820, 7, 1, 0, "PSIGNDrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1820 = PSIGNDrm64
+ { 1821, 3, 1, 0, "PSIGNDrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1821 = PSIGNDrr128
+ { 1822, 3, 1, 0, "PSIGNDrr64", 0, 0|5|(13<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1822 = PSIGNDrr64
+ { 1823, 7, 1, 0, "PSIGNWrm128", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1823 = PSIGNWrm128
+ { 1824, 7, 1, 0, "PSIGNWrm64", 0|(1<<TID::MayLoad), 0|6|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo136 }, // Inst #1824 = PSIGNWrm64
+ { 1825, 3, 1, 0, "PSIGNWrr128", 0, 0|5|(1<<6)|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1825 = PSIGNWrr128
+ { 1826, 3, 1, 0, "PSIGNWrr64", 0, 0|5|(13<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo137 }, // Inst #1826 = PSIGNWrr64
+ { 1827, 3, 1, 0, "PSLLDQri", 0, 0|23|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1827 = PSLLDQri
+ { 1828, 3, 1, 0, "PSLLDri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1828 = PSLLDri
+ { 1829, 7, 1, 0, "PSLLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1829 = PSLLDrm
+ { 1830, 3, 1, 0, "PSLLDrr", 0, 0|5|(1<<6)|(1<<8)|(242<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1830 = PSLLDrr
+ { 1831, 3, 1, 0, "PSLLQri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1831 = PSLLQri
+ { 1832, 7, 1, 0, "PSLLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1832 = PSLLQrm
+ { 1833, 3, 1, 0, "PSLLQrr", 0, 0|5|(1<<6)|(1<<8)|(243<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1833 = PSLLQrr
+ { 1834, 3, 1, 0, "PSLLWri", 0, 0|22|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1834 = PSLLWri
+ { 1835, 7, 1, 0, "PSLLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1835 = PSLLWrm
+ { 1836, 3, 1, 0, "PSLLWrr", 0, 0|5|(1<<6)|(1<<8)|(241<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1836 = PSLLWrr
+ { 1837, 3, 1, 0, "PSRADri", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1837 = PSRADri
+ { 1838, 7, 1, 0, "PSRADrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1838 = PSRADrm
+ { 1839, 3, 1, 0, "PSRADrr", 0, 0|5|(1<<6)|(1<<8)|(226<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1839 = PSRADrr
+ { 1840, 3, 1, 0, "PSRAWri", 0, 0|20|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1840 = PSRAWri
+ { 1841, 7, 1, 0, "PSRAWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1841 = PSRAWrm
+ { 1842, 3, 1, 0, "PSRAWrr", 0, 0|5|(1<<6)|(1<<8)|(225<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1842 = PSRAWrr
+ { 1843, 3, 1, 0, "PSRLDQri", 0, 0|19|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1843 = PSRLDQri
+ { 1844, 3, 1, 0, "PSRLDri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(114<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1844 = PSRLDri
+ { 1845, 7, 1, 0, "PSRLDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1845 = PSRLDrm
+ { 1846, 3, 1, 0, "PSRLDrr", 0, 0|5|(1<<6)|(1<<8)|(210<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1846 = PSRLDrr
+ { 1847, 3, 1, 0, "PSRLQri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(115<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1847 = PSRLQri
+ { 1848, 7, 1, 0, "PSRLQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1848 = PSRLQrm
+ { 1849, 3, 1, 0, "PSRLQrr", 0, 0|5|(1<<6)|(1<<8)|(211<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1849 = PSRLQrr
+ { 1850, 3, 1, 0, "PSRLWri", 0, 0|18|(1<<6)|(1<<8)|(1<<13)|(113<<24), NULL, NULL, NULL, OperandInfo189 }, // Inst #1850 = PSRLWri
+ { 1851, 7, 1, 0, "PSRLWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1851 = PSRLWrm
+ { 1852, 3, 1, 0, "PSRLWrr", 0, 0|5|(1<<6)|(1<<8)|(209<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1852 = PSRLWrr
+ { 1853, 7, 1, 0, "PSUBBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1853 = PSUBBrm
+ { 1854, 3, 1, 0, "PSUBBrr", 0, 0|5|(1<<6)|(1<<8)|(248<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1854 = PSUBBrr
+ { 1855, 7, 1, 0, "PSUBDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1855 = PSUBDrm
+ { 1856, 3, 1, 0, "PSUBDrr", 0, 0|5|(1<<6)|(1<<8)|(250<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1856 = PSUBDrr
+ { 1857, 7, 1, 0, "PSUBQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1857 = PSUBQrm
+ { 1858, 3, 1, 0, "PSUBQrr", 0, 0|5|(1<<6)|(1<<8)|(251<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1858 = PSUBQrr
+ { 1859, 7, 1, 0, "PSUBSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1859 = PSUBSBrm
+ { 1860, 3, 1, 0, "PSUBSBrr", 0, 0|5|(1<<6)|(1<<8)|(232<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1860 = PSUBSBrr
+ { 1861, 7, 1, 0, "PSUBSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1861 = PSUBSWrm
+ { 1862, 3, 1, 0, "PSUBSWrr", 0, 0|5|(1<<6)|(1<<8)|(233<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1862 = PSUBSWrr
+ { 1863, 7, 1, 0, "PSUBUSBrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1863 = PSUBUSBrm
+ { 1864, 3, 1, 0, "PSUBUSBrr", 0, 0|5|(1<<6)|(1<<8)|(216<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1864 = PSUBUSBrr
+ { 1865, 7, 1, 0, "PSUBUSWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1865 = PSUBUSWrm
+ { 1866, 3, 1, 0, "PSUBUSWrr", 0, 0|5|(1<<6)|(1<<8)|(217<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1866 = PSUBUSWrr
+ { 1867, 7, 1, 0, "PSUBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1867 = PSUBWrm
+ { 1868, 3, 1, 0, "PSUBWrr", 0, 0|5|(1<<6)|(1<<8)|(249<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1868 = PSUBWrr
+ { 1869, 6, 0, 0, "PTESTrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(13<<8)|(23<<24), NULL, ImplicitList1, Barriers1, OperandInfo74 }, // Inst #1869 = PTESTrm
+ { 1870, 2, 0, 0, "PTESTrr", 0, 0|5|(1<<6)|(13<<8)|(23<<24), NULL, ImplicitList1, Barriers1, OperandInfo75 }, // Inst #1870 = PTESTrr
+ { 1871, 7, 1, 0, "PUNPCKHBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1871 = PUNPCKHBWrm
+ { 1872, 3, 1, 0, "PUNPCKHBWrr", 0, 0|5|(1<<6)|(1<<8)|(104<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1872 = PUNPCKHBWrr
+ { 1873, 7, 1, 0, "PUNPCKHDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1873 = PUNPCKHDQrm
+ { 1874, 3, 1, 0, "PUNPCKHDQrr", 0, 0|5|(1<<6)|(1<<8)|(106<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1874 = PUNPCKHDQrr
+ { 1875, 7, 1, 0, "PUNPCKHQDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(109<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1875 = PUNPCKHQDQrm
+ { 1876, 3, 1, 0, "PUNPCKHQDQrr", 0, 0|5|(1<<6)|(1<<8)|(109<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1876 = PUNPCKHQDQrr
+ { 1877, 7, 1, 0, "PUNPCKHWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1877 = PUNPCKHWDrm
+ { 1878, 3, 1, 0, "PUNPCKHWDrr", 0, 0|5|(1<<6)|(1<<8)|(105<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1878 = PUNPCKHWDrr
+ { 1879, 7, 1, 0, "PUNPCKLBWrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1879 = PUNPCKLBWrm
+ { 1880, 3, 1, 0, "PUNPCKLBWrr", 0, 0|5|(1<<6)|(1<<8)|(96<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1880 = PUNPCKLBWrr
+ { 1881, 7, 1, 0, "PUNPCKLDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1881 = PUNPCKLDQrm
+ { 1882, 3, 1, 0, "PUNPCKLDQrr", 0, 0|5|(1<<6)|(1<<8)|(98<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1882 = PUNPCKLDQrr
+ { 1883, 7, 1, 0, "PUNPCKLQDQrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(108<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1883 = PUNPCKLQDQrm
+ { 1884, 3, 1, 0, "PUNPCKLQDQrr", 0, 0|5|(1<<6)|(1<<8)|(108<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1884 = PUNPCKLQDQrr
+ { 1885, 7, 1, 0, "PUNPCKLWDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1885 = PUNPCKLWDrm
+ { 1886, 3, 1, 0, "PUNPCKLWDrr", 0, 0|5|(1<<6)|(1<<8)|(97<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1886 = PUNPCKLWDrr
+ { 1887, 1, 0, 0, "PUSH16r", 0|(1<<TID::MayStore), 0|2|(1<<6)|(80<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1887 = PUSH16r
+ { 1888, 5, 0, 0, "PUSH16rmm", 0|(1<<TID::MayStore), 0|30|(1<<6)|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1888 = PUSH16rmm
+ { 1889, 1, 0, 0, "PUSH16rmr", 0|(1<<TID::MayStore), 0|22|(1<<6)|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo93 }, // Inst #1889 = PUSH16rmr
+ { 1890, 1, 0, 0, "PUSH32i16", 0|(1<<TID::MayStore), 0|1|(3<<13)|(104<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1890 = PUSH32i16
+ { 1891, 1, 0, 0, "PUSH32i32", 0|(1<<TID::MayStore), 0|1|(4<<13)|(104<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1891 = PUSH32i32
+ { 1892, 1, 0, 0, "PUSH32i8", 0|(1<<TID::MayStore), 0|1|(1<<13)|(106<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo5 }, // Inst #1892 = PUSH32i8
+ { 1893, 1, 0, 0, "PUSH32r", 0|(1<<TID::MayStore), 0|2|(80<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1893 = PUSH32r
+ { 1894, 5, 0, 0, "PUSH32rmm", 0|(1<<TID::MayStore), 0|30|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo30 }, // Inst #1894 = PUSH32rmm
+ { 1895, 1, 0, 0, "PUSH32rmr", 0|(1<<TID::MayStore), 0|22|(255<<24), ImplicitList2, ImplicitList2, NULL, OperandInfo57 }, // Inst #1895 = PUSH32rmr
+ { 1896, 1, 0, 0, "PUSH64i16", 0|(1<<TID::MayStore), 0|1|(3<<13)|(104<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1896 = PUSH64i16
+ { 1897, 1, 0, 0, "PUSH64i32", 0|(1<<TID::MayStore), 0|1|(4<<13)|(104<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1897 = PUSH64i32
+ { 1898, 1, 0, 0, "PUSH64i8", 0|(1<<TID::MayStore), 0|1|(1<<13)|(106<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo5 }, // Inst #1898 = PUSH64i8
+ { 1899, 1, 0, 0, "PUSH64r", 0|(1<<TID::MayStore), 0|2|(80<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1899 = PUSH64r
+ { 1900, 5, 0, 0, "PUSH64rmm", 0|(1<<TID::MayStore), 0|30|(255<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo30 }, // Inst #1900 = PUSH64rmm
+ { 1901, 1, 0, 0, "PUSH64rmr", 0|(1<<TID::MayStore), 0|22|(255<<24), ImplicitList4, ImplicitList4, NULL, OperandInfo58 }, // Inst #1901 = PUSH64rmr
+ { 1902, 0, 0, 0, "PUSHF", 0|(1<<TID::MayStore), 0|1|(1<<6)|(156<<24), ImplicitList3, ImplicitList2, NULL, 0 }, // Inst #1902 = PUSHF
+ { 1903, 0, 0, 0, "PUSHFD", 0|(1<<TID::MayStore), 0|1|(156<<24), ImplicitList3, ImplicitList2, NULL, 0 }, // Inst #1903 = PUSHFD
+ { 1904, 0, 0, 0, "PUSHFQ64", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|1|(156<<24), ImplicitList5, ImplicitList4, NULL, 0 }, // Inst #1904 = PUSHFQ64
+ { 1905, 0, 0, 0, "PUSHFS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1905 = PUSHFS16
+ { 1906, 0, 0, 0, "PUSHFS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1906 = PUSHFS32
+ { 1907, 0, 0, 0, "PUSHFS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(160<<24), NULL, NULL, NULL, 0 }, // Inst #1907 = PUSHFS64
+ { 1908, 0, 0, 0, "PUSHGS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1908 = PUSHGS16
+ { 1909, 0, 0, 0, "PUSHGS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1909 = PUSHGS32
+ { 1910, 0, 0, 0, "PUSHGS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(168<<24), NULL, NULL, NULL, 0 }, // Inst #1910 = PUSHGS64
+ { 1911, 7, 1, 0, "PXORrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #1911 = PXORrm
+ { 1912, 3, 1, 0, "PXORrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(239<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #1912 = PXORrr
+ { 1913, 5, 0, 0, "RCL16m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1913 = RCL16m1
+ { 1914, 5, 0, 0, "RCL16mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1914 = RCL16mCL
+ { 1915, 6, 0, 0, "RCL16mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1915 = RCL16mi
+ { 1916, 2, 1, 0, "RCL16r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1916 = RCL16r1
+ { 1917, 2, 1, 0, "RCL16rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1917 = RCL16rCL
+ { 1918, 3, 1, 0, "RCL16ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1918 = RCL16ri
+ { 1919, 5, 0, 0, "RCL32m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1919 = RCL32m1
+ { 1920, 5, 0, 0, "RCL32mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1920 = RCL32mCL
+ { 1921, 6, 0, 0, "RCL32mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1921 = RCL32mi
+ { 1922, 2, 1, 0, "RCL32r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1922 = RCL32r1
+ { 1923, 2, 1, 0, "RCL32rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1923 = RCL32rCL
+ { 1924, 3, 1, 0, "RCL32ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1924 = RCL32ri
+ { 1925, 5, 0, 0, "RCL64m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1925 = RCL64m1
+ { 1926, 5, 0, 0, "RCL64mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1926 = RCL64mCL
+ { 1927, 6, 0, 0, "RCL64mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1927 = RCL64mi
+ { 1928, 2, 1, 0, "RCL64r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1928 = RCL64r1
+ { 1929, 2, 1, 0, "RCL64rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1929 = RCL64rCL
+ { 1930, 3, 1, 0, "RCL64ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1930 = RCL64ri
+ { 1931, 5, 0, 0, "RCL8m1", 0|(1<<TID::UnmodeledSideEffects), 0|26|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1931 = RCL8m1
+ { 1932, 5, 0, 0, "RCL8mCL", 0|(1<<TID::UnmodeledSideEffects), 0|26|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1932 = RCL8mCL
+ { 1933, 6, 0, 0, "RCL8mi", 0|(1<<TID::UnmodeledSideEffects), 0|26|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1933 = RCL8mi
+ { 1934, 2, 1, 0, "RCL8r1", 0|(1<<TID::UnmodeledSideEffects), 0|18|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1934 = RCL8r1
+ { 1935, 2, 1, 0, "RCL8rCL", 0|(1<<TID::UnmodeledSideEffects), 0|18|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1935 = RCL8rCL
+ { 1936, 3, 1, 0, "RCL8ri", 0|(1<<TID::UnmodeledSideEffects), 0|18|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1936 = RCL8ri
+ { 1937, 6, 1, 0, "RCPPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1937 = RCPPSm
+ { 1938, 6, 1, 0, "RCPPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1938 = RCPPSm_Int
+ { 1939, 2, 1, 0, "RCPPSr", 0, 0|5|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1939 = RCPPSr
+ { 1940, 2, 1, 0, "RCPPSr_Int", 0, 0|5|(1<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1940 = RCPPSr_Int
+ { 1941, 6, 1, 0, "RCPSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #1941 = RCPSSm
+ { 1942, 6, 1, 0, "RCPSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #1942 = RCPSSm_Int
+ { 1943, 2, 1, 0, "RCPSSr", 0, 0|5|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #1943 = RCPSSr
+ { 1944, 2, 1, 0, "RCPSSr_Int", 0, 0|5|(12<<8)|(83<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #1944 = RCPSSr_Int
+ { 1945, 5, 0, 0, "RCR16m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1945 = RCR16m1
+ { 1946, 5, 0, 0, "RCR16mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1946 = RCR16mCL
+ { 1947, 6, 0, 0, "RCR16mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1947 = RCR16mi
+ { 1948, 2, 1, 0, "RCR16r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1948 = RCR16r1
+ { 1949, 2, 1, 0, "RCR16rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1949 = RCR16rCL
+ { 1950, 3, 1, 0, "RCR16ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1950 = RCR16ri
+ { 1951, 5, 0, 0, "RCR32m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1951 = RCR32m1
+ { 1952, 5, 0, 0, "RCR32mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1952 = RCR32mCL
+ { 1953, 6, 0, 0, "RCR32mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1953 = RCR32mi
+ { 1954, 2, 1, 0, "RCR32r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1954 = RCR32r1
+ { 1955, 2, 1, 0, "RCR32rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1955 = RCR32rCL
+ { 1956, 3, 1, 0, "RCR32ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1956 = RCR32ri
+ { 1957, 5, 0, 0, "RCR64m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1957 = RCR64m1
+ { 1958, 5, 0, 0, "RCR64mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1958 = RCR64mCL
+ { 1959, 6, 0, 0, "RCR64mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1959 = RCR64mi
+ { 1960, 2, 1, 0, "RCR64r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1960 = RCR64r1
+ { 1961, 2, 1, 0, "RCR64rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #1961 = RCR64rCL
+ { 1962, 3, 1, 0, "RCR64ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #1962 = RCR64ri
+ { 1963, 5, 0, 0, "RCR8m1", 0|(1<<TID::UnmodeledSideEffects), 0|27|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1963 = RCR8m1
+ { 1964, 5, 0, 0, "RCR8mCL", 0|(1<<TID::UnmodeledSideEffects), 0|27|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1964 = RCR8mCL
+ { 1965, 6, 0, 0, "RCR8mi", 0|(1<<TID::UnmodeledSideEffects), 0|27|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1965 = RCR8mi
+ { 1966, 2, 1, 0, "RCR8r1", 0|(1<<TID::UnmodeledSideEffects), 0|19|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1966 = RCR8r1
+ { 1967, 2, 1, 0, "RCR8rCL", 0|(1<<TID::UnmodeledSideEffects), 0|19|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #1967 = RCR8rCL
+ { 1968, 3, 1, 0, "RCR8ri", 0|(1<<TID::UnmodeledSideEffects), 0|19|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #1968 = RCR8ri
+ { 1969, 0, 0, 0, "RDMSR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(50<<24), NULL, NULL, NULL, 0 }, // Inst #1969 = RDMSR
+ { 1970, 0, 0, 0, "RDPMC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(51<<24), NULL, NULL, NULL, 0 }, // Inst #1970 = RDPMC
+ { 1971, 0, 0, 0, "RDTSC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(49<<24), NULL, ImplicitList19, NULL, 0 }, // Inst #1971 = RDTSC
+ { 1972, 0, 0, 0, "RDTSCP", 0|(1<<TID::UnmodeledSideEffects), 0|42|(1<<8)|(1<<24), NULL, ImplicitList45, NULL, 0 }, // Inst #1972 = RDTSCP
+ { 1973, 0, 0, 0, "REPNE_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(242<<24), ImplicitList42, ImplicitList27, NULL, 0 }, // Inst #1973 = REPNE_PREFIX
+ { 1974, 0, 0, 0, "REP_MOVSB", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(164<<24), ImplicitList46, ImplicitList46, NULL, 0 }, // Inst #1974 = REP_MOVSB
+ { 1975, 0, 0, 0, "REP_MOVSD", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(165<<24), ImplicitList46, ImplicitList46, NULL, 0 }, // Inst #1975 = REP_MOVSD
+ { 1976, 0, 0, 0, "REP_MOVSQ", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(2<<8)|(1<<12)|(165<<24), ImplicitList47, ImplicitList47, NULL, 0 }, // Inst #1976 = REP_MOVSQ
+ { 1977, 0, 0, 0, "REP_MOVSW", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|1|(1<<6)|(2<<8)|(165<<24), ImplicitList46, ImplicitList46, NULL, 0 }, // Inst #1977 = REP_MOVSW
+ { 1978, 0, 0, 0, "REP_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(243<<24), ImplicitList42, ImplicitList27, NULL, 0 }, // Inst #1978 = REP_PREFIX
+ { 1979, 0, 0, 0, "REP_STOSB", 0|(1<<TID::MayStore), 0|1|(2<<8)|(170<<24), ImplicitList48, ImplicitList49, NULL, 0 }, // Inst #1979 = REP_STOSB
+ { 1980, 0, 0, 0, "REP_STOSD", 0|(1<<TID::MayStore), 0|1|(2<<8)|(171<<24), ImplicitList50, ImplicitList49, NULL, 0 }, // Inst #1980 = REP_STOSD
+ { 1981, 0, 0, 0, "REP_STOSQ", 0|(1<<TID::MayStore), 0|1|(2<<8)|(1<<12)|(171<<24), ImplicitList51, ImplicitList52, NULL, 0 }, // Inst #1981 = REP_STOSQ
+ { 1982, 0, 0, 0, "REP_STOSW", 0|(1<<TID::MayStore), 0|1|(1<<6)|(2<<8)|(171<<24), ImplicitList53, ImplicitList49, NULL, 0 }, // Inst #1982 = REP_STOSW
+ { 1983, 0, 0, 0, "RET", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::Variadic), 0|1|(7<<16)|(195<<24), NULL, NULL, NULL, 0 }, // Inst #1983 = RET
+ { 1984, 1, 0, 0, "RETI", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Terminator)|(1<<TID::Variadic), 0|1|(3<<13)|(7<<16)|(194<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #1984 = RETI
+ { 1985, 5, 0, 0, "ROL16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1985 = ROL16m1
+ { 1986, 5, 0, 0, "ROL16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1986 = ROL16mCL
+ { 1987, 6, 0, 0, "ROL16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1987 = ROL16mi
+ { 1988, 2, 1, 0, "ROL16r1", 0, 0|16|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1988 = ROL16r1
+ { 1989, 2, 1, 0, "ROL16rCL", 0, 0|16|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #1989 = ROL16rCL
+ { 1990, 3, 1, 0, "ROL16ri", 0, 0|16|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #1990 = ROL16ri
+ { 1991, 5, 0, 0, "ROL32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1991 = ROL32m1
+ { 1992, 5, 0, 0, "ROL32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1992 = ROL32mCL
+ { 1993, 6, 0, 0, "ROL32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1993 = ROL32mi
+ { 1994, 2, 1, 0, "ROL32r1", 0, 0|16|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1994 = ROL32r1
+ { 1995, 2, 1, 0, "ROL32rCL", 0, 0|16|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #1995 = ROL32rCL
+ { 1996, 3, 1, 0, "ROL32ri", 0, 0|16|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #1996 = ROL32ri
+ { 1997, 5, 0, 0, "ROL64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1997 = ROL64m1
+ { 1998, 5, 0, 0, "ROL64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #1998 = ROL64mCL
+ { 1999, 6, 0, 0, "ROL64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #1999 = ROL64mi
+ { 2000, 2, 1, 0, "ROL64r1", 0, 0|16|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2000 = ROL64r1
+ { 2001, 2, 1, 0, "ROL64rCL", 0, 0|16|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2001 = ROL64rCL
+ { 2002, 3, 1, 0, "ROL64ri", 0, 0|16|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2002 = ROL64ri
+ { 2003, 5, 0, 0, "ROL8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2003 = ROL8m1
+ { 2004, 5, 0, 0, "ROL8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2004 = ROL8mCL
+ { 2005, 6, 0, 0, "ROL8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|24|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2005 = ROL8mi
+ { 2006, 2, 1, 0, "ROL8r1", 0, 0|16|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2006 = ROL8r1
+ { 2007, 2, 1, 0, "ROL8rCL", 0, 0|16|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2007 = ROL8rCL
+ { 2008, 3, 1, 0, "ROL8ri", 0, 0|16|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2008 = ROL8ri
+ { 2009, 5, 0, 0, "ROR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2009 = ROR16m1
+ { 2010, 5, 0, 0, "ROR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2010 = ROR16mCL
+ { 2011, 6, 0, 0, "ROR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2011 = ROR16mi
+ { 2012, 2, 1, 0, "ROR16r1", 0, 0|17|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2012 = ROR16r1
+ { 2013, 2, 1, 0, "ROR16rCL", 0, 0|17|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2013 = ROR16rCL
+ { 2014, 3, 1, 0, "ROR16ri", 0, 0|17|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2014 = ROR16ri
+ { 2015, 5, 0, 0, "ROR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2015 = ROR32m1
+ { 2016, 5, 0, 0, "ROR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2016 = ROR32mCL
+ { 2017, 6, 0, 0, "ROR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2017 = ROR32mi
+ { 2018, 2, 1, 0, "ROR32r1", 0, 0|17|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2018 = ROR32r1
+ { 2019, 2, 1, 0, "ROR32rCL", 0, 0|17|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2019 = ROR32rCL
+ { 2020, 3, 1, 0, "ROR32ri", 0, 0|17|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2020 = ROR32ri
+ { 2021, 5, 0, 0, "ROR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2021 = ROR64m1
+ { 2022, 5, 0, 0, "ROR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2022 = ROR64mCL
+ { 2023, 6, 0, 0, "ROR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2023 = ROR64mi
+ { 2024, 2, 1, 0, "ROR64r1", 0, 0|17|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2024 = ROR64r1
+ { 2025, 2, 1, 0, "ROR64rCL", 0, 0|17|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2025 = ROR64rCL
+ { 2026, 3, 1, 0, "ROR64ri", 0, 0|17|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2026 = ROR64ri
+ { 2027, 5, 0, 0, "ROR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2027 = ROR8m1
+ { 2028, 5, 0, 0, "ROR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2028 = ROR8mCL
+ { 2029, 6, 0, 0, "ROR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|25|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2029 = ROR8mi
+ { 2030, 2, 1, 0, "ROR8r1", 0, 0|17|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2030 = ROR8r1
+ { 2031, 2, 1, 0, "ROR8rCL", 0, 0|17|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2031 = ROR8rCL
+ { 2032, 3, 1, 0, "ROR8ri", 0, 0|17|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2032 = ROR8ri
+ { 2033, 7, 1, 0, "ROUNDPDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo183 }, // Inst #2033 = ROUNDPDm_Int
+ { 2034, 3, 1, 0, "ROUNDPDr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(9<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #2034 = ROUNDPDr_Int
+ { 2035, 7, 1, 0, "ROUNDPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo183 }, // Inst #2035 = ROUNDPSm_Int
+ { 2036, 3, 1, 0, "ROUNDPSr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(8<<24), NULL, NULL, NULL, OperandInfo184 }, // Inst #2036 = ROUNDPSr_Int
+ { 2037, 8, 1, 0, "ROUNDSDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2037 = ROUNDSDm_Int
+ { 2038, 4, 1, 0, "ROUNDSDr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(11<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2038 = ROUNDSDr_Int
+ { 2039, 8, 1, 0, "ROUNDSSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(14<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2039 = ROUNDSSm_Int
+ { 2040, 4, 1, 0, "ROUNDSSr_Int", 0, 0|5|(1<<6)|(14<<8)|(1<<13)|(10<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2040 = ROUNDSSr_Int
+ { 2041, 0, 0, 0, "RSM", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(170<<24), NULL, NULL, NULL, 0 }, // Inst #2041 = RSM
+ { 2042, 6, 1, 0, "RSQRTPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2042 = RSQRTPSm
+ { 2043, 6, 1, 0, "RSQRTPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2043 = RSQRTPSm_Int
+ { 2044, 2, 1, 0, "RSQRTPSr", 0, 0|5|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2044 = RSQRTPSr
+ { 2045, 2, 1, 0, "RSQRTPSr_Int", 0, 0|5|(1<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2045 = RSQRTPSr_Int
+ { 2046, 6, 1, 0, "RSQRTSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #2046 = RSQRTSSm
+ { 2047, 6, 1, 0, "RSQRTSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2047 = RSQRTSSm_Int
+ { 2048, 2, 1, 0, "RSQRTSSr", 0, 0|5|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #2048 = RSQRTSSr
+ { 2049, 2, 1, 0, "RSQRTSSr_Int", 0, 0|5|(12<<8)|(82<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2049 = RSQRTSSr_Int
+ { 2050, 0, 0, 0, "SAHF", 0, 0|1|(158<<24), ImplicitList28, ImplicitList1, Barriers1, 0 }, // Inst #2050 = SAHF
+ { 2051, 5, 0, 0, "SAR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2051 = SAR16m1
+ { 2052, 5, 0, 0, "SAR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2052 = SAR16mCL
+ { 2053, 6, 0, 0, "SAR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2053 = SAR16mi
+ { 2054, 2, 1, 0, "SAR16r1", 0, 0|23|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2054 = SAR16r1
+ { 2055, 2, 1, 0, "SAR16rCL", 0, 0|23|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2055 = SAR16rCL
+ { 2056, 3, 1, 0, "SAR16ri", 0, 0|23|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2056 = SAR16ri
+ { 2057, 5, 0, 0, "SAR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2057 = SAR32m1
+ { 2058, 5, 0, 0, "SAR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2058 = SAR32mCL
+ { 2059, 6, 0, 0, "SAR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2059 = SAR32mi
+ { 2060, 2, 1, 0, "SAR32r1", 0, 0|23|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2060 = SAR32r1
+ { 2061, 2, 1, 0, "SAR32rCL", 0, 0|23|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2061 = SAR32rCL
+ { 2062, 3, 1, 0, "SAR32ri", 0, 0|23|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2062 = SAR32ri
+ { 2063, 5, 0, 0, "SAR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2063 = SAR64m1
+ { 2064, 5, 0, 0, "SAR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2064 = SAR64mCL
+ { 2065, 6, 0, 0, "SAR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2065 = SAR64mi
+ { 2066, 2, 1, 0, "SAR64r1", 0, 0|23|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2066 = SAR64r1
+ { 2067, 2, 1, 0, "SAR64rCL", 0, 0|23|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2067 = SAR64rCL
+ { 2068, 3, 1, 0, "SAR64ri", 0, 0|23|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2068 = SAR64ri
+ { 2069, 5, 0, 0, "SAR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2069 = SAR8m1
+ { 2070, 5, 0, 0, "SAR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2070 = SAR8mCL
+ { 2071, 6, 0, 0, "SAR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|31|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2071 = SAR8mi
+ { 2072, 2, 1, 0, "SAR8r1", 0, 0|23|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2072 = SAR8r1
+ { 2073, 2, 1, 0, "SAR8rCL", 0, 0|23|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2073 = SAR8rCL
+ { 2074, 3, 1, 0, "SAR8ri", 0, 0|23|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2074 = SAR8ri
+ { 2075, 1, 0, 0, "SBB16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2075 = SBB16i16
+ { 2076, 6, 0, 0, "SBB16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2076 = SBB16mi
+ { 2077, 6, 0, 0, "SBB16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2077 = SBB16mi8
+ { 2078, 6, 0, 0, "SBB16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2078 = SBB16mr
+ { 2079, 3, 1, 0, "SBB16ri", 0, 0|19|(1<<6)|(3<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2079 = SBB16ri
+ { 2080, 3, 1, 0, "SBB16ri8", 0, 0|19|(1<<6)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2080 = SBB16ri8
+ { 2081, 7, 1, 0, "SBB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2081 = SBB16rm
+ { 2082, 3, 1, 0, "SBB16rr", 0, 0|3|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2082 = SBB16rr
+ { 2083, 3, 1, 0, "SBB16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2083 = SBB16rr_REV
+ { 2084, 1, 0, 0, "SBB32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2084 = SBB32i32
+ { 2085, 6, 0, 0, "SBB32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2085 = SBB32mi
+ { 2086, 6, 0, 0, "SBB32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2086 = SBB32mi8
+ { 2087, 6, 0, 0, "SBB32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2087 = SBB32mr
+ { 2088, 3, 1, 0, "SBB32ri", 0, 0|19|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2088 = SBB32ri
+ { 2089, 3, 1, 0, "SBB32ri8", 0, 0|19|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2089 = SBB32ri8
+ { 2090, 7, 1, 0, "SBB32rm", 0|(1<<TID::MayLoad), 0|6|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2090 = SBB32rm
+ { 2091, 3, 1, 0, "SBB32rr", 0, 0|3|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2091 = SBB32rr
+ { 2092, 3, 1, 0, "SBB32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2092 = SBB32rr_REV
+ { 2093, 1, 0, 0, "SBB64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(29<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2093 = SBB64i32
+ { 2094, 6, 0, 0, "SBB64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2094 = SBB64mi32
+ { 2095, 6, 0, 0, "SBB64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2095 = SBB64mi8
+ { 2096, 6, 0, 0, "SBB64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2096 = SBB64mr
+ { 2097, 3, 1, 0, "SBB64ri32", 0, 0|19|(1<<12)|(4<<13)|(129<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2097 = SBB64ri32
+ { 2098, 3, 1, 0, "SBB64ri8", 0, 0|19|(1<<12)|(1<<13)|(131<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2098 = SBB64ri8
+ { 2099, 7, 1, 0, "SBB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2099 = SBB64rm
+ { 2100, 3, 1, 0, "SBB64rr", 0, 0|3|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2100 = SBB64rr
+ { 2101, 3, 1, 0, "SBB64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(27<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2101 = SBB64rr_REV
+ { 2102, 1, 0, 0, "SBB8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(28<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2102 = SBB8i8
+ { 2103, 6, 0, 0, "SBB8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|27|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2103 = SBB8mi
+ { 2104, 6, 0, 0, "SBB8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2104 = SBB8mr
+ { 2105, 3, 1, 0, "SBB8ri", 0, 0|19|(1<<13)|(128<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2105 = SBB8ri
+ { 2106, 7, 1, 0, "SBB8rm", 0|(1<<TID::MayLoad), 0|6|(26<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2106 = SBB8rm
+ { 2107, 3, 1, 0, "SBB8rr", 0, 0|3|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2107 = SBB8rr
+ { 2108, 3, 1, 0, "SBB8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(26<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2108 = SBB8rr_REV
+ { 2109, 0, 0, 0, "SCAS16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2109 = SCAS16
+ { 2110, 0, 0, 0, "SCAS32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2110 = SCAS32
+ { 2111, 0, 0, 0, "SCAS64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(175<<24), NULL, NULL, NULL, 0 }, // Inst #2111 = SCAS64
+ { 2112, 0, 0, 0, "SCAS8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(174<<24), NULL, NULL, NULL, 0 }, // Inst #2112 = SCAS8
+ { 2113, 5, 0, 0, "SETAEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(147<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2113 = SETAEm
+ { 2114, 1, 1, 0, "SETAEr", 0, 0|16|(1<<8)|(147<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2114 = SETAEr
+ { 2115, 5, 0, 0, "SETAm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(151<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2115 = SETAm
+ { 2116, 1, 1, 0, "SETAr", 0, 0|16|(1<<8)|(151<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2116 = SETAr
+ { 2117, 5, 0, 0, "SETBEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(150<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2117 = SETBEm
+ { 2118, 1, 1, 0, "SETBEr", 0, 0|16|(1<<8)|(150<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2118 = SETBEr
+ { 2119, 1, 1, 0, "SETB_C16r", 0, 0|32|(1<<6)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo93 }, // Inst #2119 = SETB_C16r
+ { 2120, 1, 1, 0, "SETB_C32r", 0, 0|32|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo57 }, // Inst #2120 = SETB_C32r
+ { 2121, 1, 1, 0, "SETB_C64r", 0, 0|32|(1<<12)|(25<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo58 }, // Inst #2121 = SETB_C64r
+ { 2122, 1, 1, 0, "SETB_C8r", 0, 0|32|(24<<24), ImplicitList1, ImplicitList1, Barriers1, OperandInfo94 }, // Inst #2122 = SETB_C8r
+ { 2123, 5, 0, 0, "SETBm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(146<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2123 = SETBm
+ { 2124, 1, 1, 0, "SETBr", 0, 0|16|(1<<8)|(146<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2124 = SETBr
+ { 2125, 5, 0, 0, "SETEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(148<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2125 = SETEm
+ { 2126, 1, 1, 0, "SETEr", 0, 0|16|(1<<8)|(148<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2126 = SETEr
+ { 2127, 5, 0, 0, "SETGEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(157<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2127 = SETGEm
+ { 2128, 1, 1, 0, "SETGEr", 0, 0|16|(1<<8)|(157<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2128 = SETGEr
+ { 2129, 5, 0, 0, "SETGm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(159<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2129 = SETGm
+ { 2130, 1, 1, 0, "SETGr", 0, 0|16|(1<<8)|(159<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2130 = SETGr
+ { 2131, 5, 0, 0, "SETLEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(158<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2131 = SETLEm
+ { 2132, 1, 1, 0, "SETLEr", 0, 0|16|(1<<8)|(158<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2132 = SETLEr
+ { 2133, 5, 0, 0, "SETLm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(156<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2133 = SETLm
+ { 2134, 1, 1, 0, "SETLr", 0, 0|16|(1<<8)|(156<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2134 = SETLr
+ { 2135, 5, 0, 0, "SETNEm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(149<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2135 = SETNEm
+ { 2136, 1, 1, 0, "SETNEr", 0, 0|16|(1<<8)|(149<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2136 = SETNEr
+ { 2137, 5, 0, 0, "SETNOm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(145<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2137 = SETNOm
+ { 2138, 1, 1, 0, "SETNOr", 0, 0|16|(1<<8)|(145<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2138 = SETNOr
+ { 2139, 5, 0, 0, "SETNPm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(155<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2139 = SETNPm
+ { 2140, 1, 1, 0, "SETNPr", 0, 0|16|(1<<8)|(155<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2140 = SETNPr
+ { 2141, 5, 0, 0, "SETNSm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(153<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2141 = SETNSm
+ { 2142, 1, 1, 0, "SETNSr", 0, 0|16|(1<<8)|(153<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2142 = SETNSr
+ { 2143, 5, 0, 0, "SETOm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(144<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2143 = SETOm
+ { 2144, 1, 1, 0, "SETOr", 0, 0|16|(1<<8)|(144<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2144 = SETOr
+ { 2145, 5, 0, 0, "SETPm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(154<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2145 = SETPm
+ { 2146, 1, 1, 0, "SETPr", 0, 0|16|(1<<8)|(154<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2146 = SETPr
+ { 2147, 5, 0, 0, "SETSm", 0|(1<<TID::MayStore), 0|24|(1<<8)|(152<<24), ImplicitList1, NULL, NULL, OperandInfo30 }, // Inst #2147 = SETSm
+ { 2148, 1, 1, 0, "SETSr", 0, 0|16|(1<<8)|(152<<24), ImplicitList1, NULL, NULL, OperandInfo94 }, // Inst #2148 = SETSr
+ { 2149, 0, 0, 0, "SFENCE", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|23|(1<<8)|(174<<24), NULL, NULL, NULL, 0 }, // Inst #2149 = SFENCE
+ { 2150, 5, 1, 0, "SGDTm", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2150 = SGDTm
+ { 2151, 5, 0, 0, "SHL16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2151 = SHL16m1
+ { 2152, 5, 0, 0, "SHL16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2152 = SHL16mCL
+ { 2153, 6, 0, 0, "SHL16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2153 = SHL16mi
+ { 2154, 2, 1, 0, "SHL16r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2154 = SHL16r1
+ { 2155, 2, 1, 0, "SHL16rCL", 0, 0|20|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2155 = SHL16rCL
+ { 2156, 3, 1, 0, "SHL16ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2156 = SHL16ri
+ { 2157, 5, 0, 0, "SHL32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2157 = SHL32m1
+ { 2158, 5, 0, 0, "SHL32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2158 = SHL32mCL
+ { 2159, 6, 0, 0, "SHL32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2159 = SHL32mi
+ { 2160, 2, 1, 0, "SHL32r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2160 = SHL32r1
+ { 2161, 2, 1, 0, "SHL32rCL", 0, 0|20|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2161 = SHL32rCL
+ { 2162, 3, 1, 0, "SHL32ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2162 = SHL32ri
+ { 2163, 5, 0, 0, "SHL64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2163 = SHL64m1
+ { 2164, 5, 0, 0, "SHL64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2164 = SHL64mCL
+ { 2165, 6, 0, 0, "SHL64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2165 = SHL64mi
+ { 2166, 2, 1, 0, "SHL64r1", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2166 = SHL64r1
+ { 2167, 2, 1, 0, "SHL64rCL", 0, 0|20|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2167 = SHL64rCL
+ { 2168, 3, 1, 0, "SHL64ri", 0|(1<<TID::ConvertibleTo3Addr), 0|20|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2168 = SHL64ri
+ { 2169, 5, 0, 0, "SHL8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2169 = SHL8m1
+ { 2170, 5, 0, 0, "SHL8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2170 = SHL8mCL
+ { 2171, 6, 0, 0, "SHL8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|28|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2171 = SHL8mi
+ { 2172, 2, 1, 0, "SHL8r1", 0|(1<<TID::ConvertibleTo3Addr)|(1<<TID::UnmodeledSideEffects), 0|20|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2172 = SHL8r1
+ { 2173, 2, 1, 0, "SHL8rCL", 0, 0|20|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2173 = SHL8rCL
+ { 2174, 3, 1, 0, "SHL8ri", 0, 0|20|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2174 = SHL8ri
+ { 2175, 6, 0, 0, "SHLD16mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2175 = SHLD16mrCL
+ { 2176, 7, 0, 0, "SHLD16mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo190 }, // Inst #2176 = SHLD16mri8
+ { 2177, 3, 1, 0, "SHLD16rrCL", 0, 0|3|(1<<6)|(1<<8)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2177 = SHLD16rrCL
+ { 2178, 4, 1, 0, "SHLD16rri8", 0|(1<<TID::Commutable), 0|3|(1<<6)|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo191 }, // Inst #2178 = SHLD16rri8
+ { 2179, 6, 0, 0, "SHLD32mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2179 = SHLD32mrCL
+ { 2180, 7, 0, 0, "SHLD32mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo192 }, // Inst #2180 = SHLD32mri8
+ { 2181, 3, 1, 0, "SHLD32rrCL", 0, 0|3|(1<<8)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2181 = SHLD32rrCL
+ { 2182, 4, 1, 0, "SHLD32rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo193 }, // Inst #2182 = SHLD32rri8
+ { 2183, 6, 0, 0, "SHLD64mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2183 = SHLD64mrCL
+ { 2184, 7, 0, 0, "SHLD64mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #2184 = SHLD64mri8
+ { 2185, 3, 1, 0, "SHLD64rrCL", 0, 0|3|(1<<8)|(1<<12)|(165<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2185 = SHLD64rrCL
+ { 2186, 4, 1, 0, "SHLD64rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<12)|(1<<13)|(164<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #2186 = SHLD64rri8
+ { 2187, 5, 0, 0, "SHR16m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2187 = SHR16m1
+ { 2188, 5, 0, 0, "SHR16mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2188 = SHR16mCL
+ { 2189, 6, 0, 0, "SHR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2189 = SHR16mi
+ { 2190, 2, 1, 0, "SHR16r1", 0, 0|21|(1<<6)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2190 = SHR16r1
+ { 2191, 2, 1, 0, "SHR16rCL", 0, 0|21|(1<<6)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo91 }, // Inst #2191 = SHR16rCL
+ { 2192, 3, 1, 0, "SHR16ri", 0, 0|21|(1<<6)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2192 = SHR16ri
+ { 2193, 5, 0, 0, "SHR32m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2193 = SHR32m1
+ { 2194, 5, 0, 0, "SHR32mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2194 = SHR32mCL
+ { 2195, 6, 0, 0, "SHR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2195 = SHR32mi
+ { 2196, 2, 1, 0, "SHR32r1", 0, 0|21|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2196 = SHR32r1
+ { 2197, 2, 1, 0, "SHR32rCL", 0, 0|21|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo52 }, // Inst #2197 = SHR32rCL
+ { 2198, 3, 1, 0, "SHR32ri", 0, 0|21|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2198 = SHR32ri
+ { 2199, 5, 0, 0, "SHR64m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2199 = SHR64m1
+ { 2200, 5, 0, 0, "SHR64mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2200 = SHR64mCL
+ { 2201, 6, 0, 0, "SHR64mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2201 = SHR64mi
+ { 2202, 2, 1, 0, "SHR64r1", 0, 0|21|(1<<12)|(209<<24), NULL, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2202 = SHR64r1
+ { 2203, 2, 1, 0, "SHR64rCL", 0, 0|21|(1<<12)|(211<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo53 }, // Inst #2203 = SHR64rCL
+ { 2204, 3, 1, 0, "SHR64ri", 0, 0|21|(1<<12)|(1<<13)|(193<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2204 = SHR64ri
+ { 2205, 5, 0, 0, "SHR8m1", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2205 = SHR8m1
+ { 2206, 5, 0, 0, "SHR8mCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo30 }, // Inst #2206 = SHR8mCL
+ { 2207, 6, 0, 0, "SHR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2207 = SHR8mi
+ { 2208, 2, 1, 0, "SHR8r1", 0, 0|21|(208<<24), NULL, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2208 = SHR8r1
+ { 2209, 2, 1, 0, "SHR8rCL", 0, 0|21|(210<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo92 }, // Inst #2209 = SHR8rCL
+ { 2210, 3, 1, 0, "SHR8ri", 0, 0|21|(1<<13)|(192<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2210 = SHR8ri
+ { 2211, 6, 0, 0, "SHRD16mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2211 = SHRD16mrCL
+ { 2212, 7, 0, 0, "SHRD16mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo190 }, // Inst #2212 = SHRD16mri8
+ { 2213, 3, 1, 0, "SHRD16rrCL", 0, 0|3|(1<<6)|(1<<8)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2213 = SHRD16rrCL
+ { 2214, 4, 1, 0, "SHRD16rri8", 0|(1<<TID::Commutable), 0|3|(1<<6)|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo191 }, // Inst #2214 = SHRD16rri8
+ { 2215, 6, 0, 0, "SHRD32mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2215 = SHRD32mrCL
+ { 2216, 7, 0, 0, "SHRD32mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo192 }, // Inst #2216 = SHRD32mri8
+ { 2217, 3, 1, 0, "SHRD32rrCL", 0, 0|3|(1<<8)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2217 = SHRD32rrCL
+ { 2218, 4, 1, 0, "SHRD32rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo193 }, // Inst #2218 = SHRD32rri8
+ { 2219, 6, 0, 0, "SHRD64mrCL", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2219 = SHRD64mrCL
+ { 2220, 7, 0, 0, "SHRD64mri8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<8)|(1<<12)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo194 }, // Inst #2220 = SHRD64mri8
+ { 2221, 3, 1, 0, "SHRD64rrCL", 0, 0|3|(1<<8)|(1<<12)|(173<<24), ImplicitList44, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2221 = SHRD64rrCL
+ { 2222, 4, 1, 0, "SHRD64rri8", 0|(1<<TID::Commutable), 0|3|(1<<8)|(1<<12)|(1<<13)|(172<<24), NULL, ImplicitList1, Barriers1, OperandInfo195 }, // Inst #2222 = SHRD64rri8
+ { 2223, 8, 1, 0, "SHUFPDrmi", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2223 = SHUFPDrmi
+ { 2224, 4, 1, 0, "SHUFPDrri", 0, 0|5|(1<<6)|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2224 = SHUFPDrri
+ { 2225, 8, 1, 0, "SHUFPSrmi", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo44 }, // Inst #2225 = SHUFPSrmi
+ { 2226, 4, 1, 0, "SHUFPSrri", 0|(1<<TID::ConvertibleTo3Addr), 0|5|(1<<8)|(1<<13)|(198<<24), NULL, NULL, NULL, OperandInfo45 }, // Inst #2226 = SHUFPSrri
+ { 2227, 5, 1, 0, "SIDTm", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2227 = SIDTm
+ { 2228, 0, 0, 0, "SIN_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(254<<24), NULL, NULL, NULL, 0 }, // Inst #2228 = SIN_F
+ { 2229, 2, 1, 0, "SIN_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #2229 = SIN_Fp32
+ { 2230, 2, 1, 0, "SIN_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #2230 = SIN_Fp64
+ { 2231, 2, 1, 0, "SIN_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #2231 = SIN_Fp80
+ { 2232, 5, 1, 0, "SLDT16m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2232 = SLDT16m
+ { 2233, 1, 1, 0, "SLDT16r", 0|(1<<TID::UnmodeledSideEffects), 0|16|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2233 = SLDT16r
+ { 2234, 5, 1, 0, "SLDT64m", 0|(1<<TID::UnmodeledSideEffects), 0|24|(1<<8)|(1<<12), NULL, NULL, NULL, OperandInfo30 }, // Inst #2234 = SLDT64m
+ { 2235, 1, 1, 0, "SLDT64r", 0|(1<<TID::UnmodeledSideEffects), 0|16|(1<<8)|(1<<12), NULL, NULL, NULL, OperandInfo58 }, // Inst #2235 = SLDT64r
+ { 2236, 5, 1, 0, "SMSW16m", 0|(1<<TID::UnmodeledSideEffects), 0|28|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2236 = SMSW16m
+ { 2237, 1, 1, 0, "SMSW16r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<6)|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo93 }, // Inst #2237 = SMSW16r
+ { 2238, 1, 1, 0, "SMSW32r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8)|(1<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2238 = SMSW32r
+ { 2239, 1, 1, 0, "SMSW64r", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8)|(1<<12)|(1<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2239 = SMSW64r
+ { 2240, 6, 1, 0, "SQRTPDm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2240 = SQRTPDm
+ { 2241, 6, 1, 0, "SQRTPDm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2241 = SQRTPDm_Int
+ { 2242, 2, 1, 0, "SQRTPDr", 0, 0|5|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2242 = SQRTPDr
+ { 2243, 2, 1, 0, "SQRTPDr_Int", 0, 0|5|(1<<6)|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2243 = SQRTPDr_Int
+ { 2244, 6, 1, 0, "SQRTPSm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2244 = SQRTPSm
+ { 2245, 6, 1, 0, "SQRTPSm_Int", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2245 = SQRTPSm_Int
+ { 2246, 2, 1, 0, "SQRTPSr", 0, 0|5|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2246 = SQRTPSr
+ { 2247, 2, 1, 0, "SQRTPSr_Int", 0, 0|5|(1<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2247 = SQRTPSr_Int
+ { 2248, 6, 1, 0, "SQRTSDm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo82 }, // Inst #2248 = SQRTSDm
+ { 2249, 6, 1, 0, "SQRTSDm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2249 = SQRTSDm_Int
+ { 2250, 2, 1, 0, "SQRTSDr", 0, 0|5|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo105 }, // Inst #2250 = SQRTSDr
+ { 2251, 2, 1, 0, "SQRTSDr_Int", 0, 0|5|(11<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2251 = SQRTSDr_Int
+ { 2252, 6, 1, 0, "SQRTSSm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo80 }, // Inst #2252 = SQRTSSm
+ { 2253, 6, 1, 0, "SQRTSSm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo74 }, // Inst #2253 = SQRTSSm_Int
+ { 2254, 2, 1, 0, "SQRTSSr", 0, 0|5|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo106 }, // Inst #2254 = SQRTSSr
+ { 2255, 2, 1, 0, "SQRTSSr_Int", 0, 0|5|(12<<8)|(81<<24), NULL, NULL, NULL, OperandInfo75 }, // Inst #2255 = SQRTSSr_Int
+ { 2256, 0, 0, 0, "SQRT_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(250<<24), NULL, NULL, NULL, 0 }, // Inst #2256 = SQRT_F
+ { 2257, 2, 1, 0, "SQRT_Fp32", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo2 }, // Inst #2257 = SQRT_Fp32
+ { 2258, 2, 1, 0, "SQRT_Fp64", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo3 }, // Inst #2258 = SQRT_Fp64
+ { 2259, 2, 1, 0, "SQRT_Fp80", 0, 0|(3<<16), NULL, NULL, NULL, OperandInfo4 }, // Inst #2259 = SQRT_Fp80
+ { 2260, 0, 0, 0, "SS_PREFIX", 0|(1<<TID::UnmodeledSideEffects), 0|1|(54<<24), NULL, NULL, NULL, 0 }, // Inst #2260 = SS_PREFIX
+ { 2261, 0, 0, 0, "STC", 0|(1<<TID::UnmodeledSideEffects), 0|1|(249<<24), NULL, NULL, NULL, 0 }, // Inst #2261 = STC
+ { 2262, 0, 0, 0, "STD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(253<<24), NULL, NULL, NULL, 0 }, // Inst #2262 = STD
+ { 2263, 0, 0, 0, "STI", 0|(1<<TID::UnmodeledSideEffects), 0|1|(251<<24), NULL, NULL, NULL, 0 }, // Inst #2263 = STI
+ { 2264, 5, 0, 0, "STMXCSR", 0|(1<<TID::MayLoad)|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(1<<8)|(174<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2264 = STMXCSR
+ { 2265, 0, 0, 0, "STOSB", 0|(1<<TID::UnmodeledSideEffects), 0|1|(170<<24), ImplicitList54, ImplicitList35, NULL, 0 }, // Inst #2265 = STOSB
+ { 2266, 0, 0, 0, "STOSD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(171<<24), ImplicitList55, ImplicitList35, NULL, 0 }, // Inst #2266 = STOSD
+ { 2267, 0, 0, 0, "STOSW", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(171<<24), ImplicitList56, ImplicitList35, NULL, 0 }, // Inst #2267 = STOSW
+ { 2268, 5, 1, 0, "STRm", 0|(1<<TID::UnmodeledSideEffects), 0|25|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2268 = STRm
+ { 2269, 1, 1, 0, "STRr", 0|(1<<TID::UnmodeledSideEffects), 0|17|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2269 = STRr
+ { 2270, 5, 0, 0, "ST_F32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2270 = ST_F32m
+ { 2271, 5, 0, 0, "ST_F64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|26|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2271 = ST_F64m
+ { 2272, 5, 0, 0, "ST_FP32m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(217<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2272 = ST_FP32m
+ { 2273, 5, 0, 0, "ST_FP64m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|27|(221<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2273 = ST_FP64m
+ { 2274, 5, 0, 0, "ST_FP80m", 0|(1<<TID::MayStore)|(1<<TID::UnmodeledSideEffects), 0|31|(219<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2274 = ST_FP80m
+ { 2275, 1, 0, 0, "ST_FPrr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(216<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2275 = ST_FPrr
+ { 2276, 6, 0, 0, "ST_Fp32m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #2276 = ST_Fp32m
+ { 2277, 6, 0, 0, "ST_Fp64m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2277 = ST_Fp64m
+ { 2278, 6, 0, 0, "ST_Fp64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2278 = ST_Fp64m32
+ { 2279, 6, 0, 0, "ST_Fp80m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2279 = ST_Fp80m32
+ { 2280, 6, 0, 0, "ST_Fp80m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2280 = ST_Fp80m64
+ { 2281, 6, 0, 0, "ST_FpP32m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo97 }, // Inst #2281 = ST_FpP32m
+ { 2282, 6, 0, 0, "ST_FpP64m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2282 = ST_FpP64m
+ { 2283, 6, 0, 0, "ST_FpP64m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo98 }, // Inst #2283 = ST_FpP64m32
+ { 2284, 6, 0, 0, "ST_FpP80m", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2284 = ST_FpP80m
+ { 2285, 6, 0, 0, "ST_FpP80m32", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2285 = ST_FpP80m32
+ { 2286, 6, 0, 0, "ST_FpP80m64", 0|(1<<TID::MayStore), 0|(2<<16), NULL, NULL, NULL, OperandInfo99 }, // Inst #2286 = ST_FpP80m64
+ { 2287, 1, 0, 0, "ST_Frr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(208<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2287 = ST_Frr
+ { 2288, 1, 0, 0, "SUB16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2288 = SUB16i16
+ { 2289, 6, 0, 0, "SUB16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2289 = SUB16mi
+ { 2290, 6, 0, 0, "SUB16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2290 = SUB16mi8
+ { 2291, 6, 0, 0, "SUB16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2291 = SUB16mr
+ { 2292, 3, 1, 0, "SUB16ri", 0, 0|21|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2292 = SUB16ri
+ { 2293, 3, 1, 0, "SUB16ri8", 0, 0|21|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2293 = SUB16ri8
+ { 2294, 7, 1, 0, "SUB16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2294 = SUB16rm
+ { 2295, 3, 1, 0, "SUB16rr", 0, 0|3|(1<<6)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2295 = SUB16rr
+ { 2296, 3, 1, 0, "SUB16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2296 = SUB16rr_REV
+ { 2297, 1, 0, 0, "SUB32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2297 = SUB32i32
+ { 2298, 6, 0, 0, "SUB32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2298 = SUB32mi
+ { 2299, 6, 0, 0, "SUB32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2299 = SUB32mi8
+ { 2300, 6, 0, 0, "SUB32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2300 = SUB32mr
+ { 2301, 3, 1, 0, "SUB32ri", 0, 0|21|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2301 = SUB32ri
+ { 2302, 3, 1, 0, "SUB32ri8", 0, 0|21|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2302 = SUB32ri8
+ { 2303, 7, 1, 0, "SUB32rm", 0|(1<<TID::MayLoad), 0|6|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2303 = SUB32rm
+ { 2304, 3, 1, 0, "SUB32rr", 0, 0|3|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2304 = SUB32rr
+ { 2305, 3, 1, 0, "SUB32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2305 = SUB32rr_REV
+ { 2306, 1, 0, 0, "SUB64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(45<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2306 = SUB64i32
+ { 2307, 6, 0, 0, "SUB64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2307 = SUB64mi32
+ { 2308, 6, 0, 0, "SUB64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2308 = SUB64mi8
+ { 2309, 6, 0, 0, "SUB64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2309 = SUB64mr
+ { 2310, 3, 1, 0, "SUB64ri32", 0, 0|21|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2310 = SUB64ri32
+ { 2311, 3, 1, 0, "SUB64ri8", 0, 0|21|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2311 = SUB64ri8
+ { 2312, 7, 1, 0, "SUB64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2312 = SUB64rm
+ { 2313, 3, 1, 0, "SUB64rr", 0, 0|3|(1<<12)|(41<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2313 = SUB64rr
+ { 2314, 3, 1, 0, "SUB64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(43<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2314 = SUB64rr_REV
+ { 2315, 1, 0, 0, "SUB8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(44<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2315 = SUB8i8
+ { 2316, 6, 0, 0, "SUB8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|29|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2316 = SUB8mi
+ { 2317, 6, 0, 0, "SUB8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2317 = SUB8mr
+ { 2318, 3, 1, 0, "SUB8ri", 0, 0|21|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2318 = SUB8ri
+ { 2319, 7, 1, 0, "SUB8rm", 0|(1<<TID::MayLoad), 0|6|(42<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2319 = SUB8rm
+ { 2320, 3, 1, 0, "SUB8rr", 0, 0|3|(40<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2320 = SUB8rr
+ { 2321, 3, 1, 0, "SUB8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(42<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2321 = SUB8rr_REV
+ { 2322, 7, 1, 0, "SUBPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2322 = SUBPDrm
+ { 2323, 3, 1, 0, "SUBPDrr", 0, 0|5|(1<<6)|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2323 = SUBPDrr
+ { 2324, 7, 1, 0, "SUBPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2324 = SUBPSrm
+ { 2325, 3, 1, 0, "SUBPSrr", 0, 0|5|(1<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2325 = SUBPSrr
+ { 2326, 5, 0, 0, "SUBR_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2326 = SUBR_F32m
+ { 2327, 5, 0, 0, "SUBR_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2327 = SUBR_F64m
+ { 2328, 5, 0, 0, "SUBR_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2328 = SUBR_FI16m
+ { 2329, 5, 0, 0, "SUBR_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|29|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2329 = SUBR_FI32m
+ { 2330, 1, 0, 0, "SUBR_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2330 = SUBR_FPrST0
+ { 2331, 1, 0, 0, "SUBR_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2331 = SUBR_FST0r
+ { 2332, 7, 1, 0, "SUBR_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2332 = SUBR_Fp32m
+ { 2333, 7, 1, 0, "SUBR_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2333 = SUBR_Fp64m
+ { 2334, 7, 1, 0, "SUBR_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2334 = SUBR_Fp64m32
+ { 2335, 7, 1, 0, "SUBR_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2335 = SUBR_Fp80m32
+ { 2336, 7, 1, 0, "SUBR_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2336 = SUBR_Fp80m64
+ { 2337, 7, 1, 0, "SUBR_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2337 = SUBR_FpI16m32
+ { 2338, 7, 1, 0, "SUBR_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2338 = SUBR_FpI16m64
+ { 2339, 7, 1, 0, "SUBR_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2339 = SUBR_FpI16m80
+ { 2340, 7, 1, 0, "SUBR_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2340 = SUBR_FpI32m32
+ { 2341, 7, 1, 0, "SUBR_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2341 = SUBR_FpI32m64
+ { 2342, 7, 1, 0, "SUBR_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2342 = SUBR_FpI32m80
+ { 2343, 1, 0, 0, "SUBR_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2343 = SUBR_FrST0
+ { 2344, 7, 1, 0, "SUBSDrm", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo26 }, // Inst #2344 = SUBSDrm
+ { 2345, 7, 1, 0, "SUBSDrm_Int", 0|(1<<TID::MayLoad), 0|6|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2345 = SUBSDrm_Int
+ { 2346, 3, 1, 0, "SUBSDrr", 0, 0|5|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo27 }, // Inst #2346 = SUBSDrr
+ { 2347, 3, 1, 0, "SUBSDrr_Int", 0, 0|5|(11<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2347 = SUBSDrr_Int
+ { 2348, 7, 1, 0, "SUBSSrm", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo28 }, // Inst #2348 = SUBSSrm
+ { 2349, 7, 1, 0, "SUBSSrm_Int", 0|(1<<TID::MayLoad), 0|6|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2349 = SUBSSrm_Int
+ { 2350, 3, 1, 0, "SUBSSrr", 0, 0|5|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo29 }, // Inst #2350 = SUBSSrr
+ { 2351, 3, 1, 0, "SUBSSrr_Int", 0, 0|5|(12<<8)|(92<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2351 = SUBSSrr_Int
+ { 2352, 5, 0, 0, "SUB_F32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(216<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2352 = SUB_F32m
+ { 2353, 5, 0, 0, "SUB_F64m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(220<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2353 = SUB_F64m
+ { 2354, 5, 0, 0, "SUB_FI16m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(222<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2354 = SUB_FI16m
+ { 2355, 5, 0, 0, "SUB_FI32m", 0|(1<<TID::MayLoad)|(1<<TID::UnmodeledSideEffects), 0|28|(218<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2355 = SUB_FI32m
+ { 2356, 1, 0, 0, "SUB_FPrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(9<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2356 = SUB_FPrST0
+ { 2357, 1, 0, 0, "SUB_FST0r", 0|(1<<TID::UnmodeledSideEffects), 0|2|(3<<8)|(224<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2357 = SUB_FST0r
+ { 2358, 3, 1, 0, "SUB_Fp32", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo32 }, // Inst #2358 = SUB_Fp32
+ { 2359, 7, 1, 0, "SUB_Fp32m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2359 = SUB_Fp32m
+ { 2360, 3, 1, 0, "SUB_Fp64", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo34 }, // Inst #2360 = SUB_Fp64
+ { 2361, 7, 1, 0, "SUB_Fp64m", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2361 = SUB_Fp64m
+ { 2362, 7, 1, 0, "SUB_Fp64m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2362 = SUB_Fp64m32
+ { 2363, 3, 1, 0, "SUB_Fp80", 0, 0|(4<<16), NULL, NULL, NULL, OperandInfo36 }, // Inst #2363 = SUB_Fp80
+ { 2364, 7, 1, 0, "SUB_Fp80m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2364 = SUB_Fp80m32
+ { 2365, 7, 1, 0, "SUB_Fp80m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2365 = SUB_Fp80m64
+ { 2366, 7, 1, 0, "SUB_FpI16m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2366 = SUB_FpI16m32
+ { 2367, 7, 1, 0, "SUB_FpI16m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2367 = SUB_FpI16m64
+ { 2368, 7, 1, 0, "SUB_FpI16m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2368 = SUB_FpI16m80
+ { 2369, 7, 1, 0, "SUB_FpI32m32", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo33 }, // Inst #2369 = SUB_FpI32m32
+ { 2370, 7, 1, 0, "SUB_FpI32m64", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo35 }, // Inst #2370 = SUB_FpI32m64
+ { 2371, 7, 1, 0, "SUB_FpI32m80", 0|(1<<TID::MayLoad), 0|(3<<16), NULL, NULL, NULL, OperandInfo37 }, // Inst #2371 = SUB_FpI32m80
+ { 2372, 1, 0, 0, "SUB_FrST0", 0|(1<<TID::UnmodeledSideEffects), 0|2|(7<<8)|(232<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2372 = SUB_FrST0
+ { 2373, 0, 0, 0, "SWAPGS", 0|(1<<TID::UnmodeledSideEffects), 0|41|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2373 = SWAPGS
+ { 2374, 0, 0, 0, "SYSCALL", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(5<<24), NULL, NULL, NULL, 0 }, // Inst #2374 = SYSCALL
+ { 2375, 0, 0, 0, "SYSENTER", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(52<<24), NULL, NULL, NULL, 0 }, // Inst #2375 = SYSENTER
+ { 2376, 0, 0, 0, "SYSEXIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(53<<24), NULL, NULL, NULL, 0 }, // Inst #2376 = SYSEXIT
+ { 2377, 0, 0, 0, "SYSEXIT64", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(1<<12)|(53<<24), NULL, NULL, NULL, 0 }, // Inst #2377 = SYSEXIT64
+ { 2378, 0, 0, 0, "SYSRET", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(7<<24), NULL, NULL, NULL, 0 }, // Inst #2378 = SYSRET
+ { 2379, 1, 0, 0, "TAILJMPd", 0|(1<<TID::Return)|(1<<TID::Branch)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(233<<24), NULL, NULL, NULL, OperandInfo5 }, // Inst #2379 = TAILJMPd
+ { 2380, 5, 0, 0, "TAILJMPm", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|28|(255<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2380 = TAILJMPm
+ { 2381, 1, 0, 0, "TAILJMPr", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2381 = TAILJMPr
+ { 2382, 1, 0, 0, "TAILJMPr64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|20|(255<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2382 = TAILJMPr64
+ { 2383, 2, 0, 0, "TCRETURNdi", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo38 }, // Inst #2383 = TCRETURNdi
+ { 2384, 2, 0, 0, "TCRETURNdi64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo38 }, // Inst #2384 = TCRETURNdi64
+ { 2385, 2, 0, 0, "TCRETURNri", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo55 }, // Inst #2385 = TCRETURNri
+ { 2386, 2, 0, 0, "TCRETURNri64", 0|(1<<TID::Return)|(1<<TID::Barrier)|(1<<TID::Call)|(1<<TID::Terminator)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0, NULL, NULL, NULL, OperandInfo56 }, // Inst #2386 = TCRETURNri64
+ { 2387, 1, 0, 0, "TEST16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2387 = TEST16i16
+ { 2388, 6, 0, 0, "TEST16mi", 0|(1<<TID::MayLoad), 0|24|(1<<6)|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2388 = TEST16mi
+ { 2389, 2, 0, 0, "TEST16ri", 0, 0|16|(1<<6)|(3<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo54 }, // Inst #2389 = TEST16ri
+ { 2390, 6, 0, 0, "TEST16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo46 }, // Inst #2390 = TEST16rm
+ { 2391, 2, 0, 0, "TEST16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo47 }, // Inst #2391 = TEST16rr
+ { 2392, 1, 0, 0, "TEST32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2392 = TEST32i32
+ { 2393, 6, 0, 0, "TEST32mi", 0|(1<<TID::MayLoad), 0|24|(4<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2393 = TEST32mi
+ { 2394, 2, 0, 0, "TEST32ri", 0, 0|16|(4<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo55 }, // Inst #2394 = TEST32ri
+ { 2395, 6, 0, 0, "TEST32rm", 0|(1<<TID::MayLoad), 0|6|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo48 }, // Inst #2395 = TEST32rm
+ { 2396, 2, 0, 0, "TEST32rr", 0|(1<<TID::Commutable), 0|3|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo49 }, // Inst #2396 = TEST32rr
+ { 2397, 1, 0, 0, "TEST64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(169<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2397 = TEST64i32
+ { 2398, 6, 0, 0, "TEST64mi32", 0|(1<<TID::MayLoad), 0|24|(1<<12)|(4<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2398 = TEST64mi32
+ { 2399, 2, 0, 0, "TEST64ri32", 0, 0|16|(1<<12)|(4<<13)|(247<<24), NULL, ImplicitList1, Barriers1, OperandInfo56 }, // Inst #2399 = TEST64ri32
+ { 2400, 6, 0, 0, "TEST64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo50 }, // Inst #2400 = TEST64rm
+ { 2401, 2, 0, 0, "TEST64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(133<<24), NULL, ImplicitList1, Barriers1, OperandInfo51 }, // Inst #2401 = TEST64rr
+ { 2402, 1, 0, 0, "TEST8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(168<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2402 = TEST8i8
+ { 2403, 6, 0, 0, "TEST8mi", 0|(1<<TID::MayLoad), 0|24|(1<<13)|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2403 = TEST8mi
+ { 2404, 2, 0, 0, "TEST8ri", 0, 0|16|(1<<13)|(246<<24), NULL, ImplicitList1, Barriers1, OperandInfo68 }, // Inst #2404 = TEST8ri
+ { 2405, 6, 0, 0, "TEST8rm", 0|(1<<TID::MayLoad), 0|6|(132<<24), NULL, ImplicitList1, Barriers1, OperandInfo69 }, // Inst #2405 = TEST8rm
+ { 2406, 2, 0, 0, "TEST8rr", 0|(1<<TID::Commutable), 0|3|(132<<24), NULL, ImplicitList1, Barriers1, OperandInfo67 }, // Inst #2406 = TEST8rr
+ { 2407, 4, 0, 0, "TLS_addr32", 0, 0, ImplicitList2, ImplicitList9, Barriers3, OperandInfo197 }, // Inst #2407 = TLS_addr32
+ { 2408, 4, 0, 0, "TLS_addr64", 0, 0, ImplicitList4, ImplicitList10, Barriers4, OperandInfo198 }, // Inst #2408 = TLS_addr64
+ { 2409, 0, 0, 0, "TRAP", 0|(1<<TID::Barrier)|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(11<<24), NULL, NULL, NULL, 0 }, // Inst #2409 = TRAP
+ { 2410, 0, 0, 0, "TST_F", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<8)|(228<<24), NULL, NULL, NULL, 0 }, // Inst #2410 = TST_F
+ { 2411, 1, 0, 0, "TST_Fp32", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo100 }, // Inst #2411 = TST_Fp32
+ { 2412, 1, 0, 0, "TST_Fp64", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo101 }, // Inst #2412 = TST_Fp64
+ { 2413, 1, 0, 0, "TST_Fp80", 0, 0|(2<<16), NULL, NULL, NULL, OperandInfo102 }, // Inst #2413 = TST_Fp80
+ { 2414, 6, 0, 0, "UCOMISDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo82 }, // Inst #2414 = UCOMISDrm
+ { 2415, 2, 0, 0, "UCOMISDrr", 0, 0|5|(1<<6)|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo105 }, // Inst #2415 = UCOMISDrr
+ { 2416, 6, 0, 0, "UCOMISSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo80 }, // Inst #2416 = UCOMISSrm
+ { 2417, 2, 0, 0, "UCOMISSrr", 0, 0|5|(1<<8)|(46<<24), NULL, ImplicitList1, Barriers1, OperandInfo106 }, // Inst #2417 = UCOMISSrr
+ { 2418, 1, 0, 0, "UCOM_FIPr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(10<<8)|(232<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2418 = UCOM_FIPr
+ { 2419, 1, 0, 0, "UCOM_FIr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(6<<8)|(232<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2419 = UCOM_FIr
+ { 2420, 0, 0, 0, "UCOM_FPPr", 0|(1<<TID::UnmodeledSideEffects), 0|1|(5<<8)|(233<<24), ImplicitList24, ImplicitList1, Barriers1, 0 }, // Inst #2420 = UCOM_FPPr
+ { 2421, 1, 0, 0, "UCOM_FPr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(232<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2421 = UCOM_FPr
+ { 2422, 2, 0, 0, "UCOM_FpIr32", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #2422 = UCOM_FpIr32
+ { 2423, 2, 0, 0, "UCOM_FpIr64", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #2423 = UCOM_FpIr64
+ { 2424, 2, 0, 0, "UCOM_FpIr80", 0, 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #2424 = UCOM_FpIr80
+ { 2425, 2, 0, 0, "UCOM_Fpr32", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo2 }, // Inst #2425 = UCOM_Fpr32
+ { 2426, 2, 0, 0, "UCOM_Fpr64", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo3 }, // Inst #2426 = UCOM_Fpr64
+ { 2427, 2, 0, 0, "UCOM_Fpr80", 0|(1<<TID::UnmodeledSideEffects), 0|(5<<16), NULL, ImplicitList1, Barriers1, OperandInfo4 }, // Inst #2427 = UCOM_Fpr80
+ { 2428, 1, 0, 0, "UCOM_Fr", 0|(1<<TID::UnmodeledSideEffects), 0|2|(8<<8)|(224<<24), ImplicitList24, ImplicitList1, Barriers1, OperandInfo31 }, // Inst #2428 = UCOM_Fr
+ { 2429, 7, 1, 0, "UNPCKHPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2429 = UNPCKHPDrm
+ { 2430, 3, 1, 0, "UNPCKHPDrr", 0, 0|5|(1<<6)|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2430 = UNPCKHPDrr
+ { 2431, 7, 1, 0, "UNPCKHPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2431 = UNPCKHPSrm
+ { 2432, 3, 1, 0, "UNPCKHPSrr", 0, 0|5|(1<<8)|(21<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2432 = UNPCKHPSrr
+ { 2433, 7, 1, 0, "UNPCKLPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2433 = UNPCKLPDrm
+ { 2434, 3, 1, 0, "UNPCKLPDrr", 0, 0|5|(1<<6)|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2434 = UNPCKLPDrr
+ { 2435, 7, 1, 0, "UNPCKLPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2435 = UNPCKLPSrm
+ { 2436, 3, 1, 0, "UNPCKLPSrr", 0, 0|5|(1<<8)|(20<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2436 = UNPCKLPSrr
+ { 2437, 3, 0, 0, "VASTART_SAVE_XMM_REGS", 0|(1<<TID::UsesCustomInserter)|(1<<TID::Variadic), 0, NULL, NULL, NULL, OperandInfo199 }, // Inst #2437 = VASTART_SAVE_XMM_REGS
+ { 2438, 5, 0, 0, "VERRm", 0|(1<<TID::UnmodeledSideEffects), 0|28|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2438 = VERRm
+ { 2439, 1, 0, 0, "VERRr", 0|(1<<TID::UnmodeledSideEffects), 0|20|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2439 = VERRr
+ { 2440, 5, 0, 0, "VERWm", 0|(1<<TID::UnmodeledSideEffects), 0|29|(1<<8), NULL, NULL, NULL, OperandInfo30 }, // Inst #2440 = VERWm
+ { 2441, 1, 0, 0, "VERWr", 0|(1<<TID::UnmodeledSideEffects), 0|21|(1<<8), NULL, NULL, NULL, OperandInfo93 }, // Inst #2441 = VERWr
+ { 2442, 0, 0, 0, "VMCALL", 0|(1<<TID::UnmodeledSideEffects), 0|33|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2442 = VMCALL
+ { 2443, 5, 0, 0, "VMCLEARm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<6)|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2443 = VMCLEARm
+ { 2444, 0, 0, 0, "VMLAUNCH", 0|(1<<TID::UnmodeledSideEffects), 0|34|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2444 = VMLAUNCH
+ { 2445, 5, 0, 0, "VMPTRLDm", 0|(1<<TID::UnmodeledSideEffects), 0|30|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2445 = VMPTRLDm
+ { 2446, 5, 1, 0, "VMPTRSTm", 0|(1<<TID::UnmodeledSideEffects), 0|31|(1<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2446 = VMPTRSTm
+ { 2447, 6, 1, 0, "VMREAD32rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #2447 = VMREAD32rm
+ { 2448, 2, 1, 0, "VMREAD32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2448 = VMREAD32rr
+ { 2449, 6, 1, 0, "VMREAD64rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #2449 = VMREAD64rm
+ { 2450, 2, 1, 0, "VMREAD64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(120<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2450 = VMREAD64rr
+ { 2451, 0, 0, 0, "VMRESUME", 0|(1<<TID::UnmodeledSideEffects), 0|35|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2451 = VMRESUME
+ { 2452, 6, 1, 0, "VMWRITE32rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo48 }, // Inst #2452 = VMWRITE32rm
+ { 2453, 2, 1, 0, "VMWRITE32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2453 = VMWRITE32rr
+ { 2454, 6, 1, 0, "VMWRITE64rm", 0|(1<<TID::UnmodeledSideEffects), 0|6|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo50 }, // Inst #2454 = VMWRITE64rm
+ { 2455, 2, 1, 0, "VMWRITE64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<8)|(121<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2455 = VMWRITE64rr
+ { 2456, 0, 0, 0, "VMXOFF", 0|(1<<TID::UnmodeledSideEffects), 0|36|(1<<8)|(1<<24), NULL, NULL, NULL, 0 }, // Inst #2456 = VMXOFF
+ { 2457, 5, 0, 0, "VMXON", 0|(1<<TID::UnmodeledSideEffects), 0|30|(11<<8)|(199<<24), NULL, NULL, NULL, OperandInfo30 }, // Inst #2457 = VMXON
+ { 2458, 1, 1, 0, "V_SET0", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo200 }, // Inst #2458 = V_SET0
+ { 2459, 1, 1, 0, "V_SETALLONES", 0|(1<<TID::FoldableAsLoad)|(1<<TID::Rematerializable)|(1<<TID::CheapAsAMove), 0|32|(1<<6)|(1<<8)|(118<<24), NULL, NULL, NULL, OperandInfo200 }, // Inst #2459 = V_SETALLONES
+ { 2460, 0, 0, 0, "WAIT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(155<<24), NULL, NULL, NULL, 0 }, // Inst #2460 = WAIT
+ { 2461, 0, 0, 0, "WBINVD", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(9<<24), NULL, NULL, NULL, 0 }, // Inst #2461 = WBINVD
+ { 2462, 5, 0, 0, "WINCALL64m", 0|(1<<TID::Call)|(1<<TID::MayLoad)|(1<<TID::Variadic), 0|26|(255<<24), ImplicitList4, ImplicitList57, Barriers8, OperandInfo30 }, // Inst #2462 = WINCALL64m
+ { 2463, 1, 0, 0, "WINCALL64pcrel32", 0|(1<<TID::Call)|(1<<TID::Variadic)|(1<<TID::UnmodeledSideEffects), 0|1|(232<<24), ImplicitList4, ImplicitList57, Barriers8, OperandInfo5 }, // Inst #2463 = WINCALL64pcrel32
+ { 2464, 1, 0, 0, "WINCALL64r", 0|(1<<TID::Call)|(1<<TID::Variadic), 0|18|(255<<24), ImplicitList4, ImplicitList57, Barriers8, OperandInfo58 }, // Inst #2464 = WINCALL64r
+ { 2465, 0, 0, 0, "WRMSR", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<8)|(48<<24), NULL, NULL, NULL, 0 }, // Inst #2465 = WRMSR
+ { 2466, 6, 0, 0, "XADD16rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<6)|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo7 }, // Inst #2466 = XADD16rm
+ { 2467, 2, 1, 0, "XADD16rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<6)|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo47 }, // Inst #2467 = XADD16rr
+ { 2468, 6, 0, 0, "XADD32rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo11 }, // Inst #2468 = XADD32rm
+ { 2469, 2, 1, 0, "XADD32rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(193<<24), NULL, NULL, NULL, OperandInfo49 }, // Inst #2469 = XADD32rr
+ { 2470, 6, 0, 0, "XADD64rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(1<<12)|(193<<24), NULL, NULL, NULL, OperandInfo15 }, // Inst #2470 = XADD64rm
+ { 2471, 2, 1, 0, "XADD64rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(1<<12)|(193<<24), NULL, NULL, NULL, OperandInfo51 }, // Inst #2471 = XADD64rr
+ { 2472, 6, 0, 0, "XADD8rm", 0|(1<<TID::UnmodeledSideEffects), 0|4|(1<<8)|(192<<24), NULL, NULL, NULL, OperandInfo20 }, // Inst #2472 = XADD8rm
+ { 2473, 2, 1, 0, "XADD8rr", 0|(1<<TID::UnmodeledSideEffects), 0|3|(1<<8)|(192<<24), NULL, NULL, NULL, OperandInfo67 }, // Inst #2473 = XADD8rr
+ { 2474, 1, 0, 0, "XCHG16ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(1<<6)|(144<<24), NULL, NULL, NULL, OperandInfo93 }, // Inst #2474 = XCHG16ar
+ { 2475, 7, 1, 0, "XCHG16rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<6)|(135<<24), NULL, NULL, NULL, OperandInfo9 }, // Inst #2475 = XCHG16rm
+ { 2476, 3, 1, 0, "XCHG16rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(135<<24), NULL, NULL, NULL, OperandInfo10 }, // Inst #2476 = XCHG16rr
+ { 2477, 1, 0, 0, "XCHG32ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(144<<24), NULL, NULL, NULL, OperandInfo57 }, // Inst #2477 = XCHG32ar
+ { 2478, 7, 1, 0, "XCHG32rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(135<<24), NULL, NULL, NULL, OperandInfo13 }, // Inst #2478 = XCHG32rm
+ { 2479, 3, 1, 0, "XCHG32rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(135<<24), NULL, NULL, NULL, OperandInfo14 }, // Inst #2479 = XCHG32rr
+ { 2480, 1, 0, 0, "XCHG64ar", 0|(1<<TID::UnmodeledSideEffects), 0|2|(1<<12)|(144<<24), NULL, NULL, NULL, OperandInfo58 }, // Inst #2480 = XCHG64ar
+ { 2481, 7, 1, 0, "XCHG64rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(1<<12)|(135<<24), NULL, NULL, NULL, OperandInfo17 }, // Inst #2481 = XCHG64rm
+ { 2482, 3, 1, 0, "XCHG64rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(135<<24), NULL, NULL, NULL, OperandInfo18 }, // Inst #2482 = XCHG64rr
+ { 2483, 7, 1, 0, "XCHG8rm", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|6|(134<<24), NULL, NULL, NULL, OperandInfo22 }, // Inst #2483 = XCHG8rm
+ { 2484, 3, 1, 0, "XCHG8rr", 0|(1<<TID::UnmodeledSideEffects), 0|5|(134<<24), NULL, NULL, NULL, OperandInfo23 }, // Inst #2484 = XCHG8rr
+ { 2485, 1, 0, 0, "XCH_F", 0|(1<<TID::UnmodeledSideEffects), 0|2|(4<<8)|(200<<24), NULL, NULL, NULL, OperandInfo31 }, // Inst #2485 = XCH_F
+ { 2486, 0, 0, 0, "XLAT", 0|(1<<TID::UnmodeledSideEffects), 0|1|(215<<24), NULL, NULL, NULL, 0 }, // Inst #2486 = XLAT
+ { 2487, 1, 0, 0, "XOR16i16", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<6)|(3<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2487 = XOR16i16
+ { 2488, 6, 0, 0, "XOR16mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2488 = XOR16mi
+ { 2489, 6, 0, 0, "XOR16mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2489 = XOR16mi8
+ { 2490, 6, 0, 0, "XOR16mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo7 }, // Inst #2490 = XOR16mr
+ { 2491, 3, 1, 0, "XOR16ri", 0, 0|22|(1<<6)|(3<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2491 = XOR16ri
+ { 2492, 3, 1, 0, "XOR16ri8", 0, 0|22|(1<<6)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo8 }, // Inst #2492 = XOR16ri8
+ { 2493, 7, 1, 0, "XOR16rm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo9 }, // Inst #2493 = XOR16rm
+ { 2494, 3, 1, 0, "XOR16rr", 0|(1<<TID::Commutable), 0|3|(1<<6)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2494 = XOR16rr
+ { 2495, 3, 1, 0, "XOR16rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<6)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo10 }, // Inst #2495 = XOR16rr_REV
+ { 2496, 1, 0, 0, "XOR32i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(4<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2496 = XOR32i32
+ { 2497, 6, 0, 0, "XOR32mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2497 = XOR32mi
+ { 2498, 6, 0, 0, "XOR32mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2498 = XOR32mi8
+ { 2499, 6, 0, 0, "XOR32mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo11 }, // Inst #2499 = XOR32mr
+ { 2500, 3, 1, 0, "XOR32ri", 0, 0|22|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2500 = XOR32ri
+ { 2501, 3, 1, 0, "XOR32ri8", 0, 0|22|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo12 }, // Inst #2501 = XOR32ri8
+ { 2502, 7, 1, 0, "XOR32rm", 0|(1<<TID::MayLoad), 0|6|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo13 }, // Inst #2502 = XOR32rm
+ { 2503, 3, 1, 0, "XOR32rr", 0|(1<<TID::Commutable), 0|3|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2503 = XOR32rr
+ { 2504, 3, 1, 0, "XOR32rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo14 }, // Inst #2504 = XOR32rr_REV
+ { 2505, 1, 0, 0, "XOR64i32", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<12)|(4<<13)|(53<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2505 = XOR64i32
+ { 2506, 6, 0, 0, "XOR64mi32", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2506 = XOR64mi32
+ { 2507, 6, 0, 0, "XOR64mi8", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2507 = XOR64mi8
+ { 2508, 6, 0, 0, "XOR64mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(1<<12)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo15 }, // Inst #2508 = XOR64mr
+ { 2509, 3, 1, 0, "XOR64ri32", 0, 0|22|(1<<12)|(4<<13)|(129<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2509 = XOR64ri32
+ { 2510, 3, 1, 0, "XOR64ri8", 0, 0|22|(1<<12)|(1<<13)|(131<<24), NULL, ImplicitList1, Barriers1, OperandInfo16 }, // Inst #2510 = XOR64ri8
+ { 2511, 7, 1, 0, "XOR64rm", 0|(1<<TID::MayLoad), 0|6|(1<<12)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo17 }, // Inst #2511 = XOR64rm
+ { 2512, 3, 1, 0, "XOR64rr", 0|(1<<TID::Commutable), 0|3|(1<<12)|(49<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2512 = XOR64rr
+ { 2513, 3, 1, 0, "XOR64rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(1<<12)|(51<<24), NULL, ImplicitList1, Barriers1, OperandInfo18 }, // Inst #2513 = XOR64rr_REV
+ { 2514, 1, 0, 0, "XOR8i8", 0|(1<<TID::UnmodeledSideEffects), 0|1|(1<<13)|(52<<24), NULL, ImplicitList1, Barriers1, OperandInfo5 }, // Inst #2514 = XOR8i8
+ { 2515, 6, 0, 0, "XOR8mi", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|30|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo6 }, // Inst #2515 = XOR8mi
+ { 2516, 6, 0, 0, "XOR8mr", 0|(1<<TID::MayLoad)|(1<<TID::MayStore), 0|4|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo20 }, // Inst #2516 = XOR8mr
+ { 2517, 3, 1, 0, "XOR8ri", 0, 0|22|(1<<13)|(128<<24), NULL, ImplicitList1, Barriers1, OperandInfo21 }, // Inst #2517 = XOR8ri
+ { 2518, 7, 1, 0, "XOR8rm", 0|(1<<TID::MayLoad), 0|6|(50<<24), NULL, ImplicitList1, Barriers1, OperandInfo22 }, // Inst #2518 = XOR8rm
+ { 2519, 3, 1, 0, "XOR8rr", 0|(1<<TID::Commutable), 0|3|(48<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2519 = XOR8rr
+ { 2520, 3, 1, 0, "XOR8rr_REV", 0|(1<<TID::UnmodeledSideEffects), 0|5|(50<<24), NULL, ImplicitList1, Barriers1, OperandInfo23 }, // Inst #2520 = XOR8rr_REV
+ { 2521, 7, 1, 0, "XORPDrm", 0|(1<<TID::MayLoad), 0|6|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2521 = XORPDrm
+ { 2522, 3, 1, 0, "XORPDrr", 0|(1<<TID::Commutable), 0|5|(1<<6)|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2522 = XORPDrr
+ { 2523, 7, 1, 0, "XORPSrm", 0|(1<<TID::MayLoad), 0|6|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo24 }, // Inst #2523 = XORPSrm
+ { 2524, 3, 1, 0, "XORPSrr", 0|(1<<TID::Commutable), 0|5|(1<<8)|(87<<24), NULL, NULL, NULL, OperandInfo25 }, // Inst #2524 = XORPSrr
};
} // End llvm namespace
diff --git a/libclamav/c++/X86GenInstrNames.inc b/libclamav/c++/X86GenInstrNames.inc
index f8ebc6b..549a87e 100644
--- a/libclamav/c++/X86GenInstrNames.inc
+++ b/libclamav/c++/X86GenInstrNames.inc
@@ -1091,1450 +1091,1451 @@ namespace X86 {
MAXSSrr = 1078,
MAXSSrr_Int = 1079,
MFENCE = 1080,
- MINPDrm = 1081,
- MINPDrm_Int = 1082,
- MINPDrr = 1083,
- MINPDrr_Int = 1084,
- MINPSrm = 1085,
- MINPSrm_Int = 1086,
- MINPSrr = 1087,
- MINPSrr_Int = 1088,
- MINSDrm = 1089,
- MINSDrm_Int = 1090,
- MINSDrr = 1091,
- MINSDrr_Int = 1092,
- MINSSrm = 1093,
- MINSSrm_Int = 1094,
- MINSSrr = 1095,
- MINSSrr_Int = 1096,
- MMX_CVTPD2PIrm = 1097,
- MMX_CVTPD2PIrr = 1098,
- MMX_CVTPI2PDrm = 1099,
- MMX_CVTPI2PDrr = 1100,
- MMX_CVTPI2PSrm = 1101,
- MMX_CVTPI2PSrr = 1102,
- MMX_CVTPS2PIrm = 1103,
- MMX_CVTPS2PIrr = 1104,
- MMX_CVTTPD2PIrm = 1105,
- MMX_CVTTPD2PIrr = 1106,
- MMX_CVTTPS2PIrm = 1107,
- MMX_CVTTPS2PIrr = 1108,
- MMX_EMMS = 1109,
- MMX_FEMMS = 1110,
- MMX_MASKMOVQ = 1111,
- MMX_MASKMOVQ64 = 1112,
- MMX_MOVD64from64rr = 1113,
- MMX_MOVD64grr = 1114,
- MMX_MOVD64mr = 1115,
- MMX_MOVD64rm = 1116,
- MMX_MOVD64rr = 1117,
- MMX_MOVD64rrv164 = 1118,
- MMX_MOVD64to64rr = 1119,
- MMX_MOVDQ2Qrr = 1120,
- MMX_MOVNTQmr = 1121,
- MMX_MOVQ2DQrr = 1122,
- MMX_MOVQ2FR64rr = 1123,
- MMX_MOVQ64gmr = 1124,
- MMX_MOVQ64mr = 1125,
- MMX_MOVQ64rm = 1126,
- MMX_MOVQ64rr = 1127,
- MMX_MOVZDI2PDIrm = 1128,
- MMX_MOVZDI2PDIrr = 1129,
- MMX_PACKSSDWrm = 1130,
- MMX_PACKSSDWrr = 1131,
- MMX_PACKSSWBrm = 1132,
- MMX_PACKSSWBrr = 1133,
- MMX_PACKUSWBrm = 1134,
- MMX_PACKUSWBrr = 1135,
- MMX_PADDBrm = 1136,
- MMX_PADDBrr = 1137,
- MMX_PADDDrm = 1138,
- MMX_PADDDrr = 1139,
- MMX_PADDQrm = 1140,
- MMX_PADDQrr = 1141,
- MMX_PADDSBrm = 1142,
- MMX_PADDSBrr = 1143,
- MMX_PADDSWrm = 1144,
- MMX_PADDSWrr = 1145,
- MMX_PADDUSBrm = 1146,
- MMX_PADDUSBrr = 1147,
- MMX_PADDUSWrm = 1148,
- MMX_PADDUSWrr = 1149,
- MMX_PADDWrm = 1150,
- MMX_PADDWrr = 1151,
- MMX_PANDNrm = 1152,
- MMX_PANDNrr = 1153,
- MMX_PANDrm = 1154,
- MMX_PANDrr = 1155,
- MMX_PAVGBrm = 1156,
- MMX_PAVGBrr = 1157,
- MMX_PAVGWrm = 1158,
- MMX_PAVGWrr = 1159,
- MMX_PCMPEQBrm = 1160,
- MMX_PCMPEQBrr = 1161,
- MMX_PCMPEQDrm = 1162,
- MMX_PCMPEQDrr = 1163,
- MMX_PCMPEQWrm = 1164,
- MMX_PCMPEQWrr = 1165,
- MMX_PCMPGTBrm = 1166,
- MMX_PCMPGTBrr = 1167,
- MMX_PCMPGTDrm = 1168,
- MMX_PCMPGTDrr = 1169,
- MMX_PCMPGTWrm = 1170,
- MMX_PCMPGTWrr = 1171,
- MMX_PEXTRWri = 1172,
- MMX_PINSRWrmi = 1173,
- MMX_PINSRWrri = 1174,
- MMX_PMADDWDrm = 1175,
- MMX_PMADDWDrr = 1176,
- MMX_PMAXSWrm = 1177,
- MMX_PMAXSWrr = 1178,
- MMX_PMAXUBrm = 1179,
- MMX_PMAXUBrr = 1180,
- MMX_PMINSWrm = 1181,
- MMX_PMINSWrr = 1182,
- MMX_PMINUBrm = 1183,
- MMX_PMINUBrr = 1184,
- MMX_PMOVMSKBrr = 1185,
- MMX_PMULHUWrm = 1186,
- MMX_PMULHUWrr = 1187,
- MMX_PMULHWrm = 1188,
- MMX_PMULHWrr = 1189,
- MMX_PMULLWrm = 1190,
- MMX_PMULLWrr = 1191,
- MMX_PMULUDQrm = 1192,
- MMX_PMULUDQrr = 1193,
- MMX_PORrm = 1194,
- MMX_PORrr = 1195,
- MMX_PSADBWrm = 1196,
- MMX_PSADBWrr = 1197,
- MMX_PSHUFWmi = 1198,
- MMX_PSHUFWri = 1199,
- MMX_PSLLDri = 1200,
- MMX_PSLLDrm = 1201,
- MMX_PSLLDrr = 1202,
- MMX_PSLLQri = 1203,
- MMX_PSLLQrm = 1204,
- MMX_PSLLQrr = 1205,
- MMX_PSLLWri = 1206,
- MMX_PSLLWrm = 1207,
- MMX_PSLLWrr = 1208,
- MMX_PSRADri = 1209,
- MMX_PSRADrm = 1210,
- MMX_PSRADrr = 1211,
- MMX_PSRAWri = 1212,
- MMX_PSRAWrm = 1213,
- MMX_PSRAWrr = 1214,
- MMX_PSRLDri = 1215,
- MMX_PSRLDrm = 1216,
- MMX_PSRLDrr = 1217,
- MMX_PSRLQri = 1218,
- MMX_PSRLQrm = 1219,
- MMX_PSRLQrr = 1220,
- MMX_PSRLWri = 1221,
- MMX_PSRLWrm = 1222,
- MMX_PSRLWrr = 1223,
- MMX_PSUBBrm = 1224,
- MMX_PSUBBrr = 1225,
- MMX_PSUBDrm = 1226,
- MMX_PSUBDrr = 1227,
- MMX_PSUBQrm = 1228,
- MMX_PSUBQrr = 1229,
- MMX_PSUBSBrm = 1230,
- MMX_PSUBSBrr = 1231,
- MMX_PSUBSWrm = 1232,
- MMX_PSUBSWrr = 1233,
- MMX_PSUBUSBrm = 1234,
- MMX_PSUBUSBrr = 1235,
- MMX_PSUBUSWrm = 1236,
- MMX_PSUBUSWrr = 1237,
- MMX_PSUBWrm = 1238,
- MMX_PSUBWrr = 1239,
- MMX_PUNPCKHBWrm = 1240,
- MMX_PUNPCKHBWrr = 1241,
- MMX_PUNPCKHDQrm = 1242,
- MMX_PUNPCKHDQrr = 1243,
- MMX_PUNPCKHWDrm = 1244,
- MMX_PUNPCKHWDrr = 1245,
- MMX_PUNPCKLBWrm = 1246,
- MMX_PUNPCKLBWrr = 1247,
- MMX_PUNPCKLDQrm = 1248,
- MMX_PUNPCKLDQrr = 1249,
- MMX_PUNPCKLWDrm = 1250,
- MMX_PUNPCKLWDrr = 1251,
- MMX_PXORrm = 1252,
- MMX_PXORrr = 1253,
- MMX_V_SET0 = 1254,
- MMX_V_SETALLONES = 1255,
- MONITOR = 1256,
- MOV16ao16 = 1257,
- MOV16mi = 1258,
- MOV16mr = 1259,
- MOV16ms = 1260,
- MOV16o16a = 1261,
- MOV16r0 = 1262,
- MOV16ri = 1263,
- MOV16rm = 1264,
- MOV16rr = 1265,
- MOV16rr_REV = 1266,
- MOV16rs = 1267,
- MOV16sm = 1268,
- MOV16sr = 1269,
- MOV32ao32 = 1270,
- MOV32cr = 1271,
- MOV32dr = 1272,
- MOV32mi = 1273,
- MOV32mr = 1274,
- MOV32o32a = 1275,
- MOV32r0 = 1276,
- MOV32rc = 1277,
- MOV32rd = 1278,
- MOV32ri = 1279,
- MOV32rm = 1280,
- MOV32rr = 1281,
- MOV32rr_REV = 1282,
- MOV64FSrm = 1283,
- MOV64GSrm = 1284,
- MOV64ao64 = 1285,
- MOV64ao8 = 1286,
- MOV64cr = 1287,
- MOV64dr = 1288,
- MOV64mi32 = 1289,
- MOV64mr = 1290,
- MOV64ms = 1291,
- MOV64o64a = 1292,
- MOV64o8a = 1293,
- MOV64r0 = 1294,
- MOV64rc = 1295,
- MOV64rd = 1296,
- MOV64ri = 1297,
- MOV64ri32 = 1298,
- MOV64ri64i32 = 1299,
- MOV64rm = 1300,
- MOV64rr = 1301,
- MOV64rr_REV = 1302,
- MOV64rs = 1303,
- MOV64sm = 1304,
- MOV64sr = 1305,
- MOV64toPQIrr = 1306,
- MOV64toSDrm = 1307,
- MOV64toSDrr = 1308,
- MOV8ao8 = 1309,
- MOV8mi = 1310,
- MOV8mr = 1311,
- MOV8mr_NOREX = 1312,
- MOV8o8a = 1313,
- MOV8r0 = 1314,
- MOV8ri = 1315,
- MOV8rm = 1316,
- MOV8rm_NOREX = 1317,
- MOV8rr = 1318,
- MOV8rr_NOREX = 1319,
- MOV8rr_REV = 1320,
- MOVAPDmr = 1321,
- MOVAPDrm = 1322,
- MOVAPDrr = 1323,
- MOVAPSmr = 1324,
- MOVAPSrm = 1325,
- MOVAPSrr = 1326,
- MOVDDUPrm = 1327,
- MOVDDUPrr = 1328,
- MOVDI2PDIrm = 1329,
- MOVDI2PDIrr = 1330,
- MOVDI2SSrm = 1331,
- MOVDI2SSrr = 1332,
- MOVDQAmr = 1333,
- MOVDQArm = 1334,
- MOVDQArr = 1335,
- MOVDQUmr = 1336,
- MOVDQUmr_Int = 1337,
- MOVDQUrm = 1338,
- MOVDQUrm_Int = 1339,
- MOVHLPSrr = 1340,
- MOVHPDmr = 1341,
- MOVHPDrm = 1342,
- MOVHPSmr = 1343,
- MOVHPSrm = 1344,
- MOVLHPSrr = 1345,
- MOVLPDmr = 1346,
- MOVLPDrm = 1347,
- MOVLPSmr = 1348,
- MOVLPSrm = 1349,
- MOVLQ128mr = 1350,
- MOVMSKPDrr = 1351,
- MOVMSKPSrr = 1352,
- MOVNTDQArm = 1353,
- MOVNTDQ_64mr = 1354,
- MOVNTDQmr = 1355,
- MOVNTDQmr_Int = 1356,
- MOVNTI_64mr = 1357,
- MOVNTImr = 1358,
- MOVNTImr_Int = 1359,
- MOVNTPDmr = 1360,
- MOVNTPDmr_Int = 1361,
- MOVNTPSmr = 1362,
- MOVNTPSmr_Int = 1363,
- MOVPC32r = 1364,
- MOVPDI2DImr = 1365,
- MOVPDI2DIrr = 1366,
- MOVPQI2QImr = 1367,
- MOVPQIto64rr = 1368,
- MOVQI2PQIrm = 1369,
- MOVQxrxr = 1370,
- MOVSB = 1371,
- MOVSD = 1372,
- MOVSDmr = 1373,
- MOVSDrm = 1374,
- MOVSDrr = 1375,
- MOVSDto64mr = 1376,
- MOVSDto64rr = 1377,
- MOVSHDUPrm = 1378,
- MOVSHDUPrr = 1379,
- MOVSLDUPrm = 1380,
- MOVSLDUPrr = 1381,
- MOVSS2DImr = 1382,
- MOVSS2DIrr = 1383,
- MOVSSmr = 1384,
- MOVSSrm = 1385,
- MOVSSrr = 1386,
- MOVSW = 1387,
- MOVSX16rm8 = 1388,
- MOVSX16rm8W = 1389,
- MOVSX16rr8 = 1390,
- MOVSX16rr8W = 1391,
- MOVSX32rm16 = 1392,
- MOVSX32rm8 = 1393,
- MOVSX32rr16 = 1394,
- MOVSX32rr8 = 1395,
- MOVSX64rm16 = 1396,
- MOVSX64rm32 = 1397,
- MOVSX64rm8 = 1398,
- MOVSX64rr16 = 1399,
- MOVSX64rr32 = 1400,
- MOVSX64rr8 = 1401,
- MOVUPDmr = 1402,
- MOVUPDmr_Int = 1403,
- MOVUPDrm = 1404,
- MOVUPDrm_Int = 1405,
- MOVUPDrr = 1406,
- MOVUPSmr = 1407,
- MOVUPSmr_Int = 1408,
- MOVUPSrm = 1409,
- MOVUPSrm_Int = 1410,
- MOVUPSrr = 1411,
- MOVZDI2PDIrm = 1412,
- MOVZDI2PDIrr = 1413,
- MOVZPQILo2PQIrm = 1414,
- MOVZPQILo2PQIrr = 1415,
- MOVZQI2PQIrm = 1416,
- MOVZQI2PQIrr = 1417,
- MOVZX16rm8 = 1418,
- MOVZX16rm8W = 1419,
- MOVZX16rr8 = 1420,
- MOVZX16rr8W = 1421,
- MOVZX32_NOREXrm8 = 1422,
- MOVZX32_NOREXrr8 = 1423,
- MOVZX32rm16 = 1424,
- MOVZX32rm8 = 1425,
- MOVZX32rr16 = 1426,
- MOVZX32rr8 = 1427,
- MOVZX64rm16 = 1428,
- MOVZX64rm16_Q = 1429,
- MOVZX64rm32 = 1430,
- MOVZX64rm8 = 1431,
- MOVZX64rm8_Q = 1432,
- MOVZX64rr16 = 1433,
- MOVZX64rr16_Q = 1434,
- MOVZX64rr32 = 1435,
- MOVZX64rr8 = 1436,
- MOVZX64rr8_Q = 1437,
- MOV_Fp3232 = 1438,
- MOV_Fp3264 = 1439,
- MOV_Fp3280 = 1440,
- MOV_Fp6432 = 1441,
- MOV_Fp6464 = 1442,
- MOV_Fp6480 = 1443,
- MOV_Fp8032 = 1444,
- MOV_Fp8064 = 1445,
- MOV_Fp8080 = 1446,
- MPSADBWrmi = 1447,
- MPSADBWrri = 1448,
- MUL16m = 1449,
- MUL16r = 1450,
- MUL32m = 1451,
- MUL32r = 1452,
- MUL64m = 1453,
- MUL64r = 1454,
- MUL8m = 1455,
- MUL8r = 1456,
- MULPDrm = 1457,
- MULPDrr = 1458,
- MULPSrm = 1459,
- MULPSrr = 1460,
- MULSDrm = 1461,
- MULSDrm_Int = 1462,
- MULSDrr = 1463,
- MULSDrr_Int = 1464,
- MULSSrm = 1465,
- MULSSrm_Int = 1466,
- MULSSrr = 1467,
- MULSSrr_Int = 1468,
- MUL_F32m = 1469,
- MUL_F64m = 1470,
- MUL_FI16m = 1471,
- MUL_FI32m = 1472,
- MUL_FPrST0 = 1473,
- MUL_FST0r = 1474,
- MUL_Fp32 = 1475,
- MUL_Fp32m = 1476,
- MUL_Fp64 = 1477,
- MUL_Fp64m = 1478,
- MUL_Fp64m32 = 1479,
- MUL_Fp80 = 1480,
- MUL_Fp80m32 = 1481,
- MUL_Fp80m64 = 1482,
- MUL_FpI16m32 = 1483,
- MUL_FpI16m64 = 1484,
- MUL_FpI16m80 = 1485,
- MUL_FpI32m32 = 1486,
- MUL_FpI32m64 = 1487,
- MUL_FpI32m80 = 1488,
- MUL_FrST0 = 1489,
- MWAIT = 1490,
- NEG16m = 1491,
- NEG16r = 1492,
- NEG32m = 1493,
- NEG32r = 1494,
- NEG64m = 1495,
- NEG64r = 1496,
- NEG8m = 1497,
- NEG8r = 1498,
- NOOP = 1499,
- NOOPL = 1500,
- NOOPW = 1501,
- NOT16m = 1502,
- NOT16r = 1503,
- NOT32m = 1504,
- NOT32r = 1505,
- NOT64m = 1506,
- NOT64r = 1507,
- NOT8m = 1508,
- NOT8r = 1509,
- OR16i16 = 1510,
- OR16mi = 1511,
- OR16mi8 = 1512,
- OR16mr = 1513,
- OR16ri = 1514,
- OR16ri8 = 1515,
- OR16rm = 1516,
- OR16rr = 1517,
- OR16rr_REV = 1518,
- OR32i32 = 1519,
- OR32mi = 1520,
- OR32mi8 = 1521,
- OR32mr = 1522,
- OR32ri = 1523,
- OR32ri8 = 1524,
- OR32rm = 1525,
- OR32rr = 1526,
- OR32rr_REV = 1527,
- OR64i32 = 1528,
- OR64mi32 = 1529,
- OR64mi8 = 1530,
- OR64mr = 1531,
- OR64ri32 = 1532,
- OR64ri8 = 1533,
- OR64rm = 1534,
- OR64rr = 1535,
- OR64rr_REV = 1536,
- OR8i8 = 1537,
- OR8mi = 1538,
- OR8mr = 1539,
- OR8ri = 1540,
- OR8rm = 1541,
- OR8rr = 1542,
- OR8rr_REV = 1543,
- ORPDrm = 1544,
- ORPDrr = 1545,
- ORPSrm = 1546,
- ORPSrr = 1547,
- OUT16ir = 1548,
- OUT16rr = 1549,
- OUT32ir = 1550,
- OUT32rr = 1551,
- OUT8ir = 1552,
- OUT8rr = 1553,
- OUTSB = 1554,
- OUTSD = 1555,
- OUTSW = 1556,
- PABSBrm128 = 1557,
- PABSBrm64 = 1558,
- PABSBrr128 = 1559,
- PABSBrr64 = 1560,
- PABSDrm128 = 1561,
- PABSDrm64 = 1562,
- PABSDrr128 = 1563,
- PABSDrr64 = 1564,
- PABSWrm128 = 1565,
- PABSWrm64 = 1566,
- PABSWrr128 = 1567,
- PABSWrr64 = 1568,
- PACKSSDWrm = 1569,
- PACKSSDWrr = 1570,
- PACKSSWBrm = 1571,
- PACKSSWBrr = 1572,
- PACKUSDWrm = 1573,
- PACKUSDWrr = 1574,
- PACKUSWBrm = 1575,
- PACKUSWBrr = 1576,
- PADDBrm = 1577,
- PADDBrr = 1578,
- PADDDrm = 1579,
- PADDDrr = 1580,
- PADDQrm = 1581,
- PADDQrr = 1582,
- PADDSBrm = 1583,
- PADDSBrr = 1584,
- PADDSWrm = 1585,
- PADDSWrr = 1586,
- PADDUSBrm = 1587,
- PADDUSBrr = 1588,
- PADDUSWrm = 1589,
- PADDUSWrr = 1590,
- PADDWrm = 1591,
- PADDWrr = 1592,
- PALIGNR128rm = 1593,
- PALIGNR128rr = 1594,
- PALIGNR64rm = 1595,
- PALIGNR64rr = 1596,
- PANDNrm = 1597,
- PANDNrr = 1598,
- PANDrm = 1599,
- PANDrr = 1600,
- PAVGBrm = 1601,
- PAVGBrr = 1602,
- PAVGWrm = 1603,
- PAVGWrr = 1604,
- PBLENDVBrm0 = 1605,
- PBLENDVBrr0 = 1606,
- PBLENDWrmi = 1607,
- PBLENDWrri = 1608,
- PCMPEQBrm = 1609,
- PCMPEQBrr = 1610,
- PCMPEQDrm = 1611,
- PCMPEQDrr = 1612,
- PCMPEQQrm = 1613,
- PCMPEQQrr = 1614,
- PCMPEQWrm = 1615,
- PCMPEQWrr = 1616,
- PCMPESTRIArm = 1617,
- PCMPESTRIArr = 1618,
- PCMPESTRICrm = 1619,
- PCMPESTRICrr = 1620,
- PCMPESTRIOrm = 1621,
- PCMPESTRIOrr = 1622,
- PCMPESTRISrm = 1623,
- PCMPESTRISrr = 1624,
- PCMPESTRIZrm = 1625,
- PCMPESTRIZrr = 1626,
- PCMPESTRIrm = 1627,
- PCMPESTRIrr = 1628,
- PCMPESTRM128MEM = 1629,
- PCMPESTRM128REG = 1630,
- PCMPESTRM128rm = 1631,
- PCMPESTRM128rr = 1632,
- PCMPGTBrm = 1633,
- PCMPGTBrr = 1634,
- PCMPGTDrm = 1635,
- PCMPGTDrr = 1636,
- PCMPGTQrm = 1637,
- PCMPGTQrr = 1638,
- PCMPGTWrm = 1639,
- PCMPGTWrr = 1640,
- PCMPISTRIArm = 1641,
- PCMPISTRIArr = 1642,
- PCMPISTRICrm = 1643,
- PCMPISTRICrr = 1644,
- PCMPISTRIOrm = 1645,
- PCMPISTRIOrr = 1646,
- PCMPISTRISrm = 1647,
- PCMPISTRISrr = 1648,
- PCMPISTRIZrm = 1649,
- PCMPISTRIZrr = 1650,
- PCMPISTRIrm = 1651,
- PCMPISTRIrr = 1652,
- PCMPISTRM128MEM = 1653,
- PCMPISTRM128REG = 1654,
- PCMPISTRM128rm = 1655,
- PCMPISTRM128rr = 1656,
- PEXTRBmr = 1657,
- PEXTRBrr = 1658,
- PEXTRDmr = 1659,
- PEXTRDrr = 1660,
- PEXTRQmr = 1661,
- PEXTRQrr = 1662,
- PEXTRWmr = 1663,
- PEXTRWri = 1664,
- PHADDDrm128 = 1665,
- PHADDDrm64 = 1666,
- PHADDDrr128 = 1667,
- PHADDDrr64 = 1668,
- PHADDSWrm128 = 1669,
- PHADDSWrm64 = 1670,
- PHADDSWrr128 = 1671,
- PHADDSWrr64 = 1672,
- PHADDWrm128 = 1673,
- PHADDWrm64 = 1674,
- PHADDWrr128 = 1675,
- PHADDWrr64 = 1676,
- PHMINPOSUWrm128 = 1677,
- PHMINPOSUWrr128 = 1678,
- PHSUBDrm128 = 1679,
- PHSUBDrm64 = 1680,
- PHSUBDrr128 = 1681,
- PHSUBDrr64 = 1682,
- PHSUBSWrm128 = 1683,
- PHSUBSWrm64 = 1684,
- PHSUBSWrr128 = 1685,
- PHSUBSWrr64 = 1686,
- PHSUBWrm128 = 1687,
- PHSUBWrm64 = 1688,
- PHSUBWrr128 = 1689,
- PHSUBWrr64 = 1690,
- PINSRBrm = 1691,
- PINSRBrr = 1692,
- PINSRDrm = 1693,
- PINSRDrr = 1694,
- PINSRQrm = 1695,
- PINSRQrr = 1696,
- PINSRWrmi = 1697,
- PINSRWrri = 1698,
- PMADDUBSWrm128 = 1699,
- PMADDUBSWrm64 = 1700,
- PMADDUBSWrr128 = 1701,
- PMADDUBSWrr64 = 1702,
- PMADDWDrm = 1703,
- PMADDWDrr = 1704,
- PMAXSBrm = 1705,
- PMAXSBrr = 1706,
- PMAXSDrm = 1707,
- PMAXSDrr = 1708,
- PMAXSWrm = 1709,
- PMAXSWrr = 1710,
- PMAXUBrm = 1711,
- PMAXUBrr = 1712,
- PMAXUDrm = 1713,
- PMAXUDrr = 1714,
- PMAXUWrm = 1715,
- PMAXUWrr = 1716,
- PMINSBrm = 1717,
- PMINSBrr = 1718,
- PMINSDrm = 1719,
- PMINSDrr = 1720,
- PMINSWrm = 1721,
- PMINSWrr = 1722,
- PMINUBrm = 1723,
- PMINUBrr = 1724,
- PMINUDrm = 1725,
- PMINUDrr = 1726,
- PMINUWrm = 1727,
- PMINUWrr = 1728,
- PMOVMSKBrr = 1729,
- PMOVSXBDrm = 1730,
- PMOVSXBDrr = 1731,
- PMOVSXBQrm = 1732,
- PMOVSXBQrr = 1733,
- PMOVSXBWrm = 1734,
- PMOVSXBWrr = 1735,
- PMOVSXDQrm = 1736,
- PMOVSXDQrr = 1737,
- PMOVSXWDrm = 1738,
- PMOVSXWDrr = 1739,
- PMOVSXWQrm = 1740,
- PMOVSXWQrr = 1741,
- PMOVZXBDrm = 1742,
- PMOVZXBDrr = 1743,
- PMOVZXBQrm = 1744,
- PMOVZXBQrr = 1745,
- PMOVZXBWrm = 1746,
- PMOVZXBWrr = 1747,
- PMOVZXDQrm = 1748,
- PMOVZXDQrr = 1749,
- PMOVZXWDrm = 1750,
- PMOVZXWDrr = 1751,
- PMOVZXWQrm = 1752,
- PMOVZXWQrr = 1753,
- PMULDQrm = 1754,
- PMULDQrr = 1755,
- PMULHRSWrm128 = 1756,
- PMULHRSWrm64 = 1757,
- PMULHRSWrr128 = 1758,
- PMULHRSWrr64 = 1759,
- PMULHUWrm = 1760,
- PMULHUWrr = 1761,
- PMULHWrm = 1762,
- PMULHWrr = 1763,
- PMULLDrm = 1764,
- PMULLDrm_int = 1765,
- PMULLDrr = 1766,
- PMULLDrr_int = 1767,
- PMULLWrm = 1768,
- PMULLWrr = 1769,
- PMULUDQrm = 1770,
- PMULUDQrr = 1771,
- POP16r = 1772,
- POP16rmm = 1773,
- POP16rmr = 1774,
- POP32r = 1775,
- POP32rmm = 1776,
- POP32rmr = 1777,
- POP64r = 1778,
- POP64rmm = 1779,
- POP64rmr = 1780,
- POPCNT16rm = 1781,
- POPCNT16rr = 1782,
- POPCNT32rm = 1783,
- POPCNT32rr = 1784,
- POPCNT64rm = 1785,
- POPCNT64rr = 1786,
- POPF = 1787,
- POPFD = 1788,
- POPFQ = 1789,
- POPFS16 = 1790,
- POPFS32 = 1791,
- POPFS64 = 1792,
- POPGS16 = 1793,
- POPGS32 = 1794,
- POPGS64 = 1795,
- PORrm = 1796,
- PORrr = 1797,
- PREFETCHNTA = 1798,
- PREFETCHT0 = 1799,
- PREFETCHT1 = 1800,
- PREFETCHT2 = 1801,
- PSADBWrm = 1802,
- PSADBWrr = 1803,
- PSHUFBrm128 = 1804,
- PSHUFBrm64 = 1805,
- PSHUFBrr128 = 1806,
- PSHUFBrr64 = 1807,
- PSHUFDmi = 1808,
- PSHUFDri = 1809,
- PSHUFHWmi = 1810,
- PSHUFHWri = 1811,
- PSHUFLWmi = 1812,
- PSHUFLWri = 1813,
- PSIGNBrm128 = 1814,
- PSIGNBrm64 = 1815,
- PSIGNBrr128 = 1816,
- PSIGNBrr64 = 1817,
- PSIGNDrm128 = 1818,
- PSIGNDrm64 = 1819,
- PSIGNDrr128 = 1820,
- PSIGNDrr64 = 1821,
- PSIGNWrm128 = 1822,
- PSIGNWrm64 = 1823,
- PSIGNWrr128 = 1824,
- PSIGNWrr64 = 1825,
- PSLLDQri = 1826,
- PSLLDri = 1827,
- PSLLDrm = 1828,
- PSLLDrr = 1829,
- PSLLQri = 1830,
- PSLLQrm = 1831,
- PSLLQrr = 1832,
- PSLLWri = 1833,
- PSLLWrm = 1834,
- PSLLWrr = 1835,
- PSRADri = 1836,
- PSRADrm = 1837,
- PSRADrr = 1838,
- PSRAWri = 1839,
- PSRAWrm = 1840,
- PSRAWrr = 1841,
- PSRLDQri = 1842,
- PSRLDri = 1843,
- PSRLDrm = 1844,
- PSRLDrr = 1845,
- PSRLQri = 1846,
- PSRLQrm = 1847,
- PSRLQrr = 1848,
- PSRLWri = 1849,
- PSRLWrm = 1850,
- PSRLWrr = 1851,
- PSUBBrm = 1852,
- PSUBBrr = 1853,
- PSUBDrm = 1854,
- PSUBDrr = 1855,
- PSUBQrm = 1856,
- PSUBQrr = 1857,
- PSUBSBrm = 1858,
- PSUBSBrr = 1859,
- PSUBSWrm = 1860,
- PSUBSWrr = 1861,
- PSUBUSBrm = 1862,
- PSUBUSBrr = 1863,
- PSUBUSWrm = 1864,
- PSUBUSWrr = 1865,
- PSUBWrm = 1866,
- PSUBWrr = 1867,
- PTESTrm = 1868,
- PTESTrr = 1869,
- PUNPCKHBWrm = 1870,
- PUNPCKHBWrr = 1871,
- PUNPCKHDQrm = 1872,
- PUNPCKHDQrr = 1873,
- PUNPCKHQDQrm = 1874,
- PUNPCKHQDQrr = 1875,
- PUNPCKHWDrm = 1876,
- PUNPCKHWDrr = 1877,
- PUNPCKLBWrm = 1878,
- PUNPCKLBWrr = 1879,
- PUNPCKLDQrm = 1880,
- PUNPCKLDQrr = 1881,
- PUNPCKLQDQrm = 1882,
- PUNPCKLQDQrr = 1883,
- PUNPCKLWDrm = 1884,
- PUNPCKLWDrr = 1885,
- PUSH16r = 1886,
- PUSH16rmm = 1887,
- PUSH16rmr = 1888,
- PUSH32i16 = 1889,
- PUSH32i32 = 1890,
- PUSH32i8 = 1891,
- PUSH32r = 1892,
- PUSH32rmm = 1893,
- PUSH32rmr = 1894,
- PUSH64i16 = 1895,
- PUSH64i32 = 1896,
- PUSH64i8 = 1897,
- PUSH64r = 1898,
- PUSH64rmm = 1899,
- PUSH64rmr = 1900,
- PUSHF = 1901,
- PUSHFD = 1902,
- PUSHFQ64 = 1903,
- PUSHFS16 = 1904,
- PUSHFS32 = 1905,
- PUSHFS64 = 1906,
- PUSHGS16 = 1907,
- PUSHGS32 = 1908,
- PUSHGS64 = 1909,
- PXORrm = 1910,
- PXORrr = 1911,
- RCL16m1 = 1912,
- RCL16mCL = 1913,
- RCL16mi = 1914,
- RCL16r1 = 1915,
- RCL16rCL = 1916,
- RCL16ri = 1917,
- RCL32m1 = 1918,
- RCL32mCL = 1919,
- RCL32mi = 1920,
- RCL32r1 = 1921,
- RCL32rCL = 1922,
- RCL32ri = 1923,
- RCL64m1 = 1924,
- RCL64mCL = 1925,
- RCL64mi = 1926,
- RCL64r1 = 1927,
- RCL64rCL = 1928,
- RCL64ri = 1929,
- RCL8m1 = 1930,
- RCL8mCL = 1931,
- RCL8mi = 1932,
- RCL8r1 = 1933,
- RCL8rCL = 1934,
- RCL8ri = 1935,
- RCPPSm = 1936,
- RCPPSm_Int = 1937,
- RCPPSr = 1938,
- RCPPSr_Int = 1939,
- RCPSSm = 1940,
- RCPSSm_Int = 1941,
- RCPSSr = 1942,
- RCPSSr_Int = 1943,
- RCR16m1 = 1944,
- RCR16mCL = 1945,
- RCR16mi = 1946,
- RCR16r1 = 1947,
- RCR16rCL = 1948,
- RCR16ri = 1949,
- RCR32m1 = 1950,
- RCR32mCL = 1951,
- RCR32mi = 1952,
- RCR32r1 = 1953,
- RCR32rCL = 1954,
- RCR32ri = 1955,
- RCR64m1 = 1956,
- RCR64mCL = 1957,
- RCR64mi = 1958,
- RCR64r1 = 1959,
- RCR64rCL = 1960,
- RCR64ri = 1961,
- RCR8m1 = 1962,
- RCR8mCL = 1963,
- RCR8mi = 1964,
- RCR8r1 = 1965,
- RCR8rCL = 1966,
- RCR8ri = 1967,
- RDMSR = 1968,
- RDPMC = 1969,
- RDTSC = 1970,
- RDTSCP = 1971,
- REPNE_PREFIX = 1972,
- REP_MOVSB = 1973,
- REP_MOVSD = 1974,
- REP_MOVSQ = 1975,
- REP_MOVSW = 1976,
- REP_PREFIX = 1977,
- REP_STOSB = 1978,
- REP_STOSD = 1979,
- REP_STOSQ = 1980,
- REP_STOSW = 1981,
- RET = 1982,
- RETI = 1983,
- ROL16m1 = 1984,
- ROL16mCL = 1985,
- ROL16mi = 1986,
- ROL16r1 = 1987,
- ROL16rCL = 1988,
- ROL16ri = 1989,
- ROL32m1 = 1990,
- ROL32mCL = 1991,
- ROL32mi = 1992,
- ROL32r1 = 1993,
- ROL32rCL = 1994,
- ROL32ri = 1995,
- ROL64m1 = 1996,
- ROL64mCL = 1997,
- ROL64mi = 1998,
- ROL64r1 = 1999,
- ROL64rCL = 2000,
- ROL64ri = 2001,
- ROL8m1 = 2002,
- ROL8mCL = 2003,
- ROL8mi = 2004,
- ROL8r1 = 2005,
- ROL8rCL = 2006,
- ROL8ri = 2007,
- ROR16m1 = 2008,
- ROR16mCL = 2009,
- ROR16mi = 2010,
- ROR16r1 = 2011,
- ROR16rCL = 2012,
- ROR16ri = 2013,
- ROR32m1 = 2014,
- ROR32mCL = 2015,
- ROR32mi = 2016,
- ROR32r1 = 2017,
- ROR32rCL = 2018,
- ROR32ri = 2019,
- ROR64m1 = 2020,
- ROR64mCL = 2021,
- ROR64mi = 2022,
- ROR64r1 = 2023,
- ROR64rCL = 2024,
- ROR64ri = 2025,
- ROR8m1 = 2026,
- ROR8mCL = 2027,
- ROR8mi = 2028,
- ROR8r1 = 2029,
- ROR8rCL = 2030,
- ROR8ri = 2031,
- ROUNDPDm_Int = 2032,
- ROUNDPDr_Int = 2033,
- ROUNDPSm_Int = 2034,
- ROUNDPSr_Int = 2035,
- ROUNDSDm_Int = 2036,
- ROUNDSDr_Int = 2037,
- ROUNDSSm_Int = 2038,
- ROUNDSSr_Int = 2039,
- RSM = 2040,
- RSQRTPSm = 2041,
- RSQRTPSm_Int = 2042,
- RSQRTPSr = 2043,
- RSQRTPSr_Int = 2044,
- RSQRTSSm = 2045,
- RSQRTSSm_Int = 2046,
- RSQRTSSr = 2047,
- RSQRTSSr_Int = 2048,
- SAHF = 2049,
- SAR16m1 = 2050,
- SAR16mCL = 2051,
- SAR16mi = 2052,
- SAR16r1 = 2053,
- SAR16rCL = 2054,
- SAR16ri = 2055,
- SAR32m1 = 2056,
- SAR32mCL = 2057,
- SAR32mi = 2058,
- SAR32r1 = 2059,
- SAR32rCL = 2060,
- SAR32ri = 2061,
- SAR64m1 = 2062,
- SAR64mCL = 2063,
- SAR64mi = 2064,
- SAR64r1 = 2065,
- SAR64rCL = 2066,
- SAR64ri = 2067,
- SAR8m1 = 2068,
- SAR8mCL = 2069,
- SAR8mi = 2070,
- SAR8r1 = 2071,
- SAR8rCL = 2072,
- SAR8ri = 2073,
- SBB16i16 = 2074,
- SBB16mi = 2075,
- SBB16mi8 = 2076,
- SBB16mr = 2077,
- SBB16ri = 2078,
- SBB16ri8 = 2079,
- SBB16rm = 2080,
- SBB16rr = 2081,
- SBB16rr_REV = 2082,
- SBB32i32 = 2083,
- SBB32mi = 2084,
- SBB32mi8 = 2085,
- SBB32mr = 2086,
- SBB32ri = 2087,
- SBB32ri8 = 2088,
- SBB32rm = 2089,
- SBB32rr = 2090,
- SBB32rr_REV = 2091,
- SBB64i32 = 2092,
- SBB64mi32 = 2093,
- SBB64mi8 = 2094,
- SBB64mr = 2095,
- SBB64ri32 = 2096,
- SBB64ri8 = 2097,
- SBB64rm = 2098,
- SBB64rr = 2099,
- SBB64rr_REV = 2100,
- SBB8i8 = 2101,
- SBB8mi = 2102,
- SBB8mr = 2103,
- SBB8ri = 2104,
- SBB8rm = 2105,
- SBB8rr = 2106,
- SBB8rr_REV = 2107,
- SCAS16 = 2108,
- SCAS32 = 2109,
- SCAS64 = 2110,
- SCAS8 = 2111,
- SETAEm = 2112,
- SETAEr = 2113,
- SETAm = 2114,
- SETAr = 2115,
- SETBEm = 2116,
- SETBEr = 2117,
- SETB_C16r = 2118,
- SETB_C32r = 2119,
- SETB_C64r = 2120,
- SETB_C8r = 2121,
- SETBm = 2122,
- SETBr = 2123,
- SETEm = 2124,
- SETEr = 2125,
- SETGEm = 2126,
- SETGEr = 2127,
- SETGm = 2128,
- SETGr = 2129,
- SETLEm = 2130,
- SETLEr = 2131,
- SETLm = 2132,
- SETLr = 2133,
- SETNEm = 2134,
- SETNEr = 2135,
- SETNOm = 2136,
- SETNOr = 2137,
- SETNPm = 2138,
- SETNPr = 2139,
- SETNSm = 2140,
- SETNSr = 2141,
- SETOm = 2142,
- SETOr = 2143,
- SETPm = 2144,
- SETPr = 2145,
- SETSm = 2146,
- SETSr = 2147,
- SFENCE = 2148,
- SGDTm = 2149,
- SHL16m1 = 2150,
- SHL16mCL = 2151,
- SHL16mi = 2152,
- SHL16r1 = 2153,
- SHL16rCL = 2154,
- SHL16ri = 2155,
- SHL32m1 = 2156,
- SHL32mCL = 2157,
- SHL32mi = 2158,
- SHL32r1 = 2159,
- SHL32rCL = 2160,
- SHL32ri = 2161,
- SHL64m1 = 2162,
- SHL64mCL = 2163,
- SHL64mi = 2164,
- SHL64r1 = 2165,
- SHL64rCL = 2166,
- SHL64ri = 2167,
- SHL8m1 = 2168,
- SHL8mCL = 2169,
- SHL8mi = 2170,
- SHL8r1 = 2171,
- SHL8rCL = 2172,
- SHL8ri = 2173,
- SHLD16mrCL = 2174,
- SHLD16mri8 = 2175,
- SHLD16rrCL = 2176,
- SHLD16rri8 = 2177,
- SHLD32mrCL = 2178,
- SHLD32mri8 = 2179,
- SHLD32rrCL = 2180,
- SHLD32rri8 = 2181,
- SHLD64mrCL = 2182,
- SHLD64mri8 = 2183,
- SHLD64rrCL = 2184,
- SHLD64rri8 = 2185,
- SHR16m1 = 2186,
- SHR16mCL = 2187,
- SHR16mi = 2188,
- SHR16r1 = 2189,
- SHR16rCL = 2190,
- SHR16ri = 2191,
- SHR32m1 = 2192,
- SHR32mCL = 2193,
- SHR32mi = 2194,
- SHR32r1 = 2195,
- SHR32rCL = 2196,
- SHR32ri = 2197,
- SHR64m1 = 2198,
- SHR64mCL = 2199,
- SHR64mi = 2200,
- SHR64r1 = 2201,
- SHR64rCL = 2202,
- SHR64ri = 2203,
- SHR8m1 = 2204,
- SHR8mCL = 2205,
- SHR8mi = 2206,
- SHR8r1 = 2207,
- SHR8rCL = 2208,
- SHR8ri = 2209,
- SHRD16mrCL = 2210,
- SHRD16mri8 = 2211,
- SHRD16rrCL = 2212,
- SHRD16rri8 = 2213,
- SHRD32mrCL = 2214,
- SHRD32mri8 = 2215,
- SHRD32rrCL = 2216,
- SHRD32rri8 = 2217,
- SHRD64mrCL = 2218,
- SHRD64mri8 = 2219,
- SHRD64rrCL = 2220,
- SHRD64rri8 = 2221,
- SHUFPDrmi = 2222,
- SHUFPDrri = 2223,
- SHUFPSrmi = 2224,
- SHUFPSrri = 2225,
- SIDTm = 2226,
- SIN_F = 2227,
- SIN_Fp32 = 2228,
- SIN_Fp64 = 2229,
- SIN_Fp80 = 2230,
- SLDT16m = 2231,
- SLDT16r = 2232,
- SLDT64m = 2233,
- SLDT64r = 2234,
- SMSW16m = 2235,
- SMSW16r = 2236,
- SMSW32r = 2237,
- SMSW64r = 2238,
- SQRTPDm = 2239,
- SQRTPDm_Int = 2240,
- SQRTPDr = 2241,
- SQRTPDr_Int = 2242,
- SQRTPSm = 2243,
- SQRTPSm_Int = 2244,
- SQRTPSr = 2245,
- SQRTPSr_Int = 2246,
- SQRTSDm = 2247,
- SQRTSDm_Int = 2248,
- SQRTSDr = 2249,
- SQRTSDr_Int = 2250,
- SQRTSSm = 2251,
- SQRTSSm_Int = 2252,
- SQRTSSr = 2253,
- SQRTSSr_Int = 2254,
- SQRT_F = 2255,
- SQRT_Fp32 = 2256,
- SQRT_Fp64 = 2257,
- SQRT_Fp80 = 2258,
- SS_PREFIX = 2259,
- STC = 2260,
- STD = 2261,
- STI = 2262,
- STMXCSR = 2263,
- STOSB = 2264,
- STOSD = 2265,
- STOSW = 2266,
- STRm = 2267,
- STRr = 2268,
- ST_F32m = 2269,
- ST_F64m = 2270,
- ST_FP32m = 2271,
- ST_FP64m = 2272,
- ST_FP80m = 2273,
- ST_FPrr = 2274,
- ST_Fp32m = 2275,
- ST_Fp64m = 2276,
- ST_Fp64m32 = 2277,
- ST_Fp80m32 = 2278,
- ST_Fp80m64 = 2279,
- ST_FpP32m = 2280,
- ST_FpP64m = 2281,
- ST_FpP64m32 = 2282,
- ST_FpP80m = 2283,
- ST_FpP80m32 = 2284,
- ST_FpP80m64 = 2285,
- ST_Frr = 2286,
- SUB16i16 = 2287,
- SUB16mi = 2288,
- SUB16mi8 = 2289,
- SUB16mr = 2290,
- SUB16ri = 2291,
- SUB16ri8 = 2292,
- SUB16rm = 2293,
- SUB16rr = 2294,
- SUB16rr_REV = 2295,
- SUB32i32 = 2296,
- SUB32mi = 2297,
- SUB32mi8 = 2298,
- SUB32mr = 2299,
- SUB32ri = 2300,
- SUB32ri8 = 2301,
- SUB32rm = 2302,
- SUB32rr = 2303,
- SUB32rr_REV = 2304,
- SUB64i32 = 2305,
- SUB64mi32 = 2306,
- SUB64mi8 = 2307,
- SUB64mr = 2308,
- SUB64ri32 = 2309,
- SUB64ri8 = 2310,
- SUB64rm = 2311,
- SUB64rr = 2312,
- SUB64rr_REV = 2313,
- SUB8i8 = 2314,
- SUB8mi = 2315,
- SUB8mr = 2316,
- SUB8ri = 2317,
- SUB8rm = 2318,
- SUB8rr = 2319,
- SUB8rr_REV = 2320,
- SUBPDrm = 2321,
- SUBPDrr = 2322,
- SUBPSrm = 2323,
- SUBPSrr = 2324,
- SUBR_F32m = 2325,
- SUBR_F64m = 2326,
- SUBR_FI16m = 2327,
- SUBR_FI32m = 2328,
- SUBR_FPrST0 = 2329,
- SUBR_FST0r = 2330,
- SUBR_Fp32m = 2331,
- SUBR_Fp64m = 2332,
- SUBR_Fp64m32 = 2333,
- SUBR_Fp80m32 = 2334,
- SUBR_Fp80m64 = 2335,
- SUBR_FpI16m32 = 2336,
- SUBR_FpI16m64 = 2337,
- SUBR_FpI16m80 = 2338,
- SUBR_FpI32m32 = 2339,
- SUBR_FpI32m64 = 2340,
- SUBR_FpI32m80 = 2341,
- SUBR_FrST0 = 2342,
- SUBSDrm = 2343,
- SUBSDrm_Int = 2344,
- SUBSDrr = 2345,
- SUBSDrr_Int = 2346,
- SUBSSrm = 2347,
- SUBSSrm_Int = 2348,
- SUBSSrr = 2349,
- SUBSSrr_Int = 2350,
- SUB_F32m = 2351,
- SUB_F64m = 2352,
- SUB_FI16m = 2353,
- SUB_FI32m = 2354,
- SUB_FPrST0 = 2355,
- SUB_FST0r = 2356,
- SUB_Fp32 = 2357,
- SUB_Fp32m = 2358,
- SUB_Fp64 = 2359,
- SUB_Fp64m = 2360,
- SUB_Fp64m32 = 2361,
- SUB_Fp80 = 2362,
- SUB_Fp80m32 = 2363,
- SUB_Fp80m64 = 2364,
- SUB_FpI16m32 = 2365,
- SUB_FpI16m64 = 2366,
- SUB_FpI16m80 = 2367,
- SUB_FpI32m32 = 2368,
- SUB_FpI32m64 = 2369,
- SUB_FpI32m80 = 2370,
- SUB_FrST0 = 2371,
- SWAPGS = 2372,
- SYSCALL = 2373,
- SYSENTER = 2374,
- SYSEXIT = 2375,
- SYSEXIT64 = 2376,
- SYSRET = 2377,
- TAILJMPd = 2378,
- TAILJMPm = 2379,
- TAILJMPr = 2380,
- TAILJMPr64 = 2381,
- TCRETURNdi = 2382,
- TCRETURNdi64 = 2383,
- TCRETURNri = 2384,
- TCRETURNri64 = 2385,
- TEST16i16 = 2386,
- TEST16mi = 2387,
- TEST16ri = 2388,
- TEST16rm = 2389,
- TEST16rr = 2390,
- TEST32i32 = 2391,
- TEST32mi = 2392,
- TEST32ri = 2393,
- TEST32rm = 2394,
- TEST32rr = 2395,
- TEST64i32 = 2396,
- TEST64mi32 = 2397,
- TEST64ri32 = 2398,
- TEST64rm = 2399,
- TEST64rr = 2400,
- TEST8i8 = 2401,
- TEST8mi = 2402,
- TEST8ri = 2403,
- TEST8rm = 2404,
- TEST8rr = 2405,
- TLS_addr32 = 2406,
- TLS_addr64 = 2407,
- TRAP = 2408,
- TST_F = 2409,
- TST_Fp32 = 2410,
- TST_Fp64 = 2411,
- TST_Fp80 = 2412,
- UCOMISDrm = 2413,
- UCOMISDrr = 2414,
- UCOMISSrm = 2415,
- UCOMISSrr = 2416,
- UCOM_FIPr = 2417,
- UCOM_FIr = 2418,
- UCOM_FPPr = 2419,
- UCOM_FPr = 2420,
- UCOM_FpIr32 = 2421,
- UCOM_FpIr64 = 2422,
- UCOM_FpIr80 = 2423,
- UCOM_Fpr32 = 2424,
- UCOM_Fpr64 = 2425,
- UCOM_Fpr80 = 2426,
- UCOM_Fr = 2427,
- UNPCKHPDrm = 2428,
- UNPCKHPDrr = 2429,
- UNPCKHPSrm = 2430,
- UNPCKHPSrr = 2431,
- UNPCKLPDrm = 2432,
- UNPCKLPDrr = 2433,
- UNPCKLPSrm = 2434,
- UNPCKLPSrr = 2435,
- VASTART_SAVE_XMM_REGS = 2436,
- VERRm = 2437,
- VERRr = 2438,
- VERWm = 2439,
- VERWr = 2440,
- VMCALL = 2441,
- VMCLEARm = 2442,
- VMLAUNCH = 2443,
- VMPTRLDm = 2444,
- VMPTRSTm = 2445,
- VMREAD32rm = 2446,
- VMREAD32rr = 2447,
- VMREAD64rm = 2448,
- VMREAD64rr = 2449,
- VMRESUME = 2450,
- VMWRITE32rm = 2451,
- VMWRITE32rr = 2452,
- VMWRITE64rm = 2453,
- VMWRITE64rr = 2454,
- VMXOFF = 2455,
- VMXON = 2456,
- V_SET0 = 2457,
- V_SETALLONES = 2458,
- WAIT = 2459,
- WBINVD = 2460,
- WINCALL64m = 2461,
- WINCALL64pcrel32 = 2462,
- WINCALL64r = 2463,
- WRMSR = 2464,
- XADD16rm = 2465,
- XADD16rr = 2466,
- XADD32rm = 2467,
- XADD32rr = 2468,
- XADD64rm = 2469,
- XADD64rr = 2470,
- XADD8rm = 2471,
- XADD8rr = 2472,
- XCHG16ar = 2473,
- XCHG16rm = 2474,
- XCHG16rr = 2475,
- XCHG32ar = 2476,
- XCHG32rm = 2477,
- XCHG32rr = 2478,
- XCHG64ar = 2479,
- XCHG64rm = 2480,
- XCHG64rr = 2481,
- XCHG8rm = 2482,
- XCHG8rr = 2483,
- XCH_F = 2484,
- XLAT = 2485,
- XOR16i16 = 2486,
- XOR16mi = 2487,
- XOR16mi8 = 2488,
- XOR16mr = 2489,
- XOR16ri = 2490,
- XOR16ri8 = 2491,
- XOR16rm = 2492,
- XOR16rr = 2493,
- XOR16rr_REV = 2494,
- XOR32i32 = 2495,
- XOR32mi = 2496,
- XOR32mi8 = 2497,
- XOR32mr = 2498,
- XOR32ri = 2499,
- XOR32ri8 = 2500,
- XOR32rm = 2501,
- XOR32rr = 2502,
- XOR32rr_REV = 2503,
- XOR64i32 = 2504,
- XOR64mi32 = 2505,
- XOR64mi8 = 2506,
- XOR64mr = 2507,
- XOR64ri32 = 2508,
- XOR64ri8 = 2509,
- XOR64rm = 2510,
- XOR64rr = 2511,
- XOR64rr_REV = 2512,
- XOR8i8 = 2513,
- XOR8mi = 2514,
- XOR8mr = 2515,
- XOR8ri = 2516,
- XOR8rm = 2517,
- XOR8rr = 2518,
- XOR8rr_REV = 2519,
- XORPDrm = 2520,
- XORPDrr = 2521,
- XORPSrm = 2522,
- XORPSrr = 2523,
- INSTRUCTION_LIST_END = 2524
+ MINGW_ALLOCA = 1081,
+ MINPDrm = 1082,
+ MINPDrm_Int = 1083,
+ MINPDrr = 1084,
+ MINPDrr_Int = 1085,
+ MINPSrm = 1086,
+ MINPSrm_Int = 1087,
+ MINPSrr = 1088,
+ MINPSrr_Int = 1089,
+ MINSDrm = 1090,
+ MINSDrm_Int = 1091,
+ MINSDrr = 1092,
+ MINSDrr_Int = 1093,
+ MINSSrm = 1094,
+ MINSSrm_Int = 1095,
+ MINSSrr = 1096,
+ MINSSrr_Int = 1097,
+ MMX_CVTPD2PIrm = 1098,
+ MMX_CVTPD2PIrr = 1099,
+ MMX_CVTPI2PDrm = 1100,
+ MMX_CVTPI2PDrr = 1101,
+ MMX_CVTPI2PSrm = 1102,
+ MMX_CVTPI2PSrr = 1103,
+ MMX_CVTPS2PIrm = 1104,
+ MMX_CVTPS2PIrr = 1105,
+ MMX_CVTTPD2PIrm = 1106,
+ MMX_CVTTPD2PIrr = 1107,
+ MMX_CVTTPS2PIrm = 1108,
+ MMX_CVTTPS2PIrr = 1109,
+ MMX_EMMS = 1110,
+ MMX_FEMMS = 1111,
+ MMX_MASKMOVQ = 1112,
+ MMX_MASKMOVQ64 = 1113,
+ MMX_MOVD64from64rr = 1114,
+ MMX_MOVD64grr = 1115,
+ MMX_MOVD64mr = 1116,
+ MMX_MOVD64rm = 1117,
+ MMX_MOVD64rr = 1118,
+ MMX_MOVD64rrv164 = 1119,
+ MMX_MOVD64to64rr = 1120,
+ MMX_MOVDQ2Qrr = 1121,
+ MMX_MOVNTQmr = 1122,
+ MMX_MOVQ2DQrr = 1123,
+ MMX_MOVQ2FR64rr = 1124,
+ MMX_MOVQ64gmr = 1125,
+ MMX_MOVQ64mr = 1126,
+ MMX_MOVQ64rm = 1127,
+ MMX_MOVQ64rr = 1128,
+ MMX_MOVZDI2PDIrm = 1129,
+ MMX_MOVZDI2PDIrr = 1130,
+ MMX_PACKSSDWrm = 1131,
+ MMX_PACKSSDWrr = 1132,
+ MMX_PACKSSWBrm = 1133,
+ MMX_PACKSSWBrr = 1134,
+ MMX_PACKUSWBrm = 1135,
+ MMX_PACKUSWBrr = 1136,
+ MMX_PADDBrm = 1137,
+ MMX_PADDBrr = 1138,
+ MMX_PADDDrm = 1139,
+ MMX_PADDDrr = 1140,
+ MMX_PADDQrm = 1141,
+ MMX_PADDQrr = 1142,
+ MMX_PADDSBrm = 1143,
+ MMX_PADDSBrr = 1144,
+ MMX_PADDSWrm = 1145,
+ MMX_PADDSWrr = 1146,
+ MMX_PADDUSBrm = 1147,
+ MMX_PADDUSBrr = 1148,
+ MMX_PADDUSWrm = 1149,
+ MMX_PADDUSWrr = 1150,
+ MMX_PADDWrm = 1151,
+ MMX_PADDWrr = 1152,
+ MMX_PANDNrm = 1153,
+ MMX_PANDNrr = 1154,
+ MMX_PANDrm = 1155,
+ MMX_PANDrr = 1156,
+ MMX_PAVGBrm = 1157,
+ MMX_PAVGBrr = 1158,
+ MMX_PAVGWrm = 1159,
+ MMX_PAVGWrr = 1160,
+ MMX_PCMPEQBrm = 1161,
+ MMX_PCMPEQBrr = 1162,
+ MMX_PCMPEQDrm = 1163,
+ MMX_PCMPEQDrr = 1164,
+ MMX_PCMPEQWrm = 1165,
+ MMX_PCMPEQWrr = 1166,
+ MMX_PCMPGTBrm = 1167,
+ MMX_PCMPGTBrr = 1168,
+ MMX_PCMPGTDrm = 1169,
+ MMX_PCMPGTDrr = 1170,
+ MMX_PCMPGTWrm = 1171,
+ MMX_PCMPGTWrr = 1172,
+ MMX_PEXTRWri = 1173,
+ MMX_PINSRWrmi = 1174,
+ MMX_PINSRWrri = 1175,
+ MMX_PMADDWDrm = 1176,
+ MMX_PMADDWDrr = 1177,
+ MMX_PMAXSWrm = 1178,
+ MMX_PMAXSWrr = 1179,
+ MMX_PMAXUBrm = 1180,
+ MMX_PMAXUBrr = 1181,
+ MMX_PMINSWrm = 1182,
+ MMX_PMINSWrr = 1183,
+ MMX_PMINUBrm = 1184,
+ MMX_PMINUBrr = 1185,
+ MMX_PMOVMSKBrr = 1186,
+ MMX_PMULHUWrm = 1187,
+ MMX_PMULHUWrr = 1188,
+ MMX_PMULHWrm = 1189,
+ MMX_PMULHWrr = 1190,
+ MMX_PMULLWrm = 1191,
+ MMX_PMULLWrr = 1192,
+ MMX_PMULUDQrm = 1193,
+ MMX_PMULUDQrr = 1194,
+ MMX_PORrm = 1195,
+ MMX_PORrr = 1196,
+ MMX_PSADBWrm = 1197,
+ MMX_PSADBWrr = 1198,
+ MMX_PSHUFWmi = 1199,
+ MMX_PSHUFWri = 1200,
+ MMX_PSLLDri = 1201,
+ MMX_PSLLDrm = 1202,
+ MMX_PSLLDrr = 1203,
+ MMX_PSLLQri = 1204,
+ MMX_PSLLQrm = 1205,
+ MMX_PSLLQrr = 1206,
+ MMX_PSLLWri = 1207,
+ MMX_PSLLWrm = 1208,
+ MMX_PSLLWrr = 1209,
+ MMX_PSRADri = 1210,
+ MMX_PSRADrm = 1211,
+ MMX_PSRADrr = 1212,
+ MMX_PSRAWri = 1213,
+ MMX_PSRAWrm = 1214,
+ MMX_PSRAWrr = 1215,
+ MMX_PSRLDri = 1216,
+ MMX_PSRLDrm = 1217,
+ MMX_PSRLDrr = 1218,
+ MMX_PSRLQri = 1219,
+ MMX_PSRLQrm = 1220,
+ MMX_PSRLQrr = 1221,
+ MMX_PSRLWri = 1222,
+ MMX_PSRLWrm = 1223,
+ MMX_PSRLWrr = 1224,
+ MMX_PSUBBrm = 1225,
+ MMX_PSUBBrr = 1226,
+ MMX_PSUBDrm = 1227,
+ MMX_PSUBDrr = 1228,
+ MMX_PSUBQrm = 1229,
+ MMX_PSUBQrr = 1230,
+ MMX_PSUBSBrm = 1231,
+ MMX_PSUBSBrr = 1232,
+ MMX_PSUBSWrm = 1233,
+ MMX_PSUBSWrr = 1234,
+ MMX_PSUBUSBrm = 1235,
+ MMX_PSUBUSBrr = 1236,
+ MMX_PSUBUSWrm = 1237,
+ MMX_PSUBUSWrr = 1238,
+ MMX_PSUBWrm = 1239,
+ MMX_PSUBWrr = 1240,
+ MMX_PUNPCKHBWrm = 1241,
+ MMX_PUNPCKHBWrr = 1242,
+ MMX_PUNPCKHDQrm = 1243,
+ MMX_PUNPCKHDQrr = 1244,
+ MMX_PUNPCKHWDrm = 1245,
+ MMX_PUNPCKHWDrr = 1246,
+ MMX_PUNPCKLBWrm = 1247,
+ MMX_PUNPCKLBWrr = 1248,
+ MMX_PUNPCKLDQrm = 1249,
+ MMX_PUNPCKLDQrr = 1250,
+ MMX_PUNPCKLWDrm = 1251,
+ MMX_PUNPCKLWDrr = 1252,
+ MMX_PXORrm = 1253,
+ MMX_PXORrr = 1254,
+ MMX_V_SET0 = 1255,
+ MMX_V_SETALLONES = 1256,
+ MONITOR = 1257,
+ MOV16ao16 = 1258,
+ MOV16mi = 1259,
+ MOV16mr = 1260,
+ MOV16ms = 1261,
+ MOV16o16a = 1262,
+ MOV16r0 = 1263,
+ MOV16ri = 1264,
+ MOV16rm = 1265,
+ MOV16rr = 1266,
+ MOV16rr_REV = 1267,
+ MOV16rs = 1268,
+ MOV16sm = 1269,
+ MOV16sr = 1270,
+ MOV32ao32 = 1271,
+ MOV32cr = 1272,
+ MOV32dr = 1273,
+ MOV32mi = 1274,
+ MOV32mr = 1275,
+ MOV32o32a = 1276,
+ MOV32r0 = 1277,
+ MOV32rc = 1278,
+ MOV32rd = 1279,
+ MOV32ri = 1280,
+ MOV32rm = 1281,
+ MOV32rr = 1282,
+ MOV32rr_REV = 1283,
+ MOV64FSrm = 1284,
+ MOV64GSrm = 1285,
+ MOV64ao64 = 1286,
+ MOV64ao8 = 1287,
+ MOV64cr = 1288,
+ MOV64dr = 1289,
+ MOV64mi32 = 1290,
+ MOV64mr = 1291,
+ MOV64ms = 1292,
+ MOV64o64a = 1293,
+ MOV64o8a = 1294,
+ MOV64r0 = 1295,
+ MOV64rc = 1296,
+ MOV64rd = 1297,
+ MOV64ri = 1298,
+ MOV64ri32 = 1299,
+ MOV64ri64i32 = 1300,
+ MOV64rm = 1301,
+ MOV64rr = 1302,
+ MOV64rr_REV = 1303,
+ MOV64rs = 1304,
+ MOV64sm = 1305,
+ MOV64sr = 1306,
+ MOV64toPQIrr = 1307,
+ MOV64toSDrm = 1308,
+ MOV64toSDrr = 1309,
+ MOV8ao8 = 1310,
+ MOV8mi = 1311,
+ MOV8mr = 1312,
+ MOV8mr_NOREX = 1313,
+ MOV8o8a = 1314,
+ MOV8r0 = 1315,
+ MOV8ri = 1316,
+ MOV8rm = 1317,
+ MOV8rm_NOREX = 1318,
+ MOV8rr = 1319,
+ MOV8rr_NOREX = 1320,
+ MOV8rr_REV = 1321,
+ MOVAPDmr = 1322,
+ MOVAPDrm = 1323,
+ MOVAPDrr = 1324,
+ MOVAPSmr = 1325,
+ MOVAPSrm = 1326,
+ MOVAPSrr = 1327,
+ MOVDDUPrm = 1328,
+ MOVDDUPrr = 1329,
+ MOVDI2PDIrm = 1330,
+ MOVDI2PDIrr = 1331,
+ MOVDI2SSrm = 1332,
+ MOVDI2SSrr = 1333,
+ MOVDQAmr = 1334,
+ MOVDQArm = 1335,
+ MOVDQArr = 1336,
+ MOVDQUmr = 1337,
+ MOVDQUmr_Int = 1338,
+ MOVDQUrm = 1339,
+ MOVDQUrm_Int = 1340,
+ MOVHLPSrr = 1341,
+ MOVHPDmr = 1342,
+ MOVHPDrm = 1343,
+ MOVHPSmr = 1344,
+ MOVHPSrm = 1345,
+ MOVLHPSrr = 1346,
+ MOVLPDmr = 1347,
+ MOVLPDrm = 1348,
+ MOVLPSmr = 1349,
+ MOVLPSrm = 1350,
+ MOVLQ128mr = 1351,
+ MOVMSKPDrr = 1352,
+ MOVMSKPSrr = 1353,
+ MOVNTDQArm = 1354,
+ MOVNTDQ_64mr = 1355,
+ MOVNTDQmr = 1356,
+ MOVNTDQmr_Int = 1357,
+ MOVNTI_64mr = 1358,
+ MOVNTImr = 1359,
+ MOVNTImr_Int = 1360,
+ MOVNTPDmr = 1361,
+ MOVNTPDmr_Int = 1362,
+ MOVNTPSmr = 1363,
+ MOVNTPSmr_Int = 1364,
+ MOVPC32r = 1365,
+ MOVPDI2DImr = 1366,
+ MOVPDI2DIrr = 1367,
+ MOVPQI2QImr = 1368,
+ MOVPQIto64rr = 1369,
+ MOVQI2PQIrm = 1370,
+ MOVQxrxr = 1371,
+ MOVSB = 1372,
+ MOVSD = 1373,
+ MOVSDmr = 1374,
+ MOVSDrm = 1375,
+ MOVSDrr = 1376,
+ MOVSDto64mr = 1377,
+ MOVSDto64rr = 1378,
+ MOVSHDUPrm = 1379,
+ MOVSHDUPrr = 1380,
+ MOVSLDUPrm = 1381,
+ MOVSLDUPrr = 1382,
+ MOVSS2DImr = 1383,
+ MOVSS2DIrr = 1384,
+ MOVSSmr = 1385,
+ MOVSSrm = 1386,
+ MOVSSrr = 1387,
+ MOVSW = 1388,
+ MOVSX16rm8 = 1389,
+ MOVSX16rm8W = 1390,
+ MOVSX16rr8 = 1391,
+ MOVSX16rr8W = 1392,
+ MOVSX32rm16 = 1393,
+ MOVSX32rm8 = 1394,
+ MOVSX32rr16 = 1395,
+ MOVSX32rr8 = 1396,
+ MOVSX64rm16 = 1397,
+ MOVSX64rm32 = 1398,
+ MOVSX64rm8 = 1399,
+ MOVSX64rr16 = 1400,
+ MOVSX64rr32 = 1401,
+ MOVSX64rr8 = 1402,
+ MOVUPDmr = 1403,
+ MOVUPDmr_Int = 1404,
+ MOVUPDrm = 1405,
+ MOVUPDrm_Int = 1406,
+ MOVUPDrr = 1407,
+ MOVUPSmr = 1408,
+ MOVUPSmr_Int = 1409,
+ MOVUPSrm = 1410,
+ MOVUPSrm_Int = 1411,
+ MOVUPSrr = 1412,
+ MOVZDI2PDIrm = 1413,
+ MOVZDI2PDIrr = 1414,
+ MOVZPQILo2PQIrm = 1415,
+ MOVZPQILo2PQIrr = 1416,
+ MOVZQI2PQIrm = 1417,
+ MOVZQI2PQIrr = 1418,
+ MOVZX16rm8 = 1419,
+ MOVZX16rm8W = 1420,
+ MOVZX16rr8 = 1421,
+ MOVZX16rr8W = 1422,
+ MOVZX32_NOREXrm8 = 1423,
+ MOVZX32_NOREXrr8 = 1424,
+ MOVZX32rm16 = 1425,
+ MOVZX32rm8 = 1426,
+ MOVZX32rr16 = 1427,
+ MOVZX32rr8 = 1428,
+ MOVZX64rm16 = 1429,
+ MOVZX64rm16_Q = 1430,
+ MOVZX64rm32 = 1431,
+ MOVZX64rm8 = 1432,
+ MOVZX64rm8_Q = 1433,
+ MOVZX64rr16 = 1434,
+ MOVZX64rr16_Q = 1435,
+ MOVZX64rr32 = 1436,
+ MOVZX64rr8 = 1437,
+ MOVZX64rr8_Q = 1438,
+ MOV_Fp3232 = 1439,
+ MOV_Fp3264 = 1440,
+ MOV_Fp3280 = 1441,
+ MOV_Fp6432 = 1442,
+ MOV_Fp6464 = 1443,
+ MOV_Fp6480 = 1444,
+ MOV_Fp8032 = 1445,
+ MOV_Fp8064 = 1446,
+ MOV_Fp8080 = 1447,
+ MPSADBWrmi = 1448,
+ MPSADBWrri = 1449,
+ MUL16m = 1450,
+ MUL16r = 1451,
+ MUL32m = 1452,
+ MUL32r = 1453,
+ MUL64m = 1454,
+ MUL64r = 1455,
+ MUL8m = 1456,
+ MUL8r = 1457,
+ MULPDrm = 1458,
+ MULPDrr = 1459,
+ MULPSrm = 1460,
+ MULPSrr = 1461,
+ MULSDrm = 1462,
+ MULSDrm_Int = 1463,
+ MULSDrr = 1464,
+ MULSDrr_Int = 1465,
+ MULSSrm = 1466,
+ MULSSrm_Int = 1467,
+ MULSSrr = 1468,
+ MULSSrr_Int = 1469,
+ MUL_F32m = 1470,
+ MUL_F64m = 1471,
+ MUL_FI16m = 1472,
+ MUL_FI32m = 1473,
+ MUL_FPrST0 = 1474,
+ MUL_FST0r = 1475,
+ MUL_Fp32 = 1476,
+ MUL_Fp32m = 1477,
+ MUL_Fp64 = 1478,
+ MUL_Fp64m = 1479,
+ MUL_Fp64m32 = 1480,
+ MUL_Fp80 = 1481,
+ MUL_Fp80m32 = 1482,
+ MUL_Fp80m64 = 1483,
+ MUL_FpI16m32 = 1484,
+ MUL_FpI16m64 = 1485,
+ MUL_FpI16m80 = 1486,
+ MUL_FpI32m32 = 1487,
+ MUL_FpI32m64 = 1488,
+ MUL_FpI32m80 = 1489,
+ MUL_FrST0 = 1490,
+ MWAIT = 1491,
+ NEG16m = 1492,
+ NEG16r = 1493,
+ NEG32m = 1494,
+ NEG32r = 1495,
+ NEG64m = 1496,
+ NEG64r = 1497,
+ NEG8m = 1498,
+ NEG8r = 1499,
+ NOOP = 1500,
+ NOOPL = 1501,
+ NOOPW = 1502,
+ NOT16m = 1503,
+ NOT16r = 1504,
+ NOT32m = 1505,
+ NOT32r = 1506,
+ NOT64m = 1507,
+ NOT64r = 1508,
+ NOT8m = 1509,
+ NOT8r = 1510,
+ OR16i16 = 1511,
+ OR16mi = 1512,
+ OR16mi8 = 1513,
+ OR16mr = 1514,
+ OR16ri = 1515,
+ OR16ri8 = 1516,
+ OR16rm = 1517,
+ OR16rr = 1518,
+ OR16rr_REV = 1519,
+ OR32i32 = 1520,
+ OR32mi = 1521,
+ OR32mi8 = 1522,
+ OR32mr = 1523,
+ OR32ri = 1524,
+ OR32ri8 = 1525,
+ OR32rm = 1526,
+ OR32rr = 1527,
+ OR32rr_REV = 1528,
+ OR64i32 = 1529,
+ OR64mi32 = 1530,
+ OR64mi8 = 1531,
+ OR64mr = 1532,
+ OR64ri32 = 1533,
+ OR64ri8 = 1534,
+ OR64rm = 1535,
+ OR64rr = 1536,
+ OR64rr_REV = 1537,
+ OR8i8 = 1538,
+ OR8mi = 1539,
+ OR8mr = 1540,
+ OR8ri = 1541,
+ OR8rm = 1542,
+ OR8rr = 1543,
+ OR8rr_REV = 1544,
+ ORPDrm = 1545,
+ ORPDrr = 1546,
+ ORPSrm = 1547,
+ ORPSrr = 1548,
+ OUT16ir = 1549,
+ OUT16rr = 1550,
+ OUT32ir = 1551,
+ OUT32rr = 1552,
+ OUT8ir = 1553,
+ OUT8rr = 1554,
+ OUTSB = 1555,
+ OUTSD = 1556,
+ OUTSW = 1557,
+ PABSBrm128 = 1558,
+ PABSBrm64 = 1559,
+ PABSBrr128 = 1560,
+ PABSBrr64 = 1561,
+ PABSDrm128 = 1562,
+ PABSDrm64 = 1563,
+ PABSDrr128 = 1564,
+ PABSDrr64 = 1565,
+ PABSWrm128 = 1566,
+ PABSWrm64 = 1567,
+ PABSWrr128 = 1568,
+ PABSWrr64 = 1569,
+ PACKSSDWrm = 1570,
+ PACKSSDWrr = 1571,
+ PACKSSWBrm = 1572,
+ PACKSSWBrr = 1573,
+ PACKUSDWrm = 1574,
+ PACKUSDWrr = 1575,
+ PACKUSWBrm = 1576,
+ PACKUSWBrr = 1577,
+ PADDBrm = 1578,
+ PADDBrr = 1579,
+ PADDDrm = 1580,
+ PADDDrr = 1581,
+ PADDQrm = 1582,
+ PADDQrr = 1583,
+ PADDSBrm = 1584,
+ PADDSBrr = 1585,
+ PADDSWrm = 1586,
+ PADDSWrr = 1587,
+ PADDUSBrm = 1588,
+ PADDUSBrr = 1589,
+ PADDUSWrm = 1590,
+ PADDUSWrr = 1591,
+ PADDWrm = 1592,
+ PADDWrr = 1593,
+ PALIGNR128rm = 1594,
+ PALIGNR128rr = 1595,
+ PALIGNR64rm = 1596,
+ PALIGNR64rr = 1597,
+ PANDNrm = 1598,
+ PANDNrr = 1599,
+ PANDrm = 1600,
+ PANDrr = 1601,
+ PAVGBrm = 1602,
+ PAVGBrr = 1603,
+ PAVGWrm = 1604,
+ PAVGWrr = 1605,
+ PBLENDVBrm0 = 1606,
+ PBLENDVBrr0 = 1607,
+ PBLENDWrmi = 1608,
+ PBLENDWrri = 1609,
+ PCMPEQBrm = 1610,
+ PCMPEQBrr = 1611,
+ PCMPEQDrm = 1612,
+ PCMPEQDrr = 1613,
+ PCMPEQQrm = 1614,
+ PCMPEQQrr = 1615,
+ PCMPEQWrm = 1616,
+ PCMPEQWrr = 1617,
+ PCMPESTRIArm = 1618,
+ PCMPESTRIArr = 1619,
+ PCMPESTRICrm = 1620,
+ PCMPESTRICrr = 1621,
+ PCMPESTRIOrm = 1622,
+ PCMPESTRIOrr = 1623,
+ PCMPESTRISrm = 1624,
+ PCMPESTRISrr = 1625,
+ PCMPESTRIZrm = 1626,
+ PCMPESTRIZrr = 1627,
+ PCMPESTRIrm = 1628,
+ PCMPESTRIrr = 1629,
+ PCMPESTRM128MEM = 1630,
+ PCMPESTRM128REG = 1631,
+ PCMPESTRM128rm = 1632,
+ PCMPESTRM128rr = 1633,
+ PCMPGTBrm = 1634,
+ PCMPGTBrr = 1635,
+ PCMPGTDrm = 1636,
+ PCMPGTDrr = 1637,
+ PCMPGTQrm = 1638,
+ PCMPGTQrr = 1639,
+ PCMPGTWrm = 1640,
+ PCMPGTWrr = 1641,
+ PCMPISTRIArm = 1642,
+ PCMPISTRIArr = 1643,
+ PCMPISTRICrm = 1644,
+ PCMPISTRICrr = 1645,
+ PCMPISTRIOrm = 1646,
+ PCMPISTRIOrr = 1647,
+ PCMPISTRISrm = 1648,
+ PCMPISTRISrr = 1649,
+ PCMPISTRIZrm = 1650,
+ PCMPISTRIZrr = 1651,
+ PCMPISTRIrm = 1652,
+ PCMPISTRIrr = 1653,
+ PCMPISTRM128MEM = 1654,
+ PCMPISTRM128REG = 1655,
+ PCMPISTRM128rm = 1656,
+ PCMPISTRM128rr = 1657,
+ PEXTRBmr = 1658,
+ PEXTRBrr = 1659,
+ PEXTRDmr = 1660,
+ PEXTRDrr = 1661,
+ PEXTRQmr = 1662,
+ PEXTRQrr = 1663,
+ PEXTRWmr = 1664,
+ PEXTRWri = 1665,
+ PHADDDrm128 = 1666,
+ PHADDDrm64 = 1667,
+ PHADDDrr128 = 1668,
+ PHADDDrr64 = 1669,
+ PHADDSWrm128 = 1670,
+ PHADDSWrm64 = 1671,
+ PHADDSWrr128 = 1672,
+ PHADDSWrr64 = 1673,
+ PHADDWrm128 = 1674,
+ PHADDWrm64 = 1675,
+ PHADDWrr128 = 1676,
+ PHADDWrr64 = 1677,
+ PHMINPOSUWrm128 = 1678,
+ PHMINPOSUWrr128 = 1679,
+ PHSUBDrm128 = 1680,
+ PHSUBDrm64 = 1681,
+ PHSUBDrr128 = 1682,
+ PHSUBDrr64 = 1683,
+ PHSUBSWrm128 = 1684,
+ PHSUBSWrm64 = 1685,
+ PHSUBSWrr128 = 1686,
+ PHSUBSWrr64 = 1687,
+ PHSUBWrm128 = 1688,
+ PHSUBWrm64 = 1689,
+ PHSUBWrr128 = 1690,
+ PHSUBWrr64 = 1691,
+ PINSRBrm = 1692,
+ PINSRBrr = 1693,
+ PINSRDrm = 1694,
+ PINSRDrr = 1695,
+ PINSRQrm = 1696,
+ PINSRQrr = 1697,
+ PINSRWrmi = 1698,
+ PINSRWrri = 1699,
+ PMADDUBSWrm128 = 1700,
+ PMADDUBSWrm64 = 1701,
+ PMADDUBSWrr128 = 1702,
+ PMADDUBSWrr64 = 1703,
+ PMADDWDrm = 1704,
+ PMADDWDrr = 1705,
+ PMAXSBrm = 1706,
+ PMAXSBrr = 1707,
+ PMAXSDrm = 1708,
+ PMAXSDrr = 1709,
+ PMAXSWrm = 1710,
+ PMAXSWrr = 1711,
+ PMAXUBrm = 1712,
+ PMAXUBrr = 1713,
+ PMAXUDrm = 1714,
+ PMAXUDrr = 1715,
+ PMAXUWrm = 1716,
+ PMAXUWrr = 1717,
+ PMINSBrm = 1718,
+ PMINSBrr = 1719,
+ PMINSDrm = 1720,
+ PMINSDrr = 1721,
+ PMINSWrm = 1722,
+ PMINSWrr = 1723,
+ PMINUBrm = 1724,
+ PMINUBrr = 1725,
+ PMINUDrm = 1726,
+ PMINUDrr = 1727,
+ PMINUWrm = 1728,
+ PMINUWrr = 1729,
+ PMOVMSKBrr = 1730,
+ PMOVSXBDrm = 1731,
+ PMOVSXBDrr = 1732,
+ PMOVSXBQrm = 1733,
+ PMOVSXBQrr = 1734,
+ PMOVSXBWrm = 1735,
+ PMOVSXBWrr = 1736,
+ PMOVSXDQrm = 1737,
+ PMOVSXDQrr = 1738,
+ PMOVSXWDrm = 1739,
+ PMOVSXWDrr = 1740,
+ PMOVSXWQrm = 1741,
+ PMOVSXWQrr = 1742,
+ PMOVZXBDrm = 1743,
+ PMOVZXBDrr = 1744,
+ PMOVZXBQrm = 1745,
+ PMOVZXBQrr = 1746,
+ PMOVZXBWrm = 1747,
+ PMOVZXBWrr = 1748,
+ PMOVZXDQrm = 1749,
+ PMOVZXDQrr = 1750,
+ PMOVZXWDrm = 1751,
+ PMOVZXWDrr = 1752,
+ PMOVZXWQrm = 1753,
+ PMOVZXWQrr = 1754,
+ PMULDQrm = 1755,
+ PMULDQrr = 1756,
+ PMULHRSWrm128 = 1757,
+ PMULHRSWrm64 = 1758,
+ PMULHRSWrr128 = 1759,
+ PMULHRSWrr64 = 1760,
+ PMULHUWrm = 1761,
+ PMULHUWrr = 1762,
+ PMULHWrm = 1763,
+ PMULHWrr = 1764,
+ PMULLDrm = 1765,
+ PMULLDrm_int = 1766,
+ PMULLDrr = 1767,
+ PMULLDrr_int = 1768,
+ PMULLWrm = 1769,
+ PMULLWrr = 1770,
+ PMULUDQrm = 1771,
+ PMULUDQrr = 1772,
+ POP16r = 1773,
+ POP16rmm = 1774,
+ POP16rmr = 1775,
+ POP32r = 1776,
+ POP32rmm = 1777,
+ POP32rmr = 1778,
+ POP64r = 1779,
+ POP64rmm = 1780,
+ POP64rmr = 1781,
+ POPCNT16rm = 1782,
+ POPCNT16rr = 1783,
+ POPCNT32rm = 1784,
+ POPCNT32rr = 1785,
+ POPCNT64rm = 1786,
+ POPCNT64rr = 1787,
+ POPF = 1788,
+ POPFD = 1789,
+ POPFQ = 1790,
+ POPFS16 = 1791,
+ POPFS32 = 1792,
+ POPFS64 = 1793,
+ POPGS16 = 1794,
+ POPGS32 = 1795,
+ POPGS64 = 1796,
+ PORrm = 1797,
+ PORrr = 1798,
+ PREFETCHNTA = 1799,
+ PREFETCHT0 = 1800,
+ PREFETCHT1 = 1801,
+ PREFETCHT2 = 1802,
+ PSADBWrm = 1803,
+ PSADBWrr = 1804,
+ PSHUFBrm128 = 1805,
+ PSHUFBrm64 = 1806,
+ PSHUFBrr128 = 1807,
+ PSHUFBrr64 = 1808,
+ PSHUFDmi = 1809,
+ PSHUFDri = 1810,
+ PSHUFHWmi = 1811,
+ PSHUFHWri = 1812,
+ PSHUFLWmi = 1813,
+ PSHUFLWri = 1814,
+ PSIGNBrm128 = 1815,
+ PSIGNBrm64 = 1816,
+ PSIGNBrr128 = 1817,
+ PSIGNBrr64 = 1818,
+ PSIGNDrm128 = 1819,
+ PSIGNDrm64 = 1820,
+ PSIGNDrr128 = 1821,
+ PSIGNDrr64 = 1822,
+ PSIGNWrm128 = 1823,
+ PSIGNWrm64 = 1824,
+ PSIGNWrr128 = 1825,
+ PSIGNWrr64 = 1826,
+ PSLLDQri = 1827,
+ PSLLDri = 1828,
+ PSLLDrm = 1829,
+ PSLLDrr = 1830,
+ PSLLQri = 1831,
+ PSLLQrm = 1832,
+ PSLLQrr = 1833,
+ PSLLWri = 1834,
+ PSLLWrm = 1835,
+ PSLLWrr = 1836,
+ PSRADri = 1837,
+ PSRADrm = 1838,
+ PSRADrr = 1839,
+ PSRAWri = 1840,
+ PSRAWrm = 1841,
+ PSRAWrr = 1842,
+ PSRLDQri = 1843,
+ PSRLDri = 1844,
+ PSRLDrm = 1845,
+ PSRLDrr = 1846,
+ PSRLQri = 1847,
+ PSRLQrm = 1848,
+ PSRLQrr = 1849,
+ PSRLWri = 1850,
+ PSRLWrm = 1851,
+ PSRLWrr = 1852,
+ PSUBBrm = 1853,
+ PSUBBrr = 1854,
+ PSUBDrm = 1855,
+ PSUBDrr = 1856,
+ PSUBQrm = 1857,
+ PSUBQrr = 1858,
+ PSUBSBrm = 1859,
+ PSUBSBrr = 1860,
+ PSUBSWrm = 1861,
+ PSUBSWrr = 1862,
+ PSUBUSBrm = 1863,
+ PSUBUSBrr = 1864,
+ PSUBUSWrm = 1865,
+ PSUBUSWrr = 1866,
+ PSUBWrm = 1867,
+ PSUBWrr = 1868,
+ PTESTrm = 1869,
+ PTESTrr = 1870,
+ PUNPCKHBWrm = 1871,
+ PUNPCKHBWrr = 1872,
+ PUNPCKHDQrm = 1873,
+ PUNPCKHDQrr = 1874,
+ PUNPCKHQDQrm = 1875,
+ PUNPCKHQDQrr = 1876,
+ PUNPCKHWDrm = 1877,
+ PUNPCKHWDrr = 1878,
+ PUNPCKLBWrm = 1879,
+ PUNPCKLBWrr = 1880,
+ PUNPCKLDQrm = 1881,
+ PUNPCKLDQrr = 1882,
+ PUNPCKLQDQrm = 1883,
+ PUNPCKLQDQrr = 1884,
+ PUNPCKLWDrm = 1885,
+ PUNPCKLWDrr = 1886,
+ PUSH16r = 1887,
+ PUSH16rmm = 1888,
+ PUSH16rmr = 1889,
+ PUSH32i16 = 1890,
+ PUSH32i32 = 1891,
+ PUSH32i8 = 1892,
+ PUSH32r = 1893,
+ PUSH32rmm = 1894,
+ PUSH32rmr = 1895,
+ PUSH64i16 = 1896,
+ PUSH64i32 = 1897,
+ PUSH64i8 = 1898,
+ PUSH64r = 1899,
+ PUSH64rmm = 1900,
+ PUSH64rmr = 1901,
+ PUSHF = 1902,
+ PUSHFD = 1903,
+ PUSHFQ64 = 1904,
+ PUSHFS16 = 1905,
+ PUSHFS32 = 1906,
+ PUSHFS64 = 1907,
+ PUSHGS16 = 1908,
+ PUSHGS32 = 1909,
+ PUSHGS64 = 1910,
+ PXORrm = 1911,
+ PXORrr = 1912,
+ RCL16m1 = 1913,
+ RCL16mCL = 1914,
+ RCL16mi = 1915,
+ RCL16r1 = 1916,
+ RCL16rCL = 1917,
+ RCL16ri = 1918,
+ RCL32m1 = 1919,
+ RCL32mCL = 1920,
+ RCL32mi = 1921,
+ RCL32r1 = 1922,
+ RCL32rCL = 1923,
+ RCL32ri = 1924,
+ RCL64m1 = 1925,
+ RCL64mCL = 1926,
+ RCL64mi = 1927,
+ RCL64r1 = 1928,
+ RCL64rCL = 1929,
+ RCL64ri = 1930,
+ RCL8m1 = 1931,
+ RCL8mCL = 1932,
+ RCL8mi = 1933,
+ RCL8r1 = 1934,
+ RCL8rCL = 1935,
+ RCL8ri = 1936,
+ RCPPSm = 1937,
+ RCPPSm_Int = 1938,
+ RCPPSr = 1939,
+ RCPPSr_Int = 1940,
+ RCPSSm = 1941,
+ RCPSSm_Int = 1942,
+ RCPSSr = 1943,
+ RCPSSr_Int = 1944,
+ RCR16m1 = 1945,
+ RCR16mCL = 1946,
+ RCR16mi = 1947,
+ RCR16r1 = 1948,
+ RCR16rCL = 1949,
+ RCR16ri = 1950,
+ RCR32m1 = 1951,
+ RCR32mCL = 1952,
+ RCR32mi = 1953,
+ RCR32r1 = 1954,
+ RCR32rCL = 1955,
+ RCR32ri = 1956,
+ RCR64m1 = 1957,
+ RCR64mCL = 1958,
+ RCR64mi = 1959,
+ RCR64r1 = 1960,
+ RCR64rCL = 1961,
+ RCR64ri = 1962,
+ RCR8m1 = 1963,
+ RCR8mCL = 1964,
+ RCR8mi = 1965,
+ RCR8r1 = 1966,
+ RCR8rCL = 1967,
+ RCR8ri = 1968,
+ RDMSR = 1969,
+ RDPMC = 1970,
+ RDTSC = 1971,
+ RDTSCP = 1972,
+ REPNE_PREFIX = 1973,
+ REP_MOVSB = 1974,
+ REP_MOVSD = 1975,
+ REP_MOVSQ = 1976,
+ REP_MOVSW = 1977,
+ REP_PREFIX = 1978,
+ REP_STOSB = 1979,
+ REP_STOSD = 1980,
+ REP_STOSQ = 1981,
+ REP_STOSW = 1982,
+ RET = 1983,
+ RETI = 1984,
+ ROL16m1 = 1985,
+ ROL16mCL = 1986,
+ ROL16mi = 1987,
+ ROL16r1 = 1988,
+ ROL16rCL = 1989,
+ ROL16ri = 1990,
+ ROL32m1 = 1991,
+ ROL32mCL = 1992,
+ ROL32mi = 1993,
+ ROL32r1 = 1994,
+ ROL32rCL = 1995,
+ ROL32ri = 1996,
+ ROL64m1 = 1997,
+ ROL64mCL = 1998,
+ ROL64mi = 1999,
+ ROL64r1 = 2000,
+ ROL64rCL = 2001,
+ ROL64ri = 2002,
+ ROL8m1 = 2003,
+ ROL8mCL = 2004,
+ ROL8mi = 2005,
+ ROL8r1 = 2006,
+ ROL8rCL = 2007,
+ ROL8ri = 2008,
+ ROR16m1 = 2009,
+ ROR16mCL = 2010,
+ ROR16mi = 2011,
+ ROR16r1 = 2012,
+ ROR16rCL = 2013,
+ ROR16ri = 2014,
+ ROR32m1 = 2015,
+ ROR32mCL = 2016,
+ ROR32mi = 2017,
+ ROR32r1 = 2018,
+ ROR32rCL = 2019,
+ ROR32ri = 2020,
+ ROR64m1 = 2021,
+ ROR64mCL = 2022,
+ ROR64mi = 2023,
+ ROR64r1 = 2024,
+ ROR64rCL = 2025,
+ ROR64ri = 2026,
+ ROR8m1 = 2027,
+ ROR8mCL = 2028,
+ ROR8mi = 2029,
+ ROR8r1 = 2030,
+ ROR8rCL = 2031,
+ ROR8ri = 2032,
+ ROUNDPDm_Int = 2033,
+ ROUNDPDr_Int = 2034,
+ ROUNDPSm_Int = 2035,
+ ROUNDPSr_Int = 2036,
+ ROUNDSDm_Int = 2037,
+ ROUNDSDr_Int = 2038,
+ ROUNDSSm_Int = 2039,
+ ROUNDSSr_Int = 2040,
+ RSM = 2041,
+ RSQRTPSm = 2042,
+ RSQRTPSm_Int = 2043,
+ RSQRTPSr = 2044,
+ RSQRTPSr_Int = 2045,
+ RSQRTSSm = 2046,
+ RSQRTSSm_Int = 2047,
+ RSQRTSSr = 2048,
+ RSQRTSSr_Int = 2049,
+ SAHF = 2050,
+ SAR16m1 = 2051,
+ SAR16mCL = 2052,
+ SAR16mi = 2053,
+ SAR16r1 = 2054,
+ SAR16rCL = 2055,
+ SAR16ri = 2056,
+ SAR32m1 = 2057,
+ SAR32mCL = 2058,
+ SAR32mi = 2059,
+ SAR32r1 = 2060,
+ SAR32rCL = 2061,
+ SAR32ri = 2062,
+ SAR64m1 = 2063,
+ SAR64mCL = 2064,
+ SAR64mi = 2065,
+ SAR64r1 = 2066,
+ SAR64rCL = 2067,
+ SAR64ri = 2068,
+ SAR8m1 = 2069,
+ SAR8mCL = 2070,
+ SAR8mi = 2071,
+ SAR8r1 = 2072,
+ SAR8rCL = 2073,
+ SAR8ri = 2074,
+ SBB16i16 = 2075,
+ SBB16mi = 2076,
+ SBB16mi8 = 2077,
+ SBB16mr = 2078,
+ SBB16ri = 2079,
+ SBB16ri8 = 2080,
+ SBB16rm = 2081,
+ SBB16rr = 2082,
+ SBB16rr_REV = 2083,
+ SBB32i32 = 2084,
+ SBB32mi = 2085,
+ SBB32mi8 = 2086,
+ SBB32mr = 2087,
+ SBB32ri = 2088,
+ SBB32ri8 = 2089,
+ SBB32rm = 2090,
+ SBB32rr = 2091,
+ SBB32rr_REV = 2092,
+ SBB64i32 = 2093,
+ SBB64mi32 = 2094,
+ SBB64mi8 = 2095,
+ SBB64mr = 2096,
+ SBB64ri32 = 2097,
+ SBB64ri8 = 2098,
+ SBB64rm = 2099,
+ SBB64rr = 2100,
+ SBB64rr_REV = 2101,
+ SBB8i8 = 2102,
+ SBB8mi = 2103,
+ SBB8mr = 2104,
+ SBB8ri = 2105,
+ SBB8rm = 2106,
+ SBB8rr = 2107,
+ SBB8rr_REV = 2108,
+ SCAS16 = 2109,
+ SCAS32 = 2110,
+ SCAS64 = 2111,
+ SCAS8 = 2112,
+ SETAEm = 2113,
+ SETAEr = 2114,
+ SETAm = 2115,
+ SETAr = 2116,
+ SETBEm = 2117,
+ SETBEr = 2118,
+ SETB_C16r = 2119,
+ SETB_C32r = 2120,
+ SETB_C64r = 2121,
+ SETB_C8r = 2122,
+ SETBm = 2123,
+ SETBr = 2124,
+ SETEm = 2125,
+ SETEr = 2126,
+ SETGEm = 2127,
+ SETGEr = 2128,
+ SETGm = 2129,
+ SETGr = 2130,
+ SETLEm = 2131,
+ SETLEr = 2132,
+ SETLm = 2133,
+ SETLr = 2134,
+ SETNEm = 2135,
+ SETNEr = 2136,
+ SETNOm = 2137,
+ SETNOr = 2138,
+ SETNPm = 2139,
+ SETNPr = 2140,
+ SETNSm = 2141,
+ SETNSr = 2142,
+ SETOm = 2143,
+ SETOr = 2144,
+ SETPm = 2145,
+ SETPr = 2146,
+ SETSm = 2147,
+ SETSr = 2148,
+ SFENCE = 2149,
+ SGDTm = 2150,
+ SHL16m1 = 2151,
+ SHL16mCL = 2152,
+ SHL16mi = 2153,
+ SHL16r1 = 2154,
+ SHL16rCL = 2155,
+ SHL16ri = 2156,
+ SHL32m1 = 2157,
+ SHL32mCL = 2158,
+ SHL32mi = 2159,
+ SHL32r1 = 2160,
+ SHL32rCL = 2161,
+ SHL32ri = 2162,
+ SHL64m1 = 2163,
+ SHL64mCL = 2164,
+ SHL64mi = 2165,
+ SHL64r1 = 2166,
+ SHL64rCL = 2167,
+ SHL64ri = 2168,
+ SHL8m1 = 2169,
+ SHL8mCL = 2170,
+ SHL8mi = 2171,
+ SHL8r1 = 2172,
+ SHL8rCL = 2173,
+ SHL8ri = 2174,
+ SHLD16mrCL = 2175,
+ SHLD16mri8 = 2176,
+ SHLD16rrCL = 2177,
+ SHLD16rri8 = 2178,
+ SHLD32mrCL = 2179,
+ SHLD32mri8 = 2180,
+ SHLD32rrCL = 2181,
+ SHLD32rri8 = 2182,
+ SHLD64mrCL = 2183,
+ SHLD64mri8 = 2184,
+ SHLD64rrCL = 2185,
+ SHLD64rri8 = 2186,
+ SHR16m1 = 2187,
+ SHR16mCL = 2188,
+ SHR16mi = 2189,
+ SHR16r1 = 2190,
+ SHR16rCL = 2191,
+ SHR16ri = 2192,
+ SHR32m1 = 2193,
+ SHR32mCL = 2194,
+ SHR32mi = 2195,
+ SHR32r1 = 2196,
+ SHR32rCL = 2197,
+ SHR32ri = 2198,
+ SHR64m1 = 2199,
+ SHR64mCL = 2200,
+ SHR64mi = 2201,
+ SHR64r1 = 2202,
+ SHR64rCL = 2203,
+ SHR64ri = 2204,
+ SHR8m1 = 2205,
+ SHR8mCL = 2206,
+ SHR8mi = 2207,
+ SHR8r1 = 2208,
+ SHR8rCL = 2209,
+ SHR8ri = 2210,
+ SHRD16mrCL = 2211,
+ SHRD16mri8 = 2212,
+ SHRD16rrCL = 2213,
+ SHRD16rri8 = 2214,
+ SHRD32mrCL = 2215,
+ SHRD32mri8 = 2216,
+ SHRD32rrCL = 2217,
+ SHRD32rri8 = 2218,
+ SHRD64mrCL = 2219,
+ SHRD64mri8 = 2220,
+ SHRD64rrCL = 2221,
+ SHRD64rri8 = 2222,
+ SHUFPDrmi = 2223,
+ SHUFPDrri = 2224,
+ SHUFPSrmi = 2225,
+ SHUFPSrri = 2226,
+ SIDTm = 2227,
+ SIN_F = 2228,
+ SIN_Fp32 = 2229,
+ SIN_Fp64 = 2230,
+ SIN_Fp80 = 2231,
+ SLDT16m = 2232,
+ SLDT16r = 2233,
+ SLDT64m = 2234,
+ SLDT64r = 2235,
+ SMSW16m = 2236,
+ SMSW16r = 2237,
+ SMSW32r = 2238,
+ SMSW64r = 2239,
+ SQRTPDm = 2240,
+ SQRTPDm_Int = 2241,
+ SQRTPDr = 2242,
+ SQRTPDr_Int = 2243,
+ SQRTPSm = 2244,
+ SQRTPSm_Int = 2245,
+ SQRTPSr = 2246,
+ SQRTPSr_Int = 2247,
+ SQRTSDm = 2248,
+ SQRTSDm_Int = 2249,
+ SQRTSDr = 2250,
+ SQRTSDr_Int = 2251,
+ SQRTSSm = 2252,
+ SQRTSSm_Int = 2253,
+ SQRTSSr = 2254,
+ SQRTSSr_Int = 2255,
+ SQRT_F = 2256,
+ SQRT_Fp32 = 2257,
+ SQRT_Fp64 = 2258,
+ SQRT_Fp80 = 2259,
+ SS_PREFIX = 2260,
+ STC = 2261,
+ STD = 2262,
+ STI = 2263,
+ STMXCSR = 2264,
+ STOSB = 2265,
+ STOSD = 2266,
+ STOSW = 2267,
+ STRm = 2268,
+ STRr = 2269,
+ ST_F32m = 2270,
+ ST_F64m = 2271,
+ ST_FP32m = 2272,
+ ST_FP64m = 2273,
+ ST_FP80m = 2274,
+ ST_FPrr = 2275,
+ ST_Fp32m = 2276,
+ ST_Fp64m = 2277,
+ ST_Fp64m32 = 2278,
+ ST_Fp80m32 = 2279,
+ ST_Fp80m64 = 2280,
+ ST_FpP32m = 2281,
+ ST_FpP64m = 2282,
+ ST_FpP64m32 = 2283,
+ ST_FpP80m = 2284,
+ ST_FpP80m32 = 2285,
+ ST_FpP80m64 = 2286,
+ ST_Frr = 2287,
+ SUB16i16 = 2288,
+ SUB16mi = 2289,
+ SUB16mi8 = 2290,
+ SUB16mr = 2291,
+ SUB16ri = 2292,
+ SUB16ri8 = 2293,
+ SUB16rm = 2294,
+ SUB16rr = 2295,
+ SUB16rr_REV = 2296,
+ SUB32i32 = 2297,
+ SUB32mi = 2298,
+ SUB32mi8 = 2299,
+ SUB32mr = 2300,
+ SUB32ri = 2301,
+ SUB32ri8 = 2302,
+ SUB32rm = 2303,
+ SUB32rr = 2304,
+ SUB32rr_REV = 2305,
+ SUB64i32 = 2306,
+ SUB64mi32 = 2307,
+ SUB64mi8 = 2308,
+ SUB64mr = 2309,
+ SUB64ri32 = 2310,
+ SUB64ri8 = 2311,
+ SUB64rm = 2312,
+ SUB64rr = 2313,
+ SUB64rr_REV = 2314,
+ SUB8i8 = 2315,
+ SUB8mi = 2316,
+ SUB8mr = 2317,
+ SUB8ri = 2318,
+ SUB8rm = 2319,
+ SUB8rr = 2320,
+ SUB8rr_REV = 2321,
+ SUBPDrm = 2322,
+ SUBPDrr = 2323,
+ SUBPSrm = 2324,
+ SUBPSrr = 2325,
+ SUBR_F32m = 2326,
+ SUBR_F64m = 2327,
+ SUBR_FI16m = 2328,
+ SUBR_FI32m = 2329,
+ SUBR_FPrST0 = 2330,
+ SUBR_FST0r = 2331,
+ SUBR_Fp32m = 2332,
+ SUBR_Fp64m = 2333,
+ SUBR_Fp64m32 = 2334,
+ SUBR_Fp80m32 = 2335,
+ SUBR_Fp80m64 = 2336,
+ SUBR_FpI16m32 = 2337,
+ SUBR_FpI16m64 = 2338,
+ SUBR_FpI16m80 = 2339,
+ SUBR_FpI32m32 = 2340,
+ SUBR_FpI32m64 = 2341,
+ SUBR_FpI32m80 = 2342,
+ SUBR_FrST0 = 2343,
+ SUBSDrm = 2344,
+ SUBSDrm_Int = 2345,
+ SUBSDrr = 2346,
+ SUBSDrr_Int = 2347,
+ SUBSSrm = 2348,
+ SUBSSrm_Int = 2349,
+ SUBSSrr = 2350,
+ SUBSSrr_Int = 2351,
+ SUB_F32m = 2352,
+ SUB_F64m = 2353,
+ SUB_FI16m = 2354,
+ SUB_FI32m = 2355,
+ SUB_FPrST0 = 2356,
+ SUB_FST0r = 2357,
+ SUB_Fp32 = 2358,
+ SUB_Fp32m = 2359,
+ SUB_Fp64 = 2360,
+ SUB_Fp64m = 2361,
+ SUB_Fp64m32 = 2362,
+ SUB_Fp80 = 2363,
+ SUB_Fp80m32 = 2364,
+ SUB_Fp80m64 = 2365,
+ SUB_FpI16m32 = 2366,
+ SUB_FpI16m64 = 2367,
+ SUB_FpI16m80 = 2368,
+ SUB_FpI32m32 = 2369,
+ SUB_FpI32m64 = 2370,
+ SUB_FpI32m80 = 2371,
+ SUB_FrST0 = 2372,
+ SWAPGS = 2373,
+ SYSCALL = 2374,
+ SYSENTER = 2375,
+ SYSEXIT = 2376,
+ SYSEXIT64 = 2377,
+ SYSRET = 2378,
+ TAILJMPd = 2379,
+ TAILJMPm = 2380,
+ TAILJMPr = 2381,
+ TAILJMPr64 = 2382,
+ TCRETURNdi = 2383,
+ TCRETURNdi64 = 2384,
+ TCRETURNri = 2385,
+ TCRETURNri64 = 2386,
+ TEST16i16 = 2387,
+ TEST16mi = 2388,
+ TEST16ri = 2389,
+ TEST16rm = 2390,
+ TEST16rr = 2391,
+ TEST32i32 = 2392,
+ TEST32mi = 2393,
+ TEST32ri = 2394,
+ TEST32rm = 2395,
+ TEST32rr = 2396,
+ TEST64i32 = 2397,
+ TEST64mi32 = 2398,
+ TEST64ri32 = 2399,
+ TEST64rm = 2400,
+ TEST64rr = 2401,
+ TEST8i8 = 2402,
+ TEST8mi = 2403,
+ TEST8ri = 2404,
+ TEST8rm = 2405,
+ TEST8rr = 2406,
+ TLS_addr32 = 2407,
+ TLS_addr64 = 2408,
+ TRAP = 2409,
+ TST_F = 2410,
+ TST_Fp32 = 2411,
+ TST_Fp64 = 2412,
+ TST_Fp80 = 2413,
+ UCOMISDrm = 2414,
+ UCOMISDrr = 2415,
+ UCOMISSrm = 2416,
+ UCOMISSrr = 2417,
+ UCOM_FIPr = 2418,
+ UCOM_FIr = 2419,
+ UCOM_FPPr = 2420,
+ UCOM_FPr = 2421,
+ UCOM_FpIr32 = 2422,
+ UCOM_FpIr64 = 2423,
+ UCOM_FpIr80 = 2424,
+ UCOM_Fpr32 = 2425,
+ UCOM_Fpr64 = 2426,
+ UCOM_Fpr80 = 2427,
+ UCOM_Fr = 2428,
+ UNPCKHPDrm = 2429,
+ UNPCKHPDrr = 2430,
+ UNPCKHPSrm = 2431,
+ UNPCKHPSrr = 2432,
+ UNPCKLPDrm = 2433,
+ UNPCKLPDrr = 2434,
+ UNPCKLPSrm = 2435,
+ UNPCKLPSrr = 2436,
+ VASTART_SAVE_XMM_REGS = 2437,
+ VERRm = 2438,
+ VERRr = 2439,
+ VERWm = 2440,
+ VERWr = 2441,
+ VMCALL = 2442,
+ VMCLEARm = 2443,
+ VMLAUNCH = 2444,
+ VMPTRLDm = 2445,
+ VMPTRSTm = 2446,
+ VMREAD32rm = 2447,
+ VMREAD32rr = 2448,
+ VMREAD64rm = 2449,
+ VMREAD64rr = 2450,
+ VMRESUME = 2451,
+ VMWRITE32rm = 2452,
+ VMWRITE32rr = 2453,
+ VMWRITE64rm = 2454,
+ VMWRITE64rr = 2455,
+ VMXOFF = 2456,
+ VMXON = 2457,
+ V_SET0 = 2458,
+ V_SETALLONES = 2459,
+ WAIT = 2460,
+ WBINVD = 2461,
+ WINCALL64m = 2462,
+ WINCALL64pcrel32 = 2463,
+ WINCALL64r = 2464,
+ WRMSR = 2465,
+ XADD16rm = 2466,
+ XADD16rr = 2467,
+ XADD32rm = 2468,
+ XADD32rr = 2469,
+ XADD64rm = 2470,
+ XADD64rr = 2471,
+ XADD8rm = 2472,
+ XADD8rr = 2473,
+ XCHG16ar = 2474,
+ XCHG16rm = 2475,
+ XCHG16rr = 2476,
+ XCHG32ar = 2477,
+ XCHG32rm = 2478,
+ XCHG32rr = 2479,
+ XCHG64ar = 2480,
+ XCHG64rm = 2481,
+ XCHG64rr = 2482,
+ XCHG8rm = 2483,
+ XCHG8rr = 2484,
+ XCH_F = 2485,
+ XLAT = 2486,
+ XOR16i16 = 2487,
+ XOR16mi = 2488,
+ XOR16mi8 = 2489,
+ XOR16mr = 2490,
+ XOR16ri = 2491,
+ XOR16ri8 = 2492,
+ XOR16rm = 2493,
+ XOR16rr = 2494,
+ XOR16rr_REV = 2495,
+ XOR32i32 = 2496,
+ XOR32mi = 2497,
+ XOR32mi8 = 2498,
+ XOR32mr = 2499,
+ XOR32ri = 2500,
+ XOR32ri8 = 2501,
+ XOR32rm = 2502,
+ XOR32rr = 2503,
+ XOR32rr_REV = 2504,
+ XOR64i32 = 2505,
+ XOR64mi32 = 2506,
+ XOR64mi8 = 2507,
+ XOR64mr = 2508,
+ XOR64ri32 = 2509,
+ XOR64ri8 = 2510,
+ XOR64rm = 2511,
+ XOR64rr = 2512,
+ XOR64rr_REV = 2513,
+ XOR8i8 = 2514,
+ XOR8mi = 2515,
+ XOR8mr = 2516,
+ XOR8ri = 2517,
+ XOR8rm = 2518,
+ XOR8rr = 2519,
+ XOR8rr_REV = 2520,
+ XORPDrm = 2521,
+ XORPDrr = 2522,
+ XORPSrm = 2523,
+ XORPSrr = 2524,
+ INSTRUCTION_LIST_END = 2525
};
}
} // End llvm namespace
diff --git a/libclamav/c++/merge.sh b/libclamav/c++/merge.sh
index dd4a43f..475a94c 100755
--- a/libclamav/c++/merge.sh
+++ b/libclamav/c++/merge.sh
@@ -7,7 +7,7 @@ echo "Creating grafts for llvm-upstream"
REPONAME=llvm
REFPFX=refs/tags/merge-$REPONAME-
-UPSTREAM=$REPONAME-upstream/master
+UPSTREAM=$REPONAME-upstream/release
git for-each-ref $REFPFX* --format='%(refname)' | while read tag_ref
do
tag_svn_ref=`echo $tag_ref|sed -e s\|$REFPFX\|\|`
@@ -19,8 +19,15 @@ do
echo "$local_ref $local_parent_ref $upstream_ref" >>.git/info/grafts
done
echo "Merging llvm-upstream"
-MERGEREV=`git log $UPSTREAM -1 |grep /trunk@|sed -s 's/.*@\([0-9]*\).*/\1/'`
-git merge -s subtree --squash llvm-upstream/master && git commit || {
-echo "Merge failed: resolve conflicts and run: git tag merge-llvm-$MERGEREV && rm .git/info/grafts"; exit 1;}
-git tag merge-llvm-$MERGEREV
-rm .git/info/grafts
+MERGEREV=`git log $UPSTREAM -1 |grep /release_27@|sed -s 's/.*@\([0-9]*\).*/\1/'`
+echo "$MERGEREV"
+git merge -s subtree --squash llvm-upstream/release
+
+echo "Run strip-llvm.sh from libclamav/c++"
+echo "Then fix conflicts if needed: git mergetool"
+echo "Then commit the result and tag it: git commit && git tag merge-llvm-$MERGEREV"
+echo "Then remove the grafts: rm .git/info/grafts"
+# && git commit || {
+# echo "Merge failed: resolve conflicts and run: git tag merge-llvm-$MERGEREV && rm .git/info/grafts"; exit 1;}
+# git tag merge-llvm-$MERGEREV
+# rm .git/info/grafts
--
Debian repository for ClamAV
More information about the Pkg-clamav-commits
mailing list