[mupen64plus] 150/262: Don't allow to override r0 register
Sven Eckelmann
ecsv-guest at moszumanska.debian.org
Thu Nov 26 05:59:28 UTC 2015
This is an automated email from the git hooks/post-receive script.
ecsv-guest pushed a commit to branch master
in repository mupen64plus.
commit 6c90880a4414be8ae8f35eeda6abd65d2c13a4bf
Author: Sven Eckelmann <sven.eckelmann at gmx.de>
Date: Sun Oct 4 01:15:36 2009 +0200
Don't allow to override r0 register
r0 on MIPS is hardwired to zero. It is allowed to write to this
register, but the result of any operation with the target register r0 is
discarded.
---
debian/changelog | 1 +
debian/patches/fix_r0_override.patch | 467 +++++++++++++++++++++++++++++++++++
debian/patches/series | 1 +
3 files changed, 469 insertions(+)
diff --git a/debian/changelog b/debian/changelog
index bf29879..ba6cb7e 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -13,6 +13,7 @@ mupen64plus (1.5+dfsg1-6) UNRELEASED; urgency=low
- Add load_aidacrate.patch, Set aiDacrate during savestate load to fix
slowdowns after savestate load
- Add load_vistatus.patch, Set video width and status during savestate load
+ - Add fix_r0_override.patch, Don't allow to override r0 register
-- Sven Eckelmann <sven.eckelmann at gmx.de> Sat, 03 Oct 2009 00:36:41 +0200
diff --git a/debian/patches/fix_r0_override.patch b/debian/patches/fix_r0_override.patch
new file mode 100644
index 0000000..b639155
--- /dev/null
+++ b/debian/patches/fix_r0_override.patch
@@ -0,0 +1,467 @@
+Description: Don't allow to override r0 register
+ r0 on MIPS is hardwired to zero. It is allowed to write to this register, but
+ the result of any operation with the target register r0 is discarded.
+Bug: http://code.google.com/p/mupen64plus/issues/detail?id=278
+Author: Sven Eckelmann <sven.eckelmann at gmx.de>
+
+---
+diff --git a/r4300/pure_interp.c b/r4300/pure_interp.c
+index d38cb9e2d00b0ade17fba2334246b20732a7a924..16cf6d810375a4d199a0f2dd54d5077c26301388 100644
+--- a/r4300/pure_interp.c
++++ b/r4300/pure_interp.c
+@@ -34,6 +34,10 @@
+ #include "../debugger/debugger.h"
+ #endif
+
++#define check_r0_rd() { if (PC->f.r.rd == reg) { interp_addr+=4; return; } }
++#define check_r0_rt() { if (PC->f.r.rt == reg) { interp_addr+=4; return; } }
++#define check_r0_irt() { if (PC->f.i.rt == reg) { interp_addr+=4; return; } }
++
+ unsigned int interp_addr;
+ unsigned int op;
+ static int skip;
+@@ -52,6 +56,7 @@ static void NI()
+
+ static void SLL()
+ {
++ check_r0_rd();
+ rrd32 = (unsigned int)(rrt32) << rsa;
+ sign_extended(rrd);
+ interp_addr+=4;
+@@ -59,6 +64,7 @@ static void SLL()
+
+ static void SRL()
+ {
++ check_r0_rd();
+ rrd32 = (unsigned int)rrt32 >> rsa;
+ sign_extended(rrd);
+ interp_addr+=4;
+@@ -66,6 +72,7 @@ static void SRL()
+
+ static void SRA()
+ {
++ check_r0_rd();
+ rrd32 = (signed int)rrt32 >> rsa;
+ sign_extended(rrd);
+ interp_addr+=4;
+@@ -73,6 +80,7 @@ static void SRA()
+
+ static void SLLV()
+ {
++ check_r0_rd();
+ rrd32 = (unsigned int)(rrt32) << (rrs32&0x1F);
+ sign_extended(rrd);
+ interp_addr+=4;
+@@ -80,6 +88,7 @@ static void SLLV()
+
+ static void SRLV()
+ {
++ check_r0_rd();
+ rrd32 = (unsigned int)rrt32 >> (rrs32 & 0x1F);
+ sign_extended(rrd);
+ interp_addr+=4;
+@@ -87,6 +96,7 @@ static void SRLV()
+
+ static void SRAV()
+ {
++ check_r0_rd();
+ rrd32 = (signed int)rrt32 >> (rrs32 & 0x1F);
+ sign_extended(rrd);
+ interp_addr+=4;
+@@ -140,6 +150,7 @@ static void SYNC()
+
+ static void MFHI()
+ {
++ check_r0_rd();
+ rrd = hi;
+ interp_addr+=4;
+ }
+@@ -152,6 +163,7 @@ static void MTHI()
+
+ static void MFLO()
+ {
++ check_r0_rd();
+ rrd = lo;
+ interp_addr+=4;
+ }
+@@ -164,18 +176,21 @@ static void MTLO()
+
+ static void DSLLV()
+ {
++ check_r0_rd();
+ rrd = rrt << (rrs32&0x3F);
+ interp_addr+=4;
+ }
+
+ static void DSRLV()
+ {
++ check_r0_rd();
+ rrd = (unsigned long long)rrt >> (rrs32 & 0x3F);
+ interp_addr+=4;
+ }
+
+ static void DSRAV()
+ {
++ check_r0_rd();
+ rrd = (long long)rrt >> (rrs32 & 0x3F);
+ interp_addr+=4;
+ }
+@@ -323,6 +338,7 @@ static void DDIVU()
+
+ static void ADD()
+ {
++ check_r0_rd();
+ rrd32 = rrs32 + rrt32;
+ sign_extended(rrd);
+ interp_addr+=4;
+@@ -330,6 +346,7 @@ static void ADD()
+
+ static void ADDU()
+ {
++ check_r0_rd();
+ rrd32 = rrs32 + rrt32;
+ sign_extended(rrd);
+ interp_addr+=4;
+@@ -337,6 +354,7 @@ static void ADDU()
+
+ static void SUB()
+ {
++ check_r0_rd();
+ rrd32 = rrs32 - rrt32;
+ sign_extended(rrd);
+ interp_addr+=4;
+@@ -344,6 +362,7 @@ static void SUB()
+
+ static void SUBU()
+ {
++ check_r0_rd();
+ rrd32 = rrs32 - rrt32;
+ sign_extended(rrd);
+ interp_addr+=4;
+@@ -351,30 +370,35 @@ static void SUBU()
+
+ static void AND()
+ {
++ check_r0_rd();
+ rrd = rrs & rrt;
+ interp_addr+=4;
+ }
+
+ static void OR()
+ {
++ check_r0_rd();
+ rrd = rrs | rrt;
+ interp_addr+=4;
+ }
+
+ static void XOR()
+ {
++ check_r0_rd();
+ rrd = rrs ^ rrt;
+ interp_addr+=4;
+ }
+
+ static void NOR()
+ {
++ check_r0_rd();
+ rrd = ~(rrs | rrt);
+ interp_addr+=4;
+ }
+
+ static void SLT()
+ {
++ check_r0_rd();
+ if (rrs < rrt) rrd = 1;
+ else rrd = 0;
+ interp_addr+=4;
+@@ -382,6 +406,7 @@ static void SLT()
+
+ static void SLTU()
+ {
++ check_r0_rd();
+ if ((unsigned long long)rrs < (unsigned long long)rrt)
+ rrd = 1;
+ else rrd = 0;
+@@ -390,24 +415,28 @@ static void SLTU()
+
+ static void DADD()
+ {
++ check_r0_rd();
+ rrd = rrs + rrt;
+ interp_addr+=4;
+ }
+
+ static void DADDU()
+ {
++ check_r0_rd();
+ rrd = rrs + rrt;
+ interp_addr+=4;
+ }
+
+ static void DSUB()
+ {
++ check_r0_rd();
+ rrd = rrs - rrt;
+ interp_addr+=4;
+ }
+
+ static void DSUBU()
+ {
++ check_r0_rd();
+ rrd = rrs - rrt;
+ interp_addr+=4;
+ }
+@@ -424,36 +453,42 @@ static void TEQ()
+
+ static void DSLL()
+ {
++ check_r0_rd();
+ rrd = rrt << rsa;
+ interp_addr+=4;
+ }
+
+ static void DSRL()
+ {
++ check_r0_rd();
+ rrd = (unsigned long long)rrt >> rsa;
+ interp_addr+=4;
+ }
+
+ static void DSRA()
+ {
++ check_r0_rd();
+ rrd = rrt >> rsa;
+ interp_addr+=4;
+ }
+
+ static void DSLL32()
+ {
++ check_r0_rd();
+ rrd = rrt << (32+rsa);
+ interp_addr+=4;
+ }
+
+ static void DSRL32()
+ {
++ check_r0_rd();
+ rrd = (unsigned long long int)rrt >> (32+rsa);
+ interp_addr+=4;
+ }
+
+ static void DSRA32()
+ {
++ check_r0_rd();
+ rrd = (signed long long int)rrt >> (32+rsa);
+ interp_addr+=4;
+ }
+@@ -982,6 +1017,7 @@ static void MFC0()
+ printf("lecture de Random\n");
+ stop=1;
+ default:
++ check_r0_rt();
+ rrt32 = reg_cop0[PC->f.r.nrd];
+ sign_extended(rrt);
+ }
+@@ -1932,6 +1968,7 @@ static void (*interp_cop1_l[64])(void) =
+
+ static void MFC1()
+ {
++ check_r0_rt();
+ rrt32 = *((int*)reg_cop1_simple[rfs]);
+ sign_extended(rrt);
+ interp_addr+=4;
+@@ -1939,12 +1976,14 @@ static void MFC1()
+
+ static void DMFC1()
+ {
++ check_r0_rt();
+ rrt = *((long long*)(reg_cop1_double[rfs]));
+ interp_addr+=4;
+ }
+
+ static void CFC1()
+ {
++ check_r0_rt();
+ if (rfs==31)
+ {
+ rrt32 = FCR31;
+@@ -2221,6 +2260,7 @@ static void BGTZ()
+
+ static void ADDI()
+ {
++ check_r0_irt();
+ irt32 = irs32 + iimmediate;
+ sign_extended(irt);
+ interp_addr+=4;
+@@ -2228,6 +2268,7 @@ static void ADDI()
+
+ static void ADDIU()
+ {
++ check_r0_irt();
+ irt32 = irs32 + iimmediate;
+ sign_extended(irt);
+ interp_addr+=4;
+@@ -2235,6 +2276,7 @@ static void ADDIU()
+
+ static void SLTI()
+ {
++ check_r0_irt();
+ if (irs < iimmediate) irt = 1;
+ else irt = 0;
+ interp_addr+=4;
+@@ -2242,6 +2284,7 @@ static void SLTI()
+
+ static void SLTIU()
+ {
++ check_r0_irt();
+ if ((unsigned long long)irs < (unsigned long long)((long long)iimmediate))
+ irt = 1;
+ else irt = 0;
+@@ -2250,24 +2293,28 @@ static void SLTIU()
+
+ static void ANDI()
+ {
++ check_r0_irt();
+ irt = irs & (unsigned short)iimmediate;
+ interp_addr+=4;
+ }
+
+ static void ORI()
+ {
++ check_r0_irt();
+ irt = irs | (unsigned short)iimmediate;
+ interp_addr+=4;
+ }
+
+ static void XORI()
+ {
++ check_r0_irt();
+ irt = irs ^ (unsigned short)iimmediate;
+ interp_addr+=4;
+ }
+
+ static void LUI()
+ {
++ check_r0_irt();
+ irt32 = iimmediate << 16;
+ sign_extended(irt);
+ interp_addr+=4;
+@@ -2436,12 +2483,14 @@ static void BGTZL()
+
+ static void DADDI()
+ {
++ check_r0_irt();
+ irt = irs + iimmediate;
+ interp_addr+=4;
+ }
+
+ static void DADDIU()
+ {
++ check_r0_irt();
+ irt = irs + iimmediate;
+ interp_addr+=4;
+ }
+@@ -2449,6 +2498,7 @@ static void DADDIU()
+ static void LDL()
+ {
+ unsigned long long int word = 0;
++ check_r0_irt();
+ interp_addr+=4;
+ switch ((iimmediate + irs32) & 7)
+ {
+@@ -2505,6 +2555,7 @@ static void LDL()
+ static void LDR()
+ {
+ unsigned long long int word = 0;
++ check_r0_irt();
+ interp_addr+=4;
+ switch ((iimmediate + irs32) & 7)
+ {
+@@ -2560,6 +2611,7 @@ static void LDR()
+
+ static void LB()
+ {
++ check_r0_irt();
+ interp_addr+=4;
+ address = iimmediate + irs32;
+ rdword = (unsigned long long *) &irt;
+@@ -2569,6 +2621,7 @@ static void LB()
+
+ static void LH()
+ {
++ check_r0_irt();
+ interp_addr+=4;
+ address = iimmediate + irs32;
+ rdword = (unsigned long long *) &irt;
+@@ -2579,6 +2632,7 @@ static void LH()
+ static void LWL()
+ {
+ unsigned long long int word = 0;
++ check_r0_irt();
+ interp_addr+=4;
+ switch ((iimmediate + irs32) & 3)
+ {
+@@ -2611,6 +2665,7 @@ static void LWL()
+
+ static void LW()
+ {
++ check_r0_irt();
+ address = iimmediate + irs32;
+ rdword = (unsigned long long *) &irt;
+ interp_addr+=4;
+@@ -2620,6 +2675,7 @@ static void LW()
+
+ static void LBU()
+ {
++ check_r0_irt();
+ interp_addr+=4;
+ address = iimmediate + irs32;
+ rdword = (unsigned long long *) &irt;
+@@ -2628,6 +2684,7 @@ static void LBU()
+
+ static void LHU()
+ {
++ check_r0_irt();
+ interp_addr+=4;
+ address = iimmediate + irs32;
+ rdword = (unsigned long long *) &irt;
+@@ -2637,6 +2694,7 @@ static void LHU()
+ static void LWR()
+ {
+ unsigned long long int word = 0;
++ check_r0_irt();
+ interp_addr+=4;
+ switch ((iimmediate + irs32) & 3)
+ {
+@@ -2668,6 +2726,7 @@ static void LWR()
+
+ static void LWU()
+ {
++ check_r0_irt();
+ address = iimmediate + irs32;
+ rdword = (unsigned long long *) &irt;
+ interp_addr+=4;
+@@ -2899,6 +2958,7 @@ static void CACHE()
+
+ static void LL()
+ {
++ check_r0_irt();
+ address = iimmediate + irs32;
+ rdword = (unsigned long long *) &irt;
+ interp_addr+=4;
+@@ -2929,6 +2989,7 @@ static void LDC1()
+
+ static void LD()
+ {
++ check_r0_irt();
+ interp_addr+=4;
+ address = iimmediate + irs32;
+ rdword = (unsigned long long *) &irt;
+@@ -2937,6 +2998,7 @@ static void LD()
+
+ static void SC()
+ {
++ check_r0_irt();
+ interp_addr+=4;
+ if(llbit)
+ {
diff --git a/debian/patches/series b/debian/patches/series
index ecb467e..ec7dc0f 100644
--- a/debian/patches/series
+++ b/debian/patches/series
@@ -30,3 +30,4 @@ interpreter_x86_fldcw.patch
correct_fpr32_mapping.patch
load_aidacrate.patch
load_vistatus.patch
+fix_r0_override.patch
--
Alioth's /usr/local/bin/git-commit-notice on /srv/git.debian.org/git/pkg-games/mupen64plus.git
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