[SCM] libav/experimental: PPC970 patch + cpu-specific tuning support by (Romain Dolbeau <dolbeau at irisa dot fr>)
siretart at users.alioth.debian.org
siretart at users.alioth.debian.org
Sun Jun 30 15:36:41 UTC 2013
The following commit has been merged in the experimental branch:
commit a4adb60858f1fa0b35b08576ea34e531f0f83459
Author: Michael Niedermayer <michaelni at gmx.at>
Date: Sun Jun 29 00:39:57 2003 +0000
PPC970 patch + cpu-specific tuning support by (Romain Dolbeau <dolbeau at irisa dot fr>)
Originally committed as revision 1997 to svn://svn.ffmpeg.org/ffmpeg/trunk
diff --git a/configure b/configure
index 787bf38..a92137e 100755
--- a/configure
+++ b/configure
@@ -26,6 +26,7 @@ ranlib="ranlib"
make="make"
strip="strip"
cpu=`uname -m`
+tune="generic"
mmx="default"
altivec="default"
mmi="default"
@@ -272,6 +273,8 @@ for opt do
;;
--cpu=*) cpu=`echo $opt | cut -d '=' -f 2`
;;
+ --tune=*) tune=`echo $opt | cut -d '=' -f 2`
+ ;;
--disable-mmx) mmx="no"
;;
--disable-altivec) altivec="no"
@@ -351,6 +354,58 @@ if test $altivec = "default"; then
fi
fi
+# Add processor-specific flags
+TUNECPU="generic"
+if test $tune != "generic"; then
+ case $tune in
+ 601|ppc601|PowerPC601)
+ CFLAGS="$CFLAGS -mcpu=601"
+ if test $altivec = "yes"; then
+ echo "WARNING: tuning for PPC601 but altivec enabled !";
+ fi
+ TUNECPU=ppc601
+ ;;
+ 603*|ppc603*|PowerPC603*)
+ CFLAGS="$CFLAGS -mcpu=603"
+ if test $altivec = "yes"; then
+ echo "WARNING: tuning for PPC603 but altivec enabled !";
+ fi
+ TUNECPU=ppc603
+ ;;
+ 604*|ppc604*|PowerPC604*)
+ CFLAGS="$CFLAGS -mcpu=604"
+ if test $altivec = "yes"; then
+ echo "WARNING: tuning for PPC604 but altivec enabled !";
+ fi
+ TUNECPU=ppc604
+ ;;
+ G3|75*|ppc75*|PowerPC75*)
+ CFLAGS="$CFLAGS -mcpu=750"
+ if test $altivec = "yes"; then
+ echo "WARNING: tuning for PPC75x but altivec enabled !";
+ fi
+ TUNECPU=ppc750
+ ;;
+ G4|74*|ppc74*|PowerPC74*)
+ CFLAGS="$CFLAGS -mcpu=7400"
+ if test $altivec = "no"; then
+ echo "WARNING: tuning for PPC74xx but altivec disabled !";
+ fi
+ TUNECPU=ppc7400
+ ;;
+ G5|970|ppc970|PowerPC970|power4*|Power4*)
+ CFLAGS="$CFLAGS -mcpu=970 -mtune=970 -mpowerpc64 -force_cpusubtype_ALL "
+ if test $altivec = "no"; then
+ echo "WARNING: tuning for PPC970 but altivec disabled !";
+ fi
+ TUNECPU=ppc970
+ ;;
+ *)
+ echo "WARNING: unknown CPU "$tune", ignored"
+ ;;
+ esac
+fi
+
# See if we have <altivec.h>
cat > $TMPC << EOF
#include <altivec.h>
@@ -686,6 +741,7 @@ echo " --extra-cflags=ECFLAGS add ECFLAGS to CFLAGS [$CFLAGS]"
echo " --extra-ldflags=ELDFLAGS add ELDFLAGS to LDFLAGS [$LDFLAGS]"
echo " --extra-libs=ELIBS add ELIBS [$ELIBS]"
echo " --cpu=CPU force cpu to CPU [$cpu]"
+echo " --tune=PROCESSOR tune code for a particular CPU (may fails or misperforms on other CPUs)"
echo " --disable-mmx disable mmx usage"
echo " --disable-altivec disable AltiVec usage"
echo " --disable-audio-oss disable OSS audio support [default=no]"
@@ -712,7 +768,7 @@ echo "Install prefix $prefix"
echo "Source path $source_path"
echo "C compiler $cc"
echo "make $make"
-echo "CPU $cpu"
+echo "CPU $cpu ($tune)"
echo "Big Endian $bigendian"
if test $cpu = "x86"; then
echo "MMX enabled $mmx"
@@ -792,6 +848,7 @@ elif test "$cpu" = "mips" ; then
echo "TARGET_ARCH_MIPS=yes" >> config.mak
echo "#define ARCH_MIPS 1" >> $TMPH
fi
+echo "#define TUNECPU $TUNECPU" >> $TMPH
if test "$bigendian" = "yes" ; then
echo "WORDS_BIGENDIAN=yes" >> config.mak
echo "#define WORDS_BIGENDIAN 1" >> $TMPH
diff --git a/libavcodec/ppc/dsputil_ppc.c b/libavcodec/ppc/dsputil_ppc.c
index 374309e..8a5de9d 100644
--- a/libavcodec/ppc/dsputil_ppc.c
+++ b/libavcodec/ppc/dsputil_ppc.c
@@ -57,7 +57,8 @@ static unsigned char* perfname[] = {
"put_no_rnd_pixels8_xy2_altivec",
"put_pixels16_xy2_altivec",
"put_no_rnd_pixels16_xy2_altivec",
- "clear_blocks_dcbz32_ppc"
+ "clear_blocks_dcbz32_ppc",
+ "clear_blocks_dcbz128_ppc"
};
#ifdef POWERPC_PERF_USE_PMC
unsigned long long perfdata_miss[powerpc_perf_total][powerpc_data_total];
@@ -110,6 +111,18 @@ void powerpc_display_perf_report(void)
It simply clear to zero a single cache line,
so you need to know the cache line size to use it !
It's absurd, but it's fast...
+
+ update 24/06/2003 : Apple released yesterday the G5,
+ with a PPC970. cache line size : 128 bytes. Oups.
+ The semantic of dcbz was changed, it always clear
+ 32 bytes. so the function below will work, but will
+ be slow. So I fixed check_dcbz_effect to use dcbzl,
+ which is defined to clear a cache line (as dcbz before).
+ So we still can distinguish, and use dcbz (32 bytes)
+ or dcbzl (one cache line) as required.
+
+ see <http://developer.apple.com/technotes/tn/tn2087.html>
+ and <http://developer.apple.com/technotes/tn/tn2086.html>
*/
void clear_blocks_dcbz32_ppc(DCTELEM *blocks)
{
@@ -126,7 +139,7 @@ POWERPC_TBL_START_COUNT(powerpc_clear_blocks_dcbz32, 1);
i += 16;
}
for ( ; i < sizeof(DCTELEM)*6*64 ; i += 32) {
- asm volatile("dcbz %0,%1" : : "r" (blocks), "r" (i) : "memory");
+ asm volatile("dcbz %0,%1" : : "r" (i), "r" (blocks) : "memory");
}
if (misal) {
((unsigned long*)blocks)[188] = 0L;
@@ -141,8 +154,45 @@ POWERPC_TBL_START_COUNT(powerpc_clear_blocks_dcbz32, 1);
POWERPC_TBL_STOP_COUNT(powerpc_clear_blocks_dcbz32, 1);
}
+/* same as above, when dcbzl clear a whole 128B cache line
+ i.e. the PPC970 aka G5 */
+#ifndef NO_DCBZL
+void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
+{
+POWERPC_TBL_DECLARE(powerpc_clear_blocks_dcbz128, 1);
+ register int misal = ((unsigned long)blocks & 0x0000007f);
+ register int i = 0;
+POWERPC_TBL_START_COUNT(powerpc_clear_blocks_dcbz128, 1);
+#if 1
+ if (misal) {
+ // we could probably also optimize this case,
+ // but there's not much point as the machines
+ // aren't available yet (2003-06-26)
+ memset(blocks, 0, sizeof(DCTELEM)*6*64);
+ }
+ else
+ for ( ; i < sizeof(DCTELEM)*6*64 ; i += 128) {
+ asm volatile("dcbzl %0,%1" : : "r" (i), "r" (blocks) : "memory");
+ }
+#else
+ memset(blocks, 0, sizeof(DCTELEM)*6*64);
+#endif
+POWERPC_TBL_STOP_COUNT(powerpc_clear_blocks_dcbz128, 1);
+}
+#else
+void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
+{
+ memset(blocks, 0, sizeof(DCTELEM)*6*64);
+}
+#endif
+
+#ifndef NO_DCBZL
/* check dcbz report how many bytes are set to 0 by dcbz */
-long check_dcbz_effect(void)
+/* update 24/06/2003 : replace dcbz by dcbzl to get
+ the intended effect (Apple "fixed" dcbz)
+ unfortunately this cannot be used unless the assembler
+ knows about dcbzl ... */
+long check_dcbzl_effect(void)
{
register char *fakedata = (char*)av_malloc(1024);
register char *fakedata_middle;
@@ -159,7 +209,7 @@ long check_dcbz_effect(void)
memset(fakedata, 0xFF, 1024);
- asm volatile("dcbz %0, %1" : : "r" (fakedata_middle), "r" (zero));
+ asm volatile("dcbzl %0, %1" : : "r" (fakedata_middle), "r" (zero));
for (i = 0; i < 1024 ; i ++)
{
@@ -171,15 +221,24 @@ long check_dcbz_effect(void)
return count;
}
+#else
+long check_dcbzl_effect(void)
+{
+ return 0;
+}
+#endif
void dsputil_init_ppc(DSPContext* c, AVCodecContext *avctx)
{
- // Common optimisations whether Altivec or not
+ // Common optimizations whether Altivec is available or not
- switch (check_dcbz_effect()) {
+ switch (check_dcbzl_effect()) {
case 32:
c->clear_blocks = clear_blocks_dcbz32_ppc;
break;
+ case 128:
+ c->clear_blocks = clear_blocks_dcbz128_ppc;
+ break;
default:
break;
}
diff --git a/libavcodec/ppc/dsputil_ppc.h b/libavcodec/ppc/dsputil_ppc.h
index ef1481a..0e619ee 100644
--- a/libavcodec/ppc/dsputil_ppc.h
+++ b/libavcodec/ppc/dsputil_ppc.h
@@ -37,6 +37,7 @@ enum powerpc_perf_index {
altivec_put_pixels16_xy2_num,
altivec_put_no_rnd_pixels16_xy2_num,
powerpc_clear_blocks_dcbz32,
+ powerpc_clear_blocks_dcbz128,
powerpc_perf_total
};
enum powerpc_data_index {
diff --git a/libavcodec/ppc/gcc_fixes.h b/libavcodec/ppc/gcc_fixes.h
index 855a5b4..653378d 100644
--- a/libavcodec/ppc/gcc_fixes.h
+++ b/libavcodec/ppc/gcc_fixes.h
@@ -13,9 +13,15 @@
#ifdef CONFIG_DARWIN
#define AVV(x...) (x)
+/* The Apple assembler shipped w/ gcc-3.3 knows about DCBZL, previous assemblers don't
+ We assume here that the Darwin GCC is from Apple.... */
+#if (__GNUC__ * 100 + __GNUC_MINOR__ < 303)
+#define NO_DCBZL
+#endif
#else
#define AVV(x...) {x}
-
+/* I don't think any non-Apple assembler knows about DCBZL */
+#define NO_DCBZL
#if (__GNUC__ * 100 + __GNUC_MINOR__ < 303)
/* This code was provided to me by Bartosch Pixa
--
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