[beignet] 02/06: Disable fast atomics, they break too much

[Rebecca Palmer]

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rnpalmer-guest pushed a commit to branch master
in repository beignet.

commit a88e76f3f47ad38c3ed12c36f7fb00f83c2344de
Author: Rebecca N. Palmer <rebecca_palmer at zoho.com>
Date:   Tue May 19 08:51:23 2015 +0100

    Disable fast atomics, they break too much
---
 debian/changelog                                 |  1 +
 debian/patches/disable-broken-fast-atomics.patch | 50 ++++++++++++++++++++++++
 debian/patches/series                            |  1 +
 3 files changed, 52 insertions(+)

diff --git a/debian/changelog b/debian/changelog
index d6e73c6..3a14dc4 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -14,6 +14,7 @@ beignet (1.0.3-1) UNRELEASED; urgency=medium
   * Disable devices where __local silently does nothing,
     and document workarounds.
   * Make libx11-dev dependency explicit.
+  * Disable fast atomics, they break too much.
 
  -- Rebecca N. Palmer <rebecca_palmer at zoho.com>  Fri, 24 Apr 2015 21:16:12 +0100
 
diff --git a/debian/patches/disable-broken-fast-atomics.patch b/debian/patches/disable-broken-fast-atomics.patch
new file mode 100644
index 0000000..61f0b9e
--- /dev/null
+++ b/debian/patches/disable-broken-fast-atomics.patch
@@ -0,0 +1,50 @@
+Description: Disable fast atomics, they break Haswell
+
+Revert "CL/Driver: enable atomics in L3 for HSW."
+(upstream ef7127c03bd533277afc443b335c37a69927250a)
+
+This optimization is rejected by a Linux security mechanism,
+making all kernels fail to run on Haswell with
+"drm_intel_gem_bo_context_exec() failed: Invalid argument"
+
+Origin: upstream 83f8739b6fc4893fac60145326052ccb5cf653dc
+Author: Zhigang Gong <zhigang.gong at intel.com>
+
+diff --git a/src/intel/intel_defines.h b/src/intel/intel_defines.h
+index 651e285..1080a91 100644
+--- a/src/intel/intel_defines.h
++++ b/src/intel/intel_defines.h
+@@ -305,10 +305,6 @@
+ #define URB_SIZE(intel)         (IS_IGDNG(intel->device_id) ? 1024 : \
+                                  IS_G4X(intel->device_id) ? 384 : 256)
+ 
+-// HSW
+-#define HSW_SCRATCH1_OFFSET                      (0xB038)
+-#define HSW_ROW_CHICKEN3_HDC_OFFSET              (0xE49C)
+-
+ // L3 cache stuff 
+ #define GEN7_L3_SQC_REG1_ADDRESS_OFFSET          (0XB010)
+ #define GEN7_L3_CNTL_REG2_ADDRESS_OFFSET         (0xB020)
+diff --git a/src/intel/intel_gpgpu.c b/src/intel/intel_gpgpu.c
+index ab4545e..b083dab 100644
+--- a/src/intel/intel_gpgpu.c
++++ b/src/intel/intel_gpgpu.c
+@@ -719,16 +719,7 @@ static void
+ intel_gpgpu_set_L3_gen75(intel_gpgpu_t *gpgpu, uint32_t use_slm)
+ {
+   /* still set L3 in batch buffer for fulsim. */
+-  BEGIN_BATCH(gpgpu->batch, 15);
+-  OUT_BATCH(gpgpu->batch, CMD_LOAD_REGISTER_IMM | 1); /* length - 2 */
+-  /* FIXME: KMD always disable the atomic in L3 for some reason.
+-     I checked the spec, and don't think we need that workaround now.
+-     Before I send a patch to kernel, let's just enable it here. */
+-  OUT_BATCH(gpgpu->batch, HSW_SCRATCH1_OFFSET);
+-  OUT_BATCH(gpgpu->batch, 0);                         /* enable atomic in L3 */
+-  OUT_BATCH(gpgpu->batch, CMD_LOAD_REGISTER_IMM | 1); /* length - 2 */
+-  OUT_BATCH(gpgpu->batch, HSW_ROW_CHICKEN3_HDC_OFFSET);
+-  OUT_BATCH(gpgpu->batch, (1 << 6ul) << 16);          /* enable atomic in L3 */
++  BEGIN_BATCH(gpgpu->batch, 9);
+   OUT_BATCH(gpgpu->batch, CMD_LOAD_REGISTER_IMM | 1); /* length - 2 */
+   OUT_BATCH(gpgpu->batch, GEN7_L3_SQC_REG1_ADDRESS_OFFSET);
+   OUT_BATCH(gpgpu->batch, 0x08800000);
+
diff --git a/debian/patches/series b/debian/patches/series
index 9275b5b..60b32b1 100644
--- a/debian/patches/series
+++ b/debian/patches/series
@@ -8,3 +8,4 @@ builtin_pow-fix-spurious-failure.patch
 tgamma-accuracy.patch
 python3.patch
 self-test.patch
+disable-broken-fast-atomics.patch

-- 
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