[libclc] 81/291: Add intN vloadN() implementations for address spaces 3 and 4

[Andreas Beckmann]

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anbe pushed a commit to branch master
in repository libclc.

commit 227cc19cb126903bd284198e05d96f6cbd92bf3e
Author: Aaron Watry <awatry at gmail.com>
Date:   Mon Aug 12 14:42:51 2013 +0000

    Add intN vloadN() implementations for address spaces 3 and 4
    
    Not hooked up to R600 yet due to current lack of support, at least on EG.
    
    Signed-off-by: Aaron Watry <awatry at gmail.com>
    Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
    
    git-svn-id: https://llvm.org/svn/llvm-project/libclc/trunk@188181 91177308-0d34-0410-b5e6-96231b3b80d8
---
 generic/lib/shared/vload_impl.ll | 60 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/generic/lib/shared/vload_impl.ll b/generic/lib/shared/vload_impl.ll
index 2416aaf..33ba996 100644
--- a/generic/lib/shared/vload_impl.ll
+++ b/generic/lib/shared/vload_impl.ll
@@ -61,6 +61,66 @@ define <16 x i32> @__clc_vload16_i32__addr2(i32 addrspace(2)* nocapture %addr) n
   ret <16 x i32> %2
 }
 
+define <2 x i32> @__clc_vload2_i32__addr3(i32 addrspace(3)* nocapture %addr) nounwind readonly alwaysinline {
+  %1 = bitcast i32 addrspace(3)* %addr to <2 x i32> addrspace(3)*
+  %2 = load <2 x i32> addrspace(3)* %1, align 4, !tbaa !3
+  ret <2 x i32> %2
+}
+
+define <3 x i32> @__clc_vload3_i32__addr3(i32 addrspace(3)* nocapture %addr) nounwind readonly alwaysinline {
+  %1 = bitcast i32 addrspace(3)* %addr to <3 x i32> addrspace(3)*
+  %2 = load <3 x i32> addrspace(3)* %1, align 4, !tbaa !3
+  ret <3 x i32> %2
+}
+
+define <4 x i32> @__clc_vload4_i32__addr3(i32 addrspace(3)* nocapture %addr) nounwind readonly alwaysinline {
+  %1 = bitcast i32 addrspace(3)* %addr to <4 x i32> addrspace(3)*
+  %2 = load <4 x i32> addrspace(3)* %1, align 4, !tbaa !3
+  ret <4 x i32> %2
+}
+
+define <8 x i32> @__clc_vload8_i32__addr3(i32 addrspace(3)* nocapture %addr) nounwind readonly alwaysinline {
+  %1 = bitcast i32 addrspace(3)* %addr to <8 x i32> addrspace(3)*
+  %2 = load <8 x i32> addrspace(3)* %1, align 4, !tbaa !3
+  ret <8 x i32> %2
+}
+
+define <16 x i32> @__clc_vload16_i32__addr3(i32 addrspace(3)* nocapture %addr) nounwind readonly alwaysinline {
+  %1 = bitcast i32 addrspace(3)* %addr to <16 x i32> addrspace(3)*
+  %2 = load <16 x i32> addrspace(3)* %1, align 4, !tbaa !3
+  ret <16 x i32> %2
+}
+
+define <2 x i32> @__clc_vload2_i32__addr4(i32 addrspace(4)* nocapture %addr) nounwind readonly alwaysinline {
+  %1 = bitcast i32 addrspace(4)* %addr to <2 x i32> addrspace(4)*
+  %2 = load <2 x i32> addrspace(4)* %1, align 4, !tbaa !3
+  ret <2 x i32> %2
+}
+
+define <3 x i32> @__clc_vload3_i32__addr4(i32 addrspace(4)* nocapture %addr) nounwind readonly alwaysinline {
+  %1 = bitcast i32 addrspace(4)* %addr to <3 x i32> addrspace(4)*
+  %2 = load <3 x i32> addrspace(4)* %1, align 4, !tbaa !3
+  ret <3 x i32> %2
+}
+
+define <4 x i32> @__clc_vload4_i32__addr4(i32 addrspace(4)* nocapture %addr) nounwind readonly alwaysinline {
+  %1 = bitcast i32 addrspace(4)* %addr to <4 x i32> addrspace(4)*
+  %2 = load <4 x i32> addrspace(4)* %1, align 4, !tbaa !3
+  ret <4 x i32> %2
+}
+
+define <8 x i32> @__clc_vload8_i32__addr4(i32 addrspace(4)* nocapture %addr) nounwind readonly alwaysinline {
+  %1 = bitcast i32 addrspace(4)* %addr to <8 x i32> addrspace(4)*
+  %2 = load <8 x i32> addrspace(4)* %1, align 4, !tbaa !3
+  ret <8 x i32> %2
+}
+
+define <16 x i32> @__clc_vload16_i32__addr4(i32 addrspace(4)* nocapture %addr) nounwind readonly alwaysinline {
+  %1 = bitcast i32 addrspace(4)* %addr to <16 x i32> addrspace(4)*
+  %2 = load <16 x i32> addrspace(4)* %1, align 4, !tbaa !3
+  ret <16 x i32> %2
+}
+
 !1 = metadata !{metadata !"char", metadata !5}
 !2 = metadata !{metadata !"short", metadata !5}
 !3 = metadata !{metadata !"int", metadata !5}

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