r46490 - in /branches/upstream/libverilog-perl/current: ./ Netlist/ Parser/ Preproc/ t/ verilog/

jawnsy-guest at users.alioth.debian.org jawnsy-guest at users.alioth.debian.org
Thu Oct 29 01:54:47 UTC 2009


Author: jawnsy-guest
Date: Thu Oct 29 01:54:42 2009
New Revision: 46490

URL: http://svn.debian.org/wsvn/pkg-perl/?sc=1&rev=46490
Log:
[svn-upgrade] Integrating new upstream version, libverilog-perl (3.221)

Modified:
    branches/upstream/libverilog-perl/current/Changes
    branches/upstream/libverilog-perl/current/EditFiles.pm
    branches/upstream/libverilog-perl/current/Getopt.pm
    branches/upstream/libverilog-perl/current/Language.pm
    branches/upstream/libverilog-perl/current/META.yml
    branches/upstream/libverilog-perl/current/Netlist.pm
    branches/upstream/libverilog-perl/current/Netlist/Cell.pm
    branches/upstream/libverilog-perl/current/Netlist/ContAssign.pm
    branches/upstream/libverilog-perl/current/Netlist/File.pm
    branches/upstream/libverilog-perl/current/Netlist/Interface.pm
    branches/upstream/libverilog-perl/current/Netlist/Module.pm
    branches/upstream/libverilog-perl/current/Netlist/Net.pm
    branches/upstream/libverilog-perl/current/Netlist/Pin.pm
    branches/upstream/libverilog-perl/current/Netlist/Port.pm
    branches/upstream/libverilog-perl/current/Netlist/Subclass.pm
    branches/upstream/libverilog-perl/current/Parser/Parser.pm
    branches/upstream/libverilog-perl/current/Parser/SigParser.pm
    branches/upstream/libverilog-perl/current/Parser/VParseLex.l
    branches/upstream/libverilog-perl/current/Parser/bisonpre
    branches/upstream/libverilog-perl/current/Parser/callbackgen
    branches/upstream/libverilog-perl/current/Preproc/Preproc.pm
    branches/upstream/libverilog-perl/current/Preproc/VPreproc.cpp
    branches/upstream/libverilog-perl/current/Preproc/VPreprocLex.l
    branches/upstream/libverilog-perl/current/Std.pm
    branches/upstream/libverilog-perl/current/t/34_parser.out
    branches/upstream/libverilog-perl/current/t/35_sigparser.out
    branches/upstream/libverilog-perl/current/verilog/parser_bugs.v
    branches/upstream/libverilog-perl/current/vhier
    branches/upstream/libverilog-perl/current/vpassert
    branches/upstream/libverilog-perl/current/vppreproc
    branches/upstream/libverilog-perl/current/vrename

Modified: branches/upstream/libverilog-perl/current/Changes
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/Changes?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/Changes (original)
+++ branches/upstream/libverilog-perl/current/Changes Thu Oct 29 01:54:42 2009
@@ -2,6 +2,16 @@
 
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
+
+* Verilog::Language 3.221 2009/10/28
+
+****	Fix SystemPerl hitting "undefined find_interface..." in 3.220.
+
+****	Fix erroring on strings with backslashed newlines, bug168. [Pete Nixon]
+
+****	Fix compile error on RHEL3 with gettext, bug169. [Marek Rouchal]
+
+****	Fix line number miscounting with `pragma.
 
 * Verilog::Language 3.220 2009/09/30
 

Modified: branches/upstream/libverilog-perl/current/EditFiles.pm
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/EditFiles.pm?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/EditFiles.pm (original)
+++ branches/upstream/libverilog-perl/current/EditFiles.pm Thu Oct 29 01:54:42 2009
@@ -13,7 +13,7 @@
 ######################################################################
 #### Configuration Section
 
-$VERSION = '3.220';
+$VERSION = '3.221';
 
 #######################################################################
 # CONSTRUCTORS

Modified: branches/upstream/libverilog-perl/current/Getopt.pm
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/Getopt.pm?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/Getopt.pm (original)
+++ branches/upstream/libverilog-perl/current/Getopt.pm Thu Oct 29 01:54:42 2009
@@ -16,7 +16,7 @@
 ######################################################################
 #### Configuration Section
 
-$VERSION = '3.220';
+$VERSION = '3.221';
 
 # Basenames we should ignore when recursing directories,
 # Because they contain large files of no relevance

Modified: branches/upstream/libverilog-perl/current/Language.pm
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/Language.pm?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/Language.pm (original)
+++ branches/upstream/libverilog-perl/current/Language.pm Thu Oct 29 01:54:42 2009
@@ -187,7 +187,7 @@
 ######################################################################
 #### Configuration Section
 
-$VERSION = '3.220';
+$VERSION = '3.221';
 
 ######################################################################
 #### Internal Variables

Modified: branches/upstream/libverilog-perl/current/META.yml
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/META.yml?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/META.yml (original)
+++ branches/upstream/libverilog-perl/current/META.yml Thu Oct 29 01:54:42 2009
@@ -1,6 +1,6 @@
 # http://module-build.sourceforge.net/META-spec.html
 name:         Verilog-Perl
-version:      3.220
+version:      3.221
 version_from: Language.pm
 license:      perl
 installdirs:  site

Modified: branches/upstream/libverilog-perl/current/Netlist.pm
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/Netlist.pm?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/Netlist.pm (original)
+++ branches/upstream/libverilog-perl/current/Netlist.pm Thu Oct 29 01:54:42 2009
@@ -14,7 +14,7 @@
 use strict;
 use vars qw($Debug $Verbose $VERSION);
 
-$VERSION = '3.220';
+$VERSION = '3.221';
 
 ######################################################################
 #### Error Handling

Modified: branches/upstream/libverilog-perl/current/Netlist/Cell.pm
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/Netlist/Cell.pm?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/Netlist/Cell.pm (original)
+++ branches/upstream/libverilog-perl/current/Netlist/Cell.pm Thu Oct 29 01:54:42 2009
@@ -12,7 +12,7 @@
 @ISA = qw(Verilog::Netlist::Cell::Struct
 	Verilog::Netlist::Subclass);
 
-$VERSION = '3.220';
+$VERSION = '3.221';
 
 structs('new',
 	'Verilog::Netlist::Cell::Struct'
@@ -66,7 +66,7 @@
 	    my $sm = $netlist->find_module_or_interface_for_cell ($name);
 	    if (!$sm) {
 		my $name2 = $netlist->remove_defines($name);
-		$sm = $netlist->find_module_or_inteface_for_cell ($name2)
+		$sm = $netlist->find_module_or_interface_for_cell ($name2)
 		    if $name ne $name2;
 	    }
 	    if ($sm) {

Modified: branches/upstream/libverilog-perl/current/Netlist/ContAssign.pm
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/Netlist/ContAssign.pm?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/Netlist/ContAssign.pm (original)
+++ branches/upstream/libverilog-perl/current/Netlist/ContAssign.pm Thu Oct 29 01:54:42 2009
@@ -12,7 +12,7 @@
 @ISA = qw(Verilog::Netlist::ContAssign::Struct
 	Verilog::Netlist::Subclass);
 
-$VERSION = '3.220';
+$VERSION = '3.221';
 
 structs('new',
 	'Verilog::Netlist::ContAssign::Struct'

Modified: branches/upstream/libverilog-perl/current/Netlist/File.pm
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/Netlist/File.pm?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/Netlist/File.pm (original)
+++ branches/upstream/libverilog-perl/current/Netlist/File.pm Thu Oct 29 01:54:42 2009
@@ -13,7 +13,7 @@
 @ISA = qw(Verilog::Netlist::File::Struct
 	Verilog::Netlist::Subclass);
 
-$VERSION = '3.220';
+$VERSION = '3.221';
 
 structs('new',
 	'Verilog::Netlist::File::Struct'

Modified: branches/upstream/libverilog-perl/current/Netlist/Interface.pm
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/Netlist/Interface.pm?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/Netlist/Interface.pm (original)
+++ branches/upstream/libverilog-perl/current/Netlist/Interface.pm Thu Oct 29 01:54:42 2009
@@ -14,7 +14,7 @@
 @ISA = qw(Verilog::Netlist::Interface::Struct
 	Verilog::Netlist::Subclass);
 
-$VERSION = '3.220';
+$VERSION = '3.221';
 
 structs('new',
 	'Verilog::Netlist::Interface::Struct'

Modified: branches/upstream/libverilog-perl/current/Netlist/Module.pm
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/Netlist/Module.pm?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/Netlist/Module.pm (original)
+++ branches/upstream/libverilog-perl/current/Netlist/Module.pm Thu Oct 29 01:54:42 2009
@@ -17,7 +17,7 @@
 @ISA = qw(Verilog::Netlist::Module::Struct
 	Verilog::Netlist::Subclass);
 
-$VERSION = '3.220';
+$VERSION = '3.221';
 
 structs('new',
 	'Verilog::Netlist::Module::Struct'

Modified: branches/upstream/libverilog-perl/current/Netlist/Net.pm
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/Netlist/Net.pm?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/Netlist/Net.pm (original)
+++ branches/upstream/libverilog-perl/current/Netlist/Net.pm Thu Oct 29 01:54:42 2009
@@ -12,7 +12,7 @@
 @ISA = qw(Verilog::Netlist::Net::Struct
 	Verilog::Netlist::Subclass);
 
-$VERSION = '3.220';
+$VERSION = '3.221';
 
 my %_Type_Widths = (
     'bit'	=> 1,

Modified: branches/upstream/libverilog-perl/current/Netlist/Pin.pm
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/Netlist/Pin.pm?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/Netlist/Pin.pm (original)
+++ branches/upstream/libverilog-perl/current/Netlist/Pin.pm Thu Oct 29 01:54:42 2009
@@ -17,7 +17,7 @@
 @ISA = qw(Verilog::Netlist::Pin::Struct
 	Verilog::Netlist::Subclass);
 
-$VERSION = '3.220';
+$VERSION = '3.221';
 
 structs('new',
 	'Verilog::Netlist::Pin::Struct'

Modified: branches/upstream/libverilog-perl/current/Netlist/Port.pm
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/Netlist/Port.pm?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/Netlist/Port.pm (original)
+++ branches/upstream/libverilog-perl/current/Netlist/Port.pm Thu Oct 29 01:54:42 2009
@@ -12,7 +12,7 @@
 @ISA = qw(Verilog::Netlist::Port::Struct
 	Verilog::Netlist::Subclass);
 
-$VERSION = '3.220';
+$VERSION = '3.221';
 
 structs('_new_base',
 	'Verilog::Netlist::Port::Struct'

Modified: branches/upstream/libverilog-perl/current/Netlist/Subclass.pm
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/Netlist/Subclass.pm?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/Netlist/Subclass.pm (original)
+++ branches/upstream/libverilog-perl/current/Netlist/Subclass.pm Thu Oct 29 01:54:42 2009
@@ -10,7 +10,7 @@
 use vars qw($VERSION @EXPORT);
 use strict;
 
-$VERSION = '3.220';
+$VERSION = '3.221';
 @EXPORT = qw(structs);
 
 # Maybe in the future.  For now all users of this must do it themselves

Modified: branches/upstream/libverilog-perl/current/Parser/Parser.pm
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/Parser/Parser.pm?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/Parser/Parser.pm (original)
+++ branches/upstream/libverilog-perl/current/Parser/Parser.pm Thu Oct 29 01:54:42 2009
@@ -14,7 +14,7 @@
 use strict;
 use vars qw($VERSION $Debug);
 
-$VERSION = '3.220';
+$VERSION = '3.221';
 
 #$Debug sets the default value for debug.  You're better off with the object method though.
 

Modified: branches/upstream/libverilog-perl/current/Parser/SigParser.pm
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/Parser/SigParser.pm?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/Parser/SigParser.pm (original)
+++ branches/upstream/libverilog-perl/current/Parser/SigParser.pm Thu Oct 29 01:54:42 2009
@@ -14,7 +14,7 @@
 ######################################################################
 #### Configuration Section
 
-$VERSION = '3.220';
+$VERSION = '3.221';
 
 our @_Callback_Names = qw(
   attribute

Modified: branches/upstream/libverilog-perl/current/Parser/VParseLex.l
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/Parser/VParseLex.l?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/Parser/VParseLex.l (original)
+++ branches/upstream/libverilog-perl/current/Parser/VParseLex.l Thu Oct 29 01:54:42 2009
@@ -87,9 +87,11 @@
 %s V95 V01 V05 S05
 %s STRING ATTRMODE
 %s CMTMODE PROTMODE
+%s DUMMY_TO_AVOID_WARNING
 
 space	[ ]
 ws	[ \t\f\r]+
+crnl	[\r]*[\n]
 	/* identifier */
 id	[a-zA-Z_][a-zA-Z0-9_$]*
 	/* escaped identifier */
@@ -102,7 +104,7 @@
   /* Verilog 1995 */
 <V95,V01,V05,S05>{
   {ws}			{ StashPrefix; }	/* otherwise ignore white-space */
-  \n			{ StashPrefix; NEXTLINE(); }		/* Count line numbers */
+  {crnl}		{ StashPrefix; NEXTLINE(); }		/* Count line numbers */
   /*     Keywords */
   "always"		{ FL; VALTEXT; CALLBACK(keywordCb); return yALWAYS; }
   "and"			{ FL; VALTEXT; CALLBACK(keywordCb); return yAND; }
@@ -514,12 +516,13 @@
 
   /************************************************************************/
   /* STRINGS */
-<STRING>\n 		{ yyerrorf("Unterminated string\n"); }
-<STRING>\r		;
-<STRING>[^\"\\]* 	{ yymore(); }
+<STRING><<EOF>>		{ yyerrorf("EOF in unterminated string"); yyleng = 0; yy_pop_state(); }
+<STRING>{crnl}		{ yyerrorf("Unterminated string"); NEXTLINE(); }
+<STRING>\\{crnl} 	{ NEXTLINE(); yymore(); }
 <STRING>\\.	 	{ yymore(); }
 <STRING>\" 		{ yy_pop_state();
 			  FL; VALTEXT; CALLBACK(stringCb); return yaSTRING; }
+<STRING>.	 	{ yymore(); }
 
   /************************************************************************/
   /* Multi-line COMMENTS */
@@ -540,7 +543,7 @@
 
   /************************************************************************/
   /* Attributes */
-<ATTRMODE>\n		{ yymore(); NEXTLINE(); }
+<ATTRMODE>{crnl}	{ yymore(); NEXTLINE(); }
 <ATTRMODE>"*)"		{ FL; VALTEXT; CALLBACK(attributeCb); yy_pop_state(); }
 <ATTRMODE>. 		{ yymore(); }
 <ATTRMODE><<EOF>>	{ yyerrorf("EOF in (*");
@@ -558,7 +561,7 @@
   "`accelerate"			{ FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility
   "`autoexpand_vectornets"	{ FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility
   "`celldefine"			{ FL; VALTEXT; CALLBACK(preprocCb); LEXP->m_inCellDefine=true; }
-  "`default_decay_time"{ws}+[^\n]*	{ FL; VALTEXT; CALLBACK(preprocCb); } // Verilog spec - delays only
+  "`default_decay_time"{ws}+[^\n\r]*	{ FL; VALTEXT; CALLBACK(preprocCb); } // Verilog spec - delays only
   "`default_nettype"{ws}+[a-zA-Z0-9]*	{ FL; VALTEXT; CALLBACK(preprocCb); } // Verilog 2001
   "`delay_mode_distributed"	{ FL; VALTEXT; CALLBACK(preprocCb); } // Verilog spec - delays only
   "`delay_mode_path"		{ FL; VALTEXT; CALLBACK(preprocCb); } // Verilog spec - delays only
@@ -570,7 +573,7 @@
   "`endprotect"			{ FL; VALTEXT; CALLBACK(preprocCb); }
   "`expand_vectornets"		{ FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility
   "`inline"			{ FL; VALTEXT; CALLBACK(preprocCb); }
-  "`line"{ws}+[^\n]*\n		{ LPARSEP->inLineDirective(yytext); FL; VALTEXT; CALLBACK(preprocCb); }
+  "`line"{ws}+[^\n\r]*{crnl}	{ LPARSEP->inLineDirective(yytext); FL; VALTEXT; CALLBACK(preprocCb); }
   "`noaccelerate"		{ FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility
   "`noexpand_vectornets"	{ FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility
   "`noremove_gatenames"		{ FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility
@@ -578,14 +581,14 @@
   "`nosuppress_faults"		{ FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility
   "`nounconnected_drive"	{ FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility
   "`portcoerce"			{ FL; VALTEXT; CALLBACK(preprocCb); }
-  "`pragma"{ws}+[^\n]*\n	{ FL; VALTEXT; CALLBACK(preprocCb); } // Verilog 2005
+  "`pragma"{ws}+[^\n\r]*	{ FL; VALTEXT; CALLBACK(preprocCb); } // Verilog 2005
   "`protect"			{ FL; VALTEXT; CALLBACK(preprocCb); }
   "`protected"			{ FL; VALTEXT; CALLBACK(preprocCb); yy_push_state(PROTMODE); }
   "`remove_gatenames"		{ FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility
   "`remove_netnames"		{ FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility
   "`resetall"			{ FL; VALTEXT; CALLBACK(preprocCb); }
   "`suppress_faults"		{ FL; VALTEXT; CALLBACK(preprocCb); } // Verilog-XL compatibility
-  "`timescale"{ws}+[^\n]*\n	{ FL; VALTEXT; CALLBACK(preprocCb); NEXTLINE(); }
+  "`timescale"{ws}+[^\n\r]*	{ FL; VALTEXT; CALLBACK(preprocCb); }
 
   /* See also setLanguage below */
   "`begin_keywords"[ \t]*\"1364-1995\"		{ yy_push_state(V95); CALLBACK(preprocCb); }

Modified: branches/upstream/libverilog-perl/current/Parser/bisonpre
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/Parser/bisonpre?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/Parser/bisonpre (original)
+++ branches/upstream/libverilog-perl/current/Parser/bisonpre Thu Oct 29 01:54:42 2009
@@ -9,7 +9,7 @@
 use strict;
 use vars qw ($Debug $VERSION);
 
-$VERSION = '3.220';
+$VERSION = '3.221';
 
 our $Self;
 

Modified: branches/upstream/libverilog-perl/current/Parser/callbackgen
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/Parser/callbackgen?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/Parser/callbackgen (original)
+++ branches/upstream/libverilog-perl/current/Parser/callbackgen Thu Oct 29 01:54:42 2009
@@ -9,7 +9,7 @@
 use strict;
 use vars qw ($Debug $VERSION);
 
-$VERSION = '3.220';
+$VERSION = '3.221';
 
 # xs_manual=>1,   -> The .xs file makes the handler itself
 

Modified: branches/upstream/libverilog-perl/current/Preproc/Preproc.pm
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/Preproc/Preproc.pm?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/Preproc/Preproc.pm (original)
+++ branches/upstream/libverilog-perl/current/Preproc/Preproc.pm Thu Oct 29 01:54:42 2009
@@ -11,7 +11,7 @@
 use strict;
 use vars qw($VERSION);
 
-$VERSION = '3.220';
+$VERSION = '3.221';
 
 ######################################################################
 #### Configuration Section

Modified: branches/upstream/libverilog-perl/current/Preproc/VPreproc.cpp
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/Preproc/VPreproc.cpp?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/Preproc/VPreproc.cpp (original)
+++ branches/upstream/libverilog-perl/current/Preproc/VPreproc.cpp Thu Oct 29 01:54:42 2009
@@ -123,7 +123,7 @@
     int getToken();
     void parseTop();
     void parseUndef();
-    string gettext(bool stop_at_eol);
+    string getparseline(bool stop_at_eol);
     bool isEof() const { return (m_lexp==NULL); }
     void open(string filename, VFileLine* filelinep);
     void insertUnreadback(const string& text) { m_lineCmt += text; }
@@ -161,11 +161,11 @@
 }
 string VPreproc::getline() {
     VPreprocImp* idatap = static_cast<VPreprocImp*>(m_opaquep);
-    return idatap->gettext(true);
+    return idatap->getparseline(true);
 }
 string VPreproc::getall() {
     VPreprocImp* idatap = static_cast<VPreprocImp*>(m_opaquep);
-    return idatap->gettext(false);
+    return idatap->getparseline(false);
 }
 void VPreproc::debug(int level) {
     VPreprocImp* idatap = static_cast<VPreprocImp*>(m_opaquep);
@@ -871,7 +871,7 @@
     }
 }
 
-string VPreprocImp::gettext(bool stop_at_eol) {
+string VPreprocImp::getparseline(bool stop_at_eol) {
     // Get a single line from the parse stream.  Buffer unreturned text until the newline.
     if (isEof()) return "";
     while (1) {

Modified: branches/upstream/libverilog-perl/current/Preproc/VPreprocLex.l
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/Preproc/VPreprocLex.l?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/Preproc/VPreprocLex.l (original)
+++ branches/upstream/libverilog-perl/current/Preproc/VPreprocLex.l Thu Oct 29 01:54:42 2009
@@ -113,6 +113,7 @@
 <STRMODE><<EOF>>	{ linenoInc(); yyerrorf("EOF in unterminated string"); yyleng=0; yyterminate(); }
 <STRMODE>{crnl}		{ linenoInc(); yyerrorf("Unterminated string"); BEGIN(INITIAL); }
 <STRMODE>[^\"\\]	{ yymore(); }
+<STRMODE>{backslash}{crnl}	{ linenoInc(); yymore(); }
 <STRMODE>{backslash}.	{ yymore(); }
 <STRMODE>{quote} 	{ yy_pop_state();
 			  if (VPreprocLex::s_currentLexp->m_parenLevel) appendDefValue(yytext,yyleng);

Modified: branches/upstream/libverilog-perl/current/Std.pm
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/Std.pm?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/Std.pm (original)
+++ branches/upstream/libverilog-perl/current/Std.pm Thu Oct 29 01:54:42 2009
@@ -14,7 +14,7 @@
 ######################################################################
 #### Configuration Section
 
-$VERSION = '3.220';
+$VERSION = '3.221';
 
 #######################################################################
 # ACCESSORS

Modified: branches/upstream/libverilog-perl/current/t/34_parser.out
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/t/34_parser.out?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/t/34_parser.out (original)
+++ branches/upstream/libverilog-perl/current/t/34_parser.out Thu Oct 29 01:54:42 2009
@@ -306,9 +306,9 @@
 
 
 '
-verilog/example.v:005: PREPROC '`timescale 1ns/1ns
-'
+verilog/example.v:005: PREPROC '`timescale 1ns/1ns'
 verilog/example.v:007: unreadback '
+
 '
 verilog/example.v:007: KEYWORD 'module'
 verilog/example.v:007: unreadback ' '

Modified: branches/upstream/libverilog-perl/current/t/35_sigparser.out
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/t/35_sigparser.out?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/t/35_sigparser.out (original)
+++ branches/upstream/libverilog-perl/current/t/35_sigparser.out Thu Oct 29 01:54:42 2009
@@ -249,78 +249,80 @@
 verilog/parser_bugs.v:268: MODULE  'module' 'bug16' undef '0'
 verilog/parser_bugs.v:271: ENDMODULE  'endmodule'
 verilog/parser_bugs.v:273: VAR  'parameter' 'bug39' 'netlist' '' '' '' '0'
-verilog/parser_bugs.v:278: MODULE  'module' 'bug64' undef '0'
-verilog/parser_bugs.v:279: VAR  'parameter' 'a' 'module' '' 'integer' '' '1'
-verilog/parser_bugs.v:279: VAR  'parameter' 'b' 'module' '' 'integer' '' '2'
-verilog/parser_bugs.v:280: VAR  'parameter' 'c' 'module' '' 'real' '' '3.0'
-verilog/parser_bugs.v:281: VAR  'parameter' 'd' 'module' '' 'realtime' '' '4.0'
-verilog/parser_bugs.v:282: VAR  'parameter' 'e' 'module' '' 'time' '' '5.0'
-verilog/parser_bugs.v:283: ENDMODULE  'endmodule'
-verilog/parser_bugs.v:285: MODULE  'module' 'bug166' undef '0'
-verilog/parser_bugs.v:286: CONTASSIGN  'assign' '{{o1,o2},o3,o4,{o5,o6}}' '{{i1,i2},i3,i4,{i5,i6}}'
-verilog/parser_bugs.v:287: ENDMODULE  'endmodule'
-verilog/parser_bugs.v:289: MODULE  'module' 'coverage20090318' undef '0'
-verilog/parser_bugs.v:290: TASK  'task' 'atask'
-verilog/parser_bugs.v:292: ENDTASKFUNC  'endtask'
-verilog/parser_bugs.v:293: ENDMODULE  'endmodule'
-verilog/parser_bugs.v:295: MODULE  'module' 'svsig' undef '0'
-verilog/parser_bugs.v:296: FUNCTION  'function' 'count' 'int'
-verilog/parser_bugs.v:296: VAR  'port' 'd' 'function' '' 'logic [3:0]' '' ''
-verilog/parser_bugs.v:296: PORT  'd' 'function' 'input' 'logic [3:0]' '' '1'
-verilog/parser_bugs.v:297: VAR  'var' 'count' 'function' '' 'int' '' 'd[0]+d[1]+d[2]+d[3]'
-verilog/parser_bugs.v:302: ENDTASKFUNC  'endfunction'
-verilog/parser_bugs.v:303: TASK  'task' 'autoconst'
-verilog/parser_bugs.v:304: VAR  'var' 'CONS' 'task' '' 'const int' '' '8'
-verilog/parser_bugs.v:307: ENDTASKFUNC  'endtask'
-verilog/parser_bugs.v:308: ENDMODULE  'endmodule'
-verilog/parser_bugs.v:310: MODULE  'module' 'bug_empty_func_param' undef '0'
-verilog/parser_bugs.v:320: ENDMODULE  'endmodule'
-verilog/parser_bugs.v:322: MODULE  'module' 'dotted_funcs' undef '0'
-verilog/parser_bugs.v:325: ENDMODULE  'endmodule'
-verilog/parser_bugs.v:327: MODULE  'module' 'var_only_in_block' undef '0'
-verilog/parser_bugs.v:329: VAR  'var' 'only_a_var_in_blk' 'module' '' 'integer' '' ''
-verilog/parser_bugs.v:331: ENDMODULE  'endmodule'
-verilog/parser_bugs.v:333: MODULE  'module' 'v2k_vec_no_vec' undef '0'
-verilog/parser_bugs.v:334: VAR  'port' 'VEC' 'module' '' '[2:0]' '' ''
-verilog/parser_bugs.v:334: PORT  'VEC' 'module' 'input' '[2:0]' '' '1'
-verilog/parser_bugs.v:335: VAR  'port' 'VEC2' 'module' '' '[2:0]' '' ''
-verilog/parser_bugs.v:335: PORT  'VEC2' 'module' 'input' '[2:0]' '' '2'
-verilog/parser_bugs.v:336: VAR  'port' 'NOVEC' 'module' '' '' '' ''
-verilog/parser_bugs.v:336: PORT  'NOVEC' 'module' 'input' '' '' '3'
-verilog/parser_bugs.v:337: VAR  'port' 'ARY' 'module' '' '' '[1:0]' ''
-verilog/parser_bugs.v:337: PORT  'ARY' 'module' 'input' '' '[1:0]' '4'
-verilog/parser_bugs.v:338: VAR  'port' 'NOARY2' 'module' '' '' '' ''
-verilog/parser_bugs.v:338: PORT  'NOARY2' 'module' 'input' '' '' '5'
-verilog/parser_bugs.v:339: VAR  'port' 'STILL_IN' 'module' '' 'logic' '' ''
-verilog/parser_bugs.v:339: PORT  'STILL_IN' 'module' 'input' 'logic' '' '6'
-verilog/parser_bugs.v:340: VAR  'port' 'TYPED' 'module' '' 'logic' '' ''
-verilog/parser_bugs.v:340: PORT  'TYPED' 'module' 'input' 'logic' '' '7'
-verilog/parser_bugs.v:342: TASK  'task' 't'
-verilog/parser_bugs.v:342: VAR  'port' 'FVEC' 'task' '' '[2:0]' '' ''
-verilog/parser_bugs.v:342: PORT  'FVEC' 'task' 'input' '[2:0]' '' '1'
-verilog/parser_bugs.v:342: VAR  'port' 'FVEC2' 'task' '' '[2:0]' '' ''
-verilog/parser_bugs.v:342: PORT  'FVEC2' 'task' 'input' '[2:0]' '' '1'
-verilog/parser_bugs.v:343: VAR  'port' 'NOVEC' 'task' '' '' '' ''
-verilog/parser_bugs.v:343: PORT  'NOVEC' 'task' 'input' '' '' '1'
-verilog/parser_bugs.v:345: ENDTASKFUNC  'endtask'
-verilog/parser_bugs.v:346: ENDMODULE  'endmodule'
-verilog/parser_bugs.v:348: MODULE  'module' 'bugfor' undef '0'
-verilog/parser_bugs.v:350: ENDMODULE  'endmodule'
-verilog/parser_bugs.v:352: MODULE  'module' 'bug85' undef '0'
-verilog/parser_bugs.v:352: VAR  'parameter' 'T_DATA' 'module' '' 'type' '' 'byte'
-verilog/parser_bugs.v:353: PORT  'data' 'module' '' '' '' '1'
-verilog/parser_bugs.v:354: VAR  'port' 'data' 'module' '' 'T_DATA' '' ''
-verilog/parser_bugs.v:354: PORT  'data' 'module' 'input' 'T_DATA' '' '0'
-verilog/parser_bugs.v:356: INSTANT  'sub' 'sub' ''
-verilog/parser_bugs.v:355: PARAMPIN  'T_DATA' 'T_DATA' '1'
-verilog/parser_bugs.v:356: PIN  'data' 'data' '1'
-verilog/parser_bugs.v:356: ENDCELL  ''
-verilog/parser_bugs.v:357: ENDMODULE  'endmodule'
-verilog/parser_bugs.v:359: MODULE  'module' 'bugmodportcomma' undef '0'
-verilog/parser_bugs.v:359: PORT  'a' 'module' '' '' '' '1'
-verilog/parser_bugs.v:360: VAR  'port' 'a' 'module' '' '' '' ''
-verilog/parser_bugs.v:360: PORT  'a' 'module' 'input' '' '' '0'
-verilog/parser_bugs.v:361: ENDMODULE  'endmodule'
+verilog/parser_bugs.v:279: MODULE  'module' 'bug64' undef '0'
+verilog/parser_bugs.v:280: VAR  'parameter' 'a' 'module' '' 'integer' '' '1'
+verilog/parser_bugs.v:280: VAR  'parameter' 'b' 'module' '' 'integer' '' '2'
+verilog/parser_bugs.v:281: VAR  'parameter' 'c' 'module' '' 'real' '' '3.0'
+verilog/parser_bugs.v:282: VAR  'parameter' 'd' 'module' '' 'realtime' '' '4.0'
+verilog/parser_bugs.v:283: VAR  'parameter' 'e' 'module' '' 'time' '' '5.0'
+verilog/parser_bugs.v:284: ENDMODULE  'endmodule'
+verilog/parser_bugs.v:286: MODULE  'module' 'bug166' undef '0'
+verilog/parser_bugs.v:287: CONTASSIGN  'assign' '{{o1,o2},o3,o4,{o5,o6}}' '{{i1,i2},i3,i4,{i5,i6}}'
+verilog/parser_bugs.v:288: ENDMODULE  'endmodule'
+verilog/parser_bugs.v:290: MODULE  'module' 'coverage20090318' undef '0'
+verilog/parser_bugs.v:291: TASK  'task' 'atask'
+verilog/parser_bugs.v:293: ENDTASKFUNC  'endtask'
+verilog/parser_bugs.v:294: ENDMODULE  'endmodule'
+verilog/parser_bugs.v:296: MODULE  'module' 'svsig' undef '0'
+verilog/parser_bugs.v:297: FUNCTION  'function' 'count' 'int'
+verilog/parser_bugs.v:297: VAR  'port' 'd' 'function' '' 'logic [3:0]' '' ''
+verilog/parser_bugs.v:297: PORT  'd' 'function' 'input' 'logic [3:0]' '' '1'
+verilog/parser_bugs.v:298: VAR  'var' 'count' 'function' '' 'int' '' 'd[0]+d[1]+d[2]+d[3]'
+verilog/parser_bugs.v:303: ENDTASKFUNC  'endfunction'
+verilog/parser_bugs.v:304: TASK  'task' 'autoconst'
+verilog/parser_bugs.v:305: VAR  'var' 'CONS' 'task' '' 'const int' '' '8'
+verilog/parser_bugs.v:308: ENDTASKFUNC  'endtask'
+verilog/parser_bugs.v:309: ENDMODULE  'endmodule'
+verilog/parser_bugs.v:311: MODULE  'module' 'bug_empty_func_param' undef '0'
+verilog/parser_bugs.v:321: ENDMODULE  'endmodule'
+verilog/parser_bugs.v:323: MODULE  'module' 'dotted_funcs' undef '0'
+verilog/parser_bugs.v:326: ENDMODULE  'endmodule'
+verilog/parser_bugs.v:328: MODULE  'module' 'var_only_in_block' undef '0'
+verilog/parser_bugs.v:330: VAR  'var' 'only_a_var_in_blk' 'module' '' 'integer' '' ''
+verilog/parser_bugs.v:332: ENDMODULE  'endmodule'
+verilog/parser_bugs.v:334: MODULE  'module' 'v2k_vec_no_vec' undef '0'
+verilog/parser_bugs.v:335: VAR  'port' 'VEC' 'module' '' '[2:0]' '' ''
+verilog/parser_bugs.v:335: PORT  'VEC' 'module' 'input' '[2:0]' '' '1'
+verilog/parser_bugs.v:336: VAR  'port' 'VEC2' 'module' '' '[2:0]' '' ''
+verilog/parser_bugs.v:336: PORT  'VEC2' 'module' 'input' '[2:0]' '' '2'
+verilog/parser_bugs.v:337: VAR  'port' 'NOVEC' 'module' '' '' '' ''
+verilog/parser_bugs.v:337: PORT  'NOVEC' 'module' 'input' '' '' '3'
+verilog/parser_bugs.v:338: VAR  'port' 'ARY' 'module' '' '' '[1:0]' ''
+verilog/parser_bugs.v:338: PORT  'ARY' 'module' 'input' '' '[1:0]' '4'
+verilog/parser_bugs.v:339: VAR  'port' 'NOARY2' 'module' '' '' '' ''
+verilog/parser_bugs.v:339: PORT  'NOARY2' 'module' 'input' '' '' '5'
+verilog/parser_bugs.v:340: VAR  'port' 'STILL_IN' 'module' '' 'logic' '' ''
+verilog/parser_bugs.v:340: PORT  'STILL_IN' 'module' 'input' 'logic' '' '6'
+verilog/parser_bugs.v:341: VAR  'port' 'TYPED' 'module' '' 'logic' '' ''
+verilog/parser_bugs.v:341: PORT  'TYPED' 'module' 'input' 'logic' '' '7'
+verilog/parser_bugs.v:343: TASK  'task' 't'
+verilog/parser_bugs.v:343: VAR  'port' 'FVEC' 'task' '' '[2:0]' '' ''
+verilog/parser_bugs.v:343: PORT  'FVEC' 'task' 'input' '[2:0]' '' '1'
+verilog/parser_bugs.v:343: VAR  'port' 'FVEC2' 'task' '' '[2:0]' '' ''
+verilog/parser_bugs.v:343: PORT  'FVEC2' 'task' 'input' '[2:0]' '' '1'
+verilog/parser_bugs.v:344: VAR  'port' 'NOVEC' 'task' '' '' '' ''
+verilog/parser_bugs.v:344: PORT  'NOVEC' 'task' 'input' '' '' '1'
+verilog/parser_bugs.v:346: ENDTASKFUNC  'endtask'
+verilog/parser_bugs.v:347: ENDMODULE  'endmodule'
+verilog/parser_bugs.v:349: MODULE  'module' 'bugfor' undef '0'
+verilog/parser_bugs.v:351: ENDMODULE  'endmodule'
+verilog/parser_bugs.v:353: MODULE  'module' 'bug85' undef '0'
+verilog/parser_bugs.v:353: VAR  'parameter' 'T_DATA' 'module' '' 'type' '' 'byte'
+verilog/parser_bugs.v:354: PORT  'data' 'module' '' '' '' '1'
+verilog/parser_bugs.v:355: VAR  'port' 'data' 'module' '' 'T_DATA' '' ''
+verilog/parser_bugs.v:355: PORT  'data' 'module' 'input' 'T_DATA' '' '0'
+verilog/parser_bugs.v:357: INSTANT  'sub' 'sub' ''
+verilog/parser_bugs.v:356: PARAMPIN  'T_DATA' 'T_DATA' '1'
+verilog/parser_bugs.v:357: PIN  'data' 'data' '1'
+verilog/parser_bugs.v:357: ENDCELL  ''
+verilog/parser_bugs.v:358: ENDMODULE  'endmodule'
+verilog/parser_bugs.v:360: MODULE  'module' 'bugmodportcomma' undef '0'
+verilog/parser_bugs.v:360: PORT  'a' 'module' '' '' '' '1'
+verilog/parser_bugs.v:361: VAR  'port' 'a' 'module' '' '' '' ''
+verilog/parser_bugs.v:361: PORT  'a' 'module' 'input' '' '' '0'
+verilog/parser_bugs.v:362: ENDMODULE  'endmodule'
+verilog/parser_bugs.v:364: MODULE  'module' 'bug168' undef '0'
+verilog/parser_bugs.v:369: ENDMODULE  'endmodule'
 verilog/pinorder.v:006: MODULE  'module' 'pinorder4' undef '0'
 verilog/pinorder.v:007: VAR  'net' 'b_i' 'module' 'wire' '' '' ''
 verilog/pinorder.v:008: VAR  'net' 'd_o' 'module' 'wire' '' '' ''

Modified: branches/upstream/libverilog-perl/current/verilog/parser_bugs.v
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/verilog/parser_bugs.v?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/verilog/parser_bugs.v (original)
+++ branches/upstream/libverilog-perl/current/verilog/parser_bugs.v Thu Oct 29 01:54:42 2009
@@ -360,3 +360,10 @@
 module bugmodportcomma (,a,);
    input a;
 endmodule
+
+module bug168;
+   initial $display("\nWarning!  This is a\
+              string with a line\
+              continuation\
+              at time %0d PS", $time);
+endmodule

Modified: branches/upstream/libverilog-perl/current/vhier
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/vhier?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/vhier (original)
+++ branches/upstream/libverilog-perl/current/vhier Thu Oct 29 01:54:42 2009
@@ -16,7 +16,7 @@
 use strict;
 use vars qw ($Debug $VERSION);
 
-$VERSION = '3.220';
+$VERSION = '3.221';
 
 ######################################################################
 # main

Modified: branches/upstream/libverilog-perl/current/vpassert
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/vpassert?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/vpassert (original)
+++ branches/upstream/libverilog-perl/current/vpassert Thu Oct 29 01:54:42 2009
@@ -33,7 +33,7 @@
 	     %File_Mtime %File_Mtime_Read %File_Mtime_Read_Used
 	     %File_Dest
 	     );
-$VERSION = '3.220';
+$VERSION = '3.221';
 
 ######################################################################
 # configuration

Modified: branches/upstream/libverilog-perl/current/vppreproc
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/vppreproc?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/vppreproc (original)
+++ branches/upstream/libverilog-perl/current/vppreproc Thu Oct 29 01:54:42 2009
@@ -16,7 +16,7 @@
 use strict;
 use vars qw ($Debug $VERSION);
 
-$VERSION = '3.220';
+$VERSION = '3.221';
 
 ######################################################################
 # main

Modified: branches/upstream/libverilog-perl/current/vrename
URL: http://svn.debian.org/wsvn/pkg-perl/branches/upstream/libverilog-perl/current/vrename?rev=46490&op=diff
==============================================================================
--- branches/upstream/libverilog-perl/current/vrename (original)
+++ branches/upstream/libverilog-perl/current/vrename Thu Oct 29 01:54:42 2009
@@ -23,7 +23,7 @@
 	     $Debug $Opt_Xref $Opt_Crypt $Opt_Crypt_All $Opt_Write $Opt_Keywords
 	     @Files);
 
-$VERSION = '3.220';
+$VERSION = '3.221';
 
 ######################################################################
 




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