r51388 - in /trunk/libverilog-perl/debian: changelog control

[jawnsy-guest at users.alioth.debian.org]

Author: jawnsy-guest
Date: Sun Jan 24 04:24:50 2010
New Revision: 51388

URL: http://svn.debian.org/wsvn/pkg-perl/?sc=1&rev=51388
Log:
* Update copyright information to new DEP5 format
* Rewrite control description
* Update years of copyright

Modified:
    trunk/libverilog-perl/debian/changelog
    trunk/libverilog-perl/debian/control

Modified: trunk/libverilog-perl/debian/changelog
URL: http://svn.debian.org/wsvn/pkg-perl/trunk/libverilog-perl/debian/changelog?rev=51388&op=diff
==============================================================================
--- trunk/libverilog-perl/debian/changelog (original)
+++ trunk/libverilog-perl/debian/changelog Sun Jan 24 04:24:50 2010
@@ -1,8 +1,11 @@
 libverilog-perl (3.230-1) UNRELEASED; urgency=low
 
   * New upstream release
+  * Update copyright information to new DEP5 format
+  * Rewrite control description
+  * Update years of copyright
 
- -- Jonathan Yu <jawnsy at cpan.org>  Fri, 22 Jan 2010 13:12:55 -0500
+ -- Jonathan Yu <jawnsy at cpan.org>  Sat, 23 Jan 2010 23:33:07 -0500
 
 libverilog-perl (3.223-1) unstable; urgency=low
 

Modified: trunk/libverilog-perl/debian/control
URL: http://svn.debian.org/wsvn/pkg-perl/trunk/libverilog-perl/debian/control?rev=51388&op=diff
==============================================================================
--- trunk/libverilog-perl/debian/control (original)
+++ trunk/libverilog-perl/debian/control Sun Jan 24 04:24:50 2010
@@ -1,10 +1,11 @@
 Source: libverilog-perl
 Section: perl
 Priority: optional
+Build-Depends: debhelper (>= 7.0.50~), perl, flex, bison, libtest-pod-perl,
+ libbit-vector-perl
 Maintainer: Debian Perl Group <pkg-perl-maintainers at lists.alioth.debian.org>
 Uploaders: أحÙ
د الÙ
Ø­Ù
ودي (Ahmed El-Mahmoudy) <aelmahmoudy at users.sourceforge.net>,
  Nathan Handler <nhandler at ubuntu.com>, Jonathan Yu <jawnsy at cpan.org>
-Build-Depends: debhelper (>= 7.0.50~), perl, flex, bison, libtest-pod-perl, libbit-vector-perl
 Standards-Version: 3.8.3
 Homepage: http://search.cpan.org/dist/Verilog-Perl/
 Vcs-Svn: svn://svn.debian.org/pkg-perl/trunk/libverilog-perl/
@@ -13,24 +14,23 @@
 Package: libverilog-perl
 Architecture: any
 Depends: ${perl:Depends}, ${shlibs:Depends}, ${misc:Depends}
-Description: building point for Verilog support in the Perl language
- The Verilog-Perl library is a building point for Verilog support in the Perl
- language. It includes:
-  * Verilog::Getopt which parses command line options similar to C++ and VCS.
-  * Verilog::Language which knows the language keywords and parses numbers.
-  * Verilog::Netlist which builds netlists out of Verilog files. This allows
+Description: framework providing Verilog support
+ Verilog is a Perl framework providing Verilog support in the Perl language.
+ It includes:
+ .
+  * Verilog::Getopt, which parses command line options similar to C++ and VCS
+  * Verilog::Language, which knows the language keywords and parses numbers.
+  * Verilog::Netlist, which builds netlists out of Verilog files. This allows
     easy scripts to determine things such as the hierarchy of modules.
-  * Verilog::Parser invokes callbacks for language tokens.
-  * Verilog::Preproc preprocesses the language, and allows reading
+  * Verilog::Parser, which invokes callbacks for language tokens
+  * Verilog::Preproc, preprocesses the language, and allows reading
     post-processed files right from Perl without temporary files.
-  * vpassert inserts PLIish warnings and assertions for any simulator.
+ .
+ It also includes a variety of useful utilities:
+ .
+  * vpassert inserts PLIish warnings and assertions for any simulator
   * vppreproc preprocesses the complete Verilog 2001 and SystemVerilog
-    language.
-  * vrename renames and cross-references Verilog symbols. Vrename
-    creates Verilog cross references and makes it easy to rename
-    signal and module names across multiple files. Vrename uses a
-    simple and efficient three step process. First, you run vrename to
-    create a list of signals in the design. You then edit this list,
-    changing as many symbols as you wish. Vrename is then run a second
-    time to apply the changes.
-  .
+    language
+  * vrename renames and cross-references Verilog symbols. It creates Verilog
+    cross references and makes it easy to rename signal and module names over
+    multiple files.