[SCM] WebKit Debian packaging branch, webkit-1.2, updated. upstream/1.1.90-6072-g9a69373
zoltan at webkit.org
zoltan at webkit.org
Wed Apr 7 23:41:10 UTC 2010
The following commit has been merged in the webkit-1.2 branch:
commit 1916f847efc6144c9308c804f86b388fca57d01b
Author: zoltan at webkit.org <zoltan at webkit.org@268f45cc-cd09-0410-ab3c-d52691b4dbfc>
Date: Sat Nov 14 00:44:42 2009 +0000
https://bugs.webkit.org/show_bug.cgi?id=31050
Patch by Zoltan Herczeg <zherczeg at inf.u-szeged.hu> on 2009-11-14
Reviewed by Gavin Barraclough.
Adding JSVALUE32_64 support for ARM (but not turning it
on by default). All optimizations must be disabled, since
this patch is only the first of a series of patches.
During the work, a lot of x86 specific code revealed and
made platform independent.
See revisions: 50531 50541 50593 50594 50595
* assembler/ARMAssembler.h:
(JSC::ARMAssembler::):
(JSC::ARMAssembler::fdivd_r):
* assembler/MacroAssemblerARM.h:
(JSC::MacroAssemblerARM::lshift32):
(JSC::MacroAssemblerARM::neg32):
(JSC::MacroAssemblerARM::rshift32):
(JSC::MacroAssemblerARM::branchOr32):
(JSC::MacroAssemblerARM::set8):
(JSC::MacroAssemblerARM::setTest8):
(JSC::MacroAssemblerARM::loadDouble):
(JSC::MacroAssemblerARM::divDouble):
(JSC::MacroAssemblerARM::convertInt32ToDouble):
(JSC::MacroAssemblerARM::zeroDouble):
* jit/JIT.cpp:
* jit/JIT.h:
* jit/JITOpcodes.cpp:
(JSC::JIT::privateCompileCTIMachineTrampolines):
* jit/JITStubs.cpp:
* wtf/StdLibExtras.h:
git-svn-id: http://svn.webkit.org/repository/webkit/trunk@50981 268f45cc-cd09-0410-ab3c-d52691b4dbfc
diff --git a/JavaScriptCore/ChangeLog b/JavaScriptCore/ChangeLog
index 245ff29..b13e250 100644
--- a/JavaScriptCore/ChangeLog
+++ b/JavaScriptCore/ChangeLog
@@ -1,3 +1,38 @@
+2009-11-14 Zoltan Herczeg <zherczeg at inf.u-szeged.hu>
+
+ Reviewed by Gavin Barraclough.
+
+ https://bugs.webkit.org/show_bug.cgi?id=31050
+
+ Adding JSVALUE32_64 support for ARM (but not turning it
+ on by default). All optimizations must be disabled, since
+ this patch is only the first of a series of patches.
+
+ During the work, a lot of x86 specific code revealed and
+ made platform independent.
+ See revisions: 50531 50541 50593 50594 50595
+
+ * assembler/ARMAssembler.h:
+ (JSC::ARMAssembler::):
+ (JSC::ARMAssembler::fdivd_r):
+ * assembler/MacroAssemblerARM.h:
+ (JSC::MacroAssemblerARM::lshift32):
+ (JSC::MacroAssemblerARM::neg32):
+ (JSC::MacroAssemblerARM::rshift32):
+ (JSC::MacroAssemblerARM::branchOr32):
+ (JSC::MacroAssemblerARM::set8):
+ (JSC::MacroAssemblerARM::setTest8):
+ (JSC::MacroAssemblerARM::loadDouble):
+ (JSC::MacroAssemblerARM::divDouble):
+ (JSC::MacroAssemblerARM::convertInt32ToDouble):
+ (JSC::MacroAssemblerARM::zeroDouble):
+ * jit/JIT.cpp:
+ * jit/JIT.h:
+ * jit/JITOpcodes.cpp:
+ (JSC::JIT::privateCompileCTIMachineTrampolines):
+ * jit/JITStubs.cpp:
+ * wtf/StdLibExtras.h:
+
2009-11-13 Dominik Röttsches <dominik.roettsches at access-company.com>
Reviewed by Eric Seidel.
diff --git a/JavaScriptCore/assembler/ARMAssembler.h b/JavaScriptCore/assembler/ARMAssembler.h
index 6a86734..500d743 100644
--- a/JavaScriptCore/assembler/ARMAssembler.h
+++ b/JavaScriptCore/assembler/ARMAssembler.h
@@ -121,6 +121,7 @@ namespace JSC {
MUL = 0x00000090,
MULL = 0x00c00090,
FADDD = 0x0e300b00,
+ FDIVD = 0x0e800b00,
FSUBD = 0x0e300b40,
FMULD = 0x0e200b00,
FCMPD = 0x0eb40b40,
@@ -400,6 +401,11 @@ namespace JSC {
emitInst(static_cast<ARMWord>(cc) | FADDD, dd, dn, dm);
}
+ void fdivd_r(int dd, int dn, int dm, Condition cc = AL)
+ {
+ emitInst(static_cast<ARMWord>(cc) | FDIVD, dd, dn, dm);
+ }
+
void fsubd_r(int dd, int dn, int dm, Condition cc = AL)
{
emitInst(static_cast<ARMWord>(cc) | FSUBD, dd, dn, dm);
diff --git a/JavaScriptCore/assembler/MacroAssemblerARM.h b/JavaScriptCore/assembler/MacroAssemblerARM.h
index 4d13b0f..ed16db5 100644
--- a/JavaScriptCore/assembler/MacroAssemblerARM.h
+++ b/JavaScriptCore/assembler/MacroAssemblerARM.h
@@ -120,9 +120,9 @@ public:
void lshift32(RegisterID shift_amount, RegisterID dest)
{
- ARMWord w = m_assembler.getImm(0x1f, ARMRegisters::S0, true);
- ASSERT(!(w & ARMAssembler::OP2_INV_IMM));
- m_assembler.ands_r(ARMRegisters::S0, shift_amount, w);
+ ARMWord w = ARMAssembler::getOp2(0x1f);
+ ASSERT(w != ARMAssembler::INVALID_IMM);
+ m_assembler.and_r(ARMRegisters::S0, shift_amount, w);
m_assembler.movs_r(dest, m_assembler.lsl_r(dest, ARMRegisters::S0));
}
@@ -147,6 +147,11 @@ public:
m_assembler.muls_r(dest, src, ARMRegisters::S0);
}
+ void neg32(RegisterID srcDest)
+ {
+ m_assembler.rsbs_r(srcDest, srcDest, ARMAssembler::getOp2(0));
+ }
+
void not32(RegisterID dest)
{
m_assembler.mvns_r(dest, dest);
@@ -164,9 +169,9 @@ public:
void rshift32(RegisterID shift_amount, RegisterID dest)
{
- ARMWord w = m_assembler.getImm(0x1f, ARMRegisters::S0, true);
- ASSERT(!(w & ARMAssembler::OP2_INV_IMM));
- m_assembler.ands_r(ARMRegisters::S0, shift_amount, w);
+ ARMWord w = ARMAssembler::getOp2(0x1f);
+ ASSERT(w != ARMAssembler::INVALID_IMM);
+ m_assembler.and_r(ARMRegisters::S0, shift_amount, w);
m_assembler.movs_r(dest, m_assembler.asr_r(dest, ARMRegisters::S0));
}
@@ -525,6 +530,13 @@ public:
return Jump(m_assembler.jmp(ARMCondition(cond)));
}
+ Jump branchOr32(Condition cond, RegisterID src, RegisterID dest)
+ {
+ ASSERT((cond == Signed) || (cond == Zero) || (cond == NonZero));
+ or32(src, dest);
+ return Jump(m_assembler.jmp(ARMCondition(cond)));
+ }
+
void breakpoint()
{
m_assembler.bkpt(0);
@@ -568,6 +580,25 @@ public:
m_assembler.mov_r(dest, ARMAssembler::getOp2(1), ARMCondition(cond));
}
+ void set8(Condition cond, RegisterID left, RegisterID right, RegisterID dest)
+ {
+ // ARM doesn't have byte registers
+ set32(cond, left, right, dest);
+ }
+
+ void set8(Condition cond, Address left, RegisterID right, RegisterID dest)
+ {
+ // ARM doesn't have byte registers
+ load32(left, ARMRegisters::S1);
+ set32(cond, ARMRegisters::S1, right, dest);
+ }
+
+ void set8(Condition cond, RegisterID left, Imm32 right, RegisterID dest)
+ {
+ // ARM doesn't have byte registers
+ set32(cond, left, right, dest);
+ }
+
void setTest32(Condition cond, Address address, Imm32 mask, RegisterID dest)
{
load32(address, ARMRegisters::S1);
@@ -579,6 +610,12 @@ public:
m_assembler.mov_r(dest, ARMAssembler::getOp2(1), ARMCondition(cond));
}
+ void setTest8(Condition cond, Address address, Imm32 mask, RegisterID dest)
+ {
+ // ARM doesn't have byte registers
+ setTest32(cond, address, mask, dest);
+ }
+
void add32(Imm32 imm, RegisterID src, RegisterID dest)
{
m_assembler.add_r(dest, src, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
@@ -686,6 +723,12 @@ public:
m_assembler.doubleTransfer(true, dest, address.base, address.offset);
}
+ void loadDouble(void* address, FPRegisterID dest)
+ {
+ m_assembler.ldr_un_imm(ARMRegisters::S0, (ARMWord)address);
+ m_assembler.fdtr_u(true, dest, ARMRegisters::S0, 0);
+ }
+
void storeDouble(FPRegisterID src, ImplicitAddress address)
{
m_assembler.doubleTransfer(false, src, address.base, address.offset);
@@ -702,6 +745,18 @@ public:
addDouble(ARMRegisters::SD0, dest);
}
+ void divDouble(FPRegisterID src, FPRegisterID dest)
+ {
+ m_assembler.fdivd_r(dest, dest, src);
+ }
+
+ void divDouble(Address src, FPRegisterID dest)
+ {
+ ASSERT_NOT_REACHED(); // Untested
+ loadDouble(src, ARMRegisters::SD0);
+ divDouble(ARMRegisters::SD0, dest);
+ }
+
void subDouble(FPRegisterID src, FPRegisterID dest)
{
m_assembler.fsubd_r(dest, dest, src);
@@ -730,6 +785,23 @@ public:
m_assembler.fsitod_r(dest, dest);
}
+ void convertInt32ToDouble(Address src, FPRegisterID dest)
+ {
+ ASSERT_NOT_REACHED(); // Untested
+ // flds does not worth the effort here
+ load32(src, ARMRegisters::S1);
+ convertInt32ToDouble(ARMRegisters::S1, dest);
+ }
+
+ void convertInt32ToDouble(AbsoluteAddress src, FPRegisterID dest)
+ {
+ ASSERT_NOT_REACHED(); // Untested
+ // flds does not worth the effort here
+ m_assembler.ldr_un_imm(ARMRegisters::S1, (ARMWord)src.m_ptr);
+ m_assembler.dtr_u(true, ARMRegisters::S1, ARMRegisters::S1, 0);
+ convertInt32ToDouble(ARMRegisters::S1, dest);
+ }
+
Jump branchDouble(DoubleCondition cond, FPRegisterID left, FPRegisterID right)
{
m_assembler.fcmpd_r(left, right);
@@ -768,6 +840,12 @@ public:
failureCases.append(branchTest32(Zero, dest));
}
+ void zeroDouble(FPRegisterID srcDest)
+ {
+ m_assembler.mov_r(ARMRegisters::S0, ARMAssembler::getOp2(0));
+ convertInt32ToDouble(ARMRegisters::S0, srcDest);
+ }
+
protected:
ARMAssembler::Condition ARMCondition(Condition cond)
{
diff --git a/JavaScriptCore/jit/JIT.cpp b/JavaScriptCore/jit/JIT.cpp
index 000e4b8..c0d1258 100644
--- a/JavaScriptCore/jit/JIT.cpp
+++ b/JavaScriptCore/jit/JIT.cpp
@@ -37,7 +37,6 @@ JSC::MacroAssemblerX86Common::SSE2CheckState JSC::MacroAssemblerX86Common::s_sse
#include "CodeBlock.h"
#include "Interpreter.h"
#include "JITInlineMethods.h"
-#include "JITStubs.h"
#include "JITStubCall.h"
#include "JSArray.h"
#include "JSFunction.h"
diff --git a/JavaScriptCore/jit/JIT.h b/JavaScriptCore/jit/JIT.h
index e19ea17..ea64605 100644
--- a/JavaScriptCore/jit/JIT.h
+++ b/JavaScriptCore/jit/JIT.h
@@ -465,6 +465,8 @@ namespace JSC {
static const int patchOffsetMethodCheckProtoObj = 11;
static const int patchOffsetMethodCheckProtoStruct = 18;
static const int patchOffsetMethodCheckPutFunction = 29;
+#elif PLATFORM(ARM_TRADITIONAL)
+// patchOffset... values should go here; JIT optimizations currently not supported on ARM with JSVALUE32_64.
#else
#error "JSVALUE32_64 not supported on this platform."
#endif
diff --git a/JavaScriptCore/jit/JITOpcodes.cpp b/JavaScriptCore/jit/JITOpcodes.cpp
index d403e35..87e845e 100644
--- a/JavaScriptCore/jit/JITOpcodes.cpp
+++ b/JavaScriptCore/jit/JITOpcodes.cpp
@@ -138,7 +138,7 @@ void JIT::privateCompileCTIMachineTrampolines(RefPtr<ExecutablePool>* executable
loadPtr(Address(regT2, OBJECT_OFFSETOF(FunctionExecutable, m_jitCode)), regT0);
jump(regT0);
-#if PLATFORM(X86)
+#if PLATFORM(X86) || PLATFORM(ARM_TRADITIONAL)
Label nativeCallThunk = align();
preserveReturnAddressAfterCall(regT0);
emitPutToCallFrameHeader(regT0, RegisterFile::ReturnPC); // Push return address
@@ -149,6 +149,7 @@ void JIT::privateCompileCTIMachineTrampolines(RefPtr<ExecutablePool>* executable
emitGetFromCallFrameHeaderPtr(RegisterFile::ScopeChain, regT1, regT1);
emitPutToCallFrameHeader(regT1, RegisterFile::ScopeChain);
+#if PLATFORM(X86)
emitGetFromCallFrameHeader32(RegisterFile::ArgumentCount, regT0);
/* We have two structs that we use to describe the stackframe we set up for our
@@ -248,6 +249,66 @@ void JIT::privateCompileCTIMachineTrampolines(RefPtr<ExecutablePool>* executable
// so pull them off now
addPtr(Imm32(NativeCallFrameSize - sizeof(NativeFunctionCalleeSignature)), stackPointerRegister);
+#elif PLATFORM(ARM_TRADITIONAL)
+ emitGetFromCallFrameHeader32(RegisterFile::ArgumentCount, regT0);
+
+ // Allocate stack space for our arglist
+ COMPILE_ASSERT((sizeof(ArgList) & 0x7) == 0 && sizeof(JSValue) == 8 && sizeof(Register) == 8, ArgList_should_by_8byte_aligned);
+ subPtr(Imm32(sizeof(ArgList)), stackPointerRegister);
+
+ // Set up arguments
+ subPtr(Imm32(1), regT0); // Don't include 'this' in argcount
+
+ // Push argcount
+ storePtr(regT0, Address(stackPointerRegister, OBJECT_OFFSETOF(ArgList, m_argCount)));
+
+ // Calculate the start of the callframe header, and store in regT1
+ move(callFrameRegister, regT1);
+ sub32(Imm32(RegisterFile::CallFrameHeaderSize * (int32_t)sizeof(Register)), regT1);
+
+ // Calculate start of arguments as callframe header - sizeof(Register) * argcount (regT1)
+ mul32(Imm32(sizeof(Register)), regT0, regT0);
+ subPtr(regT0, regT1);
+
+ // push pointer to arguments
+ storePtr(regT1, Address(stackPointerRegister, OBJECT_OFFSETOF(ArgList, m_args)));
+
+ // Argument passing method:
+ // r0 - points to return value
+ // r1 - callFrame
+ // r2 - callee
+ // stack: this(JSValue) and a pointer to ArgList
+
+ move(stackPointerRegister, regT3);
+ subPtr(Imm32(8), stackPointerRegister);
+ move(stackPointerRegister, regT0);
+ subPtr(Imm32(8 + 4 + 4 /* padding */), stackPointerRegister);
+
+ // Setup arg4:
+ storePtr(regT3, Address(stackPointerRegister, 8));
+
+ // Setup arg3
+ // regT1 currently points to the first argument, regT1-sizeof(Register) points to 'this'
+ load32(Address(regT1, -(int32_t)sizeof(void*) * 2), regT3);
+ storePtr(regT3, Address(stackPointerRegister, 0));
+ load32(Address(regT1, -(int32_t)sizeof(void*)), regT3);
+ storePtr(regT3, Address(stackPointerRegister, 4));
+
+ // Setup arg2:
+ emitGetFromCallFrameHeaderPtr(RegisterFile::Callee, regT2);
+
+ // Setup arg1:
+ move(callFrameRegister, regT1);
+
+ call(Address(regT2, OBJECT_OFFSETOF(JSFunction, m_data)));
+
+ // Load return value
+ load32(Address(stackPointerRegister, 16), regT0);
+ load32(Address(stackPointerRegister, 20), regT1);
+
+ addPtr(Imm32(sizeof(ArgList) + 16 + 8), stackPointerRegister);
+#endif
+
// Check for an exception
move(ImmPtr(&globalData->exception), regT2);
Jump sawException = branch32(NotEqual, tagFor(0, regT2), Imm32(JSValue::EmptyValueTag));
diff --git a/JavaScriptCore/jit/JITStubs.cpp b/JavaScriptCore/jit/JITStubs.cpp
index fd9464b..cf9aae0 100644
--- a/JavaScriptCore/jit/JITStubs.cpp
+++ b/JavaScriptCore/jit/JITStubs.cpp
@@ -56,6 +56,7 @@
#include "RegExpPrototype.h"
#include "Register.h"
#include "SamplingTool.h"
+#include <wtf/StdLibExtras.h>
#include <stdarg.h>
#include <stdio.h>
@@ -270,6 +271,40 @@ SYMBOL_STRING(ctiOpThrowNotCaught) ":" "\n"
"bx lr" "\n"
);
+#elif COMPILER(GCC) && PLATFORM(ARM_TRADITIONAL)
+
+asm volatile (
+".globl " SYMBOL_STRING(ctiTrampoline) "\n"
+SYMBOL_STRING(ctiTrampoline) ":" "\n"
+ "stmdb sp!, {r1-r3}" "\n"
+ "stmdb sp!, {r4-r8, lr}" "\n"
+ "sub sp, sp, #68" "\n"
+ "mov r4, r2" "\n"
+ "mov r5, #512" "\n"
+ // r0 contains the code
+ "mov lr, pc" "\n"
+ "mov pc, r0" "\n"
+ "add sp, sp, #68" "\n"
+ "ldmia sp!, {r4-r8, lr}" "\n"
+ "add sp, sp, #12" "\n"
+ "mov pc, lr" "\n"
+);
+
+asm volatile (
+".globl " SYMBOL_STRING(ctiVMThrowTrampoline) "\n"
+SYMBOL_STRING(ctiVMThrowTrampoline) ":" "\n"
+ "mov r0, sp" "\n"
+ "bl " SYMBOL_STRING(cti_vm_throw) "\n"
+
+// Both has the same return sequence
+".globl " SYMBOL_STRING(ctiOpThrowNotCaught) "\n"
+SYMBOL_STRING(ctiOpThrowNotCaught) ":" "\n"
+ "add sp, sp, #68" "\n"
+ "ldmia sp!, {r4-r8, lr}" "\n"
+ "add sp, sp, #12" "\n"
+ "mov pc, lr" "\n"
+);
+
#elif COMPILER(MSVC)
#if USE(JIT_STUB_ARGUMENT_VA_LIST)
@@ -906,6 +941,14 @@ static NEVER_INLINE void throwStackOverflowError(CallFrame* callFrame, JSGlobalD
#elif PLATFORM(ARM_TRADITIONAL) && COMPILER(GCC)
+#if USE(JSVALUE32_64)
+#define THUNK_RETURN_ADDRESS_OFFSET 64
+#else
+#define THUNK_RETURN_ADDRESS_OFFSET 32
+#endif
+
+COMPILE_ASSERT(offsetof(struct JITStackFrame, thunkReturnAddress) == THUNK_RETURN_ADDRESS_OFFSET, JITStackFrame_thunkReturnAddress_offset_mismatch);
+
#define DEFINE_STUB_FUNCTION(rtype, op) \
extern "C" { \
rtype JITStubThunked_##op(STUB_ARGS_DECLARATION); \
@@ -913,9 +956,9 @@ static NEVER_INLINE void throwStackOverflowError(CallFrame* callFrame, JSGlobalD
asm volatile ( \
".globl " SYMBOL_STRING(cti_##op) "\n" \
SYMBOL_STRING(cti_##op) ":" "\n" \
- "str lr, [sp, #32]" "\n" \
+ "str lr, [sp, #" STRINGIZE_VALUE_OF(THUNK_RETURN_ADDRESS_OFFSET) "]" "\n" \
"bl " SYMBOL_STRING(JITStubThunked_##op) "\n" \
- "ldr lr, [sp, #32]" "\n" \
+ "ldr lr, [sp, #" STRINGIZE_VALUE_OF(THUNK_RETURN_ADDRESS_OFFSET) "]" "\n" \
"mov pc, lr" "\n" \
); \
rtype JITStubThunked_##op(STUB_ARGS_DECLARATION)
diff --git a/JavaScriptCore/wtf/StdLibExtras.h b/JavaScriptCore/wtf/StdLibExtras.h
index c9b5742..dd90c85 100644
--- a/JavaScriptCore/wtf/StdLibExtras.h
+++ b/JavaScriptCore/wtf/StdLibExtras.h
@@ -48,6 +48,10 @@
// NULL can cause compiler problems, especially in cases of multiple inheritance.
#define OBJECT_OFFSETOF(class, field) (reinterpret_cast<ptrdiff_t>(&(reinterpret_cast<class*>(0x4000)->field)) - 0x4000)
+// STRINGIZE: Can convert any value to quoted string, even expandable macros
+#define STRINGIZE(exp) #exp
+#define STRINGIZE_VALUE_OF(exp) STRINGIZE(exp)
+
namespace WTF {
/*
--
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