[SCM] WebKit Debian packaging branch, debian/experimental, updated. upstream/1.3.3-9427-gc2be6fc
zherczeg at webkit.org
zherczeg at webkit.org
Wed Dec 22 12:03:30 UTC 2010
The following commit has been merged in the debian/experimental branch:
commit b69941453078f47827f7eb70e2c7df3ebe3a59ab
Author: zherczeg at webkit.org <zherczeg at webkit.org@268f45cc-cd09-0410-ab3c-d52691b4dbfc>
Date: Fri Aug 13 06:49:16 2010 +0000
Refactoring the fpu code generator for the ARM port
https://bugs.webkit.org/show_bug.cgi?id=43842
Reviewed by Gavin Barraclough.
Support up to 32 double precision registers, and the
recent VFP instruction formats. This patch is mainly
a style change which keeps the current functionality.
* assembler/ARMAssembler.h:
(JSC::ARMRegisters::):
(JSC::ARMAssembler::):
(JSC::ARMAssembler::emitInst):
(JSC::ARMAssembler::emitDoublePrecisionInst):
(JSC::ARMAssembler::emitSinglePrecisionInst):
(JSC::ARMAssembler::vadd_f64_r):
(JSC::ARMAssembler::vdiv_f64_r):
(JSC::ARMAssembler::vsub_f64_r):
(JSC::ARMAssembler::vmul_f64_r):
(JSC::ARMAssembler::vcmp_f64_r):
(JSC::ARMAssembler::vsqrt_f64_r):
(JSC::ARMAssembler::vmov_vfp_r):
(JSC::ARMAssembler::vmov_arm_r):
(JSC::ARMAssembler::vcvt_f64_s32_r):
(JSC::ARMAssembler::vcvt_s32_f64_r):
(JSC::ARMAssembler::vmrs_apsr):
* assembler/MacroAssemblerARM.h:
(JSC::MacroAssemblerARM::addDouble):
(JSC::MacroAssemblerARM::divDouble):
(JSC::MacroAssemblerARM::subDouble):
(JSC::MacroAssemblerARM::mulDouble):
(JSC::MacroAssemblerARM::sqrtDouble):
(JSC::MacroAssemblerARM::convertInt32ToDouble):
(JSC::MacroAssemblerARM::branchDouble):
(JSC::MacroAssemblerARM::branchConvertDoubleToInt32):
git-svn-id: http://svn.webkit.org/repository/webkit/trunk@65303 268f45cc-cd09-0410-ab3c-d52691b4dbfc
diff --git a/JavaScriptCore/ChangeLog b/JavaScriptCore/ChangeLog
index 2eb4178..fcce543 100644
--- a/JavaScriptCore/ChangeLog
+++ b/JavaScriptCore/ChangeLog
@@ -1,3 +1,41 @@
+2010-08-12 Zoltan Herczeg <zherczeg at webkit.org>
+
+ Reviewed by Gavin Barraclough.
+
+ Refactoring the fpu code generator for the ARM port
+ https://bugs.webkit.org/show_bug.cgi?id=43842
+
+ Support up to 32 double precision registers, and the
+ recent VFP instruction formats. This patch is mainly
+ a style change which keeps the current functionality.
+
+ * assembler/ARMAssembler.h:
+ (JSC::ARMRegisters::):
+ (JSC::ARMAssembler::):
+ (JSC::ARMAssembler::emitInst):
+ (JSC::ARMAssembler::emitDoublePrecisionInst):
+ (JSC::ARMAssembler::emitSinglePrecisionInst):
+ (JSC::ARMAssembler::vadd_f64_r):
+ (JSC::ARMAssembler::vdiv_f64_r):
+ (JSC::ARMAssembler::vsub_f64_r):
+ (JSC::ARMAssembler::vmul_f64_r):
+ (JSC::ARMAssembler::vcmp_f64_r):
+ (JSC::ARMAssembler::vsqrt_f64_r):
+ (JSC::ARMAssembler::vmov_vfp_r):
+ (JSC::ARMAssembler::vmov_arm_r):
+ (JSC::ARMAssembler::vcvt_f64_s32_r):
+ (JSC::ARMAssembler::vcvt_s32_f64_r):
+ (JSC::ARMAssembler::vmrs_apsr):
+ * assembler/MacroAssemblerARM.h:
+ (JSC::MacroAssemblerARM::addDouble):
+ (JSC::MacroAssemblerARM::divDouble):
+ (JSC::MacroAssemblerARM::subDouble):
+ (JSC::MacroAssemblerARM::mulDouble):
+ (JSC::MacroAssemblerARM::sqrtDouble):
+ (JSC::MacroAssemblerARM::convertInt32ToDouble):
+ (JSC::MacroAssemblerARM::branchDouble):
+ (JSC::MacroAssemblerARM::branchConvertDoubleToInt32):
+
2010-08-12 Sheriff Bot <webkit.review.bot at gmail.com>
Unreviewed, rolling out r65295.
diff --git a/JavaScriptCore/assembler/ARMAssembler.h b/JavaScriptCore/assembler/ARMAssembler.h
index a19864a..da128e7 100644
--- a/JavaScriptCore/assembler/ARMAssembler.h
+++ b/JavaScriptCore/assembler/ARMAssembler.h
@@ -40,32 +40,54 @@ namespace JSC {
r0 = 0,
r1,
r2,
- r3,
- S0 = r3,
+ r3, S0 = r3,
r4,
r5,
r6,
r7,
- r8,
- S1 = r8,
+ r8, S1 = r8,
r9,
r10,
r11,
r12,
- r13,
- sp = r13,
- r14,
- lr = r14,
- r15,
- pc = r15
+ r13, sp = r13,
+ r14, lr = r14,
+ r15, pc = r15
} RegisterID;
typedef enum {
d0,
d1,
d2,
- d3,
- SD0 = d3
+ d3, SD0 = d3,
+ d4,
+ d5,
+ d6,
+ d7,
+ d8,
+ d9,
+ d10,
+ d11,
+ d12,
+ d13,
+ d14,
+ d15,
+ d16,
+ d17,
+ d18,
+ d19,
+ d20,
+ d21,
+ d22,
+ d23,
+ d24,
+ d25,
+ d26,
+ d27,
+ d28,
+ d29,
+ d30,
+ d31
} FPRegisterID;
} // namespace ARMRegisters
@@ -118,12 +140,12 @@ namespace JSC {
MVN = (0xf << 21),
MUL = 0x00000090,
MULL = 0x00c00090,
- FADDD = 0x0e300b00,
- FDIVD = 0x0e800b00,
- FSUBD = 0x0e300b40,
- FMULD = 0x0e200b00,
- FCMPD = 0x0eb40b40,
- FSQRTD = 0x0eb10bc0,
+ VADD_F64 = 0x0e300b00,
+ VDIV_F64 = 0x0e800b00,
+ VSUB_F64 = 0x0e300b40,
+ VMUL_F64 = 0x0e200b00,
+ VCMP_F64 = 0x0eb40b40,
+ VSQRT_F64 = 0x0eb10bc0,
DTR = 0x05000000,
LDRH = 0x00100090,
STRH = 0x00000090,
@@ -135,11 +157,11 @@ namespace JSC {
#if WTF_ARM_ARCH_AT_LEAST(5) || defined(__ARM_ARCH_4T__)
BX = 0x012fff10,
#endif
- FMSR = 0x0e000a10,
- FMRS = 0x0e100a10,
- FSITOD = 0x0eb80bc0,
- FTOSID = 0x0ebd0b40,
- FMSTAT = 0x0ef1fa10,
+ VMOV_VFP = 0x0e000a10,
+ VMOV_ARM = 0x0e100a10,
+ VCVT_F64_S32 = 0x0eb80bc0,
+ VCVT_S32_F64 = 0x0ebd0b40,
+ VMRS_APSR = 0x0ef1fa10,
#if WTF_ARM_ARCH_AT_LEAST(5)
CLZ = 0x016f0f10,
BKPT = 0xe120070,
@@ -234,10 +256,26 @@ namespace JSC {
void emitInst(ARMWord op, int rd, int rn, ARMWord op2)
{
- ASSERT ( ((op2 & ~OP2_IMM) <= 0xfff) || (((op2 & ~OP2_IMMh) <= 0xfff)) );
+ ASSERT(((op2 & ~OP2_IMM) <= 0xfff) || (((op2 & ~OP2_IMMh) <= 0xfff)));
m_buffer.putInt(op | RN(rn) | RD(rd) | op2);
}
+ void emitDoublePrecisionInst(ARMWord op, int dd, int dn, int dm)
+ {
+ ASSERT((dd >= 0 && dd <= 31) && (dn >= 0 && dn <= 31) && (dm >= 0 && dm <= 31));
+ m_buffer.putInt(op | ((dd & 0xf) << 12) | ((dd & 0x10) << (22 - 4))
+ | ((dn & 0xf) << 16) | ((dn & 0x10) << (7 - 4))
+ | (dm & 0xf) | ((dm & 0x10) << (5 - 4)));
+ }
+
+ void emitSinglePrecisionInst(ARMWord op, int sd, int sn, int sm)
+ {
+ ASSERT((sd >= 0 && sd <= 31) && (sn >= 0 && sn <= 31) && (sm >= 0 && sm <= 31));
+ m_buffer.putInt(op | ((sd >> 1) << 12) | ((sd & 0x1) << 22)
+ | ((sn >> 1) << 16) | ((sn & 0x1) << 7)
+ | (sm >> 1) | ((sm & 0x1) << 5));
+ }
+
void and_r(int rd, int rn, ARMWord op2, Condition cc = AL)
{
emitInst(static_cast<ARMWord>(cc) | AND, rd, rn, op2);
@@ -402,34 +440,34 @@ namespace JSC {
m_buffer.putInt(static_cast<ARMWord>(cc) | MULL | RN(rdhi) | RD(rdlo) | RS(rn) | RM(rm));
}
- void faddd_r(int dd, int dn, int dm, Condition cc = AL)
+ void vadd_f64_r(int dd, int dn, int dm, Condition cc = AL)
{
- emitInst(static_cast<ARMWord>(cc) | FADDD, dd, dn, dm);
+ emitDoublePrecisionInst(static_cast<ARMWord>(cc) | VADD_F64, dd, dn, dm);
}
- void fdivd_r(int dd, int dn, int dm, Condition cc = AL)
+ void vdiv_f64_r(int dd, int dn, int dm, Condition cc = AL)
{
- emitInst(static_cast<ARMWord>(cc) | FDIVD, dd, dn, dm);
+ emitDoublePrecisionInst(static_cast<ARMWord>(cc) | VDIV_F64, dd, dn, dm);
}
- void fsubd_r(int dd, int dn, int dm, Condition cc = AL)
+ void vsub_f64_r(int dd, int dn, int dm, Condition cc = AL)
{
- emitInst(static_cast<ARMWord>(cc) | FSUBD, dd, dn, dm);
+ emitDoublePrecisionInst(static_cast<ARMWord>(cc) | VSUB_F64, dd, dn, dm);
}
- void fmuld_r(int dd, int dn, int dm, Condition cc = AL)
+ void vmul_f64_r(int dd, int dn, int dm, Condition cc = AL)
{
- emitInst(static_cast<ARMWord>(cc) | FMULD, dd, dn, dm);
+ emitDoublePrecisionInst(static_cast<ARMWord>(cc) | VMUL_F64, dd, dn, dm);
}
- void fcmpd_r(int dd, int dm, Condition cc = AL)
+ void vcmp_f64_r(int dd, int dm, Condition cc = AL)
{
- emitInst(static_cast<ARMWord>(cc) | FCMPD, dd, 0, dm);
+ emitDoublePrecisionInst(static_cast<ARMWord>(cc) | VCMP_F64, dd, 0, dm);
}
- void fsqrtd_r(int dd, int dm, Condition cc = AL)
+ void vsqrt_f64_r(int dd, int dm, Condition cc = AL)
{
- emitInst(static_cast<ARMWord>(cc) | FSQRTD, dd, 0, dm);
+ emitDoublePrecisionInst(static_cast<ARMWord>(cc) | VSQRT_F64, dd, 0, dm);
}
void ldr_imm(int rd, ARMWord imm, Condition cc = AL)
@@ -516,29 +554,33 @@ namespace JSC {
dtr_u(true, reg, ARMRegisters::sp, 0, cc);
}
- void fmsr_r(int dd, int rn, Condition cc = AL)
+ void vmov_vfp_r(int sn, int rt, Condition cc = AL)
{
- emitInst(static_cast<ARMWord>(cc) | FMSR, rn, dd, 0);
+ ASSERT(rt <= 15);
+ emitSinglePrecisionInst(static_cast<ARMWord>(cc) | VMOV_VFP, rt << 1, sn, 0);
}
- void fmrs_r(int rd, int dn, Condition cc = AL)
+ void vmov_arm_r(int rt, int sn, Condition cc = AL)
{
- emitInst(static_cast<ARMWord>(cc) | FMRS, rd, dn, 0);
+ ASSERT(rt <= 15);
+ emitSinglePrecisionInst(static_cast<ARMWord>(cc) | VMOV_ARM, rt << 1, sn, 0);
}
- void fsitod_r(int dd, int dm, Condition cc = AL)
+ void vcvt_f64_s32_r(int dd, int sm, Condition cc = AL)
{
- emitInst(static_cast<ARMWord>(cc) | FSITOD, dd, 0, dm);
+ ASSERT(!(sm & 0x1)); // sm must be divisible by 2
+ emitDoublePrecisionInst(static_cast<ARMWord>(cc) | VCVT_F64_S32, dd, 0, (sm >> 1));
}
- void ftosid_r(int fd, int dm, Condition cc = AL)
+ void vcvt_s32_f64_r(int sd, int dm, Condition cc = AL)
{
- emitInst(static_cast<ARMWord>(cc) | FTOSID, fd, 0, dm);
+ ASSERT(!(sd & 0x1)); // sd must be divisible by 2
+ emitDoublePrecisionInst(static_cast<ARMWord>(cc) | VCVT_S32_F64, (sd >> 1), 0, dm);
}
- void fmstat(Condition cc = AL)
+ void vmrs_apsr(Condition cc = AL)
{
- m_buffer.putInt(static_cast<ARMWord>(cc) | FMSTAT);
+ m_buffer.putInt(static_cast<ARMWord>(cc) | VMRS_APSR);
}
#if WTF_ARM_ARCH_AT_LEAST(5)
diff --git a/JavaScriptCore/assembler/MacroAssemblerARM.h b/JavaScriptCore/assembler/MacroAssemblerARM.h
index bb1a6da..48ddf24 100644
--- a/JavaScriptCore/assembler/MacroAssemblerARM.h
+++ b/JavaScriptCore/assembler/MacroAssemblerARM.h
@@ -795,7 +795,7 @@ public:
void addDouble(FPRegisterID src, FPRegisterID dest)
{
- m_assembler.faddd_r(dest, dest, src);
+ m_assembler.vadd_f64_r(dest, dest, src);
}
void addDouble(Address src, FPRegisterID dest)
@@ -806,7 +806,7 @@ public:
void divDouble(FPRegisterID src, FPRegisterID dest)
{
- m_assembler.fdivd_r(dest, dest, src);
+ m_assembler.vdiv_f64_r(dest, dest, src);
}
void divDouble(Address src, FPRegisterID dest)
@@ -818,7 +818,7 @@ public:
void subDouble(FPRegisterID src, FPRegisterID dest)
{
- m_assembler.fsubd_r(dest, dest, src);
+ m_assembler.vsub_f64_r(dest, dest, src);
}
void subDouble(Address src, FPRegisterID dest)
@@ -829,7 +829,7 @@ public:
void mulDouble(FPRegisterID src, FPRegisterID dest)
{
- m_assembler.fmuld_r(dest, dest, src);
+ m_assembler.vmul_f64_r(dest, dest, src);
}
void mulDouble(Address src, FPRegisterID dest)
@@ -840,13 +840,13 @@ public:
void sqrtDouble(FPRegisterID src, FPRegisterID dest)
{
- m_assembler.fsqrtd_r(dest, src);
+ m_assembler.vsqrt_f64_r(dest, src);
}
void convertInt32ToDouble(RegisterID src, FPRegisterID dest)
{
- m_assembler.fmsr_r(dest, src);
- m_assembler.fsitod_r(dest, dest);
+ m_assembler.vmov_vfp_r(dest << 1, src);
+ m_assembler.vcvt_f64_s32_r(dest, dest << 1);
}
void convertInt32ToDouble(Address src, FPRegisterID dest)
@@ -868,8 +868,8 @@ public:
Jump branchDouble(DoubleCondition cond, FPRegisterID left, FPRegisterID right)
{
- m_assembler.fcmpd_r(left, right);
- m_assembler.fmstat();
+ m_assembler.vcmp_f64_r(left, right);
+ m_assembler.vmrs_apsr();
if (cond & DoubleConditionBitSpecial)
m_assembler.cmp_r(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::VS);
return Jump(m_assembler.jmp(static_cast<ARMAssembler::Condition>(cond & ~DoubleConditionMask)));
@@ -893,11 +893,11 @@ public:
// (specifically, in this case, 0).
void branchConvertDoubleToInt32(FPRegisterID src, RegisterID dest, JumpList& failureCases, FPRegisterID fpTemp)
{
- m_assembler.ftosid_r(ARMRegisters::SD0, src);
- m_assembler.fmrs_r(dest, ARMRegisters::SD0);
+ m_assembler.vcvt_s32_f64_r(ARMRegisters::SD0 << 1, src);
+ m_assembler.vmov_arm_r(dest, ARMRegisters::SD0 << 1);
// Convert the integer result back to float & compare to the original value - if not equal or unordered (NaN) then jump.
- m_assembler.fsitod_r(ARMRegisters::SD0, ARMRegisters::SD0);
+ m_assembler.vcvt_f64_s32_r(ARMRegisters::SD0, ARMRegisters::SD0 << 1);
failureCases.append(branchDouble(DoubleNotEqualOrUnordered, src, ARMRegisters::SD0));
// If the result is zero, it might have been -0.0, and 0.0 equals to -0.0
--
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