[SCM] WebKit Debian packaging branch, debian/experimental, updated. upstream/1.3.3-9427-gc2be6fc
commit-queue at webkit.org
commit-queue at webkit.org
Wed Dec 22 15:06:48 UTC 2010
The following commit has been merged in the debian/experimental branch:
commit 309317451bb32c903908a8a8680762c2736620e5
Author: commit-queue at webkit.org <commit-queue at webkit.org@268f45cc-cd09-0410-ab3c-d52691b4dbfc>
Date: Thu Oct 28 01:30:09 2010 +0000
2010-10-27 Chao-ying Fu <fu at mips.com>
Reviewed by Oliver Hunt.
Support emit_op_mod() for MIPS on JSVALUE32_64
https://bugs.webkit.org/show_bug.cgi?id=46511
This patch uses MIPS div instructions for op_mod to improve performance.
* jit/JITArithmetic32_64.cpp:
(JSC::JIT::emit_op_mod):
git-svn-id: http://svn.webkit.org/repository/webkit/trunk@70736 268f45cc-cd09-0410-ab3c-d52691b4dbfc
diff --git a/JavaScriptCore/ChangeLog b/JavaScriptCore/ChangeLog
index 42c5f7a..ee304a9 100644
--- a/JavaScriptCore/ChangeLog
+++ b/JavaScriptCore/ChangeLog
@@ -1,3 +1,15 @@
+2010-10-27 Chao-ying Fu <fu at mips.com>
+
+ Reviewed by Oliver Hunt.
+
+ Support emit_op_mod() for MIPS on JSVALUE32_64
+ https://bugs.webkit.org/show_bug.cgi?id=46511
+
+ This patch uses MIPS div instructions for op_mod to improve performance.
+
+ * jit/JITArithmetic32_64.cpp:
+ (JSC::JIT::emit_op_mod):
+
2010-10-27 Brent Fulgham <bfulgham at webkit.org>
Unreviewed build correction.
diff --git a/JavaScriptCore/jit/JITArithmetic32_64.cpp b/JavaScriptCore/jit/JITArithmetic32_64.cpp
index 8683c74..e0b31f0 100644
--- a/JavaScriptCore/jit/JITArithmetic32_64.cpp
+++ b/JavaScriptCore/jit/JITArithmetic32_64.cpp
@@ -1293,7 +1293,7 @@ void JIT::emitSlow_op_div(Instruction* currentInstruction, Vector<SlowCaseEntry>
/* ------------------------------ BEGIN: OP_MOD ------------------------------ */
-#if CPU(X86) || CPU(X86_64)
+#if CPU(X86) || CPU(X86_64) || CPU(MIPS)
void JIT::emit_op_mod(Instruction* currentInstruction)
{
@@ -1301,34 +1301,47 @@ void JIT::emit_op_mod(Instruction* currentInstruction)
unsigned op1 = currentInstruction[2].u.operand;
unsigned op2 = currentInstruction[3].u.operand;
+#if CPU(X86) || CPU(X86_64)
+ // Make sure registers are correct for x86 IDIV instructions.
+ ASSERT(regT0 == X86Registers::eax);
+ ASSERT(regT1 == X86Registers::edx);
+ ASSERT(regT2 == X86Registers::ecx);
+ ASSERT(regT3 == X86Registers::ebx);
+#endif
+
if (isOperandConstantImmediateInt(op2) && getConstantOperand(op2).asInt32() != 0) {
- emitLoad(op1, X86Registers::edx, X86Registers::eax);
- move(Imm32(getConstantOperand(op2).asInt32()), X86Registers::ecx);
- addSlowCase(branch32(NotEqual, X86Registers::edx, Imm32(JSValue::Int32Tag)));
+ emitLoad(op1, regT1, regT0);
+ move(Imm32(getConstantOperand(op2).asInt32()), regT2);
+ addSlowCase(branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag)));
if (getConstantOperand(op2).asInt32() == -1)
- addSlowCase(branch32(Equal, X86Registers::eax, Imm32(0x80000000))); // -2147483648 / -1 => EXC_ARITHMETIC
+ addSlowCase(branch32(Equal, regT0, Imm32(0x80000000))); // -2147483648 / -1 => EXC_ARITHMETIC
} else {
- emitLoad2(op1, X86Registers::edx, X86Registers::eax, op2, X86Registers::ebx, X86Registers::ecx);
- addSlowCase(branch32(NotEqual, X86Registers::edx, Imm32(JSValue::Int32Tag)));
- addSlowCase(branch32(NotEqual, X86Registers::ebx, Imm32(JSValue::Int32Tag)));
+ emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
+ addSlowCase(branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag)));
+ addSlowCase(branch32(NotEqual, regT3, Imm32(JSValue::Int32Tag)));
- addSlowCase(branch32(Equal, X86Registers::eax, Imm32(0x80000000))); // -2147483648 / -1 => EXC_ARITHMETIC
- addSlowCase(branch32(Equal, X86Registers::ecx, Imm32(0))); // divide by 0
+ addSlowCase(branch32(Equal, regT0, Imm32(0x80000000))); // -2147483648 / -1 => EXC_ARITHMETIC
+ addSlowCase(branch32(Equal, regT2, Imm32(0))); // divide by 0
}
- move(X86Registers::eax, X86Registers::ebx); // Save dividend payload, in case of 0.
+ move(regT0, regT3); // Save dividend payload, in case of 0.
+#if CPU(X86) || CPU(X86_64)
m_assembler.cdq();
- m_assembler.idivl_r(X86Registers::ecx);
+ m_assembler.idivl_r(regT2);
+#elif CPU(MIPS)
+ m_assembler.div(regT0, regT2);
+ m_assembler.mfhi(regT1);
+#endif
// If the remainder is zero and the dividend is negative, the result is -0.
- Jump storeResult1 = branchTest32(NonZero, X86Registers::edx);
- Jump storeResult2 = branchTest32(Zero, X86Registers::ebx, Imm32(0x80000000)); // not negative
+ Jump storeResult1 = branchTest32(NonZero, regT1);
+ Jump storeResult2 = branchTest32(Zero, regT3, Imm32(0x80000000)); // not negative
emitStore(dst, jsNumber(-0.0));
Jump end = jump();
storeResult1.link(this);
storeResult2.link(this);
- emitStoreInt32(dst, X86Registers::edx, (op1 == dst || op2 == dst));
+ emitStoreInt32(dst, regT1, (op1 == dst || op2 == dst));
end.link(this);
}
@@ -1355,7 +1368,7 @@ void JIT::emitSlow_op_mod(Instruction* currentInstruction, Vector<SlowCaseEntry>
stubCall.call(dst);
}
-#else // CPU(X86) || CPU(X86_64)
+#else // CPU(X86) || CPU(X86_64) || CPU(MIPS)
void JIT::emit_op_mod(Instruction* currentInstruction)
{
--
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