[gcc-6] 156/401: * Update to SVN 20160603 (r237075, 6.1.1) from the gcc-6-branch.
Ximin Luo
infinity0 at debian.org
Wed Apr 5 15:48:44 UTC 2017
This is an automated email from the git hooks/post-receive script.
infinity0 pushed a commit to branch pu/reproducible_builds
in repository gcc-6.
commit 66099fbd8c3bfdd25f22bd76ec7c9215462c7a63
Author: doko <doko at 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca>
Date: Fri Jun 3 16:59:55 2016 +0000
* Update to SVN 20160603 (r237075, 6.1.1) from the gcc-6-branch.
git-svn-id: svn://anonscm.debian.org/gcccvs/branches/sid/gcc-6@8873 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca
---
debian/changelog | 6 +-
debian/patches/svn-updates.diff | 1052 +++++++++++++++++++++++++++++++++++++--
2 files changed, 1021 insertions(+), 37 deletions(-)
diff --git a/debian/changelog b/debian/changelog
index c130be1..0120738 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,6 +1,6 @@
gcc-6 (6.1.1-5) UNRELEASED; urgency=medium
- * Update to SVN 20160602 (r237043, 6.1.1) from the gcc-6-branch.
+ * Update to SVN 20160603 (r237075, 6.1.1) from the gcc-6-branch.
- Fix PR libstdc++/70762, PR libstdc++/69703, PR libstdc++/69703,
PR libstdc++/71038, PR libstdc++/71036, PR libstdc++/71037,
PR libstdc++/71005, PR libstdc++/71004, PR libstdc++/70609, PR c/71171,
@@ -13,7 +13,7 @@ gcc-6 (6.1.1-5) UNRELEASED; urgency=medium
PR c++/71372, PR c++/70972, PR c++/71166, PR c++/71227, PR c++/60095,
PR c++/69515, PR c++/69009, PR c++/71173, PR c++/70522, PR c++/70584,
PR c++/70735, PR c++/71306, PR c++/71349, PR c++/71105, PR c++/71147,
- PR ada/71358, PR ada/71317, PR fortran/71156.
+ PR ada/71358, PR ada/71317, PR fortran/71156, PR middle-end/71387.
* Fix cross building libgnatprj on i386 targeting 64bit archs (YunQiang Su).
Closes: #823126.
* Detect hard float for non-linux or non-glibc arm-*-*eabihf builds (Helmut
@@ -22,7 +22,7 @@ gcc-6 (6.1.1-5) UNRELEASED; urgency=medium
* gccgo: Combine combine gccgo's ld() and ldShared() methods
in cmd/go (Michael Hudson-Doyle). LP: #1586872.
- -- Matthias Klose <doko at debian.org> Thu, 02 Jun 2016 23:07:05 +0200
+ -- Matthias Klose <doko at debian.org> Fri, 03 Jun 2016 18:58:40 +0200
gcc-6 (6.1.1-4) unstable; urgency=medium
diff --git a/debian/patches/svn-updates.diff b/debian/patches/svn-updates.diff
index 8bd6fb0..19a6a15 100644
--- a/debian/patches/svn-updates.diff
+++ b/debian/patches/svn-updates.diff
@@ -1,10 +1,10 @@
-# DP: updates from the 6 branch upto 20160602 (r237043).
+# DP: updates from the 6 branch upto 20160603 (r237075).
last_update()
{
cat > ${dir}LAST_UPDATED <EOF
-Thu Jun 2 19:49:56 CEST 2016
-Thu Jun 2 17:49:56 UTC 2016 (revision 237043)
+Fri Jun 3 18:53:33 CEST 2016
+Fri Jun 3 16:53:33 UTC 2016 (revision 237075)
EOF
}
@@ -3331,13 +3331,26 @@ Index: gcc/cgraph.c
===================================================================
--- a/src/gcc/cgraph.c (.../tags/gcc_6_1_0_release)
+++ b/src/gcc/cgraph.c (.../branches/gcc-6-branch)
-@@ -1507,7 +1507,8 @@
+@@ -1504,10 +1504,21 @@
+ update_stmt_fn (DECL_STRUCT_FUNCTION (e->caller->decl), new_stmt);
+ }
+
++ /* If changing the call to __cxa_pure_virtual or similar noreturn function,
++ adjust gimple_call_fntype too. */
++ if (gimple_call_noreturn_p (new_stmt)
++ && VOID_TYPE_P (TREE_TYPE (TREE_TYPE (e->callee->decl)))
++ && TYPE_ARG_TYPES (TREE_TYPE (e->callee->decl))
++ && (TREE_VALUE (TYPE_ARG_TYPES (TREE_TYPE (e->callee->decl)))
++ == void_type_node))
++ gimple_call_set_fntype (new_stmt, TREE_TYPE (e->callee->decl));
++
/* If the call becomes noreturn, remove the LHS if possible. */
if (lhs
&& (gimple_call_flags (new_stmt) & ECF_NORETURN)
- && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (lhs))) == INTEGER_CST)
-+ && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (lhs))) == INTEGER_CST
-+ && !TREE_ADDRESSABLE (TREE_TYPE (lhs)))
++ && (VOID_TYPE_P (TREE_TYPE (gimple_call_fntype (new_stmt)))
++ || (TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (lhs))) == INTEGER_CST
++ && !TREE_ADDRESSABLE (TREE_TYPE (lhs)))))
{
if (TREE_CODE (lhs) == SSA_NAME)
{
@@ -3347,7 +3360,7 @@ Index: gcc/DATESTAMP
+++ b/src/gcc/DATESTAMP (.../branches/gcc-6-branch)
@@ -1 +1 @@
-20160427
-+20160602
++20160603
Index: gcc/tree.h
===================================================================
--- a/src/gcc/tree.h (.../tags/gcc_6_1_0_release)
@@ -3621,7 +3634,73 @@ Index: gcc/ChangeLog
===================================================================
--- a/src/gcc/ChangeLog (.../tags/gcc_6_1_0_release)
+++ b/src/gcc/ChangeLog (.../branches/gcc-6-branch)
-@@ -1,3 +1,784 @@
+@@ -1,3 +1,850 @@
++2016-06-03 Jakub Jelinek <jakub at redhat.com>
++
++ PR middle-end/71387
++ * cgraph.c (cgraph_edge::redirect_call_stmt_to_callee): If redirecting
++ to noreturn e->callee->decl that has void return type and void
++ arguments, adjust gimple_call_fntype and remove lhs even if it had
++ previously addressable type.
++
++2016-06-02 Michael Meissner <meissner at linux.vnet.ibm.com>
++
++ Back port from trunk
++ 2016-05-26 Michael Meissner <meissner at linux.vnet.ibm.com>
++
++ * config/rs6000/rs6000.c (rs6000_emit_p9_fp_minmax): New function
++ for ISA 3.0 min/max support.
++ (rs6000_emit_p9_fp_cmove): New function for ISA 3.0 floating point
++ conditional move support.
++ (rs6000_emit_cmove): Call rs6000_emit_p9_fp_minmax and
++ rs6000_emit_p9_fp_cmove if the ISA 3.0 instructions are
++ available.
++ * config/rs6000/rs6000.md (SFDF2): New iterator to allow doing
++ conditional moves where the comparison type is different from move
++ type.
++ (fp_minmax): New code iterator for smin/smax.
++ (minmax): New code attributes for min/max.
++ (SMINMAX): Likewise.
++ (smax<mode>3): Combine min, max insns into one insn using the
++ fp_minmax code iterator. Add support for ISA 3.0 min/max
++ instructions that don't need -ffast-math.
++ (s<minmax><mode>3): Likewise.
++ (smax<mode>3_vsx): Likewise.
++ (smin<mode>3): Likewise.
++ (s<minmax><mode>3_vsx): Likewise.
++ (smin<mode>3_vsx): Likewise.
++ (pre-VSX min/max splitters): Likewise.
++ (s<minmax><mode>3_fpr): Likewise.
++ (movsfcc): Rewrite floating point conditional moves to combine
++ SFmode/DFmode into a single insn.
++ (mov<mode>cc): Likewise.
++ (movdfcc): Likewise.
++ (fselsfsf4): Combine FSEL cases into a single insn, using SFDF and
++ SFDF2 iterators to handle all combinations.
++ (fseldfsf4): Likewise.
++ (fsel<SFDF:mode><SFDF2:mode>4): Likewise.
++ (fseldfdf4): Likewise.
++ (fselsfdf4): Likewise.
++ (mov<SFDF:mode><SFDF2:mode>cc_p9): Add support for the ISA 3.0
++ comparison instructions that set a 0/-1 mask, and use it for
++ floating point conditional move via XXSEL.
++ (fpmask<mode>): Likewise.
++ (xxsel<mode>): Likewise.
++ * config/rs6000/predicates.md (min_max_operator): Delete, no
++ longer used.
++ (fpmask_comparison_operaton): New insn for ISA 3.0 comparison
++ instructions that generate a 0/-1 mask for use with XXSEL.
++ * config/rs6000/rs6000.h (TARGET_MINMAX_SF): New helper macros to
++ say whether floating point min/max is available, either through
++ FSEL, ISA 2.06 min/max, and ISA 3.0 min/max instrucitons.
++ (TARGET_MINMAX_DF): Likewise.
++
++ Back port from trunk
++ 2016-05-18 Michael Meissner <meissner at linux.vnet.ibm.com>
++
++ * config/rs6000/predicate.md (all_ones_constant): New predicate
++ for vector constant with all 1's set.
++
+2016-06-02 Kelvin Nilsen <kelvin at gcc.gnu.org>
+
+ Back port from trunk
@@ -4406,7 +4485,7 @@ Index: gcc/ChangeLog
2016-04-27 Release Manager
* GCC 6.1.0 released.
-@@ -49,7 +830,7 @@
+@@ -49,7 +896,7 @@
constant boolean.
2016-04-20 Andrew Pinski <apinski at cavium.com>
@@ -4415,14 +4494,191 @@ Index: gcc/ChangeLog
PR target/64971
* config/aarch64/aarch64.md (sibcall): Force call
+Index: gcc/testsuite/gcc.target/powerpc/p9-minmax-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/p9-minmax-1.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/p9-minmax-1.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,171 @@
++/* { dg-do compile { target { powerpc*-*-* } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-options "-mcpu=power9 -O2 -mpower9-minmax -ffast-math" } */
++/* { dg-final { scan-assembler-not "fsel" } } */
++/* { dg-final { scan-assembler "xscmpeqdp" } } */
++/* { dg-final { scan-assembler "xscmpgtdp" } } */
++/* { dg-final { scan-assembler "xscmpgedp" } } */
++/* { dg-final { scan-assembler-not "xscmpodp" } } */
++/* { dg-final { scan-assembler-not "xscmpudp" } } */
++/* { dg-final { scan-assembler "xsmaxcdp" } } */
++/* { dg-final { scan-assembler-not "xsmaxdp" } } */
++/* { dg-final { scan-assembler "xsmincdp" } } */
++/* { dg-final { scan-assembler-not "xsmindp" } } */
++/* { dg-final { scan-assembler "xxsel" } } */
++
++double
++dbl_max1 (double a, double b)
++{
++ return (a >= b) ? a : b;
++}
++
++double
++dbl_max2 (double a, double b)
++{
++ return (a > b) ? a : b;
++}
++
++double
++dbl_min1 (double a, double b)
++{
++ return (a < b) ? a : b;
++}
++
++double
++dbl_min2 (double a, double b)
++{
++ return (a <= b) ? a : b;
++}
++
++double
++dbl_cmp_eq (double a, double b, double c, double d)
++{
++ return (a == b) ? c : d;
++}
++
++double
++dbl_cmp_ne (double a, double b, double c, double d)
++{
++ return (a != b) ? c : d;
++}
++
++double
++dbl_cmp_gt (double a, double b, double c, double d)
++{
++ return (a > b) ? c : d;
++}
++
++double
++dbl_cmp_ge (double a, double b, double c, double d)
++{
++ return (a >= b) ? c : d;
++}
++
++double
++dbl_cmp_lt (double a, double b, double c, double d)
++{
++ return (a < b) ? c : d;
++}
++
++double
++dbl_cmp_le (double a, double b, double c, double d)
++{
++ return (a <= b) ? c : d;
++}
++
++float
++flt_max1 (float a, float b)
++{
++ return (a >= b) ? a : b;
++}
++
++float
++flt_max2 (float a, float b)
++{
++ return (a > b) ? a : b;
++}
++
++float
++flt_min1 (float a, float b)
++{
++ return (a < b) ? a : b;
++}
++
++float
++flt_min2 (float a, float b)
++{
++ return (a <= b) ? a : b;
++}
++
++float
++flt_cmp_eq (float a, float b, float c, float d)
++{
++ return (a == b) ? c : d;
++}
++
++float
++flt_cmp_ne (float a, float b, float c, float d)
++{
++ return (a != b) ? c : d;
++}
++
++float
++flt_cmp_gt (float a, float b, float c, float d)
++{
++ return (a > b) ? c : d;
++}
++
++float
++flt_cmp_ge (float a, float b, float c, float d)
++{
++ return (a >= b) ? c : d;
++}
++
++float
++flt_cmp_lt (float a, float b, float c, float d)
++{
++ return (a < b) ? c : d;
++}
++
++float
++flt_cmp_le (float a, float b, float c, float d)
++{
++ return (a <= b) ? c : d;
++}
++
++double
++dbl_flt_max1 (float a, float b)
++{
++ return (a > b) ? a : b;
++}
++
++double
++dbl_flt_max2 (double a, float b)
++{
++ return (a > b) ? a : b;
++}
++
++double
++dbl_flt_max3 (float a, double b)
++{
++ return (a > b) ? a : b;
++}
++
++double
++dbl_flt_min1 (float a, float b)
++{
++ return (a < b) ? a : b;
++}
++
++double
++dbl_flt_min2 (double a, float b)
++{
++ return (a < b) ? a : b;
++}
++
++double
++dbl_flt_min3 (float a, double b)
++{
++ return (a < b) ? a : b;
++}
Index: gcc/testsuite/gcc.target/powerpc/vsx-elemrev-4.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-4.c (.../tags/gcc_6_1_0_release)
+++ b/src/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-4.c (.../branches/gcc-6-branch)
-@@ -0,0 +1,228 @@
+@@ -0,0 +1,229 @@
+/* { dg-do compile { target { powerpc64-*-* } } } */
+/* { dg-skip-if "do not override mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-options "-mcpu=power9 -O0" } */
++/* { dg-require-effective-target p9vector_hw } */
+/* { dg-final { scan-assembler-times "lxvx" 40 } } */
+/* { dg-final { scan-assembler-times "stxvx" 40 } } */
+
@@ -4678,6 +4934,202 @@ Index: gcc/testsuite/gcc.target/powerpc/darn-2.c
+}
+
+/* { dg-final { scan-assembler "darn" } } */
+Index: gcc/testsuite/gcc.target/powerpc/p9-minmax-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/p9-minmax-2.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/p9-minmax-2.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,191 @@
++/* { dg-do compile { target { powerpc*-*-* } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-options "-mcpu=power9 -O2 -mpower9-minmax" } */
++/* { dg-final { scan-assembler-not "fsel" } } */
++/* { dg-final { scan-assembler "xscmpeqdp" } } */
++/* { dg-final { scan-assembler "xscmpgtdp" } } */
++/* { dg-final { scan-assembler-not "xscmpodp" } } */
++/* { dg-final { scan-assembler-not "xscmpudp" } } */
++/* { dg-final { scan-assembler "xsmaxcdp" } } */
++/* { dg-final { scan-assembler-not "xsmaxdp" } } */
++/* { dg-final { scan-assembler "xsmincdp" } } */
++/* { dg-final { scan-assembler-not "xsmindp" } } */
++/* { dg-final { scan-assembler "xxsel" } } */
++
++/* Due to NaN support, <= and >= are not handled presently unless -ffast-math
++ is used. At some point this will be fixed and the xscmpgedp instruction can
++ be generated normally. The <= and >= tests are bracketed with
++ #ifdef DO_GE_LE. */
++
++#ifdef DO_GE_LE
++double
++dbl_max1 (double a, double b)
++{
++ return (a >= b) ? a : b;
++}
++#endif
++
++double
++dbl_max2 (double a, double b)
++{
++ return (a > b) ? a : b;
++}
++
++double
++dbl_min1 (double a, double b)
++{
++ return (a < b) ? a : b;
++}
++
++#ifdef DO_GE_LE
++double
++dbl_min2 (double a, double b)
++{
++ return (a <= b) ? a : b;
++}
++#endif
++
++double
++dbl_cmp_eq (double a, double b, double c, double d)
++{
++ return (a == b) ? c : d;
++}
++
++double
++dbl_cmp_ne (double a, double b, double c, double d)
++{
++ return (a != b) ? c : d;
++}
++
++double
++dbl_cmp_gt (double a, double b, double c, double d)
++{
++ return (a > b) ? c : d;
++}
++
++#ifdef DO_GE_LE
++double
++dbl_cmp_ge (double a, double b, double c, double d)
++{
++ return (a >= b) ? c : d;
++}
++#endif
++
++double
++dbl_cmp_lt (double a, double b, double c, double d)
++{
++ return (a < b) ? c : d;
++}
++
++#ifdef DO_GE_LE
++double
++dbl_cmp_le (double a, double b, double c, double d)
++{
++ return (a <= b) ? c : d;
++}
++#endif
++
++#ifdef DO_GE_LE
++float
++flt_max1 (float a, float b)
++{
++ return (a >= b) ? a : b;
++}
++#endif
++
++float
++flt_max2 (float a, float b)
++{
++ return (a > b) ? a : b;
++}
++
++float
++flt_min1 (float a, float b)
++{
++ return (a < b) ? a : b;
++}
++
++#ifdef DO_GE_LE
++float
++flt_min2 (float a, float b)
++{
++ return (a <= b) ? a : b;
++}
++#endif
++
++float
++flt_cmp_eq (float a, float b, float c, float d)
++{
++ return (a == b) ? c : d;
++}
++
++float
++flt_cmp_ne (float a, float b, float c, float d)
++{
++ return (a != b) ? c : d;
++}
++
++float
++flt_cmp_gt (float a, float b, float c, float d)
++{
++ return (a > b) ? c : d;
++}
++
++#ifdef DO_GE_LE
++float
++flt_cmp_ge (float a, float b, float c, float d)
++{
++ return (a >= b) ? c : d;
++}
++#endif
++
++float
++flt_cmp_lt (float a, float b, float c, float d)
++{
++ return (a < b) ? c : d;
++}
++
++#ifdef DO_GE_LE
++float
++flt_cmp_le (float a, float b, float c, float d)
++{
++ return (a <= b) ? c : d;
++}
++#endif
++
++double
++dbl_flt_max1 (float a, float b)
++{
++ return (a > b) ? a : b;
++}
++
++double
++dbl_flt_max2 (double a, float b)
++{
++ return (a > b) ? a : b;
++}
++
++double
++dbl_flt_max3 (float a, double b)
++{
++ return (a > b) ? a : b;
++}
++
++double
++dbl_flt_min1 (float a, float b)
++{
++ return (a < b) ? a : b;
++}
++
++double
++dbl_flt_min2 (double a, float b)
++{
++ return (a < b) ? a : b;
++}
++
++double
++dbl_flt_min3 (float a, double b)
++{
++ return (a < b) ? a : b;
++}
Index: gcc/testsuite/gcc.target/powerpc/p9-vparity.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/powerpc/p9-vparity.c (.../tags/gcc_6_1_0_release)
@@ -5289,10 +5741,11 @@ Index: gcc/testsuite/gcc.target/powerpc/vsx-elemrev-2.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-2.c (.../tags/gcc_6_1_0_release)
+++ b/src/gcc/testsuite/gcc.target/powerpc/vsx-elemrev-2.c (.../branches/gcc-6-branch)
-@@ -0,0 +1,234 @@
+@@ -0,0 +1,235 @@
+/* { dg-do compile { target { powerpc64le*-*-* } } } */
+/* { dg-skip-if "do not override mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-options "-mcpu=power9 -O0" } */
++/* { dg-require-effective-target p9vector_hw } */
+/* { dg-final { scan-assembler-times "lxvd2x" 6 } } */
+/* { dg-final { scan-assembler-times "lxvw4x" 6 } } */
+/* { dg-final { scan-assembler-times "lxvh8x" 4 } } */
@@ -8041,7 +8494,28 @@ Index: gcc/testsuite/ChangeLog
===================================================================
--- a/src/gcc/testsuite/ChangeLog (.../tags/gcc_6_1_0_release)
+++ b/src/gcc/testsuite/ChangeLog (.../branches/gcc-6-branch)
-@@ -1,3 +1,488 @@
+@@ -1,3 +1,509 @@
++2016-06-03 Bill Schmidt <wschmidt at linux.vnet.ibm.com>
++
++ PR target/70957
++ * gcc.target/powerpc/vsx-elemrev-2.c: Require p9vector hardware
++ support.
++ * gcc.target/powerpc/vsx-elemrev-4.c: Likewise.
++
++2016-06-03 Jakub Jelinek <jakub at redhat.com>
++
++ PR middle-end/71387
++ * g++.dg/opt/pr71387.C: New test.
++
++2016-06-02 Michael Meissner <meissner at linux.vnet.ibm.com>
++
++ Back port from trunk
++ 2016-05-26 Michael Meissner <meissner at linux.vnet.ibm.com>
++
++ * gcc.target/powerpc/p9-minmax-1.c: New tests for ISA 3.0
++ floating point min/max/comparison instructions.
++ * gcc.target/powerpc/p9-minmax-2.c: Likewise.
++
+2016-06-02 Jakub Jelinek <jakub at redhat.com>
+
+ PR c++/71372
@@ -8642,6 +9116,63 @@ Index: gcc/testsuite/g++.dg/opt/pr71210-1.C
+ S1 f3 () const { return f2 (); }
+};
+void f4 () { S2 a; a.f3 (); }
+Index: gcc/testsuite/g++.dg/opt/pr71387.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/opt/pr71387.C (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/g++.dg/opt/pr71387.C (.../branches/gcc-6-branch)
+@@ -0,0 +1,52 @@
++// PR middle-end/71387
++// { dg-do compile }
++// { dg-options "-Og" }
++
++struct A
++{
++ A ();
++ inline A (const A &);
++};
++
++struct B
++{
++ explicit B (unsigned long) : b(0), c(1) {}
++ A a;
++ unsigned long b;
++ int c;
++};
++
++struct C {};
++
++struct D
++{
++ explicit D (const C *) {}
++};
++
++struct E : public D
++{
++ E (const C *x) : D(x) {}
++ virtual A foo () const = 0;
++ virtual A bar () const = 0;
++};
++
++struct F : public B
++{
++ inline void baz ();
++ F (const E *);
++ const E *f;
++};
++
++inline void
++F::baz ()
++{
++ if (b == 0)
++ a = f->bar ();
++ else
++ a = f->foo ();
++}
++
++F::F (const E *) : B(4)
++{
++ baz ();
++}
Index: gcc/testsuite/g++.dg/pr71184.C
===================================================================
--- a/src/gcc/testsuite/g++.dg/pr71184.C (.../tags/gcc_6_1_0_release)
@@ -797893,7 +798424,19 @@ Index: gcc/config/rs6000/predicates.md
===================================================================
--- a/src/gcc/config/rs6000/predicates.md (.../tags/gcc_6_1_0_release)
+++ b/src/gcc/config/rs6000/predicates.md (.../branches/gcc-6-branch)
-@@ -698,48 +698,25 @@
+@@ -669,6 +669,11 @@
+ (and (match_code "const_int,const_double,const_wide_int,const_vector")
+ (match_test "op == CONST0_RTX (mode)")))
+
++;; Return 1 if operand is constant -1 (scalars and vectors).
++(define_predicate "all_ones_constant"
++ (and (match_code "const_int,const_double,const_wide_int,const_vector")
++ (match_test "op == CONSTM1_RTX (mode) && !FLOAT_MODE_P (mode)")))
++
+ ;; Return 1 if operand is 0.0.
+ (define_predicate "zero_fp_constant"
+ (and (match_code "const_double")
+@@ -698,48 +703,25 @@
(define_predicate "quad_memory_operand"
(match_code "mem")
{
@@ -797956,6 +798499,29 @@ Index: gcc/config/rs6000/predicates.md
})
;; Return 1 if the operand is an indexed or indirect memory operand.
+@@ -1091,10 +1073,6 @@
+ (define_special_predicate "equality_operator"
+ (match_code "eq,ne"))
+
+-;; Return true if operand is MIN or MAX operator.
+-(define_predicate "min_max_operator"
+- (match_code "smin,smax,umin,umax"))
+-
+ ;; Return 1 if OP is a comparison operation that is valid for a branch
+ ;; instruction. We check the opcode against the mode of the CC value.
+ ;; validate_condition_mode is an assertion.
+@@ -1137,6 +1115,11 @@
+ (and (match_operand 0 "branch_comparison_operator")
+ (match_code "ne,le,ge,leu,geu,ordered")))
+
++;; Return 1 if OP is a comparison operator suitable for vector/scalar
++;; comparisons that generate a -1/0 mask.
++(define_predicate "fpmask_comparison_operator"
++ (match_code "eq,gt,ge"))
++
+ ;; Return 1 if OP is a comparison operation that is valid for a branch
+ ;; insn, which is true if the corresponding bit in the CC register is set.
+ (define_predicate "branch_positive_comparison_operator"
Index: gcc/config/rs6000/rs6000-cpus.def
===================================================================
--- a/src/gcc/config/rs6000/rs6000-cpus.def (.../tags/gcc_6_1_0_release)
@@ -799699,7 +800265,128 @@ Index: gcc/config/rs6000/rs6000.c
else
return "stxvd2x %x1,%y0";
}
-@@ -25949,7 +26473,7 @@
+@@ -21747,6 +22271,101 @@
+ return 1;
+ }
+
++/* ISA 3.0 (power9) minmax subcase to emit a XSMAXCDP or XSMINCDP instruction
++ for SF/DF scalars. Move TRUE_COND to DEST if OP of the operands of the last
++ comparison is nonzero/true, FALSE_COND if it is zero/false. Return 0 if the
++ hardware has no such operation. */
++
++static int
++rs6000_emit_p9_fp_minmax (rtx dest, rtx op, rtx true_cond, rtx false_cond)
++{
++ enum rtx_code code = GET_CODE (op);
++ rtx op0 = XEXP (op, 0);
++ rtx op1 = XEXP (op, 1);
++ machine_mode compare_mode = GET_MODE (op0);
++ machine_mode result_mode = GET_MODE (dest);
++ bool max_p = false;
++
++ if (result_mode != compare_mode)
++ return 0;
++
++ if (code == GE || code == GT)
++ max_p = true;
++ else if (code == LE || code == LT)
++ max_p = false;
++ else
++ return 0;
++
++ if (rtx_equal_p (op0, true_cond) && rtx_equal_p (op1, false_cond))
++ ;
++
++ else if (rtx_equal_p (op1, true_cond) && rtx_equal_p (op0, false_cond))
++ max_p = !max_p;
++
++ else
++ return 0;
++
++ rs6000_emit_minmax (dest, max_p ? SMAX : SMIN, op0, op1);
++ return 1;
++}
++
++/* ISA 3.0 (power9) conditional move subcase to emit XSCMP{EQ,GE,GT,NE}DP and
++ XXSEL instructions for SF/DF scalars. Move TRUE_COND to DEST if OP of the
++ operands of the last comparison is nonzero/true, FALSE_COND if it is
++ zero/false. Return 0 if the hardware has no such operation. */
++
++static int
++rs6000_emit_p9_fp_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
++{
++ enum rtx_code code = GET_CODE (op);
++ rtx op0 = XEXP (op, 0);
++ rtx op1 = XEXP (op, 1);
++ machine_mode result_mode = GET_MODE (dest);
++ rtx compare_rtx;
++ rtx cmove_rtx;
++ rtx clobber_rtx;
++
++ if (!can_create_pseudo_p ())
++ return 0;
++
++ switch (code)
++ {
++ case EQ:
++ case GE:
++ case GT:
++ break;
++
++ case NE:
++ case LT:
++ case LE:
++ code = swap_condition (code);
++ std::swap (op0, op1);
++ break;
++
++ default:
++ return 0;
++ }
++
++ /* Generate: [(parallel [(set (dest)
++ (if_then_else (op (cmp1) (cmp2))
++ (true)
++ (false)))
++ (clobber (scratch))])]. */
++
++ compare_rtx = gen_rtx_fmt_ee (code, CCFPmode, op0, op1);
++ cmove_rtx = gen_rtx_SET (dest,
++ gen_rtx_IF_THEN_ELSE (result_mode,
++ compare_rtx,
++ true_cond,
++ false_cond));
++
++ clobber_rtx = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (V2DImode));
++ emit_insn (gen_rtx_PARALLEL (VOIDmode,
++ gen_rtvec (2, cmove_rtx, clobber_rtx)));
++
++ return 1;
++}
++
+ /* Emit a conditional move: move TRUE_COND to DEST if OP of the
+ operands of the last comparison is nonzero/true, FALSE_COND if it
+ is zero/false. Return 0 if the hardware has no such operation. */
+@@ -21773,6 +22392,18 @@
+ if (GET_MODE (false_cond) != result_mode)
+ return 0;
+
++ /* See if we can use the ISA 3.0 (power9) min/max/compare functions. */
++ if (TARGET_P9_MINMAX
++ && (compare_mode == SFmode || compare_mode == DFmode)
++ && (result_mode == SFmode || result_mode == DFmode))
++ {
++ if (rs6000_emit_p9_fp_minmax (dest, op, true_cond, false_cond))
++ return 1;
++
++ if (rs6000_emit_p9_fp_cmove (dest, op, true_cond, false_cond))
++ return 1;
++ }
++
+ /* Don't allow using floating point comparisons for integer results for
+ now. */
+ if (FLOAT_MODE_P (compare_mode) && !FLOAT_MODE_P (result_mode))
+@@ -25949,7 +26580,7 @@
if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
{
rtx areg, savereg, mem;
@@ -799708,7 +800395,7 @@ Index: gcc/config/rs6000/rs6000.c
offset = (info->altivec_save_offset + frame_off
+ 16 * (i - info->first_altivec_reg_save));
-@@ -25956,18 +26480,30 @@
+@@ -25956,18 +26587,30 @@
savereg = gen_rtx_REG (V4SImode, i);
@@ -799749,7 +800436,7 @@ Index: gcc/config/rs6000/rs6000.c
rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
areg, GEN_INT (offset));
-@@ -26687,23 +27223,35 @@
+@@ -26687,23 +27330,35 @@
for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
{
@@ -799799,7 +800486,7 @@ Index: gcc/config/rs6000/rs6000.c
}
}
-@@ -26890,23 +27438,35 @@
+@@ -26890,23 +27545,35 @@
for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
{
@@ -799849,7 +800536,7 @@ Index: gcc/config/rs6000/rs6000.c
}
}
-@@ -27724,6 +28284,11 @@
+@@ -27724,6 +28391,11 @@
const0_rtx, const0_rtx));
call_fusage = NULL_RTX;
use_reg (&call_fusage, r12);
@@ -799861,7 +800548,7 @@ Index: gcc/config/rs6000/rs6000.c
add_function_usage_to (insn, call_fusage);
emit_insn (gen_frame_load (r0, r1, info->lr_save_offset));
insn = emit_move_insn (lr, r0);
-@@ -33448,17 +34013,25 @@
+@@ -33448,17 +34120,25 @@
if (!REG_P (target))
tmp = gen_reg_rtx (mode);
@@ -799897,7 +800584,7 @@ Index: gcc/config/rs6000/rs6000.c
/* Copy into target, possibly by way of a register. */
if (!REG_P (target))
-@@ -34056,7 +34629,7 @@
+@@ -34056,7 +34736,7 @@
static bool
rs6000_lra_p (void)
{
@@ -799906,7 +800593,7 @@ Index: gcc/config/rs6000/rs6000.c
}
/* Given FROM and TO register numbers, say whether this elimination is allowed.
-@@ -34417,7 +34990,8 @@
+@@ -34417,7 +35097,8 @@
{ "power8-fusion", OPTION_MASK_P8_FUSION, false, true },
{ "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true },
{ "power8-vector", OPTION_MASK_P8_VECTOR, false, true },
@@ -799916,7 +800603,7 @@ Index: gcc/config/rs6000/rs6000.c
{ "power9-fusion", OPTION_MASK_P9_FUSION, false, true },
{ "power9-minmax", OPTION_MASK_P9_MINMAX, false, true },
{ "power9-vector", OPTION_MASK_P9_VECTOR, false, true },
-@@ -34474,6 +35048,7 @@
+@@ -34474,6 +35155,7 @@
{ "popcntd", RS6000_BTM_POPCNTD, false, false },
{ "cell", RS6000_BTM_CELL, false, false },
{ "power8-vector", RS6000_BTM_P8_VECTOR, false, false },
@@ -799924,7 +800611,7 @@ Index: gcc/config/rs6000/rs6000.c
{ "crypto", RS6000_BTM_CRYPTO, false, false },
{ "htm", RS6000_BTM_HTM, false, false },
{ "hard-dfp", RS6000_BTM_DFP, false, false },
-@@ -35049,7 +35624,9 @@
+@@ -35049,7 +35731,9 @@
size_t i;
size_t start_column = 0;
size_t cur_column;
@@ -799935,7 +800622,7 @@ Index: gcc/config/rs6000/rs6000.c
const char *comma = "";
if (indent)
-@@ -35067,27 +35644,45 @@
+@@ -35067,27 +35751,45 @@
cur_column = start_column;
for (i = 0; i < num_elements; i++)
{
@@ -800243,7 +800930,23 @@ Index: gcc/config/rs6000/rs6000.h
===================================================================
--- a/src/gcc/config/rs6000/rs6000.h (.../tags/gcc_6_1_0_release)
+++ b/src/gcc/config/rs6000/rs6000.h (.../branches/gcc-6-branch)
-@@ -615,6 +615,7 @@
+@@ -594,6 +594,15 @@
+ in the register. */
+ #define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP)
+
++/* ISA 3.0 has new min/max functions that don't need fast math that are being
++ phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct
++ answers if the arguments are not in the normal range. */
++#define TARGET_MINMAX_SF (TARGET_SF_FPR && TARGET_PPC_GFXOPT \
++ && (TARGET_P9_MINMAX || !flag_trapping_math))
++
++#define TARGET_MINMAX_DF (TARGET_DF_FPR && TARGET_PPC_GFXOPT \
++ && (TARGET_P9_MINMAX || !flag_trapping_math))
++
+ /* In switching from using target_flags to using rs6000_isa_flags, the options
+ machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map
+ OPTION_MASK_<xxx> back into MASK_<xxx>. */
+@@ -615,6 +624,7 @@
#define MASK_MULTIPLE OPTION_MASK_MULTIPLE
#define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE
#define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR
@@ -800251,7 +800954,7 @@ Index: gcc/config/rs6000/rs6000.h
#define MASK_POPCNTB OPTION_MASK_POPCNTB
#define MASK_POPCNTD OPTION_MASK_POPCNTD
#define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT
-@@ -655,6 +656,11 @@
+@@ -655,6 +665,11 @@
#define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE
#endif
@@ -800263,7 +800966,7 @@ Index: gcc/config/rs6000/rs6000.h
/* For power systems, we want to enable Altivec and VSX builtins even if the
user did not use -maltivec or -mvsx to allow the builtins to be used inside
of #pragma GCC target or the target attribute to change the code level for a
-@@ -2638,7 +2644,9 @@
+@@ -2638,7 +2653,9 @@
#define RS6000_BTC_MISC 0x00000000 /* No special attributes. */
#define RS6000_BTC_CONST 0x00000100 /* uses no global state. */
@@ -800274,7 +800977,7 @@ Index: gcc/config/rs6000/rs6000.h
#define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */
#define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */
-@@ -2660,6 +2668,7 @@
+@@ -2660,6 +2677,7 @@
#define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */
#define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */
#define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */
@@ -800282,7 +800985,7 @@ Index: gcc/config/rs6000/rs6000.h
#define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */
#define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */
#define RS6000_BTM_SPE MASK_STRING /* E500 */
-@@ -2673,10 +2682,12 @@
+@@ -2673,10 +2691,12 @@
#define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */
#define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */
#define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */
@@ -800295,7 +800998,7 @@ Index: gcc/config/rs6000/rs6000.h
| RS6000_BTM_CRYPTO \
| RS6000_BTM_FRE \
| RS6000_BTM_FRES \
-@@ -2691,6 +2702,7 @@
+@@ -2691,6 +2711,7 @@
/* Define builtin enum index. */
@@ -800303,7 +801006,7 @@ Index: gcc/config/rs6000/rs6000.h
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
-@@ -2703,6 +2715,7 @@
+@@ -2703,6 +2724,7 @@
#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
@@ -800311,7 +801014,7 @@ Index: gcc/config/rs6000/rs6000.h
#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
-@@ -2722,6 +2735,7 @@
+@@ -2722,6 +2744,7 @@
RS6000_BUILTIN_COUNT
};
@@ -800613,7 +801316,18 @@ Index: gcc/config/rs6000/rs6000.md
===================================================================
--- a/src/gcc/config/rs6000/rs6000.md (.../tags/gcc_6_1_0_release)
+++ b/src/gcc/config/rs6000/rs6000.md (.../branches/gcc-6-branch)
-@@ -577,7 +577,9 @@
+@@ -489,6 +489,10 @@
+ ; Iterator for just SF/DF
+ (define_mode_iterator SFDF [SF DF])
+
++; Like SFDF, but a different name to match conditional move where the
++; comparison operands may be a different mode than the input operands.
++(define_mode_iterator SFDF2 [SF DF])
++
+ ; Iterator for 128-bit floating point that uses the IBM double-double format
+ (define_mode_iterator IBM128 [(IF "FLOAT128_IBM_P (IFmode)")
+ (TF "FLOAT128_IBM_P (TFmode)")])
+@@ -577,7 +581,9 @@
(V16QI "b")
(V8HI "h")
(V4SI "w")
@@ -800624,7 +801338,277 @@ Index: gcc/config/rs6000/rs6000.md
;; How many bits in this mode?
(define_mode_attr bits [(QI "8") (HI "16") (SI "32") (DI "64")])
-@@ -12563,8 +12565,10 @@
+@@ -698,6 +704,15 @@
+ (define_mode_iterator RELOAD [V16QI V8HI V4SI V2DI V4SF V2DF V1TI
+ SF SD SI DF DD DI TI PTI KF IF TF])
+
++;; Iterate over smin, smax
++(define_code_iterator fp_minmax [smin smax])
++
++(define_code_attr minmax [(smin "min")
++ (smax "max")])
++
++(define_code_attr SMINMAX [(smin "SMIN")
++ (smax "SMAX")])
++
+
+ ;; Start with fixed-point load and store insns. Here we put only the more
+ ;; complex forms. Basic data transfer is done later.
+@@ -4599,74 +4614,45 @@
+ ;; On VSX, we only check for TARGET_VSX instead of checking for a vsx/p8 vector
+ ;; to allow either DF/SF to use only traditional registers.
+
+-(define_expand "smax<mode>3"
++(define_expand "s<minmax><mode>3"
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
+- (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
+- (match_operand:SFDF 2 "gpc_reg_operand" ""))
+- (match_dup 1)
+- (match_dup 2)))]
+- "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
++ (fp_minmax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
++ (match_operand:SFDF 2 "gpc_reg_operand" "")))]
++ "TARGET_MINMAX_<MODE>"
+ {
+- rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
++ rs6000_emit_minmax (operands[0], <SMINMAX>, operands[1], operands[2]);
+ DONE;
+ })
+
+-(define_insn "*smax<mode>3_vsx"
+- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
+- (smax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
+- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
+- "TARGET_<MODE>_FPR && TARGET_VSX"
+- "xsmaxdp %x0,%x1,%x2"
++(define_insn "*s<minmax><mode>3_vsx"
++ [(set (match_operand:SFDF 0 "vsx_register_operand" "=<Fv>")
++ (fp_minmax:SFDF (match_operand:SFDF 1 "vsx_register_operand" "<Fv>")
++ (match_operand:SFDF 2 "vsx_register_operand" "<Fv>")))]
++ "TARGET_VSX && TARGET_<MODE>_FPR"
++{
++ return (TARGET_P9_MINMAX
++ ? "xs<minmax>cdp %x0,%x1,%x2"
++ : "xs<minmax>dp %x0,%x1,%x2");
++}
+ [(set_attr "type" "fp")])
+
+-(define_expand "smin<mode>3"
+- [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
+- (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
+- (match_operand:SFDF 2 "gpc_reg_operand" ""))
+- (match_dup 2)
+- (match_dup 1)))]
+- "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
+-{
+- rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
+- DONE;
+-})
++;; The conditional move instructions allow us to perform max and min operations
++;; even when we don't have the appropriate max/min instruction using the FSEL
++;; instruction.
+
+-(define_insn "*smin<mode>3_vsx"
+- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
+- (smin:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
+- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
+- "TARGET_<MODE>_FPR && TARGET_VSX"
+- "xsmindp %x0,%x1,%x2"
+- [(set_attr "type" "fp")])
+-
+-(define_split
++(define_insn_and_split "*s<minmax><mode>3_fpr"
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
+- (match_operator:SFDF 3 "min_max_operator"
+- [(match_operand:SFDF 1 "gpc_reg_operand" "")
+- (match_operand:SFDF 2 "gpc_reg_operand" "")]))]
+- "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math
+- && !TARGET_VSX"
++ (fp_minmax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
++ (match_operand:SFDF 2 "gpc_reg_operand" "")))]
++ "!TARGET_VSX && TARGET_MINMAX_<MODE>"
++ "#"
++ "&& 1"
+ [(const_int 0)]
+ {
+- rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), operands[1],
+- operands[2]);
++ rs6000_emit_minmax (operands[0], <SMINMAX>, operands[1], operands[2]);
+ DONE;
+ })
+
+-(define_split
+- [(set (match_operand:SF 0 "gpc_reg_operand" "")
+- (match_operator:SF 3 "min_max_operator"
+- [(match_operand:SF 1 "gpc_reg_operand" "")
+- (match_operand:SF 2 "gpc_reg_operand" "")]))]
+- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
+- && TARGET_SINGLE_FLOAT && !flag_trapping_math"
+- [(const_int 0)]
+- "
+-{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
+- operands[1], operands[2]);
+- DONE;
+-}")
+-
+ (define_expand "mov<mode>cc"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "")
+ (if_then_else:GPR (match_operand 1 "comparison_operator" "")
+@@ -4749,12 +4735,13 @@
+ [(set_attr "type" "isel")
+ (set_attr "length" "4")])
+
+-(define_expand "movsfcc"
+- [(set (match_operand:SF 0 "gpc_reg_operand" "")
+- (if_then_else:SF (match_operand 1 "comparison_operator" "")
+- (match_operand:SF 2 "gpc_reg_operand" "")
+- (match_operand:SF 3 "gpc_reg_operand" "")))]
+- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
++;; Floating point conditional move
++(define_expand "mov<mode>cc"
++ [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
++ (if_then_else:SFDF (match_operand 1 "comparison_operator" "")
++ (match_operand:SFDF 2 "gpc_reg_operand" "")
++ (match_operand:SFDF 3 "gpc_reg_operand" "")))]
++ "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT"
+ "
+ {
+ if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
+@@ -4763,76 +4750,70 @@
+ FAIL;
+ }")
+
+-(define_insn "*fselsfsf4"
+- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+- (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
+- (match_operand:SF 4 "zero_fp_constant" "F"))
+- (match_operand:SF 2 "gpc_reg_operand" "f")
+- (match_operand:SF 3 "gpc_reg_operand" "f")))]
+- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
++(define_insn "*fsel<SFDF:mode><SFDF2:mode>4"
++ [(set (match_operand:SFDF 0 "fpr_reg_operand" "=&<SFDF:rreg2>")
++ (if_then_else:SFDF
++ (ge (match_operand:SFDF2 1 "fpr_reg_operand" "<SFDF2:rreg2>")
++ (match_operand:SFDF2 4 "zero_fp_constant" "F"))
++ (match_operand:SFDF 2 "fpr_reg_operand" "<SFDF:rreg2>")
++ (match_operand:SFDF 3 "fpr_reg_operand" "<SFDF:rreg2>")))]
++ "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT"
+ "fsel %0,%1,%2,%3"
+ [(set_attr "type" "fp")])
+
+-(define_insn "*fseldfsf4"
+- [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+- (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
+- (match_operand:DF 4 "zero_fp_constant" "F"))
+- (match_operand:SF 2 "gpc_reg_operand" "f")
+- (match_operand:SF 3 "gpc_reg_operand" "f")))]
+- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
+- "fsel %0,%1,%2,%3"
+- [(set_attr "type" "fp")])
++(define_insn_and_split "*mov<SFDF:mode><SFDF2:mode>cc_p9"
++ [(set (match_operand:SFDF 0 "vsx_register_operand" "=&<SFDF:Fv>,<SFDF:Fv>")
++ (if_then_else:SFDF
++ (match_operator:CCFP 1 "fpmask_comparison_operator"
++ [(match_operand:SFDF2 2 "vsx_register_operand" "<SFDF2:Fv>,<SFDF2:Fv>")
++ (match_operand:SFDF2 3 "vsx_register_operand" "<SFDF2:Fv>,<SFDF2:Fv>")])
++ (match_operand:SFDF 4 "vsx_register_operand" "<SFDF:Fv>,<SFDF:Fv>")
++ (match_operand:SFDF 5 "vsx_register_operand" "<SFDF:Fv>,<SFDF:Fv>")))
++ (clobber (match_scratch:V2DI 6 "=0,&wa"))]
++ "TARGET_P9_MINMAX"
++ "#"
++ ""
++ [(set (match_dup 6)
++ (if_then_else:V2DI (match_dup 1)
++ (match_dup 7)
++ (match_dup 8)))
++ (set (match_dup 0)
++ (if_then_else:SFDF (ne (match_dup 6)
++ (match_dup 8))
++ (match_dup 4)
++ (match_dup 5)))]
++{
++ if (GET_CODE (operands[6]) == SCRATCH)
++ operands[6] = gen_reg_rtx (V2DImode);
+
+-;; The conditional move instructions allow us to perform max and min
+-;; operations even when
++ operands[7] = CONSTM1_RTX (V2DImode);
++ operands[8] = CONST0_RTX (V2DImode);
++}
++ [(set_attr "length" "8")
++ (set_attr "type" "vecperm")])
+
+-(define_split
+- [(set (match_operand:DF 0 "gpc_reg_operand" "")
+- (match_operator:DF 3 "min_max_operator"
+- [(match_operand:DF 1 "gpc_reg_operand" "")
+- (match_operand:DF 2 "gpc_reg_operand" "")]))]
+- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
+- && !flag_trapping_math"
+- [(const_int 0)]
+- "
+-{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
+- operands[1], operands[2]);
+- DONE;
+-}")
++(define_insn "*fpmask<mode>"
++ [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa")
++ (if_then_else:V2DI
++ (match_operator:CCFP 1 "fpmask_comparison_operator"
++ [(match_operand:SFDF 2 "vsx_register_operand" "<Fv>")
++ (match_operand:SFDF 3 "vsx_register_operand" "<Fv>")])
++ (match_operand:V2DI 4 "all_ones_constant" "")
++ (match_operand:V2DI 5 "zero_constant" "")))]
++ "TARGET_P9_MINMAX"
++ "xscmp%V1dp %x0,%x2,%x3"
++ [(set_attr "type" "fpcompare")])
+
+-(define_expand "movdfcc"
+- [(set (match_operand:DF 0 "gpc_reg_operand" "")
+- (if_then_else:DF (match_operand 1 "comparison_operator" "")
+- (match_operand:DF 2 "gpc_reg_operand" "")
+- (match_operand:DF 3 "gpc_reg_operand" "")))]
+- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
+- "
+-{
+- if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
+- DONE;
+- else
+- FAIL;
+-}")
++(define_insn "*xxsel<mode>"
++ [(set (match_operand:SFDF 0 "vsx_register_operand" "=<Fv>")
++ (if_then_else:SFDF (ne (match_operand:V2DI 1 "vsx_register_operand" "wa")
++ (match_operand:V2DI 2 "zero_constant" ""))
++ (match_operand:SFDF 3 "vsx_register_operand" "<Fv>")
++ (match_operand:SFDF 4 "vsx_register_operand" "<Fv>")))]
++ "TARGET_P9_MINMAX"
++ "xxsel %x0,%x1,%x3,%x4"
++ [(set_attr "type" "vecperm")])
+
+-(define_insn "*fseldfdf4"
+- [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
+- (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
+- (match_operand:DF 4 "zero_fp_constant" "F"))
+- (match_operand:DF 2 "gpc_reg_operand" "d")
+- (match_operand:DF 3 "gpc_reg_operand" "d")))]
+- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
+- "fsel %0,%1,%2,%3"
+- [(set_attr "type" "fp")])
+-
+-(define_insn "*fselsfdf4"
+- [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
+- (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
+- (match_operand:SF 4 "zero_fp_constant" "F"))
+- (match_operand:DF 2 "gpc_reg_operand" "d")
+- (match_operand:DF 3 "gpc_reg_operand" "d")))]
+- "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
+- "fsel %0,%1,%2,%3"
+- [(set_attr "type" "fp")])
+
+ ;; Conversions to and from floating-point.
+
+@@ -12563,8 +12544,10 @@
(set_attr "indexed" "no")])
;; A return instruction which the middle-end doesn't see.
--
Alioth's /usr/local/bin/git-commit-notice on /srv/git.debian.org/git/reproducible/gcc-6.git
More information about the Reproducible-commits
mailing list