[gcc-6] 167/401: * Update to SVN 20160629 (r237851, 6.1.1) from the gcc-6-branch.
Ximin Luo
infinity0 at debian.org
Wed Apr 5 15:48:51 UTC 2017
This is an automated email from the git hooks/post-receive script.
infinity0 pushed a commit to branch pu/reproducible_builds
in repository gcc-6.
commit 70655ffc2fbbecd32480a06692c96737cff46fbf
Author: doko <doko at 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca>
Date: Wed Jun 29 13:46:13 2016 +0000
* Update to SVN 20160629 (r237851, 6.1.1) from the gcc-6-branch.
git-svn-id: svn://anonscm.debian.org/gcccvs/branches/sid/gcc-6@8898 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca
---
debian/changelog | 7 +-
debian/patches/svn-updates.diff | 2040 ++++++++++++++++++++++++++++++++++++---
2 files changed, 1920 insertions(+), 127 deletions(-)
diff --git a/debian/changelog b/debian/changelog
index 4e95a26..354724e 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,5 +1,10 @@
gcc-6 (6.1.1-8) UNRELEASED; urgency=medium
+ * Update to SVN 20160629 (r237851, 6.1.1) from the gcc-6-branch.
+ - Fix PR tree-optimization/71647, PR target/30417 (AVR),
+ PR target/71103 (AVR), PR tree-optimization/71588, PR middle-end/71581,
+ PR c++/71528, PR fortran/70673.
+
[ Aurelien Jarno ]
* Apply proposed patch from Matthew Fortune to fix libjava on mips64el.
@@ -7,7 +12,7 @@ gcc-6 (6.1.1-8) UNRELEASED; urgency=medium
* Add AArch64 Vulcan cpu support (Dann Frazier). LP: #1594452.
* gfortran: Suggest libcoarrays-dev. Closes: #827995.
- -- Matthias Klose <doko at debian.org> Fri, 24 Jun 2016 14:18:56 +0200
+ -- Matthias Klose <doko at debian.org> Wed, 29 Jun 2016 15:14:24 +0200
gcc-6 (6.1.1-7) unstable; urgency=medium
diff --git a/debian/patches/svn-updates.diff b/debian/patches/svn-updates.diff
index 612c37f..14a6519 100644
--- a/debian/patches/svn-updates.diff
+++ b/debian/patches/svn-updates.diff
@@ -1,10 +1,10 @@
-# DP: updates from the 6 branch upto 20160620 (r237590).
+# DP: updates from the 6 branch upto 20160629 (r237851).
last_update()
{
cat > ${dir}LAST_UPDATED <EOF
-Mon Jun 20 13:16:32 CEST 2016
-Mon Jun 20 11:16:32 UTC 2016 (revision 237590)
+Wed Jun 29 15:12:54 CEST 2016
+Wed Jun 29 13:12:54 UTC 2016 (revision 237851)
EOF
}
@@ -16,7 +16,18 @@ Index: libgomp/ChangeLog
===================================================================
--- a/src/libgomp/ChangeLog (.../tags/gcc_6_1_0_release)
+++ b/src/libgomp/ChangeLog (.../branches/gcc-6-branch)
-@@ -1,3 +1,46 @@
+@@ -1,3 +1,57 @@
++2016-06-21 Jakub Jelinek <jakub at redhat.com>
++
++ Backported from mainline
++ 2016-06-17 Jakub Jelinek <jakub at redhat.com>
++
++ * testsuite/libgomp.c++/target-21.C: New test.
++
++ 2016-06-16 Jakub Jelinek <jakub at redhat.com>
++
++ * testsuite/libgomp.c++/target-20.C: New test.
++
+2016-06-10 Thomas Schwinge <thomas at codesourcery.com>
+
+ PR middle-end/71373
@@ -63,6 +74,269 @@ Index: libgomp/ChangeLog
2016-04-27 Release Manager
* GCC 6.1.0 released.
+Index: libgomp/testsuite/libgomp.c++/target-20.C
+===================================================================
+--- a/src/libgomp/testsuite/libgomp.c++/target-20.C (.../tags/gcc_6_1_0_release)
++++ b/src/libgomp/testsuite/libgomp.c++/target-20.C (.../branches/gcc-6-branch)
+@@ -0,0 +1,80 @@
++extern "C" void abort ();
++struct S { int a, b, c, d; };
++
++void
++foo (S &s)
++{
++ int err;
++ #pragma omp target map (s.b, s.d) map (from: err)
++ {
++ err = s.b != 21 || s.d != 24;
++ s.b++; s.d++;
++ }
++ if (err || s.b != 22 || s.d != 25)
++ abort ();
++ #pragma omp target data map (s.b, s.d)
++ {
++ #pragma omp target map (alloc: s.b, s.d) map (from: err)
++ {
++ err = s.b != 22 || s.d != 25;
++ s.b++; s.d++;
++ }
++ }
++ if (err || s.b != 23 || s.d != 26)
++ abort ();
++ #pragma omp target data map (s)
++ {
++ #pragma omp target map (alloc: s.b, s.d) map (from: err)
++ {
++ err = s.b != 23 || s.d != 26;
++ s.b++; s.d++;
++ }
++ }
++ if (err || s.b != 24 || s.d != 27)
++ abort ();
++}
++
++template <typename T, typename U>
++void
++bar (S &s, T &t, U u)
++{
++ int err;
++ #pragma omp target map (s.b, s.d, t.b, t.d, u.b, u.d) map (from: err)
++ {
++ err = s.b != 21 || s.d != 24 || t.b != 73 || t.d != 82 || u.b != 31 || u.d != 37;
++ s.b++; s.d++; t.b++; t.d++; u.b++; u.d++;
++ }
++ if (err || s.b != 22 || s.d != 25 || t.b != 74 || t.d != 83 || u.b != 32 || u.d != 38)
++ abort ();
++ #pragma omp target data map (s.b, s.d, t.b, t.d, u.b, u.d)
++ {
++ #pragma omp target map (alloc: s.b, s.d, t.b, t.d, u.b, u.d) map (from: err)
++ {
++ err = s.b != 22 || s.d != 25 || t.b != 74 || t.d != 83 || u.b != 32 || u.d != 38;
++ s.b++; s.d++; t.b++; t.d++; u.b++; u.d++;
++ }
++ }
++ if (err || s.b != 23 || s.d != 26 || t.b != 75 || t.d != 84 || u.b != 33 || u.d != 39)
++ abort ();
++ #pragma omp target data map (s, t, u)
++ {
++ #pragma omp target map (alloc: s.b, s.d, t.b, t.d, u.b, u.d) map (from: err)
++ {
++ err = s.b != 23 || s.d != 26 || t.b != 75 || t.d != 84 || u.b != 33 || u.d != 39;
++ s.b++; s.d++; t.b++; t.d++; u.b++; u.d++;
++ }
++ }
++ if (err || s.b != 24 || s.d != 27 || t.b != 76 || t.d != 85 || u.b != 34 || u.d != 40)
++ abort ();
++}
++
++int
++main ()
++{
++ S s = { 1, 21, 2, 24 };
++ foo (s);
++ S s2 = { 3, 21, 4, 24 };
++ S t = { 5, 73, 6, 82 };
++ S u = { 7, 31, 8, 37 };
++ bar <S, S &> (s2, t, u);
++}
+Index: libgomp/testsuite/libgomp.c++/target-21.C
+===================================================================
+--- a/src/libgomp/testsuite/libgomp.c++/target-21.C (.../tags/gcc_6_1_0_release)
++++ b/src/libgomp/testsuite/libgomp.c++/target-21.C (.../branches/gcc-6-branch)
+@@ -0,0 +1,173 @@
++extern "C" void abort ();
++struct T { char t[270]; };
++struct S { int (&x)[10]; int *&y; T t; int &z; S (); ~S (); };
++
++template <int N>
++void
++foo (S s)
++{
++ int err;
++ #pragma omp target map (s.x[0:N], s.y[0:N]) map (s.t.t[16:3]) map (from: err)
++ {
++ err = s.x[2] != 28 || s.y[2] != 37 || s.t.t[17] != 81;
++ s.x[2]++;
++ s.y[2]++;
++ s.t.t[17]++;
++ }
++ if (err || s.x[2] != 29 || s.y[2] != 38 || s.t.t[17] != 82)
++ abort ();
++}
++
++template <int N>
++void
++bar (S s)
++{
++ int err;
++ #pragma omp target map (s.x, s.z)map(from:err)
++ {
++ err = s.x[2] != 29 || s.z != 6;
++ s.x[2]++;
++ s.z++;
++ }
++ if (err || s.x[2] != 30 || s.z != 7)
++ abort ();
++}
++
++template <int N>
++void
++foo2 (S &s)
++{
++ int err;
++ #pragma omp target map (s.x[N:10], s.y[N:10]) map (from: err) map (s.t.t[N+16:N+3])
++ {
++ err = s.x[2] != 30 || s.y[2] != 38 || s.t.t[17] != 81;
++ s.x[2]++;
++ s.y[2]++;
++ s.t.t[17]++;
++ }
++ if (err || s.x[2] != 31 || s.y[2] != 39 || s.t.t[17] != 82)
++ abort ();
++}
++
++template <int N>
++void
++bar2 (S &s)
++{
++ int err;
++ #pragma omp target map (s.x, s.z)map(from:err)
++ {
++ err = s.x[2] != 31 || s.z != 7;
++ s.x[2]++;
++ s.z++;
++ }
++ if (err || s.x[2] != 32 || s.z != 8)
++ abort ();
++}
++
++template <typename U>
++void
++foo3 (U s)
++{
++ int err;
++ #pragma omp target map (s.x[0:10], s.y[0:10]) map (from: err) map (s.t.t[16:3])
++ {
++ err = s.x[2] != 32 || s.y[2] != 39 || s.t.t[17] != 82;
++ s.x[2]++;
++ s.y[2]++;
++ s.t.t[17]++;
++ }
++ if (err || s.x[2] != 33 || s.y[2] != 40 || s.t.t[17] != 83)
++ abort ();
++}
++
++template <typename U>
++void
++bar3 (U s)
++{
++ int err;
++ #pragma omp target map (s.x, s.z)map(from:err)
++ {
++ err = s.x[2] != 33 || s.z != 8;
++ s.x[2]++;
++ s.z++;
++ }
++ if (err || s.x[2] != 34 || s.z != 9)
++ abort ();
++}
++
++template <typename U>
++void
++foo4 (U &s)
++{
++ int err;
++ #pragma omp target map (s.x[0:10], s.y[0:10]) map (from: err) map (s.t.t[16:3])
++ {
++ err = s.x[2] != 34 || s.y[2] != 40 || s.t.t[17] != 82;
++ s.x[2]++;
++ s.y[2]++;
++ s.t.t[17]++;
++ }
++ if (err || s.x[2] != 35 || s.y[2] != 41 || s.t.t[17] != 83)
++ abort ();
++}
++
++template <typename U>
++void
++bar4 (U &s)
++{
++ int err;
++ #pragma omp target map (s.x, s.z)map(from:err)
++ {
++ err = s.x[2] != 35 || s.z != 9;
++ s.x[2]++;
++ s.z++;
++ }
++ if (err || s.x[2] != 36 || s.z != 10)
++ abort ();
++}
++
++int xt[10] = { 1, 2, 28, 3, 4, 5, 6, 7, 8, 9 };
++int yt[10] = { 1, 2, 37, 3, 4, 5, 6, 7, 8, 9 };
++int *yp = yt;
++int zt = 6;
++
++S::S () : x (xt), y (yp), z (zt)
++{
++}
++
++S::~S ()
++{
++}
++
++int
++main ()
++{
++ S s;
++ s.t.t[16] = 5;
++ s.t.t[17] = 81;
++ s.t.t[18] = 9;
++ foo <10> (s);
++ if (s.t.t[17] != 81)
++ abort ();
++ bar <7> (s);
++ foo2 <0> (s);
++ if (s.t.t[17] != 82)
++ abort ();
++ bar2 <21> (s);
++ foo3 <S> (s);
++ if (s.t.t[17] != 82)
++ abort ();
++ bar3 <S> (s);
++ foo4 <S> (s);
++ if (s.t.t[17] != 83)
++ abort ();
++ bar4 <S> (s);
++ s.x[2] -= 4;
++ s.y[2] -= 2;
++ s.z -= 2;
++ s.t.t[17]--;
++ foo3 <S &> (s);
++ if (s.t.t[17] != 83)
++ abort ();
++ bar3 <S &> (s);
++}
Index: libgomp/testsuite/libgomp.oacc-c++/template-reduction.C
===================================================================
--- a/src/libgomp/testsuite/libgomp.oacc-c++/template-reduction.C (.../tags/gcc_6_1_0_release)
@@ -4065,6 +4339,21 @@ Index: gcc/tree-ssa-tail-merge.c
if (e1->hashval != e2->hashval)
return 0;
+Index: gcc/machmode.h
+===================================================================
+--- a/src/gcc/machmode.h (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/machmode.h (.../branches/gcc-6-branch)
+@@ -269,6 +269,10 @@
+ extern const unsigned char mode_2xwider[NUM_MACHINE_MODES];
+ #define GET_MODE_2XWIDER_MODE(MODE) ((machine_mode) mode_2xwider[MODE])
+
++/* Get the complex mode from the component mode. */
++extern const unsigned char mode_complex[NUM_MACHINE_MODES];
++#define GET_MODE_COMPLEX_MODE(MODE) ((machine_mode) mode_complex[MODE])
++
+ /* Return the mode for data of a given size SIZE and mode class CLASS.
+ If LIMIT is nonzero, then don't use modes bigger than MAX_FIXED_MODE_SIZE.
+ The value is BLKmode if no other mode is found. */
Index: gcc/tree-chkp.c
===================================================================
--- a/src/gcc/tree-chkp.c (.../tags/gcc_6_1_0_release)
@@ -4106,6 +4395,40 @@ Index: gcc/tree-chkp.c
bounds = chkp_make_addressed_object_bounds (TREE_OPERAND (ptr_src, 0), iter);
break;
+Index: gcc/tree-ssa-uninit.c
+===================================================================
+--- a/src/gcc/tree-ssa-uninit.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/tree-ssa-uninit.c (.../branches/gcc-6-branch)
+@@ -133,6 +133,29 @@
+ if (!has_undefined_value_p (t))
+ return;
+
++ /* Anonymous SSA_NAMEs shouldn't be uninitialized, but ssa_undefined_value_p
++ can return true if the def stmt of anonymous SSA_NAME is COMPLEX_EXPR
++ created for conversion from scalar to complex. Use the underlying var of
++ the COMPLEX_EXPRs real part in that case. See PR71581. */
++ if (expr == NULL_TREE
++ && var == NULL_TREE
++ && SSA_NAME_VAR (t) == NULL_TREE
++ && is_gimple_assign (SSA_NAME_DEF_STMT (t))
++ && gimple_assign_rhs_code (SSA_NAME_DEF_STMT (t)) == COMPLEX_EXPR)
++ {
++ tree v = gimple_assign_rhs1 (SSA_NAME_DEF_STMT (t));
++ if (TREE_CODE (v) == SSA_NAME
++ && has_undefined_value_p (v)
++ && zerop (gimple_assign_rhs2 (SSA_NAME_DEF_STMT (t))))
++ {
++ expr = SSA_NAME_VAR (v);
++ var = expr;
++ }
++ }
++
++ if (expr == NULL_TREE)
++ return;
++
+ /* TREE_NO_WARNING either means we already warned, or the front end
+ wishes to suppress the warning. */
+ if ((context
Index: gcc/graphite-isl-ast-to-gimple.c
===================================================================
--- a/src/gcc/graphite-isl-ast-to-gimple.c (.../tags/gcc_6_1_0_release)
@@ -4898,7 +5221,104 @@ Index: gcc/DATESTAMP
+++ b/src/gcc/DATESTAMP (.../branches/gcc-6-branch)
@@ -1 +1 @@
-20160427
-+20160620
++20160629
+Index: gcc/tree-ssa-strlen.c
+===================================================================
+--- a/src/gcc/tree-ssa-strlen.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/tree-ssa-strlen.c (.../branches/gcc-6-branch)
+@@ -859,6 +859,65 @@
+ }
+ }
+
++/* Return true if STMT is a call to a builtin function with the right
++ arguments and attributes that should be considered for optimization
++ by this pass. */
++
++static bool
++valid_builtin_call (gimple *stmt)
++{
++ if (!gimple_call_builtin_p (stmt, BUILT_IN_NORMAL))
++ return false;
++
++ tree callee = gimple_call_fndecl (stmt);
++ switch (DECL_FUNCTION_CODE (callee))
++ {
++ case BUILT_IN_MEMCMP:
++ case BUILT_IN_STRCHR:
++ case BUILT_IN_STRCHR_CHKP:
++ case BUILT_IN_STRLEN:
++ case BUILT_IN_STRLEN_CHKP:
++ /* The above functions should be pure. Punt if they aren't. */
++ if (gimple_vdef (stmt) || gimple_vuse (stmt) == NULL_TREE)
++ return false;
++ break;
++
++ case BUILT_IN_CALLOC:
++ case BUILT_IN_MALLOC:
++ case BUILT_IN_MEMCPY:
++ case BUILT_IN_MEMCPY_CHK:
++ case BUILT_IN_MEMCPY_CHKP:
++ case BUILT_IN_MEMCPY_CHK_CHKP:
++ case BUILT_IN_MEMPCPY:
++ case BUILT_IN_MEMPCPY_CHK:
++ case BUILT_IN_MEMPCPY_CHKP:
++ case BUILT_IN_MEMPCPY_CHK_CHKP:
++ case BUILT_IN_MEMSET:
++ case BUILT_IN_STPCPY:
++ case BUILT_IN_STPCPY_CHK:
++ case BUILT_IN_STPCPY_CHKP:
++ case BUILT_IN_STPCPY_CHK_CHKP:
++ case BUILT_IN_STRCAT:
++ case BUILT_IN_STRCAT_CHK:
++ case BUILT_IN_STRCAT_CHKP:
++ case BUILT_IN_STRCAT_CHK_CHKP:
++ case BUILT_IN_STRCPY:
++ case BUILT_IN_STRCPY_CHK:
++ case BUILT_IN_STRCPY_CHKP:
++ case BUILT_IN_STRCPY_CHK_CHKP:
++ /* The above functions should be neither const nor pure. Punt if they
++ aren't. */
++ if (gimple_vdef (stmt) == NULL_TREE || gimple_vuse (stmt) == NULL_TREE)
++ return false;
++ break;
++
++ default:
++ break;
++ }
++
++ return true;
++}
++
+ /* If the last .MEM setter statement before STMT is
+ memcpy (x, y, strlen (y) + 1), the only .MEM use of it is STMT
+ and STMT is known to overwrite x[strlen (x)], adjust the last memcpy to
+@@ -934,7 +993,7 @@
+ return;
+ }
+
+- if (!gimple_call_builtin_p (last.stmt, BUILT_IN_NORMAL))
++ if (!valid_builtin_call (last.stmt))
+ return;
+
+ callee = gimple_call_fndecl (last.stmt);
+@@ -1810,7 +1869,7 @@
+ if (!stmt1 || !is_gimple_call (stmt1))
+ return true;
+ tree callee1 = gimple_call_fndecl (stmt1);
+- if (!gimple_call_builtin_p (stmt1, BUILT_IN_NORMAL))
++ if (!valid_builtin_call (stmt1))
+ return true;
+ enum built_in_function code1 = DECL_FUNCTION_CODE (callee1);
+ tree size = gimple_call_arg (stmt2, 2);
+@@ -2055,7 +2114,7 @@
+ if (is_gimple_call (stmt))
+ {
+ tree callee = gimple_call_fndecl (stmt);
+- if (gimple_call_builtin_p (stmt, BUILT_IN_NORMAL))
++ if (valid_builtin_call (stmt))
+ switch (DECL_FUNCTION_CODE (callee))
+ {
+ case BUILT_IN_STRLEN:
Index: gcc/tree.h
===================================================================
--- a/src/gcc/tree.h (.../tags/gcc_6_1_0_release)
@@ -5268,7 +5688,31 @@ Index: gcc/omp-low.c
default:
gcc_unreachable ();
}
-@@ -13680,6 +13674,9 @@
+@@ -4481,8 +4475,9 @@
+ if (new_var == NULL_TREE)
+ new_var = maybe_lookup_decl_in_outer_ctx (var, ctx);
+ x = builtin_decl_explicit (BUILT_IN_ASSUME_ALIGNED);
+- x = build_call_expr_loc (clause_loc, x, 2, new_var,
+- omp_clause_aligned_alignment (c));
++ tree alarg = omp_clause_aligned_alignment (c);
++ alarg = fold_convert_loc (clause_loc, size_type_node, alarg);
++ x = build_call_expr_loc (clause_loc, x, 2, new_var, alarg);
+ x = fold_convert_loc (clause_loc, TREE_TYPE (new_var), x);
+ x = build2 (MODIFY_EXPR, TREE_TYPE (new_var), new_var, x);
+ gimplify_and_add (x, ilist);
+@@ -4495,8 +4490,9 @@
+ t = maybe_lookup_decl_in_outer_ctx (var, ctx);
+ t = build_fold_addr_expr_loc (clause_loc, t);
+ t2 = builtin_decl_explicit (BUILT_IN_ASSUME_ALIGNED);
+- t = build_call_expr_loc (clause_loc, t2, 2, t,
+- omp_clause_aligned_alignment (c));
++ tree alarg = omp_clause_aligned_alignment (c);
++ alarg = fold_convert_loc (clause_loc, size_type_node, alarg);
++ t = build_call_expr_loc (clause_loc, t2, 2, t, alarg);
+ t = fold_convert_loc (clause_loc, ptype, t);
+ x = create_tmp_var (ptype);
+ t = build2 (MODIFY_EXPR, ptype, x, t);
+@@ -13680,6 +13676,9 @@
tree new_parm_decl = copy_node (DECL_ARGUMENTS (kern_fndecl));
DECL_CONTEXT (new_parm_decl) = kern_fndecl;
DECL_ARGUMENTS (kern_fndecl) = new_parm_decl;
@@ -5309,7 +5753,106 @@ Index: gcc/ChangeLog
===================================================================
--- a/src/gcc/ChangeLog (.../tags/gcc_6_1_0_release)
+++ b/src/gcc/ChangeLog (.../branches/gcc-6-branch)
-@@ -1,3 +1,1212 @@
+@@ -1,3 +1,1311 @@
++2016-06-27 Michael Meissner <meissner at linux.vnet.ibm.com>
++
++ Back port from trunk
++ 2016-06-21 Michael Meissner <meissner at linux.vnet.ibm.com>
++
++ * stor-layout.c (layout_type): Move setting complex MODE to
++ layout_type, instead of setting it ahead of time by the caller.
++
++ Back port from trunk
++ 2016-05-11 Alan Modra <amodra at gmail.com>
++
++ * config/rs6000/rs6000.c (is_complex_IBM_long_double,
++ abi_v4_pass_in_fpr): New functions.
++ (rs6000_function_arg_boundary): Exclude complex IBM long double
++ from 64-bit alignment when ABI_V4.
++ (rs6000_function_arg, rs6000_function_arg_advance_1,
++ rs6000_gimplify_va_arg): Use abi_v4_pass_in_fpr.
++
++ Back port from trunk
++ 2016-05-02 Michael Meissner <meissner at linux.vnet.ibm.com>
++
++ * machmode.h (mode_complex): Add support to give the complex mode
++ for a given mode.
++ (GET_MODE_COMPLEX_MODE): Likewise.
++ * stor-layout.c (layout_type): For COMPLEX_TYPE, use the mode
++ stored by build_complex_type and gfc_build_complex_type instead of
++ trying to figure out the appropriate mode based on the size. Raise
++ an assertion error, if the type was not set.
++ * genmodes.c (struct mode_data): Add field for the complex type of
++ the given type.
++ (blank_mode): Likewise.
++ (make_complex_modes): Remember the complex mode created in the
++ base type.
++ (emit_mode_complex): Write out the mode_complex array to map a
++ type mode to the complex version.
++ (emit_insn_modes_c): Likewise.
++ * tree.c (build_complex_type): Set the complex type to use before
++ calling layout_type.
++ * config/rs6000/rs6000.c (rs6000_hard_regno_nregs_internal): Add
++ support for __float128 complex datatypes.
++ (rs6000_hard_regno_mode_ok): Likewise.
++ (rs6000_setup_reg_addr_masks): Likewise.
++ (rs6000_complex_function_value): Likewise.
++ * config/rs6000/rs6000.h (FLOAT128_IEEE_P): Likewise.
++ __float128 and __ibm128 complex.
++ (FLOAT128_IBM_P): Likewise.
++ (ALTIVEC_ARG_MAX_RETURN): Likewise.
++ * doc/extend.texi (Additional Floating Types): Document that
++ -mfloat128 must be used to enable __float128. Document complex
++ __float128 and __ibm128 support.
++
++2016-06-24 Jakub Jelinek <jakub at redhat.com>
++
++ PR tree-optimization/71647
++ * omp-low.c (lower_rec_input_clauses): Convert
++ omp_clause_aligned_alignment (c) to size_type_node for the
++ last argument of __builtin_assume_aligned.
++
++2016-06-22 Eric Botcazou <ebotcazou at adacore.com>
++
++ * function.c (assign_parm_setup_reg): Prevent sharing in another case.
++
++2016-06-21 Georg-Johann Lay <avr at gjlay.de>
++
++ Backport from 2016-06-21 trunk r237639.
++
++ PR target/30417
++ * config/avr/gen-avr-mmcu-specs.c (print_mcu):
++ [*link_data_start]: Wrap -Tdata into %{!Tdata:...}.
++ [*link_text_start]: Wrap -Ttext into %{!Ttext:...}.
++
++2016-06-21 Georg-Johann Lay <avr at gjlay.de>
++
++ PR target/71103
++ * config/avr/avr.md (movqi): Only handle loading subreg:qi of
++ constant addresses if can_create_pseudo_p.
++
++2016-06-21 Jakub Jelinek <jakub at redhat.com>
++
++ PR tree-optimization/71588
++ * tree-ssa-strlen.c (valid_builtin_call): New function.
++ (adjust_last_stmt, handle_builtin_memset, strlen_optimize_stmt): Use
++ it.
++
++ Backported from mainline
++ 2016-06-20 Jakub Jelinek <jakub at redhat.com>
++
++ PR middle-end/71581
++ * tree-ssa-uninit.c (warn_uninit): If EXPR and VAR are NULL,
++ see if T isn't anonymous SSA_NAME with COMPLEX_EXPR created
++ for conversion of scalar user var to complex type and use the
++ underlying SSA_NAME_VAR in that case. If EXPR is still NULL,
++ punt.
++
++ 2016-06-16 Jakub Jelinek <jakub at redhat.com>
++
++ * gimplify.c (gimplify_scan_omp_clauses): Handle COMPONENT_REFs
++ with base of reference to struct.
++
+2016-06-20 Ilya Enkovich <ilya.enkovich at intel.com>
+
+ Backport from mainline r237484.
@@ -6522,7 +7065,7 @@ Index: gcc/ChangeLog
2016-04-27 Release Manager
* GCC 6.1.0 released.
-@@ -49,7 +1258,7 @@
+@@ -49,7 +1357,7 @@
constant boolean.
2016-04-20 Andrew Pinski <apinski at cavium.com>
@@ -7675,6 +8218,333 @@ Index: gcc/testsuite/gcc.target/powerpc/pr71186.c
+
+ return 0;
+}
+Index: gcc/testsuite/gcc.target/powerpc/float128-complex-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/float128-complex-1.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/float128-complex-1.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,157 @@
++/* { dg-do compile { target { powerpc*-*-linux* } } } */
++/* { dg-require-effective-target powerpc_float128_sw_ok } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
++/* { dg-options "-O2 -mcpu=power7 -mfloat128" } */
++
++#ifndef NO_FLOAT
++typedef _Complex float float_complex;
++extern float_complex cfloat1 (void);
++extern float_complex cfloat2 (void);
++
++#define FLOAT_ARG(NAME, OP) ARG_OP(float, float_complex, NAME, OP)
++#define FLOAT_PTR(NAME, OP) PTR_OP(float, float_complex, NAME, OP)
++#define FLOAT_CALL() CALL_OP(float, float_complex, cfloat1, cfloat2)
++
++#else
++#define FLOAT_ARG(NAME, OP)
++#define FLOAT_PTR(NAME, OP)
++#define FLOAT_CALL()
++#endif
++
++#ifndef NO_DOUBLE
++typedef _Complex double double_complex;
++extern double_complex cdouble1 (void);
++extern double_complex cdouble2 (void);
++
++#define DOUBLE_ARG(NAME, OP) ARG_OP(double, double_complex, NAME, OP)
++#define DOUBLE_PTR(NAME, OP) PTR_OP(double, double_complex, NAME, OP)
++#define DOUBLE_CALL() CALL_OP(double, double_complex, cdouble1, cdouble2)
++
++#else
++#define DOUBLE_ARG(NAME, OP)
++#define DOUBLE_PTR(NAME, OP)
++#define DOUBLE_CALL()
++#endif
++
++#ifndef NO_FLOAT128
++#ifdef __VSX__
++typedef _Complex float __attribute__((mode(KC))) float128_complex;
++#else
++typedef _Complex float __attribute__((mode(TC))) float128_complex;
++#endif
++
++extern float128_complex cfloat128_1 (void);
++extern float128_complex cfloat128_2 (void);
++
++#define FLOAT128_ARG(NAME, OP) ARG_OP(float128, float128_complex, NAME, OP)
++#define FLOAT128_PTR(NAME, OP) PTR_OP(float128, float128_complex, NAME, OP)
++#define FLOAT128_CALL() CALL_OP(float128, float128_complex, cfloat128_1, cfloat128_2)
++
++#else
++#define FLOAT128_ARG(NAME, OP)
++#define FLOAT128_PTR(NAME, OP)
++#define FLOAT128_CALL()
++#endif
++
++#ifndef NO_LDOUBLE
++typedef _Complex long double ldouble_complex;
++extern ldouble_complex cldouble1 (void);
++extern ldouble_complex cldouble2 (void);
++
++#define LDOUBLE_ARG(NAME, OP) ARG_OP(ldouble, ldouble_complex, NAME, OP)
++#define LDOUBLE_PTR(NAME, OP) PTR_OP(ldouble, ldouble_complex, NAME, OP)
++#define LDOUBLE_CALL() CALL_OP(ldouble, ldouble_complex, cldouble1, cldouble2)
++
++#else
++#define LDOUBLE_ARG(NAME, OP)
++#define LDOUBLE_PTR(NAME, OP)
++#define LDOUBLE_CALL()
++#endif
++
++
++#define ARG_OP(SUFFIX, TYPE, NAME, OP) \
++TYPE arg_ ## NAME ## _ ## SUFFIX (TYPE a, TYPE b) \
++{ \
++ return a OP b; \
++}
++
++#define PTR_OP(SUFFIX, TYPE, NAME, OP) \
++void ptr_ ## NAME ## _ ## SUFFIX (TYPE *p, TYPE *a, TYPE *b) \
++{ \
++ *p = *a OP *b; \
++}
++
++#define CALL_OP(SUFFIX, TYPE, FUNC1, FUNC2) \
++TYPE call_ ## SUFFIX (void) \
++{ \
++ TYPE value1 = FUNC1 (); \
++ TYPE value2 = FUNC2 (); \
++ return value1 + value2; \
++}
++
++#ifndef NO_ARG
++#ifndef NO_ADD
++FLOAT_ARG (add, +)
++DOUBLE_ARG (add, +)
++FLOAT128_ARG (add, +)
++LDOUBLE_ARG (add, +)
++#endif
++
++#ifndef NO_SUB
++FLOAT_ARG (sub, -)
++DOUBLE_ARG (sub, -)
++FLOAT128_ARG (sub, -)
++LDOUBLE_ARG (sub, -)
++#endif
++
++#ifndef NO_MUL
++FLOAT_ARG (mul, *)
++DOUBLE_ARG (mul, *)
++FLOAT128_ARG (mul, *)
++LDOUBLE_ARG (mul, *)
++#endif
++
++#ifndef NO_DIV
++FLOAT_ARG (div, /)
++DOUBLE_ARG (div, /)
++FLOAT128_ARG (div, /)
++LDOUBLE_ARG (div, /)
++#endif
++#endif
++
++#ifndef NO_PTR
++#ifndef NO_ADD
++FLOAT_PTR (add, +)
++DOUBLE_PTR (add, +)
++FLOAT128_PTR (add, +)
++LDOUBLE_PTR (add, +)
++#endif
++
++#ifndef NO_SUB
++FLOAT_PTR (sub, -)
++DOUBLE_PTR (sub, -)
++FLOAT128_PTR (sub, -)
++LDOUBLE_PTR (sub, -)
++#endif
++
++#ifndef NO_MUL
++FLOAT_PTR (mul, *)
++DOUBLE_PTR (mul, *)
++FLOAT128_PTR (mul, *)
++LDOUBLE_PTR (mul, *)
++#endif
++
++#ifndef NO_DIV
++FLOAT_PTR (div, /)
++DOUBLE_PTR (div, /)
++FLOAT128_PTR (div, /)
++LDOUBLE_PTR (div, /)
++#endif
++#endif
++
++#ifndef NO_CALL
++FLOAT_CALL ()
++DOUBLE_CALL ()
++FLOAT128_CALL ()
++LDOUBLE_CALL ()
++#endif
+Index: gcc/testsuite/gcc.target/powerpc/float128-complex-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/float128-complex-2.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/float128-complex-2.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,160 @@
++/* { dg-do compile { target { powerpc*-*-linux* } } } */
++/* { dg-require-effective-target powerpc_float128_hw_ok } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-options "-O2 -mcpu=power9 -mfloat128 -mfloat128-hardware" } */
++
++#ifndef NO_FLOAT
++typedef _Complex float float_complex;
++extern float_complex cfloat1 (void);
++extern float_complex cfloat2 (void);
++
++#define FLOAT_ARG(NAME, OP) ARG_OP(float, float_complex, NAME, OP)
++#define FLOAT_PTR(NAME, OP) PTR_OP(float, float_complex, NAME, OP)
++#define FLOAT_CALL() CALL_OP(float, float_complex, cfloat1, cfloat2)
++
++#else
++#define FLOAT_ARG(NAME, OP)
++#define FLOAT_PTR(NAME, OP)
++#define FLOAT_CALL()
++#endif
++
++#ifndef NO_DOUBLE
++typedef _Complex double double_complex;
++extern double_complex cdouble1 (void);
++extern double_complex cdouble2 (void);
++
++#define DOUBLE_ARG(NAME, OP) ARG_OP(double, double_complex, NAME, OP)
++#define DOUBLE_PTR(NAME, OP) PTR_OP(double, double_complex, NAME, OP)
++#define DOUBLE_CALL() CALL_OP(double, double_complex, cdouble1, cdouble2)
++
++#else
++#define DOUBLE_ARG(NAME, OP)
++#define DOUBLE_PTR(NAME, OP)
++#define DOUBLE_CALL()
++#endif
++
++#ifndef NO_FLOAT128
++#ifdef __VSX__
++typedef _Complex float __attribute__((mode(KC))) float128_complex;
++#else
++typedef _Complex float __attribute__((mode(TC))) float128_complex;
++#endif
++
++extern float128_complex cfloat128_1 (void);
++extern float128_complex cfloat128_2 (void);
++
++#define FLOAT128_ARG(NAME, OP) ARG_OP(float128, float128_complex, NAME, OP)
++#define FLOAT128_PTR(NAME, OP) PTR_OP(float128, float128_complex, NAME, OP)
++#define FLOAT128_CALL() CALL_OP(float128, float128_complex, cfloat128_1, cfloat128_2)
++
++#else
++#define FLOAT128_ARG(NAME, OP)
++#define FLOAT128_PTR(NAME, OP)
++#define FLOAT128_CALL()
++#endif
++
++#ifndef NO_LDOUBLE
++typedef _Complex long double ldouble_complex;
++extern ldouble_complex cldouble1 (void);
++extern ldouble_complex cldouble2 (void);
++
++#define LDOUBLE_ARG(NAME, OP) ARG_OP(ldouble, ldouble_complex, NAME, OP)
++#define LDOUBLE_PTR(NAME, OP) PTR_OP(ldouble, ldouble_complex, NAME, OP)
++#define LDOUBLE_CALL() CALL_OP(ldouble, ldouble_complex, cldouble1, cldouble2)
++
++#else
++#define LDOUBLE_ARG(NAME, OP)
++#define LDOUBLE_PTR(NAME, OP)
++#define LDOUBLE_CALL()
++#endif
++
++
++#define ARG_OP(SUFFIX, TYPE, NAME, OP) \
++TYPE arg_ ## NAME ## _ ## SUFFIX (TYPE a, TYPE b) \
++{ \
++ return a OP b; \
++}
++
++#define PTR_OP(SUFFIX, TYPE, NAME, OP) \
++void ptr_ ## NAME ## _ ## SUFFIX (TYPE *p, TYPE *a, TYPE *b) \
++{ \
++ *p = *a OP *b; \
++}
++
++#define CALL_OP(SUFFIX, TYPE, FUNC1, FUNC2) \
++TYPE call_ ## SUFFIX (void) \
++{ \
++ TYPE value1 = FUNC1 (); \
++ TYPE value2 = FUNC2 (); \
++ return value1 + value2; \
++}
++
++#ifndef NO_ARG
++#ifndef NO_ADD
++FLOAT_ARG (add, +)
++DOUBLE_ARG (add, +)
++FLOAT128_ARG (add, +)
++LDOUBLE_ARG (add, +)
++#endif
++
++#ifndef NO_SUB
++FLOAT_ARG (sub, -)
++DOUBLE_ARG (sub, -)
++FLOAT128_ARG (sub, -)
++LDOUBLE_ARG (sub, -)
++#endif
++
++#ifndef NO_MUL
++FLOAT_ARG (mul, *)
++DOUBLE_ARG (mul, *)
++FLOAT128_ARG (mul, *)
++LDOUBLE_ARG (mul, *)
++#endif
++
++#ifndef NO_DIV
++FLOAT_ARG (div, /)
++DOUBLE_ARG (div, /)
++FLOAT128_ARG (div, /)
++LDOUBLE_ARG (div, /)
++#endif
++#endif
++
++#ifndef NO_PTR
++#ifndef NO_ADD
++FLOAT_PTR (add, +)
++DOUBLE_PTR (add, +)
++FLOAT128_PTR (add, +)
++LDOUBLE_PTR (add, +)
++#endif
++
++#ifndef NO_SUB
++FLOAT_PTR (sub, -)
++DOUBLE_PTR (sub, -)
++FLOAT128_PTR (sub, -)
++LDOUBLE_PTR (sub, -)
++#endif
++
++#ifndef NO_MUL
++FLOAT_PTR (mul, *)
++DOUBLE_PTR (mul, *)
++FLOAT128_PTR (mul, *)
++LDOUBLE_PTR (mul, *)
++#endif
++
++#ifndef NO_DIV
++FLOAT_PTR (div, /)
++DOUBLE_PTR (div, /)
++FLOAT128_PTR (div, /)
++LDOUBLE_PTR (div, /)
++#endif
++#endif
++
++#ifndef NO_CALL
++FLOAT_CALL ()
++DOUBLE_CALL ()
++FLOAT128_CALL ()
++LDOUBLE_CALL ()
++#endif
++
++/* { dg-final { scan-assembler "xsaddqp" } } */
++/* { dg-final { scan-assembler "xssubqp" } } */
Index: gcc/testsuite/gcc.target/powerpc/p9-permute.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/powerpc/p9-permute.c (.../tags/gcc_6_1_0_release)
@@ -9260,6 +10130,43 @@ Index: gcc/testsuite/gcc.target/i386/avx512f-trunc-vec-2.c
+#include "avx512f-trunc-vec-1.c"
+
+/* { dg-final { scan-assembler-times "vrndscalepd\[^\n\]+zmm\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */
+Index: gcc/testsuite/gcc.target/i386/pr71647.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr71647.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr71647.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,32 @@
++/* PR tree-optimization/71647 */
++/* { dg-do compile } */
++/* { dg-options "-O3 -fopenmp-simd -mavx -mno-avx512f -fdump-tree-vect-details" } */
++
++void
++foo (double *a, double *b)
++{
++ int i;
++#pragma omp simd aligned(a,b:4*sizeof(double))
++ for (i = 0; i < 32768; i++)
++ a[i] += b[i];
++}
++
++void
++bar (double *a, double *b)
++{
++ int i;
++#pragma omp simd aligned(a,b:32)
++ for (i = 0; i < 32768; i++)
++ a[i] += b[i];
++}
++
++void
++baz (double *a, double *b)
++{
++ int i;
++#pragma omp simd aligned(a,b:32L)
++ for (i = 0; i < 32768; i++)
++ a[i] += b[i];
++}
++
++/* { dg-final { scan-tree-dump-not "Alignment of access forced using peeling" "vect" } } */
Index: gcc/testsuite/gcc.target/i386/pr70750-1.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/i386/pr70750-1.c (.../tags/gcc_6_1_0_release)
@@ -12131,6 +13038,36 @@ Index: gcc/testsuite/gfortran.dg/dec_structure_3.f90
+endif
+
+end
+Index: gcc/testsuite/gfortran.dg/pr70673.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/pr70673.f90 (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/pr70673.f90 (.../branches/gcc-6-branch)
+@@ -0,0 +1,25 @@
++! { dg-do run }
++!
++! Test the fix for PR70673
++!
++! Contributed by David Kinniburgh <davidgkinniburgh at yahoo.co.uk>
++!
++module m
++contains
++ subroutine s(inp)
++ character(*), intent(in) :: inp
++ character(:), allocatable :: a
++ a = a ! This used to ICE.
++ a = inp
++ a = a ! This used to ICE too
++ if ((len (a) .ne. 5) .or. (a .ne. "hello")) call abort
++ a = a(2:3) ! Make sure that temporary creation is not broken.
++ if ((len (a) .ne. 2) .or. (a .ne. "el")) call abort
++ deallocate (a)
++ a = a ! This would ICE too.
++ end subroutine s
++end module m
++
++ use m
++ call s("hello")
++end
Index: gcc/testsuite/gfortran.dg/dec_structure_11.f90
===================================================================
--- a/src/gcc/testsuite/gfortran.dg/dec_structure_11.f90 (.../tags/gcc_6_1_0_release)
@@ -12501,6 +13438,49 @@ Index: gcc/testsuite/gnat.dg/debug5.adb
+begin
+ Discard (R);
+end Debug5;
+Index: gcc/testsuite/gcc.dg/guality/param-5.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/guality/param-5.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.dg/guality/param-5.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,38 @@
++/* { dg-do run } */
++/* { dg-options "-g" } */
++/* { dg-skip-if "" { *-*-* } { "*" } { "-O0" } } */
++
++typedef __UINTPTR_TYPE__ uintptr_t;
++
++typedef struct { uintptr_t pa; uintptr_t pb; } fatp_t
++ __attribute__ ((aligned (2 * __alignof__ (uintptr_t))));
++
++__attribute__((noinline, noclone)) void
++clear_stack (void)
++{
++ char a[128 * 1024 + 128];
++
++ __builtin_memset (a + 128 * 1024, 0, 128);
++}
++
++__attribute__((noinline, noclone)) void
++foo (fatp_t str, int count)
++{
++ char a[128 * 1024];
++
++ if (count > 0)
++ foo (str, count - 1);
++ clear_stack ();
++ count--; /* BREAK */
++}
++
++int
++main (void)
++{
++ fatp_t ptr = { 31415927, 27182818 };
++ foo (ptr, 1);
++ return 0;
++}
++
++/* { dg-final { gdb-test 26 "str.pa" "31415927" } } */
++/* { dg-final { gdb-test 26 "str.pb" "27182818" } } */
Index: gcc/testsuite/gcc.dg/goacc/nested-function-1.c
===================================================================
--- a/src/gcc/testsuite/gcc.dg/goacc/nested-function-1.c (.../tags/gcc_6_1_0_release)
@@ -12811,6 +13791,28 @@ Index: gcc/testsuite/gcc.dg/graphite/pr69068.c
+ for (en = 0; en < 2; ++en)
+ zh[en] = ((qo == 0) || (((qo * 2) != 0))) ? 1 : -1;
+}
+Index: gcc/testsuite/gcc.dg/pr71558.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/pr71558.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.dg/pr71558.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,17 @@
++/* PR tree-optimization/71588 */
++
++/* strcpy must not be pure, but make sure we don't ICE even when
++ it is declared incorrectly. */
++char *strcpy (char *, const char *) __attribute__ ((__pure__));
++__SIZE_TYPE__ strlen (const char *);
++void *malloc (__SIZE_TYPE__);
++
++char a[20];
++
++char *
++foo (void)
++{
++ __SIZE_TYPE__ b = strlen (a);
++ char *c = malloc (b);
++ return strcpy (c, a);
++}
Index: gcc/testsuite/gcc.dg/pr71071.c
===================================================================
--- a/src/gcc/testsuite/gcc.dg/pr71071.c (.../tags/gcc_6_1_0_release)
@@ -13127,11 +14129,79 @@ Index: gcc/testsuite/gcc.dg/vect/pr71259.c
+ __builtin_abort ();
+ return 0;
+}
+Index: gcc/testsuite/gcc.dg/pr71581.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/pr71581.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.dg/pr71581.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,24 @@
++/* PR middle-end/71581 */
++/* { dg-do compile } */
++/* { dg-options "-Wuninitialized" } */
++
++_Complex float
++f1 (void)
++{
++ float x;
++ return x; /* { dg-warning "is used uninitialized in this function" } */
++}
++
++_Complex double
++f2 (void)
++{
++ double x;
++ return x; /* { dg-warning "is used uninitialized in this function" } */
++}
++
++_Complex int
++f3 (void)
++{
++ int x;
++ return x; /* { dg-warning "is used uninitialized in this function" } */
++}
Index: gcc/testsuite/ChangeLog
===================================================================
--- a/src/gcc/testsuite/ChangeLog (.../tags/gcc_6_1_0_release)
+++ b/src/gcc/testsuite/ChangeLog (.../branches/gcc-6-branch)
-@@ -1,3 +1,721 @@
+@@ -1,3 +1,760 @@
++2016-06-27 Paul Thomas <pault at gcc.gnu.org>
++
++ PR fortran/70673
++ * gfortran.dg/pr70673.f90: New test.
++
++2016-06-27 Michael Meissner <meissner at linux.vnet.ibm.com>
++
++ Back port from trunk
++ 2016-05-02 Michael Meissner <meissner at linux.vnet.ibm.com>
++
++ * gcc.target/powerpc/float128-complex-1.c: New tests for complex
++ __float128.
++ * gcc.target/powerpc/float128-complex-2.c: Likewise.
++
++2016-06-24 Jakub Jelinek <jakub at redhat.com>
++
++ PR tree-optimization/71647
++ * gcc.target/i386/pr71647.c: New test.
++
++2016-06-22 Eric Botcazou <ebotcazou at adacore.com>
++
++ * gcc.dg/guality/param-5.c: New test.
++
++2016-06-21 Jakub Jelinek <jakub at redhat.com>
++
++ PR tree-optimization/71588
++ * gcc.dg/pr71558.c: New test.
++
++ Backported from mainline
++ 2016-06-20 Jakub Jelinek <jakub at redhat.com>
++
++ PR middle-end/71581
++ * gcc.dg/pr71581.c: New test.
++
++ 2016-06-14 Jakub Jelinek <jakub at redhat.com>
++
++ PR c++/71528
++ * g++.dg/opt/pr71528.C: New test.
++
+2016-06-20 Ilya Enkovich <ilya.enkovich at intel.com>
+
+ Backport from mainline r237484.
@@ -13962,6 +15032,34 @@ Index: gcc/testsuite/g++.dg/opt/pr70847.C
+ D d;
+ d.f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f().f();
+}
+Index: gcc/testsuite/g++.dg/opt/pr71528.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/opt/pr71528.C (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/g++.dg/opt/pr71528.C (.../branches/gcc-6-branch)
+@@ -0,0 +1,23 @@
++// PR c++/71528
++// { dg-do run }
++// { dg-options "-O2" }
++
++extern int &x;
++int y;
++
++int &
++foo ()
++{
++ return y;
++}
++
++int &x = foo ();
++
++int
++main ()
++{
++ if (&x != &y)
++ __builtin_abort ();
++}
++
++extern int &x;
Index: gcc/testsuite/g++.dg/opt/pr71210-1.C
===================================================================
--- a/src/gcc/testsuite/g++.dg/opt/pr71210-1.C (.../tags/gcc_6_1_0_release)
@@ -15534,7 +16632,22 @@ Index: gcc/cp/decl.c
===================================================================
--- a/src/gcc/cp/decl.c (.../tags/gcc_6_1_0_release)
+++ b/src/gcc/cp/decl.c (.../branches/gcc-6-branch)
-@@ -5329,10 +5329,7 @@
+@@ -2090,6 +2090,14 @@
+ if (VAR_P (newdecl))
+ {
+ DECL_THIS_EXTERN (newdecl) |= DECL_THIS_EXTERN (olddecl);
++ /* For already initialized vars, TREE_READONLY could have been
++ cleared in cp_finish_decl, because the var needs runtime
++ initialization or destruction. Make sure not to set
++ TREE_READONLY on it again. */
++ if (DECL_INITIALIZED_P (olddecl)
++ && !DECL_EXTERNAL (olddecl)
++ && !TREE_READONLY (olddecl))
++ TREE_READONLY (newdecl) = 0;
+ DECL_INITIALIZED_P (newdecl) |= DECL_INITIALIZED_P (olddecl);
+ DECL_NONTRIVIALLY_INITIALIZED_P (newdecl)
+ |= DECL_NONTRIVIALLY_INITIALIZED_P (olddecl);
+@@ -5329,10 +5337,7 @@
complete_type (type);
if (!DECL_SIZE (decl)
&& TREE_TYPE (decl) != error_mark_node
@@ -15546,7 +16659,7 @@ Index: gcc/cp/decl.c
layout_decl (decl, 0);
if (!DECL_EXTERNAL (decl) && DECL_SIZE (decl) == NULL_TREE)
-@@ -6633,6 +6630,13 @@
+@@ -6633,6 +6638,13 @@
adc_variable_type);
if (type == error_mark_node)
return;
@@ -15560,7 +16673,7 @@ Index: gcc/cp/decl.c
cp_apply_type_quals_to_decl (cp_type_quals (type), decl);
}
-@@ -11186,8 +11190,7 @@
+@@ -11186,8 +11198,7 @@
}
else if (!staticp && !dependent_type_p (type)
&& !COMPLETE_TYPE_P (complete_type (type))
@@ -15570,7 +16683,7 @@ Index: gcc/cp/decl.c
|| initialized == 0))
{
if (TREE_CODE (type) != ARRAY_TYPE
-@@ -13382,6 +13385,19 @@
+@@ -13382,6 +13393,19 @@
use_short_enum = flag_short_enums
|| lookup_attribute ("packed", TYPE_ATTRIBUTES (enumtype));
@@ -15590,7 +16703,7 @@ Index: gcc/cp/decl.c
for (itk = (use_short_enum ? itk_char : itk_int);
itk != itk_none;
itk++)
-@@ -14999,8 +15015,9 @@
+@@ -14999,8 +15023,9 @@
tree var = iv->decl;
tree type = TREE_TYPE (var);
@@ -15643,7 +16756,32 @@ Index: gcc/cp/ChangeLog
===================================================================
--- a/src/gcc/cp/ChangeLog (.../tags/gcc_6_1_0_release)
+++ b/src/gcc/cp/ChangeLog (.../branches/gcc-6-branch)
-@@ -1,3 +1,176 @@
+@@ -1,3 +1,201 @@
++2016-06-21 Jakub Jelinek <jakub at redhat.com>
++
++ Backported from mainline
++ 2016-06-17 Jakub Jelinek <jakub at redhat.com>
++
++ * semantics.c (handle_omp_array_sections_1): Don't ICE when
++ processing_template_decl when checking for bitfields and unions.
++ Look through REFERENCE_REF_P as base of COMPONENT_REF.
++ (finish_omp_clauses): Look through REFERENCE_REF_P even for
++ array sections with COMPONENT_REF bases.
++
++ 2016-06-16 Jakub Jelinek <jakub at redhat.com>
++
++ * parser.c (cp_parser_omp_var_list_no_open): Call
++ convert_from_reference before cp_parser_postfix_dot_deref_expression.
++ * semantics.c (finish_omp_clauses): Don't ICE when
++ processing_template_decl when checking for bitfields and unions.
++ Look through REFERENCE_REF_P as base of COMPONENT_REF.
++
++ 2016-06-14 Jakub Jelinek <jakub at redhat.com>
++
++ PR c++/71528
++ * decl.c (duplicate_decls): For DECL_INITIALIZED_P non-external
++ olddecl vars, preserve their TREE_READONLY bit.
++
+2016-06-14 Paolo Carlini <paolo.carlini at oracle.com>
+
+ PR c++/70572
@@ -16229,7 +17367,36 @@ Index: gcc/cp/semantics.c
return error_mark_node;
bool saw_generic_lambda = false;
-@@ -5884,7 +5884,8 @@
+@@ -4507,7 +4507,8 @@
+ || OMP_CLAUSE_CODE (c) == OMP_CLAUSE_FROM)
+ && !type_dependent_expression_p (t))
+ {
+- if (DECL_BIT_FIELD (TREE_OPERAND (t, 1)))
++ if (TREE_CODE (TREE_OPERAND (t, 1)) == FIELD_DECL
++ && DECL_BIT_FIELD (TREE_OPERAND (t, 1)))
+ {
+ error_at (OMP_CLAUSE_LOCATION (c),
+ "bit-field %qE in %qs clause",
+@@ -4516,7 +4517,8 @@
+ }
+ while (TREE_CODE (t) == COMPONENT_REF)
+ {
+- if (TREE_CODE (TREE_TYPE (TREE_OPERAND (t, 0))) == UNION_TYPE)
++ if (TREE_TYPE (TREE_OPERAND (t, 0))
++ && TREE_CODE (TREE_TYPE (TREE_OPERAND (t, 0))) == UNION_TYPE)
+ {
+ error_at (OMP_CLAUSE_LOCATION (c),
+ "%qE is a member of a union", t);
+@@ -4524,6 +4526,8 @@
+ }
+ t = TREE_OPERAND (t, 0);
+ }
++ if (REFERENCE_REF_P (t))
++ t = TREE_OPERAND (t, 0);
+ }
+ if (!VAR_P (t) && TREE_CODE (t) != PARM_DECL)
+ {
+@@ -5884,7 +5888,8 @@
}
if (TREE_CODE (type) == REFERENCE_TYPE)
type = TREE_TYPE (type);
@@ -16239,6 +17406,46 @@ Index: gcc/cp/semantics.c
&& TREE_CODE (type) != POINTER_TYPE)
{
error ("linear clause applied to non-integral non-pointer "
+@@ -6583,6 +6588,8 @@
+ {
+ while (TREE_CODE (t) == COMPONENT_REF)
+ t = TREE_OPERAND (t, 0);
++ if (REFERENCE_REF_P (t))
++ t = TREE_OPERAND (t, 0);
+ if (bitmap_bit_p (&map_field_head, DECL_UID (t)))
+ break;
+ if (bitmap_bit_p (&map_head, DECL_UID (t)))
+@@ -6621,7 +6628,8 @@
+ {
+ if (type_dependent_expression_p (t))
+ break;
+- if (DECL_BIT_FIELD (TREE_OPERAND (t, 1)))
++ if (TREE_CODE (TREE_OPERAND (t, 1)) == FIELD_DECL
++ && DECL_BIT_FIELD (TREE_OPERAND (t, 1)))
+ {
+ error_at (OMP_CLAUSE_LOCATION (c),
+ "bit-field %qE in %qs clause",
+@@ -6637,8 +6645,9 @@
+ }
+ while (TREE_CODE (t) == COMPONENT_REF)
+ {
+- if (TREE_CODE (TREE_TYPE (TREE_OPERAND (t, 0)))
+- == UNION_TYPE)
++ if (TREE_TYPE (TREE_OPERAND (t, 0))
++ && (TREE_CODE (TREE_TYPE (TREE_OPERAND (t, 0)))
++ == UNION_TYPE))
+ {
+ error_at (OMP_CLAUSE_LOCATION (c),
+ "%qE is a member of a union", t);
+@@ -6649,6 +6658,8 @@
+ }
+ if (remove)
+ break;
++ if (REFERENCE_REF_P (t))
++ t = TREE_OPERAND (t, 0);
+ if (VAR_P (t) || TREE_CODE (t) == PARM_DECL)
+ {
+ if (bitmap_bit_p (&map_field_head, DECL_UID (t)))
Index: gcc/cp/decl2.c
===================================================================
--- a/src/gcc/cp/decl2.c (.../tags/gcc_6_1_0_release)
@@ -16352,7 +17559,15 @@ Index: gcc/cp/parser.c
if (cp_lexer_peek_token (parser->lexer)->type != CPP_OPEN_SQUARE)
{
error_at (token->location, "expected %<[%>");
-@@ -30000,25 +30017,6 @@
+@@ -29965,6 +29982,7 @@
+ = cp_lexer_peek_token (parser->lexer)->location;
+ cp_id_kind idk = CP_ID_KIND_NONE;
+ cp_lexer_consume_token (parser->lexer);
++ decl = convert_from_reference (decl);
+ decl
+ = cp_parser_postfix_dot_deref_expression (parser, CPP_DOT,
+ decl, false,
+@@ -30000,25 +30018,6 @@
RT_CLOSE_SQUARE))
goto skip_comma;
@@ -16378,7 +17593,7 @@ Index: gcc/cp/parser.c
decl = tree_cons (low_bound, length, decl);
}
break;
-@@ -33884,7 +33882,9 @@
+@@ -33884,7 +33883,9 @@
strcat (p_name, " for");
mask |= OMP_FOR_CLAUSE_MASK;
@@ -16389,7 +17604,7 @@ Index: gcc/cp/parser.c
mask &= ~(OMP_CLAUSE_MASK_1 << PRAGMA_OMP_CLAUSE_NOWAIT);
/* Composite distribute parallel for{, simd} disallows ordered clause. */
if ((mask & (OMP_CLAUSE_MASK_1 << PRAGMA_OMP_CLAUSE_DIST_SCHEDULE)) != 0)
-@@ -34223,7 +34223,8 @@
+@@ -34223,7 +34224,8 @@
}
}
@@ -16399,7 +17614,7 @@ Index: gcc/cp/parser.c
if (cclauses)
{
cp_omp_split_clauses (loc, OMP_PARALLEL, mask, clauses, cclauses);
-@@ -35396,6 +35397,8 @@
+@@ -35396,6 +35398,8 @@
cp_parser_oacc_loop (cp_parser *parser, cp_token *pragma_tok, char *p_name,
omp_clause_mask mask, tree *cclauses, bool *if_p)
{
@@ -16408,7 +17623,7 @@ Index: gcc/cp/parser.c
strcat (p_name, " loop");
mask |= OACC_LOOP_CLAUSE_MASK;
-@@ -35403,7 +35406,7 @@
+@@ -35403,7 +35407,7 @@
cclauses == NULL);
if (cclauses)
{
@@ -16417,7 +17632,7 @@ Index: gcc/cp/parser.c
if (*cclauses)
*cclauses = finish_omp_clauses (*cclauses, false);
if (clauses)
-@@ -35496,8 +35499,6 @@
+@@ -35496,8 +35500,6 @@
if (strcmp (p, "loop") == 0)
{
cp_lexer_consume_token (parser->lexer);
@@ -19246,7 +20461,13 @@ Index: gcc/fortran/ChangeLog
===================================================================
--- a/src/gcc/fortran/ChangeLog (.../tags/gcc_6_1_0_release)
+++ b/src/gcc/fortran/ChangeLog (.../branches/gcc-6-branch)
-@@ -1,3 +1,160 @@
+@@ -1,3 +1,166 @@
++2016-06-27 Paul Thomas <pault at gcc.gnu.org>
++
++ PR fortran/70673
++ * frontend-passes.c (realloc_string_callback): Add a call to
++ gfc_dep_compare_expr.
++
+2016-06-12 Dominique d'Humieres <dominiq at lps.ens.fr>
+
+ PR fortran/60751
@@ -19800,19 +21021,26 @@ Index: gcc/fortran/frontend-passes.c
===================================================================
--- a/src/gcc/fortran/frontend-passes.c (.../tags/gcc_6_1_0_release)
+++ b/src/gcc/fortran/frontend-passes.c (.../branches/gcc-6-branch)
-@@ -174,8 +174,10 @@
+@@ -174,8 +174,17 @@
if (!gfc_check_dependency (expr1, expr2, true))
return 0;
-
+
++ /* gfc_check_dependency doesn't always pick up identical expressions.
++ However, eliminating the above sends the compiler into an infinite
++ loop on valid expressions. Without this check, the gimplifier emits
++ an ICE for a = a, where a is deferred character length. */
++ if (!gfc_dep_compare_expr (expr1, expr2))
++ return 0;
++
current_code = c;
+ inserted_block = NULL;
+ changed_statement = NULL;
n = create_var (expr2, "trim");
co->expr2 = n;
return 0;
-@@ -2812,6 +2814,12 @@
+@@ -2812,6 +2821,12 @@
if (in_where)
return 0;
@@ -22284,6 +23512,38 @@ Index: gcc/BASE-VER
@@ -1 +1 @@
-6.1.0
+6.1.1
+Index: gcc/function.c
+===================================================================
+--- a/src/gcc/function.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/function.c (.../branches/gcc-6-branch)
+@@ -3314,6 +3314,8 @@
+ set_mem_attributes (parmreg, parm, 1);
+ }
+
++ /* We need to preserve an address based on VIRTUAL_STACK_VARS_REGNUM for
++ the debug info in case it is not legitimate. */
+ if (GET_MODE (parmreg) != GET_MODE (rtl))
+ {
+ rtx tempreg = gen_reg_rtx (GET_MODE (rtl));
+@@ -3323,7 +3325,8 @@
+ all->last_conversion_insn);
+ emit_move_insn (tempreg, rtl);
+ tempreg = convert_to_mode (GET_MODE (parmreg), tempreg, unsigned_p);
+- emit_move_insn (parmreg, tempreg);
++ emit_move_insn (MEM_P (parmreg) ? copy_rtx (parmreg) : parmreg,
++ tempreg);
+ all->first_conversion_insn = get_insns ();
+ all->last_conversion_insn = get_last_insn ();
+ end_sequence ();
+@@ -3331,7 +3334,7 @@
+ did_conversion = true;
+ }
+ else
+- emit_move_insn (parmreg, rtl);
++ emit_move_insn (MEM_P (parmreg) ? copy_rtx (parmreg) : parmreg, rtl);
+
+ rtl = parmreg;
+
Index: gcc/stor-layout.c
===================================================================
--- a/src/gcc/stor-layout.c (.../tags/gcc_6_1_0_release)
@@ -22316,7 +23576,20 @@ Index: gcc/stor-layout.c
/* Given a size SIZE that may not be a constant, return a SAVE_EXPR
to serve as the actual size-expression for a type or decl. */
-@@ -2245,12 +2231,6 @@
+@@ -2161,10 +2147,8 @@
+ case COMPLEX_TYPE:
+ TYPE_UNSIGNED (type) = TYPE_UNSIGNED (TREE_TYPE (type));
+ SET_TYPE_MODE (type,
+- mode_for_size (2 * TYPE_PRECISION (TREE_TYPE (type)),
+- (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE
+- ? MODE_COMPLEX_FLOAT : MODE_COMPLEX_INT),
+- 0));
++ GET_MODE_COMPLEX_MODE (TYPE_MODE (TREE_TYPE (type))));
++
+ TYPE_SIZE (type) = bitsize_int (GET_MODE_BITSIZE (TYPE_MODE (type)));
+ TYPE_SIZE_UNIT (type) = size_int (GET_MODE_SIZE (TYPE_MODE (type)));
+ break;
+@@ -2245,12 +2229,6 @@
case REFERENCE_TYPE:
{
machine_mode mode = TYPE_MODE (type);
@@ -22790,7 +24063,111 @@ Index: gcc/gimplify.c
===================================================================
--- a/src/gcc/gimplify.c (.../tags/gcc_6_1_0_release)
+++ b/src/gcc/gimplify.c (.../branches/gcc-6-branch)
-@@ -8224,7 +8224,13 @@
+@@ -6894,6 +6894,11 @@
+ {
+ while (TREE_CODE (decl) == COMPONENT_REF)
+ decl = TREE_OPERAND (decl, 0);
++ if (TREE_CODE (decl) == INDIRECT_REF
++ && DECL_P (TREE_OPERAND (decl, 0))
++ && (TREE_CODE (TREE_TYPE (TREE_OPERAND (decl, 0)))
++ == REFERENCE_TYPE))
++ decl = TREE_OPERAND (decl, 0);
+ }
+ if (gimplify_expr (pd, pre_p, NULL, is_gimple_lvalue, fb_lvalue)
+ == GS_ERROR)
+@@ -6909,9 +6914,11 @@
+ break;
+ }
+
+- if (TYPE_SIZE_UNIT (TREE_TYPE (decl)) == NULL
+- || (TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (decl)))
+- != INTEGER_CST))
++ tree stype = TREE_TYPE (decl);
++ if (TREE_CODE (stype) == REFERENCE_TYPE)
++ stype = TREE_TYPE (stype);
++ if (TYPE_SIZE_UNIT (stype) == NULL
++ || TREE_CODE (TYPE_SIZE_UNIT (stype)) != INTEGER_CST)
+ {
+ error_at (OMP_CLAUSE_LOCATION (c),
+ "mapping field %qE of variable length "
+@@ -6951,6 +6958,14 @@
+ base = get_inner_reference (base, &bitsize, &bitpos, &offset,
+ &mode, &unsignedp, &reversep,
+ &volatilep, false);
++ tree orig_base = base;
++ if ((TREE_CODE (base) == INDIRECT_REF
++ || (TREE_CODE (base) == MEM_REF
++ && integer_zerop (TREE_OPERAND (base, 1))))
++ && DECL_P (TREE_OPERAND (base, 0))
++ && (TREE_CODE (TREE_TYPE (TREE_OPERAND (base, 0)))
++ == REFERENCE_TYPE))
++ base = TREE_OPERAND (base, 0);
+ gcc_assert (base == decl
+ && (offset == NULL_TREE
+ || TREE_CODE (offset) == INTEGER_CST));
+@@ -6964,7 +6979,10 @@
+ tree l = build_omp_clause (OMP_CLAUSE_LOCATION (c),
+ OMP_CLAUSE_MAP);
+ OMP_CLAUSE_SET_MAP_KIND (l, GOMP_MAP_STRUCT);
+- OMP_CLAUSE_DECL (l) = decl;
++ if (orig_base != base)
++ OMP_CLAUSE_DECL (l) = unshare_expr (orig_base);
++ else
++ OMP_CLAUSE_DECL (l) = decl;
+ OMP_CLAUSE_SIZE (l) = size_int (1);
+ if (struct_map_to_clause == NULL)
+ struct_map_to_clause = new hash_map<tree, tree>;
+@@ -7006,6 +7024,18 @@
+ *list_p = l;
+ list_p = &OMP_CLAUSE_CHAIN (l);
+ }
++ if (orig_base != base && code == OMP_TARGET)
++ {
++ tree c2 = build_omp_clause (OMP_CLAUSE_LOCATION (c),
++ OMP_CLAUSE_MAP);
++ enum gomp_map_kind mkind
++ = GOMP_MAP_FIRSTPRIVATE_REFERENCE;
++ OMP_CLAUSE_SET_MAP_KIND (c2, mkind);
++ OMP_CLAUSE_DECL (c2) = decl;
++ OMP_CLAUSE_SIZE (c2) = size_zero_node;
++ OMP_CLAUSE_CHAIN (c2) = OMP_CLAUSE_CHAIN (l);
++ OMP_CLAUSE_CHAIN (l) = c2;
++ }
+ flags = GOVD_MAP | GOVD_EXPLICIT;
+ if (GOMP_MAP_ALWAYS_P (OMP_CLAUSE_MAP_KIND (c)) || ptr)
+ flags |= GOVD_SEEN;
+@@ -7024,8 +7054,12 @@
+ o1 = 0;
+ if (bitpos)
+ o1 = o1 + bitpos / BITS_PER_UNIT;
+- for (sc = &OMP_CLAUSE_CHAIN (*osc);
+- *sc != c; sc = &OMP_CLAUSE_CHAIN (*sc))
++ sc = &OMP_CLAUSE_CHAIN (*osc);
++ if (*sc != c
++ && (OMP_CLAUSE_MAP_KIND (*sc)
++ == GOMP_MAP_FIRSTPRIVATE_REFERENCE))
++ sc = &OMP_CLAUSE_CHAIN (*sc);
++ for (; *sc != c; sc = &OMP_CLAUSE_CHAIN (*sc))
+ if (ptr && sc == prev_list_p)
+ break;
+ else if (TREE_CODE (OMP_CLAUSE_DECL (*sc))
+@@ -7061,6 +7095,15 @@
+ &mode, &unsignedp,
+ &reversep, &volatilep,
+ false);
++ if ((TREE_CODE (base) == INDIRECT_REF
++ || (TREE_CODE (base) == MEM_REF
++ && integer_zerop (TREE_OPERAND (base,
++ 1))))
++ && DECL_P (TREE_OPERAND (base, 0))
++ && (TREE_CODE (TREE_TYPE (TREE_OPERAND (base,
++ 0)))
++ == REFERENCE_TYPE))
++ base = TREE_OPERAND (base, 0);
+ if (base != decl)
+ break;
+ if (scp)
+@@ -8224,7 +8267,13 @@
case OMP_CLAUSE_VECTOR:
case OMP_CLAUSE_AUTO:
case OMP_CLAUSE_SEQ:
@@ -22804,7 +24181,7 @@ Index: gcc/gimplify.c
break;
default:
-@@ -8785,7 +8791,10 @@
+@@ -8785,7 +8834,10 @@
decl, false))
;
else if (outer->region_type != ORT_COMBINED_PARALLEL)
@@ -22816,7 +24193,7 @@ Index: gcc/gimplify.c
if (outer)
{
n = splay_tree_lookup (outer->variables,
-@@ -8868,7 +8877,10 @@
+@@ -8868,7 +8920,10 @@
decl, false))
;
else if (outer->region_type != ORT_COMBINED_PARALLEL)
@@ -22828,7 +24205,7 @@ Index: gcc/gimplify.c
if (outer)
{
n = splay_tree_lookup (outer->variables,
-@@ -8946,7 +8958,12 @@
+@@ -8946,7 +9001,12 @@
|| (ort == ORT_SIMD
&& TREE_VEC_LENGTH (OMP_FOR_INIT (for_stmt)) > 1))
{
@@ -22940,6 +24317,66 @@ Index: gcc/tree-ssa-coalesce.c
type equivalency also holds for SSA names with the same
underlying decl.
+Index: gcc/genmodes.c
+===================================================================
+--- a/src/gcc/genmodes.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/genmodes.c (.../branches/gcc-6-branch)
+@@ -66,6 +66,7 @@
+ this mode as a component. */
+ struct mode_data *next_cont; /* Next mode in that list. */
+
++ struct mode_data *complex; /* complex type with mode as component. */
+ const char *file; /* file and line of definition, */
+ unsigned int line; /* for error reporting */
+ unsigned int counter; /* Rank ordering of modes */
+@@ -83,7 +84,7 @@
+ static const struct mode_data blank_mode = {
+ 0, "<unknown>", MAX_MODE_CLASS,
+ -1U, -1U, -1U, -1U,
+- 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0,
+ "<unknown>", 0, 0, 0, 0, false, 0
+ };
+
+@@ -472,6 +473,7 @@
+
+ c = new_mode (cclass, buf, file, line);
+ c->component = m;
++ m->complex = c;
+ }
+ }
+
+@@ -1381,6 +1383,22 @@
+ }
+
+ static void
++emit_mode_complex (void)
++{
++ int c;
++ struct mode_data *m;
++
++ print_decl ("unsigned char", "mode_complex", "NUM_MACHINE_MODES");
++
++ for_all_modes (c, m)
++ tagged_printf ("%smode",
++ m->complex ? m->complex->name : void_mode->name,
++ m->name);
++
++ print_closer ();
++}
++
++static void
+ emit_mode_mask (void)
+ {
+ int c;
+@@ -1745,6 +1763,7 @@
+ emit_mode_size ();
+ emit_mode_nunits ();
+ emit_mode_wider ();
++ emit_mode_complex ();
+ emit_mode_mask ();
+ emit_mode_inner ();
+ emit_mode_unit_size ();
Index: gcc/gimple-fold.c
===================================================================
--- a/src/gcc/gimple-fold.c (.../tags/gcc_6_1_0_release)
@@ -806386,14 +807823,15 @@ Index: gcc/config/avr/avr.md
===================================================================
--- a/src/gcc/config/avr/avr.md (.../tags/gcc_6_1_0_release)
+++ b/src/gcc/config/avr/avr.md (.../branches/gcc-6-branch)
-@@ -641,6 +641,21 @@
+@@ -641,6 +641,22 @@
if (avr_mem_flash_p (dest))
DONE;
+ if (QImode == <MODE>mode
+ && SUBREG_P (src)
-+ && CONSTANT_ADDRESS_P (SUBREG_REG (src)))
-+ {
++ && CONSTANT_ADDRESS_P (SUBREG_REG (src))
++ && can_create_pseudo_p())
++ {
+ // store_bitfield may want to store a SYMBOL_REF or CONST in a
+ // structure that's represented as PSImode. As the upper 16 bits
+ // of PSImode cannot be expressed as an HImode subreg, the rhs is
@@ -806408,6 +807846,35 @@ Index: gcc/config/avr/avr.md
/* One of the operands has to be in a register. */
if (!register_operand (dest, <MODE>mode)
&& !reg_or_0_operand (src, <MODE>mode))
+Index: gcc/config/avr/gen-avr-mmcu-specs.c
+===================================================================
+--- a/src/gcc/config/avr/gen-avr-mmcu-specs.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/config/avr/gen-avr-mmcu-specs.c (.../branches/gcc-6-branch)
+@@ -27,7 +27,7 @@
+
+ #include "avr-devices.c"
+
+-// Get rid of "defaults.h". We just need tm.h for `WITH_AVRLIBS' and
++// Get rid of "defaults.h". We just need tm.h for `WITH_AVRLIBC' and
+ // and `WITH_RTEMS'. */
+ #define GCC_DEFAULTS_H
+
+@@ -242,12 +242,13 @@
+ fprintf (f, "*link_data_start:\n");
+ if (mcu->data_section_start
+ != arch->default_data_section_start)
+- fprintf (f, "\t-Tdata 0x%lX", 0x800000UL + mcu->data_section_start);
++ fprintf (f, "\t%%{!Tdata:-Tdata 0x%lX}",
++ 0x800000UL + mcu->data_section_start);
+ fprintf (f, "\n\n");
+
+ fprintf (f, "*link_text_start:\n");
+ if (mcu->text_section_start != 0x0)
+- fprintf (f, "\t-Ttext 0x%lX", 0UL + mcu->text_section_start);
++ fprintf (f, "\t%%{!Ttext:-Ttext 0x%lX}", 0UL + mcu->text_section_start);
+ fprintf (f, "\n\n");
+ }
+
Index: gcc/config/rtems.h
===================================================================
--- a/src/gcc/config/rtems.h (.../tags/gcc_6_1_0_release)
@@ -807303,7 +808770,26 @@ Index: gcc/config/rs6000/rs6000.c
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
-@@ -2105,7 +2121,9 @@
+@@ -1866,7 +1882,7 @@
+ 128-bit floating point that can go in vector registers, which has VSX
+ memory addressing. */
+ if (FP_REGNO_P (regno))
+- reg_size = (VECTOR_MEM_VSX_P (mode)
++ reg_size = (VECTOR_MEM_VSX_P (mode) || FLOAT128_VECTOR_P (mode)
+ ? UNITS_PER_VSX_WORD
+ : UNITS_PER_FP_WORD);
+
+@@ -1898,6 +1914,9 @@
+ {
+ int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
+
++ if (COMPLEX_MODE_P (mode))
++ mode = GET_MODE_INNER (mode);
++
+ /* PTImode can only go in GPRs. Quad word memory operations require even/odd
+ register combinations, and use PTImode where we need to deal with quad
+ word memory operations. Don't allow quad words in the argument or frame
+@@ -2105,7 +2124,9 @@
else if (keep_spaces)
*p++ = ' ';
@@ -807314,7 +808800,7 @@ Index: gcc/config/rs6000/rs6000.c
*p++ = 'o';
else if (keep_spaces)
*p++ = ' ';
-@@ -2642,8 +2660,7 @@
+@@ -2642,8 +2663,7 @@
if (TARGET_LINK_STACK)
fprintf (stderr, DEBUG_FMT_S, "link_stack", "true");
@@ -807324,7 +808810,46 @@ Index: gcc/config/rs6000/rs6000.c
if (TARGET_P8_FUSION)
{
-@@ -2769,17 +2786,31 @@
+@@ -2699,9 +2719,18 @@
+
+ for (m = 0; m < NUM_MACHINE_MODES; ++m)
+ {
+- machine_mode m2 = (machine_mode)m;
+- unsigned short msize = GET_MODE_SIZE (m2);
++ machine_mode m2 = (machine_mode) m;
++ bool complex_p = false;
++ size_t msize;
+
++ if (COMPLEX_MODE_P (m2))
++ {
++ complex_p = true;
++ m2 = GET_MODE_INNER (m2);
++ }
++
++ msize = GET_MODE_SIZE (m2);
++
+ /* SDmode is special in that we want to access it only via REG+REG
+ addressing on power7 and above, since we want to use the LFIWZX and
+ STFIWZX instructions to load it. */
+@@ -2722,7 +2751,7 @@
+ /* Indicate if the mode takes more than 1 physical register. If
+ it takes a single register, indicate it can do REG+REG
+ addressing. */
+- if (nregs > 1 || m == BLKmode)
++ if (nregs > 1 || m == BLKmode || complex_p)
+ addr_mask |= RELOAD_REG_MULTIPLE;
+ else
+ addr_mask |= RELOAD_REG_INDEXED;
+@@ -2738,7 +2767,7 @@
+ && msize <= 8
+ && !VECTOR_MODE_P (m2)
+ && !FLOAT128_VECTOR_P (m2)
+- && !COMPLEX_MODE_P (m2)
++ && !complex_p
+ && (m2 != DFmode || !TARGET_UPPER_REGS_DF)
+ && (m2 != SFmode || !TARGET_UPPER_REGS_SF)
+ && !(TARGET_E500_DOUBLE && msize == 8))
+@@ -2769,17 +2798,31 @@
}
/* GPR and FPR registers can do REG+OFFSET addressing, except
@@ -807362,7 +808887,7 @@ Index: gcc/config/rs6000/rs6000.c
/* VMX registers can do (REG & -16) and ((REG+REG) & -16)
addressing on 128-bit types. */
if (rc == RELOAD_REG_VMX && msize == 16
-@@ -3102,7 +3133,7 @@
+@@ -3102,7 +3145,7 @@
}
/* Support for new D-form instructions. */
@@ -807371,7 +808896,7 @@ Index: gcc/config/rs6000/rs6000.c
rs6000_constraints[RS6000_CONSTRAINT_wb] = ALTIVEC_REGS;
/* Support for ISA 3.0 (power9) vectors. */
-@@ -3621,6 +3652,9 @@
+@@ -3621,6 +3664,9 @@
| ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)
| ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0)
| ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0)
@@ -807381,7 +808906,7 @@ Index: gcc/config/rs6000/rs6000.c
| ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0)
| ((TARGET_HTM) ? RS6000_BTM_HTM : 0)
| ((TARGET_DFP) ? RS6000_BTM_DFP : 0)
-@@ -3974,7 +4008,8 @@
+@@ -3974,7 +4020,8 @@
/* For the newer switches (vsx, dfp, etc.) set some of the older options,
unless the user explicitly used the -mno-<option> to disable the code. */
@@ -807391,7 +808916,7 @@ Index: gcc/config/rs6000/rs6000.c
rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~rs6000_isa_flags_explicit);
else if (TARGET_P8_VECTOR || TARGET_DIRECT_MOVE || TARGET_CRYPTO)
rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~rs6000_isa_flags_explicit);
-@@ -4188,26 +4223,49 @@
+@@ -4188,26 +4235,49 @@
&& !(rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION))
rs6000_isa_flags |= OPTION_MASK_TOC_FUSION;
@@ -807447,7 +808972,7 @@ Index: gcc/config/rs6000/rs6000.c
}
/* ISA 3.0 vector instructions include ISA 2.07. */
-@@ -4218,6 +4276,47 @@
+@@ -4218,6 +4288,47 @@
rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR;
}
@@ -807495,7 +809020,7 @@ Index: gcc/config/rs6000/rs6000.c
/* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
support. If we only have ISA 2.06 support, and the user did not specify
the switch, leave it set to -1 so the movmisalign patterns are enabled,
-@@ -6134,6 +6233,128 @@
+@@ -6134,6 +6245,128 @@
gcc_unreachable ();
}
@@ -807624,7 +809149,7 @@ Index: gcc/config/rs6000/rs6000.c
const char *
output_vec_const_move (rtx *operands)
{
-@@ -6147,24 +6368,61 @@
+@@ -6147,24 +6380,61 @@
if (TARGET_VSX)
{
@@ -807694,7 +809219,7 @@ Index: gcc/config/rs6000/rs6000.c
/* Do we need to construct a value using VSLDOI? */
shift = vspltis_shifted (vec);
if (shift != 0)
-@@ -6436,6 +6694,15 @@
+@@ -6436,6 +6706,15 @@
return;
}
@@ -807710,7 +809235,7 @@ Index: gcc/config/rs6000/rs6000.c
/* With single precision floating point on VSX, know that internally single
precision is actually represented as a double, and either make 2 V2DF
vectors, and convert these vectors to single precision, or do one
-@@ -6444,14 +6711,23 @@
+@@ -6444,14 +6723,23 @@
{
if (all_same)
{
@@ -807741,7 +809266,7 @@ Index: gcc/config/rs6000/rs6000.c
}
else
{
-@@ -6572,21 +6848,29 @@
+@@ -6572,21 +6860,29 @@
gen_rtvec (3, target, reg,
force_reg (V16QImode, x)),
UNSPEC_VPERM);
@@ -807784,7 +809309,7 @@ Index: gcc/config/rs6000/rs6000.c
}
emit_insn (gen_rtx_SET (target, x));
-@@ -6902,6 +7186,59 @@
+@@ -6902,6 +7198,59 @@
return false;
}
@@ -807844,7 +809369,7 @@ Index: gcc/config/rs6000/rs6000.c
/* Return true if this is a load or store quad operation. This function does
not handle the atomic quad memory instructions. */
-@@ -6994,6 +7331,10 @@
+@@ -6994,6 +7343,10 @@
if (TARGET_POWERPC64 && (offset & 3) != 0)
return false;
@@ -807855,7 +809380,7 @@ Index: gcc/config/rs6000/rs6000.c
extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
if (extra < 0)
extra = 0;
-@@ -7023,13 +7364,14 @@
+@@ -7023,13 +7376,14 @@
case TImode:
case TFmode:
case KFmode:
@@ -807876,7 +809401,7 @@ Index: gcc/config/rs6000/rs6000.c
break;
case V4HImode:
-@@ -7096,6 +7438,11 @@
+@@ -7096,6 +7450,11 @@
if (GET_CODE (op) != SYMBOL_REF)
return false;
@@ -807888,7 +809413,7 @@ Index: gcc/config/rs6000/rs6000.c
dsize = GET_MODE_SIZE (mode);
decl = SYMBOL_REF_DECL (op);
if (!decl)
-@@ -7250,6 +7597,9 @@
+@@ -7250,6 +7609,9 @@
return false;
if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
return false;
@@ -807898,7 +809423,7 @@ Index: gcc/config/rs6000/rs6000.c
if (!reg_offset_addressing_ok_p (mode))
return virtual_stack_registers_memory_p (x);
if (legitimate_constant_pool_address_p (x, mode, strict || lra_in_progress))
-@@ -7388,6 +7738,9 @@
+@@ -7388,6 +7750,9 @@
return false;
if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
return false;
@@ -807908,7 +809433,7 @@ Index: gcc/config/rs6000/rs6000.c
/* Restrict addressing for DI because of our SUBREG hackery. */
if (TARGET_E500_DOUBLE && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
return false;
-@@ -7399,7 +7752,7 @@
+@@ -7399,7 +7764,7 @@
if (DEFAULT_ABI == ABI_V4 && flag_pic)
return false;
@@ -807917,7 +809442,7 @@ Index: gcc/config/rs6000/rs6000.c
push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
recognizes some LO_SUM addresses as valid although this
function says opposite. In most cases, LRA through different
-@@ -7453,7 +7806,8 @@
+@@ -7453,7 +7818,8 @@
{
unsigned int extra;
@@ -807927,7 +809452,7 @@ Index: gcc/config/rs6000/rs6000.c
{
if (virtual_stack_registers_memory_p (x))
return x;
-@@ -8149,12 +8503,16 @@
+@@ -8149,12 +8515,16 @@
{
bool reg_offset_p = reg_offset_addressing_ok_p (mode);
@@ -807947,7 +809472,7 @@ Index: gcc/config/rs6000/rs6000.c
reg_offset_p = false;
/* We must recognize output that we have already generated ourselves. */
-@@ -8164,6 +8522,11 @@
+@@ -8164,6 +8534,11 @@
&& GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
&& GET_CODE (XEXP (x, 1)) == CONST_INT)
{
@@ -807959,7 +809484,7 @@ Index: gcc/config/rs6000/rs6000.c
push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
opnum, (enum reload_type) type);
-@@ -8175,6 +8538,11 @@
+@@ -8175,6 +8550,11 @@
if (GET_CODE (x) == LO_SUM
&& GET_CODE (XEXP (x, 0)) == HIGH)
{
@@ -807971,7 +809496,7 @@ Index: gcc/config/rs6000/rs6000.c
push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
opnum, (enum reload_type) type);
-@@ -8207,6 +8575,11 @@
+@@ -8207,6 +8587,11 @@
{
rtx hi = gen_rtx_HIGH (Pmode, copy_rtx (x));
x = gen_rtx_LO_SUM (Pmode, hi, x);
@@ -807983,7 +809508,7 @@ Index: gcc/config/rs6000/rs6000.c
push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
opnum, (enum reload_type) type);
-@@ -8244,6 +8617,11 @@
+@@ -8244,6 +8629,11 @@
GEN_INT (high)),
GEN_INT (low));
@@ -807995,7 +809520,7 @@ Index: gcc/config/rs6000/rs6000.c
push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
opnum, (enum reload_type) type);
-@@ -8304,6 +8682,11 @@
+@@ -8304,6 +8694,11 @@
x = gen_rtx_LO_SUM (GET_MODE (x),
gen_rtx_HIGH (Pmode, x), x);
@@ -808007,7 +809532,7 @@ Index: gcc/config/rs6000/rs6000.c
push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
opnum, (enum reload_type) type);
-@@ -8337,9 +8720,16 @@
+@@ -8337,9 +8732,16 @@
{
x = create_TOC_reference (x, NULL_RTX);
if (TARGET_CMODEL != CMODEL_SMALL)
@@ -808027,7 +809552,7 @@ Index: gcc/config/rs6000/rs6000.c
*win = 1;
return x;
}
-@@ -8395,6 +8785,7 @@
+@@ -8395,6 +8797,7 @@
rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict)
{
bool reg_offset_p = reg_offset_addressing_ok_p (mode);
@@ -808035,7 +809560,7 @@ Index: gcc/config/rs6000/rs6000.c
/* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
if (VECTOR_MEM_ALTIVEC_P (mode)
-@@ -8414,15 +8805,26 @@
+@@ -8414,15 +8817,26 @@
return 1;
if (virtual_stack_registers_memory_p (x))
return 1;
@@ -808070,7 +809595,7 @@ Index: gcc/config/rs6000/rs6000.c
/* For TImode, if we have load/store quad and TImode in VSX registers, only
allow register indirect addresses. This will allow the values to go in
either GPRs or VSX registers without reloading. The vector types would
-@@ -8461,7 +8863,8 @@
+@@ -8461,7 +8875,8 @@
&& legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict)))
&& rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
return 1;
@@ -808080,7 +809605,128 @@ Index: gcc/config/rs6000/rs6000.c
return 1;
return 0;
}
-@@ -12260,7 +12663,7 @@
+@@ -10044,6 +10459,35 @@
+ return must_pass_in_stack_var_size_or_pad (mode, type);
+ }
+
++static inline bool
++is_complex_IBM_long_double (machine_mode mode)
++{
++ return mode == ICmode || (!TARGET_IEEEQUAD && mode == TCmode);
++}
++
++/* Whether ABI_V4 passes MODE args to a function in floating point
++ registers. */
++
++static bool
++abi_v4_pass_in_fpr (machine_mode mode)
++{
++ if (!TARGET_FPRS || !TARGET_HARD_FLOAT)
++ return false;
++ if (TARGET_SINGLE_FLOAT && mode == SFmode)
++ return true;
++ if (TARGET_DOUBLE_FLOAT && mode == DFmode)
++ return true;
++ /* ABI_V4 passes complex IBM long double in 8 gprs.
++ Stupid, but we can't change the ABI now. */
++ if (is_complex_IBM_long_double (mode))
++ return false;
++ if (FLOAT128_2REG_P (mode))
++ return true;
++ if (DECIMAL_FLOAT_MODE_P (mode))
++ return true;
++ return false;
++}
++
+ /* If defined, a C expression which determines whether, and in which
+ direction, to pad out an argument with extra space. The value
+ should be of type `enum direction': either `upward' to pad above
+@@ -10128,6 +10572,7 @@
+ && (GET_MODE_SIZE (mode) == 8
+ || (TARGET_HARD_FLOAT
+ && TARGET_FPRS
++ && !is_complex_IBM_long_double (mode)
+ && FLOAT128_2REG_P (mode))))
+ return 64;
+ else if (FLOAT128_VECTOR_P (mode))
+@@ -10507,11 +10952,7 @@
+ }
+ else if (DEFAULT_ABI == ABI_V4)
+ {
+- if (TARGET_HARD_FLOAT && TARGET_FPRS
+- && ((TARGET_SINGLE_FLOAT && mode == SFmode)
+- || (TARGET_DOUBLE_FLOAT && mode == DFmode)
+- || FLOAT128_2REG_P (mode)
+- || DECIMAL_FLOAT_MODE_P (mode)))
++ if (abi_v4_pass_in_fpr (mode))
+ {
+ /* _Decimal128 must use an even/odd register pair. This assumes
+ that the register number is odd when fregno is odd. */
+@@ -11168,11 +11609,7 @@
+
+ else if (abi == ABI_V4)
+ {
+- if (TARGET_HARD_FLOAT && TARGET_FPRS
+- && ((TARGET_SINGLE_FLOAT && mode == SFmode)
+- || (TARGET_DOUBLE_FLOAT && mode == DFmode)
+- || FLOAT128_2REG_P (mode)
+- || DECIMAL_FLOAT_MODE_P (mode)))
++ if (abi_v4_pass_in_fpr (mode))
+ {
+ /* _Decimal128 must use an even/odd register pair. This assumes
+ that the register number is odd when fregno is odd. */
+@@ -12093,12 +12530,8 @@
+ rsize = (size + 3) / 4;
+ align = 1;
+
+- if (TARGET_HARD_FLOAT && TARGET_FPRS
+- && ((TARGET_SINGLE_FLOAT && TYPE_MODE (type) == SFmode)
+- || (TARGET_DOUBLE_FLOAT
+- && (TYPE_MODE (type) == DFmode
+- || FLOAT128_2REG_P (TYPE_MODE (type))
+- || DECIMAL_FLOAT_MODE_P (TYPE_MODE (type))))))
++ machine_mode mode = TYPE_MODE (type);
++ if (abi_v4_pass_in_fpr (mode))
+ {
+ /* FP args go in FP registers, if present. */
+ reg = fpr;
+@@ -12105,7 +12538,7 @@
+ n_reg = (size + 7) / 8;
+ sav_ofs = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4) * 4;
+ sav_scale = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4);
+- if (TYPE_MODE (type) != SFmode && TYPE_MODE (type) != SDmode)
++ if (mode != SFmode && mode != SDmode)
+ align = 8;
+ }
+ else
+@@ -12125,7 +12558,7 @@
+ addr = create_tmp_var (ptr_type_node, "addr");
+
+ /* AltiVec vectors never go in registers when -mabi=altivec. */
+- if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
++ if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
+ align = 16;
+ else
+ {
+@@ -12146,7 +12579,7 @@
+ }
+ /* _Decimal128 is passed in even/odd fpr pairs; the stored
+ reg number is 0 for f1, so we want to make it odd. */
+- else if (reg == fpr && TYPE_MODE (type) == TDmode)
++ else if (reg == fpr && mode == TDmode)
+ {
+ t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
+ build_int_cst (TREE_TYPE (reg), 1));
+@@ -12173,7 +12606,7 @@
+ FP register for 32-bit binaries. */
+ if (TARGET_32BIT
+ && TARGET_HARD_FLOAT && TARGET_FPRS
+- && TYPE_MODE (type) == SDmode)
++ && mode == SDmode)
+ t = fold_build_pointer_plus_hwi (t, size);
+
+ gimplify_assign (addr, t, pre_p);
+@@ -12260,7 +12693,7 @@
/* const function, function only depends on the inputs. */
TREE_READONLY (t) = 1;
TREE_NOTHROW (t) = 1;
@@ -808089,7 +809735,7 @@ Index: gcc/config/rs6000/rs6000.c
}
else if ((classify & RS6000_BTC_PURE) != 0)
{
-@@ -12268,7 +12671,7 @@
+@@ -12268,7 +12701,7 @@
external state. */
DECL_PURE_P (t) = 1;
TREE_NOTHROW (t) = 1;
@@ -808098,7 +809744,7 @@ Index: gcc/config/rs6000/rs6000.c
}
else if ((classify & RS6000_BTC_FP) != 0)
{
-@@ -12300,6 +12703,7 @@
+@@ -12300,6 +12733,7 @@
/* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
@@ -808106,7 +809752,7 @@ Index: gcc/config/rs6000/rs6000.c
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
-@@ -12312,6 +12716,7 @@
+@@ -12312,6 +12746,7 @@
#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
@@ -808114,7 +809760,7 @@ Index: gcc/config/rs6000/rs6000.c
#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
-@@ -12333,6 +12738,7 @@
+@@ -12333,6 +12768,7 @@
/* DST operations: void foo (void *, const int, const char). */
@@ -808122,7 +809768,7 @@ Index: gcc/config/rs6000/rs6000.c
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
-@@ -12345,6 +12751,7 @@
+@@ -12345,6 +12781,7 @@
#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
@@ -808130,7 +809776,7 @@ Index: gcc/config/rs6000/rs6000.c
#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
-@@ -12366,6 +12773,7 @@
+@@ -12366,6 +12803,7 @@
/* Simple binary operations: VECc = foo (VECa, VECb). */
@@ -808138,7 +809784,7 @@ Index: gcc/config/rs6000/rs6000.c
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
-@@ -12378,6 +12786,7 @@
+@@ -12378,6 +12816,7 @@
#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
@@ -808146,7 +809792,7 @@ Index: gcc/config/rs6000/rs6000.c
#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
{ MASK, ICODE, NAME, ENUM },
-@@ -12397,6 +12806,7 @@
+@@ -12397,6 +12836,7 @@
#include "rs6000-builtin.def"
};
@@ -808154,7 +809800,7 @@ Index: gcc/config/rs6000/rs6000.c
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
-@@ -12409,6 +12819,7 @@
+@@ -12409,6 +12849,7 @@
#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
@@ -808162,7 +809808,7 @@ Index: gcc/config/rs6000/rs6000.c
#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
-@@ -12431,6 +12842,7 @@
+@@ -12431,6 +12872,7 @@
};
/* SPE predicates. */
@@ -808170,7 +809816,7 @@ Index: gcc/config/rs6000/rs6000.c
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
-@@ -12443,6 +12855,7 @@
+@@ -12443,6 +12885,7 @@
#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
@@ -808178,7 +809824,7 @@ Index: gcc/config/rs6000/rs6000.c
#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
-@@ -12463,6 +12876,7 @@
+@@ -12463,6 +12906,7 @@
};
/* SPE evsel predicates. */
@@ -808186,7 +809832,7 @@ Index: gcc/config/rs6000/rs6000.c
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
-@@ -12475,6 +12889,7 @@
+@@ -12475,6 +12919,7 @@
#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
@@ -808194,7 +809840,7 @@ Index: gcc/config/rs6000/rs6000.c
#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
-@@ -12495,6 +12910,7 @@
+@@ -12495,6 +12940,7 @@
};
/* PAIRED predicates. */
@@ -808202,7 +809848,7 @@ Index: gcc/config/rs6000/rs6000.c
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
-@@ -12507,6 +12923,7 @@
+@@ -12507,6 +12953,7 @@
#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
@@ -808210,7 +809856,7 @@ Index: gcc/config/rs6000/rs6000.c
#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
-@@ -12528,6 +12945,7 @@
+@@ -12528,6 +12975,7 @@
/* ABS* operations. */
@@ -808218,7 +809864,7 @@ Index: gcc/config/rs6000/rs6000.c
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
-@@ -12540,6 +12958,7 @@
+@@ -12540,6 +12988,7 @@
#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
@@ -808226,7 +809872,7 @@ Index: gcc/config/rs6000/rs6000.c
#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
-@@ -12562,6 +12981,7 @@
+@@ -12562,6 +13011,7 @@
/* Simple unary operations: VECb = foo (unsigned literal) or VECb =
foo (VECa). */
@@ -808234,7 +809880,7 @@ Index: gcc/config/rs6000/rs6000.c
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
-@@ -12574,6 +12994,7 @@
+@@ -12574,6 +13024,7 @@
#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
@@ -808242,7 +809888,7 @@ Index: gcc/config/rs6000/rs6000.c
#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
{ MASK, ICODE, NAME, ENUM },
-@@ -12593,7 +13014,43 @@
+@@ -12593,7 +13044,43 @@
#include "rs6000-builtin.def"
};
@@ -808286,7 +809932,7 @@ Index: gcc/config/rs6000/rs6000.c
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
-@@ -12606,6 +13063,7 @@
+@@ -12606,6 +13093,7 @@
#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
@@ -808294,7 +809940,7 @@ Index: gcc/config/rs6000/rs6000.c
#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
-@@ -12625,6 +13083,7 @@
+@@ -12625,6 +13113,7 @@
#include "rs6000-builtin.def"
};
@@ -808302,7 +809948,7 @@ Index: gcc/config/rs6000/rs6000.c
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
-@@ -14129,6 +14588,47 @@
+@@ -14129,6 +14618,47 @@
case VSX_BUILTIN_STXVW4X_V16QI:
return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp);
@@ -808350,7 +809996,7 @@ Index: gcc/config/rs6000/rs6000.c
case ALTIVEC_BUILTIN_MFVSCR:
icode = CODE_FOR_altivec_mfvscr;
tmode = insn_data[icode].operand[0].mode;
-@@ -14323,6 +14823,46 @@
+@@ -14323,6 +14853,46 @@
case VSX_BUILTIN_LXVW4X_V16QI:
return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi,
exp, target, false);
@@ -808397,7 +810043,7 @@ Index: gcc/config/rs6000/rs6000.c
break;
default:
break;
-@@ -14792,6 +15332,8 @@
+@@ -14792,6 +15362,8 @@
error ("Builtin function %s requires the -mhard-dfp option", name);
else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0)
error ("Builtin function %s requires the -mpower8-vector option", name);
@@ -808406,7 +810052,7 @@ Index: gcc/config/rs6000/rs6000.c
else if ((fnmask & (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
== (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
error ("Builtin function %s requires the -mhard-float and"
-@@ -14990,9 +15532,11 @@
+@@ -14990,9 +15562,11 @@
}
unsigned attr = rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK;
@@ -808419,7 +810065,7 @@ Index: gcc/config/rs6000/rs6000.c
/* Handle simple unary operations. */
d = bdesc_1arg;
-@@ -15012,6 +15556,12 @@
+@@ -15012,6 +15586,12 @@
if (d->code == fcode)
return rs6000_expand_ternop_builtin (d->icode, exp, target);
@@ -808432,7 +810078,7 @@ Index: gcc/config/rs6000/rs6000.c
gcc_unreachable ();
}
-@@ -15816,10 +16366,44 @@
+@@ -15816,10 +16396,44 @@
VSX_BUILTIN_STXVW4X_V8HI);
def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid,
VSX_BUILTIN_STXVW4X_V16QI);
@@ -808477,7 +810123,7 @@ Index: gcc/config/rs6000/rs6000.c
def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
-@@ -16351,10 +16935,6 @@
+@@ -16351,10 +16965,6 @@
while (num_args > 0 && h.mode[num_args] == VOIDmode)
num_args--;
@@ -808488,7 +810134,7 @@ Index: gcc/config/rs6000/rs6000.c
ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]];
if (!ret_type && h.uns_p[0])
ret_type = builtin_mode_to_type[h.mode[0]][0];
-@@ -16406,6 +16986,7 @@
+@@ -16406,6 +17016,7 @@
tree opaque_ftype_opaque = NULL_TREE;
tree opaque_ftype_opaque_opaque = NULL_TREE;
tree opaque_ftype_opaque_opaque_opaque = NULL_TREE;
@@ -808496,7 +810142,7 @@ Index: gcc/config/rs6000/rs6000.c
tree v2si_ftype_qi = NULL_TREE;
tree v2si_ftype_v2si_qi = NULL_TREE;
tree v2si_ftype_int_qi = NULL_TREE;
-@@ -16622,6 +17203,64 @@
+@@ -16622,6 +17233,64 @@
def_builtin (d->name, type, d->code);
}
@@ -808561,7 +810207,52 @@ Index: gcc/config/rs6000/rs6000.c
}
/* Set up AIX/Darwin/64-bit Linux quad floating point routines. */
-@@ -18152,6 +18791,16 @@
+@@ -18006,25 +18675,33 @@
+ addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX]
+ & ~RELOAD_REG_AND_M16);
+
+- else
++ /* If the register allocator hasn't made up its mind yet on the register
++ class to use, settle on defaults to use. */
++ else if (rclass == NO_REGS)
+ {
+- if (TARGET_DEBUG_ADDR)
+- fprintf (stderr,
+- "rs6000_secondary_reload_memory: mode = %s, class = %s, "
+- "class is not GPR, FPR, VMX\n",
+- GET_MODE_NAME (mode), reg_class_names[rclass]);
++ addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_ANY]
++ & ~RELOAD_REG_AND_M16);
+
+- return -1;
++ if ((addr_mask & RELOAD_REG_MULTIPLE) != 0)
++ addr_mask &= ~(RELOAD_REG_INDEXED
++ | RELOAD_REG_PRE_INCDEC
++ | RELOAD_REG_PRE_MODIFY);
+ }
+
++ else
++ addr_mask = 0;
++
+ /* If the register isn't valid in this register class, just return now. */
+ if ((addr_mask & RELOAD_REG_VALID) == 0)
+ {
+ if (TARGET_DEBUG_ADDR)
+- fprintf (stderr,
+- "rs6000_secondary_reload_memory: mode = %s, class = %s, "
+- "not valid in class\n",
+- GET_MODE_NAME (mode), reg_class_names[rclass]);
++ {
++ fprintf (stderr,
++ "rs6000_secondary_reload_memory: mode = %s, class = %s, "
++ "not valid in class\n",
++ GET_MODE_NAME (mode), reg_class_names[rclass]);
++ debug_rtx (addr);
++ }
+
+ return -1;
+ }
+@@ -18152,6 +18829,16 @@
}
}
@@ -808578,7 +810269,7 @@ Index: gcc/config/rs6000/rs6000.c
/* Make sure the register class can handle offset addresses. */
else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
{
-@@ -18158,7 +18807,7 @@
+@@ -18158,7 +18845,7 @@
if ((addr_mask & RELOAD_REG_OFFSET) == 0)
{
extra_cost = 1;
@@ -808587,7 +810278,7 @@ Index: gcc/config/rs6000/rs6000.c
}
}
-@@ -18171,8 +18820,15 @@
+@@ -18171,8 +18858,15 @@
break;
case LO_SUM:
@@ -808604,7 +810295,7 @@ Index: gcc/config/rs6000/rs6000.c
fail_msg = "bad LO_SUM";
extra_cost = -1;
}
-@@ -18188,8 +18844,17 @@
+@@ -18188,8 +18882,17 @@
case CONST:
case SYMBOL_REF:
case LABEL_REF:
@@ -808624,7 +810315,7 @@ Index: gcc/config/rs6000/rs6000.c
break;
/* TOC references look like offsetable memory. */
-@@ -18200,6 +18865,12 @@
+@@ -18200,6 +18903,12 @@
extra_cost = -1;
}
@@ -808637,7 +810328,17 @@ Index: gcc/config/rs6000/rs6000.c
else if ((addr_mask & RELOAD_REG_OFFSET) == 0)
{
extra_cost = 1;
-@@ -18827,6 +19498,16 @@
+@@ -18653,6 +19362,9 @@
+ fprintf (stderr, ", reload func = %s, extra cost = %d",
+ insn_data[sri->icode].name, sri->extra_cost);
+
++ else if (sri->extra_cost > 0)
++ fprintf (stderr, ", extra cost = %d", sri->extra_cost);
++
+ fputs ("\n", stderr);
+ debug_rtx (x);
+ }
+@@ -18827,6 +19539,16 @@
}
}
@@ -808654,7 +810355,7 @@ Index: gcc/config/rs6000/rs6000.c
/* Make sure the register class can handle offset addresses. */
else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
{
-@@ -18857,6 +19538,13 @@
+@@ -18857,6 +19579,13 @@
}
}
@@ -808668,7 +810369,24 @@ Index: gcc/config/rs6000/rs6000.c
/* Make sure the register class can handle offset addresses. */
else if (legitimate_lo_sum_address_p (mode, addr, false))
{
-@@ -19067,7 +19755,8 @@
+@@ -19046,6 +19775,16 @@
+ machine_mode mode = GET_MODE (x);
+ bool is_constant = CONSTANT_P (x);
+
++ /* If a mode can't go in FPR/ALTIVEC/VSX registers, don't return a preferred
++ reload class for it. */
++ if ((rclass == ALTIVEC_REGS || rclass == VSX_REGS)
++ && (reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID) == 0)
++ return NO_REGS;
++
++ if ((rclass == FLOAT_REGS || rclass == VSX_REGS)
++ && (reg_addr[mode].addr_mask[RELOAD_REG_FPR] & RELOAD_REG_VALID) == 0)
++ return NO_REGS;
++
+ /* For VSX, see if we should prefer FLOAT_REGS or ALTIVEC_REGS. Do not allow
+ the reloading of address expressions using PLUS into floating point
+ registers. */
+@@ -19067,7 +19806,8 @@
}
/* D-form addressing can easily reload the value. */
@@ -808678,7 +810396,33 @@ Index: gcc/config/rs6000/rs6000.c
return rclass;
/* If this is a scalar floating point value and we don't have D-form
-@@ -19483,8 +20172,16 @@
+@@ -19095,6 +19835,25 @@
+ return NO_REGS;
+ }
+
++ /* If we haven't picked a register class, and the type is a vector or
++ floating point type, prefer to use the VSX, FPR, or Altivec register
++ classes. */
++ if (rclass == NO_REGS)
++ {
++ if (TARGET_VSX && VECTOR_MEM_VSX_OR_P8_VECTOR_P (mode))
++ return VSX_REGS;
++
++ if (TARGET_ALTIVEC && VECTOR_MEM_ALTIVEC_P (mode))
++ return ALTIVEC_REGS;
++
++ if (DECIMAL_FLOAT_MODE_P (mode))
++ return TARGET_DFP ? FLOAT_REGS : NO_REGS;
++
++ if (TARGET_FPRS && TARGET_HARD_FLOAT && FLOAT_MODE_P (mode)
++ && (reg_addr[mode].addr_mask[RELOAD_REG_FPR] & RELOAD_REG_VALID) == 0)
++ return FLOAT_REGS;
++ }
++
+ if (GET_MODE_CLASS (mode) == MODE_INT && rclass == NON_SPECIAL_REGS)
+ return GENERAL_REGS;
+
+@@ -19483,8 +20242,16 @@
else if (TARGET_VSX && dest_vsx_p)
{
@@ -808696,7 +810440,7 @@ Index: gcc/config/rs6000/rs6000.c
else
return "lxvd2x %x0,%y1";
}
-@@ -19513,8 +20210,16 @@
+@@ -19513,8 +20280,16 @@
else if (TARGET_VSX && src_vsx_p)
{
@@ -808714,7 +810458,7 @@ Index: gcc/config/rs6000/rs6000.c
else
return "stxvd2x %x1,%y0";
}
-@@ -19536,10 +20241,8 @@
+@@ -19536,10 +20311,8 @@
if (dest_gpr_p)
return "#";
@@ -808727,7 +810471,7 @@ Index: gcc/config/rs6000/rs6000.c
return output_vec_const_move (operands);
}
-@@ -21747,6 +22450,101 @@
+@@ -21747,6 +22520,101 @@
return 1;
}
@@ -808829,7 +810573,7 @@ Index: gcc/config/rs6000/rs6000.c
/* Emit a conditional move: move TRUE_COND to DEST if OP of the
operands of the last comparison is nonzero/true, FALSE_COND if it
is zero/false. Return 0 if the hardware has no such operation. */
-@@ -21773,6 +22571,18 @@
+@@ -21773,6 +22641,18 @@
if (GET_MODE (false_cond) != result_mode)
return 0;
@@ -808848,7 +810592,7 @@ Index: gcc/config/rs6000/rs6000.c
/* Don't allow using floating point comparisons for integer results for
now. */
if (FLOAT_MODE_P (compare_mode) && !FLOAT_MODE_P (result_mode))
-@@ -25949,7 +26759,7 @@
+@@ -25949,7 +26829,7 @@
if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
{
rtx areg, savereg, mem;
@@ -808857,7 +810601,7 @@ Index: gcc/config/rs6000/rs6000.c
offset = (info->altivec_save_offset + frame_off
+ 16 * (i - info->first_altivec_reg_save));
-@@ -25956,18 +26766,30 @@
+@@ -25956,18 +26836,30 @@
savereg = gen_rtx_REG (V4SImode, i);
@@ -808898,7 +810642,7 @@ Index: gcc/config/rs6000/rs6000.c
rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
areg, GEN_INT (offset));
-@@ -26687,23 +27509,35 @@
+@@ -26687,23 +27579,35 @@
for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
{
@@ -808948,7 +810692,7 @@ Index: gcc/config/rs6000/rs6000.c
}
}
-@@ -26890,23 +27724,35 @@
+@@ -26890,23 +27794,35 @@
for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
{
@@ -808998,7 +810742,7 @@ Index: gcc/config/rs6000/rs6000.c
}
}
-@@ -27724,6 +28570,11 @@
+@@ -27724,6 +28640,11 @@
const0_rtx, const0_rtx));
call_fusage = NULL_RTX;
use_reg (&call_fusage, r12);
@@ -809010,7 +810754,7 @@ Index: gcc/config/rs6000/rs6000.c
add_function_usage_to (insn, call_fusage);
emit_insn (gen_frame_load (r0, r1, info->lr_save_offset));
insn = emit_move_insn (lr, r0);
-@@ -33448,17 +34299,25 @@
+@@ -33448,17 +34369,25 @@
if (!REG_P (target))
tmp = gen_reg_rtx (mode);
@@ -809046,7 +810790,23 @@ Index: gcc/config/rs6000/rs6000.c
/* Copy into target, possibly by way of a register. */
if (!REG_P (target))
-@@ -34056,7 +34915,7 @@
+@@ -33869,8 +34798,14 @@
+ machine_mode inner = GET_MODE_INNER (mode);
+ unsigned int inner_bytes = GET_MODE_UNIT_SIZE (mode);
+
+- if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
++ if (TARGET_FLOAT128
++ && (mode == KCmode
++ || (mode == TCmode && TARGET_IEEEQUAD)))
++ regno = ALTIVEC_ARG_RETURN;
++
++ else if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
+ regno = FP_ARG_RETURN;
++
+ else
+ {
+ regno = GP_ARG_RETURN;
+@@ -34056,7 +34991,7 @@
static bool
rs6000_lra_p (void)
{
@@ -809055,7 +810815,7 @@ Index: gcc/config/rs6000/rs6000.c
}
/* Given FROM and TO register numbers, say whether this elimination is allowed.
-@@ -34417,7 +35276,8 @@
+@@ -34417,7 +35352,8 @@
{ "power8-fusion", OPTION_MASK_P8_FUSION, false, true },
{ "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true },
{ "power8-vector", OPTION_MASK_P8_VECTOR, false, true },
@@ -809065,7 +810825,7 @@ Index: gcc/config/rs6000/rs6000.c
{ "power9-fusion", OPTION_MASK_P9_FUSION, false, true },
{ "power9-minmax", OPTION_MASK_P9_MINMAX, false, true },
{ "power9-vector", OPTION_MASK_P9_VECTOR, false, true },
-@@ -34474,6 +35334,7 @@
+@@ -34474,6 +35410,7 @@
{ "popcntd", RS6000_BTM_POPCNTD, false, false },
{ "cell", RS6000_BTM_CELL, false, false },
{ "power8-vector", RS6000_BTM_P8_VECTOR, false, false },
@@ -809073,7 +810833,7 @@ Index: gcc/config/rs6000/rs6000.c
{ "crypto", RS6000_BTM_CRYPTO, false, false },
{ "htm", RS6000_BTM_HTM, false, false },
{ "hard-dfp", RS6000_BTM_DFP, false, false },
-@@ -35049,7 +35910,9 @@
+@@ -35049,7 +35986,9 @@
size_t i;
size_t start_column = 0;
size_t cur_column;
@@ -809084,7 +810844,7 @@ Index: gcc/config/rs6000/rs6000.c
const char *comma = "";
if (indent)
-@@ -35067,27 +35930,45 @@
+@@ -35067,27 +36006,45 @@
cur_column = start_column;
for (i = 0; i < num_elements; i++)
{
@@ -809747,6 +811507,23 @@ Index: gcc/config/rs6000/rs6000.h
===================================================================
--- a/src/gcc/config/rs6000/rs6000.h (.../tags/gcc_6_1_0_release)
+++ b/src/gcc/config/rs6000/rs6000.h (.../branches/gcc-6-branch)
+@@ -418,12 +418,12 @@
+ Similarly IFmode is the IBM long double format even if the default is IEEE
+ 128-bit. */
+ #define FLOAT128_IEEE_P(MODE) \
+- (((MODE) == TFmode && TARGET_IEEEQUAD) \
+- || ((MODE) == KFmode))
++ ((TARGET_IEEEQUAD && ((MODE) == TFmode || (MODE) == TCmode)) \
++ || ((MODE) == KFmode) || ((MODE) == KCmode))
+
+ #define FLOAT128_IBM_P(MODE) \
+- (((MODE) == TFmode && !TARGET_IEEEQUAD) \
+- || ((MODE) == IFmode))
++ ((!TARGET_IEEEQUAD && ((MODE) == TFmode || (MODE) == TCmode)) \
++ || ((MODE) == IFmode) || ((MODE) == ICmode))
+
+ /* Helper macros to say whether a 128-bit floating point type can go in a
+ single vector register, or whether it needs paired scalar values. */
@@ -594,6 +594,15 @@
in the register. */
#define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP)
@@ -809783,7 +811560,18 @@ Index: gcc/config/rs6000/rs6000.h
/* For power systems, we want to enable Altivec and VSX builtins even if the
user did not use -maltivec or -mvsx to allow the builtins to be used inside
of #pragma GCC target or the target attribute to change the code level for a
-@@ -2638,7 +2653,9 @@
+@@ -1774,7 +1789,9 @@
+ #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
+ #define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \
+ : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
+-#define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? ALTIVEC_ARG_RETURN \
++#define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 \
++ ? (ALTIVEC_ARG_RETURN \
++ + (TARGET_FLOAT128 ? 1 : 0)) \
+ : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
+
+ /* Flags for the call/call_value rtl operations set up by function_arg */
+@@ -2638,7 +2655,9 @@
#define RS6000_BTC_MISC 0x00000000 /* No special attributes. */
#define RS6000_BTC_CONST 0x00000100 /* uses no global state. */
@@ -809794,7 +811582,7 @@ Index: gcc/config/rs6000/rs6000.h
#define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */
#define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */
-@@ -2660,6 +2677,7 @@
+@@ -2660,6 +2679,7 @@
#define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */
#define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */
#define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */
@@ -809802,7 +811590,7 @@ Index: gcc/config/rs6000/rs6000.h
#define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */
#define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */
#define RS6000_BTM_SPE MASK_STRING /* E500 */
-@@ -2673,10 +2691,12 @@
+@@ -2673,10 +2693,12 @@
#define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */
#define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */
#define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */
@@ -809815,7 +811603,7 @@ Index: gcc/config/rs6000/rs6000.h
| RS6000_BTM_CRYPTO \
| RS6000_BTM_FRE \
| RS6000_BTM_FRES \
-@@ -2691,6 +2711,7 @@
+@@ -2691,6 +2713,7 @@
/* Define builtin enum index. */
@@ -809823,7 +811611,7 @@ Index: gcc/config/rs6000/rs6000.h
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
-@@ -2703,6 +2724,7 @@
+@@ -2703,6 +2726,7 @@
#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
@@ -809831,7 +811619,7 @@ Index: gcc/config/rs6000/rs6000.h
#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
-@@ -2722,6 +2744,7 @@
+@@ -2722,6 +2746,7 @@
RS6000_BUILTIN_COUNT
};
--
Alioth's /usr/local/bin/git-commit-notice on /srv/git.debian.org/git/reproducible/gcc-6.git
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