[gcc-6] 174/401: * Update to SVN 20160705 (r237999, 6.1.1) from the gcc-6-branch.
Ximin Luo
infinity0 at debian.org
Wed Apr 5 15:48:56 UTC 2017
This is an automated email from the git hooks/post-receive script.
infinity0 pushed a commit to branch pu/reproducible_builds
in repository gcc-6.
commit fd641fb9d5dfd98beed830318718c37dd79c0aa3
Author: doko <doko at 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca>
Date: Tue Jul 5 09:28:20 2016 +0000
* Update to SVN 20160705 (r237999, 6.1.1) from the gcc-6-branch.
git-svn-id: svn://anonscm.debian.org/gcccvs/branches/sid/gcc-6@8915 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca
---
debian/changelog | 5 +
debian/patches/svn-updates.diff | 2867 +++++++++++++++++++++++++++++++++++----
2 files changed, 2632 insertions(+), 240 deletions(-)
diff --git a/debian/changelog b/debian/changelog
index b199d12..5b12134 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,5 +1,10 @@
gcc-6 (6.1.1-9) UNRELEASED; urgency=medium
+ * Update to SVN 20160705 (r237999, 6.1.1) from the gcc-6-branch.
+ - Fix PR fortran/71717, PR libstdc++/71313, PR c/71685, PR c++/71739,
+ PR target/71670 (PPC), PR middle-end/71626, PR target/71559 (x86),
+ PR target/71656 (PPC), PR target/71698 (PPC), PR driver/71651,
+ PR fortran/71687, PR fortran/71704, PR fortran/71705.
* Mark cross compilers as M-A: foreign. Addresses: #827136.
* On sparc64, configure with --with-cpu-32=ultrasparc, drop the
sparc-force-cpu patch. Closes: #809509.
diff --git a/debian/patches/svn-updates.diff b/debian/patches/svn-updates.diff
index b5e18c0..506e234 100644
--- a/debian/patches/svn-updates.diff
+++ b/debian/patches/svn-updates.diff
@@ -1,10 +1,10 @@
-# DP: updates from the 6 branch upto 20160630 (r237878).
+# DP: updates from the 6 branch upto 20160705 (r237999).
last_update()
{
cat > ${dir}LAST_UPDATED <EOF
-Thu Jun 30 14:07:58 CEST 2016
-Thu Jun 30 12:07:58 UTC 2016 (revision 237878)
+Tue Jul 5 10:54:16 CEST 2016
+Tue Jul 5 08:54:16 UTC 2016 (revision 237999)
EOF
}
@@ -16,7 +16,15 @@ Index: libgomp/ChangeLog
===================================================================
--- a/src/libgomp/ChangeLog (.../tags/gcc_6_1_0_release)
+++ b/src/libgomp/ChangeLog (.../branches/gcc-6-branch)
-@@ -1,3 +1,57 @@
+@@ -1,3 +1,65 @@
++2016-07-02 Jakub Jelinek <jakub at redhat.com>
++
++ Backported from mainline
++ 2016-07-01 Jakub Jelinek <jakub at redhat.com>
++
++ PR fortran/71717
++ * testsuite/libgomp.fortran/associate3.f90: New test.
++
+2016-06-21 Jakub Jelinek <jakub at redhat.com>
+
+ Backported from mainline
@@ -337,6 +345,31 @@ Index: libgomp/testsuite/libgomp.c++/target-21.C
+ abort ();
+ bar3 <S &> (s);
+}
+Index: libgomp/testsuite/libgomp.fortran/associate3.f90
+===================================================================
+--- a/src/libgomp/testsuite/libgomp.fortran/associate3.f90 (.../tags/gcc_6_1_0_release)
++++ b/src/libgomp/testsuite/libgomp.fortran/associate3.f90 (.../branches/gcc-6-branch)
+@@ -0,0 +1,20 @@
++! PR fortran/71717
++! { dg-do run }
++
++ type t
++ real, allocatable :: f(:)
++ end type
++ type (t) :: v
++ integer :: i, j
++ allocate (v%f(4))
++ v%f = 19.
++ i = 5
++ associate (u => v, k => i)
++ !$omp parallel do
++ do j = 1, 4
++ u%f(j) = 21.
++ if (j.eq.1) k = 7
++ end do
++ end associate
++ if (any (v%f(:).ne.21.) .or. i.ne.7) call abort
++end
Index: libgomp/testsuite/libgomp.oacc-c++/template-reduction.C
===================================================================
--- a/src/libgomp/testsuite/libgomp.oacc-c++/template-reduction.C (.../tags/gcc_6_1_0_release)
@@ -1813,6 +1846,15 @@ Index: libstdc++-v3/src/filesystem/ops.cc
}
} // namespace
+@@ -1138,7 +1172,7 @@
+ uintmax_t count = 0;
+ if (ec.value() == 0 && fs.type() == file_type::directory)
+ for (directory_iterator d(p, ec), end; ec.value() == 0 && d != end; ++d)
+- count += fs::remove(d->path(), ec);
++ count += fs::remove_all(d->path(), ec);
+ if (ec.value())
+ return -1;
+ return fs::remove(p, ec) ? ++count : -1; // fs:remove() calls ec.clear()
Index: libstdc++-v3/src/c++11/cow-stdexcept.cc
===================================================================
--- a/src/libstdc++-v3/src/c++11/cow-stdexcept.cc (.../tags/gcc_6_1_0_release)
@@ -2359,7 +2401,15 @@ Index: libstdc++-v3/ChangeLog
===================================================================
--- a/src/libstdc++-v3/ChangeLog (.../tags/gcc_6_1_0_release)
+++ b/src/libstdc++-v3/ChangeLog (.../branches/gcc-6-branch)
-@@ -1,3 +1,146 @@
+@@ -1,3 +1,154 @@
++2016-07-04 Ville Voutilainen <ville.voutilainen at gmail.com>
++
++ PR libstdc++/71313
++ * src/filesystem/ops.cc (remove_all(const path&, error_code&)):
++ Call remove_all for children of a directory.
++ * testsuite/experimental/filesystem/operations/create_directories.cc:
++ Adjust.
++
+2016-06-17 Jonathan Wakely <jwakely at redhat.com>
+
+ PR libstdc++/71545
@@ -3045,6 +3095,20 @@ Index: libstdc++-v3/testsuite/22_locale/codecvt/codecvt_utf8/69703.cc
+ test01();
+ test02();
+}
+Index: libstdc++-v3/testsuite/experimental/filesystem/operations/create_directories.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/experimental/filesystem/operations/create_directories.cc (.../tags/gcc_6_1_0_release)
++++ b/src/libstdc++-v3/testsuite/experimental/filesystem/operations/create_directories.cc (.../branches/gcc-6-branch)
+@@ -65,7 +65,8 @@
+ VERIFY( b );
+ VERIFY( is_directory(p/"./d4/../d5") );
+
+- remove_all(p, ec);
++ std::uintmax_t count = remove_all(p, ec);
++ VERIFY( count == 6 );
+ }
+
+ int
Index: libstdc++-v3/testsuite/experimental/filesystem/operations/canonical.cc
===================================================================
--- a/src/libstdc++-v3/testsuite/experimental/filesystem/operations/canonical.cc (.../tags/gcc_6_1_0_release)
@@ -4470,6 +4534,44 @@ Index: gcc/graphite-isl-ast-to-gimple.c
for (gphi_iterator psi = gsi_start_phis (bb); !gsi_end_p (psi);
gsi_next (&psi))
{
+Index: gcc/opts-common.c
+===================================================================
+--- a/src/gcc/opts-common.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/opts-common.c (.../branches/gcc-6-branch)
+@@ -373,8 +373,9 @@
+ to specific options. We want to do the reverse: to find all the ways
+ that a user could validly spell an option.
+
+- Given valid OPT_TEXT (with a leading dash), add it and all of its valid
+- variant spellings to CANDIDATES, each without a leading dash.
++ Given valid OPT_TEXT (with a leading dash) for OPTION, add it and all
++ of its valid variant spellings to CANDIDATES, each without a leading
++ dash.
+
+ For example, given "-Wabi-tag", the following are added to CANDIDATES:
+ "Wabi-tag"
+@@ -386,9 +387,11 @@
+
+ void
+ add_misspelling_candidates (auto_vec<char *> *candidates,
++ const struct cl_option *option,
+ const char *opt_text)
+ {
+ gcc_assert (candidates);
++ gcc_assert (option);
+ gcc_assert (opt_text);
+ candidates->safe_push (xstrdup (opt_text + 1));
+ for (unsigned i = 0; i < ARRAY_SIZE (option_map); i++)
+@@ -397,6 +400,9 @@
+ const char *new_prefix = option_map[i].new_prefix;
+ size_t new_prefix_len = strlen (new_prefix);
+
++ if (option->cl_reject_negative && option_map[i].negated)
++ continue;
++
+ if (strncmp (opt_text, new_prefix, new_prefix_len) == 0)
+ {
+ char *alternative = concat (opt0 + 1, opt_text + new_prefix_len,
Index: gcc/c-family/c-gimplify.c
===================================================================
--- a/src/gcc/c-family/c-gimplify.c (.../tags/gcc_6_1_0_release)
@@ -4723,7 +4825,16 @@ Index: gcc/c/ChangeLog
===================================================================
--- a/src/gcc/c/ChangeLog (.../tags/gcc_6_1_0_release)
+++ b/src/gcc/c/ChangeLog (.../branches/gcc-6-branch)
-@@ -1,3 +1,35 @@
+@@ -1,3 +1,44 @@
++2016-07-02 Jakub Jelinek <jakub at redhat.com>
++
++ Backported from mainline
++ 2016-06-29 Jakub Jelinek <jakub at redhat.com>
++
++ PR c/71685
++ * c-typeck.c (c_build_qualified_type): Don't clear
++ C_TYPE_INCOMPLETE_VARS for the main variant.
++
+2016-06-10 Thomas Schwinge <thomas at codesourcery.com>
+
+ PR c/71381
@@ -5168,6 +5279,16 @@ Index: gcc/c/c-typeck.c
if (location != UNKNOWN_LOCATION)
protected_set_expr_location (result.value, location);
+@@ -13533,7 +13538,8 @@
+ : build_qualified_type (type, type_quals));
+ /* A variant type does not inherit the list of incomplete vars from the
+ type main variant. */
+- if (RECORD_OR_UNION_TYPE_P (var_type))
++ if (RECORD_OR_UNION_TYPE_P (var_type)
++ && TYPE_MAIN_VARIANT (var_type) != var_type)
+ C_TYPE_INCOMPLETE_VARS (var_type) = 0;
+ return var_type;
+ }
Index: gcc/c/c-tree.h
===================================================================
--- a/src/gcc/c/c-tree.h (.../tags/gcc_6_1_0_release)
@@ -5221,7 +5342,7 @@ Index: gcc/DATESTAMP
+++ b/src/gcc/DATESTAMP (.../branches/gcc-6-branch)
@@ -1 +1 @@
-20160427
-+20160630
++20160705
Index: gcc/tree-ssa-strlen.c
===================================================================
--- a/src/gcc/tree-ssa-strlen.c (.../tags/gcc_6_1_0_release)
@@ -5319,6 +5440,19 @@ Index: gcc/tree-ssa-strlen.c
switch (DECL_FUNCTION_CODE (callee))
{
case BUILT_IN_STRLEN:
+Index: gcc/tree.c
+===================================================================
+--- a/src/gcc/tree.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/tree.c (.../branches/gcc-6-branch)
+@@ -5015,7 +5015,7 @@
+ && TREE_CODE (TREE_VALUE (attr2)) == TREE_LIST)
+ {
+ /* Handle attribute format. */
+- if (is_attribute_p ("format", TREE_PURPOSE (attr1)))
++ if (is_attribute_p ("format", get_attribute_name (attr1)))
+ {
+ attr1 = TREE_VALUE (attr1);
+ attr2 = TREE_VALUE (attr2);
Index: gcc/tree.h
===================================================================
--- a/src/gcc/tree.h (.../tags/gcc_6_1_0_release)
@@ -5388,6 +5522,37 @@ Index: gcc/configure
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for LEON instructions" >&5
$as_echo_n "checking assembler for LEON instructions... " >&6; }
if test "${gcc_cv_as_sparc_leon+set}" = set; then :
+Index: gcc/gcc.c
+===================================================================
+--- a/src/gcc/gcc.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/gcc.c (.../branches/gcc-6-branch)
+@@ -7667,12 +7667,14 @@
+ for (unsigned j = 0; e->values[j].arg != NULL; j++)
+ {
+ char *with_arg = concat (opt_text, e->values[j].arg, NULL);
+- add_misspelling_candidates (m_option_suggestions, with_arg);
++ add_misspelling_candidates (m_option_suggestions, option,
++ with_arg);
+ free (with_arg);
+ }
+ }
+ else
+- add_misspelling_candidates (m_option_suggestions, opt_text);
++ add_misspelling_candidates (m_option_suggestions, option,
++ opt_text);
+ break;
+
+ case OPT_fsanitize_:
+@@ -7696,7 +7698,8 @@
+ /* Add with_arg and all of its variant spellings e.g.
+ "-fno-sanitize=address" to candidates (albeit without
+ leading dashes). */
+- add_misspelling_candidates (m_option_suggestions, with_arg);
++ add_misspelling_candidates (m_option_suggestions, option,
++ with_arg);
+ free (with_arg);
+ }
+ }
Index: gcc/fold-const.c
===================================================================
--- a/src/gcc/fold-const.c (.../tags/gcc_6_1_0_release)
@@ -5795,7 +5960,180 @@ Index: gcc/ChangeLog
===================================================================
--- a/src/gcc/ChangeLog (.../tags/gcc_6_1_0_release)
+++ b/src/gcc/ChangeLog (.../branches/gcc-6-branch)
-@@ -1,3 +1,1334 @@
+@@ -1,3 +1,1507 @@
++2016-07-04 Jakub Jelinek <jakub at redhat.com>
++
++ PR c++/71739
++ * tree.c (attribute_value_equal): Use get_attribute_name instead of
++ directly using TREE_PURPOSE.
++
++2016-07-04 Segher Boessenkool <segher at kernel.crashing.org>
++
++ Backport from mainline
++ 2016-06-27 Segher Boessenkool <segher at kernel.crashing.org>
++
++ PR target/71670
++ * config/rs6000/rs6000.md (ashdi3_extswsli_dot): Use
++ gen_ashdi3_extswsli_dot2 instead of gen_ashdi3_extswsli_dot.
++
++2016-07-02 Jakub Jelinek <jakub at redhat.com>
++
++ Backported from mainline
++ 2016-06-28 Jakub Jelinek <jakub at redhat.com>
++
++ PR middle-end/71626
++ * config/i386/i386.c (ix86_expand_vector_move): For SUBREG of
++ a constant, force its SUBREG_REG into memory or register instead
++ of whole op1.
++
++ 2016-06-20 Jakub Jelinek <jakub at redhat.com>
++
++ PR target/71559
++ * config/i386/i386.c (ix86_fp_cmp_code_to_pcmp_immediate): Fix up
++ returned values and add UN*/LTGT/*ORDERED cases with values matching
++ D operand modifier on vcmp for AVX.
++
++2016-07-01 Kelvin Nilsen <kelvin at gcc.gnu.org>
++
++ Backport from trunk r237659
++ 2016-06-21 Kelvin Nilsen <kelvin at gcc.gnu.org>
++
++ * config/rs6000/rs6000.h: Add conditional preprocessing directives
++ to disable Power9-specific compiler features if HAVE_AS_POWER9 is
++ not defined.
++
++2016-07-01 Peter Bergner <bergner at vnet.ibm.com>
++
++ Backport from trunk
++ 2016-06-27 Peter Bergner <bergner at vnet.ibm.com>
++
++ PR target/71656
++ * config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Add
++ OPTION_MASK_P9_DFORM_VECTOR.
++ * config/rs6000/rs6000.c (rs6000_option_override_internal): Do not
++ disable -mpower9-dform-vector when using reload.
++ (quad_address_p): Remove 'gpr_p' argument and all associated code.
++ New 'strict' argument. Update all callers. Add strict addressing
++ support.
++ (rs6000_legitimate_offset_address_p): Remove call to
++ virtual_stack_registers_memory_p.
++ (rs6000_legitimize_reload_address): Add quad address support.
++ (rs6000_legitimate_address_p): Move call to quad_address_p above
++ call to virtual_stack_registers_memory_p. Adjust quad_address_p args
++ to account for new strict usage.
++ (rs6000_output_move_128bit): Adjust quad_address_p args to account
++ for new strict usage.
++ * config/rs6000/predicates.md (quad_memory_operand): Likewise.
++
++2016-07-01 Bill Schmidt <wschmidt at linux.vnet.ibm.com>
++
++ Backport from mainline
++ 2016-06-24 Bill Schmidt <wschmidt at linux.vnet.ibm.com>
++
++ * config/rs6000/rs6000-builtin.def (BU_FLOAT128_2): New #define.
++ (BU_FLOAT128_1): Likewise.
++ (FABSQ): Likewise.
++ (COPYSIGNQ): Likewise.
++ (RS6000_BUILTIN_NANQ): Likewise.
++ (RS6000_BUILTIN_NANSQ): Likewise.
++ (RS6000_BUILTIN_INFQ): Likewise.
++ (RS6000_BUILTIN_HUGE_VALQ): Likewise.
++ * config/rs6000/rs6000.c (rs6000_fold_builtin): New prototype.
++ (TARGET_FOLD_BUILTIN): New #define.
++ (rs6000_builtin_mask_calculate): Add TARGET_FLOAT128 entry.
++ (rs6000_invalid_builtin): Add handling for RS6000_BTM_FLOAT128.
++ (rs6000_fold_builtin): New target hook implementation, handling
++ folding of 128-bit NaNs and infinities.
++ (rs6000_init_builtins): Initialize const_str_type_node; ensure all
++ entries are filled in to avoid problems during bootstrap
++ self-test; define builtins for 128-bit NaNs and infinities.
++ (rs6000_opt_mask): Add entry for float128.
++ * config/rs6000/rs6000.h (RS6000_BTM_FLOAT128): New #define.
++ (RS6000_BTM_COMMON): Include RS6000_BTM_FLOAT128.
++ (rs6000_builtin_type_index): Add RS6000_BTI_const_str.
++ (const_str_type_node): New #define.
++ * config/rs6000/rs6000.md (copysign<mode>3 for IEEE128): Convert
++ to a define_expand that dispatches to either copysign<mode>3_soft
++ or copysign<mode>3_hard.
++ (copysign<mode>3_hard): Rename from copysign<mode>3.
++ (copysign<mode>3_soft): New define_insn.
++ * doc/extend.texi: Document new builtins.
++
++2016-07-01 Peter Bergner <bergner at vnet.ibm.com>
++
++ Backport from trunk
++ 2016-07-01 Peter Bergner <bergner at vnet.ibm.com>
++
++ PR target/71698
++ * config/rs6000/rs6000.c (rs6000_secondary_reload_simple_move): Disallow
++ TDmode values.
++
++2016-07-01 Kelvin Nilsen <kelvin at gcc.gnu.org>
++
++ Backport from trunk r236992
++ 2016-06-01 Kelvin Nilsen <kelvin at gcc.gnu.org>
++
++ * config/rs6000/altivec.h (vec_slv): New macro.
++ (vec_srv): New macro.
++ * config/rs6000/altivec.md (UNSPEC_VSLV): New value.
++ (UNSPEC_VSRV): New value.
++ (vslv): New insn.
++ (vsrv): New insn.
++ * config/rs6000/rs6000-builtin.def (vslv): New builtin definition.
++ (vsrv): New builtin definition.
++ * config/rs6000/rs6000-c.c (P9V_BUILTIN_VSLV): Macro expansion to
++ define argument types for new builtin.
++ (P9V_BUILTIN_VSRV): Macro expansion to define argument types for
++ new builtin.
++ * doc/extend.texi: Document the new vec_vslv and vec_srv built-in
++ functions.
++
++2016-07-01 Eric Botcazou <ebotcazou at adacore.com>
++
++ * config/arm/arm.c (arm_function_ok_for_sibcall): Add another check
++ for NULL decl.
++
++2016-06-30 Kelvin Nilsen <kelvin at gcc.gnu.org>
++
++ Backport from trunk r237390
++ 2016-06-13 Kelvin Nilsen <kelvin at gcc.gnu.org>
++
++ * config/rs6000/altivec.h (vec_absd): New macro for vector absolute
++ difference unsigned.
++ (vec_absdb): New macro for vector absolute difference unsigned
++ byte.
++ (vec_absdh): New macro for vector absolute difference unsigned
++ half-word.
++ (vec_absdw): New macro for vector absolute difference unsigned word.
++ * config/rs6000/altivec.md (UNSPEC_VADU): New value.
++ (vadu<mode>3): New insn.
++ (*p9_vadu<mode>3): New insn.
++ * config/rs6000/rs6000-builtin.def (vadub): New built-in
++ definition.
++ (vaduh): New built-in definition.
++ (vaduw): New built-in definition.
++ (vadu): New overloaded built-in definition.
++ (vadub): New overloaded built-in definition.
++ (vaduh): New overloaded built-in definition.
++ (vaduw): New overloaded built-in definition.
++ * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
++ overloaded vector absolute difference unsigned functions.
++ * doc/extend.texi (PowerPC AltiVec Built-in Functions): Document
++ the ISA 3.0 vector absolute difference unsigned built-in functions.
++
++2016-06-30 David Malcolm <dmalcolm at redhat.com>
++
++ Backport from trunk r237880.
++ 2016-06-30 David Malcolm <dmalcolm at redhat.com>
++
++ PR driver/71651
++ * gcc.c (driver::build_option_suggestions): Pass "option" to
++ add_misspelling_candidates.
++ * opts-common.c (add_misspelling_candidates): Add "option" param;
++ use it to avoid adding negated forms for options marked with
++ RejectNegative.
++ * opts.h (add_misspelling_candidates): Add "option" param.
++
+2016-06-30 Jakub Jelinek <jakub at redhat.com>
+
+ PR middle-end/71693
@@ -7130,7 +7468,7 @@ Index: gcc/ChangeLog
2016-04-27 Release Manager
* GCC 6.1.0 released.
-@@ -49,7 +1380,7 @@
+@@ -49,7 +1553,7 @@
constant boolean.
2016-04-20 Andrew Pinski <apinski at cavium.com>
@@ -7565,6 +7903,35 @@ Index: gcc/testsuite/gcc.target/powerpc/vsx-elemrev-4.c
+{
+ vec_xst (vuc, 0, ucp);
+}
+Index: gcc/testsuite/gcc.target/powerpc/vadsduh-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vadsduh-1.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vadsduh-1.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,24 @@
++/* { dg-do compile { target { powerpc*-*-* } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-skip-if "" { powerpc*-*-aix* } } */
++/* { dg-options "-mcpu=power9" } */
++
++/* This test should succeed on both 32- and 64-bit configurations. */
++#include <altivec.h>
++
++__vector unsigned short
++doAbsoluteDifferenceUnsigned (__vector unsigned short *p,
++ __vector unsigned short *q)
++{
++ __vector unsigned short source_1, source_2;
++ __vector unsigned short us_result;
++
++ source_1 = *p;
++ source_2 = *q;
++
++ us_result = __builtin_vec_vaduh (source_1, source_2);
++ return us_result;
++}
++
++/* { dg-final { scan-assembler "vabsduh" } } */
Index: gcc/testsuite/gcc.target/powerpc/dform-1.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/powerpc/dform-1.c (.../tags/gcc_6_1_0_release)
@@ -7582,10 +7949,13 @@ Index: gcc/testsuite/gcc.target/powerpc/darn-2.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/powerpc/darn-2.c (.../tags/gcc_6_1_0_release)
+++ b/src/gcc/testsuite/gcc.target/powerpc/darn-2.c (.../branches/gcc-6-branch)
-@@ -0,0 +1,12 @@
+@@ -0,0 +1,15 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
-+/* { dg-options "-mcpu=power9" } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-require-effective-target lp64 } */
++/* { dg-skip-if "" { powerpc*-*-aix* } } */
++/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
@@ -7916,6 +8286,34 @@ Index: gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c
#include <altivec.h>
+Index: gcc/testsuite/gcc.target/powerpc/vadsduh-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vadsduh-2.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vadsduh-2.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,23 @@
++/* { dg-do compile { target { powerpc*-*-* } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-skip-if "" { powerpc*-*-aix* } } */
++/* { dg-options "-mcpu=power9" } */
++
++/* This test should succeed on both 32- and 64-bit configurations. */
++#include <altivec.h>
++
++__vector unsigned short
++doAbsoluteDifferenceUnsignedMacro (__vector unsigned short *p,
++ __vector unsigned short *q)
++{
++ __vector unsigned short result, source_1, source_2;
++
++ source_1 = *p;
++ source_2 = *q;
++
++ result = vec_absdh (source_1, source_2);
++ return result;
++}
++
++/* { dg-final { scan-assembler "vabsduh" } } */
Index: gcc/testsuite/gcc.target/powerpc/dform-2.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/powerpc/dform-2.c (.../tags/gcc_6_1_0_release)
@@ -7929,6 +8327,31 @@ Index: gcc/testsuite/gcc.target/powerpc/dform-2.c
#ifndef TYPE
#define TYPE float
+Index: gcc/testsuite/gcc.target/powerpc/pr71656-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/pr71656-1.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/pr71656-1.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,20 @@
++/* Test for reload ICE arising from POWER9 Vector Dform code generation. */
++/* { dg-do compile } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-options "-O1 -mcpu=power9 -mpower9-dform-vector -mno-lra" } */
++
++typedef __attribute__((altivec(vector__))) int type_t;
++type_t
++func (type_t *src)
++{
++ asm volatile ("# force the base reg on the load below to be spilled"
++ : /* no outputs */
++ : /* no inputs */
++ : "r0", "r3", "r4", "r5", "r6", "r7",
++ "r8", "r9", "r10", "r11", "r12", "r14", "r15",
++ "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
++ "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31");
++ return src[1];
++}
++
Index: gcc/testsuite/gcc.target/powerpc/dform-3.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/powerpc/dform-3.c (.../tags/gcc_6_1_0_release)
@@ -7973,6 +8396,58 @@ Index: gcc/testsuite/gcc.target/powerpc/dform-3.c
+/* { dg-final { scan-assembler-not "mfvsrld " } } */
+/* { dg-final { scan-assembler "l\[dq\] " } } */
+/* { dg-final { scan-assembler "st\[dq\] " } } */
+Index: gcc/testsuite/gcc.target/powerpc/pr71656-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/pr71656-2.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/pr71656-2.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,47 @@
++/* Test for reload ICE arising from POWER9 Vector Dform code generation. */
++/* { dg-do compile } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-options "-O3 -mcpu=power9 -mpower9-dform-vector -mno-lra -funroll-loops -fno-aggressive-loop-optimizations" } */
++
++typedef double vec[3];
++struct vec_t
++{
++ vec x;
++ vec y;
++};
++int a, j, k, l, m, n, o, p, q;
++double b, i;
++vec c;
++double h[6];
++void func1 (vec);
++
++void
++func2 (double *b)
++{
++ for (; k; k--)
++ for (; j <= k;)
++ for (; m <= q; m++)
++ for (; n <= k; n++)
++ for (; o <= l; o++)
++ {
++ j = p + m + n + o;
++ h[j] = i;
++ }
++}
++
++void
++func3 (void)
++{
++ struct vec_t d;
++ func1 (d.y);
++ func2 (&b);
++ for (; a;)
++ {
++ double *e = d.y, *g;
++ double f;
++ c[0] = g[0] + f * e[0];
++ c[1] = g[1] + f * e[1];
++ func1 (c);
++ }
++}
Index: gcc/testsuite/gcc.target/powerpc/pr70963.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/powerpc/pr70963.c (.../tags/gcc_6_1_0_release)
@@ -8039,6 +8514,259 @@ Index: gcc/testsuite/gcc.target/powerpc/p9-vneg.c
+
+/* { dg-final { scan-assembler "vnegd" } } */
+/* { dg-final { scan-assembler "vnegw" } } */
+Index: gcc/testsuite/gcc.target/powerpc/copysign128-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/copysign128-1.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/copysign128-1.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,58 @@
++/* { dg-do run { target { powerpc64*-*-* && vsx_hw } } } */
++/* { dg-options "-mfloat128 -mvsx" } */
++
++void abort ();
++
++typedef unsigned long long int uint64_t;
++
++typedef union
++{
++ __float128 value;
++
++ struct
++ {
++#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
++ unsigned negative:1;
++ unsigned exponent:15;
++ unsigned quiet_nan:1;
++ uint64_t mant_high:47;
++ uint64_t mant_low:64;
++#else
++ uint64_t mant_low:64;
++ uint64_t mant_high:47;
++ unsigned quiet_nan:1;
++ unsigned exponent:15;
++ unsigned negative:1;
++#endif
++ } nan;
++
++} ieee854_float128;
++
++int
++main (int argc, int *argv[])
++{
++ ieee854_float128 x, y, z;
++
++ x.nan.negative = 0;
++ x.nan.exponent = 0x22;
++ x.nan.quiet_nan = 0;
++ x.nan.mant_high = 0x1234;
++ x.nan.mant_low = 0xabcdef;
++
++ y.nan.negative = 1;
++ y.nan.exponent = 0;
++ y.nan.quiet_nan = 0;
++ y.nan.mant_high = 0;
++ y.nan.mant_low = 0;
++
++ z.value = __builtin_copysignq (x.value, y.value);
++
++ if (z.nan.negative != 1
++ || z.nan.exponent != 0x22
++ || z.nan.quiet_nan != 0
++ || z.nan.mant_high != 0x1234
++ || z.nan.mant_low != 0xabcdef)
++ abort ();
++
++ return 0;
++}
+Index: gcc/testsuite/gcc.target/powerpc/vadsdub-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vadsdub-1.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vadsdub-1.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,24 @@
++/* { dg-do compile { target { powerpc*-*-* } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-skip-if "" { powerpc*-*-aix* } } */
++/* { dg-options "-mcpu=power9" } */
++
++/* This test should succeed on both 32- and 64-bit configurations. */
++#include <altivec.h>
++
++__vector unsigned char
++doAbsoluteDifferenceUnsigned (__vector unsigned char *p,
++ __vector unsigned char *q)
++{
++ __vector unsigned char source_1, source_2;
++ __vector unsigned char uc_result;
++
++ source_1 = *p;
++ source_2 = *q;
++
++ uc_result = __builtin_vec_vadub (source_1, source_2);
++ return uc_result;
++}
++
++/* { dg-final { scan-assembler "vabsdub" } } */
+Index: gcc/testsuite/gcc.target/powerpc/vsrv-0.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vsrv-0.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vsrv-0.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,17 @@
++/* { dg-do compile { target { powerpc*-*-* } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-skip-if "" { powerpc*-*-aix* } } */
++/* { dg-options "-mcpu=power9" } */
++
++#include <altivec.h>
++
++__vector unsigned char
++doCharShiftLeft (__vector unsigned char *p, __vector unsigned char *q)
++{
++ __vector unsigned char result, input, shift_distance;
++ result = __builtin_vec_vsrv (input, shift_distance);
++ return result;
++}
++
++/* { dg-final { scan-assembler "vsrv" } } */
+Index: gcc/testsuite/gcc.target/powerpc/vadsdub-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vadsdub-2.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vadsdub-2.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,24 @@
++/* { dg-do compile { target { powerpc*-*-* } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-skip-if "" { powerpc*-*-aix* } } */
++/* { dg-options "-mcpu=power9" } */
++
++/* This test should succeed on both 32- and 64-bit configurations. */
++#include <altivec.h>
++
++__vector unsigned char
++doAbsoluteDifferenceUnsigned (__vector unsigned char *p,
++ __vector unsigned char *q)
++{
++ __vector unsigned char source_1, source_2;
++ __vector unsigned char uc_result;
++
++ source_1 = *p;
++ source_2 = *q;
++
++ uc_result = vec_absdb (source_1, source_2);
++ return uc_result;
++}
++
++/* { dg-final { scan-assembler "vabsdub" } } */
+Index: gcc/testsuite/gcc.target/powerpc/vslv-0.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vslv-0.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vslv-0.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,17 @@
++/* { dg-do compile { target { powerpc*-*-* } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-skip-if "" { powerpc*-*-aix* } } */
++/* { dg-options "-mcpu=power9" } */
++
++#include <altivec.h>
++
++__vector unsigned char
++doCharShiftLeft (__vector unsigned char *p, __vector unsigned char *q)
++{
++ __vector unsigned char result, input, shift_distance;
++ result = __builtin_vec_vslv (input, shift_distance);
++ return result;
++}
++
++/* { dg-final { scan-assembler "vslv" } } */
+Index: gcc/testsuite/gcc.target/powerpc/abs128-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/abs128-1.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/abs128-1.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,61 @@
++/* { dg-do run { target { powerpc64*-*-* && vsx_hw } } } */
++/* { dg-options "-mfloat128 -mvsx" } */
++
++void abort ();
++
++typedef unsigned long long int uint64_t;
++
++typedef union
++{
++ __float128 value;
++
++ struct
++ {
++#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
++ unsigned negative:1;
++ unsigned exponent:15;
++ unsigned quiet_nan:1;
++ uint64_t mant_high:47;
++ uint64_t mant_low:64;
++#else
++ uint64_t mant_low:64;
++ uint64_t mant_high:47;
++ unsigned quiet_nan:1;
++ unsigned exponent:15;
++ unsigned negative:1;
++#endif
++ } nan;
++
++} ieee854_float128;
++
++int
++main (int argc, int *argv[])
++{
++ ieee854_float128 x, z;
++
++ x.nan.negative = 1;
++ x.nan.exponent = 0x22;
++ x.nan.quiet_nan = 0;
++ x.nan.mant_high = 0x1234;
++ x.nan.mant_low = 0xabcdef;
++
++ z.value = __builtin_fabsq (x.value);
++
++ if (z.nan.negative != 0
++ || z.nan.exponent != 0x22
++ || z.nan.quiet_nan != 0
++ || z.nan.mant_high != 0x1234
++ || z.nan.mant_low != 0xabcdef)
++ abort ();
++
++ z.value = __builtin_fabsq (z.value);
++
++ if (z.nan.negative != 0
++ || z.nan.exponent != 0x22
++ || z.nan.quiet_nan != 0
++ || z.nan.mant_high != 0x1234
++ || z.nan.mant_low != 0xabcdef)
++ abort ();
++
++ return 0;
++}
+Index: gcc/testsuite/gcc.target/powerpc/vsrv-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vsrv-1.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vsrv-1.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,17 @@
++/* { dg-do compile { target { powerpc*-*-* } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-skip-if "" { powerpc*-*-aix* } } */
++/* { dg-options "-mcpu=power9" } */
++
++#include <altivec.h>
++
++__vector unsigned char
++doCharShiftLeft (__vector unsigned char *p, __vector unsigned char *q)
++{
++ __vector unsigned char result, input, shift_distance;
++ result = vec_srv (input, shift_distance);
++ return result;
++}
++
++/* { dg-final { scan-assembler "vsrv" } } */
Index: gcc/testsuite/gcc.target/powerpc/ctz-3.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/powerpc/ctz-3.c (.../tags/gcc_6_1_0_release)
@@ -8106,6 +8834,28 @@ Index: gcc/testsuite/gcc.target/powerpc/ctz-3.c
+/* { dg-final { scan-assembler-times "vctzw" 2 } } */
+/* { dg-final { scan-assembler-not "cnttzd" } } */
+/* { dg-final { scan-assembler-not "cnttzw" } } */
+Index: gcc/testsuite/gcc.target/powerpc/vslv-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vslv-1.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vslv-1.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,17 @@
++/* { dg-do compile { target { powerpc*-*-* } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-skip-if "" { powerpc*-*-aix* } } */
++/* { dg-options "-mcpu=power9" } */
++
++#include <altivec.h>
++
++__vector unsigned char
++doCharShiftLeft (__vector unsigned char *p, __vector unsigned char *q)
++{
++ __vector unsigned char result, input, shift_distance;
++ result = vec_slv (input, shift_distance);
++ return result;
++}
++
++/* { dg-final { scan-assembler "vslv" } } */
Index: gcc/testsuite/gcc.target/powerpc/ctz-4.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/powerpc/ctz-4.c (.../tags/gcc_6_1_0_release)
@@ -8234,6 +8984,135 @@ Index: gcc/testsuite/gcc.target/powerpc/pr47755.c
/* { dg-final { scan-assembler-not "lxvd2x" } } */
/* { dg-final { scan-assembler-not "lxvw4x" } } */
/* { dg-final { scan-assembler-not "lvx" } } */
+Index: gcc/testsuite/gcc.target/powerpc/pr71698.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/pr71698.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/pr71698.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,13 @@
++/* Test for a reload ICE arising from trying to direct move a TDmode value. */
++/* { dg-do compile } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-require-effective-target dfp } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-options "-O1 -mcpu=power9 -mno-lra" } */
++
++extern void testvad128 (int n, ...);
++void
++testitd128 (_Decimal128 g01d128)
++{
++ testvad128 (1, g01d128);
++}
+Index: gcc/testsuite/gcc.target/powerpc/vadsdu-0.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vadsdu-0.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vadsdu-0.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,24 @@
++/* { dg-do compile { target { powerpc*-*-* } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-skip-if "" { powerpc*-*-aix* } } */
++/* { dg-options "-mcpu=power9" } */
++
++/* This test should succeed on both 32- and 64-bit configurations. */
++#include <altivec.h>
++
++__vector unsigned int
++doAbsoluteDifferenceUnsignedInt (__vector unsigned int *p,
++ __vector unsigned int *q)
++{
++ __vector unsigned int source_1, source_2;
++ __vector unsigned int result;
++
++ source_1 = *p;
++ source_2 = *q;
++
++ result = __builtin_vec_vadu (source_1, source_2);
++ return result;
++}
++
++/* { dg-final { scan-assembler "vabsduw" } } */
+Index: gcc/testsuite/gcc.target/powerpc/nan128-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/nan128-1.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/nan128-1.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,77 @@
++/* { dg-do run { target { powerpc64*-*-* && vsx_hw } } } */
++/* { dg-options "-mfloat128 -mvsx" } */
++
++#include <stdio.h>
++
++void abort ();
++
++typedef unsigned long long int uint64_t;
++
++typedef union
++{
++ __float128 value;
++
++ struct
++ {
++#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
++ unsigned negative:1;
++ unsigned exponent:15;
++ unsigned quiet_nan:1;
++ uint64_t mant_high:47;
++ uint64_t mant_low:64;
++#else
++ uint64_t mant_low:64;
++ uint64_t mant_high:47;
++ unsigned quiet_nan:1;
++ unsigned exponent:15;
++ unsigned negative:1;
++#endif
++ } nan;
++
++} ieee854_float128;
++
++int
++main (int argc, int *argv[])
++{
++ ieee854_float128 y;
++
++ y.value = __builtin_nanq ("1");
++
++ if (y.nan.negative != 0
++ || y.nan.exponent != 0x7fff
++ || y.nan.quiet_nan != 1
++ || y.nan.mant_high != 0
++ || y.nan.mant_low != 1)
++ abort ();
++
++ y.value = __builtin_nanq ("0x2ab3c");
++
++ if (y.nan.negative != 0
++ || y.nan.exponent != 0x7fff
++ || y.nan.quiet_nan != 1
++ || y.nan.mant_high != 0
++ || y.nan.mant_low != 0x2ab3c)
++ abort ();
++
++ y.value = __builtin_nansq ("1");
++
++ if (
++ y.nan.negative != 0
++ || y.nan.exponent != 0x7fff
++ || y.nan.quiet_nan != 0
++ || y.nan.mant_high != 0
++ || y.nan.mant_low != 1
++ )
++ abort ();
++
++ y.value = __builtin_nansq ("0x2ab3c");
++
++ if (y.nan.negative != 0
++ || y.nan.exponent != 0x7fff
++ || y.nan.quiet_nan != 0
++ || y.nan.mant_high != 0
++ || y.nan.mant_low != 0x2ab3c)
++ abort ();
++
++ return 0;
++}
Index: gcc/testsuite/gcc.target/powerpc/pr68805.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/powerpc/pr68805.c (.../tags/gcc_6_1_0_release)
@@ -8246,6 +9125,34 @@ Index: gcc/testsuite/gcc.target/powerpc/pr68805.c
typedef struct bar {
void *a;
+Index: gcc/testsuite/gcc.target/powerpc/vadsdu-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vadsdu-1.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vadsdu-1.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,23 @@
++/* { dg-do compile { target { powerpc*-*-* } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-skip-if "" { powerpc*-*-aix* } } */
++/* { dg-options "-mcpu=power9" } */
++
++/* This test should succeed on both 32- and 64-bit configurations. */
++#include <altivec.h>
++
++__vector unsigned int
++doAbsoluteDifferenceUnsignedIntMacro (__vector unsigned int *p,
++ __vector unsigned int *q)
++{
++ __vector unsigned int result, source_1, source_2;
++
++ source_1 = *p;
++ source_2 = *q;
++
++ result = vec_absd (source_1, source_2);
++ return result;
++}
++
++/* { dg-final { scan-assembler "vabsduw" } } */
Index: gcc/testsuite/gcc.target/powerpc/pr71186.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/powerpc/pr71186.c (.../tags/gcc_6_1_0_release)
@@ -8445,6 +9352,95 @@ Index: gcc/testsuite/gcc.target/powerpc/float128-complex-1.c
+FLOAT128_CALL ()
+LDOUBLE_CALL ()
+#endif
+Index: gcc/testsuite/gcc.target/powerpc/inf128-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/inf128-1.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/inf128-1.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,55 @@
++/* { dg-do run { target { powerpc64*-*-* && vsx_hw } } } */
++/* { dg-options "-mfloat128 -mvsx" } */
++
++void abort ();
++
++typedef unsigned long long int uint64_t;
++
++typedef union
++{
++ __float128 value;
++
++ struct
++ {
++#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
++ unsigned negative:1;
++ unsigned exponent:15;
++ unsigned quiet_nan:1;
++ uint64_t mant_high:47;
++ uint64_t mant_low:64;
++#else
++ uint64_t mant_low:64;
++ uint64_t mant_high:47;
++ unsigned quiet_nan:1;
++ unsigned exponent:15;
++ unsigned negative:1;
++#endif
++ } nan;
++
++} ieee854_float128;
++
++int
++main (int argc, int *argv[])
++{
++ ieee854_float128 y;
++
++ y.value = __builtin_infq ();
++
++ if (y.nan.negative != 0
++ || y.nan.exponent != 0x7fff
++ || y.nan.quiet_nan != 0
++ || y.nan.mant_high != 0
++ || y.nan.mant_low != 0)
++ abort ();
++
++ y.value = __builtin_huge_valq ();
++
++ if (y.nan.negative != 0
++ || y.nan.exponent != 0x7fff
++ || y.nan.quiet_nan != 0
++ || y.nan.mant_high != 0
++ || y.nan.mant_low != 0)
++ abort ();
++
++ return 0;
++}
+Index: gcc/testsuite/gcc.target/powerpc/vadsdu-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vadsdu-2.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vadsdu-2.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,24 @@
++/* { dg-do compile { target { powerpc*-*-* } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-skip-if "" { powerpc*-*-aix* } } */
++/* { dg-options "-mcpu=power9" } */
++
++/* This test should succeed on both 32- and 64-bit configurations. */
++#include <altivec.h>
++
++__vector unsigned short
++doAbsoluteDifferenceUnsignedShort (__vector unsigned short *p,
++ __vector unsigned short *q)
++{
++ __vector unsigned short source_1, source_2;
++ __vector unsigned short result;
++
++ source_1 = *p;
++ source_2 = *q;
++
++ result = __builtin_vec_vadu (source_1, source_2);
++ return result;
++}
++
++/* { dg-final { scan-assembler "vabsduh" } } */
Index: gcc/testsuite/gcc.target/powerpc/float128-complex-2.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/powerpc/float128-complex-2.c (.../tags/gcc_6_1_0_release)
@@ -8807,6 +9803,46 @@ Index: gcc/testsuite/gcc.target/powerpc/vsx-elemrev-1.c
+{
+ vec_xst (vui, 0, uip);
+}
+Index: gcc/testsuite/gcc.target/powerpc/vadsdu-3.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vadsdu-3.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vadsdu-3.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,23 @@
++/* { dg-do compile { target { powerpc*-*-* } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-skip-if "" { powerpc*-*-aix* } } */
++/* { dg-options "-mcpu=power9" } */
++
++/* This test should succeed on both 32- and 64-bit configurations. */
++#include <altivec.h>
++
++__vector unsigned short
++doAbsoluteDifferenceUnsignedShortMacro (__vector unsigned short *p,
++ __vector unsigned short *q)
++{
++ __vector unsigned short result, source_1, source_2;
++
++ source_1 = *p;
++ source_2 = *q;
++
++ result = vec_absd (source_1, source_2);
++ return result;
++}
++
++/* { dg-final { scan-assembler "vabsduh" } } */
+Index: gcc/testsuite/gcc.target/powerpc/pr71670.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/pr71670.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/pr71670.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,7 @@
++/* { dg-do compile { target { powerpc*-*-* } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-options "-mcpu=power9 -O1" } */
++
++volatile int a;
++int b;
++void fn1(void) { b + (long)b || a; }
Index: gcc/testsuite/gcc.target/powerpc/p9-splat-2.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/powerpc/p9-splat-2.c (.../tags/gcc_6_1_0_release)
@@ -9091,6 +10127,35 @@ Index: gcc/testsuite/gcc.target/powerpc/vsx-elemrev-2.c
+{
+ vec_xst (vuc, 0, ucp);
+}
+Index: gcc/testsuite/gcc.target/powerpc/vadsdu-4.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vadsdu-4.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vadsdu-4.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,24 @@
++/* { dg-do compile { target { powerpc*-*-* } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-skip-if "" { powerpc*-*-aix* } } */
++/* { dg-options "-mcpu=power9" } */
++
++/* This test should succeed on both 32- and 64-bit configurations. */
++#include <altivec.h>
++
++__vector unsigned char
++doAbsoluteDifferenceUnsignedChar (__vector unsigned char *p,
++ __vector unsigned char *q)
++{
++ __vector unsigned char source_1, source_2;
++ __vector unsigned char result;
++
++ source_1 = *p;
++ source_2 = *q;
++
++ result = __builtin_vec_vadu (source_1, source_2);
++ return result;
++}
++
++/* { dg-final { scan-assembler "vabsdub" } } */
Index: gcc/testsuite/gcc.target/powerpc/p9-vpermr.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/powerpc/p9-vpermr.c (.../tags/gcc_6_1_0_release)
@@ -9117,12 +10182,44 @@ Index: gcc/testsuite/gcc.target/powerpc/p9-vpermr.c
+}
+
+/* { dg-final { scan-assembler "vpermr\|xxpermr" } } */
+Index: gcc/testsuite/gcc.target/powerpc/vadsduw-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vadsduw-1.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vadsduw-1.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,24 @@
++/* { dg-do compile { target { powerpc*-*-* } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-skip-if "" { powerpc*-*-aix* } } */
++/* { dg-options "-mcpu=power9" } */
++
++/* This test should succeed on both 32- and 64-bit configurations. */
++#include <altivec.h>
++
++__vector unsigned int
++doAbsoluteDifferenceUnsigned (__vector unsigned int *p,
++ __vector unsigned int *q)
++{
++ __vector unsigned int source_1, source_2;
++ __vector unsigned int ui_result;
++
++ source_1 = *p;
++ source_2 = *q;
++
++ ui_result = __builtin_vec_vaduw (source_1, source_2);
++ return ui_result;
++}
++
++/* { dg-final { scan-assembler "vabsduw" } } */
Index: gcc/testsuite/gcc.target/powerpc/darn-0.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/powerpc/darn-0.c (.../tags/gcc_6_1_0_release)
+++ b/src/gcc/testsuite/gcc.target/powerpc/darn-0.c (.../branches/gcc-6-branch)
-@@ -0,0 +1,12 @@
+@@ -0,0 +1,15 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-skip-if "" { powerpc*-*-aix* } } */
+/* { dg-options "-mcpu=power9" } */
+
+/* This test should succeed on both 32- and 64-bit configurations. */
@@ -9347,14 +10444,73 @@ Index: gcc/testsuite/gcc.target/powerpc/vsx-elemrev-3.c
+{
+ vec_xst (vui, 0, uip);
+}
+Index: gcc/testsuite/gcc.target/powerpc/vadsdu-5.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vadsdu-5.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vadsdu-5.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,23 @@
++/* { dg-do compile { target { powerpc*-*-* } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-skip-if "" { powerpc*-*-aix* } } */
++/* { dg-options "-mcpu=power9" } */
++
++/* This test should succeed on both 32- and 64-bit configurations. */
++#include <altivec.h>
++
++__vector unsigned char
++doAbsoluteDifferenceUnsignedCharMacro (__vector unsigned char *p,
++ __vector unsigned char *q)
++{
++ __vector unsigned char result, source_1, source_2;
++
++ source_1 = *p;
++ source_2 = *q;
++
++ result = vec_absd (source_1, source_2);
++ return result;
++}
++
++/* { dg-final { scan-assembler "vabsdub" } } */
+Index: gcc/testsuite/gcc.target/powerpc/vadsduw-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/vadsduw-2.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/vadsduw-2.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,23 @@
++/* { dg-do compile { target { powerpc*-*-* } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-skip-if "" { powerpc*-*-aix* } } */
++/* { dg-options "-mcpu=power9" } */
++
++/* This test should succeed on both 32- and 64-bit configurations. */
++#include <altivec.h>
++
++__vector unsigned int
++doAbsoluteDifferenceUnsignedMacro (__vector unsigned int *p,
++ __vector unsigned int *q)
++{
++ __vector unsigned int result, source_1, source_2;
++
++ source_1 = *p;
++ source_2 = *q;
++
++ result = vec_absdw (source_1, source_2);
++ return result;
++}
++
++/* { dg-final { scan-assembler "vabsduw" } } */
Index: gcc/testsuite/gcc.target/powerpc/darn-1.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/powerpc/darn-1.c (.../tags/gcc_6_1_0_release)
+++ b/src/gcc/testsuite/gcc.target/powerpc/darn-1.c (.../branches/gcc-6-branch)
-@@ -0,0 +1,12 @@
+@@ -0,0 +1,15 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
-+/* { dg-options "-mcpu=power9" } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-require-effective-target lp64 } */
++/* { dg-skip-if "" { powerpc*-*-aix* } } */
++/* { dg-options "-mcpu=power9" } */
+
+#include <altivec.h>
+
@@ -10070,6 +11226,19 @@ Index: gcc/testsuite/gcc.target/i386/pr70858.c
+{
+ return __builtin_ia32_pext_di (x, y); /* { dg-warning "implicit declaration of function .__builtin_ia32_pext_di." "" { target ia32 } } */
+}
+Index: gcc/testsuite/gcc.target/i386/avx-pr71559.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/avx-pr71559.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/avx-pr71559.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,8 @@
++/* PR target/71559 */
++/* { dg-do run { target avx } } */
++/* { dg-options "-O2 -ftree-vectorize -mavx" } */
++
++#include "avx-check.h"
++#define PR71559_TEST avx_test
++
++#include "sse2-pr71559.c"
Index: gcc/testsuite/gcc.target/i386/avx512f-floor-vec-2.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/i386/avx512f-floor-vec-2.c (.../tags/gcc_6_1_0_release)
@@ -10184,6 +11353,19 @@ Index: gcc/testsuite/gcc.target/i386/avx512f-rintf-sfix-vec-2.c
+#include "avx512f-rintf-sfix-vec-1.c"
+
+/* { dg-final { scan-assembler-times "vcvtps2dq\[^\n\]+zmm\[0-9\](?:\n|\[ \\t\]+#)" 1 } } */
+Index: gcc/testsuite/gcc.target/i386/avx512f-pr71559.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/avx512f-pr71559.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/avx512f-pr71559.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,8 @@
++/* PR target/71559 */
++/* { dg-do run { target avx512f } } */
++/* { dg-options "-O2 -ftree-vectorize -mavx512f" } */
++
++#include "avx512f-check.h"
++#define PR71559_TEST avx512f_test
++
++#include "sse2-pr71559.c"
Index: gcc/testsuite/gcc.target/i386/avx512f-trunc-vec-2.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/i386/avx512f-trunc-vec-2.c (.../tags/gcc_6_1_0_release)
@@ -10362,6 +11544,84 @@ Index: gcc/testsuite/gcc.target/i386/avx512f-ceilf-sfix-vec-1.c
+ if (r[i] != (int) ceilf (a[i]))
+ abort();
+}
+Index: gcc/testsuite/gcc.target/i386/sse2-pr71559.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/sse2-pr71559.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/sse2-pr71559.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,73 @@
++/* PR target/71559 */
++/* { dg-do run { target sse2 } } */
++/* { dg-options "-O2 -ftree-vectorize -msse2" } */
++
++#ifndef PR71559_TEST
++#include "sse2-check.h"
++#define PR71559_TEST sse2_test
++#endif
++
++#define N 16
++float a[N] = { 5.0f, -3.0f, 1.0f, __builtin_nanf (""), 9.0f, 7.0f, -3.0f, -9.0f,
++ -3.0f, -5.0f, -9.0f, __builtin_nanf (""), 0.5f, -0.5f, 0.0f, 0.0f };
++float b[N] = { -5.0f, 3.0f, 1.0f, 7.0f, 8.0f, 8.0f, -3.0f, __builtin_nanf (""),
++ -4.0f, -4.0f, -9.0f, __builtin_nanf (""), 0.0f, 0.0f, 0.0f, __builtin_nanf ("") };
++int c[N], d[N];
++
++#define FN(name, op) \
++void \
++name (void) \
++{ \
++ int i; \
++ for (i = 0; i < N; i++) \
++ c[i] = (op || d[i] > 37) ? 5 : 32; \
++}
++FN (eq, a[i] == b[i])
++FN (ne, a[i] != b[i])
++FN (gt, a[i] > b[i])
++FN (ge, a[i] >= b[i])
++FN (lt, a[i] < b[i])
++FN (le, a[i] <= b[i])
++FN (unle, !__builtin_isgreater (a[i], b[i]))
++FN (unlt, !__builtin_isgreaterequal (a[i], b[i]))
++FN (unge, !__builtin_isless (a[i], b[i]))
++FN (ungt, !__builtin_islessequal (a[i], b[i]))
++FN (uneq, !__builtin_islessgreater (a[i], b[i]))
++FN (ordered, !__builtin_isunordered (a[i], b[i]))
++FN (unordered, __builtin_isunordered (a[i], b[i]))
++
++#define TEST(name, GT, LT, EQ, UO) \
++ name (); \
++ for (i = 0; i < N; i++) \
++ { \
++ int v; \
++ switch (i % 4) \
++ { \
++ case 0: v = GT ? 5 : 32; break; \
++ case 1: v = LT ? 5 : 32; break; \
++ case 2: v = EQ ? 5 : 32; break; \
++ case 3: v = UO ? 5 : 32; break; \
++ } \
++ if (c[i] != v) \
++ __builtin_abort (); \
++ }
++
++void
++PR71559_TEST (void)
++{
++ int i;
++ asm volatile ("" : : "g" (a), "g" (b), "g" (c), "g" (d) : "memory");
++ TEST (eq, 0, 0, 1, 0)
++ TEST (ne, 1, 1, 0, 1)
++ TEST (gt, 1, 0, 0, 0)
++ TEST (ge, 1, 0, 1, 0)
++ TEST (lt, 0, 1, 0, 0)
++ TEST (le, 0, 1, 1, 0)
++ TEST (unle, 0, 1, 1, 1)
++ TEST (unlt, 0, 1, 0, 1)
++ TEST (unge, 1, 0, 1, 1)
++ TEST (ungt, 1, 0, 0, 1)
++ TEST (uneq, 0, 0, 1, 1)
++ TEST (ordered, 1, 1, 1, 0)
++ TEST (unordered, 0, 0, 0, 1)
++}
Index: gcc/testsuite/gcc.target/i386/avx512f-roundf-sfix-vec-1.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/i386/avx512f-roundf-sfix-vec-1.c (.../tags/gcc_6_1_0_release)
@@ -11000,6 +12260,81 @@ Index: gcc/testsuite/gfortran.dg/pr70931.f90
+ type(t), parameter :: z = t(1, [2])
+ print *, z
+end
+Index: gcc/testsuite/gfortran.dg/gomp/pr71704.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/gomp/pr71704.f90 (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/gomp/pr71704.f90 (.../branches/gcc-6-branch)
+@@ -0,0 +1,58 @@
++! PR fortran/71704
++! { dg-do compile }
++
++real function f0 ()
++!$omp declare simd (f0)
++ f0 = 1
++end
++
++real function f1 ()
++!$omp declare target (f1)
++ f1 = 1
++end
++
++real function f2 ()
++!$omp declare reduction (foo : integer : omp_out = omp_out + omp_in) &
++!$omp & initializer (omp_priv = 0)
++ f2 = 1
++end
++
++real function f3 ()
++ real, save :: t
++!$omp threadprivate (t)
++ f3 = 1
++end
++
++real function f4 ()
++!$omp taskwait
++ f4 = 1
++end
++
++real function f5 ()
++!$omp barrier
++ f5 = 1
++end
++
++real function f6 ()
++!$omp parallel
++!$omp end parallel
++ f6 = 1
++end
++
++real function f7 ()
++!$omp single
++!$omp end single
++ f7 = 1
++end
++
++real function f8 ()
++!$omp critical
++!$omp end critical
++ f8 = 1
++end
++
++real function f9 ()
++!$omp critical
++!$omp end critical
++ f9 = 1
++end
+Index: gcc/testsuite/gfortran.dg/gomp/pr71705.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/gomp/pr71705.f90 (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/gomp/pr71705.f90 (.../branches/gcc-6-branch)
+@@ -0,0 +1,7 @@
++! PR fortran/71705
++! { dg-do compile }
++
++ real :: x
++ x = 0.0
++ !$omp target update to(x)
++end
Index: gcc/testsuite/gfortran.dg/gomp/pr70855.f90
===================================================================
--- a/src/gcc/testsuite/gfortran.dg/gomp/pr70855.f90 (.../tags/gcc_6_1_0_release)
@@ -11162,6 +12497,22 @@ Index: gcc/testsuite/gfortran.dg/gomp/order-2.f90
+ !$omp declare simd (f5) notinbranch ! { dg-error "Unexpected" }
+ end function f5
+end subroutine f1
+Index: gcc/testsuite/gfortran.dg/gomp/pr71687.f90
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/gomp/pr71687.f90 (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/gomp/pr71687.f90 (.../branches/gcc-6-branch)
+@@ -0,0 +1,11 @@
++! PR fortran/71687
++! { dg-do compile }
++! { dg-additional-options "-fstack-arrays -O2" }
++
++subroutine s (n, x)
++ integer :: n
++ real :: x(n)
++!$omp parallel
++ x(1:n) = x(n:1:-1)
++!$omp end parallel
++end
Index: gcc/testsuite/gfortran.dg/goacc/subroutines.f90
===================================================================
--- a/src/gcc/testsuite/gfortran.dg/goacc/subroutines.f90 (.../tags/gcc_6_1_0_release)
@@ -13431,6 +14782,39 @@ Index: gcc/testsuite/gcc.c-torture/execute/pr71494.c
+ __builtin_abort ();
+ return 0;
+}
+Index: gcc/testsuite/gcc.c-torture/execute/pr71626-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.c-torture/execute/pr71626-1.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.c-torture/execute/pr71626-1.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,19 @@
++/* PR middle-end/71626 */
++
++typedef __INTPTR_TYPE__ V __attribute__((__vector_size__(sizeof (__INTPTR_TYPE__))));
++
++__attribute__((noinline, noclone)) V
++foo ()
++{
++ V v = { (__INTPTR_TYPE__) foo };
++ return v;
++}
++
++int
++main ()
++{
++ V v = foo ();
++ if (v[0] != (__INTPTR_TYPE__) foo)
++ __builtin_abort ();
++ return 0;
++}
+Index: gcc/testsuite/gcc.c-torture/execute/pr71626-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.c-torture/execute/pr71626-2.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.c-torture/execute/pr71626-2.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,4 @@
++/* PR middle-end/71626 */
++/* { dg-additional-options "-fpic" { target fpic } } */
++
++#include "pr71626-1.c"
Index: gcc/testsuite/gcc.c-torture/execute/pr71554.c
===================================================================
--- a/src/gcc/testsuite/gcc.c-torture/execute/pr71554.c (.../tags/gcc_6_1_0_release)
@@ -14018,6 +15402,17 @@ Index: gcc/testsuite/gcc.dg/pr71071.c
+ if (a.b)
+ ;
+}
+Index: gcc/testsuite/gcc.dg/pr71685.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/pr71685.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.dg/pr71685.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,6 @@
++/* PR c/71685 */
++/* { dg-do compile } */
++/* { dg-options "-std=gnu11" } */
++
++extern struct S v, s;
++struct S { int t; int p[]; } v = { 4, 0 };
Index: gcc/testsuite/gcc.dg/torture/pr70935.c
===================================================================
--- a/src/gcc/testsuite/gcc.dg/torture/pr70935.c (.../tags/gcc_6_1_0_release)
@@ -14346,11 +15741,161 @@ Index: gcc/testsuite/gcc.dg/pr71581.c
+ int x;
+ return x; /* { dg-warning "is used uninitialized in this function" } */
+}
+Index: gcc/testsuite/gcc.dg/spellcheck-options-12.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/spellcheck-options-12.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/gcc.dg/spellcheck-options-12.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,7 @@
++/* Verify that we don't include -Wno- variants for options marked
++ with RejectNegative when considering hints for misspelled options
++ (PR driver/71651). */
++
++/* { dg-do compile } */
++/* { dg-options "-fno-stack-protector-explicit" } */
++/* { dg-error "unrecognized command line option .-fno-stack-protector-explicit.; did you mean .-fstack-protector-explicit.." "" { target *-*-* } 0 } */
Index: gcc/testsuite/ChangeLog
===================================================================
--- a/src/gcc/testsuite/ChangeLog (.../tags/gcc_6_1_0_release)
+++ b/src/gcc/testsuite/ChangeLog (.../branches/gcc-6-branch)
-@@ -1,3 +1,774 @@
+@@ -1,3 +1,912 @@
++2016-07-04 Jakub Jelinek <jakub at redhat.com>
++
++ PR c++/71739
++ * g++.dg/cpp0x/pr71739.C: New test.
++
++2016-07-04 Segher Boessenkool <segher at kernel.crashing.org>
++
++ Backport from mainline
++ 2016-06-27 Segher Boessenkool <segher at kernel.crashing.org>
++
++ PR target/71670
++ * gcc.target/powerpc/pr71670.c: New testcase.
++
++2016-07-02 Jakub Jelinek <jakub at redhat.com>
++
++ Backported from mainline
++ 2016-07-01 Jakub Jelinek <jakub at redhat.com>
++
++ PR fortran/71687
++ * gfortran.dg/gomp/pr71687.f90: New test.
++
++ 2016-06-30 Jakub Jelinek <jakub at redhat.com>
++
++ PR fortran/71704
++ * gfortran.dg/gomp/pr71704.f90: New test.
++
++ PR fortran/71705
++ * gfortran.dg/gomp/pr71705.f90: New test.
++
++ 2016-06-29 Jakub Jelinek <jakub at redhat.com>
++
++ PR c/71685
++ * gcc.dg/pr71685.c: New test.
++
++ 2016-06-28 Jakub Jelinek <jakub at redhat.com>
++
++ PR middle-end/71626
++ * gcc.c-torture/execute/pr71626-1.c: New test.
++ * gcc.c-torture/execute/pr71626-2.c: New test.
++
++ 2016-06-20 Jakub Jelinek <jakub at redhat.com>
++
++ PR target/71559
++ * gcc.target/i386/sse2-pr71559.c: New test.
++ * gcc.target/i386/avx-pr71559.c: New test.
++ * gcc.target/i386/avx512f-pr71559.c: New test.
++
++2016-07-01 Kelvin Nilsen <kelvin at gcc.gnu.org>
++
++ Backport from trunk r237659
++ 2016-06-21 Kelvin Nilsen <kelvin at gcc.gnu.org>
++
++ * gcc.target/powerpc/darn-0.c: Add dejagnu directives to disable
++ test if effective-target is not powerpc_p9vector_ok, or if a -mcpu
++ override other than -mcpu=power9 command-line option is specified,
++ or if the target operating system is aix.
++ * gcc.target/powerpc/darn-1.c: Likewise.
++ * gcc.target/powerpc/darn-2.c: Likewise.
++ * gcc.target/powerpc/vslv-0.c: Add dejagnu directives to disable
++ test if effective-target is not powerpc_p9vector_ok or if the
++ target operating system is aix.
++ * gcc.target/powerpc/vslv-1.c: Likewise.
++ * gcc.target/powerpc/vsrv-0.c: Likewise.
++ * gcc.target/powerpc/vsrv-1.c: Likewise.
++
++2016-07-01 Peter Bergner <bergner at vnet.ibm.com>
++
++ Backport from trunk
++ 2016-06-27 Peter Bergner <bergner at vnet.ibm.com>
++
++ PR target/71656
++ * gcc.target/powerpc/pr71656-1.c: New test.
++ * gcc.target/powerpc/pr71656-2.c: New test.
++
++2016-07-01 Bill Schmidt <wschmidt at linux.vnet.ibm.com>
++
++ Backport from mainline
++ 2016-06-24 Bill Schmidt <wschmidt at linux.vnet.ibm.com>
++
++ * gcc.target/powerpc/abs128-1.c: New.
++ * gcc.target/powerpc/copysign128-1.c: New.
++ * gcc.target/powerpc/inf128-1.c: New.
++ * gcc.target/powerpc/nan128-1.c: New.
++
++ Backport from mainline
++ 2016-06-28 Bill Schmidt <wschmidt at linux.vnet.ibm.com>
++
++ * gcc.target/powerpc/abs128-1.c: Require VSX.
++ * gcc.target/powerpc/copysign128-1.c: Likewise.
++ * gcc.target/powerpc/inf128-1.c: Likewise.
++ * gcc.target/powerpc/nan128-1.c: Likewise.
++
++2016-07-01 Peter Bergner <bergner at vnet.ibm.com>
++
++ Backport from trunk
++ 2016-07-01 Peter Bergner <bergner at vnet.ibm.com>
++
++ PR target/71698
++ * gcc.target/powerpc/pr71698.c: New test.
++
++2016-07-01 Kelvin Nilsen <kelvin at gcc.gnu.org>
++
++ Backport from trunk r236992
++ 2016-06-01 Kelvin Nilsen <kelvin at gcc.gnu.org>
++
++ * gcc.target/powerpc/vslv-0.c: New test.
++ * gcc.target/powerpc/vslv-1.c: New test.
++ * gcc.target/powerpc/vsrv-0.c: New test.
++ * gcc.target/powerpc/vsrv-1.c: New test.
++
++2016-06-30 Kelvin Nilsen <kelvin at gcc.gnu.org>
++
++ Backport from trunk r237390
++ 2016-06-13 Kelvin Nilsen <kelvin at gcc.gnu.org>
++ Backport from trunk r237646
++ 2016-06-20 Kelvin Nilsen <kelvin at gcc.gnu.org>
++
++ * gcc.target/powerpc/vadsdu-0.c: New test.
++ * gcc.target/powerpc/vadsdu-1.c: New test.
++ * gcc.target/powerpc/vadsdu-2.c: New test.
++ * gcc.target/powerpc/vadsdu-3.c: New test.
++ * gcc.target/powerpc/vadsdu-4.c: New test.
++ * gcc.target/powerpc/vadsdu-5.c: New test.
++ * gcc.target/powerpc/vadsdub-1.c: New test.
++ * gcc.target/powerpc/vadsdub-2.c: New test.
++ * gcc.target/powerpc/vadsduh-1.c: New test.
++ * gcc.target/powerpc/vadsduh-2.c: New test.
++ * gcc.target/powerpc/vadsduw-1.c: New test.
++ * gcc.target/powerpc/vadsduw-2.c: New test.
++
++2016-06-30 David Malcolm <dmalcolm at redhat.com>
++
++ Backport from trunk r237880.
++ 2016-06-30 David Malcolm <dmalcolm at redhat.com>
++
++ PR driver/71651
++ * gcc.dg/spellcheck-options-12.c: New test case.
++
+2016-06-30 Jakub Jelinek <jakub at redhat.com>
+
+ PR middle-end/71693
@@ -15538,6 +17083,16 @@ Index: gcc/testsuite/g++.dg/cpp0x/inh-ctor21.C
+int main() {
+ B b(abort_on_copy{});
+}
+Index: gcc/testsuite/g++.dg/cpp0x/pr71739.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp0x/pr71739.C (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp0x/pr71739.C (.../branches/gcc-6-branch)
+@@ -0,0 +1,5 @@
++// PR c++/71739
++// { dg-do compile { target c++11 } }
++
++template <int N> struct alignas(N) A;
++template <int N> struct alignas(N) A {};
Index: gcc/testsuite/g++.dg/cpp0x/constexpr-recursion2.C
===================================================================
--- a/src/gcc/testsuite/g++.dg/cpp0x/constexpr-recursion2.C (.../tags/gcc_6_1_0_release)
@@ -18042,6 +19597,18 @@ Index: gcc/dwarf2out.c
/* The point here is to flush out the limbo list so that it is empty
and we don't need to stream it for LTO. */
flush_limbo_die_list ();
+Index: gcc/opts.h
+===================================================================
+--- a/src/gcc/opts.h (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/opts.h (.../branches/gcc-6-branch)
+@@ -417,6 +417,7 @@
+ } sanitizer_opts[];
+
+ extern void add_misspelling_candidates (auto_vec<char *> *candidates,
++ const struct cl_option *option,
+ const char *base_option);
+
+ #endif
Index: gcc/ada/s-osinte-gnu.ads
===================================================================
--- a/src/gcc/ada/s-osinte-gnu.ads (.../tags/gcc_6_1_0_release)
@@ -20772,7 +22339,24 @@ Index: gcc/fortran/trans-openmp.c
===================================================================
--- a/src/gcc/fortran/trans-openmp.c (.../tags/gcc_6_1_0_release)
+++ b/src/gcc/fortran/trans-openmp.c (.../branches/gcc-6-branch)
-@@ -3497,7 +3497,8 @@
+@@ -61,6 +61,7 @@
+ if (GFC_DECL_GET_SCALAR_POINTER (decl)
+ || GFC_DECL_GET_SCALAR_ALLOCATABLE (decl)
+ || GFC_DECL_CRAY_POINTEE (decl)
++ || GFC_DECL_ASSOCIATE_VAR_P (decl)
+ || VOID_TYPE_P (TREE_TYPE (TREE_TYPE (decl))))
+ return false;
+
+@@ -2180,6 +2181,8 @@
+ tree decl = gfc_get_symbol_decl (n->sym);
+ if (gfc_omp_privatize_by_reference (decl))
+ decl = build_fold_indirect_ref (decl);
++ else if (DECL_P (decl))
++ TREE_ADDRESSABLE (decl) = 1;
+ if (GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (decl)))
+ {
+ tree type = TREE_TYPE (decl);
+@@ -3497,7 +3500,8 @@
construct_clauses.independent = false;
construct_clauses.tile_list = NULL;
construct_clauses.lists[OMP_LIST_PRIVATE] = NULL;
@@ -20885,7 +22469,44 @@ Index: gcc/fortran/ChangeLog
===================================================================
--- a/src/gcc/fortran/ChangeLog (.../tags/gcc_6_1_0_release)
+++ b/src/gcc/fortran/ChangeLog (.../branches/gcc-6-branch)
-@@ -1,3 +1,181 @@
+@@ -1,3 +1,218 @@
++2016-07-02 Jakub Jelinek <jakub at redhat.com>
++
++ Backported from mainline
++ 2016-07-01 Jakub Jelinek <jakub at redhat.com>
++
++ PR fortran/71687
++ * f95-lang.c (struct binding_level): Add reversed field.
++ (clear_binding_level): Adjust initializer.
++ (getdecls): If reversed is clear, set it and nreverse the names
++ chain before returning it.
++ (poplevel): Use getdecls.
++ * trans-decl.c (gfc_generate_function_code, gfc_process_block_locals):
++ Use nreverse to pushdecl decls in the declaration order.
++
++ PR fortran/71717
++ * trans-openmp.c (gfc_omp_privatize_by_reference): Return false
++ for GFC_DECL_ASSOCIATE_VAR_P with POINTER_TYPE.
++
++ 2016-06-30 Jakub Jelinek <jakub at redhat.com>
++
++ PR fortran/71704
++ * parse.c (matchs, matcho): Move right before decode_omp_directive.
++ If spec_only, only gfc_match the keyword and if successful, goto
++ do_spec_only.
++ (matchds, matchdo): Define.
++ (decode_omp_directive): Add spec_only local var and set it.
++ Use matchds or matchdo macros instead of matchs or matcho
++ for declare target, declare simd, declare reduction and threadprivate
++ directives. Return ST_GET_FCN_CHARACTERISTICS if a non-declarative
++ directive could be matched.
++ (next_statement): For ST_GET_FCN_CHARACTERISTICS restore
++ gfc_current_locus from old_locus even if there is no label.
++
++ PR fortran/71705
++ * trans-openmp.c (gfc_trans_omp_clauses): Set TREE_ADDRESSABLE on
++ decls in to/from clauses.
++
+2016-06-29 Cesar Philippidis <cesar at codesourcery.com>
+
+ Back port from trunk
@@ -22622,6 +24243,50 @@ Index: gcc/fortran/resolve.c
&& (!resolve_equivalence_derived(c->ts.u.derived, sym, e)))
return false;
+Index: gcc/fortran/f95-lang.c
+===================================================================
+--- a/src/gcc/fortran/f95-lang.c (.../tags/gcc_6_1_0_release)
++++ b/src/gcc/fortran/f95-lang.c (.../branches/gcc-6-branch)
+@@ -289,6 +289,9 @@
+ tree blocks;
+ /* The binding level containing this one (the enclosing binding level). */
+ struct binding_level *level_chain;
++ /* True if nreverse has been already called on names; if false, names
++ are ordered from newest declaration to oldest one. */
++ bool reversed;
+ };
+
+ /* The binding level currently in effect. */
+@@ -299,7 +302,7 @@
+ static GTY(()) struct binding_level *global_binding_level;
+
+ /* Binding level structures are initialized by copying this one. */
+-static struct binding_level clear_binding_level = { NULL, NULL, NULL };
++static struct binding_level clear_binding_level = { NULL, NULL, NULL, false };
+
+
+ /* Return true if we are in the global binding level. */
+@@ -313,6 +316,11 @@
+ tree
+ getdecls (void)
+ {
++ if (!current_binding_level->reversed)
++ {
++ current_binding_level->reversed = true;
++ current_binding_level->names = nreverse (current_binding_level->names);
++ }
+ return current_binding_level->names;
+ }
+
+@@ -350,7 +358,7 @@
+ binding level that we are about to exit and which is returned by this
+ routine. */
+ tree block_node = NULL_TREE;
+- tree decl_chain = current_binding_level->names;
++ tree decl_chain = getdecls ();
+ tree subblock_chain = current_binding_level->blocks;
+ tree subblock_node;
+
Index: gcc/fortran/trans-decl.c
===================================================================
--- a/src/gcc/fortran/trans-decl.c (.../tags/gcc_6_1_0_release)
@@ -22705,6 +24370,24 @@ Index: gcc/fortran/trans-decl.c
if (expr->expr_type != EXPR_STRUCTURE)
return false;
cm = expr->ts.u.derived->components;
+@@ -6260,7 +6276,7 @@
+ gfc_finish_block (&cleanup));
+
+ /* Add all the decls we created during processing. */
+- decl = saved_function_decls;
++ decl = nreverse (saved_function_decls);
+ while (decl)
+ {
+ tree next;
+@@ -6452,7 +6468,7 @@
+ if (flag_coarray == GFC_FCOARRAY_LIB && has_coarray_vars)
+ generate_coarray_init (ns);
+
+- decl = saved_local_decls;
++ decl = nreverse (saved_local_decls);
+ while (decl)
+ {
+ tree next;
Index: gcc/fortran/match.c
===================================================================
--- a/src/gcc/fortran/match.c (.../tags/gcc_6_1_0_release)
@@ -22927,7 +24610,173 @@ Index: gcc/fortran/parse.c
match ("unlock", gfc_match_unlock, ST_UNLOCK);
break;
-@@ -1386,10 +1390,14 @@
+@@ -585,28 +589,6 @@
+ return ST_NONE;
+ }
+
+-/* Like match, but set a flag simd_matched if keyword matched. */
+-#define matchs(keyword, subr, st) \
+- do { \
+- if (match_word_omp_simd (keyword, subr, &old_locus, \
+- &simd_matched) == MATCH_YES) \
+- return st; \
+- else \
+- undo_new_statement (); \
+- } while (0);
+-
+-/* Like match, but don't match anything if not -fopenmp. */
+-#define matcho(keyword, subr, st) \
+- do { \
+- if (!flag_openmp) \
+- ; \
+- else if (match_word (keyword, subr, &old_locus) \
+- == MATCH_YES) \
+- return st; \
+- else \
+- undo_new_statement (); \
+- } while (0);
+-
+ static gfc_statement
+ decode_oacc_directive (void)
+ {
+@@ -698,6 +680,56 @@
+ return ST_NONE;
+ }
+
++/* Like match, but set a flag simd_matched if keyword matched
++ and if spec_only, goto do_spec_only without actually matching. */
++#define matchs(keyword, subr, st) \
++ do { \
++ if (spec_only && gfc_match (keyword) == MATCH_YES) \
++ goto do_spec_only; \
++ if (match_word_omp_simd (keyword, subr, &old_locus, \
++ &simd_matched) == MATCH_YES) \
++ return st; \
++ else \
++ undo_new_statement (); \
++ } while (0);
++
++/* Like match, but don't match anything if not -fopenmp
++ and if spec_only, goto do_spec_only without actually matching. */
++#define matcho(keyword, subr, st) \
++ do { \
++ if (!flag_openmp) \
++ ; \
++ else if (spec_only && gfc_match (keyword) == MATCH_YES) \
++ goto do_spec_only; \
++ else if (match_word (keyword, subr, &old_locus) \
++ == MATCH_YES) \
++ return st; \
++ else \
++ undo_new_statement (); \
++ } while (0);
++
++/* Like match, but set a flag simd_matched if keyword matched. */
++#define matchds(keyword, subr, st) \
++ do { \
++ if (match_word_omp_simd (keyword, subr, &old_locus, \
++ &simd_matched) == MATCH_YES) \
++ return st; \
++ else \
++ undo_new_statement (); \
++ } while (0);
++
++/* Like match, but don't match anything if not -fopenmp. */
++#define matchdo(keyword, subr, st) \
++ do { \
++ if (!flag_openmp) \
++ ; \
++ else if (match_word (keyword, subr, &old_locus) \
++ == MATCH_YES) \
++ return st; \
++ else \
++ undo_new_statement (); \
++ } while (0);
++
+ static gfc_statement
+ decode_omp_directive (void)
+ {
+@@ -704,6 +736,7 @@
+ locus old_locus;
+ char c;
+ bool simd_matched = false;
++ bool spec_only = false;
+
+ gfc_enforce_clean_symbol_state ();
+
+@@ -718,6 +751,10 @@
+ return ST_NONE;
+ }
+
++ if (gfc_current_state () == COMP_FUNCTION
++ && gfc_current_block ()->result->ts.kind == -1)
++ spec_only = true;
++
+ gfc_unset_implicit_pure (NULL);
+
+ old_locus = gfc_current_locus;
+@@ -746,12 +783,12 @@
+ matcho ("critical", gfc_match_omp_critical, ST_OMP_CRITICAL);
+ break;
+ case 'd':
+- matchs ("declare reduction", gfc_match_omp_declare_reduction,
+- ST_OMP_DECLARE_REDUCTION);
+- matchs ("declare simd", gfc_match_omp_declare_simd,
+- ST_OMP_DECLARE_SIMD);
+- matcho ("declare target", gfc_match_omp_declare_target,
+- ST_OMP_DECLARE_TARGET);
++ matchds ("declare reduction", gfc_match_omp_declare_reduction,
++ ST_OMP_DECLARE_REDUCTION);
++ matchds ("declare simd", gfc_match_omp_declare_simd,
++ ST_OMP_DECLARE_SIMD);
++ matchdo ("declare target", gfc_match_omp_declare_target,
++ ST_OMP_DECLARE_TARGET);
+ matchs ("distribute parallel do simd",
+ gfc_match_omp_distribute_parallel_do_simd,
+ ST_OMP_DISTRIBUTE_PARALLEL_DO_SIMD);
+@@ -871,8 +908,8 @@
+ matcho ("teams distribute", gfc_match_omp_teams_distribute,
+ ST_OMP_TEAMS_DISTRIBUTE);
+ matcho ("teams", gfc_match_omp_teams, ST_OMP_TEAMS);
+- matcho ("threadprivate", gfc_match_omp_threadprivate,
+- ST_OMP_THREADPRIVATE);
++ matchdo ("threadprivate", gfc_match_omp_threadprivate,
++ ST_OMP_THREADPRIVATE);
+ break;
+ case 'w':
+ matcho ("workshare", gfc_match_omp_workshare, ST_OMP_WORKSHARE);
+@@ -895,6 +932,13 @@
+ gfc_error_recovery ();
+
+ return ST_NONE;
++
++ do_spec_only:
++ reject_statement ();
++ gfc_clear_error ();
++ gfc_buffer_error (false);
++ gfc_current_locus = old_locus;
++ return ST_GET_FCN_CHARACTERISTICS;
+ }
+
+ static gfc_statement
+@@ -1315,10 +1359,13 @@
+
+ gfc_buffer_error (false);
+
+- if (st == ST_GET_FCN_CHARACTERISTICS && gfc_statement_label != NULL)
++ if (st == ST_GET_FCN_CHARACTERISTICS)
+ {
+- gfc_free_st_label (gfc_statement_label);
+- gfc_statement_label = NULL;
++ if (gfc_statement_label != NULL)
++ {
++ gfc_free_st_label (gfc_statement_label);
++ gfc_statement_label = NULL;
++ }
+ gfc_current_locus = old_locus;
+ }
+
+@@ -1386,10 +1433,14 @@
#define case_decl case ST_ATTR_DECL: case ST_COMMON: case ST_DATA_DECL: \
case ST_EQUIVALENCE: case ST_NAMELIST: case ST_STATEMENT_FUNCTION: \
@@ -22945,7 +24794,7 @@ Index: gcc/fortran/parse.c
/* Block end statements. Errors associated with interchanging these
are detected in gfc_match_end(). */
-@@ -1642,6 +1650,15 @@
+@@ -1642,6 +1693,15 @@
case ST_DEALLOCATE:
p = "DEALLOCATE";
break;
@@ -22961,7 +24810,7 @@ Index: gcc/fortran/parse.c
case ST_DERIVED_DECL:
p = _("derived type declaration");
break;
-@@ -1711,6 +1728,15 @@
+@@ -1711,6 +1771,15 @@
case ST_END_WHERE:
p = "END WHERE";
break;
@@ -22977,7 +24826,7 @@ Index: gcc/fortran/parse.c
case ST_END_TYPE:
p = "END TYPE";
break;
-@@ -2457,6 +2483,7 @@
+@@ -2457,6 +2526,7 @@
case ST_PUBLIC:
case ST_PRIVATE:
@@ -22985,7 +24834,7 @@ Index: gcc/fortran/parse.c
case ST_DERIVED_DECL:
case_decl:
if (p->state >= ORDER_EXEC)
-@@ -2465,6 +2492,14 @@
+@@ -2465,6 +2535,14 @@
p->state = ORDER_SPEC;
break;
@@ -23000,7 +24849,7 @@ Index: gcc/fortran/parse.c
case_executable:
case_exec_markers:
if (p->state < ORDER_EXEC)
-@@ -2646,6 +2681,358 @@
+@@ -2646,6 +2724,358 @@
}
@@ -23359,7 +25208,7 @@ Index: gcc/fortran/parse.c
/* Parse a derived type. */
static void
-@@ -2762,171 +3149,8 @@
+@@ -2762,171 +3192,8 @@
*/
sym = gfc_current_block ();
for (c = sym->components; c; c = c->next)
@@ -23532,7 +25381,7 @@ Index: gcc/fortran/parse.c
if (!seen_component)
sym->attr.zero_comp = 1;
-@@ -3348,8 +3572,10 @@
+@@ -3348,8 +3615,10 @@
case ST_PARAMETER:
case ST_PUBLIC:
case ST_PRIVATE:
@@ -23543,7 +25392,7 @@ Index: gcc/fortran/parse.c
declSt:
if (!verify_st_order (&ss, st, false))
{
-@@ -3364,6 +3590,10 @@
+@@ -3364,6 +3633,10 @@
parse_interface ();
break;
@@ -808019,7 +809868,56 @@ Index: gcc/config/i386/i386.c
===================================================================
--- a/src/gcc/config/i386/i386.c (.../tags/gcc_6_1_0_release)
+++ b/src/gcc/config/i386/i386.c (.../branches/gcc-6-branch)
-@@ -18895,7 +18895,7 @@
+@@ -18787,12 +18787,29 @@
+ of the register, once we have that information we may be able
+ to handle some of them more efficiently. */
+ if (can_create_pseudo_p ()
+- && register_operand (op0, mode)
+ && (CONSTANT_P (op1)
+ || (SUBREG_P (op1)
+ && CONSTANT_P (SUBREG_REG (op1))))
+- && !standard_sse_constant_p (op1))
+- op1 = validize_mem (force_const_mem (mode, op1));
++ && ((register_operand (op0, mode)
++ && !standard_sse_constant_p (op1))
++ /* ix86_expand_vector_move_misalign() does not like constants. */
++ || (SSE_REG_MODE_P (mode)
++ && MEM_P (op0)
++ && MEM_ALIGN (op0) < align)))
++ {
++ if (SUBREG_P (op1))
++ {
++ machine_mode imode = GET_MODE (SUBREG_REG (op1));
++ rtx r = force_const_mem (imode, SUBREG_REG (op1));
++ if (r)
++ r = validize_mem (r);
++ else
++ r = force_reg (imode, SUBREG_REG (op1));
++ op1 = simplify_gen_subreg (mode, r, imode, SUBREG_BYTE (op1));
++ }
++ else
++ op1 = validize_mem (force_const_mem (mode, op1));
++ }
+
+ /* We need to check memory alignment for SSE mode since attribute
+ can make operands unaligned. */
+@@ -18803,13 +18820,8 @@
+ {
+ rtx tmp[2];
+
+- /* ix86_expand_vector_move_misalign() does not like constants ... */
+- if (CONSTANT_P (op1)
+- || (SUBREG_P (op1)
+- && CONSTANT_P (SUBREG_REG (op1))))
+- op1 = validize_mem (force_const_mem (mode, op1));
+-
+- /* ... nor both arguments in memory. */
++ /* ix86_expand_vector_move_misalign() does not like both
++ arguments in memory. */
+ if (!register_operand (op0, mode)
+ && !register_operand (op1, mode))
+ op1 = force_reg (mode, op1);
+@@ -18895,7 +18907,7 @@
m = adjust_address (op0, mode, 0);
emit_insn (extract (m, op1, const0_rtx));
m = adjust_address (op0, mode, 16);
@@ -808028,7 +809926,7 @@ Index: gcc/config/i386/i386.c
}
else
emit_insn (store_unaligned (op0, op1));
-@@ -19203,7 +19203,7 @@
+@@ -19203,7 +19215,7 @@
m = adjust_address (op0, V2SFmode, 0);
emit_insn (gen_sse_storelps (m, op1));
m = adjust_address (op0, V2SFmode, 8);
@@ -808037,7 +809935,46 @@ Index: gcc/config/i386/i386.c
}
}
}
-@@ -30686,7 +30686,7 @@
+@@ -23027,17 +23039,33 @@
+ switch (code)
+ {
+ case EQ:
+- return 0x08;
++ return 0x00;
+ case NE:
+ return 0x04;
+ case GT:
+- return 0x16;
++ return 0x0e;
+ case LE:
+- return 0x1a;
++ return 0x02;
+ case GE:
+- return 0x15;
++ return 0x0d;
+ case LT:
+- return 0x19;
++ return 0x01;
++ case UNLE:
++ return 0x0a;
++ case UNLT:
++ return 0x09;
++ case UNGE:
++ return 0x05;
++ case UNGT:
++ return 0x06;
++ case UNEQ:
++ return 0x18;
++ case LTGT:
++ return 0x0c;
++ case ORDERED:
++ return 0x07;
++ case UNORDERED:
++ return 0x03;
+ default:
+ gcc_unreachable ();
+ }
+@@ -30686,7 +30714,7 @@
IX86_BUILTIN_CVTPD2PS512,
IX86_BUILTIN_CVTPD2UDQ512,
IX86_BUILTIN_CVTPH2PS512,
@@ -808046,7 +809983,7 @@ Index: gcc/config/i386/i386.c
IX86_BUILTIN_CVTPS2PD512,
IX86_BUILTIN_CVTPS2PH512,
IX86_BUILTIN_CVTPS2UDQ512,
-@@ -32126,7 +32126,6 @@
+@@ -32126,7 +32154,6 @@
IX86_BUILTIN_COPYSIGNQ,
/* Vectorizer support builtins. */
@@ -808054,7 +809991,7 @@ Index: gcc/config/i386/i386.c
IX86_BUILTIN_CPYSGNPS,
IX86_BUILTIN_CPYSGNPD,
IX86_BUILTIN_CPYSGNPS256,
-@@ -32133,7 +32132,19 @@
+@@ -32133,7 +32160,19 @@
IX86_BUILTIN_CPYSGNPS512,
IX86_BUILTIN_CPYSGNPD256,
IX86_BUILTIN_CPYSGNPD512,
@@ -808074,7 +810011,7 @@ Index: gcc/config/i386/i386.c
IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512,
-@@ -32787,9 +32798,9 @@
+@@ -32787,9 +32826,9 @@
{ OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
{ OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
{ OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
@@ -808086,7 +810023,7 @@ Index: gcc/config/i386/i386.c
/* FSGSBASE */
{ OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
-@@ -33724,12 +33735,12 @@
+@@ -33724,12 +33763,12 @@
/* BMI */
{ OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
@@ -808101,7 +810038,7 @@ Index: gcc/config/i386/i386.c
/* F16C */
{ OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
-@@ -33739,11 +33750,11 @@
+@@ -33739,11 +33778,11 @@
/* BMI2 */
{ OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
@@ -808116,7 +810053,7 @@ Index: gcc/config/i386/i386.c
/* AVX512F */
{ OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_256si, "__builtin_ia32_si512_256si", IX86_BUILTIN_SI512_SI256, UNKNOWN, (int) V16SI_FTYPE_V8SI },
-@@ -33948,6 +33959,17 @@
+@@ -33948,6 +33987,17 @@
{ OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF },
{ OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF },
{ OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF },
@@ -808134,7 +810071,7 @@ Index: gcc/config/i386/i386.c
{ OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF },
{ OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
{ OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
-@@ -34864,7 +34886,7 @@
+@@ -34864,7 +34914,7 @@
{ OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
{ OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_notruncv8dfv8si2_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
{ OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
@@ -808143,7 +810080,7 @@ Index: gcc/config/i386/i386.c
{ OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
{ OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
{ OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT },
-@@ -38441,10 +38463,13 @@
+@@ -38441,10 +38491,13 @@
{
case V2DF_FTYPE_V2DF_ROUND:
case V4DF_FTYPE_V4DF_ROUND:
@@ -808157,7 +810094,7 @@ Index: gcc/config/i386/i386.c
return ix86_expand_sse_round (d, exp, target);
case V4SI_FTYPE_V2DF_V2DF_ROUND:
case V8SI_FTYPE_V4DF_V4DF_ROUND:
-@@ -38558,6 +38583,7 @@
+@@ -38558,6 +38611,7 @@
case V16SI_FTYPE_V8SI:
case V16SF_FTYPE_V4SF:
case V16SI_FTYPE_V4SI:
@@ -808165,7 +810102,7 @@ Index: gcc/config/i386/i386.c
case V16SF_FTYPE_V16SF:
case V8DI_FTYPE_UQI:
case V8DF_FTYPE_V4DF:
-@@ -42263,6 +42289,8 @@
+@@ -42263,6 +42317,8 @@
return ix86_get_builtin (IX86_BUILTIN_FLOORPS_SFIX);
else if (out_n == 8 && in_n == 8)
return ix86_get_builtin (IX86_BUILTIN_FLOORPS_SFIX256);
@@ -808174,7 +810111,7 @@ Index: gcc/config/i386/i386.c
}
break;
-@@ -42288,6 +42316,8 @@
+@@ -42288,6 +42344,8 @@
return ix86_get_builtin (IX86_BUILTIN_CEILPS_SFIX);
else if (out_n == 8 && in_n == 8)
return ix86_get_builtin (IX86_BUILTIN_CEILPS_SFIX256);
@@ -808183,7 +810120,7 @@ Index: gcc/config/i386/i386.c
}
break;
-@@ -42300,6 +42330,8 @@
+@@ -42300,6 +42358,8 @@
return ix86_get_builtin (IX86_BUILTIN_VEC_PACK_SFIX);
else if (out_n == 8 && in_n == 4)
return ix86_get_builtin (IX86_BUILTIN_VEC_PACK_SFIX256);
@@ -808192,7 +810129,7 @@ Index: gcc/config/i386/i386.c
}
if (out_mode == SImode && in_mode == SFmode)
{
-@@ -42307,6 +42339,8 @@
+@@ -42307,6 +42367,8 @@
return ix86_get_builtin (IX86_BUILTIN_CVTPS2DQ);
else if (out_n == 8 && in_n == 8)
return ix86_get_builtin (IX86_BUILTIN_CVTPS2DQ256);
@@ -808201,7 +810138,7 @@ Index: gcc/config/i386/i386.c
}
break;
-@@ -42332,6 +42366,8 @@
+@@ -42332,6 +42394,8 @@
return ix86_get_builtin (IX86_BUILTIN_ROUNDPS_AZ_SFIX);
else if (out_n == 8 && in_n == 8)
return ix86_get_builtin (IX86_BUILTIN_ROUNDPS_AZ_SFIX256);
@@ -808210,7 +810147,7 @@ Index: gcc/config/i386/i386.c
}
break;
-@@ -42346,6 +42382,8 @@
+@@ -42346,6 +42410,8 @@
return ix86_get_builtin (IX86_BUILTIN_FLOORPD);
else if (out_n == 4 && in_n == 4)
return ix86_get_builtin (IX86_BUILTIN_FLOORPD256);
@@ -808219,7 +810156,7 @@ Index: gcc/config/i386/i386.c
}
if (out_mode == SFmode && in_mode == SFmode)
{
-@@ -42353,6 +42391,8 @@
+@@ -42353,6 +42419,8 @@
return ix86_get_builtin (IX86_BUILTIN_FLOORPS);
else if (out_n == 8 && in_n == 8)
return ix86_get_builtin (IX86_BUILTIN_FLOORPS256);
@@ -808228,7 +810165,7 @@ Index: gcc/config/i386/i386.c
}
break;
-@@ -42367,6 +42407,8 @@
+@@ -42367,6 +42435,8 @@
return ix86_get_builtin (IX86_BUILTIN_CEILPD);
else if (out_n == 4 && in_n == 4)
return ix86_get_builtin (IX86_BUILTIN_CEILPD256);
@@ -808237,7 +810174,7 @@ Index: gcc/config/i386/i386.c
}
if (out_mode == SFmode && in_mode == SFmode)
{
-@@ -42374,6 +42416,8 @@
+@@ -42374,6 +42444,8 @@
return ix86_get_builtin (IX86_BUILTIN_CEILPS);
else if (out_n == 8 && in_n == 8)
return ix86_get_builtin (IX86_BUILTIN_CEILPS256);
@@ -808246,7 +810183,7 @@ Index: gcc/config/i386/i386.c
}
break;
-@@ -42388,6 +42432,8 @@
+@@ -42388,6 +42460,8 @@
return ix86_get_builtin (IX86_BUILTIN_TRUNCPD);
else if (out_n == 4 && in_n == 4)
return ix86_get_builtin (IX86_BUILTIN_TRUNCPD256);
@@ -808255,7 +810192,7 @@ Index: gcc/config/i386/i386.c
}
if (out_mode == SFmode && in_mode == SFmode)
{
-@@ -42395,6 +42441,8 @@
+@@ -42395,6 +42469,8 @@
return ix86_get_builtin (IX86_BUILTIN_TRUNCPS);
else if (out_n == 8 && in_n == 8)
return ix86_get_builtin (IX86_BUILTIN_TRUNCPS256);
@@ -808545,7 +810482,7 @@ Index: gcc/config/rs6000/predicates.md
- else if (GET_MODE_SIZE (GET_MODE (op)) != 16)
- ret = 0;
-+ return quad_address_p (XEXP (op, 0), mode, true);
++ return quad_address_p (XEXP (op, 0), mode, false);
+})
- else if (MEM_ALIGN (op) < 128)
@@ -808633,8 +810570,7 @@ Index: gcc/config/rs6000/rs6000-cpus.def
/* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add
- P9_DFORM or P9_MINMAX until they are fully debugged. */
-+ P9_MINMAX until the hardware that supports it is available. Do not add
-+ P9_DFORM_VECTOR until LRA is the default register allocator. */
++ P9_MINMAX until the hardware that supports it is available. */
#define ISA_3_0_MASKS_SERVER (ISA_2_7_MASKS_SERVER \
| OPTION_MASK_FLOAT128_HW \
| OPTION_MASK_ISEL \
@@ -808642,6 +810578,7 @@ Index: gcc/config/rs6000/rs6000-cpus.def
| OPTION_MASK_P9_FUSION \
- | OPTION_MASK_P9_DFORM \
+ | OPTION_MASK_P9_DFORM_SCALAR \
++ | OPTION_MASK_P9_DFORM_VECTOR \
| OPTION_MASK_P9_VECTOR)
#define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)
@@ -808748,10 +810685,26 @@ Index: gcc/config/rs6000/rs6000-builtin.def
/* 128-bit long double floating point builtins. */
#define BU_LDBL128_2(ENUM, NAME, ATTR, ICODE) \
RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \
-@@ -647,8 +687,113 @@
+@@ -647,8 +687,129 @@
| RS6000_BTC_BINARY), \
CODE_FOR_ ## ICODE) /* ICODE */
++/* IEEE 128-bit floating-point builtins. */
++#define BU_FLOAT128_2(ENUM, NAME, ATTR, ICODE) \
++ RS6000_BUILTIN_2 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \
++ "__builtin_" NAME, /* NAME */ \
++ RS6000_BTM_FLOAT128, /* MASK */ \
++ (RS6000_BTC_ ## ATTR /* ATTR */ \
++ | RS6000_BTC_BINARY), \
++ CODE_FOR_ ## ICODE) /* ICODE */
++
++#define BU_FLOAT128_1(ENUM, NAME, ATTR, ICODE) \
++ RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM, /* ENUM */ \
++ "__builtin_" NAME, /* NAME */ \
++ RS6000_BTM_FLOAT128, /* MASK */ \
++ (RS6000_BTC_ ## ATTR /* ATTR */ \
++ | RS6000_BTC_UNARY), \
++ CODE_FOR_ ## ICODE) /* ICODE */
+
+/* Miscellaneous builtins for instructions added in ISA 3.0. These
+ instructions don't require either the DFP or VSX options, just the basic
@@ -808862,7 +810815,7 @@ Index: gcc/config/rs6000/rs6000-builtin.def
/* Insure 0 is not a legitimate index. */
BU_SPECIAL_X (RS6000_BUILTIN_NONE, NULL, 0, RS6000_BTC_MISC)
-@@ -1391,13 +1536,25 @@
+@@ -1391,13 +1552,25 @@
BU_VSX_X (LXVW4X_V8HI, "lxvw4x_v8hi", MEM)
BU_VSX_X (LXVW4X_V16QI, "lxvw4x_v16qi", MEM)
BU_VSX_X (STXSDX, "stxsdx", MEM)
@@ -808895,7 +810848,7 @@ Index: gcc/config/rs6000/rs6000-builtin.def
BU_VSX_X (XSABSDP, "xsabsdp", CONST)
BU_VSX_X (XSADDDP, "xsadddp", FP)
BU_VSX_X (XSCMPODP, "xscmpodp", FP)
-@@ -1455,6 +1612,8 @@
+@@ -1455,6 +1628,8 @@
/* VSX builtins that are handled as special cases. */
BU_VSX_OVERLOAD_X (LD, "ld")
BU_VSX_OVERLOAD_X (ST, "st")
@@ -808904,7 +810857,33 @@ Index: gcc/config/rs6000/rs6000-builtin.def
/* 1 argument VSX instructions added in ISA 2.07. */
BU_P8V_VSX_1 (XSCVSPDPN, "xscvspdpn", CONST, vsx_xscvspdpn)
-@@ -1639,6 +1798,11 @@
+@@ -1589,6 +1764,25 @@
+ BU_P8V_OVERLOAD_3 (VSUBECUQ, "vsubecuq")
+ BU_P8V_OVERLOAD_3 (VSUBEUQM, "vsubeuqm")
+
++/* ISA 3.0 vector overloaded 2-argument functions. */
++BU_P9V_AV_2 (VSLV, "vslv", CONST, vslv)
++BU_P9V_AV_2 (VSRV, "vsrv", CONST, vsrv)
++
++/* ISA 3.0 vector overloaded 2-argument functions. */
++BU_P9V_OVERLOAD_2 (VSLV, "vslv")
++BU_P9V_OVERLOAD_2 (VSRV, "vsrv")
++
++/* 2 argument vector functions added in ISA 3.0 (power9). */
++BU_P9V_AV_2 (VADUB, "vadub", CONST, vaduv16qi3)
++BU_P9V_AV_2 (VADUH, "vaduh", CONST, vaduv8hi3)
++BU_P9V_AV_2 (VADUW, "vaduw", CONST, vaduv4si3)
++
++/* ISA 3.0 vector overloaded 2 argument functions. */
++BU_P9V_OVERLOAD_2 (VADU, "vadu")
++BU_P9V_OVERLOAD_2 (VADUB, "vadub")
++BU_P9V_OVERLOAD_2 (VADUH, "vaduh")
++BU_P9V_OVERLOAD_2 (VADUW, "vaduw")
++
+
+ /* 2 argument extended divide functions added in ISA 2.06. */
+ BU_P7_MISC_2 (DIVWE, "divwe", CONST, dive_si)
+@@ -1639,6 +1833,11 @@
BU_DFP_MISC_2 (PACK_TD, "pack_dec128", CONST, packtd)
BU_DFP_MISC_2 (UNPACK_TD, "unpack_dec128", CONST, unpacktd)
@@ -808916,7 +810895,7 @@ Index: gcc/config/rs6000/rs6000-builtin.def
BU_LDBL128_2 (PACK_TF, "pack_longdouble", CONST, packtf)
BU_LDBL128_2 (UNPACK_TF, "unpack_longdouble", CONST, unpacktf)
-@@ -1645,6 +1809,26 @@
+@@ -1645,6 +1844,31 @@
BU_P7_MISC_2 (PACK_V1TI, "pack_vector_int128", CONST, packv1ti)
BU_P7_MISC_2 (UNPACK_V1TI, "unpack_vector_int128", CONST, unpackv1ti)
@@ -808940,9 +810919,33 @@ Index: gcc/config/rs6000/rs6000-builtin.def
+BU_P9V_OVERLOAD_1 (VPRTYBQ, "vprtybq")
+BU_P9V_OVERLOAD_1 (VPRTYBW, "vprtybw")
+
++/* 1 argument IEEE 128-bit floating-point functions. */
++BU_FLOAT128_1 (FABSQ, "fabsq", CONST, abskf2)
++
++/* 2 argument IEEE 128-bit floating-point functions. */
++BU_FLOAT128_2 (COPYSIGNQ, "copysignq", CONST, copysignkf3)
/* 1 argument crypto functions. */
BU_CRYPTO_1 (VSBOX, "vsbox", CONST, crypto_vsbox)
+@@ -2022,6 +2246,18 @@
+ BU_SPECIAL_X (RS6000_BUILTIN_CPU_SUPPORTS, "__builtin_cpu_supports",
+ RS6000_BTM_ALWAYS, RS6000_BTC_MISC)
+
++BU_SPECIAL_X (RS6000_BUILTIN_NANQ, "__builtin_nanq",
++ RS6000_BTM_FLOAT128, RS6000_BTC_CONST)
++
++BU_SPECIAL_X (RS6000_BUILTIN_NANSQ, "__builtin_nansq",
++ RS6000_BTM_FLOAT128, RS6000_BTC_CONST)
++
++BU_SPECIAL_X (RS6000_BUILTIN_INFQ, "__builtin_infq",
++ RS6000_BTM_FLOAT128, RS6000_BTC_CONST)
++
++BU_SPECIAL_X (RS6000_BUILTIN_HUGE_VALQ, "__builtin_huge_valq",
++ RS6000_BTM_FLOAT128, RS6000_BTC_CONST)
++
+ /* Darwin CfString builtin. */
+ BU_SPECIAL_X (RS6000_BUILTIN_CFSTRING, "__builtin_cfstring", RS6000_BTM_ALWAYS,
+ RS6000_BTC_MISC)
Index: gcc/config/rs6000/rs6000-c.c
===================================================================
--- a/src/gcc/config/rs6000/rs6000-c.c (.../tags/gcc_6_1_0_release)
@@ -809053,7 +811056,7 @@ Index: gcc/config/rs6000/rs6000-c.c
{ VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI,
RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE },
{ VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI,
-@@ -4123,6 +4215,43 @@
+@@ -4123,6 +4215,65 @@
{ P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
@@ -809094,10 +811097,32 @@ Index: gcc/config/rs6000/rs6000-c.c
+ { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD,
+ RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
+
++ { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUB,
++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
++ RS6000_BTI_unsigned_V16QI, 0 },
++ { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUH,
++ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
++ RS6000_BTI_unsigned_V8HI, 0 },
++ { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUW,
++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
++ RS6000_BTI_unsigned_V4SI, 0 },
++
++ { P9V_BUILTIN_VEC_VADUB, P9V_BUILTIN_VADUB,
++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
++ RS6000_BTI_unsigned_V16QI, 0 },
++
++ { P9V_BUILTIN_VEC_VADUH, P9V_BUILTIN_VADUH,
++ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI,
++ RS6000_BTI_unsigned_V8HI, 0 },
++
++ { P9V_BUILTIN_VEC_VADUW, P9V_BUILTIN_VADUW,
++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI,
++ RS6000_BTI_unsigned_V4SI, 0 },
++
{ P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 },
{ P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
-@@ -4252,6 +4381,42 @@
+@@ -4252,6 +4403,42 @@
{ P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD,
RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 },
@@ -809140,6 +811165,20 @@ Index: gcc/config/rs6000/rs6000-c.c
{ P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
{ P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM,
+@@ -4328,6 +4515,13 @@
+ { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
+ RS6000_BTI_unsigned_V16QI, 0, 0, 0 },
+
++ { P9V_BUILTIN_VEC_VSLV, P9V_BUILTIN_VSLV,
++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
++ RS6000_BTI_unsigned_V16QI, 0 },
++ { P9V_BUILTIN_VEC_VSRV, P9V_BUILTIN_VSRV,
++ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
++ RS6000_BTI_unsigned_V16QI, 0 },
++
+ /* Crypto builtins. */
+ { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI,
+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
Index: gcc/config/rs6000/rs6000.opt
===================================================================
--- a/src/gcc/config/rs6000/rs6000.opt (.../tags/gcc_6_1_0_release)
@@ -809230,7 +811269,25 @@ Index: gcc/config/rs6000/rs6000.c
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
-@@ -1866,7 +1882,7 @@
+@@ -1312,6 +1328,7 @@
+ bool);
+ rtl_opt_pass *make_pass_analyze_swaps (gcc::context*);
+ static bool rs6000_keep_leaf_when_profiled () __attribute__ ((unused));
++static tree rs6000_fold_builtin (tree, int, tree *, bool);
+
+ /* Hash table stuff for keeping track of TOC entries. */
+
+@@ -1586,6 +1603,9 @@
+ #undef TARGET_BUILTIN_DECL
+ #define TARGET_BUILTIN_DECL rs6000_builtin_decl
+
++#undef TARGET_FOLD_BUILTIN
++#define TARGET_FOLD_BUILTIN rs6000_fold_builtin
++
+ #undef TARGET_EXPAND_BUILTIN
+ #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
+
+@@ -1866,7 +1886,7 @@
128-bit floating point that can go in vector registers, which has VSX
memory addressing. */
if (FP_REGNO_P (regno))
@@ -809239,7 +811296,7 @@ Index: gcc/config/rs6000/rs6000.c
? UNITS_PER_VSX_WORD
: UNITS_PER_FP_WORD);
-@@ -1898,6 +1914,9 @@
+@@ -1898,6 +1918,9 @@
{
int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
@@ -809249,7 +811306,7 @@ Index: gcc/config/rs6000/rs6000.c
/* PTImode can only go in GPRs. Quad word memory operations require even/odd
register combinations, and use PTImode where we need to deal with quad
word memory operations. Don't allow quad words in the argument or frame
-@@ -2105,7 +2124,9 @@
+@@ -2105,7 +2128,9 @@
else if (keep_spaces)
*p++ = ' ';
@@ -809260,7 +811317,7 @@ Index: gcc/config/rs6000/rs6000.c
*p++ = 'o';
else if (keep_spaces)
*p++ = ' ';
-@@ -2642,8 +2663,7 @@
+@@ -2642,8 +2667,7 @@
if (TARGET_LINK_STACK)
fprintf (stderr, DEBUG_FMT_S, "link_stack", "true");
@@ -809270,7 +811327,7 @@ Index: gcc/config/rs6000/rs6000.c
if (TARGET_P8_FUSION)
{
-@@ -2699,9 +2719,18 @@
+@@ -2699,9 +2723,18 @@
for (m = 0; m < NUM_MACHINE_MODES; ++m)
{
@@ -809291,7 +811348,7 @@ Index: gcc/config/rs6000/rs6000.c
/* SDmode is special in that we want to access it only via REG+REG
addressing on power7 and above, since we want to use the LFIWZX and
STFIWZX instructions to load it. */
-@@ -2722,7 +2751,7 @@
+@@ -2722,7 +2755,7 @@
/* Indicate if the mode takes more than 1 physical register. If
it takes a single register, indicate it can do REG+REG
addressing. */
@@ -809300,7 +811357,7 @@ Index: gcc/config/rs6000/rs6000.c
addr_mask |= RELOAD_REG_MULTIPLE;
else
addr_mask |= RELOAD_REG_INDEXED;
-@@ -2738,7 +2767,7 @@
+@@ -2738,7 +2771,7 @@
&& msize <= 8
&& !VECTOR_MODE_P (m2)
&& !FLOAT128_VECTOR_P (m2)
@@ -809309,7 +811366,7 @@ Index: gcc/config/rs6000/rs6000.c
&& (m2 != DFmode || !TARGET_UPPER_REGS_DF)
&& (m2 != SFmode || !TARGET_UPPER_REGS_SF)
&& !(TARGET_E500_DOUBLE && msize == 8))
-@@ -2769,17 +2798,31 @@
+@@ -2769,17 +2802,31 @@
}
/* GPR and FPR registers can do REG+OFFSET addressing, except
@@ -809347,7 +811404,7 @@ Index: gcc/config/rs6000/rs6000.c
/* VMX registers can do (REG & -16) and ((REG+REG) & -16)
addressing on 128-bit types. */
if (rc == RELOAD_REG_VMX && msize == 16
-@@ -3102,7 +3145,7 @@
+@@ -3102,7 +3149,7 @@
}
/* Support for new D-form instructions. */
@@ -809356,7 +811413,7 @@ Index: gcc/config/rs6000/rs6000.c
rs6000_constraints[RS6000_CONSTRAINT_wb] = ALTIVEC_REGS;
/* Support for ISA 3.0 (power9) vectors. */
-@@ -3621,6 +3664,9 @@
+@@ -3621,11 +3668,15 @@
| ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)
| ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0)
| ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0)
@@ -809366,7 +811423,14 @@ Index: gcc/config/rs6000/rs6000.c
| ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0)
| ((TARGET_HTM) ? RS6000_BTM_HTM : 0)
| ((TARGET_DFP) ? RS6000_BTM_DFP : 0)
-@@ -3974,7 +4020,8 @@
+ | ((TARGET_HARD_FLOAT) ? RS6000_BTM_HARD_FLOAT : 0)
+- | ((TARGET_LONG_DOUBLE_128) ? RS6000_BTM_LDBL128 : 0));
++ | ((TARGET_LONG_DOUBLE_128) ? RS6000_BTM_LDBL128 : 0)
++ | ((TARGET_FLOAT128) ? RS6000_BTM_FLOAT128 : 0));
+ }
+
+ /* Implement TARGET_MD_ASM_ADJUST. All asm statements are considered
+@@ -3974,7 +4025,8 @@
/* For the newer switches (vsx, dfp, etc.) set some of the older options,
unless the user explicitly used the -mno-<option> to disable the code. */
@@ -809376,18 +811440,15 @@ Index: gcc/config/rs6000/rs6000.c
rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~rs6000_isa_flags_explicit);
else if (TARGET_P8_VECTOR || TARGET_DIRECT_MOVE || TARGET_CRYPTO)
rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~rs6000_isa_flags_explicit);
-@@ -4188,26 +4235,49 @@
+@@ -4188,26 +4240,46 @@
&& !(rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION))
rs6000_isa_flags |= OPTION_MASK_TOC_FUSION;
+ /* -mpower9-dform turns on both -mpower9-dform-scalar and
-+ -mpower9-dform-vector. There are currently problems if
-+ -mpower9-dform-vector instructions are enabled when we use the RELOAD
-+ register allocator. */
++ -mpower9-dform-vector. */
+ if (TARGET_P9_DFORM_BOTH > 0)
+ {
-+ if (!(rs6000_isa_flags_explicit & OPTION_MASK_P9_DFORM_VECTOR)
-+ && TARGET_LRA)
++ if (!(rs6000_isa_flags_explicit & OPTION_MASK_P9_DFORM_VECTOR))
+ rs6000_isa_flags |= OPTION_MASK_P9_DFORM_VECTOR;
+
+ if (!(rs6000_isa_flags_explicit & OPTION_MASK_P9_DFORM_SCALAR))
@@ -809432,15 +811493,14 @@ Index: gcc/config/rs6000/rs6000.c
}
/* ISA 3.0 vector instructions include ISA 2.07. */
-@@ -4218,6 +4288,47 @@
+@@ -4218,6 +4290,32 @@
rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR;
}
-+ /* There have been bugs with both -mvsx-timode and -mpower9-dform-vector that
-+ don't show up with -mlra, but do show up with -mno-lra. Given -mlra will
-+ become the default once PR 69847 is fixed, turn off the options with
-+ problems by default if -mno-lra was used, and warn if the user explicitly
-+ asked for the option.
++ /* There have been bugs with -mvsx-timode that don't show up with -mlra,
++ but do show up with -mno-lra. Given -mlra will become the default once
++ PR 69847 is fixed, turn off the options with problems by default if
++ -mno-lra was used, and warn if the user explicitly asked for the option.
+
+ Enable -mpower9-dform-vector by default if LRA and other power9 options.
+ Enable -mvsx-timode by default if LRA and VSX. */
@@ -809454,15 +811514,6 @@ Index: gcc/config/rs6000/rs6000.c
+ else
+ rs6000_isa_flags &= ~OPTION_MASK_VSX_TIMODE;
+ }
-+
-+ if (TARGET_P9_DFORM_VECTOR)
-+ {
-+ if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_DFORM_VECTOR) != 0)
-+ warning (0, "-mpower9-dform-vector might need -mlra");
-+
-+ else
-+ rs6000_isa_flags &= ~OPTION_MASK_P9_DFORM_VECTOR;
-+ }
+ }
+
+ else
@@ -809470,17 +811521,12 @@ Index: gcc/config/rs6000/rs6000.c
+ if (TARGET_VSX && !TARGET_VSX_TIMODE
+ && (rs6000_isa_flags_explicit & OPTION_MASK_VSX_TIMODE) == 0)
+ rs6000_isa_flags |= OPTION_MASK_VSX_TIMODE;
-+
-+ if (TARGET_VSX && TARGET_P9_VECTOR && !TARGET_P9_DFORM_VECTOR
-+ && TARGET_P9_DFORM_SCALAR && TARGET_P9_DFORM_BOTH < 0
-+ && (rs6000_isa_flags_explicit & OPTION_MASK_P9_DFORM_VECTOR) == 0)
-+ rs6000_isa_flags |= OPTION_MASK_P9_DFORM_VECTOR;
+ }
+
/* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
support. If we only have ISA 2.06 support, and the user did not specify
the switch, leave it set to -1 so the movmisalign patterns are enabled,
-@@ -6134,6 +6245,128 @@
+@@ -6134,6 +6232,128 @@
gcc_unreachable ();
}
@@ -809609,7 +811655,7 @@ Index: gcc/config/rs6000/rs6000.c
const char *
output_vec_const_move (rtx *operands)
{
-@@ -6147,24 +6380,61 @@
+@@ -6147,24 +6367,61 @@
if (TARGET_VSX)
{
@@ -809679,7 +811725,7 @@ Index: gcc/config/rs6000/rs6000.c
/* Do we need to construct a value using VSLDOI? */
shift = vspltis_shifted (vec);
if (shift != 0)
-@@ -6436,6 +6706,15 @@
+@@ -6436,6 +6693,15 @@
return;
}
@@ -809695,7 +811741,7 @@ Index: gcc/config/rs6000/rs6000.c
/* With single precision floating point on VSX, know that internally single
precision is actually represented as a double, and either make 2 V2DF
vectors, and convert these vectors to single precision, or do one
-@@ -6444,14 +6723,23 @@
+@@ -6444,14 +6710,23 @@
{
if (all_same)
{
@@ -809726,7 +811772,7 @@ Index: gcc/config/rs6000/rs6000.c
}
else
{
-@@ -6572,21 +6860,29 @@
+@@ -6572,21 +6847,29 @@
gen_rtvec (3, target, reg,
force_reg (V16QImode, x)),
UNSPEC_VPERM);
@@ -809769,7 +811815,7 @@ Index: gcc/config/rs6000/rs6000.c
}
emit_insn (gen_rtx_SET (target, x));
-@@ -6902,6 +7198,59 @@
+@@ -6902,6 +7185,49 @@
return false;
}
@@ -809789,34 +811835,24 @@ Index: gcc/config/rs6000/rs6000.c
+ 3.0 LXV/STXV instruction. */
+
+bool
-+quad_address_p (rtx addr, machine_mode mode, bool gpr_p)
++quad_address_p (rtx addr, machine_mode mode, bool strict)
+{
+ rtx op0, op1;
+
+ if (GET_MODE_SIZE (mode) != 16)
+ return false;
+
-+ if (gpr_p)
-+ {
-+ if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI)
-+ return false;
-+
-+ /* LQ/STQ can handle indirect addresses. */
-+ if (base_reg_operand (addr, Pmode))
-+ return true;
-+ }
++ if (legitimate_indirect_address_p (addr, strict))
++ return true;
+
-+ else
-+ {
-+ if (!mode_supports_vsx_dform_quad (mode))
-+ return false;
-+ }
++ if (VECTOR_MODE_P (mode) && !mode_supports_vsx_dform_quad (mode))
++ return false;
+
+ if (GET_CODE (addr) != PLUS)
+ return false;
+
+ op0 = XEXP (addr, 0);
-+ if (!base_reg_operand (op0, Pmode))
++ if (!REG_P (op0) || !INT_REG_OK_FOR_BASE_P (op0, strict))
+ return false;
+
+ op1 = XEXP (addr, 1);
@@ -809829,7 +811865,7 @@ Index: gcc/config/rs6000/rs6000.c
/* Return true if this is a load or store quad operation. This function does
not handle the atomic quad memory instructions. */
-@@ -6994,6 +7343,10 @@
+@@ -6994,6 +7320,10 @@
if (TARGET_POWERPC64 && (offset & 3) != 0)
return false;
@@ -809840,7 +811876,7 @@ Index: gcc/config/rs6000/rs6000.c
extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
if (extra < 0)
extra = 0;
-@@ -7023,13 +7376,14 @@
+@@ -7023,13 +7353,14 @@
case TImode:
case TFmode:
case KFmode:
@@ -809861,7 +811897,7 @@ Index: gcc/config/rs6000/rs6000.c
break;
case V4HImode:
-@@ -7096,6 +7450,11 @@
+@@ -7096,6 +7427,11 @@
if (GET_CODE (op) != SYMBOL_REF)
return false;
@@ -809873,17 +811909,16 @@ Index: gcc/config/rs6000/rs6000.c
dsize = GET_MODE_SIZE (mode);
decl = SYMBOL_REF_DECL (op);
if (!decl)
-@@ -7250,6 +7609,9 @@
+@@ -7250,6 +7586,8 @@
return false;
if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
return false;
+ if (mode_supports_vsx_dform_quad (mode))
-+ return (virtual_stack_registers_memory_p (x)
-+ || quad_address_p (x, mode, false));
++ return quad_address_p (x, mode, strict);
if (!reg_offset_addressing_ok_p (mode))
return virtual_stack_registers_memory_p (x);
if (legitimate_constant_pool_address_p (x, mode, strict || lra_in_progress))
-@@ -7388,6 +7750,9 @@
+@@ -7388,6 +7726,9 @@
return false;
if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
return false;
@@ -809893,7 +811928,7 @@ Index: gcc/config/rs6000/rs6000.c
/* Restrict addressing for DI because of our SUBREG hackery. */
if (TARGET_E500_DOUBLE && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
return false;
-@@ -7399,7 +7764,7 @@
+@@ -7399,7 +7740,7 @@
if (DEFAULT_ABI == ABI_V4 && flag_pic)
return false;
@@ -809902,7 +811937,7 @@ Index: gcc/config/rs6000/rs6000.c
push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
recognizes some LO_SUM addresses as valid although this
function says opposite. In most cases, LRA through different
-@@ -7453,7 +7818,8 @@
+@@ -7453,7 +7794,8 @@
{
unsigned int extra;
@@ -809912,9 +811947,11 @@ Index: gcc/config/rs6000/rs6000.c
{
if (virtual_stack_registers_memory_p (x))
return x;
-@@ -8149,12 +8515,16 @@
+@@ -8148,13 +8490,18 @@
+ int ind_levels ATTRIBUTE_UNUSED, int *win)
{
bool reg_offset_p = reg_offset_addressing_ok_p (mode);
++ bool quad_offset_p = mode_supports_vsx_dform_quad (mode);
- /* Nasty hack for vsx_splat_V2DF/V2DI load from mem, which takes a
- DFmode/DImode MEM. */
@@ -809932,7 +811969,7 @@ Index: gcc/config/rs6000/rs6000.c
reg_offset_p = false;
/* We must recognize output that we have already generated ourselves. */
-@@ -8164,6 +8534,11 @@
+@@ -8164,6 +8511,11 @@
&& GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
&& GET_CODE (XEXP (x, 1)) == CONST_INT)
{
@@ -809944,7 +811981,7 @@ Index: gcc/config/rs6000/rs6000.c
push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
opnum, (enum reload_type) type);
-@@ -8175,6 +8550,11 @@
+@@ -8175,6 +8527,11 @@
if (GET_CODE (x) == LO_SUM
&& GET_CODE (XEXP (x, 0)) == HIGH)
{
@@ -809956,7 +811993,12 @@ Index: gcc/config/rs6000/rs6000.c
push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
opnum, (enum reload_type) type);
-@@ -8207,6 +8587,11 @@
+@@ -8203,10 +8560,16 @@
+
+ if (TARGET_CMODEL != CMODEL_SMALL
+ && reg_offset_p
++ && !quad_offset_p
+ && small_toc_ref (x, VOIDmode))
{
rtx hi = gen_rtx_HIGH (Pmode, copy_rtx (x));
x = gen_rtx_LO_SUM (Pmode, hi, x);
@@ -809968,7 +812010,38 @@ Index: gcc/config/rs6000/rs6000.c
push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
opnum, (enum reload_type) type);
-@@ -8244,6 +8629,11 @@
+@@ -8215,14 +8578,14 @@
+ }
+
+ if (GET_CODE (x) == PLUS
+- && GET_CODE (XEXP (x, 0)) == REG
++ && REG_P (XEXP (x, 0))
+ && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
+ && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1)
+- && GET_CODE (XEXP (x, 1)) == CONST_INT
++ && CONST_INT_P (XEXP (x, 1))
+ && reg_offset_p
+ && !SPE_VECTOR_MODE (mode)
+ && !(TARGET_E500_DOUBLE && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
+- && (!VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode)))
++ && (quad_offset_p || !VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode)))
+ {
+ HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
+ HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
+@@ -8229,8 +8592,10 @@
+ HOST_WIDE_INT high
+ = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
+
+- /* Check for 32-bit overflow. */
+- if (high + low != val)
++ /* Check for 32-bit overflow or quad addresses with one of the
++ four least significant bits set. */
++ if (high + low != val
++ || (quad_offset_p && (low & 0xf)))
+ {
+ *win = 0;
+ return x;
+@@ -8244,6 +8609,11 @@
GEN_INT (high)),
GEN_INT (low));
@@ -809980,7 +812053,15 @@ Index: gcc/config/rs6000/rs6000.c
push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
opnum, (enum reload_type) type);
-@@ -8304,6 +8694,11 @@
+@@ -8253,6 +8623,7 @@
+
+ if (GET_CODE (x) == SYMBOL_REF
+ && reg_offset_p
++ && !quad_offset_p
+ && (!VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode))
+ && !SPE_VECTOR_MODE (mode)
+ #if TARGET_MACHO
+@@ -8304,6 +8675,11 @@
x = gen_rtx_LO_SUM (GET_MODE (x),
gen_rtx_HIGH (Pmode, x), x);
@@ -809992,7 +812073,13 @@ Index: gcc/config/rs6000/rs6000.c
push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
opnum, (enum reload_type) type);
-@@ -8337,9 +8732,16 @@
+@@ -8332,14 +8708,22 @@
+
+ if (TARGET_TOC
+ && reg_offset_p
++ && !quad_offset_p
+ && GET_CODE (x) == SYMBOL_REF
+ && use_toc_relative_ref (x, mode))
{
x = create_TOC_reference (x, NULL_RTX);
if (TARGET_CMODEL != CMODEL_SMALL)
@@ -810012,7 +812099,7 @@ Index: gcc/config/rs6000/rs6000.c
*win = 1;
return x;
}
-@@ -8395,6 +8797,7 @@
+@@ -8395,6 +8779,7 @@
rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict)
{
bool reg_offset_p = reg_offset_addressing_ok_p (mode);
@@ -810020,21 +812107,23 @@ Index: gcc/config/rs6000/rs6000.c
/* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
if (VECTOR_MEM_ALTIVEC_P (mode)
-@@ -8414,15 +8817,26 @@
+@@ -8412,17 +8797,27 @@
+ && mode_supports_pre_incdec_p (mode)
+ && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
return 1;
- if (virtual_stack_registers_memory_p (x))
- return 1;
-- if (reg_offset_p && legitimate_small_data_p (mode, x))
-- return 1;
-- if (reg_offset_p
-- && legitimate_constant_pool_address_p (x, mode,
-+
+- if (virtual_stack_registers_memory_p (x))
+ /* Handle restricted vector d-form offsets in ISA 3.0. */
+ if (quad_offset_p)
+ {
-+ if (quad_address_p (x, mode, false))
++ if (quad_address_p (x, mode, reg_ok_strict))
+ return 1;
+ }
++ else if (virtual_stack_registers_memory_p (x))
+ return 1;
+- if (reg_offset_p && legitimate_small_data_p (mode, x))
+- return 1;
+- if (reg_offset_p
+- && legitimate_constant_pool_address_p (x, mode,
+
+ else if (reg_offset_p)
+ {
@@ -810055,7 +812144,7 @@ Index: gcc/config/rs6000/rs6000.c
/* For TImode, if we have load/store quad and TImode in VSX registers, only
allow register indirect addresses. This will allow the values to go in
either GPRs or VSX registers without reloading. The vector types would
-@@ -8461,7 +8875,8 @@
+@@ -8461,7 +8856,8 @@
&& legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict)))
&& rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
return 1;
@@ -810065,7 +812154,7 @@ Index: gcc/config/rs6000/rs6000.c
return 1;
return 0;
}
-@@ -10044,6 +10459,35 @@
+@@ -10044,6 +10440,35 @@
return must_pass_in_stack_var_size_or_pad (mode, type);
}
@@ -810101,7 +812190,7 @@ Index: gcc/config/rs6000/rs6000.c
/* If defined, a C expression which determines whether, and in which
direction, to pad out an argument with extra space. The value
should be of type `enum direction': either `upward' to pad above
-@@ -10128,6 +10572,7 @@
+@@ -10128,6 +10553,7 @@
&& (GET_MODE_SIZE (mode) == 8
|| (TARGET_HARD_FLOAT
&& TARGET_FPRS
@@ -810109,7 +812198,7 @@ Index: gcc/config/rs6000/rs6000.c
&& FLOAT128_2REG_P (mode))))
return 64;
else if (FLOAT128_VECTOR_P (mode))
-@@ -10507,11 +10952,7 @@
+@@ -10507,11 +10933,7 @@
}
else if (DEFAULT_ABI == ABI_V4)
{
@@ -810122,7 +812211,7 @@ Index: gcc/config/rs6000/rs6000.c
{
/* _Decimal128 must use an even/odd register pair. This assumes
that the register number is odd when fregno is odd. */
-@@ -11168,11 +11609,7 @@
+@@ -11168,11 +11590,7 @@
else if (abi == ABI_V4)
{
@@ -810135,7 +812224,7 @@ Index: gcc/config/rs6000/rs6000.c
{
/* _Decimal128 must use an even/odd register pair. This assumes
that the register number is odd when fregno is odd. */
-@@ -12093,12 +12530,8 @@
+@@ -12093,12 +12511,8 @@
rsize = (size + 3) / 4;
align = 1;
@@ -810150,7 +812239,7 @@ Index: gcc/config/rs6000/rs6000.c
{
/* FP args go in FP registers, if present. */
reg = fpr;
-@@ -12105,7 +12538,7 @@
+@@ -12105,7 +12519,7 @@
n_reg = (size + 7) / 8;
sav_ofs = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4) * 4;
sav_scale = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4);
@@ -810159,7 +812248,7 @@ Index: gcc/config/rs6000/rs6000.c
align = 8;
}
else
-@@ -12125,7 +12558,7 @@
+@@ -12125,7 +12539,7 @@
addr = create_tmp_var (ptr_type_node, "addr");
/* AltiVec vectors never go in registers when -mabi=altivec. */
@@ -810168,7 +812257,7 @@ Index: gcc/config/rs6000/rs6000.c
align = 16;
else
{
-@@ -12146,7 +12579,7 @@
+@@ -12146,7 +12560,7 @@
}
/* _Decimal128 is passed in even/odd fpr pairs; the stored
reg number is 0 for f1, so we want to make it odd. */
@@ -810177,7 +812266,7 @@ Index: gcc/config/rs6000/rs6000.c
{
t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
build_int_cst (TREE_TYPE (reg), 1));
-@@ -12173,7 +12606,7 @@
+@@ -12173,7 +12587,7 @@
FP register for 32-bit binaries. */
if (TARGET_32BIT
&& TARGET_HARD_FLOAT && TARGET_FPRS
@@ -810186,7 +812275,7 @@ Index: gcc/config/rs6000/rs6000.c
t = fold_build_pointer_plus_hwi (t, size);
gimplify_assign (addr, t, pre_p);
-@@ -12260,7 +12693,7 @@
+@@ -12260,7 +12674,7 @@
/* const function, function only depends on the inputs. */
TREE_READONLY (t) = 1;
TREE_NOTHROW (t) = 1;
@@ -810195,7 +812284,7 @@ Index: gcc/config/rs6000/rs6000.c
}
else if ((classify & RS6000_BTC_PURE) != 0)
{
-@@ -12268,7 +12701,7 @@
+@@ -12268,7 +12682,7 @@
external state. */
DECL_PURE_P (t) = 1;
TREE_NOTHROW (t) = 1;
@@ -810204,7 +812293,7 @@ Index: gcc/config/rs6000/rs6000.c
}
else if ((classify & RS6000_BTC_FP) != 0)
{
-@@ -12300,6 +12733,7 @@
+@@ -12300,6 +12714,7 @@
/* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
@@ -810212,7 +812301,7 @@ Index: gcc/config/rs6000/rs6000.c
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
-@@ -12312,6 +12746,7 @@
+@@ -12312,6 +12727,7 @@
#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
@@ -810220,7 +812309,7 @@ Index: gcc/config/rs6000/rs6000.c
#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
-@@ -12333,6 +12768,7 @@
+@@ -12333,6 +12749,7 @@
/* DST operations: void foo (void *, const int, const char). */
@@ -810228,7 +812317,7 @@ Index: gcc/config/rs6000/rs6000.c
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
-@@ -12345,6 +12781,7 @@
+@@ -12345,6 +12762,7 @@
#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
@@ -810236,7 +812325,7 @@ Index: gcc/config/rs6000/rs6000.c
#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
-@@ -12366,6 +12803,7 @@
+@@ -12366,6 +12784,7 @@
/* Simple binary operations: VECc = foo (VECa, VECb). */
@@ -810244,7 +812333,7 @@ Index: gcc/config/rs6000/rs6000.c
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
-@@ -12378,6 +12816,7 @@
+@@ -12378,6 +12797,7 @@
#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
@@ -810252,7 +812341,7 @@ Index: gcc/config/rs6000/rs6000.c
#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
{ MASK, ICODE, NAME, ENUM },
-@@ -12397,6 +12836,7 @@
+@@ -12397,6 +12817,7 @@
#include "rs6000-builtin.def"
};
@@ -810260,7 +812349,7 @@ Index: gcc/config/rs6000/rs6000.c
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
-@@ -12409,6 +12849,7 @@
+@@ -12409,6 +12830,7 @@
#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
@@ -810268,7 +812357,7 @@ Index: gcc/config/rs6000/rs6000.c
#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
-@@ -12431,6 +12872,7 @@
+@@ -12431,6 +12853,7 @@
};
/* SPE predicates. */
@@ -810276,7 +812365,7 @@ Index: gcc/config/rs6000/rs6000.c
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
-@@ -12443,6 +12885,7 @@
+@@ -12443,6 +12866,7 @@
#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
@@ -810284,7 +812373,7 @@ Index: gcc/config/rs6000/rs6000.c
#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
-@@ -12463,6 +12906,7 @@
+@@ -12463,6 +12887,7 @@
};
/* SPE evsel predicates. */
@@ -810292,7 +812381,7 @@ Index: gcc/config/rs6000/rs6000.c
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
-@@ -12475,6 +12919,7 @@
+@@ -12475,6 +12900,7 @@
#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
@@ -810300,7 +812389,7 @@ Index: gcc/config/rs6000/rs6000.c
#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
-@@ -12495,6 +12940,7 @@
+@@ -12495,6 +12921,7 @@
};
/* PAIRED predicates. */
@@ -810308,7 +812397,7 @@ Index: gcc/config/rs6000/rs6000.c
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
-@@ -12507,6 +12953,7 @@
+@@ -12507,6 +12934,7 @@
#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
@@ -810316,7 +812405,7 @@ Index: gcc/config/rs6000/rs6000.c
#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
-@@ -12528,6 +12975,7 @@
+@@ -12528,6 +12956,7 @@
/* ABS* operations. */
@@ -810324,7 +812413,7 @@ Index: gcc/config/rs6000/rs6000.c
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
-@@ -12540,6 +12988,7 @@
+@@ -12540,6 +12969,7 @@
#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
@@ -810332,7 +812421,7 @@ Index: gcc/config/rs6000/rs6000.c
#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
-@@ -12562,6 +13011,7 @@
+@@ -12562,6 +12992,7 @@
/* Simple unary operations: VECb = foo (unsigned literal) or VECb =
foo (VECa). */
@@ -810340,7 +812429,7 @@ Index: gcc/config/rs6000/rs6000.c
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
-@@ -12574,6 +13024,7 @@
+@@ -12574,6 +13005,7 @@
#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
@@ -810348,7 +812437,7 @@ Index: gcc/config/rs6000/rs6000.c
#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
{ MASK, ICODE, NAME, ENUM },
-@@ -12593,7 +13044,43 @@
+@@ -12593,7 +13025,43 @@
#include "rs6000-builtin.def"
};
@@ -810392,7 +812481,7 @@ Index: gcc/config/rs6000/rs6000.c
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
-@@ -12606,6 +13093,7 @@
+@@ -12606,6 +13074,7 @@
#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
@@ -810400,7 +812489,7 @@ Index: gcc/config/rs6000/rs6000.c
#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
-@@ -12625,6 +13113,7 @@
+@@ -12625,6 +13094,7 @@
#include "rs6000-builtin.def"
};
@@ -810408,7 +812497,7 @@ Index: gcc/config/rs6000/rs6000.c
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
-@@ -14129,6 +14618,47 @@
+@@ -14129,6 +14599,47 @@
case VSX_BUILTIN_STXVW4X_V16QI:
return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp);
@@ -810456,7 +812545,7 @@ Index: gcc/config/rs6000/rs6000.c
case ALTIVEC_BUILTIN_MFVSCR:
icode = CODE_FOR_altivec_mfvscr;
tmode = insn_data[icode].operand[0].mode;
-@@ -14323,6 +14853,46 @@
+@@ -14323,6 +14834,46 @@
case VSX_BUILTIN_LXVW4X_V16QI:
return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi,
exp, target, false);
@@ -810503,7 +812592,7 @@ Index: gcc/config/rs6000/rs6000.c
break;
default:
break;
-@@ -14792,6 +15362,8 @@
+@@ -14792,6 +15343,8 @@
error ("Builtin function %s requires the -mhard-dfp option", name);
else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0)
error ("Builtin function %s requires the -mpower8-vector option", name);
@@ -810512,7 +812601,65 @@ Index: gcc/config/rs6000/rs6000.c
else if ((fnmask & (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
== (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
error ("Builtin function %s requires the -mhard-float and"
-@@ -14990,9 +15562,11 @@
+@@ -14798,11 +15351,57 @@
+ " -mlong-double-128 options", name);
+ else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0)
+ error ("Builtin function %s requires the -mhard-float option", name);
++ else if ((fnmask & RS6000_BTM_FLOAT128) != 0)
++ error ("Builtin function %s requires the -mfloat128 option", name);
+ else
+ error ("Builtin function %s is not supported with the current options",
+ name);
+ }
+
++/* Target hook for early folding of built-ins, shamelessly stolen
++ from ia64.c. */
++
++static tree
++rs6000_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED,
++ tree *args, bool ignore ATTRIBUTE_UNUSED)
++{
++ if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD)
++ {
++ enum rs6000_builtins fn_code
++ = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
++ switch (fn_code)
++ {
++ case RS6000_BUILTIN_NANQ:
++ case RS6000_BUILTIN_NANSQ:
++ {
++ tree type = TREE_TYPE (TREE_TYPE (fndecl));
++ const char *str = c_getstr (*args);
++ int quiet = fn_code == RS6000_BUILTIN_NANQ;
++ REAL_VALUE_TYPE real;
++
++ if (str && real_nan (&real, str, quiet, TYPE_MODE (type)))
++ return build_real (type, real);
++ return NULL_TREE;
++ }
++ case RS6000_BUILTIN_INFQ:
++ case RS6000_BUILTIN_HUGE_VALQ:
++ {
++ tree type = TREE_TYPE (TREE_TYPE (fndecl));
++ REAL_VALUE_TYPE inf;
++ real_inf (&inf);
++ return build_real (type, inf);
++ }
++ default:
++ break;
++ }
++ }
++#ifdef SUBTARGET_FOLD_BUILTIN
++ return SUBTARGET_FOLD_BUILTIN (fndecl, n_args, args, ignore);
++#else
++ return NULL_TREE;
++#endif
++}
++
+ /* Expand an expression EXP that calls a built-in function,
+ with result going to TARGET if that's convenient
+ (and in mode MODE if that's convenient).
+@@ -14990,9 +15589,11 @@
}
unsigned attr = rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK;
@@ -810525,7 +812672,7 @@ Index: gcc/config/rs6000/rs6000.c
/* Handle simple unary operations. */
d = bdesc_1arg;
-@@ -15012,6 +15586,12 @@
+@@ -15012,6 +15613,12 @@
if (d->code == fcode)
return rs6000_expand_ternop_builtin (d->icode, exp, target);
@@ -810538,7 +812685,47 @@ Index: gcc/config/rs6000/rs6000.c
gcc_unreachable ();
}
-@@ -15816,10 +16396,44 @@
+@@ -15049,6 +15656,10 @@
+ opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
+ opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
+
++ const_str_type_node
++ = build_pointer_type (build_qualified_type (char_type_node,
++ TYPE_QUAL_CONST));
++
+ /* We use V1TI mode as a special container to hold __int128_t items that
+ must live in VSX registers. */
+ if (intTI_type_node)
+@@ -15111,6 +15722,12 @@
+ lang_hooks.types.register_builtin_type (ibm128_float_type_node,
+ "__ibm128");
+ }
++ else
++ {
++ /* All types must be nonzero, or self-test barfs during bootstrap. */
++ ieee128_float_type_node = long_double_type_node;
++ ibm128_float_type_node = long_double_type_node;
++ }
+
+ /* Initialize the modes for builtin_function_type, mapping a machine mode to
+ tree type node. */
+@@ -15252,6 +15869,15 @@
+ if (TARGET_EXTRA_BUILTINS || TARGET_SPE || TARGET_PAIRED_FLOAT)
+ rs6000_common_init_builtins ();
+
++ ftype = build_function_type_list (ieee128_float_type_node,
++ const_str_type_node, NULL_TREE);
++ def_builtin ("__builtin_nanq", ftype, RS6000_BUILTIN_NANQ);
++ def_builtin ("__builtin_nansq", ftype, RS6000_BUILTIN_NANSQ);
++
++ ftype = build_function_type_list (ieee128_float_type_node, NULL_TREE);
++ def_builtin ("__builtin_infq", ftype, RS6000_BUILTIN_INFQ);
++ def_builtin ("__builtin_huge_valq", ftype, RS6000_BUILTIN_HUGE_VALQ);
++
+ ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
+ RS6000_BUILTIN_RECIP, "__builtin_recipdiv");
+ def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP);
+@@ -15816,10 +16442,44 @@
VSX_BUILTIN_STXVW4X_V8HI);
def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid,
VSX_BUILTIN_STXVW4X_V16QI);
@@ -810583,7 +812770,7 @@ Index: gcc/config/rs6000/rs6000.c
def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
-@@ -16351,10 +16965,6 @@
+@@ -16351,10 +17011,6 @@
while (num_args > 0 && h.mode[num_args] == VOIDmode)
num_args--;
@@ -810594,7 +812781,7 @@ Index: gcc/config/rs6000/rs6000.c
ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]];
if (!ret_type && h.uns_p[0])
ret_type = builtin_mode_to_type[h.mode[0]][0];
-@@ -16406,6 +17016,7 @@
+@@ -16406,6 +17062,7 @@
tree opaque_ftype_opaque = NULL_TREE;
tree opaque_ftype_opaque_opaque = NULL_TREE;
tree opaque_ftype_opaque_opaque_opaque = NULL_TREE;
@@ -810602,7 +812789,7 @@ Index: gcc/config/rs6000/rs6000.c
tree v2si_ftype_qi = NULL_TREE;
tree v2si_ftype_v2si_qi = NULL_TREE;
tree v2si_ftype_int_qi = NULL_TREE;
-@@ -16622,6 +17233,64 @@
+@@ -16622,6 +17279,64 @@
def_builtin (d->name, type, d->code);
}
@@ -810667,7 +812854,7 @@ Index: gcc/config/rs6000/rs6000.c
}
/* Set up AIX/Darwin/64-bit Linux quad floating point routines. */
-@@ -18006,25 +18675,33 @@
+@@ -18006,25 +18721,33 @@
addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX]
& ~RELOAD_REG_AND_M16);
@@ -810712,7 +812899,7 @@ Index: gcc/config/rs6000/rs6000.c
return -1;
}
-@@ -18152,6 +18829,16 @@
+@@ -18152,6 +18875,16 @@
}
}
@@ -810729,7 +812916,7 @@ Index: gcc/config/rs6000/rs6000.c
/* Make sure the register class can handle offset addresses. */
else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
{
-@@ -18158,7 +18845,7 @@
+@@ -18158,7 +18891,7 @@
if ((addr_mask & RELOAD_REG_OFFSET) == 0)
{
extra_cost = 1;
@@ -810738,7 +812925,7 @@ Index: gcc/config/rs6000/rs6000.c
}
}
-@@ -18171,8 +18858,15 @@
+@@ -18171,8 +18904,15 @@
break;
case LO_SUM:
@@ -810755,7 +812942,7 @@ Index: gcc/config/rs6000/rs6000.c
fail_msg = "bad LO_SUM";
extra_cost = -1;
}
-@@ -18188,8 +18882,17 @@
+@@ -18188,8 +18928,17 @@
case CONST:
case SYMBOL_REF:
case LABEL_REF:
@@ -810775,7 +812962,7 @@ Index: gcc/config/rs6000/rs6000.c
break;
/* TOC references look like offsetable memory. */
-@@ -18200,6 +18903,12 @@
+@@ -18200,6 +18949,12 @@
extra_cost = -1;
}
@@ -810788,7 +812975,26 @@ Index: gcc/config/rs6000/rs6000.c
else if ((addr_mask & RELOAD_REG_OFFSET) == 0)
{
extra_cost = 1;
-@@ -18653,6 +19362,9 @@
+@@ -18256,7 +19011,8 @@
+ simple move insns are issued. At present, 32-bit integers are not allowed
+ in FPR/VSX registers. Single precision binary floating is not a simple
+ move because we need to convert to the single precision memory layout.
+- The 4-byte SDmode can be moved. */
++ The 4-byte SDmode can be moved. TDmode values are disallowed since they
++ need special direct move handling, which we do not support yet. */
+ size = GET_MODE_SIZE (mode);
+ if (TARGET_DIRECT_MOVE
+ && ((mode == SDmode) || (TARGET_POWERPC64 && size == 8))
+@@ -18264,7 +19020,7 @@
+ || (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)))
+ return true;
+
+- else if (TARGET_DIRECT_MOVE_128 && size == 16
++ else if (TARGET_DIRECT_MOVE_128 && size == 16 && mode != TDmode
+ && ((to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
+ || (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)))
+ return true;
+@@ -18653,6 +19409,9 @@
fprintf (stderr, ", reload func = %s, extra cost = %d",
insn_data[sri->icode].name, sri->extra_cost);
@@ -810798,7 +813004,7 @@ Index: gcc/config/rs6000/rs6000.c
fputs ("\n", stderr);
debug_rtx (x);
}
-@@ -18827,6 +19539,16 @@
+@@ -18827,6 +19586,16 @@
}
}
@@ -810815,7 +813021,7 @@ Index: gcc/config/rs6000/rs6000.c
/* Make sure the register class can handle offset addresses. */
else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
{
-@@ -18857,6 +19579,13 @@
+@@ -18857,6 +19626,13 @@
}
}
@@ -810829,7 +813035,7 @@ Index: gcc/config/rs6000/rs6000.c
/* Make sure the register class can handle offset addresses. */
else if (legitimate_lo_sum_address_p (mode, addr, false))
{
-@@ -19046,6 +19775,16 @@
+@@ -19046,6 +19822,16 @@
machine_mode mode = GET_MODE (x);
bool is_constant = CONSTANT_P (x);
@@ -810846,7 +813052,7 @@ Index: gcc/config/rs6000/rs6000.c
/* For VSX, see if we should prefer FLOAT_REGS or ALTIVEC_REGS. Do not allow
the reloading of address expressions using PLUS into floating point
registers. */
-@@ -19067,7 +19806,8 @@
+@@ -19067,7 +19853,8 @@
}
/* D-form addressing can easily reload the value. */
@@ -810856,7 +813062,7 @@ Index: gcc/config/rs6000/rs6000.c
return rclass;
/* If this is a scalar floating point value and we don't have D-form
-@@ -19095,6 +19835,25 @@
+@@ -19095,6 +19882,25 @@
return NO_REGS;
}
@@ -810882,13 +813088,13 @@ Index: gcc/config/rs6000/rs6000.c
if (GET_MODE_CLASS (mode) == MODE_INT && rclass == NON_SPECIAL_REGS)
return GENERAL_REGS;
-@@ -19483,8 +20242,16 @@
+@@ -19483,8 +20289,16 @@
else if (TARGET_VSX && dest_vsx_p)
{
- if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
+ if (mode_supports_vsx_dform_quad (mode)
-+ && quad_address_p (XEXP (src, 0), mode, false))
++ && quad_address_p (XEXP (src, 0), mode, true))
+ return "lxv %x0,%1";
+
+ else if (TARGET_P9_VECTOR)
@@ -810900,13 +813106,13 @@ Index: gcc/config/rs6000/rs6000.c
else
return "lxvd2x %x0,%y1";
}
-@@ -19513,8 +20280,16 @@
+@@ -19513,8 +20327,16 @@
else if (TARGET_VSX && src_vsx_p)
{
- if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
+ if (mode_supports_vsx_dform_quad (mode)
-+ && quad_address_p (XEXP (dest, 0), mode, false))
++ && quad_address_p (XEXP (dest, 0), mode, true))
+ return "stxv %x1,%0";
+
+ else if (TARGET_P9_VECTOR)
@@ -810918,7 +813124,7 @@ Index: gcc/config/rs6000/rs6000.c
else
return "stxvd2x %x1,%y0";
}
-@@ -19536,10 +20311,8 @@
+@@ -19536,10 +20358,8 @@
if (dest_gpr_p)
return "#";
@@ -810931,7 +813137,7 @@ Index: gcc/config/rs6000/rs6000.c
return output_vec_const_move (operands);
}
-@@ -21747,6 +22520,101 @@
+@@ -21747,6 +22567,101 @@
return 1;
}
@@ -811033,7 +813239,7 @@ Index: gcc/config/rs6000/rs6000.c
/* Emit a conditional move: move TRUE_COND to DEST if OP of the
operands of the last comparison is nonzero/true, FALSE_COND if it
is zero/false. Return 0 if the hardware has no such operation. */
-@@ -21773,6 +22641,18 @@
+@@ -21773,6 +22688,18 @@
if (GET_MODE (false_cond) != result_mode)
return 0;
@@ -811052,7 +813258,7 @@ Index: gcc/config/rs6000/rs6000.c
/* Don't allow using floating point comparisons for integer results for
now. */
if (FLOAT_MODE_P (compare_mode) && !FLOAT_MODE_P (result_mode))
-@@ -25949,7 +26829,7 @@
+@@ -25949,7 +26876,7 @@
if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
{
rtx areg, savereg, mem;
@@ -811061,7 +813267,7 @@ Index: gcc/config/rs6000/rs6000.c
offset = (info->altivec_save_offset + frame_off
+ 16 * (i - info->first_altivec_reg_save));
-@@ -25956,18 +26836,30 @@
+@@ -25956,18 +26883,30 @@
savereg = gen_rtx_REG (V4SImode, i);
@@ -811102,7 +813308,7 @@ Index: gcc/config/rs6000/rs6000.c
rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
areg, GEN_INT (offset));
-@@ -26687,23 +27579,35 @@
+@@ -26687,23 +27626,35 @@
for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
{
@@ -811152,7 +813358,7 @@ Index: gcc/config/rs6000/rs6000.c
}
}
-@@ -26890,23 +27794,35 @@
+@@ -26890,23 +27841,35 @@
for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
{
@@ -811202,7 +813408,7 @@ Index: gcc/config/rs6000/rs6000.c
}
}
-@@ -27724,6 +28640,11 @@
+@@ -27724,6 +28687,11 @@
const0_rtx, const0_rtx));
call_fusage = NULL_RTX;
use_reg (&call_fusage, r12);
@@ -811214,7 +813420,7 @@ Index: gcc/config/rs6000/rs6000.c
add_function_usage_to (insn, call_fusage);
emit_insn (gen_frame_load (r0, r1, info->lr_save_offset));
insn = emit_move_insn (lr, r0);
-@@ -33448,17 +34369,25 @@
+@@ -33448,17 +34416,25 @@
if (!REG_P (target))
tmp = gen_reg_rtx (mode);
@@ -811250,7 +813456,7 @@ Index: gcc/config/rs6000/rs6000.c
/* Copy into target, possibly by way of a register. */
if (!REG_P (target))
-@@ -33869,8 +34798,14 @@
+@@ -33869,8 +34845,14 @@
machine_mode inner = GET_MODE_INNER (mode);
unsigned int inner_bytes = GET_MODE_UNIT_SIZE (mode);
@@ -811266,7 +813472,7 @@ Index: gcc/config/rs6000/rs6000.c
else
{
regno = GP_ARG_RETURN;
-@@ -34056,7 +34991,7 @@
+@@ -34056,7 +35038,7 @@
static bool
rs6000_lra_p (void)
{
@@ -811275,7 +813481,7 @@ Index: gcc/config/rs6000/rs6000.c
}
/* Given FROM and TO register numbers, say whether this elimination is allowed.
-@@ -34417,7 +35352,8 @@
+@@ -34417,7 +35399,8 @@
{ "power8-fusion", OPTION_MASK_P8_FUSION, false, true },
{ "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true },
{ "power8-vector", OPTION_MASK_P8_VECTOR, false, true },
@@ -811285,7 +813491,7 @@ Index: gcc/config/rs6000/rs6000.c
{ "power9-fusion", OPTION_MASK_P9_FUSION, false, true },
{ "power9-minmax", OPTION_MASK_P9_MINMAX, false, true },
{ "power9-vector", OPTION_MASK_P9_VECTOR, false, true },
-@@ -34474,6 +35410,7 @@
+@@ -34474,11 +35457,13 @@
{ "popcntd", RS6000_BTM_POPCNTD, false, false },
{ "cell", RS6000_BTM_CELL, false, false },
{ "power8-vector", RS6000_BTM_P8_VECTOR, false, false },
@@ -811293,7 +813499,13 @@ Index: gcc/config/rs6000/rs6000.c
{ "crypto", RS6000_BTM_CRYPTO, false, false },
{ "htm", RS6000_BTM_HTM, false, false },
{ "hard-dfp", RS6000_BTM_DFP, false, false },
-@@ -35049,7 +35986,9 @@
+ { "hard-float", RS6000_BTM_HARD_FLOAT, false, false },
+ { "long-double-128", RS6000_BTM_LDBL128, false, false },
++ { "float128", RS6000_BTM_FLOAT128, false, false },
+ };
+
+ /* Option variables that we want to support inside attribute((target)) and
+@@ -35049,7 +36034,9 @@
size_t i;
size_t start_column = 0;
size_t cur_column;
@@ -811304,7 +813516,7 @@ Index: gcc/config/rs6000/rs6000.c
const char *comma = "";
if (indent)
-@@ -35067,27 +36006,45 @@
+@@ -35067,27 +36054,45 @@
cur_column = start_column;
for (i = 0; i < num_elements; i++)
{
@@ -811967,7 +814179,34 @@ Index: gcc/config/rs6000/rs6000.h
===================================================================
--- a/src/gcc/config/rs6000/rs6000.h (.../tags/gcc_6_1_0_release)
+++ b/src/gcc/config/rs6000/rs6000.h (.../branches/gcc-6-branch)
-@@ -418,12 +418,12 @@
+@@ -302,6 +302,26 @@
+ #define TARGET_P8_VECTOR 0
+ #endif
+
++/* Define the ISA 3.0 flags as 0 if the target assembler does not support
++ Power9 instructions. Allow -mpower9-fusion, since it does not add new
++ instructions. Allow -misel, since it predates ISA 3.0 and does
++ not require any Power9 features. */
++
++#ifndef HAVE_AS_POWER9
++#undef TARGET_FLOAT128_HW
++#undef TARGET_MODULO
++#undef TARGET_P9_VECTOR
++#undef TARGET_P9_MINMAX
++#undef TARGET_P9_DFORM_SCALAR
++#undef TARGET_P9_DFORM_VECTOR
++#define TARGET_FLOAT128_HW 0
++#define TARGET_MODULO 0
++#define TARGET_P9_VECTOR 0
++#define TARGET_P9_MINMAX 0
++#define TARGET_P9_DFORM_SCALAR 0
++#define TARGET_P9_DFORM_VECTOR 0
++#endif
++
+ /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If
+ not, generate the lwsync code as an integer constant. */
+ #ifdef HAVE_AS_LWSYNC
+@@ -418,12 +438,12 @@
Similarly IFmode is the IBM long double format even if the default is IEEE
128-bit. */
#define FLOAT128_IEEE_P(MODE) \
@@ -811984,7 +814223,7 @@ Index: gcc/config/rs6000/rs6000.h
/* Helper macros to say whether a 128-bit floating point type can go in a
single vector register, or whether it needs paired scalar values. */
-@@ -594,6 +594,15 @@
+@@ -594,6 +614,15 @@
in the register. */
#define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP)
@@ -812000,7 +814239,7 @@ Index: gcc/config/rs6000/rs6000.h
/* In switching from using target_flags to using rs6000_isa_flags, the options
machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map
OPTION_MASK_<xxx> back into MASK_<xxx>. */
-@@ -615,6 +624,7 @@
+@@ -615,6 +644,7 @@
#define MASK_MULTIPLE OPTION_MASK_MULTIPLE
#define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE
#define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR
@@ -812008,7 +814247,7 @@ Index: gcc/config/rs6000/rs6000.h
#define MASK_POPCNTB OPTION_MASK_POPCNTB
#define MASK_POPCNTD OPTION_MASK_POPCNTD
#define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT
-@@ -655,6 +665,11 @@
+@@ -655,6 +685,11 @@
#define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE
#endif
@@ -812020,7 +814259,7 @@ Index: gcc/config/rs6000/rs6000.h
/* For power systems, we want to enable Altivec and VSX builtins even if the
user did not use -maltivec or -mvsx to allow the builtins to be used inside
of #pragma GCC target or the target attribute to change the code level for a
-@@ -1774,7 +1789,9 @@
+@@ -1774,7 +1809,9 @@
#define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
#define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \
: (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
@@ -812031,7 +814270,7 @@ Index: gcc/config/rs6000/rs6000.h
: (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
/* Flags for the call/call_value rtl operations set up by function_arg */
-@@ -2638,7 +2655,9 @@
+@@ -2638,7 +2675,9 @@
#define RS6000_BTC_MISC 0x00000000 /* No special attributes. */
#define RS6000_BTC_CONST 0x00000100 /* uses no global state. */
@@ -812042,7 +814281,7 @@ Index: gcc/config/rs6000/rs6000.h
#define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */
#define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */
-@@ -2660,6 +2679,7 @@
+@@ -2660,6 +2699,7 @@
#define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */
#define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */
#define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */
@@ -812050,11 +814289,12 @@ Index: gcc/config/rs6000/rs6000.h
#define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */
#define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */
#define RS6000_BTM_SPE MASK_STRING /* E500 */
-@@ -2673,10 +2693,12 @@
+@@ -2673,10 +2713,13 @@
#define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */
#define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */
#define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */
+#define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */
++#define RS6000_BTM_FLOAT128 MASK_P9_VECTOR /* IEEE 128-bit float. */
#define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \
| RS6000_BTM_VSX \
@@ -812063,7 +814303,13 @@ Index: gcc/config/rs6000/rs6000.h
| RS6000_BTM_CRYPTO \
| RS6000_BTM_FRE \
| RS6000_BTM_FRES \
-@@ -2691,6 +2713,7 @@
+@@ -2687,10 +2730,12 @@
+ | RS6000_BTM_CELL \
+ | RS6000_BTM_DFP \
+ | RS6000_BTM_HARD_FLOAT \
+- | RS6000_BTM_LDBL128)
++ | RS6000_BTM_LDBL128 \
++ | RS6000_BTM_FLOAT128)
/* Define builtin enum index. */
@@ -812071,7 +814317,7 @@ Index: gcc/config/rs6000/rs6000.h
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
-@@ -2703,6 +2726,7 @@
+@@ -2703,6 +2748,7 @@
#undef RS6000_BUILTIN_S
#undef RS6000_BUILTIN_X
@@ -812079,7 +814325,7 @@ Index: gcc/config/rs6000/rs6000.h
#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
-@@ -2722,6 +2746,7 @@
+@@ -2722,6 +2768,7 @@
RS6000_BUILTIN_COUNT
};
@@ -812087,6 +814333,22 @@ Index: gcc/config/rs6000/rs6000.h
#undef RS6000_BUILTIN_1
#undef RS6000_BUILTIN_2
#undef RS6000_BUILTIN_3
+@@ -2788,6 +2835,7 @@
+ RS6000_BTI_void, /* void_type_node */
+ RS6000_BTI_ieee128_float, /* ieee 128-bit floating point */
+ RS6000_BTI_ibm128_float, /* IBM 128-bit floating point */
++ RS6000_BTI_const_str, /* pointer to const char * */
+ RS6000_BTI_MAX
+ };
+
+@@ -2844,6 +2892,7 @@
+ #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
+ #define ieee128_float_type_node (rs6000_builtin_types[RS6000_BTI_ieee128_float])
+ #define ibm128_float_type_node (rs6000_builtin_types[RS6000_BTI_ibm128_float])
++#define const_str_type_node (rs6000_builtin_types[RS6000_BTI_const_str])
+
+ extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX];
+ extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
Index: gcc/config/rs6000/altivec.md
===================================================================
--- a/src/gcc/config/rs6000/altivec.md (.../tags/gcc_6_1_0_release)
@@ -812109,7 +814371,17 @@ Index: gcc/config/rs6000/altivec.md
UNSPEC_DST
UNSPEC_DSTT
UNSPEC_DSTST
-@@ -189,6 +193,13 @@
+@@ -110,6 +114,9 @@
+ UNSPEC_STVLXL
+ UNSPEC_STVRX
+ UNSPEC_STVRXL
++ UNSPEC_VSLV
++ UNSPEC_VSRV
++ UNSPEC_VADU
+ UNSPEC_VMULWHUB
+ UNSPEC_VMULWLUB
+ UNSPEC_VMULWHSB
+@@ -189,6 +196,13 @@
(KF "FLOAT128_VECTOR_P (KFmode)")
(TF "FLOAT128_VECTOR_P (TFmode)")])
@@ -812123,7 +814395,7 @@ Index: gcc/config/rs6000/altivec.md
(define_mode_attr VI_char [(V2DI "d") (V4SI "w") (V8HI "h") (V16QI "b")])
(define_mode_attr VI_scalar [(V2DI "DI") (V4SI "SI") (V8HI "HI") (V16QI "QI")])
(define_mode_attr VI_unit [(V16QI "VECTOR_UNIT_ALTIVEC_P (V16QImode)")
-@@ -203,6 +214,9 @@
+@@ -203,6 +217,9 @@
(define_mode_attr VP_small_lc [(V2DI "v4si") (V4SI "v8hi") (V8HI "v16qi")])
(define_mode_attr VU_char [(V2DI "w") (V4SI "h") (V8HI "b")])
@@ -812133,7 +814405,32 @@ Index: gcc/config/rs6000/altivec.md
;; Vector move instructions.
(define_insn "*altivec_mov<mode>"
[(set (match_operand:VM2 0 "nonimmediate_operand" "=Z,v,v,*Y,*r,*r,v,v,*r")
-@@ -1949,32 +1963,30 @@
+@@ -1617,6 +1634,24 @@
+ "vslo %0,%1,%2"
+ [(set_attr "type" "vecperm")])
+
++(define_insn "vslv"
++ [(set (match_operand:V16QI 0 "register_operand" "=v")
++ (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
++ (match_operand:V16QI 2 "register_operand" "v")]
++ UNSPEC_VSLV))]
++ "TARGET_P9_VECTOR"
++ "vslv %0,%1,%2"
++ [(set_attr "type" "vecsimple")])
++
++(define_insn "vsrv"
++ [(set (match_operand:V16QI 0 "register_operand" "=v")
++ (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
++ (match_operand:V16QI 2 "register_operand" "v")]
++ UNSPEC_VSRV))]
++ "TARGET_P9_VECTOR"
++ "vsrv %0,%1,%2"
++ [(set_attr "type" "vecsimple")])
++
+ (define_insn "*altivec_vsl<VI_char>"
+ [(set (match_operand:VI2 0 "register_operand" "=v")
+ (ashift:VI2 (match_operand:VI2 1 "register_operand" "v")
+@@ -1949,32 +1984,30 @@
;; Slightly prefer vperm, since the target does not overlap the source
(define_insn "*altivec_vperm_<mode>_internal"
@@ -812178,7 +814475,7 @@ Index: gcc/config/rs6000/altivec.md
(define_expand "altivec_vperm_<mode>_uns"
[(set (match_operand:VM 0 "register_operand" "")
-@@ -1992,18 +2004,17 @@
+@@ -1992,18 +2025,17 @@
})
(define_insn "*altivec_vperm_<mode>_uns_internal"
@@ -812203,7 +814500,7 @@ Index: gcc/config/rs6000/altivec.md
(define_expand "vec_permv16qi"
[(set (match_operand:V16QI 0 "register_operand" "")
-@@ -2032,6 +2043,19 @@
+@@ -2032,6 +2064,19 @@
FAIL;
})
@@ -812223,7 +814520,7 @@ Index: gcc/config/rs6000/altivec.md
(define_insn "altivec_vrfip" ; ceil
[(set (match_operand:V4SF 0 "register_operand" "=v")
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
-@@ -2690,20 +2714,28 @@
+@@ -2690,20 +2735,28 @@
DONE;
})
@@ -812263,7 +814560,7 @@ Index: gcc/config/rs6000/altivec.md
(define_expand "udot_prod<mode>"
[(set (match_operand:V4SI 0 "register_operand" "=v")
-@@ -2791,32 +2823,30 @@
+@@ -2791,32 +2844,30 @@
"")
(define_insn "vperm_v8hiv4si"
@@ -812308,7 +814605,7 @@ Index: gcc/config/rs6000/altivec.md
(define_expand "vec_unpacku_hi_v16qi"
-@@ -3353,7 +3383,7 @@
+@@ -3353,7 +3404,7 @@
}")
@@ -812317,10 +814614,28 @@ Index: gcc/config/rs6000/altivec.md
;; Vector count leading zeros
(define_insn "*p8v_clz<mode>2"
-@@ -3364,6 +3394,15 @@
+@@ -3364,6 +3415,33 @@
[(set_attr "length" "4")
(set_attr "type" "vecsimple")])
++;; Vector absolute difference unsigned
++(define_expand "vadu<mode>3"
++ [(set (match_operand:VI 0 "register_operand")
++ (unspec:VI [(match_operand:VI 1 "register_operand")
++ (match_operand:VI 2 "register_operand")]
++ UNSPEC_VADU))]
++ "TARGET_P9_VECTOR")
++
++;; Vector absolute difference unsigned
++(define_insn "*p9_vadu<mode>3"
++ [(set (match_operand:VI 0 "register_operand" "=v")
++ (unspec:VI [(match_operand:VI 1 "register_operand" "v")
++ (match_operand:VI 2 "register_operand" "v")]
++ UNSPEC_VADU))]
++ "TARGET_P9_VECTOR"
++ "vabsdu<wd> %0,%1,%2"
++ [(set_attr "type" "vecsimple")])
++
+;; Vector count trailing zeros
+(define_insn "*p9v_ctz<mode>2"
+ [(set (match_operand:VI2 0 "register_operand" "=v")
@@ -812333,7 +814648,7 @@ Index: gcc/config/rs6000/altivec.md
;; Vector population count
(define_insn "*p8v_popcount<mode>2"
[(set (match_operand:VI2 0 "register_operand" "=v")
-@@ -3373,6 +3412,15 @@
+@@ -3373,6 +3451,15 @@
[(set_attr "length" "4")
(set_attr "type" "vecsimple")])
@@ -812349,7 +814664,7 @@ Index: gcc/config/rs6000/altivec.md
;; Vector Gather Bits by Bytes by Doubleword
(define_insn "p8v_vgbbd"
[(set (match_operand:V16QI 0 "register_operand" "=v")
-@@ -3540,6 +3588,27 @@
+@@ -3540,6 +3627,27 @@
[(set_attr "length" "4")
(set_attr "type" "vecsimple")])
@@ -812419,6 +814734,15 @@ Index: gcc/config/rs6000/rs6000.md
;; Start with fixed-point load and store insns. Here we put only the more
;; complex forms. Basic data transfer is done later.
+@@ -4044,7 +4059,7 @@
+
+ if (REGNO (cr) == CR0_REGNO)
+ {
+- emit_insn (gen_ashdi3_extswsli_dot (dest, src2, shift, cr));
++ emit_insn (gen_ashdi3_extswsli_dot2 (dest, src2, shift, cr));
+ DONE;
+ }
+
@@ -4599,74 +4614,45 @@
;; On VSX, we only check for TARGET_VSX instead of checking for a vsx/p8 vector
;; to allow either DF/SF to use only traditional registers.
@@ -812685,6 +815009,52 @@ Index: gcc/config/rs6000/rs6000.md
""
"blr"
[(set_attr "type" "jmpreg")])
+@@ -13242,7 +13225,25 @@
+ "xssqrtqp %0,%1"
+ [(set_attr "type" "vecdiv")])
+
+-(define_insn "copysign<mode>3"
++(define_expand "copysign<mode>3"
++ [(use (match_operand:IEEE128 0 "altivec_register_operand"))
++ (use (match_operand:IEEE128 1 "altivec_register_operand"))
++ (use (match_operand:IEEE128 2 "altivec_register_operand"))]
++ "FLOAT128_IEEE_P (<MODE>mode)"
++{
++ if (TARGET_FLOAT128_HW)
++ emit_insn (gen_copysign<mode>3_hard (operands[0], operands[1],
++ operands[2]));
++ else
++ {
++ rtx tmp = gen_reg_rtx (<MODE>mode);
++ emit_insn (gen_copysign<mode>3_soft (operands[0], operands[1],
++ operands[2], tmp));
++ }
++ DONE;
++})
++
++(define_insn "copysign<mode>3_hard"
+ [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
+ (unspec:IEEE128
+ [(match_operand:IEEE128 1 "altivec_register_operand" "v")
+@@ -13252,6 +13253,18 @@
+ "xscpsgnqp %0,%2,%1"
+ [(set_attr "type" "vecsimple")])
+
++(define_insn "copysign<mode>3_soft"
++ [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
++ (unspec:IEEE128
++ [(match_operand:IEEE128 1 "altivec_register_operand" "v")
++ (match_operand:IEEE128 2 "altivec_register_operand" "v")
++ (match_operand:IEEE128 3 "altivec_register_operand" "+v")]
++ UNSPEC_COPYSIGN))]
++ "!TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
++ "xscpsgndp %x3,%x2,%x1\;xxpermdi %x0,%x3,%x1,1"
++ [(set_attr "type" "veccomplex")
++ (set_attr "length" "8")])
++
+ (define_insn "neg<mode>2_hw"
+ [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
+ (neg:IEEE128
Index: gcc/config/rs6000/altivec.h
===================================================================
--- a/src/gcc/config/rs6000/altivec.h (.../tags/gcc_6_1_0_release)
@@ -812700,7 +815070,7 @@ Index: gcc/config/rs6000/altivec.h
/* Note, xxsldi and xxpermdi were added as __builtin_vsx_<xxx> functions
instead of __builtin_vec_<xxx> */
-@@ -384,6 +384,23 @@
+@@ -384,6 +384,31 @@
#define vec_vupklsw __builtin_vec_vupklsw
#endif
@@ -812719,6 +815089,14 @@ Index: gcc/config/rs6000/altivec.h
+#ifdef _ARCH_PPC64
+#define vec_vprtybq __builtin_vec_vprtybq
+#endif
++
++#define vec_slv __builtin_vec_vslv
++#define vec_srv __builtin_vec_vsrv
++
++#define vec_absd __builtin_vec_vadu
++#define vec_absdb __builtin_vec_vadub
++#define vec_absdh __builtin_vec_vaduh
++#define vec_absdw __builtin_vec_vaduw
+#endif
+
/* Predicates.
@@ -812804,6 +815182,15 @@ Index: gcc/config/arm/arm.c
===================================================================
--- a/src/gcc/config/arm/arm.c (.../tags/gcc_6_1_0_release)
+++ b/src/gcc/config/arm/arm.c (.../branches/gcc-6-branch)
+@@ -6704,7 +6704,7 @@
+
+ /* The PIC register is live on entry to VxWorks PLT entries, so we
+ must make the call before restoring the PIC register. */
+- if (TARGET_VXWORKS_RTP && flag_pic && !targetm.binds_local_p (decl))
++ if (TARGET_VXWORKS_RTP && flag_pic && decl && !targetm.binds_local_p (decl))
+ return false;
+
+ /* If we are interworking and the function is not declared static
@@ -17755,6 +17755,7 @@
int num_saves = XVECLEN (operands[0], 0);
unsigned int regno;
--
Alioth's /usr/local/bin/git-commit-notice on /srv/git.debian.org/git/reproducible/gcc-6.git
More information about the Reproducible-commits
mailing list