[gcc-6] 230/401: - regenerate linaro diff with git --no-renames
Ximin Luo
infinity0 at debian.org
Wed Apr 5 15:49:43 UTC 2017
This is an automated email from the git hooks/post-receive script.
infinity0 pushed a commit to branch pu/reproducible_builds
in repository gcc-6.
commit 92d613379fc60cc799545034cc997d5a4a4e3ff0
Author: doko <doko at 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca>
Date: Tue Oct 18 08:32:07 2016 +0000
- regenerate linaro diff with git --no-renames
git-svn-id: svn://anonscm.debian.org/gcccvs/branches/sid/gcc-6@9002 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca
---
debian/patches/gcc-linaro.diff | 718 ++++++++++++++++++++++++++++++++++++++++-
1 file changed, 717 insertions(+), 1 deletion(-)
diff --git a/debian/patches/gcc-linaro.diff b/debian/patches/gcc-linaro.diff
index 01cae87..5c892c0 100644
--- a/debian/patches/gcc-linaro.diff
+++ b/debian/patches/gcc-linaro.diff
@@ -2,7 +2,7 @@
MSG=$(git log origin/linaro/gcc-6-branch --format=format:"%s" -n 1 --grep "Merge branches"); SVN=${MSG##* }; git log origin/gcc-6-branch --format=format:"%H" -n 1 --grep "gcc-6-branch@${SVN%.}"
-LANG=C git diff 70232cbbcab57eecc73626f3ea0e13bdfa00202d..bc32472ee917a01b63e72dc399c81d26259e78aa \
+LANG=C git diff --no-renames 70232cbbcab57eecc73626f3ea0e13bdfa00202d..bc32472ee917a01b63e72dc399c81d26259e78aa \
| egrep -v '^(diff|index) ' \
| filterdiff --strip=1 --addoldprefix=a/src/ --addnewprefix=b/src/ \
| sed 's,a/src//dev/null,/dev/null,'
@@ -80490,6 +80490,19 @@ LANG=C git diff 70232cbbcab57eecc73626f3ea0e13bdfa00202d..bc32472ee917a01b63e72d
+/* { dg-final { scan-assembler-times {vnmls\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } } */
+
--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire-1.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2 -fno-ipa-icf" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-comp-swap-release-acquire.x"
++
++/* { dg-final { scan-assembler-times "ldaex" 4 } } */
++/* { dg-final { scan-assembler-times "stlex" 4 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
@@ -80502,6 +80515,32 @@ LANG=C git diff 70232cbbcab57eecc73626f3ea0e13bdfa00202d..bc32472ee917a01b63e72d
+/* { dg-final { scan-assembler-times "ldaex" 4 } } */
+/* { dg-final { scan-assembler-times "stlex" 4 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c
++++ b/src//dev/null
+@@ -1,10 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2 -fno-ipa-icf" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-comp-swap-release-acquire.x"
+-
+-/* { dg-final { scan-assembler-times "ldaex" 4 } } */
+-/* { dg-final { scan-assembler-times "stlex" 4 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel-1.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-op-acq_rel.x"
++
++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel-2.c
@@ -0,0 +1,10 @@
@@ -80515,6 +80554,32 @@ LANG=C git diff 70232cbbcab57eecc73626f3ea0e13bdfa00202d..bc32472ee917a01b63e72d
+/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c
++++ b/src//dev/null
+@@ -1,10 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-op-acq_rel.x"
+-
+-/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-acquire-1.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-op-acquire.x"
++
++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-acquire-2.c
@@ -0,0 +1,10 @@
@@ -80528,6 +80593,32 @@ LANG=C git diff 70232cbbcab57eecc73626f3ea0e13bdfa00202d..bc32472ee917a01b63e72d
+/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-acquire.c
++++ b/src//dev/null
+@@ -1,10 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-op-acquire.x"
+-
+-/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-char-1.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-op-char.x"
++
++/* { dg-final { scan-assembler-times "ldrexb\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strexb\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-char-2.c
@@ -0,0 +1,10 @@
@@ -80541,6 +80632,33 @@ LANG=C git diff 70232cbbcab57eecc73626f3ea0e13bdfa00202d..bc32472ee917a01b63e72d
+/* { dg-final { scan-assembler-times "ldrexb\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "strexb\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-char.c
++++ b/src//dev/null
+@@ -1,10 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-op-char.x"
+-
+-/* { dg-final { scan-assembler-times "ldrexb\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-times "strexb\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-consume-1.c
+@@ -0,0 +1,11 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-op-consume.x"
++
++/* Scan for ldaex is a PR59448 consume workaround. */
++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-consume-2.c
@@ -0,0 +1,11 @@
@@ -80555,6 +80673,33 @@ LANG=C git diff 70232cbbcab57eecc73626f3ea0e13bdfa00202d..bc32472ee917a01b63e72d
+/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-consume.c
++++ b/src//dev/null
+@@ -1,11 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-op-consume.x"
+-
+-/* Scan for ldaex is a PR59448 consume workaround. */
+-/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-int-1.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-op-int.x"
++
++/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-int-2.c
@@ -0,0 +1,10 @@
@@ -80568,6 +80713,32 @@ LANG=C git diff 70232cbbcab57eecc73626f3ea0e13bdfa00202d..bc32472ee917a01b63e72d
+/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-int.c
++++ b/src//dev/null
+@@ -1,10 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-op-int.x"
+-
+-/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-relaxed-1.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-op-relaxed.x"
++
++/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-relaxed-2.c
@@ -0,0 +1,10 @@
@@ -80581,6 +80752,32 @@ LANG=C git diff 70232cbbcab57eecc73626f3ea0e13bdfa00202d..bc32472ee917a01b63e72d
+/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c
++++ b/src//dev/null
+@@ -1,10 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-op-relaxed.x"
+-
+-/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-release-1.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-op-release.x"
++
++/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-release-2.c
@@ -0,0 +1,10 @@
@@ -80594,6 +80791,32 @@ LANG=C git diff 70232cbbcab57eecc73626f3ea0e13bdfa00202d..bc32472ee917a01b63e72d
+/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-release.c
++++ b/src//dev/null
+@@ -1,10 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-op-release.x"
+-
+-/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst-1.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-op-seq_cst.x"
++
++/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst-2.c
@@ -0,0 +1,10 @@
@@ -80607,6 +80830,32 @@ LANG=C git diff 70232cbbcab57eecc73626f3ea0e13bdfa00202d..bc32472ee917a01b63e72d
+/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c
++++ b/src//dev/null
+@@ -1,10 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-op-seq_cst.x"
+-
+-/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-short-1.c
+@@ -0,0 +1,10 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_arch_v8a_ok } */
++/* { dg-options "-O2" } */
++/* { dg-add-options arm_arch_v8a } */
++
++#include "../aarch64/atomic-op-short.x"
++
++/* { dg-final { scan-assembler-times "ldrexh\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-times "strexh\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
++/* { dg-final { scan-assembler-not "dmb" } } */
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/atomic-op-short-2.c
@@ -0,0 +1,10 @@
@@ -80620,6 +80869,19 @@ LANG=C git diff 70232cbbcab57eecc73626f3ea0e13bdfa00202d..bc32472ee917a01b63e72d
+/* { dg-final { scan-assembler-times "ldrexh\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "strexh\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/atomic-op-short.c
++++ b/src//dev/null
+@@ -1,10 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_arch_v8a_ok } */
+-/* { dg-options "-O2" } */
+-/* { dg-add-options arm_arch_v8a } */
+-
+-#include "../aarch64/atomic-op-short.x"
+-
+-/* { dg-final { scan-assembler-times "ldrexh\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-times "strexh\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+-/* { dg-final { scan-assembler-not "dmb" } } */
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/attr-fp16-arith-1.c
@@ -0,0 +1,58 @@
@@ -81296,6 +81558,143 @@ LANG=C git diff 70232cbbcab57eecc73626f3ea0e13bdfa00202d..bc32472ee917a01b63e72d
-
-# All done.
-dg-finish
+--- a/src/gcc/testsuite/gcc.target/arm/neon/polytypes.c
++++ b/src//dev/null
+@@ -1,48 +0,0 @@
+-/* Check that NEON polynomial vector types are suitably incompatible with
+- integer vector types of the same layout. */
+-
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-add-options arm_neon } */
+-
+-#include <arm_neon.h>
+-
+-void s64_8 (int8x8_t a) {}
+-void u64_8 (uint8x8_t a) {}
+-void p64_8 (poly8x8_t a) {}
+-void s64_16 (int16x4_t a) {}
+-void u64_16 (uint16x4_t a) {}
+-void p64_16 (poly16x4_t a) {}
+-
+-void s128_8 (int8x16_t a) {}
+-void u128_8 (uint8x16_t a) {}
+-void p128_8 (poly8x16_t a) {}
+-void s128_16 (int16x8_t a) {}
+-void u128_16 (uint16x8_t a) {}
+-void p128_16 (poly16x8_t a) {}
+-
+-void foo ()
+-{
+- poly8x8_t v64_8;
+- poly16x4_t v64_16;
+- poly8x16_t v128_8;
+- poly16x8_t v128_16;
+-
+- s64_8 (v64_8); /* { dg-message "use -flax-vector-conversions" } */
+- /* { dg-error "incompatible type for argument 1 of 's64_8'" "" { target *-*-* } 31 } */
+- u64_8 (v64_8); /* { dg-error "incompatible type for argument 1 of 'u64_8'" } */
+- p64_8 (v64_8);
+-
+- s64_16 (v64_16); /* { dg-error "incompatible type for argument 1 of 's64_16'" } */
+- u64_16 (v64_16); /* { dg-error "incompatible type for argument 1 of 'u64_16'" } */
+- p64_16 (v64_16);
+-
+- s128_8 (v128_8); /* { dg-error "incompatible type for argument 1 of 's128_8'" } */
+- u128_8 (v128_8); /* { dg-error "incompatible type for argument 1 of 'u128_8'" } */
+- p128_8 (v128_8);
+-
+- s128_16 (v128_16); /* { dg-error "incompatible type for argument 1 of 's128_16'" } */
+- u128_16 (v128_16); /* { dg-error "incompatible type for argument 1 of 'u128_16'" } */
+- p128_16 (v128_16);
+-}
+-/* { dg-message "note: expected '\[^'\n\]*' but argument is of type '\[^'\n\]*'" "note: expected" { target *-*-* } 0 } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/pr51534.c
++++ b/src//dev/null
+@@ -1,83 +0,0 @@
+-/* Test the vector comparison intrinsics when comparing to immediate zero.
+- */
+-
+-/* { dg-do assemble } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps -mfloat-abi=hard -O3" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include <arm_neon.h>
+-
+-#define GEN_TEST(T, D, C, R) \
+- R test_##C##_##T (T a) { return C (a, D (0)); }
+-
+-#define GEN_DOUBLE_TESTS(S, T, C) \
+- GEN_TEST (T, vdup_n_s##S, C##_s##S, u##T) \
+- GEN_TEST (u##T, vdup_n_u##S, C##_u##S, u##T)
+-
+-#define GEN_QUAD_TESTS(S, T, C) \
+- GEN_TEST (T, vdupq_n_s##S, C##q_s##S, u##T) \
+- GEN_TEST (u##T, vdupq_n_u##S, C##q_u##S, u##T)
+-
+-#define GEN_COND_TESTS(C) \
+- GEN_DOUBLE_TESTS (8, int8x8_t, C) \
+- GEN_DOUBLE_TESTS (16, int16x4_t, C) \
+- GEN_DOUBLE_TESTS (32, int32x2_t, C) \
+- GEN_QUAD_TESTS (8, int8x16_t, C) \
+- GEN_QUAD_TESTS (16, int16x8_t, C) \
+- GEN_QUAD_TESTS (32, int32x4_t, C)
+-
+-GEN_COND_TESTS(vcgt)
+-GEN_COND_TESTS(vcge)
+-GEN_COND_TESTS(vclt)
+-GEN_COND_TESTS(vcle)
+-GEN_COND_TESTS(vceq)
+-
+-/* Scan for expected outputs. */
+-/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcgt\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcgt\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcgt\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcgt\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcgt\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcgt\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcge\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcge\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcge\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcge\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcge\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vcge\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
+-/* { dg-final { scan-assembler "vclt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vclt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vclt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vclt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vclt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vclt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vcle\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vcle\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vcle\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vcle\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vcle\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler "vcle\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
+-/* { dg-final { scan-assembler-times "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */
+-/* { dg-final { scan-assembler-times "vceq\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */
+-/* { dg-final { scan-assembler-times "vceq\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */
+-/* { dg-final { scan-assembler-times "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */
+-/* { dg-final { scan-assembler-times "vceq\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */
+-/* { dg-final { scan-assembler-times "vceq\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */
+-
+-/* And ensure we don't have unexpected output too. */
+-/* { dg-final { scan-assembler-not "vc\[gl\]\[te\]\.u\[0-9\]+\[ \]+\[qQdD\]\[0-9\]+, \[qQdD\]\[0-9\]+, #0" } } */
+-
+-/* Tidy up. */
--- a/src/gcc/testsuite/gcc.target/arm/neon/vRaddhns16.c
+++ b/src//dev/null
@@ -1,20 +0,0 @@
@@ -90594,6 +90993,66 @@ LANG=C git diff 70232cbbcab57eecc73626f3ea0e13bdfa00202d..bc32472ee917a01b63e72d
-}
-
-/* { dg-final { scan-assembler "vdup\.8\[ \]+\[dD\]\[0-9\]+, (\[rR\]\[0-9\]+|\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vect-vcvt.c
++++ b/src//dev/null
+@@ -1,27 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details -mvectorize-with-neon-double" } */
+-/* { dg-add-options arm_neon } */
+-
+-#define N 32
+-
+-int ib[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45};
+-float fa[N];
+-int ia[N];
+-
+-int convert()
+-{
+- int i;
+-
+- /* int -> float */
+- for (i = 0; i < N; i++)
+- fa[i] = (float) ib[i];
+-
+- /* float -> int */
+- for (i = 0; i < N; i++)
+- ia[i] = (int) fa[i];
+-
+- return 0;
+-}
+-
+-/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vect-vcvtq.c
++++ b/src//dev/null
+@@ -1,27 +0,0 @@
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details" } */
+-/* { dg-add-options arm_neon } */
+-
+-#define N 32
+-
+-int ib[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45};
+-float fa[N];
+-int ia[N];
+-
+-int convert()
+-{
+- int i;
+-
+- /* int -> float */
+- for (i = 0; i < N; i++)
+- fa[i] = (float) ib[i];
+-
+- /* float -> int */
+- for (i = 0; i < N; i++)
+- ia[i] = (int) fa[i];
+-
+- return 0;
+-}
+-
+-/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */
--- a/src/gcc/testsuite/gcc.target/arm/neon/veorQs16.c
+++ b/src//dev/null
@@ -1,20 +0,0 @@
@@ -91608,6 +92067,36 @@ LANG=C git diff 70232cbbcab57eecc73626f3ea0e13bdfa00202d..bc32472ee917a01b63e72d
-}
-
-/* { dg-final { scan-assembler "vfms\.f32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- a/src/gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c
++++ b/src//dev/null
+@@ -1,27 +0,0 @@
+-/* Check that NEON vector shifts support immediate values == size. /*
+-
+-/* { dg-do compile } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-save-temps" } */
+-/* { dg-add-options arm_neon } */
+-
+-#include <arm_neon.h>
+-
+-uint16x8_t test_vshll_n_u8 (uint8x8_t a)
+-{
+- return vshll_n_u8(a, 8);
+-}
+-
+-uint32x4_t test_vshll_n_u16 (uint16x4_t a)
+-{
+- return vshll_n_u16(a, 16);
+-}
+-
+-uint64x2_t test_vshll_n_u32 (uint32x2_t a)
+-{
+- return vshll_n_u32(a, 32);
+-}
+-
+-/* { dg-final { scan-assembler "vshll\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vshll\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+-/* { dg-final { scan-assembler "vshll\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
--- a/src/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c
+++ b/src//dev/null
@@ -1,19 +0,0 @@
@@ -125717,6 +126206,57 @@ LANG=C git diff 70232cbbcab57eecc73626f3ea0e13bdfa00202d..bc32472ee917a01b63e72d
-
-/* { dg-final { scan-assembler "vzip\.8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/polytypes.c
+@@ -0,0 +1,48 @@
++/* Check that NEON polynomial vector types are suitably incompatible with
++ integer vector types of the same layout. */
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++void s64_8 (int8x8_t a) {}
++void u64_8 (uint8x8_t a) {}
++void p64_8 (poly8x8_t a) {}
++void s64_16 (int16x4_t a) {}
++void u64_16 (uint16x4_t a) {}
++void p64_16 (poly16x4_t a) {}
++
++void s128_8 (int8x16_t a) {}
++void u128_8 (uint8x16_t a) {}
++void p128_8 (poly8x16_t a) {}
++void s128_16 (int16x8_t a) {}
++void u128_16 (uint16x8_t a) {}
++void p128_16 (poly16x8_t a) {}
++
++void foo ()
++{
++ poly8x8_t v64_8;
++ poly16x4_t v64_16;
++ poly8x16_t v128_8;
++ poly16x8_t v128_16;
++
++ s64_8 (v64_8); /* { dg-message "use -flax-vector-conversions" } */
++ /* { dg-error "incompatible type for argument 1 of 's64_8'" "" { target *-*-* } 31 } */
++ u64_8 (v64_8); /* { dg-error "incompatible type for argument 1 of 'u64_8'" } */
++ p64_8 (v64_8);
++
++ s64_16 (v64_16); /* { dg-error "incompatible type for argument 1 of 's64_16'" } */
++ u64_16 (v64_16); /* { dg-error "incompatible type for argument 1 of 'u64_16'" } */
++ p64_16 (v64_16);
++
++ s128_8 (v128_8); /* { dg-error "incompatible type for argument 1 of 's128_8'" } */
++ u128_8 (v128_8); /* { dg-error "incompatible type for argument 1 of 'u128_8'" } */
++ p128_8 (v128_8);
++
++ s128_16 (v128_16); /* { dg-error "incompatible type for argument 1 of 's128_16'" } */
++ u128_16 (v128_16); /* { dg-error "incompatible type for argument 1 of 'u128_16'" } */
++ p128_16 (v128_16);
++}
++/* { dg-message "note: expected '\[^'\n\]*' but argument is of type '\[^'\n\]*'" "note: expected" { target *-*-* } 0 } */
+--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/pr37780_1.c
@@ -0,0 +1,48 @@
+/* Test that we can remove the conditional move due to CLZ
@@ -125777,6 +126317,92 @@ LANG=C git diff 70232cbbcab57eecc73626f3ea0e13bdfa00202d..bc32472ee917a01b63e72d
/* Make sure the address of glob.c is calculated only once and using
a logical shift for the offset (200<<1). */
--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/pr51534.c
+@@ -0,0 +1,83 @@
++/* Test the vector comparison intrinsics when comparing to immediate zero.
++ */
++
++/* { dg-do assemble } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-save-temps -mfloat-abi=hard -O3" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++#define GEN_TEST(T, D, C, R) \
++ R test_##C##_##T (T a) { return C (a, D (0)); }
++
++#define GEN_DOUBLE_TESTS(S, T, C) \
++ GEN_TEST (T, vdup_n_s##S, C##_s##S, u##T) \
++ GEN_TEST (u##T, vdup_n_u##S, C##_u##S, u##T)
++
++#define GEN_QUAD_TESTS(S, T, C) \
++ GEN_TEST (T, vdupq_n_s##S, C##q_s##S, u##T) \
++ GEN_TEST (u##T, vdupq_n_u##S, C##q_u##S, u##T)
++
++#define GEN_COND_TESTS(C) \
++ GEN_DOUBLE_TESTS (8, int8x8_t, C) \
++ GEN_DOUBLE_TESTS (16, int16x4_t, C) \
++ GEN_DOUBLE_TESTS (32, int32x2_t, C) \
++ GEN_QUAD_TESTS (8, int8x16_t, C) \
++ GEN_QUAD_TESTS (16, int16x8_t, C) \
++ GEN_QUAD_TESTS (32, int32x4_t, C)
++
++GEN_COND_TESTS(vcgt)
++GEN_COND_TESTS(vcge)
++GEN_COND_TESTS(vclt)
++GEN_COND_TESTS(vcle)
++GEN_COND_TESTS(vceq)
++
++/* Scan for expected outputs. */
++/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcgt\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcgt\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcgt\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcgt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcgt\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcgt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcgt\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcgt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcgt\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcge\.u8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcge\.u16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcge\.u32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcge\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcge\.u8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcge\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcge\.u16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vcge\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vcge\.u32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+" 2 } } */
++/* { dg-final { scan-assembler "vclt\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vclt\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vclt\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vclt\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vclt\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vclt\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vcle\.s8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vcle\.s16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vcle\.s32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vcle\.s8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vcle\.s16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler "vcle\.s32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" } } */
++/* { dg-final { scan-assembler-times "vceq\.i8\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */
++/* { dg-final { scan-assembler-times "vceq\.i16\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */
++/* { dg-final { scan-assembler-times "vceq\.i32\[ \]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, #0" 2 } } */
++/* { dg-final { scan-assembler-times "vceq\.i8\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */
++/* { dg-final { scan-assembler-times "vceq\.i16\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */
++/* { dg-final { scan-assembler-times "vceq\.i32\[ \]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, #0" 2 } } */
++
++/* And ensure we don't have unexpected output too. */
++/* { dg-final { scan-assembler-not "vc\[gl\]\[te\]\.u\[0-9\]+\[ \]+\[qQdD\]\[0-9\]+, \[qQdD\]\[0-9\]+, #0" } } */
++
++/* Tidy up. */
+--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/short-vfp-1.c
@@ -0,0 +1,45 @@
+/* { dg-do compile } */
@@ -125825,6 +126451,96 @@ LANG=C git diff 70232cbbcab57eecc73626f3ea0e13bdfa00202d..bc32472ee917a01b63e72d
+/* {dg-final { scan-assembler-times {vmov\ts[0-9]+,r[0-9]+} 2 }} */
+/* {dg-final { scan-assembler-times {sxth\tr[0-9]+,r[0-9]+} 2 }} */
--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/vect-vcvt.c
+@@ -0,0 +1,27 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details -mvectorize-with-neon-double" } */
++/* { dg-add-options arm_neon } */
++
++#define N 32
++
++int ib[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45};
++float fa[N];
++int ia[N];
++
++int convert()
++{
++ int i;
++
++ /* int -> float */
++ for (i = 0; i < N; i++)
++ fa[i] = (float) ib[i];
++
++ /* float -> int */
++ for (i = 0; i < N; i++)
++ ia[i] = (int) fa[i];
++
++ return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/vect-vcvtq.c
+@@ -0,0 +1,27 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details" } */
++/* { dg-add-options arm_neon } */
++
++#define N 32
++
++int ib[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45};
++float fa[N];
++int ia[N];
++
++int convert()
++{
++ int i;
++
++ /* int -> float */
++ for (i = 0; i < N; i++)
++ fa[i] = (float) ib[i];
++
++ /* float -> int */
++ for (i = 0; i < N; i++)
++ ia[i] = (int) fa[i];
++
++ return 0;
++}
++
++/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/arm/vfp-shift-a2t2.c
+@@ -0,0 +1,27 @@
++/* Check that NEON vector shifts support immediate values == size. /*
++
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-save-temps" } */
++/* { dg-add-options arm_neon } */
++
++#include <arm_neon.h>
++
++uint16x8_t test_vshll_n_u8 (uint8x8_t a)
++{
++ return vshll_n_u8(a, 8);
++}
++
++uint32x4_t test_vshll_n_u16 (uint16x4_t a)
++{
++ return vshll_n_u16(a, 16);
++}
++
++uint64x2_t test_vshll_n_u32 (uint32x2_t a)
++{
++ return vshll_n_u32(a, 32);
++}
++
++/* { dg-final { scan-assembler "vshll\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshll\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
++/* { dg-final { scan-assembler "vshll\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/vst1Q_laneu64-1.c
@@ -0,0 +1,25 @@
+/* Test the `vst1Q_laneu64' ARM Neon intrinsic. */
--
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