[gcc-6] 352/401: * Update to SVN 20170121 (r244748) from the gcc-6-branch.

Ximin Luo infinity0 at debian.org
Wed Apr 5 15:50:37 UTC 2017


This is an automated email from the git hooks/post-receive script.

infinity0 pushed a commit to branch pu/reproducible_builds
in repository gcc-6.

commit c968bb93f8cf907c7ceeded102ca36da43646542
Author: doko <doko at 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca>
Date:   Sat Jan 21 17:39:17 2017 +0000

      * Update to SVN 20170121 (r244748) from the gcc-6-branch.
    
    
    git-svn-id: svn://anonscm.debian.org/gcccvs/branches/sid/gcc-6@9237 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca
---
 debian/changelog                              |   7 +-
 debian/patches/gcc-linaro-r244724-revert.diff | 246 ++++++++
 debian/patches/svn-updates.diff               | 772 +++++++++++++++++++++++++-
 debian/rules.patch                            |   1 +
 4 files changed, 1015 insertions(+), 11 deletions(-)

diff --git a/debian/changelog b/debian/changelog
index fb3600b..874c9d0 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,11 +1,14 @@
 gcc-6 (6.3.0-4) UNRELEASED; urgency=medium
 
+  * Update to SVN 20170121 (r244748) from the gcc-6-branch.
+    - Fix PR target/77455 (AArch64), PR rtl-optimization/79121, PR ipa/79043,
+      PR ipa/71207, PR tree-optimization/72488, PR c++/77545, PR c++/77284.
   * Fix gdc cross build.
-  * Better fix symlinks to unprefixed man pages. Closes: #851886.
+  * Fix symlinks to unprefixed man pages. Closes: #851886.
   * Fix PR go/79037, proposed golang patch (John Paul Adrian Glaubitz).
     Closes: #852091.
 
- -- Matthias Klose <doko at debian.org>  Thu, 19 Jan 2017 13:40:26 +0100
+ -- Matthias Klose <doko at debian.org>  Sat, 21 Jan 2017 18:23:21 +0100
 
 gcc-6 (6.3.0-3) unstable; urgency=medium
 
diff --git a/debian/patches/gcc-linaro-r244724-revert.diff b/debian/patches/gcc-linaro-r244724-revert.diff
new file mode 100644
index 0000000..af336e9
--- /dev/null
+++ b/debian/patches/gcc-linaro-r244724-revert.diff
@@ -0,0 +1,246 @@
+# DP: Revert PR PR target/77455, already in the Linaro branch
+
+--- a/src/gcc/testsuite/gcc.target/aarch64/eh_return.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/eh_return.c
+@@ -1,82 +0,0 @@
+-/* { dg-do run } */
+-/* { dg-options "-O2 -fno-inline" } */
+-
+-#include <stdlib.h>
+-#include <stdio.h>
+-
+-int val, test, failed;
+-
+-int main (void);
+-
+-void
+-eh0 (void *p)
+-{
+-  val = (int)(long)p & 7;
+-  if (val)
+-    abort ();
+-}
+-
+-void
+-eh1 (void *p, int x)
+-{
+-  void *q = __builtin_alloca (x);
+-  eh0 (q);
+-  __builtin_eh_return (0, p);
+-}
+-
+-void
+-eh2a (int a,int b,int c,int d,int e,int f,int g,int h, void *p)
+-{
+-  val = a + b + c + d + e + f + g + h +  (int)(long)p & 7;
+-}
+-
+-void
+-eh2 (void *p)
+-{
+-  eh2a (val, val, val, val, val, val, val, val, p);
+-  __builtin_eh_return (0, p);
+-}
+-
+-
+-void
+-continuation (void)
+-{
+-  test++;
+-  main ();
+-}
+-
+-void
+-fail (void)
+-{
+-  failed = 1;
+-  printf ("failed\n");
+-  continuation ();
+-}
+-
+-void
+-do_test1 (void)
+-{
+-  if (!val)
+-    eh1 (continuation, 100);
+-  fail ();
+-}
+-
+-void
+-do_test2 (void)
+-{
+-  if (!val)
+-    eh2 (continuation);
+-  fail ();
+-}
+-
+-int
+-main (void)
+-{
+-  if (test == 0)
+-    do_test1 ();
+-  if (test == 1)
+-    do_test2 ();
+-  if (failed || test != 2)
+-    exit (1);
+-  exit (0);
+-}
+--- a/src/gcc/config/aarch64/aarch64.md
++++ b/src/gcc/config/aarch64/aarch64.md
+@@ -587,6 +587,25 @@
+   [(set_attr "type" "branch")]
+ )
+ 
++(define_insn "eh_return"
++  [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
++    UNSPECV_EH_RETURN)]
++  ""
++  "#"
++  [(set_attr "type" "branch")]
++
++)
++
++(define_split
++  [(unspec_volatile [(match_operand:DI 0 "register_operand" "")]
++    UNSPECV_EH_RETURN)]
++  "reload_completed"
++  [(set (match_dup 1) (match_dup 0))]
++  {
++    operands[1] = aarch64_final_eh_return_addr ();
++  }
++)
++
+ (define_insn "*cb<optab><mode>1"
+   [(set (pc) (if_then_else (EQL (match_operand:GPI 0 "register_operand" "r")
+ 				(const_int 0))
+--- a/src/gcc/config/aarch64/aarch64-protos.h
++++ b/src/gcc/config/aarch64/aarch64-protos.h
+@@ -338,7 +338,7 @@
+ int aarch64_simd_attr_length_move (rtx_insn *);
+ int aarch64_uxt_size (int, HOST_WIDE_INT);
+ int aarch64_vec_fpconst_pow_of_2 (rtx);
+-rtx aarch64_eh_return_handler_rtx (void);
++rtx aarch64_final_eh_return_addr (void);
+ rtx aarch64_legitimize_reload_address (rtx *, machine_mode, int, int, int);
+ rtx aarch64_mask_from_zextract_ops (rtx, rtx);
+ const char *aarch64_output_move_struct (rtx *operands);
+--- a/src/gcc/config/aarch64/aarch64.c
++++ b/src/gcc/config/aarch64/aarch64.c
+@@ -2480,10 +2480,6 @@
+       && (!crtl->is_leaf || df_regs_ever_live_p (LR_REGNUM)))
+     return true;
+ 
+-  /* Force a frame pointer for EH returns so the return address is at FP+8.  */
+-  if (crtl->calls_eh_return)
+-    return true;
+-
+   return false;
+ }
+ 
+@@ -3040,8 +3036,7 @@
+   rtx_insn *insn;
+   /* We need to add memory barrier to prevent read from deallocated stack.  */
+   bool need_barrier_p = (get_frame_size () != 0
+-			 || cfun->machine->frame.saved_varargs_size
+-			 || crtl->calls_eh_return);
++			 || cfun->machine->frame.saved_varargs_size);
+ 
+   aarch64_layout_frame ();
+ 
+@@ -3194,40 +3189,52 @@
+     emit_jump_insn (ret_rtx);
+ }
+ 
+-/* Implement EH_RETURN_HANDLER_RTX.  EH returns need to either return
+-   normally or return to a previous frame after unwinding.
++/* Return the place to copy the exception unwinding return address to.
++   This will probably be a stack slot, but could (in theory be the
++   return register).  */
++rtx
++aarch64_final_eh_return_addr (void)
++{
++  HOST_WIDE_INT fp_offset;
+ 
+-   An EH return uses a single shared return sequence.  The epilogue is
+-   exactly like a normal epilogue except that it has an extra input
+-   register (EH_RETURN_STACKADJ_RTX) which contains the stack adjustment
+-   that must be applied after the frame has been destroyed.  An extra label
+-   is inserted before the epilogue which initializes this register to zero,
+-   and this is the entry point for a normal return.
++  aarch64_layout_frame ();
+ 
+-   An actual EH return updates the return address, initializes the stack
+-   adjustment and jumps directly into the epilogue (bypassing the zeroing
+-   of the adjustment).  Since the return address is typically saved on the
+-   stack when a function makes a call, the saved LR must be updated outside
+-   the epilogue.
++  fp_offset = cfun->machine->frame.frame_size
++	      - cfun->machine->frame.hard_fp_offset;
+ 
+-   This poses problems as the store is generated well before the epilogue,
+-   so the offset of LR is not known yet.  Also optimizations will remove the
+-   store as it appears dead, even after the epilogue is generated (as the
+-   base or offset for loading LR is different in many cases).
++  if (cfun->machine->frame.reg_offset[LR_REGNUM] < 0)
++    return gen_rtx_REG (DImode, LR_REGNUM);
+ 
+-   To avoid these problems this implementation forces the frame pointer
+-   in eh_return functions so that the location of LR is fixed and known early.
+-   It also marks the store volatile, so no optimization is permitted to
+-   remove the store.  */
+-rtx
+-aarch64_eh_return_handler_rtx (void)
+-{
+-  rtx tmp = gen_frame_mem (Pmode,
+-    plus_constant (Pmode, hard_frame_pointer_rtx, UNITS_PER_WORD));
++  /* DSE and CSELIB do not detect an alias between sp+k1 and fp+k2.  This can
++     result in a store to save LR introduced by builtin_eh_return () being
++     incorrectly deleted because the alias is not detected.
++     So in the calculation of the address to copy the exception unwinding
++     return address to, we note 2 cases.
++     If FP is needed and the fp_offset is 0, it means that SP = FP and hence
++     we return a SP-relative location since all the addresses are SP-relative
++     in this case.  This prevents the store from being optimized away.
++     If the fp_offset is not 0, then the addresses will be FP-relative and
++     therefore we return a FP-relative location.  */
+ 
+-  /* Mark the store volatile, so no optimization is permitted to remove it.  */
+-  MEM_VOLATILE_P (tmp) = true;
+-  return tmp;
++  if (frame_pointer_needed)
++    {
++      if (fp_offset)
++        return gen_frame_mem (DImode,
++			      plus_constant (Pmode, hard_frame_pointer_rtx, UNITS_PER_WORD));
++      else
++        return gen_frame_mem (DImode,
++			      plus_constant (Pmode, stack_pointer_rtx, UNITS_PER_WORD));
++    }
++
++  /* If FP is not needed, we calculate the location of LR, which would be
++     at the top of the saved registers block.  */
++
++  return gen_frame_mem (DImode,
++			plus_constant (Pmode,
++				       stack_pointer_rtx,
++				       fp_offset
++				       + cfun->machine->frame.saved_regs_size
++				       - 2 * UNITS_PER_WORD));
+ }
+ 
+ /* Possibly output code to build up a constant in a register.  For
+--- a/src/gcc/config/aarch64/aarch64.h
++++ b/src/gcc/config/aarch64/aarch64.h
+@@ -389,9 +389,9 @@
+ #define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL)	\
+   aarch64_declare_function_name (STR, NAME, DECL)
+ 
+-/* For EH returns X4 contains the stack adjustment.  */
+-#define EH_RETURN_STACKADJ_RTX	gen_rtx_REG (Pmode, R4_REGNUM)
+-#define EH_RETURN_HANDLER_RTX  aarch64_eh_return_handler_rtx ()
++/* The register that holds the return address in exception handlers.  */
++#define AARCH64_EH_STACKADJ_REGNUM	(R0_REGNUM + 4)
++#define EH_RETURN_STACKADJ_RTX	gen_rtx_REG (Pmode, AARCH64_EH_STACKADJ_REGNUM)
+ 
+ /* Don't use __builtin_setjmp until we've defined it.  */
+ #undef DONT_USE_BUILTIN_SETJMP
diff --git a/debian/patches/svn-updates.diff b/debian/patches/svn-updates.diff
index c786d78..42a2772 100644
--- a/debian/patches/svn-updates.diff
+++ b/debian/patches/svn-updates.diff
@@ -1,10 +1,10 @@
-# DP: updates from the 6 branch upto 20170118 (r244586).
+# DP: updates from the 6 branch upto 20170121 (r244748).
 
 last_update()
 {
 	cat > ${dir}LAST_UPDATED <EOF
-Wed Jan 18 19:34:31 CET 2017
-Wed Jan 18 18:34:31 UTC 2017 (revision 244586)
+Sat Jan 21 18:20:40 CET 2017
+Sat Jan 21 17:20:40 UTC 2017 (revision 244748)
 EOF
 }
 
@@ -683,6 +683,30 @@ Index: gcc/c-family/ChangeLog
  2016-12-21  Release Manager
  
  	* GCC 6.3.0 released.
+Index: gcc/ipa-polymorphic-call.c
+===================================================================
+--- a/src/gcc/ipa-polymorphic-call.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/ipa-polymorphic-call.c	(.../branches/gcc-6-branch)
+@@ -463,13 +463,13 @@
+   /* Check that type is within range.  */
+   if (offset < 0)
+     return false;
+-  if (TYPE_SIZE (outer_type) && TYPE_SIZE (otr_type)
+-      && TREE_CODE (TYPE_SIZE (outer_type)) == INTEGER_CST
+-      && TREE_CODE (TYPE_SIZE (otr_type)) == INTEGER_CST
+-      && wi::ltu_p (wi::to_offset (TYPE_SIZE (outer_type)),
+-		    (wi::to_offset (TYPE_SIZE (otr_type)) + offset)))
+-    return false;
+ 
++  /* PR ipa/71207
++     As OUTER_TYPE can be a type which has a diamond virtual inheritance,
++     it's not necessary that INNER_TYPE will fit within OUTER_TYPE with
++     a given offset.  It can happen that INNER_TYPE also contains a base object,
++     however it would point to the same instance in the OUTER_TYPE.  */
++
+   context.offset = offset;
+   context.outer_type = TYPE_MAIN_VARIANT (outer_type);
+   context.maybe_derived_type = false;
 Index: gcc/c/ChangeLog
 ===================================================================
 --- a/src/gcc/c/ChangeLog	(.../tags/gcc_6_3_0_release)
@@ -731,7 +755,7 @@ Index: gcc/DATESTAMP
 +++ b/src/gcc/DATESTAMP	(.../branches/gcc-6-branch)
 @@ -1 +1 @@
 -20161221
-+20170118
++20170121
 Index: gcc/postreload.c
 ===================================================================
 --- a/src/gcc/postreload.c	(.../tags/gcc_6_3_0_release)
@@ -852,6 +876,33 @@ Index: gcc/omp-low.c
  
    return top;
  }
+Index: gcc/ipa-inline-transform.c
+===================================================================
+--- a/src/gcc/ipa-inline-transform.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/ipa-inline-transform.c	(.../branches/gcc-6-branch)
+@@ -324,6 +324,8 @@
+   if (DECL_FUNCTION_PERSONALITY (callee->decl))
+     DECL_FUNCTION_PERSONALITY (to->decl)
+       = DECL_FUNCTION_PERSONALITY (callee->decl);
++
++  bool reload_optimization_node = false;
+   if (!opt_for_fn (callee->decl, flag_strict_aliasing)
+       && opt_for_fn (to->decl, flag_strict_aliasing))
+     {
+@@ -336,8 +338,13 @@
+ 		 to->name (), to->order);
+       DECL_FUNCTION_SPECIFIC_OPTIMIZATION (to->decl)
+ 	 = build_optimization_node (&opts);
++      reload_optimization_node = true;
+     }
+ 
++  /* Reload global optimization flags.  */
++  if (reload_optimization_node && DECL_STRUCT_FUNCTION (to->decl) == cfun)
++    set_cfun (cfun, true);
++
+   /* If aliases are involved, redirect edge to the actual destination and
+      possibly remove the aliases.  */
+   if (e->callee != callee)
 Index: gcc/tree-ssa-sccvn.c
 ===================================================================
 --- a/src/gcc/tree-ssa-sccvn.c	(.../tags/gcc_6_3_0_release)
@@ -893,6 +944,14 @@ Index: gcc/tree-ssa-sccvn.c
  	    }
  	}
      }
+@@ -4735,6 +4755,7 @@
+   walker.walk (ENTRY_BLOCK_PTR_FOR_FN (cfun));
+   if (walker.fail)
+     {
++      scc_vn_restore_ssa_info ();
+       free_scc_vn ();
+       return false;
+     }
 Index: gcc/cgraphunit.c
 ===================================================================
 --- a/src/gcc/cgraphunit.c	(.../tags/gcc_6_3_0_release)
@@ -920,7 +979,66 @@ Index: gcc/ChangeLog
 ===================================================================
 --- a/src/gcc/ChangeLog	(.../tags/gcc_6_3_0_release)
 +++ b/src/gcc/ChangeLog	(.../branches/gcc-6-branch)
-@@ -1,3 +1,256 @@
+@@ -1,3 +1,315 @@
++2017-01-20  Bill Schmidt  <wschmidt at linux.vnet.ibm.com>
++
++	Backport from mainline
++	2017-01-16  Bill Schmidt  <wschmidt at linux.vnet.ibm.com>
++
++	* config/rs6000/rs6000.c (rtx_is_swappable_p): Change
++	UNSPEC_VSX__XXSPLTD to require special splat handling.
++
++2017-01-20  Wilco Dijkstra  <wdijkstr at arm.com>
++
++	Backport from mainline
++	PR target/77455
++	* config/aarch64/aarch64.md (eh_return): Remove pattern and splitter.
++	* config/aarch64/aarch64.h (AARCH64_EH_STACKADJ_REGNUM): Remove.
++	(EH_RETURN_HANDLER_RTX): New define.
++	* config/aarch64/aarch64.c (aarch64_frame_pointer_required):
++	Force frame pointer in EH return functions.
++	(aarch64_expand_epilogue): Add barrier for eh_return.
++	(aarch64_final_eh_return_addr): Remove.
++	(aarch64_eh_return_handler_rtx): New function.
++	* config/aarch64/aarch64-protos.h (aarch64_final_eh_return_addr):
++	Remove.
++	(aarch64_eh_return_handler_rtx): New prototype.
++
++2017-01-20  Richard Earnshaw  <rearnsha at arm.com>
++
++	Backported from mainline
++	2017-01-19  Richard Earnshaw  <rearnsha at arm.com>
++
++	PR rtl-optimization/79121
++	* expr.c (expand_expr_real_2, case LSHIFT_EXPR): Look at the signedness
++	of the inner type when shifting an extended value.
++
++2017-01-20  Martin Liska  <mliska at suse.cz>
++
++	Backport from mainline
++	2017-01-13  Martin Liska  <mliska at suse.cz>
++
++	PR ipa/79043
++	* function.c (set_cfun): Add new argument force.
++	* function.h (set_cfun): Likewise.
++	* ipa-inline-transform.c (inline_call): Use the function when
++	strict alising from is dropped for function we inline to.
++
++2017-01-20  Martin Liska  <mliska at suse.cz>
++
++	Backport from mainline
++	2017-01-17  Martin Liska  <mliska at suse.cz>
++
++	PR ipa/71207
++	* ipa-polymorphic-call.c (contains_type_p): Fix wrong
++	assumption and add comment.
++
++2017-01-19  Richard Biener  <rguenther at suse.de>
++
++	PR tree-optimization/72488
++	* tree-ssa-sccvn.c (run_scc_vn): When we abort the VN make
++	sure to restore SSA info.
++
 +2017-01-17  Jakub Jelinek  <jakub at redhat.com>
 +
 +	PR debug/78839
@@ -1203,6 +1321,47 @@ Index: gcc/testsuite/gcc.target/powerpc/swaps-p8-26.c
 +  vector float c = __builtin_vec_mul (a, b);
 +  __builtin_vec_xst (c, 0, z);
 +}
+Index: gcc/testsuite/gcc.target/powerpc/swaps-p8-27.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/swaps-p8-27.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/swaps-p8-27.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,36 @@
++/* { dg-do compile { target { powerpc64le-*-* } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
++/* { dg-options "-mcpu=power8 -O3 " } */
++/* { dg-final { scan-assembler-times "lxvd2x" 2 } } */
++/* { dg-final { scan-assembler-times "stxvd2x" 1 } } */
++/* { dg-final { scan-assembler-times "xxpermdi" 3 } } */
++
++/* Verify that swap optimization works correctly for a VSX direct splat.
++   The three xxpermdi's that are generated correspond to two splats
++   and the __builtin_vsx_xxpermdi.  */
++
++int printf (const char *__restrict __format, ...);
++typedef double __m128d __attribute__ ((__vector_size__ (16), __may_alias__));
++
++double s1[] = {2134.3343, 6678.346};
++double s2[] = {41124.234, 6678.346};
++long long dd[] = {1, 2}, d[2];
++union{long long l[2]; double d[2];} e;
++
++void
++foo ()
++{
++  __m128d source1, source2, dest;
++  __m128d a, b, c;
++
++  e.d[1] = s1[1];
++  e.l[0] = !__builtin_isunordered(s1[0], s2[0]) 
++    && s1[0] == s2[0] ? -1 : 0;
++  source1 = __builtin_vec_vsx_ld (0, s1);
++  source2 = __builtin_vec_vsx_ld (0, s2);
++  a = __builtin_vec_splat (source1, 0);
++  b = __builtin_vec_splat (source2, 0);
++  c = (__m128d)__builtin_vec_cmpeq (a, b);
++  dest = __builtin_vsx_xxpermdi (source1, c, 1);
++  *(__m128d *)d = dest;
++}
 Index: gcc/testsuite/gcc.target/arm/pr78255-1.c
 ===================================================================
 --- a/src/gcc/testsuite/gcc.target/arm/pr78255-1.c	(.../tags/gcc_6_3_0_release)
@@ -1351,6 +1510,93 @@ Index: gcc/testsuite/gcc.target/aarch64/pr78255.c
 +}
 +
 +/* { dg-final { scan-assembler "b\\s+bar" } } */
+Index: gcc/testsuite/gcc.target/aarch64/eh_return.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/aarch64/eh_return.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/aarch64/eh_return.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,82 @@
++/* { dg-do run } */
++/* { dg-options "-O2 -fno-inline" } */
++
++#include <stdlib.h>
++#include <stdio.h>
++
++int val, test, failed;
++
++int main (void);
++
++void
++eh0 (void *p)
++{
++  val = (int)(long)p & 7;
++  if (val)
++    abort ();
++}
++
++void
++eh1 (void *p, int x)
++{
++  void *q = __builtin_alloca (x);
++  eh0 (q);
++  __builtin_eh_return (0, p);
++}
++
++void
++eh2a (int a,int b,int c,int d,int e,int f,int g,int h, void *p)
++{
++  val = a + b + c + d + e + f + g + h +  (int)(long)p & 7;
++}
++
++void
++eh2 (void *p)
++{
++  eh2a (val, val, val, val, val, val, val, val, p);
++  __builtin_eh_return (0, p);
++}
++
++
++void
++continuation (void)
++{
++  test++;
++  main ();
++}
++
++void
++fail (void)
++{
++  failed = 1;
++  printf ("failed\n");
++  continuation ();
++}
++
++void
++do_test1 (void)
++{
++  if (!val)
++    eh1 (continuation, 100);
++  fail ();
++}
++
++void
++do_test2 (void)
++{
++  if (!val)
++    eh2 (continuation);
++  fail ();
++}
++
++int
++main (void)
++{
++  if (test == 0)
++    do_test1 ();
++  if (test == 1)
++    do_test2 ();
++  if (failed || test != 2)
++    exit (1);
++  exit (0);
++}
 Index: gcc/testsuite/gfortran.dg/gomp/pr78866-1.f90
 ===================================================================
 --- a/src/gcc/testsuite/gfortran.dg/gomp/pr78866-1.f90	(.../tags/gcc_6_3_0_release)
@@ -1424,6 +1670,71 @@ Index: gcc/testsuite/gfortran.dg/fimplicit_none_1.f90
 +   character(n) :: c  ! { dg-error "Scalar INTEGER expression expected" }
 +   c = 'c' ! { dg-error "has no IMPLICIT type" }
 +end
+Index: gcc/testsuite/gcc.c-torture/execute/pr79121.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.c-torture/execute/pr79121.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.c-torture/execute/pr79121.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,34 @@
++extern void abort (void);
++
++__attribute__ ((noinline, noclone)) unsigned long long f1 (int x)
++{
++  return ((unsigned long long) x) << 4;
++}
++
++__attribute__ ((noinline, noclone)) long long f2 (unsigned x)
++{
++  return ((long long) x) << 4;
++}
++
++__attribute__ ((noinline, noclone)) unsigned long long f3 (unsigned x)
++{
++  return ((unsigned long long) x) << 4;
++}
++
++__attribute__ ((noinline, noclone)) long long f4 (int x)
++{
++  return ((long long) x) << 4;
++}
++
++int main ()
++{
++  if (f1 (0xf0000000) != 0xffffffff00000000)
++    abort ();
++  if (f2 (0xf0000000) != 0xf00000000)
++    abort ();
++  if (f3 (0xf0000000) != 0xf00000000)
++    abort ();
++  if (f4 (0xf0000000) != 0xffffffff00000000)
++    abort ();
++  return 0;
++}
+Index: gcc/testsuite/gcc.c-torture/execute/pr79043.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.c-torture/execute/pr79043.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.c-torture/execute/pr79043.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,21 @@
++/* PR ipa/78791 */
++
++int val;
++
++int *ptr = &val;
++float *ptr2 = &val;
++
++static
++__attribute__((always_inline, optimize ("-fno-strict-aliasing")))
++typepun ()
++{
++  *ptr2=0;
++}
++
++main()
++{
++  *ptr=1;
++  typepun ();
++  if (*ptr)
++    __builtin_abort ();
++}
 Index: gcc/testsuite/gcc.c-torture/execute/pr77767.c
 ===================================================================
 --- a/src/gcc/testsuite/gcc.c-torture/execute/pr77767.c	(.../tags/gcc_6_3_0_release)
@@ -1604,7 +1915,54 @@ Index: gcc/testsuite/ChangeLog
 ===================================================================
 --- a/src/gcc/testsuite/ChangeLog	(.../tags/gcc_6_3_0_release)
 +++ b/src/gcc/testsuite/ChangeLog	(.../branches/gcc-6-branch)
-@@ -1,3 +1,144 @@
+@@ -1,3 +1,191 @@
++2017-01-20  Bill Schmidt  <wschmidt at linux.vnet.ibm.com>
++
++	Backport from mainline
++	2017-01-16  Bill Schmidt  <wschmidt at linux.vnet.ibm.com>
++
++	* gcc.target/powerpc/swaps-p8-27.c: New.
++
++2017-01-20  Wilco Dijkstra  <wdijkstr at arm.com>
++
++	Backport from mainline
++	PR target/77455
++	* gcc.target/aarch64/eh_return.c: New test.
++
++2017-01-20  Marek Polacek  <polacek at redhat.com>
++
++	Backported from mainline
++	2017-01-04  Marek Polacek  <polacek at redhat.com>
++
++	PR c++/77545
++	PR c++/77284
++	* g++.dg/cpp0x/range-for32.C: New test.
++	* g++.dg/cpp0x/range-for33.C: New test.
++
++2017-01-20  Richard Earnshaw  <rearnsha at arm.com>
++
++	Backported from mainline
++	2017-01-19  Richard Earnshaw  <rearnsha at arm.com>
++
++	PR rtl-optimization/79121
++	* gcc.c-torture/execute/pr79121.c: New test.
++
++2017-01-20  Martin Liska  <mliska at suse.cz>
++
++	Backport from mainline
++	2017-01-13  Martin Liska  <mliska at suse.cz>
++
++	PR ipa/79043
++	* gcc.c-torture/execute/pr79043.c: New test.
++
++2017-01-20  Martin Liska  <mliska at suse.cz>
++
++	Backport from mainline
++	2017-01-17  Martin Liska  <mliska at suse.cz>
++
++	PR ipa/71207
++	* g++.dg/ipa/pr71207.C: New test.
++
 +2017-01-17  Jakub Jelinek  <jakub at redhat.com>
 +
 +	Backported from mainline
@@ -1834,6 +2192,46 @@ Index: gcc/testsuite/g++.dg/cpp0x/pr71182.C
 +    g ? g->As<T>() : nullptr;
 +  }
 +};
+Index: gcc/testsuite/g++.dg/cpp0x/range-for32.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp0x/range-for32.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp0x/range-for32.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,16 @@
++// PR c++/77545
++// { dg-do compile { target c++11 } }
++// { dg-options "-Wno-pedantic" }
++
++template < typename T > struct A
++{
++  A ();
++  ~A ();
++  T t;
++};
++
++void f (A < int > a)
++{
++  for (auto x : (A<int>[]) { a })
++    ;
++}
+Index: gcc/testsuite/g++.dg/cpp0x/range-for33.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp0x/range-for33.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp0x/range-for33.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,14 @@
++// PR c++/77284
++// { dg-do compile { target c++11 } }
++
++#include <initializer_list>
++
++struct A
++{
++  ~A () {}
++};
++
++void foo (A & v)
++{
++  for (A a : { v }) {};
++}
 Index: gcc/testsuite/g++.dg/ipa/pr77905.C
 ===================================================================
 --- a/src/gcc/testsuite/g++.dg/ipa/pr77905.C	(.../tags/gcc_6_3_0_release)
@@ -1860,6 +2258,53 @@ Index: gcc/testsuite/g++.dg/ipa/pr77905.C
 +B::B() : A(1) {}
 +
 +C::C(int) : A(1) {}
+Index: gcc/testsuite/g++.dg/ipa/pr71207.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/ipa/pr71207.C	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/ipa/pr71207.C	(.../branches/gcc-6-branch)
+@@ -0,0 +1,42 @@
++/* PR ipa/71207 */
++/* { dg-do run } */
++
++class Class1
++{
++public:
++  Class1() {};
++  virtual ~Class1() {};
++
++protected:
++  unsigned Field1;
++};
++
++class Class2 : public virtual Class1
++{
++};
++
++class Class3 : public virtual Class1
++{
++public:
++  virtual void Method1() = 0;
++
++  void Method2()
++  {
++    Method1();
++  }
++};
++
++class Class4 : public Class2, public virtual Class3
++{
++public:
++  Class4() {};
++  virtual void Method1() {};
++};
++
++int main()
++{
++  Class4 var1;
++  var1.Method2();
++
++  return 0;
++}
 Index: gcc/testsuite/c-c++-common/Wunused-var-16.c
 ===================================================================
 --- a/src/gcc/testsuite/c-c++-common/Wunused-var-16.c	(.../tags/gcc_6_3_0_release)
@@ -1893,11 +2338,32 @@ Index: gcc/cp/typeck.c
        break;
  
      case ABS_EXPR:
+Index: gcc/cp/constexpr.c
+===================================================================
+--- a/src/gcc/cp/constexpr.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/cp/constexpr.c	(.../branches/gcc-6-branch)
+@@ -5295,6 +5295,7 @@
+       /* We can see these in statement-expressions.  */
+       return true;
+ 
++    case CLEANUP_STMT:
+     case EMPTY_CLASS_EXPR:
+       return false;
+ 
 Index: gcc/cp/ChangeLog
 ===================================================================
 --- a/src/gcc/cp/ChangeLog	(.../tags/gcc_6_3_0_release)
 +++ b/src/gcc/cp/ChangeLog	(.../branches/gcc-6-branch)
-@@ -1,3 +1,32 @@
+@@ -1,3 +1,41 @@
++2017-01-20  Marek Polacek  <polacek at redhat.com>
++	
++	Backported from mainline
++	2017-01-04  Marek Polacek  <polacek at redhat.com>
++
++	PR c++/77545
++	PR c++/77284
++	* constexpr.c (potential_constant_expression_1): Handle CLEANUP_STMT.
++
 +2017-01-17  Jakub Jelinek  <jakub at redhat.com>
 +
 +	Backported from mainline
@@ -2269,6 +2735,90 @@ Index: gcc/expr.c
  					 value, cleared, alias, reverse);
  	      }
  	  }
+@@ -8941,9 +8929,9 @@
+ 
+ 	/* Left shift optimization when shifting across word_size boundary.
+ 
+-	   If mode == GET_MODE_WIDER_MODE (word_mode), then normally there isn't
+-	   native instruction to support this wide mode left shift.  Given below
+-	   scenario:
++	   If mode == GET_MODE_WIDER_MODE (word_mode), then normally
++	   there isn't native instruction to support this wide mode
++	   left shift.  Given below scenario:
+ 
+ 	    Type A = (Type) B  << C
+ 
+@@ -8952,10 +8940,11 @@
+ 
+ 			 | word_size |
+ 
+-	   If the shift amount C caused we shift B to across the word size
+-	   boundary, i.e part of B shifted into high half of destination
+-	   register, and part of B remains in the low half, then GCC will use
+-	   the following left shift expand logic:
++	   If the shift amount C caused we shift B to across the word
++	   size boundary, i.e part of B shifted into high half of
++	   destination register, and part of B remains in the low
++	   half, then GCC will use the following left shift expand
++	   logic:
+ 
+ 	   1. Initialize dest_low to B.
+ 	   2. Initialize every bit of dest_high to the sign bit of B.
+@@ -8965,20 +8954,30 @@
+ 	   5. Logic right shift D by (word_size - C).
+ 	   6. Or the result of 4 and 5 to finalize dest_high.
+ 
+-	   While, by checking gimple statements, if operand B is coming from
+-	   signed extension, then we can simplify above expand logic into:
++	   While, by checking gimple statements, if operand B is
++	   coming from signed extension, then we can simplify above
++	   expand logic into:
+ 
+ 	      1. dest_high = src_low >> (word_size - C).
+ 	      2. dest_low = src_low << C.
+ 
+-	   We can use one arithmetic right shift to finish all the purpose of
+-	   steps 2, 4, 5, 6, thus we reduce the steps needed from 6 into 2.  */
++	   We can use one arithmetic right shift to finish all the
++	   purpose of steps 2, 4, 5, 6, thus we reduce the steps
++	   needed from 6 into 2.
+ 
++	   The case is similar for zero extension, except that we
++	   initialize dest_high to zero rather than copies of the sign
++	   bit from B.  Furthermore, we need to use a logical right shift
++	   in this case.
++
++	   The choice of sign-extension versus zero-extension is
++	   determined entirely by whether or not B is signed and is
++	   independent of the current setting of unsignedp.  */
++
+ 	temp = NULL_RTX;
+ 	if (code == LSHIFT_EXPR
+ 	    && target
+ 	    && REG_P (target)
+-	    && ! unsignedp
+ 	    && mode == GET_MODE_WIDER_MODE (word_mode)
+ 	    && GET_MODE_SIZE (mode) == 2 * GET_MODE_SIZE (word_mode)
+ 	    && TREE_CONSTANT (treeop1)
+@@ -8999,6 +8998,8 @@
+ 		    rtx_insn *seq, *seq_old;
+ 		    unsigned int high_off = subreg_highpart_offset (word_mode,
+ 								    mode);
++		    bool extend_unsigned
++		      = TYPE_UNSIGNED (TREE_TYPE (gimple_assign_rhs1 (def)));
+ 		    rtx low = lowpart_subreg (word_mode, op0, mode);
+ 		    rtx dest_low = lowpart_subreg (word_mode, target, mode);
+ 		    rtx dest_high = simplify_gen_subreg (word_mode, target,
+@@ -9010,7 +9011,8 @@
+ 		    start_sequence ();
+ 		    /* dest_high = src_low >> (word_size - C).  */
+ 		    temp = expand_variable_shift (RSHIFT_EXPR, word_mode, low,
+-						  rshift, dest_high, unsignedp);
++						  rshift, dest_high,
++						  extend_unsigned);
+ 		    if (temp != dest_high)
+ 		      emit_move_insn (dest_high, temp);
+ 
 Index: gcc/lra-remat.c
 ===================================================================
 --- a/src/gcc/lra-remat.c	(.../tags/gcc_6_3_0_release)
@@ -2400,6 +2950,35 @@ Index: gcc/fortran/ChangeLog
  2016-12-21  Release Manager
  
  	* GCC 6.3.0 released.
+Index: gcc/function.c
+===================================================================
+--- a/src/gcc/function.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/function.c	(.../branches/gcc-6-branch)
+@@ -4800,9 +4800,9 @@
+ /* cfun should never be set directly; use this function.  */
+ 
+ void
+-set_cfun (struct function *new_cfun)
++set_cfun (struct function *new_cfun, bool force)
+ {
+-  if (cfun != new_cfun)
++  if (cfun != new_cfun || force)
+     {
+       cfun = new_cfun;
+       invoke_set_current_function_hook (new_cfun ? new_cfun->decl : NULL_TREE);
+Index: gcc/function.h
+===================================================================
+--- a/src/gcc/function.h	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/function.h	(.../branches/gcc-6-branch)
+@@ -606,7 +606,7 @@
+ extern void number_blocks (tree);
+ 
+ /* cfun shouldn't be set directly; use one of these functions instead.  */
+-extern void set_cfun (struct function *new_cfun);
++extern void set_cfun (struct function *new_cfun, bool force = false);
+ extern void push_cfun (struct function *new_cfun);
+ extern void pop_cfun (void);
+ 
 Index: gcc/lto/ChangeLog
 ===================================================================
 --- a/src/gcc/lto/ChangeLog	(.../tags/gcc_6_3_0_release)
@@ -44111,6 +44690,173 @@ Index: gcc/config/aarch64/aarch64-freebsd.h
 +#define TARGET_BINDS_LOCAL_P default_binds_local_p_2
 +
 +#endif  /* GCC_AARCH64_FREEBSD_H */
+Index: gcc/config/aarch64/aarch64.md
+===================================================================
+--- a/src/gcc/config/aarch64/aarch64.md	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/aarch64/aarch64.md	(.../branches/gcc-6-branch)
+@@ -587,25 +587,6 @@
+   [(set_attr "type" "branch")]
+ )
+ 
+-(define_insn "eh_return"
+-  [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
+-    UNSPECV_EH_RETURN)]
+-  ""
+-  "#"
+-  [(set_attr "type" "branch")]
+-
+-)
+-
+-(define_split
+-  [(unspec_volatile [(match_operand:DI 0 "register_operand" "")]
+-    UNSPECV_EH_RETURN)]
+-  "reload_completed"
+-  [(set (match_dup 1) (match_dup 0))]
+-  {
+-    operands[1] = aarch64_final_eh_return_addr ();
+-  }
+-)
+-
+ (define_insn "*cb<optab><mode>1"
+   [(set (pc) (if_then_else (EQL (match_operand:GPI 0 "register_operand" "r")
+ 				(const_int 0))
+Index: gcc/config/aarch64/aarch64-protos.h
+===================================================================
+--- a/src/gcc/config/aarch64/aarch64-protos.h	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/aarch64/aarch64-protos.h	(.../branches/gcc-6-branch)
+@@ -338,7 +338,7 @@
+ int aarch64_simd_attr_length_move (rtx_insn *);
+ int aarch64_uxt_size (int, HOST_WIDE_INT);
+ int aarch64_vec_fpconst_pow_of_2 (rtx);
+-rtx aarch64_final_eh_return_addr (void);
++rtx aarch64_eh_return_handler_rtx (void);
+ rtx aarch64_legitimize_reload_address (rtx *, machine_mode, int, int, int);
+ rtx aarch64_mask_from_zextract_ops (rtx, rtx);
+ const char *aarch64_output_move_struct (rtx *operands);
+Index: gcc/config/aarch64/aarch64.c
+===================================================================
+--- a/src/gcc/config/aarch64/aarch64.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/aarch64/aarch64.c	(.../branches/gcc-6-branch)
+@@ -2480,6 +2480,10 @@
+       && (!crtl->is_leaf || df_regs_ever_live_p (LR_REGNUM)))
+     return true;
+ 
++  /* Force a frame pointer for EH returns so the return address is at FP+8.  */
++  if (crtl->calls_eh_return)
++    return true;
++
+   return false;
+ }
+ 
+@@ -3036,7 +3040,8 @@
+   rtx_insn *insn;
+   /* We need to add memory barrier to prevent read from deallocated stack.  */
+   bool need_barrier_p = (get_frame_size () != 0
+-			 || cfun->machine->frame.saved_varargs_size);
++			 || cfun->machine->frame.saved_varargs_size
++			 || crtl->calls_eh_return);
+ 
+   aarch64_layout_frame ();
+ 
+@@ -3189,52 +3194,40 @@
+     emit_jump_insn (ret_rtx);
+ }
+ 
+-/* Return the place to copy the exception unwinding return address to.
+-   This will probably be a stack slot, but could (in theory be the
+-   return register).  */
+-rtx
+-aarch64_final_eh_return_addr (void)
+-{
+-  HOST_WIDE_INT fp_offset;
++/* Implement EH_RETURN_HANDLER_RTX.  EH returns need to either return
++   normally or return to a previous frame after unwinding.
+ 
+-  aarch64_layout_frame ();
++   An EH return uses a single shared return sequence.  The epilogue is
++   exactly like a normal epilogue except that it has an extra input
++   register (EH_RETURN_STACKADJ_RTX) which contains the stack adjustment
++   that must be applied after the frame has been destroyed.  An extra label
++   is inserted before the epilogue which initializes this register to zero,
++   and this is the entry point for a normal return.
+ 
+-  fp_offset = cfun->machine->frame.frame_size
+-	      - cfun->machine->frame.hard_fp_offset;
++   An actual EH return updates the return address, initializes the stack
++   adjustment and jumps directly into the epilogue (bypassing the zeroing
++   of the adjustment).  Since the return address is typically saved on the
++   stack when a function makes a call, the saved LR must be updated outside
++   the epilogue.
+ 
+-  if (cfun->machine->frame.reg_offset[LR_REGNUM] < 0)
+-    return gen_rtx_REG (DImode, LR_REGNUM);
++   This poses problems as the store is generated well before the epilogue,
++   so the offset of LR is not known yet.  Also optimizations will remove the
++   store as it appears dead, even after the epilogue is generated (as the
++   base or offset for loading LR is different in many cases).
+ 
+-  /* DSE and CSELIB do not detect an alias between sp+k1 and fp+k2.  This can
+-     result in a store to save LR introduced by builtin_eh_return () being
+-     incorrectly deleted because the alias is not detected.
+-     So in the calculation of the address to copy the exception unwinding
+-     return address to, we note 2 cases.
+-     If FP is needed and the fp_offset is 0, it means that SP = FP and hence
+-     we return a SP-relative location since all the addresses are SP-relative
+-     in this case.  This prevents the store from being optimized away.
+-     If the fp_offset is not 0, then the addresses will be FP-relative and
+-     therefore we return a FP-relative location.  */
++   To avoid these problems this implementation forces the frame pointer
++   in eh_return functions so that the location of LR is fixed and known early.
++   It also marks the store volatile, so no optimization is permitted to
++   remove the store.  */
++rtx
++aarch64_eh_return_handler_rtx (void)
++{
++  rtx tmp = gen_frame_mem (Pmode,
++    plus_constant (Pmode, hard_frame_pointer_rtx, UNITS_PER_WORD));
+ 
+-  if (frame_pointer_needed)
+-    {
+-      if (fp_offset)
+-        return gen_frame_mem (DImode,
+-			      plus_constant (Pmode, hard_frame_pointer_rtx, UNITS_PER_WORD));
+-      else
+-        return gen_frame_mem (DImode,
+-			      plus_constant (Pmode, stack_pointer_rtx, UNITS_PER_WORD));
+-    }
+-
+-  /* If FP is not needed, we calculate the location of LR, which would be
+-     at the top of the saved registers block.  */
+-
+-  return gen_frame_mem (DImode,
+-			plus_constant (Pmode,
+-				       stack_pointer_rtx,
+-				       fp_offset
+-				       + cfun->machine->frame.saved_regs_size
+-				       - 2 * UNITS_PER_WORD));
++  /* Mark the store volatile, so no optimization is permitted to remove it.  */
++  MEM_VOLATILE_P (tmp) = true;
++  return tmp;
+ }
+ 
+ /* Possibly output code to build up a constant in a register.  For
+Index: gcc/config/aarch64/aarch64.h
+===================================================================
+--- a/src/gcc/config/aarch64/aarch64.h	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/aarch64/aarch64.h	(.../branches/gcc-6-branch)
+@@ -389,9 +389,9 @@
+ #define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL)	\
+   aarch64_declare_function_name (STR, NAME, DECL)
+ 
+-/* The register that holds the return address in exception handlers.  */
+-#define AARCH64_EH_STACKADJ_REGNUM	(R0_REGNUM + 4)
+-#define EH_RETURN_STACKADJ_RTX	gen_rtx_REG (Pmode, AARCH64_EH_STACKADJ_REGNUM)
++/* For EH returns X4 contains the stack adjustment.  */
++#define EH_RETURN_STACKADJ_RTX	gen_rtx_REG (Pmode, R4_REGNUM)
++#define EH_RETURN_HANDLER_RTX  aarch64_eh_return_handler_rtx ()
+ 
+ /* Don't use __builtin_setjmp until we've defined it.  */
+ #undef DONT_USE_BUILTIN_SETJMP
 Index: gcc/config/rs6000/rs6000.opt
 ===================================================================
 --- a/src/gcc/config/rs6000/rs6000.opt	(.../tags/gcc_6_3_0_release)
@@ -44270,7 +45016,15 @@ Index: gcc/config/rs6000/rs6000.c
      }
  
    emit_insn (gen_lshrdi3 (dest_di, shift_reg, GEN_INT (63)));
-@@ -38634,6 +38658,12 @@
+@@ -38564,6 +38588,7 @@
+ 	  case UNSPEC_VSX_CVSPDPN:
+ 	    return 0;
+ 	  case UNSPEC_VSPLT_DIRECT:
++	  case UNSPEC_VSX_XXSPLTD:
+ 	    *special = SH_SPLAT;
+ 	    return 1;
+ 	  case UNSPEC_REDUC_PLUS:
+@@ -38634,6 +38659,12 @@
      {
        if (GET_CODE (body) == SET)
  	{
@@ -44283,7 +45037,7 @@ Index: gcc/config/rs6000/rs6000.c
  	  *special = SH_NOSWAP_LD;
  	  return 1;
  	}
-@@ -38645,6 +38675,12 @@
+@@ -38645,6 +38676,12 @@
      {
        if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) != UNSPEC)
  	{
diff --git a/debian/rules.patch b/debian/rules.patch
index fdd13fd..e08fa0e 100644
--- a/debian/rules.patch
+++ b/debian/rules.patch
@@ -15,6 +15,7 @@ series_file	?= $(patchdir)/series
 debian_patches = \
 	svn-updates \
 	libiberty-updates \
+	$(if $(with_linaro_branch),gcc-linaro-r244724-revert) \
 	$(if $(with_linaro_branch),gcc-linaro-r244242-revert) \
 	$(if $(with_linaro_branch),gcc-linaro) \
 	$(if $(with_linaro_branch),gcc-linaro-no-macros) \

-- 
Alioth's /usr/local/bin/git-commit-notice on /srv/git.debian.org/git/reproducible/gcc-6.git



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