[gcc-6] 370/401: * Update to SVN 20170205 (r245197) from the gcc-6-branch.
Ximin Luo
infinity0 at debian.org
Wed Apr 5 15:50:40 UTC 2017
This is an automated email from the git hooks/post-receive script.
infinity0 pushed a commit to branch pu/reproducible_builds
in repository gcc-6.
commit 6acd23faf741f673826c91dbf4ed5b4d99f22745
Author: doko <doko at 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca>
Date: Sun Feb 5 20:25:17 2017 +0000
* Update to SVN 20170205 (r245197) from the gcc-6-branch.
git-svn-id: svn://anonscm.debian.org/gcccvs/branches/sid/gcc-6@9284 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca
---
debian/changelog | 7 +-
debian/patches/svn-updates.diff | 189 ++++++++++++++++++++++++++++++++++++++--
2 files changed, 187 insertions(+), 9 deletions(-)
diff --git a/debian/changelog b/debian/changelog
index 0cda4bf..b6492d8 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,11 +1,12 @@
gcc-6 (6.3.0-6) UNRELEASED; urgency=medium
- * Update to SVN 20170202 (r245115) from the gcc-6-branch.
+ * Update to SVN 20170205 (r245197) from the gcc-6-branch.
- Fix PR libstdc++/78346, PR libstdc++/79195, PR libstdc++/79254,
PR target/78478, PR target/79268 (PPC), PR tree-optimization/79034,
PR middle-end/78742, PR target/77439 (ARM32), PR c++/79176,
PR fortran/70697, PR fortran/70696, PR fortran/79305, PR go/79037,
- PR go/79281 (closes: #853223).
+ PR go/79281 (closes: #853223), PR target/78862 (tilegx), PR lto/79061,
+ PR target/65484 (PPC).
[ Aurelien Jarno ]
* Don't use disable madd4 on MIPS big-endian.
@@ -18,7 +19,7 @@ gcc-6 (6.3.0-6) UNRELEASED; urgency=medium
* Configure staged builds with --disable-libmpx (Helmut Grohne).
Closes: #854159.
- -- Matthias Klose <doko at debian.org> Thu, 02 Feb 2017 09:44:06 +0100
+ -- Matthias Klose <doko at debian.org> Sun, 05 Feb 2017 21:16:42 +0100
gcc-6 (6.3.0-5) unstable; urgency=medium
diff --git a/debian/patches/svn-updates.diff b/debian/patches/svn-updates.diff
index 065f66c..a0a3080 100644
--- a/debian/patches/svn-updates.diff
+++ b/debian/patches/svn-updates.diff
@@ -1,10 +1,10 @@
-# DP: updates from the 6 branch upto 20170202 (r245115).
+# DP: updates from the 6 branch upto 20170205 (r245197).
last_update()
{
cat > ${dir}LAST_UPDATED <EOF
-Thu Feb 2 09:29:13 CET 2017
-Thu Feb 2 08:29:13 UTC 2017 (revision 245115)
+Sun Feb 5 21:14:30 CET 2017
+Sun Feb 5 20:14:30 UTC 2017 (revision 245197)
EOF
}
@@ -1393,7 +1393,7 @@ Index: gcc/DATESTAMP
+++ b/src/gcc/DATESTAMP (.../branches/gcc-6-branch)
@@ -1 +1 @@
-20161221
-+20170202
++20170205
Index: gcc/postreload.c
===================================================================
--- a/src/gcc/postreload.c (.../tags/gcc_6_3_0_release)
@@ -1637,7 +1637,31 @@ Index: gcc/ChangeLog
===================================================================
--- a/src/gcc/ChangeLog (.../tags/gcc_6_3_0_release)
+++ b/src/gcc/ChangeLog (.../branches/gcc-6-branch)
-@@ -1,3 +1,400 @@
+@@ -1,3 +1,424 @@
++2017-02-03 Carl Love <cel at us.ibm.com>
++
++ Backport of two commits from mainline, r244943 and r244904,
++ dated 017-01-26 and 2017-01-25 respectively
++
++ * config/rs6000/rs6000-c (altivec_overloaded_builtins): Fix order
++ of entries for ALTIVEC_BUILTIN_VEC_PACKS. Remove bogus entries
++ for P8V_BUILTIN_VEC_VGBBD.
++
++2017-02-03 Walter Lee <walt at tilera.com>
++
++ Backport from mainline
++ 2017-02-03 Walter Lee <walt at tilera.com>
++
++ PR target/78862
++ * config/tilegx/tilegx.md (tilegx_expand_prologue): Add blockage
++ after initial stackframe link reg save.
++ * config/tilepro/tilepro.md (tilepro_expand_prologue): Likewise.
++
++2017-02-03 Maxim Ostapenko <m.ostapenko at samsung.com>
++
++ PR lto/79061
++ * asan.c (asan_add_global): Force has_dynamic_init to zero in LTO mode.
++
+2017-01-31 Bill Schmidt <wschmidt at linux.vnet.ibm.com>
+
+ Backport from mainline
@@ -2832,6 +2856,37 @@ Index: gcc/testsuite/gcc.target/powerpc/pr79268.c
+ vec_xst (a, 0, x);
+ return vec_xl (0, x);
+}
+Index: gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c (.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/builtins-3-p8.c (.../branches/gcc-6-branch)
+@@ -0,0 +1,26 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target powerpc_p8vector_ok } */
++/* { dg-options "-mcpu=power8" } */
++
++#include <altivec.h>
++
++vector signed int
++test_vsi_packs_vsll_vsll (vector signed long long x,
++ vector signed long long y)
++{
++ return vec_packs (x, y);
++}
++
++vector unsigned int
++test_vui_packs_vull_vull (vector unsigned long long x,
++ vector unsigned long long y)
++{
++ return vec_packs (x, y);
++}
++
++/* Expected test results:
++ test_vsi_packs_vsll_vsll 1 vpksdss
++ test_vui_packs_vull_vull 1 vpkudus */
++
++/* { dg-final { scan-assembler-times "vpksdss" 1 } } */
++/* { dg-final { scan-assembler-times "vpkudus" 1 } } */
Index: gcc/testsuite/gcc.target/powerpc/swaps-p8-26.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/powerpc/swaps-p8-26.c (.../tags/gcc_6_3_0_release)
@@ -3811,7 +3866,22 @@ Index: gcc/testsuite/ChangeLog
===================================================================
--- a/src/gcc/testsuite/ChangeLog (.../tags/gcc_6_3_0_release)
+++ b/src/gcc/testsuite/ChangeLog (.../branches/gcc-6-branch)
-@@ -1,3 +1,280 @@
+@@ -1,3 +1,295 @@
++2017-02-03 Carl Love <cel at us.ibm.com>
++
++ * gcc.target/powerpc/builtins-3-p8.c: Add new testfile for missing
++ vec_packs built-in tests.
++
++2017-02-03 Bill Schmidt <wschmidt at linux.vnet.ibm.com>
++
++ Backport from mainline
++ 2017-01-27 Bill Schmidt <wschmidt at linux.vnet.ibm.com>
++
++ PR target/65484
++ * g++.dg/vect/pr36648.cc: Modify to reflect that the loop is not
++ vectorized on POWER unless hardware misaligned loads are
++ available.
++
+2017-01-31 Bill Schmidt <wschmidt at linux.vnet.ibm.com>
+
+ Backport from mainline
@@ -4445,6 +4515,25 @@ Index: gcc/testsuite/g++.dg/ipa/pr71207.C
+
+ return 0;
+}
+Index: gcc/testsuite/g++.dg/vect/pr36648.cc
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/vect/pr36648.cc (.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/g++.dg/vect/pr36648.cc (.../branches/gcc-6-branch)
+@@ -17,7 +17,12 @@
+
+ int main() { }
+
+-/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! vect_no_align } } } } */
+-/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { ! vect_no_align } } } } */
++/* On older powerpc hardware (POWER7 and earlier), the default flag
++ -mno-allow-movmisalign prevents vectorization. On POWER8 and later,
++ when vect_hw_misalign is true, vectorization occurs. For other
++ targets, ! vect_no_align is a sufficient test. */
+
++/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { { { ! vect_no_align } && { ! powerpc*-*-* } } || { powerpc*-*-* && vect_hw_misalign } } } } } */
++/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { { { ! vect_no_align } && { ! powerpc*-*-* } } || { powerpc*-*-* && vect_hw_misalign } } } } } */
+
++
Index: gcc/testsuite/c-c++-common/Wunused-var-16.c
===================================================================
--- a/src/gcc/testsuite/c-c++-common/Wunused-var-16.c (.../tags/gcc_6_3_0_release)
@@ -5363,6 +5452,23 @@ Index: gcc/go/gofrontend/expressions.cc
if (is_comparison)
{
+Index: gcc/asan.c
+===================================================================
+--- a/src/gcc/asan.c (.../tags/gcc_6_3_0_release)
++++ b/src/gcc/asan.c (.../branches/gcc-6-branch)
+@@ -2275,7 +2275,11 @@
+ CONSTRUCTOR_APPEND_ELT (vinner, NULL_TREE,
+ fold_convert (const_ptr_type_node, module_name_cst));
+ varpool_node *vnode = varpool_node::get (decl);
+- int has_dynamic_init = vnode ? vnode->dynamically_initialized : 0;
++ int has_dynamic_init = 0;
++ /* FIXME: Enable initialization order fiasco detection in LTO mode once
++ proper fix for PR 79061 will be applied. */
++ if (!in_lto_p)
++ has_dynamic_init = vnode ? vnode->dynamically_initialized : 0;
+ CONSTRUCTOR_APPEND_ELT (vinner, NULL_TREE,
+ build_int_cst (uptr, has_dynamic_init));
+ tree locptr = NULL_TREE;
Index: gcc/lra-remat.c
===================================================================
--- a/src/gcc/lra-remat.c (.../tags/gcc_6_3_0_release)
@@ -47224,6 +47330,24 @@ Index: gcc/config/i386/i386.c
len++;
}
else
+Index: gcc/config/tilegx/tilegx.c
+===================================================================
+--- a/src/gcc/config/tilegx/tilegx.c (.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/tilegx/tilegx.c (.../branches/gcc-6-branch)
+@@ -3996,8 +3996,11 @@
+ /* Save lr first in its special location because code after this
+ might use the link register as a scratch register. */
+ if (df_regs_ever_live_p (TILEGX_LINK_REGNUM) || crtl->calls_eh_return)
+- FRP (frame_emit_store (TILEGX_LINK_REGNUM, TILEGX_LINK_REGNUM,
+- stack_pointer_rtx, stack_pointer_rtx, 0));
++ {
++ FRP (frame_emit_store (TILEGX_LINK_REGNUM, TILEGX_LINK_REGNUM,
++ stack_pointer_rtx, stack_pointer_rtx, 0));
++ emit_insn (gen_blockage ());
++ }
+
+ if (total_size == 0)
+ {
Index: gcc/config/nds32/nds32.md
===================================================================
--- a/src/gcc/config/nds32/nds32.md (.../tags/gcc_6_3_0_release)
@@ -47535,6 +47659,41 @@ Index: gcc/config/aarch64/aarch64.h
/* Don't use __builtin_setjmp until we've defined it. */
#undef DONT_USE_BUILTIN_SETJMP
+Index: gcc/config/rs6000/rs6000-c.c
+===================================================================
+--- a/src/gcc/config/rs6000/rs6000-c.c (.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/rs6000/rs6000-c.c (.../branches/gcc-6-branch)
+@@ -2133,14 +2133,14 @@
+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
+ { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSWSS,
+ RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
++ { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS,
++ RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
++ { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS,
++ RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
+ { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS,
+ RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 },
+ { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS,
+ RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 },
+- { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS,
+- RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 },
+- { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS,
+- RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 },
+ { ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS,
+ RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 },
+ { ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS,
+@@ -4550,11 +4550,6 @@
+ { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW,
+ RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 },
+
+- { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
+- RS6000_BTI_V16QI, 0, 0, 0 },
+- { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
+- RS6000_BTI_unsigned_V16QI, 0, 0, 0 },
+-
+ { P9V_BUILTIN_VEC_VSLV, P9V_BUILTIN_VSLV,
+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
+ RS6000_BTI_unsigned_V16QI, 0 },
Index: gcc/config/rs6000/rs6000.opt
===================================================================
--- a/src/gcc/config/rs6000/rs6000.opt (.../tags/gcc_6_3_0_release)
@@ -47822,6 +47981,24 @@ Index: gcc/config/rs6000/altivec.h
/* Note, xxsldi and xxpermdi were added as __builtin_vsx_<xxx> functions
instead of __builtin_vec_<xxx> */
+Index: gcc/config/tilepro/tilepro.c
+===================================================================
+--- a/src/gcc/config/tilepro/tilepro.c (.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/tilepro/tilepro.c (.../branches/gcc-6-branch)
+@@ -3534,8 +3534,11 @@
+ /* Save lr first in its special location because code after this
+ might use the link register as a scratch register. */
+ if (df_regs_ever_live_p (TILEPRO_LINK_REGNUM) || crtl->calls_eh_return)
+- FRP (frame_emit_store (TILEPRO_LINK_REGNUM, TILEPRO_LINK_REGNUM,
+- stack_pointer_rtx, stack_pointer_rtx, 0));
++ {
++ FRP (frame_emit_store (TILEPRO_LINK_REGNUM, TILEPRO_LINK_REGNUM,
++ stack_pointer_rtx, stack_pointer_rtx, 0));
++ emit_insn (gen_blockage ());
++ }
+
+ if (total_size == 0)
+ {
Index: gcc/config/arm/arm.c
===================================================================
--- a/src/gcc/config/arm/arm.c (.../tags/gcc_6_3_0_release)
--
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