[gcc-6] 394/401: * Update the Linaro support to the 6.3-2017.03 snapshot.
Ximin Luo
infinity0 at debian.org
Wed Apr 5 15:50:44 UTC 2017
This is an automated email from the git hooks/post-receive script.
infinity0 pushed a commit to branch pu/reproducible_builds
in repository gcc-6.
commit cba671fed848c03423c100325288984f6bd3a04b
Author: doko <doko at 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca>
Date: Fri Mar 17 15:22:12 2017 +0000
* Update the Linaro support to the 6.3-2017.03 snapshot.
git-svn-id: svn://anonscm.debian.org/gcccvs/branches/sid/gcc-6@9376 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca
---
debian/changelog | 6 +
debian/patches/gcc-linaro-doc.diff | 93 +-
debian/patches/gcc-linaro-no-macros.diff | 2 +-
debian/patches/gcc-linaro.diff | 1905 ++++++++++++++++++++++--------
4 files changed, 1501 insertions(+), 505 deletions(-)
diff --git a/debian/changelog b/debian/changelog
index 0adc7f7..c48fd3d 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,9 @@
+gcc-6 (6.3.0-10) UNRELEASED; urgency=medium
+
+ * Update the Linaro support to the 6.3-2017.03 snapshot.
+
+ -- Matthias Klose <doko at debian.org> Fri, 17 Mar 2017 16:20:18 +0100
+
gcc-6 (6.3.0-9) unstable; urgency=medium
* Update to SVN 20170316 (r246188) from the gcc-6-branch.
diff --git a/debian/patches/gcc-linaro-doc.diff b/debian/patches/gcc-linaro-doc.diff
index 6ee9e58..45e8750 100644
--- a/debian/patches/gcc-linaro-doc.diff
+++ b/debian/patches/gcc-linaro-doc.diff
@@ -1,4 +1,4 @@
-# DP: Changes for the Linaro 6-2017.02 release (documentation).
+# DP: Changes for the Linaro 6-2017.03 release (documentation).
--- a/src/gcc/doc/cpp.texi
+++ b/src/gcc/doc/cpp.texi
@@ -168,7 +168,15 @@
-march=@var{name} -mcpu=@var{name} -mtune=@var{name}}
@emph{Adapteva Epiphany Options}
-@@ -632,7 +634,8 @@ Objective-C and Objective-C++ Dialects}.
+@@ -606,7 +608,6 @@ Objective-C and Objective-C++ Dialects}.
+ @gccoptlist{-mapcs-frame -mno-apcs-frame @gol
+ -mabi=@var{name} @gol
+ -mapcs-stack-check -mno-apcs-stack-check @gol
+--mapcs-float -mno-apcs-float @gol
+ -mapcs-reentrant -mno-apcs-reentrant @gol
+ -msched-prolog -mno-sched-prolog @gol
+ -mlittle-endian -mbig-endian @gol
+@@ -632,7 +633,8 @@ Objective-C and Objective-C++ Dialects}.
-mneon-for-64bits @gol
-mslow-flash-data @gol
-masm-syntax-unified @gol
@@ -178,7 +186,7 @@
@emph{AVR Options}
@gccoptlist{-mmcu=@var{mcu} -maccumulate-args -mbranch-cost=@var{cost} @gol
-@@ -9477,6 +9480,11 @@ Size of minimal partition for WHOPR (in estimated instructions).
+@@ -9477,6 +9479,11 @@ Size of minimal partition for WHOPR (in estimated instructions).
This prevents expenses of splitting very small programs into too many
partitions.
@@ -190,7 +198,7 @@
@item cxx-max-namespaces-for-diagnostic-help
The maximum number of namespaces to consult for suggestions when C++
name lookup fails for an identifier. The default is 1000.
-@@ -12827,9 +12835,9 @@ These options are defined for AArch64 implementations:
+@@ -12827,9 +12834,9 @@ These options are defined for AArch64 implementations:
@item -mabi=@var{name}
@opindex mabi
Generate code for the specified data model. Permissible values
@@ -203,7 +211,7 @@
The default depends on the specific target configuration. Note that
the LP64 and ILP32 ABIs are not link-compatible; you must compile your
-@@ -12854,25 +12862,24 @@ Generate little-endian code. This is the default when GCC is configured for an
+@@ -12854,25 +12861,24 @@ Generate little-endian code. This is the default when GCC is configured for an
@item -mcmodel=tiny
@opindex mcmodel=tiny
Generate code for the tiny code model. The program and its statically defined
@@ -236,7 +244,7 @@
@item -momit-leaf-frame-pointer
@itemx -mno-omit-leaf-frame-pointer
-@@ -12894,7 +12901,7 @@ of TLS variables.
+@@ -12894,7 +12900,7 @@ of TLS variables.
@item -mtls-size=@var{size}
@opindex mtls-size
Specify bit size of immediate TLS offsets. Valid values are 12, 24, 32, 48.
@@ -245,7 +253,7 @@
@item -mfix-cortex-a53-835769
@itemx -mno-fix-cortex-a53-835769
-@@ -12914,12 +12921,34 @@ corresponding flag to the linker.
+@@ -12914,12 +12920,34 @@ corresponding flag to the linker.
@item -mlow-precision-recip-sqrt
@item -mno-low-precision-recip-sqrt
@@ -286,12 +294,15 @@
@item -march=@var{name}
@opindex march
-@@ -12928,10 +12957,13 @@ more feature modifiers. This option has the form
+@@ -12928,10 +12956,16 @@ more feature modifiers. This option has the form
@option{-march=@var{arch}@r{@{}+ at r{[}no at r{]}@var{feature}@r{@}*}}.
The permissible values for @var{arch} are @samp{armv8-a},
- at samp{armv8.1-a} or @var{native}.
-+ at samp{armv8.1-a}, @samp{armv8.2-a} or @var{native}.
++ at samp{armv8.1-a}, @samp{armv8.2-a}, @samp{armv8.3-a} or @var{native}.
++
++The value @samp{armv8.3-a} implies @samp{armv8.2-a} and enables compiler
++support for the ARMv8.3-A architecture extensions.
+
+The value @samp{armv8.2-a} implies @samp{armv8.1-a} and enables compiler
+support for the ARMv8.2-A architecture extensions.
@@ -302,7 +313,7 @@
enables the @samp{+crc} and @samp{+lse} features.
The value @samp{native} is available on native AArch64 GNU/Linux and
-@@ -12955,18 +12987,18 @@ processors implementing the target architecture.
+@@ -12955,18 +12989,18 @@ processors implementing the target architecture.
Specify the name of the target processor for which GCC should tune the
performance of the code. Permissible values for this option are:
@samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57},
@@ -330,7 +341,7 @@
Where none of @option{-mtune=}, @option{-mcpu=} or @option{-march=}
are specified, the code is tuned to perform well across a range
-@@ -12986,12 +13018,6 @@ documented in the sub-section on
+@@ -12986,12 +13020,6 @@ documented in the sub-section on
Feature Modifiers}. Where conflicting feature modifiers are
specified, the right-most feature is used.
@@ -343,7 +354,7 @@
GCC uses @var{name} to determine what kind of instructions it can emit when
generating assembly code (as if by @option{-march}) and to determine
the target processor for which to tune for performance (as if
-@@ -13009,11 +13035,11 @@ across releases.
+@@ -13009,11 +13037,11 @@ across releases.
This option is only intended to be useful when developing GCC.
@item -mpc-relative-literal-loads
@@ -360,7 +371,7 @@
@end table
-@@ -13041,12 +13067,14 @@ instructions. This is on by default for all possible values for options
+@@ -13041,12 +13069,14 @@ instructions. This is on by default for all possible values for options
@item lse
Enable Large System Extension instructions. This is on by default for
@option{-march=armv8.1-a}.
@@ -378,7 +389,24 @@
@node Adapteva Epiphany Options
@subsection Adapteva Epiphany Options
-@@ -13966,21 +13994,42 @@ name to determine what kind of instructions it can emit when generating
+@@ -13897,16 +13927,6 @@ system is required to provide these functions. The default is
+ @option{-mno-apcs-stack-check}, since this produces smaller code.
+
+ @c not currently implemented
+- at item -mapcs-float
+- at opindex mapcs-float
+-Pass floating-point arguments using the floating-point registers. This is
+-one of the variants of the APCS at . This option is recommended if the
+-target hardware has a floating-point unit or if a lot of floating-point
+-arithmetic is going to be performed by the code. The default is
+- at option{-mno-apcs-float}, since the size of integer-only code is
+-slightly increased if @option{-mapcs-float} is used.
+-
+- at c not currently implemented
+ @item -mapcs-reentrant
+ @opindex mapcs-reentrant
+ Generate reentrant, position-independent code. The default is
+@@ -13966,21 +13986,42 @@ name to determine what kind of instructions it can emit when generating
assembly code. This option can be used in conjunction with or instead
of the @option{-mcpu=} option. Permissible names are: @samp{armv2},
@samp{armv2a}, @samp{armv3}, @samp{armv3m}, @samp{armv4}, @samp{armv4t},
@@ -395,14 +423,14 @@
- at samp{armv8.1-a+crc}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
+ at samp{armv8.1-a+crc}, @samp{armv8-m.base}, @samp{armv8-m.main},
+ at samp{armv8-m.main+dsp}, @samp{iwmmxt}, @samp{iwmmxt2}.
-+
-+Architecture revisions older than @samp{armv4t} are deprecated.
-Architecture revisions older than @option{armv4t} are deprecated.
-+ at option{-march=armv6s-m} is the @samp{armv6-m} architecture with support for
-+the (now mandatory) SVC instruction.
++Architecture revisions older than @samp{armv4t} are deprecated.
- at option{-march=armv7ve} is the armv7-a architecture with virtualization
++ at option{-march=armv6s-m} is the @samp{armv6-m} architecture with support for
++the (now mandatory) SVC instruction.
++
+ at option{-march=armv6zk} is an alias for @samp{armv6kz}, existing for backwards
+compatibility.
+
@@ -428,7 +456,7 @@
@option{-march=native} causes the compiler to auto-detect the architecture
of the build computer. At present, this feature is only supported on
GNU/Linux, and not all architectures are recognized. If the auto-detect
-@@ -14012,8 +14061,10 @@ Permissible names are: @samp{arm2}, @samp{arm250},
+@@ -14012,8 +14053,10 @@ Permissible names are: @samp{arm2}, @samp{arm250},
@samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8},
@samp{cortex-a9}, @samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a17},
@samp{cortex-a32}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57},
@@ -440,7 +468,7 @@
@samp{cortex-m7},
@samp{cortex-m4},
@samp{cortex-m3},
-@@ -14034,7 +14085,8 @@ Permissible names are: @samp{arm2}, @samp{arm250},
+@@ -14034,7 +14077,8 @@ Permissible names are: @samp{arm2}, @samp{arm250},
Additionally, this option can specify that GCC should tune the performance
of the code for a big.LITTLE system. Permissible names are:
@samp{cortex-a15.cortex-a7}, @samp{cortex-a17.cortex-a7},
@@ -450,7 +478,24 @@
@option{-mtune=generic- at var{arch}} specifies that GCC should tune the
performance for a blend of processors within architecture @var{arch}.
-@@ -14164,9 +14216,12 @@ otherwise the default is @samp{R10}.
+@@ -14072,12 +14116,14 @@ is unsuccessful the option has no effect.
+ @item -mfpu=@var{name}
+ @opindex mfpu
+ This specifies what floating-point hardware (or hardware emulation) is
+-available on the target. Permissible names are: @samp{vfp}, @samp{vfpv3},
++available on the target. Permissible names are: @samp{vfpv2}, @samp{vfpv3},
+ @samp{vfpv3-fp16}, @samp{vfpv3-d16}, @samp{vfpv3-d16-fp16}, @samp{vfpv3xd},
+- at samp{vfpv3xd-fp16}, @samp{neon}, @samp{neon-fp16}, @samp{vfpv4},
++ at samp{vfpv3xd-fp16}, @samp{neon-vfpv3}, @samp{neon-fp16}, @samp{vfpv4},
+ @samp{vfpv4-d16}, @samp{fpv4-sp-d16}, @samp{neon-vfpv4},
+ @samp{fpv5-d16}, @samp{fpv5-sp-d16},
+ @samp{fp-armv8}, @samp{neon-fp-armv8} and @samp{crypto-neon-fp-armv8}.
++Note that @samp{neon} is an alias for @samp{neon-vfpv3} and @samp{vfp}
++is an alias for @samp{vfpv2}.
+
+ If @option{-msoft-float} is specified this specifies the format of
+ floating-point values.
+@@ -14164,9 +14210,12 @@ otherwise the default is @samp{R10}.
@item -mpic-data-is-text-relative
@opindex mpic-data-is-text-relative
@@ -466,7 +511,7 @@
@item -mpoke-function-name
@opindex mpoke-function-name
-@@ -14276,10 +14331,10 @@ generating these instructions. This option is enabled by default when
+@@ -14276,10 +14325,10 @@ generating these instructions. This option is enabled by default when
@opindex mno-unaligned-access
Enables (or disables) reading and writing of 16- and 32- bit values
from addresses that are not 16- or 32- bit aligned. By default
@@ -481,7 +526,7 @@
The ARM attribute @code{Tag_CPU_unaligned_access} is set in the
generated object file to either true or false, depending upon the
-@@ -14319,6 +14374,12 @@ Print CPU tuning information as comment in assembler file. This is
+@@ -14319,6 +14368,12 @@ Print CPU tuning information as comment in assembler file. This is
an option used only for regression testing of the compiler and not
intended for ordinary use in compiling code. This option is disabled
by default.
@@ -494,7 +539,7 @@
@end table
@node AVR Options
-@@ -18081,7 +18142,7 @@ IEEE 754 floating-point data.
+@@ -18081,7 +18136,7 @@ IEEE 754 floating-point data.
The @option{-mnan=legacy} option selects the legacy encoding. In this
case quiet NaNs (qNaNs) are denoted by the first bit of their trailing
diff --git a/debian/patches/gcc-linaro-no-macros.diff b/debian/patches/gcc-linaro-no-macros.diff
index 856e9d9..3c09ada 100644
--- a/debian/patches/gcc-linaro-no-macros.diff
+++ b/debian/patches/gcc-linaro-no-macros.diff
@@ -89,7 +89,7 @@ Index: b/src/gcc/LINARO-VERSION
--- a/src/gcc/LINARO-VERSION
+++ /dev/null
@@ -1,1 +0,0 @@
--6.3-2017.02~dev
+-Snapshot 6.3-2017.03
Index: b/src/gcc/configure.ac
===================================================================
--- a/src/gcc/configure.ac
diff --git a/debian/patches/gcc-linaro.diff b/debian/patches/gcc-linaro.diff
index 10dc0ff..c2e8235 100644
--- a/debian/patches/gcc-linaro.diff
+++ b/debian/patches/gcc-linaro.diff
@@ -1,8 +1,8 @@
-# DP: Changes for the Linaro 6-2017.02 release.
+# DP: Changes for the Linaro 6-2017.03 release.
MSG=$(git log origin/linaro/gcc-6-branch --format=format:"%s" -n 1 --grep "Merge branches"); SVN=${MSG##* }; git log origin/gcc-6-branch --format=format:"%H" -n 1 --grep "gcc-6-branch@${SVN%.}"
-LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02179d21167c43b18b31b3e8008dae1ed \
+LANG=C git diff --no-renames 4b7882c54dabbb54686cb577f2a2cf28e93e743b..630c5507bb37d2caaef60a6f0773e4c820d76fe0 \
| egrep -v '^(diff|index) ' \
| filterdiff --strip=1 --addoldprefix=a/src/ --addnewprefix=b/src/ \
| sed 's,a/src//dev/null,/dev/null,'
@@ -110,7 +110,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
--- /dev/null
+++ b/src/gcc/LINARO-VERSION
@@ -0,0 +1 @@
-+6.3-2017.02~dev
++Snapshot 6.3-2017.03
--- a/src/gcc/Makefile.in
+++ b/src/gcc/Makefile.in
@@ -832,10 +832,12 @@ BASEVER := $(srcdir)/BASE-VER # 4.x.y
@@ -228,10 +228,30 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
delete original_copy_bb_pool;
--- a/src/gcc/common/config/arm/arm-common.c
+++ b/src/gcc/common/config/arm/arm-common.c
-@@ -97,6 +97,29 @@ arm_rewrite_mcpu (int argc, const char **argv)
+@@ -97,6 +97,49 @@ arm_rewrite_mcpu (int argc, const char **argv)
return arm_rewrite_selected_cpu (argv[argc - 1]);
}
++struct arm_arch_core_flag
++{
++ const char *const name;
++ const arm_feature_set flags;
++};
++
++static const struct arm_arch_core_flag arm_arch_core_flags[] =
++{
++#undef ARM_CORE
++#define ARM_CORE(NAME, X, IDENT, ARCH, FLAGS, COSTS) \
++ {NAME, FLAGS},
++#include "config/arm/arm-cores.def"
++#undef ARM_CORE
++#undef ARM_ARCH
++#define ARM_ARCH(NAME, CORE, ARCH, FLAGS) \
++ {NAME, FLAGS},
++#include "config/arm/arm-arches.def"
++#undef ARM_ARCH
++};
++
+/* Called by the driver to check whether the target denoted by current
+ command line options is a Thumb-only target. ARGV is an array of
+ -march and -mcpu values (ie. it contains the rhs after the equal
@@ -376,11 +396,12 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
--- a/src/gcc/config/aarch64/aarch64-arches.def
+++ b/src/gcc/config/aarch64/aarch64-arches.def
-@@ -32,4 +32,5 @@
+@@ -32,4 +32,6 @@
AARCH64_ARCH("armv8-a", generic, 8A, 8, AARCH64_FL_FOR_ARCH8)
AARCH64_ARCH("armv8.1-a", generic, 8_1A, 8, AARCH64_FL_FOR_ARCH8_1)
+AARCH64_ARCH("armv8.2-a", generic, 8_2A, 8, AARCH64_FL_FOR_ARCH8_2)
++AARCH64_ARCH("armv8.3-a", generic, 8_3A, 8, AARCH64_FL_FOR_ARCH8_3)
--- a/src/gcc/config/aarch64/aarch64-builtins.c
+++ b/src/gcc/config/aarch64/aarch64-builtins.c
@@ -705,6 +726,30 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
+/* Enabling "fp16" also enables "fp".
+ Disabling "fp16" just disables "fp16". */
+AARCH64_OPT_EXTENSION("fp16", AARCH64_FL_F16, AARCH64_FL_FP, 0, "fp16")
+--- /dev/null
++++ b/src/gcc/config/aarch64/aarch64-passes.def
+@@ -0,0 +1,21 @@
++/* AArch64-specific passes declarations.
++ Copyright (C) 2016 Free Software Foundation, Inc.
++ Contributed by ARM Ltd.
++
++ This file is part of GCC.
++
++ GCC is free software; you can redistribute it and/or modify it
++ under the terms of the GNU General Public License as published by
++ the Free Software Foundation; either version 3, or (at your option)
++ any later version.
++
++ GCC is distributed in the hope that it will be useful, but
++ WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with GCC; see the file COPYING3. If not see
++ <http://www.gnu.org/licenses/>. */
++
++INSERT_PASS_AFTER (pass_regrename, 1, pass_fma_steering);
--- a/src/gcc/config/aarch64/aarch64-protos.h
+++ b/src/gcc/config/aarch64/aarch64-protos.h
@@ -178,6 +178,25 @@ struct cpu_branch_cost
@@ -767,7 +812,15 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
bool aarch64_modes_tieable_p (machine_mode mode1,
machine_mode mode2);
bool aarch64_zero_extend_const_eq (machine_mode, rtx, machine_mode, rtx);
-@@ -335,11 +356,9 @@ machine_mode aarch64_hard_regno_caller_save_mode (unsigned, unsigned,
+@@ -320,6 +341,7 @@ bool aarch64_simd_scalar_immediate_valid_for_move (rtx, machine_mode);
+ bool aarch64_simd_shift_imm_p (rtx, machine_mode, bool);
+ bool aarch64_simd_valid_immediate (rtx, machine_mode, bool,
+ struct simd_immediate_info *);
++bool aarch64_split_dimode_const_store (rtx, rtx);
+ bool aarch64_symbolic_address_p (rtx);
+ bool aarch64_uimm12_shift (HOST_WIDE_INT);
+ bool aarch64_use_return_insn_p (void);
+@@ -335,11 +357,9 @@ machine_mode aarch64_hard_regno_caller_save_mode (unsigned, unsigned,
machine_mode);
int aarch64_hard_regno_mode_ok (unsigned, machine_mode);
int aarch64_hard_regno_nregs (unsigned, machine_mode);
@@ -779,7 +832,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
rtx aarch64_mask_from_zextract_ops (rtx, rtx);
const char *aarch64_output_move_struct (rtx *operands);
rtx aarch64_return_addr (int, rtx);
-@@ -352,7 +371,6 @@ unsigned aarch64_dbx_register_number (unsigned);
+@@ -352,7 +372,6 @@ unsigned aarch64_dbx_register_number (unsigned);
unsigned aarch64_trampoline_size (void);
void aarch64_asm_output_labelref (FILE *, const char *);
void aarch64_cpu_cpp_builtins (cpp_reader *);
@@ -787,7 +840,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
const char * aarch64_gen_far_branch (rtx *, int, const char *, const char *);
const char * aarch64_output_probe_stack_range (rtx, rtx);
void aarch64_err_no_fpadvsimd (machine_mode, const char *);
-@@ -369,7 +387,6 @@ void aarch64_register_pragmas (void);
+@@ -369,7 +388,6 @@ void aarch64_register_pragmas (void);
void aarch64_relayout_simd_types (void);
void aarch64_reset_previous_fndecl (void);
void aarch64_save_restore_target_globals (tree);
@@ -795,7 +848,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* Initialize builtins for SIMD intrinsics. */
void init_aarch64_simd_builtins (void);
-@@ -436,7 +453,6 @@ int aarch64_ccmp_mode_to_code (enum machine_mode mode);
+@@ -436,7 +454,6 @@ int aarch64_ccmp_mode_to_code (enum machine_mode mode);
bool extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset);
bool aarch64_operands_ok_for_ldpstp (rtx *, bool, enum machine_mode);
bool aarch64_operands_adjust_ok_for_ldpstp (rtx *, bool, enum machine_mode);
@@ -803,6 +856,13 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
extern void aarch64_asm_output_pool_epilogue (FILE *, const char *,
tree, HOST_WIDE_INT);
+@@ -450,4 +467,6 @@ enum aarch64_parse_opt_result aarch64_parse_extension (const char *,
+ std::string aarch64_get_extension_string_for_isa_flags (unsigned long,
+ unsigned long);
+
++rtl_opt_pass *make_pass_fma_steering (gcc::context *ctxt);
++
+ #endif /* GCC_AARCH64_PROTOS_H */
--- a/src/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/src/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -40,9 +40,10 @@
@@ -2424,7 +2484,26 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
#include "gimple.h"
#include "cfghooks.h"
#include "cfgloop.h"
-@@ -152,7 +153,7 @@ enum aarch64_processor aarch64_tune = cortexa53;
+@@ -61,7 +62,6 @@
+ #include "rtl-iter.h"
+ #include "tm-constrs.h"
+ #include "sched-int.h"
+-#include "cortex-a57-fma-steering.h"
+ #include "target-globals.h"
+ #include "common/common-target.h"
+
+@@ -141,6 +141,10 @@ static bool aarch64_vector_mode_supported_p (machine_mode);
+ static bool aarch64_vectorize_vec_perm_const_ok (machine_mode vmode,
+ const unsigned char *sel);
+ static int aarch64_address_cost (rtx, machine_mode, addr_space_t, bool);
++static bool aarch64_builtin_support_vector_misalignment (machine_mode mode,
++ const_tree type,
++ int misalignment,
++ bool is_packed);
+
+ /* Major revision number of the ARM Architecture implemented by the target. */
+ unsigned aarch64_architecture_version;
+@@ -152,7 +156,7 @@ enum aarch64_processor aarch64_tune = cortexa53;
unsigned long aarch64_tune_flags = 0;
/* Global flag for PC relative loads. */
@@ -2433,7 +2512,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* Support for command line parsing of boolean flags in the tuning
structures. */
-@@ -250,6 +251,38 @@ static const struct cpu_addrcost_table xgene1_addrcost_table =
+@@ -250,6 +254,38 @@ static const struct cpu_addrcost_table xgene1_addrcost_table =
0, /* imm_offset */
};
@@ -2472,7 +2551,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
static const struct cpu_regmove_cost generic_regmove_cost =
{
1, /* GP2GP */
-@@ -308,6 +341,24 @@ static const struct cpu_regmove_cost xgene1_regmove_cost =
+@@ -308,6 +344,24 @@ static const struct cpu_regmove_cost xgene1_regmove_cost =
2 /* FP2FP */
};
@@ -2497,7 +2576,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* Generic costs for vector insn classes. */
static const struct cpu_vector_cost generic_vector_cost =
{
-@@ -326,18 +377,36 @@ static const struct cpu_vector_cost generic_vector_cost =
+@@ -326,18 +380,36 @@ static const struct cpu_vector_cost generic_vector_cost =
1 /* cond_not_taken_branch_cost */
};
@@ -2537,7 +2616,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
1, /* vec_unalign_store_cost */
1, /* vec_store_cost */
1, /* cond_taken_branch_cost */
-@@ -379,6 +448,24 @@ static const struct cpu_vector_cost xgene1_vector_cost =
+@@ -379,6 +451,24 @@ static const struct cpu_vector_cost xgene1_vector_cost =
1 /* cond_not_taken_branch_cost */
};
@@ -2562,7 +2641,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* Generic costs for branch instructions. */
static const struct cpu_branch_cost generic_branch_cost =
{
-@@ -393,6 +480,37 @@ static const struct cpu_branch_cost cortexa57_branch_cost =
+@@ -393,6 +483,37 @@ static const struct cpu_branch_cost cortexa57_branch_cost =
3 /* Unpredictable. */
};
@@ -2600,7 +2679,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
static const struct tune_params generic_tunings =
{
&cortexa57_extra_costs,
-@@ -400,6 +518,7 @@ static const struct tune_params generic_tunings =
+@@ -400,6 +521,7 @@ static const struct tune_params generic_tunings =
&generic_regmove_cost,
&generic_vector_cost,
&generic_branch_cost,
@@ -2608,7 +2687,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
4, /* memmov_cost */
2, /* issue_rate */
AARCH64_FUSE_NOTHING, /* fusible_ops */
-@@ -423,14 +542,15 @@ static const struct tune_params cortexa35_tunings =
+@@ -423,14 +545,15 @@ static const struct tune_params cortexa35_tunings =
&generic_addrcost_table,
&cortexa53_regmove_cost,
&generic_vector_cost,
@@ -2628,7 +2707,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
2, /* int_reassoc_width. */
4, /* fp_reassoc_width. */
1, /* vec_reassoc_width. */
-@@ -448,14 +568,15 @@ static const struct tune_params cortexa53_tunings =
+@@ -448,14 +571,15 @@ static const struct tune_params cortexa53_tunings =
&generic_addrcost_table,
&cortexa53_regmove_cost,
&generic_vector_cost,
@@ -2647,7 +2726,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
2, /* int_reassoc_width. */
4, /* fp_reassoc_width. */
1, /* vec_reassoc_width. */
-@@ -474,13 +595,14 @@ static const struct tune_params cortexa57_tunings =
+@@ -474,13 +598,14 @@ static const struct tune_params cortexa57_tunings =
&cortexa57_regmove_cost,
&cortexa57_vector_cost,
&cortexa57_branch_cost,
@@ -2663,7 +2742,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
2, /* int_reassoc_width. */
4, /* fp_reassoc_width. */
1, /* vec_reassoc_width. */
-@@ -498,14 +620,15 @@ static const struct tune_params cortexa72_tunings =
+@@ -498,14 +623,15 @@ static const struct tune_params cortexa72_tunings =
&cortexa57_addrcost_table,
&cortexa57_regmove_cost,
&cortexa57_vector_cost,
@@ -2681,7 +2760,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
2, /* int_reassoc_width. */
4, /* fp_reassoc_width. */
1, /* vec_reassoc_width. */
-@@ -513,7 +636,33 @@ static const struct tune_params cortexa72_tunings =
+@@ -513,7 +639,33 @@ static const struct tune_params cortexa72_tunings =
2, /* min_div_recip_mul_df. */
0, /* max_case_values. */
0, /* cache_line_size. */
@@ -2716,7 +2795,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
(AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */
};
-@@ -524,6 +673,7 @@ static const struct tune_params exynosm1_tunings =
+@@ -524,6 +676,7 @@ static const struct tune_params exynosm1_tunings =
&exynosm1_regmove_cost,
&exynosm1_vector_cost,
&generic_branch_cost,
@@ -2724,7 +2803,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
4, /* memmov_cost */
3, /* issue_rate */
(AARCH64_FUSE_AES_AESMC), /* fusible_ops */
-@@ -538,7 +688,7 @@ static const struct tune_params exynosm1_tunings =
+@@ -538,7 +691,7 @@ static const struct tune_params exynosm1_tunings =
48, /* max_case_values. */
64, /* cache_line_size. */
tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */
@@ -2733,7 +2812,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
};
static const struct tune_params thunderx_tunings =
-@@ -546,8 +696,9 @@ static const struct tune_params thunderx_tunings =
+@@ -546,8 +699,9 @@ static const struct tune_params thunderx_tunings =
&thunderx_extra_costs,
&generic_addrcost_table,
&thunderx_regmove_cost,
@@ -2744,7 +2823,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
6, /* memmov_cost */
2, /* issue_rate */
AARCH64_FUSE_CMP_BRANCH, /* fusible_ops */
-@@ -562,7 +713,7 @@ static const struct tune_params thunderx_tunings =
+@@ -562,7 +716,7 @@ static const struct tune_params thunderx_tunings =
0, /* max_case_values. */
0, /* cache_line_size. */
tune_params::AUTOPREFETCHER_OFF, /* autoprefetcher_model. */
@@ -2753,7 +2832,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
};
static const struct tune_params xgene1_tunings =
-@@ -572,6 +723,7 @@ static const struct tune_params xgene1_tunings =
+@@ -572,6 +726,7 @@ static const struct tune_params xgene1_tunings =
&xgene1_regmove_cost,
&xgene1_vector_cost,
&generic_branch_cost,
@@ -2761,7 +2840,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
6, /* memmov_cost */
4, /* issue_rate */
AARCH64_FUSE_NOTHING, /* fusible_ops */
-@@ -586,7 +738,58 @@ static const struct tune_params xgene1_tunings =
+@@ -586,7 +741,58 @@ static const struct tune_params xgene1_tunings =
0, /* max_case_values. */
0, /* cache_line_size. */
tune_params::AUTOPREFETCHER_OFF, /* autoprefetcher_model. */
@@ -2821,7 +2900,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
};
/* Support for fine-grained override of the tuning structures. */
-@@ -663,16 +866,6 @@ struct aarch64_option_extension
+@@ -663,16 +869,6 @@ struct aarch64_option_extension
const unsigned long flags_off;
};
@@ -2838,7 +2917,34 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
typedef enum aarch64_cond_code
{
AARCH64_EQ = 0, AARCH64_NE, AARCH64_CS, AARCH64_CC, AARCH64_MI, AARCH64_PL,
-@@ -1703,7 +1896,7 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm)
+@@ -1110,7 +1306,8 @@ aarch64_load_symref_appropriately (rtx dest, rtx imm,
+ emit_move_insn (gp_rtx, gen_rtx_HIGH (Pmode, s));
+
+ if (mode != GET_MODE (gp_rtx))
+- gp_rtx = simplify_gen_subreg (mode, gp_rtx, GET_MODE (gp_rtx), 0);
++ gp_rtx = gen_lowpart (mode, gp_rtx);
++
+ }
+
+ if (mode == ptr_mode)
+@@ -1186,10 +1383,14 @@ aarch64_load_symref_appropriately (rtx dest, rtx imm,
+ case SYMBOL_SMALL_TLSGD:
+ {
+ rtx_insn *insns;
+- rtx result = gen_rtx_REG (Pmode, R0_REGNUM);
++ machine_mode mode = GET_MODE (dest);
++ rtx result = gen_rtx_REG (mode, R0_REGNUM);
+
+ start_sequence ();
+- aarch64_emit_call_insn (gen_tlsgd_small (result, imm));
++ if (TARGET_ILP32)
++ aarch64_emit_call_insn (gen_tlsgd_small_si (result, imm));
++ else
++ aarch64_emit_call_insn (gen_tlsgd_small_di (result, imm));
+ insns = get_insns ();
+ end_sequence ();
+
+@@ -1703,7 +1904,7 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm)
we need to expand the literal pool access carefully.
This is something that needs to be done in a number
of places, so could well live as a separate function. */
@@ -2847,7 +2953,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
{
gcc_assert (can_create_pseudo_p ());
base = gen_reg_rtx (ptr_mode);
-@@ -1766,6 +1959,88 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm)
+@@ -1766,6 +1967,88 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm)
aarch64_internal_mov_immediate (dest, imm, true, GET_MODE (dest));
}
@@ -2936,7 +3042,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
static bool
aarch64_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
tree exp ATTRIBUTE_UNUSED)
-@@ -2494,7 +2769,7 @@ static void
+@@ -2494,7 +2777,7 @@ static void
aarch64_layout_frame (void)
{
HOST_WIDE_INT offset = 0;
@@ -2945,7 +3051,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
if (reload_completed && cfun->machine->frame.laid_out)
return;
-@@ -2502,8 +2777,8 @@ aarch64_layout_frame (void)
+@@ -2502,8 +2785,8 @@ aarch64_layout_frame (void)
#define SLOT_NOT_REQUIRED (-2)
#define SLOT_REQUIRED (-1)
@@ -2956,7 +3062,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* First mark all the registers that really need to be saved... */
for (regno = R0_REGNUM; regno <= R30_REGNUM; regno++)
-@@ -2528,7 +2803,10 @@ aarch64_layout_frame (void)
+@@ -2528,7 +2811,10 @@ aarch64_layout_frame (void)
for (regno = V0_REGNUM; regno <= V31_REGNUM; regno++)
if (df_regs_ever_live_p (regno)
&& !call_used_regs[regno])
@@ -2968,7 +3074,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
if (frame_pointer_needed)
{
-@@ -2537,7 +2815,6 @@ aarch64_layout_frame (void)
+@@ -2537,7 +2823,6 @@ aarch64_layout_frame (void)
cfun->machine->frame.wb_candidate1 = R29_REGNUM;
cfun->machine->frame.reg_offset[R30_REGNUM] = UNITS_PER_WORD;
cfun->machine->frame.wb_candidate2 = R30_REGNUM;
@@ -2976,7 +3082,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
offset += 2 * UNITS_PER_WORD;
}
-@@ -2546,35 +2823,46 @@ aarch64_layout_frame (void)
+@@ -2546,35 +2831,46 @@ aarch64_layout_frame (void)
if (cfun->machine->frame.reg_offset[regno] == SLOT_REQUIRED)
{
cfun->machine->frame.reg_offset[regno] = offset;
@@ -3032,7 +3138,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
STACK_BOUNDARY / BITS_PER_UNIT);
cfun->machine->frame.frame_size
-@@ -2582,15 +2870,92 @@ aarch64_layout_frame (void)
+@@ -2582,15 +2878,92 @@ aarch64_layout_frame (void)
+ crtl->outgoing_args_size,
STACK_BOUNDARY / BITS_PER_UNIT);
@@ -3125,7 +3231,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
static unsigned
aarch64_next_callee_save (unsigned regno, unsigned limit)
{
-@@ -2599,6 +2964,9 @@ aarch64_next_callee_save (unsigned regno, unsigned limit)
+@@ -2599,6 +2972,9 @@ aarch64_next_callee_save (unsigned regno, unsigned limit)
return regno;
}
@@ -3135,7 +3241,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
static void
aarch64_pushwb_single_reg (machine_mode mode, unsigned regno,
HOST_WIDE_INT adjustment)
-@@ -2615,6 +2983,10 @@ aarch64_pushwb_single_reg (machine_mode mode, unsigned regno,
+@@ -2615,6 +2991,10 @@ aarch64_pushwb_single_reg (machine_mode mode, unsigned regno,
RTX_FRAME_RELATED_P (insn) = 1;
}
@@ -3146,7 +3252,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
static rtx
aarch64_gen_storewb_pair (machine_mode mode, rtx base, rtx reg, rtx reg2,
HOST_WIDE_INT adjustment)
-@@ -2634,11 +3006,18 @@ aarch64_gen_storewb_pair (machine_mode mode, rtx base, rtx reg, rtx reg2,
+@@ -2634,11 +3014,18 @@ aarch64_gen_storewb_pair (machine_mode mode, rtx base, rtx reg, rtx reg2,
}
}
@@ -3167,7 +3273,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
rtx reg1 = gen_rtx_REG (mode, regno1);
rtx reg2 = gen_rtx_REG (mode, regno2);
-@@ -2649,6 +3028,9 @@ aarch64_pushwb_pair_reg (machine_mode mode, unsigned regno1,
+@@ -2649,6 +3036,9 @@ aarch64_pushwb_pair_reg (machine_mode mode, unsigned regno1,
RTX_FRAME_RELATED_P (insn) = 1;
}
@@ -3177,7 +3283,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
static rtx
aarch64_gen_loadwb_pair (machine_mode mode, rtx base, rtx reg, rtx reg2,
HOST_WIDE_INT adjustment)
-@@ -2666,6 +3048,37 @@ aarch64_gen_loadwb_pair (machine_mode mode, rtx base, rtx reg, rtx reg2,
+@@ -2666,6 +3056,37 @@ aarch64_gen_loadwb_pair (machine_mode mode, rtx base, rtx reg, rtx reg2,
}
}
@@ -3215,7 +3321,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
static rtx
aarch64_gen_store_pair (machine_mode mode, rtx mem1, rtx reg1, rtx mem2,
rtx reg2)
-@@ -2683,6 +3096,9 @@ aarch64_gen_store_pair (machine_mode mode, rtx mem1, rtx reg1, rtx mem2,
+@@ -2683,6 +3104,9 @@ aarch64_gen_store_pair (machine_mode mode, rtx mem1, rtx reg1, rtx mem2,
}
}
@@ -3225,7 +3331,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
static rtx
aarch64_gen_load_pair (machine_mode mode, rtx reg1, rtx mem1, rtx reg2,
rtx mem2)
-@@ -2700,6 +3116,9 @@ aarch64_gen_load_pair (machine_mode mode, rtx reg1, rtx mem1, rtx reg2,
+@@ -2700,6 +3124,9 @@ aarch64_gen_load_pair (machine_mode mode, rtx reg1, rtx mem1, rtx reg2,
}
}
@@ -3235,7 +3341,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
static void
aarch64_save_callee_saves (machine_mode mode, HOST_WIDE_INT start_offset,
-@@ -2758,6 +3177,11 @@ aarch64_save_callee_saves (machine_mode mode, HOST_WIDE_INT start_offset,
+@@ -2758,6 +3185,11 @@ aarch64_save_callee_saves (machine_mode mode, HOST_WIDE_INT start_offset,
}
}
@@ -3247,7 +3353,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
static void
aarch64_restore_callee_saves (machine_mode mode,
HOST_WIDE_INT start_offset, unsigned start,
-@@ -2852,23 +3276,16 @@ aarch64_restore_callee_saves (machine_mode mode,
+@@ -2852,23 +3284,16 @@ aarch64_restore_callee_saves (machine_mode mode,
void
aarch64_expand_prologue (void)
{
@@ -3279,7 +3385,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
if (flag_stack_usage_info)
current_function_static_stack_size = frame_size;
-@@ -2885,129 +3302,28 @@ aarch64_expand_prologue (void)
+@@ -2885,129 +3310,28 @@ aarch64_expand_prologue (void)
aarch64_emit_probe_stack_range (STACK_CHECK_PROTECT, frame_size);
}
@@ -3295,19 +3401,19 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
- offset = hard_fp_offset;
- if (offset >= 512)
- offset = cfun->machine->frame.saved_regs_size;
--
++ aarch64_sub_sp (IP0_REGNUM, initial_adjust, true);
+
- frame_size -= (offset + crtl->outgoing_args_size);
- fp_offset = 0;
-+ aarch64_sub_sp (IP0_REGNUM, initial_adjust, true);
++ if (callee_adjust != 0)
++ aarch64_push_regs (reg1, reg2, callee_adjust);
- if (frame_size >= 0x1000000)
- {
- rtx op0 = gen_rtx_REG (Pmode, IP0_REGNUM);
- emit_move_insn (op0, GEN_INT (-frame_size));
- insn = emit_insn (gen_add2_insn (stack_pointer_rtx, op0));
-+ if (callee_adjust != 0)
-+ aarch64_push_regs (reg1, reg2, callee_adjust);
-
+-
- add_reg_note (insn, REG_CFA_ADJUST_CFA,
- gen_rtx_SET (stack_pointer_rtx,
- plus_constant (Pmode, stack_pointer_rtx,
@@ -3337,7 +3443,8 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
- frame_size = -1;
-
- if (offset > 0)
-- {
++ if (frame_pointer_needed)
+ {
- bool skip_wb = false;
-
- if (frame_pointer_needed)
@@ -3395,8 +3502,16 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
- skip_wb);
- aarch64_save_callee_saves (DFmode, fp_offset, V0_REGNUM, V31_REGNUM,
- skip_wb);
-- }
--
++ if (callee_adjust == 0)
++ aarch64_save_callee_saves (DImode, callee_offset, R29_REGNUM,
++ R30_REGNUM, false);
++ insn = emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
++ stack_pointer_rtx,
++ GEN_INT (callee_offset)));
++ RTX_FRAME_RELATED_P (insn) = 1;
++ emit_insn (gen_stack_tie (stack_pointer_rtx, hard_frame_pointer_rtx));
+ }
+
- /* when offset >= 512,
- sub sp, sp, #<outgoing_args_size> */
- if (frame_size > -1)
@@ -3408,18 +3523,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
- GEN_INT (- crtl->outgoing_args_size)));
- RTX_FRAME_RELATED_P (insn) = 1;
- }
-+ if (frame_pointer_needed)
-+ {
-+ if (callee_adjust == 0)
-+ aarch64_save_callee_saves (DImode, callee_offset, R29_REGNUM,
-+ R30_REGNUM, false);
-+ insn = emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
-+ stack_pointer_rtx,
-+ GEN_INT (callee_offset)));
-+ RTX_FRAME_RELATED_P (insn) = 1;
-+ emit_insn (gen_stack_tie (stack_pointer_rtx, hard_frame_pointer_rtx));
- }
-+
+- }
+ aarch64_save_callee_saves (DImode, callee_offset, R0_REGNUM, R30_REGNUM,
+ callee_adjust != 0 || frame_pointer_needed);
+ aarch64_save_callee_saves (DFmode, callee_offset, V0_REGNUM, V31_REGNUM,
@@ -3428,7 +3532,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
}
/* Return TRUE if we can use a simple_return insn.
-@@ -3030,151 +3346,80 @@ aarch64_use_return_insn_p (void)
+@@ -3030,151 +3354,80 @@ aarch64_use_return_insn_p (void)
return cfun->machine->frame.frame_size == 0;
}
@@ -3510,14 +3614,8 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
hard_frame_pointer_rtx,
- GEN_INT (0)));
- offset = offset - fp_offset;
-+ GEN_INT (-callee_offset)));
-+ /* If writeback is used when restoring callee-saves, the CFA
-+ is restored on the instruction doing the writeback. */
-+ RTX_FRAME_RELATED_P (insn) = callee_adjust == 0;
- }
-+ else
-+ aarch64_add_sp (IP1_REGNUM, final_adjust, df_regs_ever_live_p (IP1_REGNUM));
-
+- }
+-
- if (offset > 0)
- {
- unsigned reg1 = cfun->machine->frame.wb_candidate1;
@@ -3545,11 +3643,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
- {
- machine_mode mode1 = (reg1 <= R30_REGNUM) ? DImode : DFmode;
- rtx rreg1 = gen_rtx_REG (mode1, reg1);
-+ aarch64_restore_callee_saves (DImode, callee_offset, R0_REGNUM, R30_REGNUM,
-+ callee_adjust != 0, &cfi_ops);
-+ aarch64_restore_callee_saves (DFmode, callee_offset, V0_REGNUM, V31_REGNUM,
-+ callee_adjust != 0, &cfi_ops);
-
+-
- cfi_ops = alloc_reg_note (REG_CFA_RESTORE, rreg1, cfi_ops);
- if (reg2 == FIRST_PSEUDO_REGISTER)
- {
@@ -3561,9 +3655,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
- else
- {
- rtx rreg2 = gen_rtx_REG (mode1, reg2);
-+ if (need_barrier_p)
-+ emit_insn (gen_stack_tie (stack_pointer_rtx, stack_pointer_rtx));
-
+-
- cfi_ops = alloc_reg_note (REG_CFA_RESTORE, rreg2, cfi_ops);
- insn = emit_insn (aarch64_gen_loadwb_pair
- (mode1, stack_pointer_rtx, rreg1,
@@ -3575,30 +3667,31 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
- insn = emit_insn (gen_add2_insn (stack_pointer_rtx,
- GEN_INT (offset)));
- }
-+ if (callee_adjust != 0)
-+ aarch64_pop_regs (reg1, reg2, callee_adjust, &cfi_ops);
-
+-
- /* Reset the CFA to be SP + FRAME_SIZE. */
- rtx new_cfa = stack_pointer_rtx;
- if (frame_size > 0)
- new_cfa = plus_constant (Pmode, new_cfa, frame_size);
- cfi_ops = alloc_reg_note (REG_CFA_DEF_CFA, new_cfa, cfi_ops);
- REG_NOTES (insn) = cfi_ops;
-+ if (callee_adjust != 0 || initial_adjust > 65536)
-+ {
-+ /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
-+ insn = get_last_insn ();
-+ rtx new_cfa = plus_constant (Pmode, stack_pointer_rtx, initial_adjust);
-+ REG_NOTES (insn) = alloc_reg_note (REG_CFA_DEF_CFA, new_cfa, cfi_ops);
- RTX_FRAME_RELATED_P (insn) = 1;
-+ cfi_ops = NULL;
+- RTX_FRAME_RELATED_P (insn) = 1;
++ GEN_INT (-callee_offset)));
++ /* If writeback is used when restoring callee-saves, the CFA
++ is restored on the instruction doing the writeback. */
++ RTX_FRAME_RELATED_P (insn) = callee_adjust == 0;
}
++ else
++ aarch64_add_sp (IP1_REGNUM, final_adjust, df_regs_ever_live_p (IP1_REGNUM));
- if (frame_size > 0)
- {
- if (need_barrier_p)
- emit_insn (gen_stack_tie (stack_pointer_rtx, stack_pointer_rtx));
--
++ aarch64_restore_callee_saves (DImode, callee_offset, R0_REGNUM, R30_REGNUM,
++ callee_adjust != 0, &cfi_ops);
++ aarch64_restore_callee_saves (DFmode, callee_offset, V0_REGNUM, V31_REGNUM,
++ callee_adjust != 0, &cfi_ops);
+
- if (frame_size >= 0x1000000)
- {
- rtx op0 = gen_rtx_REG (Pmode, IP0_REGNUM);
@@ -3609,7 +3702,9 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
- {
- int hi_ofs = frame_size & 0xfff000;
- int lo_ofs = frame_size & 0x000fff;
--
++ if (need_barrier_p)
++ emit_insn (gen_stack_tie (stack_pointer_rtx, stack_pointer_rtx));
+
- if (hi_ofs && lo_ofs)
- {
- insn = emit_insn (gen_add2_insn
@@ -3620,6 +3715,19 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
- insn = emit_insn (gen_add2_insn
- (stack_pointer_rtx, GEN_INT (frame_size)));
- }
++ if (callee_adjust != 0)
++ aarch64_pop_regs (reg1, reg2, callee_adjust, &cfi_ops);
++
++ if (callee_adjust != 0 || initial_adjust > 65536)
++ {
++ /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
++ insn = get_last_insn ();
++ rtx new_cfa = plus_constant (Pmode, stack_pointer_rtx, initial_adjust);
++ REG_NOTES (insn) = alloc_reg_note (REG_CFA_DEF_CFA, new_cfa, cfi_ops);
++ RTX_FRAME_RELATED_P (insn) = 1;
++ cfi_ops = NULL;
++ }
++
+ aarch64_add_sp (IP0_REGNUM, initial_adjust, df_regs_ever_live_p (IP0_REGNUM));
- /* Reset the CFA to be SP + 0. */
@@ -3633,7 +3741,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
RTX_FRAME_RELATED_P (insn) = 1;
}
-@@ -3230,122 +3475,6 @@ aarch64_eh_return_handler_rtx (void)
+@@ -3230,122 +3483,6 @@ aarch64_eh_return_handler_rtx (void)
return tmp;
}
@@ -3756,7 +3864,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* Output code to add DELTA to the first argument, and then jump
to FUNCTION. Used for C++ multiple inheritance. */
static void
-@@ -3366,7 +3495,7 @@ aarch64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
+@@ -3366,7 +3503,7 @@ aarch64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
emit_note (NOTE_INSN_PROLOGUE_END);
if (vcall_offset == 0)
@@ -3765,7 +3873,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
else
{
gcc_assert ((vcall_offset & (POINTER_BYTES - 1)) == 0);
-@@ -3382,7 +3511,7 @@ aarch64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
+@@ -3382,7 +3519,7 @@ aarch64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
addr = gen_rtx_PRE_MODIFY (Pmode, this_rtx,
plus_constant (Pmode, this_rtx, delta));
else
@@ -3774,7 +3882,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
}
if (Pmode == ptr_mode)
-@@ -3396,7 +3525,8 @@ aarch64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
+@@ -3396,7 +3533,8 @@ aarch64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
addr = plus_constant (Pmode, temp0, vcall_offset);
else
{
@@ -3784,7 +3892,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
addr = gen_rtx_PLUS (Pmode, temp0, temp1);
}
-@@ -3575,7 +3705,12 @@ aarch64_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
+@@ -3575,7 +3713,12 @@ aarch64_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
return aarch64_tls_referenced_p (x);
}
@@ -3798,7 +3906,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
static unsigned int
aarch64_case_values_threshold (void)
-@@ -3586,7 +3721,7 @@ aarch64_case_values_threshold (void)
+@@ -3586,7 +3729,7 @@ aarch64_case_values_threshold (void)
&& selected_cpu->tune->max_case_values != 0)
return selected_cpu->tune->max_case_values;
else
@@ -3807,7 +3915,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
}
/* Return true if register REGNO is a valid index register.
-@@ -3921,9 +4056,11 @@ aarch64_classify_address (struct aarch64_address_info *info,
+@@ -3921,9 +4064,11 @@ aarch64_classify_address (struct aarch64_address_info *info,
X,X: 7-bit signed scaled offset
Q: 9-bit signed offset
We conservatively require an offset representable in either mode.
@@ -3821,7 +3929,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
&& offset_9bit_signed_unscaled_p (mode, offset));
/* A 7bit offset check because OImode will emit a ldp/stp
-@@ -4031,7 +4168,7 @@ aarch64_classify_address (struct aarch64_address_info *info,
+@@ -4031,7 +4176,7 @@ aarch64_classify_address (struct aarch64_address_info *info,
return ((GET_CODE (sym) == LABEL_REF
|| (GET_CODE (sym) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (sym)
@@ -3830,7 +3938,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
}
return false;
-@@ -4125,6 +4262,24 @@ aarch64_legitimate_address_p (machine_mode mode, rtx x,
+@@ -4125,6 +4270,24 @@ aarch64_legitimate_address_p (machine_mode mode, rtx x,
return aarch64_classify_address (&addr, x, mode, outer_code, strict_p);
}
@@ -3855,7 +3963,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* Return TRUE if rtx X is immediate constant 0.0 */
bool
aarch64_float_const_zero_rtx_p (rtx x)
-@@ -4198,6 +4353,14 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
+@@ -4198,6 +4361,14 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
&& (GET_MODE (x) == HImode || GET_MODE (x) == QImode))
return CC_NZmode;
@@ -3870,7 +3978,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
if ((GET_MODE (x) == SImode || GET_MODE (x) == DImode)
&& y == const0_rtx
&& (code == EQ || code == NE || code == LT || code == GE)
-@@ -4225,14 +4388,6 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
+@@ -4225,14 +4396,6 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
&& GET_CODE (x) == NEG)
return CC_Zmode;
@@ -3885,7 +3993,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* A test for unsigned overflow. */
if ((GET_MODE (x) == DImode || GET_MODE (x) == TImode)
&& code == NE
-@@ -4301,8 +4456,6 @@ aarch64_get_condition_code_1 (enum machine_mode mode, enum rtx_code comp_code)
+@@ -4301,8 +4464,6 @@ aarch64_get_condition_code_1 (enum machine_mode mode, enum rtx_code comp_code)
break;
case CC_SWPmode:
@@ -3894,7 +4002,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
switch (comp_code)
{
case NE: return AARCH64_NE;
-@@ -4957,7 +5110,7 @@ aarch64_legitimize_address (rtx x, rtx /* orig_x */, machine_mode mode)
+@@ -4957,7 +5118,7 @@ aarch64_legitimize_address (rtx x, rtx /* orig_x */, machine_mode mode)
if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
{
rtx base = XEXP (x, 0);
@@ -3903,7 +4011,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
HOST_WIDE_INT offset = INTVAL (offset_rtx);
if (GET_CODE (base) == PLUS)
-@@ -5015,120 +5168,6 @@ aarch64_legitimize_address (rtx x, rtx /* orig_x */, machine_mode mode)
+@@ -5015,120 +5176,6 @@ aarch64_legitimize_address (rtx x, rtx /* orig_x */, machine_mode mode)
return x;
}
@@ -4024,7 +4132,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* Return the reload icode required for a constant pool in mode. */
static enum insn_code
aarch64_constant_pool_reload_icode (machine_mode mode)
-@@ -5186,7 +5225,7 @@ aarch64_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x,
+@@ -5186,7 +5233,7 @@ aarch64_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x,
if (MEM_P (x) && GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)
&& (SCALAR_FLOAT_MODE_P (GET_MODE (x))
|| targetm.vector_mode_supported_p (GET_MODE (x)))
@@ -4033,7 +4141,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
{
sri->icode = aarch64_constant_pool_reload_icode (mode);
return NO_REGS;
-@@ -5260,18 +5299,18 @@ aarch64_initial_elimination_offset (unsigned from, unsigned to)
+@@ -5260,18 +5307,18 @@ aarch64_initial_elimination_offset (unsigned from, unsigned to)
if (to == HARD_FRAME_POINTER_REGNUM)
{
if (from == ARG_POINTER_REGNUM)
@@ -4057,7 +4165,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
}
return cfun->machine->frame.frame_size;
-@@ -5418,7 +5457,10 @@ aarch64_elf_asm_constructor (rtx symbol, int priority)
+@@ -5418,7 +5465,10 @@ aarch64_elf_asm_constructor (rtx symbol, int priority)
else
{
section *s;
@@ -4069,7 +4177,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
snprintf (buf, sizeof (buf), ".init_array.%.5u", priority);
s = get_section (buf, SECTION_WRITE, NULL);
switch_to_section (s);
-@@ -5435,7 +5477,10 @@ aarch64_elf_asm_destructor (rtx symbol, int priority)
+@@ -5435,7 +5485,10 @@ aarch64_elf_asm_destructor (rtx symbol, int priority)
else
{
section *s;
@@ -4081,7 +4189,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
snprintf (buf, sizeof (buf), ".fini_array.%.5u", priority);
s = get_section (buf, SECTION_WRITE, NULL);
switch_to_section (s);
-@@ -5520,7 +5565,7 @@ aarch64_uxt_size (int shift, HOST_WIDE_INT mask)
+@@ -5520,7 +5573,7 @@ aarch64_uxt_size (int shift, HOST_WIDE_INT mask)
static inline bool
aarch64_can_use_per_function_literal_pools_p (void)
{
@@ -4090,7 +4198,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
|| aarch64_cmodel == AARCH64_CMODEL_LARGE);
}
-@@ -6139,6 +6184,19 @@ aarch64_extend_bitfield_pattern_p (rtx x)
+@@ -6139,6 +6192,19 @@ aarch64_extend_bitfield_pattern_p (rtx x)
return op;
}
@@ -4110,7 +4218,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* Calculate the cost of calculating X, storing it in *COST. Result
is true if the total cost of the operation has now been calculated. */
static bool
-@@ -6404,10 +6462,6 @@ aarch64_rtx_costs (rtx x, machine_mode mode, int outer ATTRIBUTE_UNUSED,
+@@ -6404,10 +6470,6 @@ aarch64_rtx_costs (rtx x, machine_mode mode, int outer ATTRIBUTE_UNUSED,
/* TODO: A write to the CC flags possibly costs extra, this
needs encoding in the cost tables. */
@@ -4121,7 +4229,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
mode = GET_MODE (op0);
/* ANDS. */
if (GET_CODE (op0) == AND)
-@@ -6717,17 +6771,31 @@ cost_plus:
+@@ -6717,17 +6779,31 @@ cost_plus:
if (GET_MODE_CLASS (mode) == MODE_INT)
{
@@ -4161,7 +4269,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
}
else
{
-@@ -6831,11 +6899,12 @@ cost_plus:
+@@ -6831,11 +6907,12 @@ cost_plus:
{
int op_cost = rtx_cost (op0, VOIDmode, ZERO_EXTEND, 0, speed);
@@ -4179,7 +4287,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
*cost = op_cost;
return true;
-@@ -6865,8 +6934,8 @@ cost_plus:
+@@ -6865,8 +6942,8 @@ cost_plus:
}
else
{
@@ -4190,7 +4298,27 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
}
}
return false;
-@@ -7445,12 +7514,12 @@ aarch64_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
+@@ -7349,7 +7426,8 @@ cost_plus:
+ break;
+ }
+
+- if (dump_file && (dump_flags & TDF_DETAILS))
++ if (dump_file
++ && flag_aarch64_verbose_cost)
+ fprintf (dump_file,
+ "\nFailed to cost RTX. Assuming default cost.\n");
+
+@@ -7365,7 +7443,8 @@ aarch64_rtx_costs_wrapper (rtx x, machine_mode mode, int outer,
+ {
+ bool result = aarch64_rtx_costs (x, mode, outer, param, cost, speed);
+
+- if (dump_file && (dump_flags & TDF_DETAILS))
++ if (dump_file
++ && flag_aarch64_verbose_cost)
+ {
+ print_rtl_single (dump_file, x);
+ fprintf (dump_file, "\n%s cost: %d (%s)\n",
+@@ -7445,12 +7524,12 @@ aarch64_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
to optimize 1.0/sqrt. */
static bool
@@ -4206,7 +4334,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
|| flag_mrecip_low_precision_sqrt));
}
-@@ -7460,89 +7529,225 @@ use_rsqrt_p (void)
+@@ -7460,89 +7539,225 @@ use_rsqrt_p (void)
static tree
aarch64_builtin_reciprocal (tree fndecl)
{
@@ -4288,13 +4416,13 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
- mode == SFmode || mode == V2SFmode || mode == V4SFmode
- || mode == DFmode || mode == V2DFmode);
+ machine_mode mode = GET_MODE (dst);
++
++ if (GET_MODE_INNER (mode) == HFmode)
++ return false;
- rtx xsrc = gen_reg_rtx (mode);
- emit_move_insn (xsrc, src);
- rtx x0 = gen_reg_rtx (mode);
-+ if (GET_MODE_INNER (mode) == HFmode)
-+ return false;
-+
+ machine_mode mmsk = mode_for_vector
+ (int_mode_for_mode (GET_MODE_INNER (mode)),
+ GET_MODE_NUNITS (mode));
@@ -4419,7 +4547,8 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
+aarch64_emit_approx_div (rtx quo, rtx num, rtx den)
+{
+ machine_mode mode = GET_MODE (quo);
-+
+
+- emit_insn ((*get_rsqrts_type (mode)) (x3, xsrc, x2));
+ if (GET_MODE_INNER (mode) == HFmode)
+ return false;
+
@@ -4437,18 +4566,17 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
+ /* Estimate the approximate reciprocal. */
+ rtx xrcp = gen_reg_rtx (mode);
+ emit_insn ((*get_recpe_type (mode)) (xrcp, den));
-
-- emit_insn ((*get_rsqrts_type (mode)) (x3, xsrc, x2));
++
+ /* Iterate over the series twice for SF and thrice for DF. */
+ int iterations = (GET_MODE_INNER (mode) == DFmode) ? 3 : 2;
-
-- emit_set_insn (x1, gen_rtx_MULT (mode, x0, x3));
-- x0 = x1;
++
+ /* Optionally iterate over the series once less for faster performance,
+ while sacrificing the accuracy. */
+ if (flag_mlow_precision_div)
+ iterations--;
-+
+
+- emit_set_insn (x1, gen_rtx_MULT (mode, x0, x3));
+- x0 = x1;
+ /* Iterate over the series to calculate the approximate reciprocal. */
+ rtx xtmp = gen_reg_rtx (mode);
+ while (iterations--)
@@ -4457,24 +4585,24 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
+
+ if (iterations > 0)
+ emit_set_insn (xrcp, gen_rtx_MULT (mode, xrcp, xtmp));
- }
-
-- emit_move_insn (dst, x0);
++ }
++
+ if (num != CONST1_RTX (mode))
+ {
+ /* As the approximate reciprocal of DEN is already calculated, only
+ calculate the approximate division when NUM is not 1.0. */
+ rtx xnum = force_reg (mode, num);
+ emit_set_insn (xrcp, gen_rtx_MULT (mode, xrcp, xnum));
-+ }
-+
+ }
+
+- emit_move_insn (dst, x0);
+ /* Finalize the approximation. */
+ emit_set_insn (quo, gen_rtx_MULT (mode, xrcp, xtmp));
+ return true;
}
/* Return the number of instructions that can be issued per cycle. */
-@@ -8046,32 +8251,37 @@ aarch64_override_options_after_change_1 (struct gcc_options *opts)
+@@ -8046,32 +8261,37 @@ aarch64_override_options_after_change_1 (struct gcc_options *opts)
opts->x_align_functions = aarch64_tune_params.function_align;
}
@@ -4529,7 +4657,17 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
}
/* 'Unpack' up the internal tuning structs and update the options
-@@ -9279,15 +9489,18 @@ aarch64_classify_symbol (rtx x, rtx offset)
+@@ -8374,9 +8594,6 @@ aarch64_override_options (void)
+ while processing functions with potential target attributes. */
+ target_option_default_node = target_option_current_node
+ = build_target_option_node (&global_options);
+-
+- aarch64_register_fma_steering ();
+-
+ }
+
+ /* Implement targetm.override_options_after_change. */
+@@ -9279,15 +9496,18 @@ aarch64_classify_symbol (rtx x, rtx offset)
switch (aarch64_cmodel)
{
case AARCH64_CMODEL_TINY:
@@ -4551,7 +4689,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
|| INTVAL (offset) < -1048575 || INTVAL (offset) > 1048575)
return SYMBOL_FORCE_TO_MEM;
return SYMBOL_TINY_ABSOLUTE;
-@@ -9295,7 +9508,8 @@ aarch64_classify_symbol (rtx x, rtx offset)
+@@ -9295,7 +9515,8 @@ aarch64_classify_symbol (rtx x, rtx offset)
case AARCH64_CMODEL_SMALL:
/* Same reasoning as the tiny code model, but the offset cap here is
4G. */
@@ -4561,7 +4699,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
|| !IN_RANGE (INTVAL (offset), HOST_WIDE_INT_C (-4294967263),
HOST_WIDE_INT_C (4294967264)))
return SYMBOL_FORCE_TO_MEM;
-@@ -9317,8 +9531,7 @@ aarch64_classify_symbol (rtx x, rtx offset)
+@@ -9317,8 +9538,7 @@ aarch64_classify_symbol (rtx x, rtx offset)
/* This is alright even in PIC code as the constant
pool reference is always PC relative and within
the same translation unit. */
@@ -4571,7 +4709,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
return SYMBOL_SMALL_ABSOLUTE;
else
return SYMBOL_FORCE_TO_MEM;
-@@ -9454,6 +9667,13 @@ aarch64_build_builtin_va_list (void)
+@@ -9454,6 +9674,13 @@ aarch64_build_builtin_va_list (void)
FIELD_DECL, get_identifier ("__vr_offs"),
integer_type_node);
@@ -4585,7 +4723,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
DECL_ARTIFICIAL (f_stack) = 1;
DECL_ARTIFICIAL (f_grtop) = 1;
DECL_ARTIFICIAL (f_vrtop) = 1;
-@@ -9486,15 +9706,17 @@ aarch64_expand_builtin_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
+@@ -9486,15 +9713,17 @@ aarch64_expand_builtin_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
tree f_stack, f_grtop, f_vrtop, f_groff, f_vroff;
tree stack, grtop, vrtop, groff, vroff;
tree t;
@@ -4609,7 +4747,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
if (!TARGET_FLOAT)
{
-@@ -9823,7 +10045,8 @@ aarch64_setup_incoming_varargs (cumulative_args_t cum_v, machine_mode mode,
+@@ -9823,7 +10052,8 @@ aarch64_setup_incoming_varargs (cumulative_args_t cum_v, machine_mode mode,
{
CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
CUMULATIVE_ARGS local_cum;
@@ -4619,7 +4757,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* The caller has advanced CUM up to, but not beyond, the last named
argument. Advance a local copy of CUM past the last "real" named
-@@ -9831,9 +10054,14 @@ aarch64_setup_incoming_varargs (cumulative_args_t cum_v, machine_mode mode,
+@@ -9831,9 +10061,14 @@ aarch64_setup_incoming_varargs (cumulative_args_t cum_v, machine_mode mode,
local_cum = *cum;
aarch64_function_arg_advance (pack_cumulative_args(&local_cum), mode, type, true);
@@ -4637,7 +4775,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
if (!TARGET_FLOAT)
{
-@@ -9861,7 +10089,7 @@ aarch64_setup_incoming_varargs (cumulative_args_t cum_v, machine_mode mode,
+@@ -9861,7 +10096,7 @@ aarch64_setup_incoming_varargs (cumulative_args_t cum_v, machine_mode mode,
/* We can't use move_block_from_reg, because it will use
the wrong mode, storing D regs only. */
machine_mode mode = TImode;
@@ -4646,7 +4784,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* Set OFF to the offset from virtual_incoming_args_rtx of
the first vector register. The VR save area lies below
-@@ -9870,14 +10098,15 @@ aarch64_setup_incoming_varargs (cumulative_args_t cum_v, machine_mode mode,
+@@ -9870,14 +10105,15 @@ aarch64_setup_incoming_varargs (cumulative_args_t cum_v, machine_mode mode,
STACK_BOUNDARY / BITS_PER_UNIT);
off -= vr_saved * UNITS_PER_VREG;
@@ -4664,7 +4802,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
off += UNITS_PER_VREG;
}
}
-@@ -10839,33 +11068,6 @@ aarch64_simd_emit_reg_reg_move (rtx *operands, enum machine_mode mode,
+@@ -10839,33 +11075,6 @@ aarch64_simd_emit_reg_reg_move (rtx *operands, enum machine_mode mode,
gen_rtx_REG (mode, rsrc + count - i - 1));
}
@@ -4698,7 +4836,45 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
one of VSTRUCT modes: OI, CI, or XI. */
int
-@@ -11947,12 +12149,11 @@ aarch64_output_simd_mov_immediate (rtx const_vector,
+@@ -10899,6 +11108,37 @@ aarch64_simd_vector_alignment_reachable (const_tree type, bool is_packed)
+ return true;
+ }
+
++/* Return true if the vector misalignment factor is supported by the
++ target. */
++static bool
++aarch64_builtin_support_vector_misalignment (machine_mode mode,
++ const_tree type, int misalignment,
++ bool is_packed)
++{
++ if (TARGET_SIMD && STRICT_ALIGNMENT)
++ {
++ /* Return if movmisalign pattern is not supported for this mode. */
++ if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing)
++ return false;
++
++ if (misalignment == -1)
++ {
++ /* Misalignment factor is unknown at compile time but we know
++ it's word aligned. */
++ if (aarch64_simd_vector_alignment_reachable (type, is_packed))
++ {
++ int element_size = TREE_INT_CST_LOW (TYPE_SIZE (type));
++
++ if (element_size != 64)
++ return true;
++ }
++ return false;
++ }
++ }
++ return default_builtin_support_vector_misalignment (mode, type, misalignment,
++ is_packed);
++}
++
+ /* If VALS is a vector constant that can be loaded into a register
+ using DUP, generate instructions to do so and return an RTX to
+ assign to the register. Otherwise return NULL_RTX. */
+@@ -11947,12 +12187,11 @@ aarch64_output_simd_mov_immediate (rtx const_vector,
info.value = GEN_INT (0);
else
{
@@ -4712,7 +4888,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
if (lane_count == 1)
snprintf (templ, sizeof (templ), "fmov\t%%d0, %s", float_buf);
-@@ -12186,6 +12387,8 @@ aarch64_evpc_trn (struct expand_vec_perm_d *d)
+@@ -12186,6 +12425,8 @@ aarch64_evpc_trn (struct expand_vec_perm_d *d)
case V4SImode: gen = gen_aarch64_trn2v4si; break;
case V2SImode: gen = gen_aarch64_trn2v2si; break;
case V2DImode: gen = gen_aarch64_trn2v2di; break;
@@ -4721,7 +4897,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
case V4SFmode: gen = gen_aarch64_trn2v4sf; break;
case V2SFmode: gen = gen_aarch64_trn2v2sf; break;
case V2DFmode: gen = gen_aarch64_trn2v2df; break;
-@@ -12204,6 +12407,8 @@ aarch64_evpc_trn (struct expand_vec_perm_d *d)
+@@ -12204,6 +12445,8 @@ aarch64_evpc_trn (struct expand_vec_perm_d *d)
case V4SImode: gen = gen_aarch64_trn1v4si; break;
case V2SImode: gen = gen_aarch64_trn1v2si; break;
case V2DImode: gen = gen_aarch64_trn1v2di; break;
@@ -4730,7 +4906,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
case V4SFmode: gen = gen_aarch64_trn1v4sf; break;
case V2SFmode: gen = gen_aarch64_trn1v2sf; break;
case V2DFmode: gen = gen_aarch64_trn1v2df; break;
-@@ -12269,6 +12474,8 @@ aarch64_evpc_uzp (struct expand_vec_perm_d *d)
+@@ -12269,6 +12512,8 @@ aarch64_evpc_uzp (struct expand_vec_perm_d *d)
case V4SImode: gen = gen_aarch64_uzp2v4si; break;
case V2SImode: gen = gen_aarch64_uzp2v2si; break;
case V2DImode: gen = gen_aarch64_uzp2v2di; break;
@@ -4739,7 +4915,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
case V4SFmode: gen = gen_aarch64_uzp2v4sf; break;
case V2SFmode: gen = gen_aarch64_uzp2v2sf; break;
case V2DFmode: gen = gen_aarch64_uzp2v2df; break;
-@@ -12287,6 +12494,8 @@ aarch64_evpc_uzp (struct expand_vec_perm_d *d)
+@@ -12287,6 +12532,8 @@ aarch64_evpc_uzp (struct expand_vec_perm_d *d)
case V4SImode: gen = gen_aarch64_uzp1v4si; break;
case V2SImode: gen = gen_aarch64_uzp1v2si; break;
case V2DImode: gen = gen_aarch64_uzp1v2di; break;
@@ -4748,7 +4924,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
case V4SFmode: gen = gen_aarch64_uzp1v4sf; break;
case V2SFmode: gen = gen_aarch64_uzp1v2sf; break;
case V2DFmode: gen = gen_aarch64_uzp1v2df; break;
-@@ -12357,6 +12566,8 @@ aarch64_evpc_zip (struct expand_vec_perm_d *d)
+@@ -12357,6 +12604,8 @@ aarch64_evpc_zip (struct expand_vec_perm_d *d)
case V4SImode: gen = gen_aarch64_zip2v4si; break;
case V2SImode: gen = gen_aarch64_zip2v2si; break;
case V2DImode: gen = gen_aarch64_zip2v2di; break;
@@ -4757,7 +4933,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
case V4SFmode: gen = gen_aarch64_zip2v4sf; break;
case V2SFmode: gen = gen_aarch64_zip2v2sf; break;
case V2DFmode: gen = gen_aarch64_zip2v2df; break;
-@@ -12375,6 +12586,8 @@ aarch64_evpc_zip (struct expand_vec_perm_d *d)
+@@ -12375,6 +12624,8 @@ aarch64_evpc_zip (struct expand_vec_perm_d *d)
case V4SImode: gen = gen_aarch64_zip1v4si; break;
case V2SImode: gen = gen_aarch64_zip1v2si; break;
case V2DImode: gen = gen_aarch64_zip1v2di; break;
@@ -4766,7 +4942,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
case V4SFmode: gen = gen_aarch64_zip1v4sf; break;
case V2SFmode: gen = gen_aarch64_zip1v2sf; break;
case V2DFmode: gen = gen_aarch64_zip1v2df; break;
-@@ -12419,6 +12632,8 @@ aarch64_evpc_ext (struct expand_vec_perm_d *d)
+@@ -12419,6 +12670,8 @@ aarch64_evpc_ext (struct expand_vec_perm_d *d)
case V8HImode: gen = gen_aarch64_extv8hi; break;
case V2SImode: gen = gen_aarch64_extv2si; break;
case V4SImode: gen = gen_aarch64_extv4si; break;
@@ -4775,7 +4951,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
case V2SFmode: gen = gen_aarch64_extv2sf; break;
case V4SFmode: gen = gen_aarch64_extv4sf; break;
case V2DImode: gen = gen_aarch64_extv2di; break;
-@@ -12494,6 +12709,8 @@ aarch64_evpc_rev (struct expand_vec_perm_d *d)
+@@ -12494,6 +12747,8 @@ aarch64_evpc_rev (struct expand_vec_perm_d *d)
case V2SImode: gen = gen_aarch64_rev64v2si; break;
case V4SFmode: gen = gen_aarch64_rev64v4sf; break;
case V2SFmode: gen = gen_aarch64_rev64v2sf; break;
@@ -4784,7 +4960,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
default:
return false;
}
-@@ -12737,24 +12954,6 @@ aarch64_vectorize_vec_perm_const_ok (machine_mode vmode,
+@@ -12737,24 +12992,6 @@ aarch64_vectorize_vec_perm_const_ok (machine_mode vmode,
return ret;
}
@@ -4809,7 +4985,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
rtx
aarch64_reverse_mask (enum machine_mode mode)
{
-@@ -12776,7 +12975,14 @@ aarch64_reverse_mask (enum machine_mode mode)
+@@ -12776,7 +13013,14 @@ aarch64_reverse_mask (enum machine_mode mode)
return force_reg (V16QImode, mask);
}
@@ -4825,7 +5001,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
bool
aarch64_modes_tieable_p (machine_mode mode1, machine_mode mode2)
-@@ -12787,9 +12993,12 @@ aarch64_modes_tieable_p (machine_mode mode1, machine_mode mode2)
+@@ -12787,9 +13031,12 @@ aarch64_modes_tieable_p (machine_mode mode1, machine_mode mode2)
/* We specifically want to allow elements of "structure" modes to
be tieable to the structure. This more general condition allows
other rarer situations too. */
@@ -4841,7 +5017,71 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
return true;
return false;
-@@ -13305,6 +13514,14 @@ aarch_macro_fusion_pair_p (rtx_insn *prev, rtx_insn *curr)
+@@ -12953,6 +13200,63 @@ aarch64_expand_movmem (rtx *operands)
+ return true;
+ }
+
++/* Split a DImode store of a CONST_INT SRC to MEM DST as two
++ SImode stores. Handle the case when the constant has identical
++ bottom and top halves. This is beneficial when the two stores can be
++ merged into an STP and we avoid synthesising potentially expensive
++ immediates twice. Return true if such a split is possible. */
++
++bool
++aarch64_split_dimode_const_store (rtx dst, rtx src)
++{
++ rtx lo = gen_lowpart (SImode, src);
++ rtx hi = gen_highpart_mode (SImode, DImode, src);
++
++ bool size_p = optimize_function_for_size_p (cfun);
++
++ if (!rtx_equal_p (lo, hi))
++ return false;
++
++ unsigned int orig_cost
++ = aarch64_internal_mov_immediate (NULL_RTX, src, false, DImode);
++ unsigned int lo_cost
++ = aarch64_internal_mov_immediate (NULL_RTX, lo, false, SImode);
++
++ /* We want to transform:
++ MOV x1, 49370
++ MOVK x1, 0x140, lsl 16
++ MOVK x1, 0xc0da, lsl 32
++ MOVK x1, 0x140, lsl 48
++ STR x1, [x0]
++ into:
++ MOV w1, 49370
++ MOVK w1, 0x140, lsl 16
++ STP w1, w1, [x0]
++ So we want to perform this only when we save two instructions
++ or more. When optimizing for size, however, accept any code size
++ savings we can. */
++ if (size_p && orig_cost <= lo_cost)
++ return false;
++
++ if (!size_p
++ && (orig_cost <= lo_cost + 1))
++ return false;
++
++ rtx mem_lo = adjust_address (dst, SImode, 0);
++ if (!aarch64_mem_pair_operand (mem_lo, SImode))
++ return false;
++
++ rtx tmp_reg = gen_reg_rtx (SImode);
++ aarch64_expand_mov_immediate (tmp_reg, lo);
++ rtx mem_hi = aarch64_move_pointer (mem_lo, GET_MODE_SIZE (SImode));
++ /* Don't emit an explicit store pair as this may not be always profitable.
++ Let the sched-fusion logic decide whether to merge them. */
++ emit_move_insn (mem_lo, tmp_reg);
++ emit_move_insn (mem_hi, tmp_reg);
++
++ return true;
++}
++
+ /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
+
+ static unsigned HOST_WIDE_INT
+@@ -13305,6 +13609,14 @@ aarch_macro_fusion_pair_p (rtx_insn *prev, rtx_insn *curr)
return false;
}
@@ -4856,7 +5096,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* If MEM is in the form of [base+offset], extract the two parts
of address and set to BASE and OFFSET, otherwise return false
after clearing BASE and OFFSET. */
-@@ -13449,6 +13666,26 @@ aarch64_sched_fusion_priority (rtx_insn *insn, int max_pri,
+@@ -13449,6 +13761,26 @@ aarch64_sched_fusion_priority (rtx_insn *insn, int max_pri,
return;
}
@@ -4883,7 +5123,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* Given OPERANDS of consecutive load/store, check if we can merge
them into ldp/stp. LOAD is true if they are load instructions.
MODE is the mode of memory operands. */
-@@ -13483,6 +13720,15 @@ aarch64_operands_ok_for_ldpstp (rtx *operands, bool load,
+@@ -13483,6 +13815,15 @@ aarch64_operands_ok_for_ldpstp (rtx *operands, bool load,
if (MEM_VOLATILE_P (mem_1) || MEM_VOLATILE_P (mem_2))
return false;
@@ -4899,7 +5139,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* Check if the addresses are in the form of [base+offset]. */
extract_base_offset_in_addr (mem_1, &base_1, &offset_1);
if (base_1 == NULL_RTX || offset_1 == NULL_RTX)
-@@ -13642,6 +13888,15 @@ aarch64_operands_adjust_ok_for_ldpstp (rtx *operands, bool load,
+@@ -13642,6 +13983,15 @@ aarch64_operands_adjust_ok_for_ldpstp (rtx *operands, bool load,
return false;
}
@@ -4915,7 +5155,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
if (REG_P (reg_1) && FP_REGNUM_P (REGNO (reg_1)))
rclass_1 = FP_REGS;
else
-@@ -13877,13 +14132,13 @@ aarch64_promoted_type (const_tree t)
+@@ -13877,13 +14227,13 @@ aarch64_promoted_type (const_tree t)
/* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
static bool
@@ -4931,7 +5171,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
default:
return true;
-@@ -14017,6 +14272,10 @@ aarch64_optab_supported_p (int op, machine_mode, machine_mode,
+@@ -14017,6 +14367,10 @@ aarch64_optab_supported_p (int op, machine_mode, machine_mode,
#undef TARGET_LEGITIMATE_CONSTANT_P
#define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
@@ -4942,7 +5182,18 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
#undef TARGET_LIBGCC_CMP_RETURN_MODE
#define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
-@@ -14196,6 +14455,9 @@ aarch64_optab_supported_p (int op, machine_mode, machine_mode,
+@@ -14119,6 +14473,10 @@ aarch64_optab_supported_p (int op, machine_mode, machine_mode,
+ #undef TARGET_VECTOR_MODE_SUPPORTED_P
+ #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
+
++#undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
++#define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
++ aarch64_builtin_support_vector_misalignment
++
+ #undef TARGET_ARRAY_MODE_SUPPORTED_P
+ #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
+
+@@ -14196,6 +14554,9 @@ aarch64_optab_supported_p (int op, machine_mode, machine_mode,
#undef TARGET_CAN_USE_DOLOOP_P
#define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
@@ -4952,7 +5203,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
#undef TARGET_SCHED_MACRO_FUSION_P
#define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
-@@ -14220,6 +14482,9 @@ aarch64_optab_supported_p (int op, machine_mode, machine_mode,
+@@ -14220,6 +14581,9 @@ aarch64_optab_supported_p (int op, machine_mode, machine_mode,
#undef TARGET_OPTAB_SUPPORTED_P
#define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
@@ -4964,7 +5215,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
#include "gt-aarch64.h"
--- a/src/gcc/config/aarch64/aarch64.h
+++ b/src/gcc/config/aarch64/aarch64.h
-@@ -132,9 +132,12 @@ extern unsigned aarch64_architecture_version;
+@@ -132,9 +132,14 @@ extern unsigned aarch64_architecture_version;
#define AARCH64_FL_FP (1 << 1) /* Has FP. */
#define AARCH64_FL_CRYPTO (1 << 2) /* Has crypto. */
#define AARCH64_FL_CRC (1 << 3) /* Has CRC. */
@@ -4976,28 +5227,33 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
+/* ARMv8.2-A architecture extensions. */
+#define AARCH64_FL_V8_2 (1 << 8) /* Has ARMv8.2-A features. */
+#define AARCH64_FL_F16 (1 << 9) /* Has ARMv8.2-A FP16 extensions. */
++/* ARMv8.3-A architecture extensions. */
++#define AARCH64_FL_V8_3 (1 << 10) /* Has ARMv8.3-A features. */
/* Has FP and SIMD. */
#define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD)
-@@ -146,6 +149,8 @@ extern unsigned aarch64_architecture_version;
+@@ -146,6 +151,10 @@ extern unsigned aarch64_architecture_version;
#define AARCH64_FL_FOR_ARCH8 (AARCH64_FL_FPSIMD)
#define AARCH64_FL_FOR_ARCH8_1 \
(AARCH64_FL_FOR_ARCH8 | AARCH64_FL_LSE | AARCH64_FL_CRC | AARCH64_FL_V8_1)
+#define AARCH64_FL_FOR_ARCH8_2 \
+ (AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_V8_2)
++#define AARCH64_FL_FOR_ARCH8_3 \
++ (AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_V8_3)
/* Macros to test ISA flags. */
-@@ -155,6 +160,8 @@ extern unsigned aarch64_architecture_version;
+@@ -155,6 +164,9 @@ extern unsigned aarch64_architecture_version;
#define AARCH64_ISA_SIMD (aarch64_isa_flags & AARCH64_FL_SIMD)
#define AARCH64_ISA_LSE (aarch64_isa_flags & AARCH64_FL_LSE)
#define AARCH64_ISA_RDMA (aarch64_isa_flags & AARCH64_FL_V8_1)
+#define AARCH64_ISA_V8_2 (aarch64_isa_flags & AARCH64_FL_V8_2)
+#define AARCH64_ISA_F16 (aarch64_isa_flags & AARCH64_FL_F16)
++#define AARCH64_ISA_V8_3 (aarch64_isa_flags & AARCH64_FL_V8_3)
/* Crypto is an optional extension to AdvSIMD. */
#define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO)
-@@ -165,6 +172,10 @@ extern unsigned aarch64_architecture_version;
+@@ -165,6 +177,13 @@ extern unsigned aarch64_architecture_version;
/* Atomic instructions that can be enabled through the +lse extension. */
#define TARGET_LSE (AARCH64_ISA_LSE)
@@ -5005,10 +5261,13 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
+#define TARGET_FP_F16INST (TARGET_FLOAT && AARCH64_ISA_F16)
+#define TARGET_SIMD_F16INST (TARGET_SIMD && AARCH64_ISA_F16)
+
++/* ARMv8.3-A features. */
++#define TARGET_ARMV8_3 (AARCH64_ISA_V8_3)
++
/* Make sure this is always defined so we don't have to check for ifdefs
but rather use normal ifs. */
#ifndef TARGET_FIX_ERR_A53_835769_DEFAULT
-@@ -193,7 +204,7 @@ extern unsigned aarch64_architecture_version;
+@@ -193,7 +212,7 @@ extern unsigned aarch64_architecture_version;
((aarch64_fix_a53_err843419 == 2) \
? TARGET_FIX_ERR_A53_843419_DEFAULT : aarch64_fix_a53_err843419)
@@ -5017,7 +5276,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
#define TARGET_SIMD_RDMA (TARGET_SIMD && AARCH64_ISA_RDMA)
/* Standard register usage. */
-@@ -539,11 +550,14 @@ struct GTY (()) aarch64_frame
+@@ -539,11 +558,14 @@ struct GTY (()) aarch64_frame
STACK_BOUNDARY. */
HOST_WIDE_INT saved_varargs_size;
@@ -5036,7 +5295,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* Offset from the base of the frame (incomming SP) to the
hard_frame_pointer. This value is always a multiple of
-@@ -553,12 +567,25 @@ struct GTY (()) aarch64_frame
+@@ -553,12 +575,25 @@ struct GTY (()) aarch64_frame
/* The size of the frame. This value is the offset from base of the
* frame (incomming SP) to the stack_pointer. This value is always
* a multiple of STACK_BOUNDARY. */
@@ -5064,7 +5323,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
bool laid_out;
};
-@@ -652,21 +679,6 @@ typedef struct
+@@ -652,21 +687,6 @@ typedef struct
#define CONSTANT_ADDRESS_P(X) aarch64_constant_address_p(X)
@@ -5086,7 +5345,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
#define REGNO_OK_FOR_BASE_P(REGNO) \
aarch64_regno_ok_for_base_p (REGNO, true)
-@@ -722,7 +734,12 @@ do { \
+@@ -722,7 +742,12 @@ do { \
#define USE_STORE_PRE_INCREMENT(MODE) 0
#define USE_STORE_PRE_DECREMENT(MODE) 0
@@ -5100,7 +5359,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* Define if loading from memory in MODE, an integral mode narrower than
BITS_PER_WORD will either zero-extend or sign-extend. The value of this
-@@ -842,10 +859,7 @@ do { \
+@@ -842,10 +867,7 @@ do { \
extern void __aarch64_sync_cache_range (void *, void *); \
__aarch64_sync_cache_range (beg, end)
@@ -5168,7 +5427,19 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
if (operands[3] == NULL_RTX)
operands[3] = const0_rtx;
-@@ -1160,11 +1149,12 @@
+@@ -1003,6 +992,11 @@
+ (match_operand:GPI 1 "general_operand" ""))]
+ ""
+ "
++ if (MEM_P (operands[0]) && CONST_INT_P (operands[1])
++ && <MODE>mode == DImode
++ && aarch64_split_dimode_const_store (operands[0], operands[1]))
++ DONE;
++
+ if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
+ operands[1] = force_reg (<MODE>mode, operands[1]);
+
+@@ -1160,11 +1154,12 @@
)
(define_insn "*movhf_aarch64"
@@ -5183,7 +5454,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
mov\\t%0.h[0], %w1
umov\\t%w0, %1.h[0]
mov\\t%0.h[0], %1.h[0]
-@@ -1173,18 +1163,18 @@
+@@ -1173,18 +1168,18 @@
ldrh\\t%w0, %1
strh\\t%w1, %0
mov\\t%w0, %w1"
@@ -5207,7 +5478,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
fmov\\t%s0, %w1
fmov\\t%w0, %s1
fmov\\t%s0, %s1
-@@ -1194,16 +1184,18 @@
+@@ -1194,16 +1189,18 @@
ldr\\t%w0, %1
str\\t%w1, %0
mov\\t%w0, %w1"
@@ -5230,7 +5501,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
fmov\\t%d0, %x1
fmov\\t%x0, %d1
fmov\\t%d0, %d1
-@@ -1213,8 +1205,9 @@
+@@ -1213,8 +1210,9 @@
ldr\\t%x0, %1
str\\t%x1, %0
mov\\t%x0, %x1"
@@ -5242,7 +5513,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
)
(define_insn "*movtf_aarch64"
-@@ -1239,7 +1232,6 @@
+@@ -1239,7 +1237,6 @@
[(set_attr "type" "logic_reg,multiple,f_mcr,f_mrc,neon_move_q,f_mcr,\
f_loadd,f_stored,load2,store2,store2")
(set_attr "length" "4,8,8,8,4,4,4,4,4,4,4")
@@ -5250,7 +5521,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
(set_attr "simd" "yes,*,*,*,yes,*,*,*,*,*,*")]
)
-@@ -1552,10 +1544,10 @@
+@@ -1552,10 +1549,10 @@
(zero_extend:GPI (match_operand:SHORT 1 "nonimmediate_operand" "r,m,m")))]
""
"@
@@ -5263,7 +5534,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
)
(define_expand "<optab>qihi2"
-@@ -1564,16 +1556,26 @@
+@@ -1564,16 +1561,26 @@
""
)
@@ -5294,7 +5565,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
;; -------------------------------------------------------------------
;; Simple arithmetic
;; -------------------------------------------------------------------
-@@ -1585,25 +1587,16 @@
+@@ -1585,25 +1592,16 @@
(match_operand:GPI 2 "aarch64_pluslong_operand" "")))]
""
{
@@ -5330,7 +5601,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
})
(define_insn "*add<mode>3_aarch64"
-@@ -1765,7 +1758,7 @@
+@@ -1765,7 +1763,7 @@
"aarch64_zero_extend_const_eq (<DWI>mode, operands[2],
<MODE>mode, operands[1])"
"@
@@ -5339,7 +5610,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
cmp\\t%<w>0, #%n1"
[(set_attr "type" "alus_imm")]
)
-@@ -1797,11 +1790,11 @@
+@@ -1797,11 +1795,11 @@
"aarch64_zero_extend_const_eq (<DWI>mode, operands[3],
<MODE>mode, operands[2])"
"@
@@ -5353,7 +5624,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
(define_insn "add<mode>3_compareC"
[(set (reg:CC_C CC_REGNUM)
(ne:CC_C
-@@ -3404,7 +3397,9 @@
+@@ -3404,7 +3402,9 @@
(LOGICAL:SI (match_operand:SI 1 "register_operand" "%r,r")
(match_operand:SI 2 "aarch64_logical_operand" "r,K"))))]
""
@@ -5364,7 +5635,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
[(set_attr "type" "logic_reg,logic_imm")]
)
-@@ -3417,7 +3412,9 @@
+@@ -3417,7 +3417,9 @@
(set (match_operand:GPI 0 "register_operand" "=r,r")
(and:GPI (match_dup 1) (match_dup 2)))]
""
@@ -5375,7 +5646,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
[(set_attr "type" "logics_reg,logics_imm")]
)
-@@ -3431,7 +3428,9 @@
+@@ -3431,7 +3433,9 @@
(set (match_operand:DI 0 "register_operand" "=r,r")
(zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
""
@@ -5386,7 +5657,47 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
[(set_attr "type" "logics_reg,logics_imm")]
)
-@@ -3757,16 +3756,23 @@
+@@ -3741,6 +3745,39 @@
+ }
+ )
+
++;; Pop count be done via the "CNT" instruction in AdvSIMD.
++;;
++;; MOV v.1d, x0
++;; CNT v1.8b, v.8b
++;; ADDV b2, v1.8b
++;; MOV w0, v2.b[0]
++
++(define_expand "popcount<mode>2"
++ [(match_operand:GPI 0 "register_operand")
++ (match_operand:GPI 1 "register_operand")]
++ "TARGET_SIMD"
++{
++ rtx v = gen_reg_rtx (V8QImode);
++ rtx v1 = gen_reg_rtx (V8QImode);
++ rtx r = gen_reg_rtx (QImode);
++ rtx in = operands[1];
++ rtx out = operands[0];
++ if(<MODE>mode == SImode)
++ {
++ rtx tmp;
++ tmp = gen_reg_rtx (DImode);
++ /* If we have SImode, zero extend to DImode, pop count does
++ not change if we have extra zeros. */
++ emit_insn (gen_zero_extendsidi2 (tmp, in));
++ in = tmp;
++ }
++ emit_move_insn (v, gen_lowpart (V8QImode, in));
++ emit_insn (gen_popcountv8qi2 (v1, v));
++ emit_insn (gen_reduc_plus_scal_v8qi (r, v1));
++ emit_insn (gen_zero_extendqi<mode>2 (out, r));
++ DONE;
++})
++
+ (define_insn "clrsb<mode>2"
+ [(set (match_operand:GPI 0 "register_operand" "=r")
+ (clrsb:GPI (match_operand:GPI 1 "register_operand" "r")))]
+@@ -3757,16 +3794,23 @@
[(set_attr "type" "rbit")]
)
@@ -5419,7 +5730,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
(define_insn "*and<mode>_compare0"
[(set (reg:CC_NZ CC_REGNUM)
-@@ -3778,6 +3784,18 @@
+@@ -3778,6 +3822,18 @@
[(set_attr "type" "alus_imm")]
)
@@ -5438,7 +5749,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
(define_insn "*and<mode>3nr_compare0"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
-@@ -3785,7 +3803,9 @@
+@@ -3785,7 +3841,9 @@
(match_operand:GPI 1 "aarch64_logical_operand" "r,<lconst>"))
(const_int 0)))]
""
@@ -5449,7 +5760,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
[(set_attr "type" "logics_reg,logics_imm")]
)
-@@ -3851,22 +3871,16 @@
+@@ -3851,22 +3909,16 @@
(define_expand "ashl<mode>3"
[(set (match_operand:SHORT 0 "register_operand")
(ashift:SHORT (match_operand:SHORT 1 "register_operand")
@@ -5478,7 +5789,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
}
)
-@@ -3915,33 +3929,35 @@
+@@ -3915,33 +3967,35 @@
;; Logical left shift using SISD or Integer instruction
(define_insn "*aarch64_ashl_sisd_or_int_<mode>3"
@@ -5526,7 +5837,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
)
(define_split
-@@ -3976,18 +3992,19 @@
+@@ -3976,18 +4030,19 @@
;; Arithmetic right shift using SISD or Integer instruction
(define_insn "*aarch64_ashr_sisd_or_int_<mode>3"
@@ -5551,7 +5862,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
)
(define_split
-@@ -4079,21 +4096,25 @@
+@@ -4079,21 +4134,25 @@
[(set (match_operand:GPI 0 "register_operand" "=r,r")
(rotatert:GPI
(match_operand:GPI 1 "register_operand" "r,r")
@@ -5585,7 +5896,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
)
(define_insn "*<optab><mode>3_insn"
-@@ -4105,7 +4126,7 @@
+@@ -4105,7 +4164,7 @@
operands[3] = GEN_INT (<sizen> - UINTVAL (operands[2]));
return "<bfshift>\t%w0, %w1, %2, %3";
}
@@ -5594,7 +5905,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
)
(define_insn "*extr<mode>5_insn"
-@@ -4117,7 +4138,7 @@
+@@ -4117,7 +4176,7 @@
"UINTVAL (operands[3]) < GET_MODE_BITSIZE (<MODE>mode) &&
(UINTVAL (operands[3]) + UINTVAL (operands[4]) == GET_MODE_BITSIZE (<MODE>mode))"
"extr\\t%<w>0, %<w>1, %<w>2, %4"
@@ -5603,7 +5914,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
)
;; There are no canonicalisation rules for ashift and lshiftrt inside an ior
-@@ -4132,7 +4153,7 @@
+@@ -4132,7 +4191,7 @@
&& (UINTVAL (operands[3]) + UINTVAL (operands[4])
== GET_MODE_BITSIZE (<MODE>mode))"
"extr\\t%<w>0, %<w>1, %<w>2, %4"
@@ -5612,7 +5923,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
)
;; zero_extend version of the above
-@@ -4146,7 +4167,7 @@
+@@ -4146,7 +4205,7 @@
"UINTVAL (operands[3]) < 32 &&
(UINTVAL (operands[3]) + UINTVAL (operands[4]) == 32)"
"extr\\t%w0, %w1, %w2, %4"
@@ -5621,7 +5932,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
)
(define_insn "*extrsi5_insn_uxtw_alt"
-@@ -4159,7 +4180,7 @@
+@@ -4159,7 +4218,7 @@
"UINTVAL (operands[3]) < 32 &&
(UINTVAL (operands[3]) + UINTVAL (operands[4]) == 32)"
"extr\\t%w0, %w1, %w2, %4"
@@ -5630,7 +5941,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
)
(define_insn "*ror<mode>3_insn"
-@@ -4198,7 +4219,7 @@
+@@ -4198,7 +4257,7 @@
operands[3] = GEN_INT (<SHORT:sizen> - UINTVAL (operands[2]));
return "<su>bfiz\t%<GPI:w>0, %<GPI:w>1, %2, %3";
}
@@ -5639,7 +5950,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
)
(define_insn "*zero_extend<GPI:mode>_lshr<SHORT:mode>"
-@@ -4211,7 +4232,7 @@
+@@ -4211,7 +4270,7 @@
operands[3] = GEN_INT (<SHORT:sizen> - UINTVAL (operands[2]));
return "ubfx\t%<GPI:w>0, %<GPI:w>1, %2, %3";
}
@@ -5648,7 +5959,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
)
(define_insn "*extend<GPI:mode>_ashr<SHORT:mode>"
-@@ -4224,7 +4245,7 @@
+@@ -4224,7 +4283,7 @@
operands[3] = GEN_INT (<SHORT:sizen> - UINTVAL (operands[2]));
return "sbfx\\t%<GPI:w>0, %<GPI:w>1, %2, %3";
}
@@ -5657,7 +5968,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
)
;; -------------------------------------------------------------------
-@@ -4256,7 +4277,27 @@
+@@ -4256,7 +4315,27 @@
"IN_RANGE (INTVAL (operands[2]) + INTVAL (operands[3]),
1, GET_MODE_BITSIZE (<MODE>mode) - 1)"
"<su>bfx\\t%<w>0, %<w>1, %3, %2"
@@ -5686,7 +5997,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
)
;; Bitfield Insert (insv)
-@@ -4338,7 +4379,7 @@
+@@ -4338,7 +4417,7 @@
: GEN_INT (<GPI:sizen> - UINTVAL (operands[2]));
return "<su>bfiz\t%<GPI:w>0, %<GPI:w>1, %2, %3";
}
@@ -5695,7 +6006,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
)
;; XXX We should match (any_extend (ashift)) here, like (and (ashift)) below
-@@ -4348,11 +4389,27 @@
+@@ -4348,11 +4427,27 @@
(and:GPI (ashift:GPI (match_operand:GPI 1 "register_operand" "r")
(match_operand 2 "const_int_operand" "n"))
(match_operand 3 "const_int_operand" "n")))]
@@ -5727,7 +6038,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
)
(define_insn "bswap<mode>2"
-@@ -4420,22 +4477,23 @@
+@@ -4420,22 +4515,23 @@
;; Expands to btrunc, ceil, floor, nearbyint, rint, round, frintn.
(define_insn "<frint_pattern><mode>2"
@@ -5758,7 +6069,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
[(set_attr "type" "f_cvtf2i")]
)
-@@ -4461,23 +4519,24 @@
+@@ -4461,23 +4557,24 @@
;; fma - no throw
(define_insn "fma<mode>4"
@@ -5793,30 +6104,30 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
)
(define_insn "fms<mode>4"
-@@ -4563,19 +4622,11 @@
+@@ -4563,19 +4660,11 @@
[(set_attr "type" "f_cvt")]
)
-(define_insn "fix_trunc<GPF:mode><GPI:mode>2"
-+(define_insn "<optab>_trunc<GPF_F16:mode><GPI:mode>2"
- [(set (match_operand:GPI 0 "register_operand" "=r")
+- [(set (match_operand:GPI 0 "register_operand" "=r")
- (fix:GPI (match_operand:GPF 1 "register_operand" "w")))]
-+ (FIXUORS:GPI (match_operand:GPF_F16 1 "register_operand" "w")))]
- "TARGET_FLOAT"
+- "TARGET_FLOAT"
- "fcvtzs\\t%<GPI:w>0, %<GPF:s>1"
- [(set_attr "type" "f_cvtf2i")]
-)
-
-(define_insn "fixuns_trunc<GPF:mode><GPI:mode>2"
-- [(set (match_operand:GPI 0 "register_operand" "=r")
++(define_insn "<optab>_trunc<GPF_F16:mode><GPI:mode>2"
+ [(set (match_operand:GPI 0 "register_operand" "=r")
- (unsigned_fix:GPI (match_operand:GPF 1 "register_operand" "w")))]
-- "TARGET_FLOAT"
++ (FIXUORS:GPI (match_operand:GPF_F16 1 "register_operand" "w")))]
+ "TARGET_FLOAT"
- "fcvtzu\\t%<GPI:w>0, %<GPF:s>1"
+ "fcvtz<su>\t%<GPI:w>0, %<GPF_F16:s>1"
[(set_attr "type" "f_cvtf2i")]
)
-@@ -4599,38 +4650,116 @@
+@@ -4599,38 +4688,116 @@
[(set_attr "type" "f_cvti2f")]
)
@@ -5948,7 +6259,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
)
(define_insn "*fnmul<mode>3"
-@@ -4653,38 +4782,58 @@
+@@ -4653,38 +4820,58 @@
[(set_attr "type" "fmul<s>")]
)
@@ -6023,7 +6334,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
)
;; Given that smax/smin do not specify the result when either input is NaN,
-@@ -4709,15 +4858,17 @@
+@@ -4709,15 +4896,17 @@
[(set_attr "type" "f_minmax<s>")]
)
@@ -6049,7 +6360,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
)
;; For copysign (x, y), we want to generate:
-@@ -4775,7 +4926,7 @@
+@@ -4775,7 +4964,7 @@
[(set (match_operand:GPF_TF 0 "register_operand" "=w")
(mem:GPF_TF (match_operand 1 "aarch64_constant_pool_symref" "S")))
(clobber (match_operand:P 2 "register_operand" "=&r"))]
@@ -6058,7 +6369,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
{
aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
emit_move_insn (operands[0], gen_rtx_MEM (<GPF_TF:MODE>mode, operands[2]));
-@@ -4788,7 +4939,7 @@
+@@ -4788,7 +4977,7 @@
[(set (match_operand:VALL 0 "register_operand" "=w")
(mem:VALL (match_operand 1 "aarch64_constant_pool_symref" "S")))
(clobber (match_operand:P 2 "register_operand" "=&r"))]
@@ -6067,7 +6378,32 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
{
aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
emit_move_insn (operands[0], gen_rtx_MEM (<VALL:MODE>mode, operands[2]));
-@@ -5182,7 +5333,7 @@
+@@ -4961,20 +5150,20 @@
+ ;; The TLS ABI specifically requires that the compiler does not schedule
+ ;; instructions in the TLS stubs, in order to enable linker relaxation.
+ ;; Therefore we treat the stubs as an atomic sequence.
+-(define_expand "tlsgd_small"
++(define_expand "tlsgd_small_<mode>"
+ [(parallel [(set (match_operand 0 "register_operand" "")
+ (call (mem:DI (match_dup 2)) (const_int 1)))
+- (unspec:DI [(match_operand:DI 1 "aarch64_valid_symref" "")] UNSPEC_GOTSMALLTLS)
++ (unspec:DI [(match_operand:PTR 1 "aarch64_valid_symref" "")] UNSPEC_GOTSMALLTLS)
+ (clobber (reg:DI LR_REGNUM))])]
+ ""
+ {
+ operands[2] = aarch64_tls_get_addr ();
+ })
+
+-(define_insn "*tlsgd_small"
++(define_insn "*tlsgd_small_<mode>"
+ [(set (match_operand 0 "register_operand" "")
+ (call (mem:DI (match_operand:DI 2 "" "")) (const_int 1)))
+- (unspec:DI [(match_operand:DI 1 "aarch64_valid_symref" "S")] UNSPEC_GOTSMALLTLS)
++ (unspec:DI [(match_operand:PTR 1 "aarch64_valid_symref" "S")] UNSPEC_GOTSMALLTLS)
+ (clobber (reg:DI LR_REGNUM))
+ ]
+ ""
+@@ -5182,7 +5371,7 @@
UNSPEC_SP_TEST))
(clobber (match_scratch:PTR 3 "=&r"))]
""
@@ -6078,7 +6414,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
--- a/src/gcc/config/aarch64/aarch64.opt
+++ b/src/gcc/config/aarch64/aarch64.opt
-@@ -146,10 +146,24 @@ EnumValue
+@@ -146,10 +146,28 @@ EnumValue
Enum(aarch64_abi) String(lp64) Value(AARCH64_ABI_LP64)
mpc-relative-literal-loads
@@ -6106,6 +6442,10 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
+Enable the division approximation. Enabling this reduces
+precision of division results to about 16 bits for
+single precision and to 32 bits for double precision.
++
++mverbose-cost-dump
++Common Undocumented Var(flag_aarch64_verbose_cost)
++Enables verbose cost model dummping in the debug dump files.
--- /dev/null
+++ b/src/gcc/config/aarch64/arm_fp16.h
@@ -0,0 +1,579 @@
@@ -50575,6 +50915,78 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
;; Atomic swap with memory.
(define_insn "aarch64_atomic_swp<mode>"
+--- a/src/gcc/config/aarch64/cortex-a57-fma-steering.c
++++ b/src/gcc/config/aarch64/cortex-a57-fma-steering.c
+@@ -35,7 +35,6 @@
+ #include "context.h"
+ #include "tree-pass.h"
+ #include "regrename.h"
+-#include "cortex-a57-fma-steering.h"
+ #include "aarch64-protos.h"
+
+ /* For better performance, the destination of FMADD/FMSUB instructions should
+@@ -923,10 +922,10 @@ func_fma_steering::analyze ()
+ FOR_BB_INSNS (bb, insn)
+ {
+ operand_rr_info *dest_op_info;
+- struct du_chain *chain;
++ struct du_chain *chain = NULL;
+ unsigned dest_regno;
+- fma_forest *forest;
+- du_head_p head;
++ fma_forest *forest = NULL;
++ du_head_p head = NULL;
+ int i;
+
+ if (!is_fmul_fmac_insn (insn, true))
+@@ -1068,21 +1067,8 @@ public:
+
+ /* Create a new fma steering pass instance. */
+
+-static rtl_opt_pass *
++rtl_opt_pass *
+ make_pass_fma_steering (gcc::context *ctxt)
+ {
+ return new pass_fma_steering (ctxt);
+ }
+-
+-/* Register the FMA steering pass to the pass manager. */
+-
+-void
+-aarch64_register_fma_steering ()
+-{
+- opt_pass *pass_fma_steering = make_pass_fma_steering (g);
+-
+- struct register_pass_info fma_steering_info
+- = { pass_fma_steering, "rnreg", 1, PASS_POS_INSERT_AFTER };
+-
+- register_pass (&fma_steering_info);
+-}
+--- a/src/gcc/config/aarch64/cortex-a57-fma-steering.h
++++ b/src//dev/null
+@@ -1,22 +0,0 @@
+-/* This file contains declarations for the FMA steering optimization
+- pass for Cortex-A57.
+- Copyright (C) 2015-2016 Free Software Foundation, Inc.
+- Contributed by ARM Ltd.
+-
+- This file is part of GCC.
+-
+- GCC is free software; you can redistribute it and/or modify it
+- under the terms of the GNU General Public License as published by
+- the Free Software Foundation; either version 3, or (at your option)
+- any later version.
+-
+- GCC is distributed in the hope that it will be useful, but
+- WITHOUT ANY WARRANTY; without even the implied warranty of
+- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+- General Public License for more details.
+-
+- You should have received a copy of the GNU General Public License
+- along with GCC; see the file COPYING3. If not see
+- <http://www.gnu.org/licenses/>. */
+-
+-void aarch64_register_fma_steering (void);
--- a/src/gcc/config/aarch64/geniterators.sh
+++ b/src/gcc/config/aarch64/geniterators.sh
@@ -23,10 +23,7 @@
@@ -50928,9 +51340,24 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
(define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip")
(UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn")
(UNSPEC_UZP1 "uzp") (UNSPEC_UZP2 "uzp")])
+--- a/src/gcc/config/aarch64/predicates.md
++++ b/src/gcc/config/aarch64/predicates.md
+@@ -54,9 +54,9 @@
+ (match_test "op == const0_rtx"))))
+
+ (define_predicate "aarch64_reg_or_fp_zero"
+- (and (match_code "reg,subreg,const_double")
+- (ior (match_operand 0 "register_operand")
+- (match_test "aarch64_float_const_zero_rtx_p (op)"))))
++ (ior (match_operand 0 "register_operand")
++ (and (match_code "const_double")
++ (match_test "aarch64_float_const_zero_rtx_p (op)"))))
+
+ (define_predicate "aarch64_reg_zero_or_m1_or_1"
+ (and (match_code "reg,subreg,const_int")
--- a/src/gcc/config/aarch64/t-aarch64
+++ b/src/gcc/config/aarch64/t-aarch64
-@@ -52,7 +52,7 @@ aarch-common.o: $(srcdir)/config/arm/aarch-common.c $(CONFIG_H) $(SYSTEM_H) \
+@@ -52,16 +52,17 @@ aarch-common.o: $(srcdir)/config/arm/aarch-common.c $(CONFIG_H) $(SYSTEM_H) \
$(srcdir)/config/arm/aarch-common.c
aarch64-c.o: $(srcdir)/config/aarch64/aarch64-c.c $(CONFIG_H) $(SYSTEM_H) \
@@ -50939,6 +51366,17 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
$(srcdir)/config/aarch64/aarch64-c.c
++PASSES_EXTRA += $(srcdir)/config/aarch64/aarch64-passes.def
++
+ cortex-a57-fma-steering.o: $(srcdir)/config/aarch64/cortex-a57-fma-steering.c \
+ $(CONFIG_H) $(SYSTEM_H) $(TM_H) $(REGS_H) insn-config.h $(RTL_BASE_H) \
+ dominance.h cfg.h cfganal.h $(BASIC_BLOCK_H) $(INSN_ATTR_H) $(RECOG_H) \
+ output.h hash-map.h $(DF_H) $(OBSTACK_H) $(TARGET_H) $(RTL_H) \
+ $(CONTEXT_H) $(TREE_PASS_H) regrename.h \
+- $(srcdir)/config/aarch64/cortex-a57-fma-steering.h \
+ $(srcdir)/config/aarch64/aarch64-protos.h
+ $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
+ $(srcdir)/config/aarch64/cortex-a57-fma-steering.c
--- a/src/gcc/config/aarch64/thunderx.md
+++ b/src/gcc/config/aarch64/thunderx.md
@@ -39,7 +39,7 @@
@@ -52037,7 +52475,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
+#endif /* GCC_ARM_FLAGS_H */
--- a/src/gcc/config/arm/arm-fpus.def
+++ b/src/gcc/config/arm/arm-fpus.def
-@@ -19,30 +19,29 @@
+@@ -19,30 +19,31 @@
/* Before using #include to read this file, define a macro:
@@ -52068,6 +52506,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
-ARM_FPU("crypto-neon-fp-armv8",
- ARM_FP_MODEL_VFP, 8, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16 | FPU_FL_CRYPTO)
+ARM_FPU("vfp", 2, VFP_REG_D16, FPU_FL_NONE)
++ARM_FPU("vfpv2", 2, VFP_REG_D16, FPU_FL_NONE)
+ARM_FPU("vfpv3", 3, VFP_REG_D32, FPU_FL_NONE)
+ARM_FPU("vfpv3-fp16", 3, VFP_REG_D32, FPU_FL_FP16)
+ARM_FPU("vfpv3-d16", 3, VFP_REG_D16, FPU_FL_NONE)
@@ -52075,6 +52514,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
+ARM_FPU("vfpv3xd", 3, VFP_REG_SINGLE, FPU_FL_NONE)
+ARM_FPU("vfpv3xd-fp16", 3, VFP_REG_SINGLE, FPU_FL_FP16)
+ARM_FPU("neon", 3, VFP_REG_D32, FPU_FL_NEON)
++ARM_FPU("neon-vfpv3", 3, VFP_REG_D32, FPU_FL_NEON)
+ARM_FPU("neon-fp16", 3, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16)
+ARM_FPU("vfpv4", 4, VFP_REG_D32, FPU_FL_FP16)
+ARM_FPU("vfpv4-d16", 4, VFP_REG_D16, FPU_FL_FP16)
@@ -52109,31 +52549,6 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* The various ARM cores. */
enum processor_type
{
-@@ -77,4 +79,24 @@ enum arm_tls_type {
- TLS_GNU,
- TLS_GNU2
- };
-+
-+struct arm_arch_core_flag
-+{
-+ const char *const name;
-+ const arm_feature_set flags;
-+};
-+
-+static const struct arm_arch_core_flag arm_arch_core_flags[] =
-+{
-+#undef ARM_CORE
-+#define ARM_CORE(NAME, X, IDENT, ARCH, FLAGS, COSTS) \
-+ {NAME, FLAGS},
-+#include "arm-cores.def"
-+#undef ARM_CORE
-+#undef ARM_ARCH
-+#define ARM_ARCH(NAME, CORE, ARCH, FLAGS) \
-+ {NAME, FLAGS},
-+#include "arm-arches.def"
-+#undef ARM_ARCH
-+};
- #endif
--- a/src/gcc/config/arm/arm-protos.h
+++ b/src/gcc/config/arm/arm-protos.h
@@ -22,6 +22,8 @@
@@ -52452,8 +52867,9 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
+
+EnumValue
+Enum(arm_arch) String(armv8.2-a+fp16) Value(30)
-+
-+EnumValue
+
+ EnumValue
+-Enum(arm_arch) String(iwmmxt2) Value(30)
+Enum(arm_arch) String(armv8-m.base) Value(31)
+
+EnumValue
@@ -52464,13 +52880,93 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
+
+EnumValue
+Enum(arm_arch) String(iwmmxt) Value(34)
-
- EnumValue
--Enum(arm_arch) String(iwmmxt2) Value(30)
++
++EnumValue
+Enum(arm_arch) String(iwmmxt2) Value(35)
Enum
Name(arm_fpu) Type(int)
+@@ -441,56 +471,62 @@ EnumValue
+ Enum(arm_fpu) String(vfp) Value(0)
+
+ EnumValue
+-Enum(arm_fpu) String(vfpv3) Value(1)
++Enum(arm_fpu) String(vfpv2) Value(1)
++
++EnumValue
++Enum(arm_fpu) String(vfpv3) Value(2)
++
++EnumValue
++Enum(arm_fpu) String(vfpv3-fp16) Value(3)
+
+ EnumValue
+-Enum(arm_fpu) String(vfpv3-fp16) Value(2)
++Enum(arm_fpu) String(vfpv3-d16) Value(4)
+
+ EnumValue
+-Enum(arm_fpu) String(vfpv3-d16) Value(3)
++Enum(arm_fpu) String(vfpv3-d16-fp16) Value(5)
+
+ EnumValue
+-Enum(arm_fpu) String(vfpv3-d16-fp16) Value(4)
++Enum(arm_fpu) String(vfpv3xd) Value(6)
+
+ EnumValue
+-Enum(arm_fpu) String(vfpv3xd) Value(5)
++Enum(arm_fpu) String(vfpv3xd-fp16) Value(7)
+
+ EnumValue
+-Enum(arm_fpu) String(vfpv3xd-fp16) Value(6)
++Enum(arm_fpu) String(neon) Value(8)
+
+ EnumValue
+-Enum(arm_fpu) String(neon) Value(7)
++Enum(arm_fpu) String(neon-vfpv3) Value(9)
+
+ EnumValue
+-Enum(arm_fpu) String(neon-fp16) Value(8)
++Enum(arm_fpu) String(neon-fp16) Value(10)
+
+ EnumValue
+-Enum(arm_fpu) String(vfpv4) Value(9)
++Enum(arm_fpu) String(vfpv4) Value(11)
+
+ EnumValue
+-Enum(arm_fpu) String(vfpv4-d16) Value(10)
++Enum(arm_fpu) String(vfpv4-d16) Value(12)
+
+ EnumValue
+-Enum(arm_fpu) String(fpv4-sp-d16) Value(11)
++Enum(arm_fpu) String(fpv4-sp-d16) Value(13)
+
+ EnumValue
+-Enum(arm_fpu) String(fpv5-sp-d16) Value(12)
++Enum(arm_fpu) String(fpv5-sp-d16) Value(14)
+
+ EnumValue
+-Enum(arm_fpu) String(fpv5-d16) Value(13)
++Enum(arm_fpu) String(fpv5-d16) Value(15)
+
+ EnumValue
+-Enum(arm_fpu) String(neon-vfpv4) Value(14)
++Enum(arm_fpu) String(neon-vfpv4) Value(16)
+
+ EnumValue
+-Enum(arm_fpu) String(fp-armv8) Value(15)
++Enum(arm_fpu) String(fp-armv8) Value(17)
+
+ EnumValue
+-Enum(arm_fpu) String(neon-fp-armv8) Value(16)
++Enum(arm_fpu) String(neon-fp-armv8) Value(18)
+
+ EnumValue
+-Enum(arm_fpu) String(crypto-neon-fp-armv8) Value(17)
++Enum(arm_fpu) String(crypto-neon-fp-armv8) Value(19)
+
+ EnumValue
+-Enum(arm_fpu) String(vfp3) Value(18)
++Enum(arm_fpu) String(vfp3) Value(20)
+
--- a/src/gcc/config/arm/arm-tune.md
+++ b/src/gcc/config/arm/arm-tune.md
@@ -32,8 +32,10 @@
@@ -52939,7 +53435,17 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
if (! opts_set->x_unaligned_access)
{
-@@ -3170,6 +3206,8 @@ arm_option_override (void)
+@@ -3152,9 +3188,6 @@ arm_option_override (void)
+ if (TARGET_APCS_REENT)
+ warning (0, "APCS reentrant code not supported. Ignored");
+
+- if (TARGET_APCS_FLOAT)
+- warning (0, "passing floating point arguments in fp regs not yet supported");
+-
+ /* Initialize boolean versions of the flags, for use in the arm.md file. */
+ arm_arch3m = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH3M);
+ arm_arch4 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH4);
+@@ -3170,6 +3203,8 @@ arm_option_override (void)
arm_arch7em = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH7EM);
arm_arch8 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH8);
arm_arch8_1 = ARM_FSET_HAS_CPU2 (insn_flags, FL2_ARCH8_1);
@@ -52948,7 +53454,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
arm_arch_thumb2 = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB2);
arm_arch_xscale = ARM_FSET_HAS_CPU1 (insn_flags, FL_XSCALE);
-@@ -3184,7 +3222,15 @@ arm_option_override (void)
+@@ -3184,7 +3219,15 @@ arm_option_override (void)
arm_arch_no_volatile_ce = ARM_FSET_HAS_CPU1 (insn_flags, FL_NO_VOLATILE_CE);
arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0;
arm_arch_crc = ARM_FSET_HAS_CPU1 (insn_flags, FL_CRC32);
@@ -52964,7 +53470,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* V5 code we generate is completely interworking capable, so we turn off
TARGET_INTERWORK here to avoid many tests later on. */
-@@ -3222,10 +3268,8 @@ arm_option_override (void)
+@@ -3222,10 +3265,8 @@ arm_option_override (void)
/* If soft-float is specified then don't use FPU. */
if (TARGET_SOFT_FLOAT)
arm_fpu_attr = FPU_NONE;
@@ -52976,7 +53482,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
if (TARGET_AAPCS_BASED)
{
-@@ -3245,15 +3289,14 @@ arm_option_override (void)
+@@ -3245,15 +3286,14 @@ arm_option_override (void)
if (arm_abi == ARM_ABI_IWMMXT)
arm_pcs_default = ARM_PCS_AAPCS_IWMMXT;
else if (arm_float_abi == ARM_FLOAT_ABI_HARD
@@ -52994,7 +53500,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
sorry ("-mfloat-abi=hard and VFP");
if (arm_abi == ARM_ABI_APCS)
-@@ -3298,6 +3341,20 @@ arm_option_override (void)
+@@ -3298,6 +3338,20 @@ arm_option_override (void)
}
}
@@ -53015,7 +53521,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* If stack checking is disabled, we can use r10 as the PIC register,
which keeps r9 available. The EABI specifies r9 as the PIC register. */
if (flag_pic && TARGET_SINGLE_PIC_BASE)
-@@ -3329,10 +3386,6 @@ arm_option_override (void)
+@@ -3329,10 +3383,6 @@ arm_option_override (void)
arm_pic_register = pic_register;
}
@@ -53026,7 +53532,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* Enable -mfix-cortex-m3-ldrd by default for Cortex-M3 cores. */
if (fix_cm3_ldrd == 2)
{
-@@ -3436,6 +3489,9 @@ arm_option_override (void)
+@@ -3436,6 +3486,9 @@ arm_option_override (void)
if (target_slow_flash_data)
arm_disable_literal_pool = true;
@@ -53036,7 +53542,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* Disable scheduling fusion by default if it's not armv7 processor
or doesn't prefer ldrd/strd. */
if (flag_schedule_fusion == 2
-@@ -3568,6 +3624,9 @@ arm_compute_func_type (void)
+@@ -3568,6 +3621,9 @@ arm_compute_func_type (void)
else
type |= arm_isr_value (TREE_VALUE (a));
@@ -53046,7 +53552,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
return type;
}
-@@ -3794,6 +3853,11 @@ use_return_insn (int iscond, rtx sibling)
+@@ -3794,6 +3850,11 @@ use_return_insn (int iscond, rtx sibling)
return 0;
}
@@ -53058,7 +53564,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* If there are saved registers but the LR isn't saved, then we need
two instructions for the return. */
if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
-@@ -3801,7 +3865,7 @@ use_return_insn (int iscond, rtx sibling)
+@@ -3801,7 +3862,7 @@ use_return_insn (int iscond, rtx sibling)
/* Can't be done if any of the VFP regs are pushed,
since this also requires an insn. */
@@ -53067,7 +53573,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
return 0;
-@@ -3899,7 +3963,7 @@ const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
+@@ -3899,7 +3960,7 @@ const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
{
case SET:
/* See if we can use movw. */
@@ -53076,7 +53582,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
return 1;
else
/* Otherwise, try mvn. */
-@@ -4118,7 +4182,7 @@ optimal_immediate_sequence (enum rtx_code code, unsigned HOST_WIDE_INT val,
+@@ -4118,7 +4179,7 @@ optimal_immediate_sequence (enum rtx_code code, unsigned HOST_WIDE_INT val,
yield a shorter sequence, we may as well use zero. */
insns1 = optimal_immediate_sequence_1 (code, val, return_sequence, best_start);
if (best_start != 0
@@ -53085,7 +53591,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
{
insns2 = optimal_immediate_sequence_1 (code, val, &tmp_sequence, 0);
if (insns2 <= insns1)
-@@ -4949,7 +5013,7 @@ arm_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
+@@ -4949,7 +5010,7 @@ arm_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
if (mode == VOIDmode)
mode = GET_MODE (*op1);
@@ -53094,7 +53600,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* For DImode, we have GE/LT/GEU/LTU comparisons. In ARM mode
we can also use cmp/cmpeq for GTU/LEU. GT/LE must be either
-@@ -5255,7 +5319,6 @@ arm_function_value_regno_p (const unsigned int regno)
+@@ -5255,7 +5316,6 @@ arm_function_value_regno_p (const unsigned int regno)
if (regno == ARG_REGISTER (1)
|| (TARGET_32BIT
&& TARGET_AAPCS_BASED
@@ -53102,7 +53608,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
&& TARGET_HARD_FLOAT
&& regno == FIRST_VFP_REGNUM)
|| (TARGET_IWMMXT_ABI
-@@ -5274,7 +5337,7 @@ arm_apply_result_size (void)
+@@ -5274,7 +5334,7 @@ arm_apply_result_size (void)
if (TARGET_32BIT)
{
@@ -53111,7 +53617,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
size += 32;
if (TARGET_IWMMXT_ABI)
size += 8;
-@@ -5549,7 +5612,7 @@ aapcs_vfp_sub_candidate (const_tree type, machine_mode *modep)
+@@ -5549,7 +5609,7 @@ aapcs_vfp_sub_candidate (const_tree type, machine_mode *modep)
{
case REAL_TYPE:
mode = TYPE_MODE (type);
@@ -53120,7 +53626,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
return -1;
if (*modep == VOIDmode)
-@@ -5722,7 +5785,7 @@ use_vfp_abi (enum arm_pcs pcs_variant, bool is_double)
+@@ -5722,7 +5782,7 @@ use_vfp_abi (enum arm_pcs pcs_variant, bool is_double)
if (pcs_variant != ARM_PCS_AAPCS_LOCAL)
return false;
@@ -53129,7 +53635,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
(TARGET_VFP_DOUBLE || !is_double));
}
-@@ -5797,11 +5860,16 @@ aapcs_vfp_is_call_candidate (CUMULATIVE_ARGS *pcum, machine_mode mode,
+@@ -5797,11 +5857,16 @@ aapcs_vfp_is_call_candidate (CUMULATIVE_ARGS *pcum, machine_mode mode,
&pcum->aapcs_vfp_rcount);
}
@@ -53147,7 +53653,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
unsigned mask = (1 << (shift * pcum->aapcs_vfp_rcount)) - 1;
int regno;
-@@ -5850,6 +5918,9 @@ aapcs_vfp_allocate (CUMULATIVE_ARGS *pcum, machine_mode mode,
+@@ -5850,6 +5915,9 @@ aapcs_vfp_allocate (CUMULATIVE_ARGS *pcum, machine_mode mode,
return false;
}
@@ -53157,7 +53663,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
static rtx
aapcs_vfp_allocate_return_reg (enum arm_pcs pcs_variant ATTRIBUTE_UNUSED,
machine_mode mode,
-@@ -5940,13 +6011,13 @@ static struct
+@@ -5940,13 +6008,13 @@ static struct
required for a return from FUNCTION_ARG. */
bool (*allocate) (CUMULATIVE_ARGS *, machine_mode, const_tree);
@@ -53176,7 +53682,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
rtx (*allocate_return_reg) (enum arm_pcs, machine_mode, const_tree);
/* Finish processing this argument and prepare to start processing
-@@ -6561,6 +6632,185 @@ arm_handle_notshared_attribute (tree *node,
+@@ -6561,6 +6629,185 @@ arm_handle_notshared_attribute (tree *node,
}
#endif
@@ -53362,7 +53868,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* Return 0 if the attributes for two types are incompatible, 1 if they
are compatible, and 2 if they are nearly compatible (which causes a
warning to be generated). */
-@@ -6601,6 +6851,14 @@ arm_comp_type_attributes (const_tree type1, const_tree type2)
+@@ -6601,6 +6848,14 @@ arm_comp_type_attributes (const_tree type1, const_tree type2)
if (l1 != l2)
return 0;
@@ -53377,7 +53883,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
return 1;
}
-@@ -6711,7 +6969,7 @@ arm_function_ok_for_sibcall (tree decl, tree exp)
+@@ -6711,7 +6966,7 @@ arm_function_ok_for_sibcall (tree decl, tree exp)
may be used both as target of the call and base register for restoring
the VFP registers */
if (TARGET_APCS_FRAME && TARGET_ARM
@@ -53386,7 +53892,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
&& decl && arm_is_long_call_p (decl))
return false;
-@@ -6727,6 +6985,20 @@ arm_function_ok_for_sibcall (tree decl, tree exp)
+@@ -6727,6 +6982,20 @@ arm_function_ok_for_sibcall (tree decl, tree exp)
if (IS_INTERRUPT (func_type))
return false;
@@ -53407,7 +53913,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
{
/* Check that the return value locations are the same. For
-@@ -7187,8 +7459,7 @@ arm_legitimate_address_outer_p (machine_mode mode, rtx x, RTX_CODE outer,
+@@ -7187,8 +7456,7 @@ arm_legitimate_address_outer_p (machine_mode mode, rtx x, RTX_CODE outer,
return 1;
use_ldrd = (TARGET_LDRD
@@ -53417,7 +53923,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
if (code == POST_INC || code == PRE_DEC
|| ((code == PRE_INC || code == POST_DEC)
-@@ -7273,8 +7544,7 @@ thumb2_legitimate_address_p (machine_mode mode, rtx x, int strict_p)
+@@ -7273,8 +7541,7 @@ thumb2_legitimate_address_p (machine_mode mode, rtx x, int strict_p)
return 1;
use_ldrd = (TARGET_LDRD
@@ -53427,7 +53933,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
if (code == POST_INC || code == PRE_DEC
|| ((code == PRE_INC || code == POST_DEC)
-@@ -7367,7 +7637,6 @@ arm_legitimate_index_p (machine_mode mode, rtx index, RTX_CODE outer,
+@@ -7367,7 +7634,6 @@ arm_legitimate_index_p (machine_mode mode, rtx index, RTX_CODE outer,
/* Standard coprocessor addressing modes. */
if (TARGET_HARD_FLOAT
@@ -53435,7 +53941,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
&& (mode == SFmode || mode == DFmode))
return (code == CONST_INT && INTVAL (index) < 1024
&& INTVAL (index) > -1024
-@@ -7487,7 +7756,6 @@ thumb2_legitimate_index_p (machine_mode mode, rtx index, int strict_p)
+@@ -7487,7 +7753,6 @@ thumb2_legitimate_index_p (machine_mode mode, rtx index, int strict_p)
/* ??? Combine arm and thumb2 coprocessor addressing modes. */
/* Standard coprocessor addressing modes. */
if (TARGET_HARD_FLOAT
@@ -53443,7 +53949,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
&& (mode == SFmode || mode == DFmode))
return (code == CONST_INT && INTVAL (index) < 1024
/* Thumb-2 allows only > -256 index range for it's core register
-@@ -8033,8 +8301,7 @@ arm_legitimize_address (rtx x, rtx orig_x, machine_mode mode)
+@@ -8033,8 +8298,7 @@ arm_legitimize_address (rtx x, rtx orig_x, machine_mode mode)
/* VFP addressing modes actually allow greater offsets, but for
now we just stick with the lowest common denominator. */
@@ -53453,7 +53959,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
{
low_n = n & 0x0f;
n &= ~0x0f;
-@@ -8226,6 +8493,12 @@ arm_legitimate_constant_p_1 (machine_mode, rtx x)
+@@ -8226,6 +8490,12 @@ arm_legitimate_constant_p_1 (machine_mode, rtx x)
static bool
thumb_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
{
@@ -53466,7 +53972,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
return (CONST_INT_P (x)
|| CONST_DOUBLE_P (x)
|| CONSTANT_ADDRESS_P (x)
-@@ -8312,7 +8585,9 @@ thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
+@@ -8312,7 +8582,9 @@ thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
case CONST_INT:
if (outer == SET)
{
@@ -53477,7 +53983,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
return 0;
if (thumb_shiftable_const (INTVAL (x)))
return COSTS_N_INSNS (2);
-@@ -8329,8 +8604,8 @@ thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
+@@ -8329,8 +8601,8 @@ thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
int i;
/* This duplicates the tests in the andsi3 expander. */
for (i = 9; i <= 31; i++)
@@ -53488,7 +53994,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
return COSTS_N_INSNS (2);
}
else if (outer == ASHIFT || outer == ASHIFTRT
-@@ -8393,1006 +8668,162 @@ thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
+@@ -8393,1006 +8665,162 @@ thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
}
}
@@ -53514,7 +54020,12 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
- load at the equivalent of a single insn each. */
- *total = COSTS_N_INSNS (2 + ARM_NUM_REGS (mode));
- return true;
--
++ case ASHIFT:
++ case ASHIFTRT:
++ case LSHIFTRT:
++ case ROTATERT:
++ return (mode == SImode) ? COSTS_N_INSNS (1) : COSTS_N_INSNS (2);
+
- case DIV:
- case MOD:
- case UDIV:
@@ -53526,33 +54037,6 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
- else
- *total = COSTS_N_INSNS (20);
- return false;
--
-- case ROTATE:
-- if (REG_P (XEXP (x, 1)))
-- *total = COSTS_N_INSNS (1); /* Need to subtract from 32 */
-- else if (!CONST_INT_P (XEXP (x, 1)))
-- *total = rtx_cost (XEXP (x, 1), mode, code, 1, speed);
--
-- /* Fall through */
-+ case ASHIFT:
-+ case ASHIFTRT:
-+ case LSHIFTRT:
- case ROTATERT:
-- if (mode != SImode)
-- {
-- *total += COSTS_N_INSNS (4);
-- return true;
-- }
-+ return (mode == SImode) ? COSTS_N_INSNS (1) : COSTS_N_INSNS (2);
-
-- /* Fall through */
-- case ASHIFT: case LSHIFTRT: case ASHIFTRT:
-- *total += rtx_cost (XEXP (x, 0), mode, code, 0, speed);
-- if (mode == DImode)
-- {
-- *total += COSTS_N_INSNS (3);
-- return true;
-- }
+ case PLUS:
+ case MINUS:
+ /* Thumb-1 needs two instructions to fulfill shiftadd/shiftsub0/shiftsub1
@@ -53569,12 +54053,11 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
+ case NOT:
+ return COSTS_N_INSNS (1);
-- *total += COSTS_N_INSNS (1);
-- /* Increase the cost of complex shifts because they aren't any faster,
-- and reduce dual issue opportunities. */
-- if (arm_tune_cortex_a9
-- && outer != SET && !CONST_INT_P (XEXP (x, 1)))
-- ++*total;
+- case ROTATE:
+- if (REG_P (XEXP (x, 1)))
+- *total = COSTS_N_INSNS (1); /* Need to subtract from 32 */
+- else if (!CONST_INT_P (XEXP (x, 1)))
+- *total = rtx_cost (XEXP (x, 1), mode, code, 1, speed);
+ case MULT:
+ if (CONST_INT_P (XEXP (x, 1)))
+ {
@@ -53591,7 +54074,13 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
+ }
+ return COSTS_N_INSNS (1);
-- return true;
+- /* Fall through */
+- case ROTATERT:
+- if (mode != SImode)
+- {
+- *total += COSTS_N_INSNS (4);
+- return true;
+- }
+ case SET:
+ /* A SET doesn't have a mode, so let's look at the SET_DEST to get
+ the mode. */
@@ -53609,16 +54098,14 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
+ cost += COSTS_N_INSNS (1);
+ return cost;
-- case MINUS:
+- /* Fall through */
+- case ASHIFT: case LSHIFTRT: case ASHIFTRT:
+- *total += rtx_cost (XEXP (x, 0), mode, code, 0, speed);
- if (mode == DImode)
- {
-- *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
-- if (CONST_INT_P (XEXP (x, 0))
-- && const_ok_for_arm (INTVAL (XEXP (x, 0))))
-- {
-- *total += rtx_cost (XEXP (x, 1), mode, code, 1, speed);
-- return true;
-- }
+- *total += COSTS_N_INSNS (3);
+- return true;
+- }
+ case CONST_INT:
+ if (outer == SET)
+ {
@@ -53655,18 +54142,43 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
+ return 0;
+ return COSTS_N_INSNS (2);
-- if (CONST_INT_P (XEXP (x, 1))
-- && const_ok_for_arm (INTVAL (XEXP (x, 1))))
-- {
-- *total += rtx_cost (XEXP (x, 0), mode, code, 0, speed);
-- return true;
-- }
+- *total += COSTS_N_INSNS (1);
+- /* Increase the cost of complex shifts because they aren't any faster,
+- and reduce dual issue opportunities. */
+- if (arm_tune_cortex_a9
+- && outer != SET && !CONST_INT_P (XEXP (x, 1)))
+- ++*total;
+ case CONST:
+ case CONST_DOUBLE:
+ case LABEL_REF:
+ case SYMBOL_REF:
+ return COSTS_N_INSNS (3);
+- return true;
++ case UDIV:
++ case UMOD:
++ case DIV:
++ case MOD:
++ return 100;
+
+- case MINUS:
+- if (mode == DImode)
+- {
+- *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
+- if (CONST_INT_P (XEXP (x, 0))
+- && const_ok_for_arm (INTVAL (XEXP (x, 0))))
+- {
+- *total += rtx_cost (XEXP (x, 1), mode, code, 1, speed);
+- return true;
+- }
+-
+- if (CONST_INT_P (XEXP (x, 1))
+- && const_ok_for_arm (INTVAL (XEXP (x, 1))))
+- {
+- *total += rtx_cost (XEXP (x, 0), mode, code, 0, speed);
+- return true;
+- }
+-
- return false;
- }
-
@@ -54507,22 +55019,29 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
- *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
-
- return false;
--
++ case TRUNCATE:
++ return 99;
+
- case IF_THEN_ELSE:
- *total = 0;
- return false;
--
++ case AND:
++ case XOR:
++ case IOR:
++ return COSTS_N_INSNS (1);
+
- case COMPARE:
- if (cc_register (XEXP (x, 0), VOIDmode))
- * total = 0;
- else
- *total = COSTS_N_INSNS (1);
- return false;
-+ case UDIV:
-+ case UMOD:
-+ case DIV:
-+ case MOD:
-+ return 100;
++ case MEM:
++ return (COSTS_N_INSNS (1)
++ + COSTS_N_INSNS (1)
++ * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
++ + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
++ ? COSTS_N_INSNS (1) : 0));
- case ABS:
- if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
@@ -54531,17 +55050,16 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
- else
- *total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode));
- return false;
-+ case TRUNCATE:
-+ return 99;
++ case IF_THEN_ELSE:
++ /* XXX a guess. */
++ if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
++ return 14;
++ return 2;
- case SIGN_EXTEND:
-- case ZERO_EXTEND:
+ case ZERO_EXTEND:
- return arm_rtx_costs_1 (x, outer_code, total, 0);
-+ case AND:
-+ case XOR:
-+ case IOR:
-+ return COSTS_N_INSNS (1);
-
+-
- case CONST_INT:
- if (const_ok_for_arm (INTVAL (x)))
- /* A multiplication by a constant requires another instruction
@@ -54561,28 +55079,16 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
- else
- *total = COSTS_N_INSNS (2);
- return true;
-+ case MEM:
-+ return (COSTS_N_INSNS (1)
-+ + COSTS_N_INSNS (1)
-+ * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
-+ + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
-+ ? COSTS_N_INSNS (1) : 0));
-
+-
- case CONST:
- case LABEL_REF:
- case SYMBOL_REF:
- *total = COSTS_N_INSNS (2);
- return true;
-+ case IF_THEN_ELSE:
-+ /* XXX a guess. */
-+ if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
-+ return 14;
-+ return 2;
-
+-
- case CONST_DOUBLE:
- *total = COSTS_N_INSNS (4);
- return true;
-+ case ZERO_EXTEND:
+ /* XXX still guessing. */
+ switch (GET_MODE (XEXP (x, 0)))
+ {
@@ -54629,7 +55135,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
}
}
-@@ -9519,7 +8950,7 @@ arm_unspec_cost (rtx x, enum rtx_code /* outer_code */, bool speed_p, int *cost)
+@@ -9519,7 +8947,7 @@ arm_unspec_cost (rtx x, enum rtx_code /* outer_code */, bool speed_p, int *cost)
flags are live or not, and thus no realistic way to determine what
the size will eventually be. */
static bool
@@ -54638,7 +55144,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
const struct cpu_cost_table *extra_cost,
int *cost, bool speed_p)
{
-@@ -10771,8 +10202,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
+@@ -10771,8 +10199,6 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
if ((arm_arch4 || GET_MODE (XEXP (x, 0)) == SImode)
&& MEM_P (XEXP (x, 0)))
{
@@ -54647,7 +55153,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
if (mode == DImode)
*cost += COSTS_N_INSNS (1);
-@@ -11164,390 +10593,70 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
+@@ -11164,390 +10590,70 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code,
/* Vector costs? */
}
*cost = LIBCALL_COST (1);
@@ -55083,7 +55589,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* All address computations that can be done are free, but rtx cost returns
the same for practically all of them. So we weight the different types
of address here in the order (most pref first):
-@@ -12269,7 +11378,7 @@ vfp3_const_double_index (rtx x)
+@@ -12269,7 +11375,7 @@ vfp3_const_double_index (rtx x)
/* We can permit four significant bits of mantissa only, plus a high bit
which is always 1. */
@@ -55092,7 +55598,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
if ((mantissa & mask) != 0)
return -1;
-@@ -12423,6 +11532,12 @@ neon_valid_immediate (rtx op, machine_mode mode, int inverse,
+@@ -12423,6 +11529,12 @@ neon_valid_immediate (rtx op, machine_mode mode, int inverse,
return 18;
}
@@ -55105,7 +55611,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* Splat vector constant out into a byte vector. */
for (i = 0; i < n_elts; i++)
{
-@@ -13151,7 +12266,7 @@ coproc_secondary_reload_class (machine_mode mode, rtx x, bool wb)
+@@ -13151,7 +12263,7 @@ coproc_secondary_reload_class (machine_mode mode, rtx x, bool wb)
{
if (mode == HFmode)
{
@@ -55114,7 +55620,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
return GENERAL_REGS;
if (s_register_operand (x, mode) || neon_vector_mem_operand (x, 2, true))
return NO_REGS;
-@@ -15988,14 +15103,17 @@ gen_operands_ldrd_strd (rtx *operands, bool load,
+@@ -15988,14 +15100,17 @@ gen_operands_ldrd_strd (rtx *operands, bool load,
/* If the same input register is used in both stores
when storing different constants, try to find a free register.
For example, the code
@@ -55139,7 +55645,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
if (const_store
&& REGNO (operands[0]) == REGNO (operands[1])
&& INTVAL (operands[4]) != INTVAL (operands[5]))
-@@ -16014,7 +15132,6 @@ gen_operands_ldrd_strd (rtx *operands, bool load,
+@@ -16014,7 +15129,6 @@ gen_operands_ldrd_strd (rtx *operands, bool load,
}
else if (TARGET_ARM)
{
@@ -55147,7 +55653,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
int regno = REGNO (operands[0]);
if (!peep2_reg_dead_p (4, operands[0]))
{
-@@ -16368,7 +15485,7 @@ get_jump_table_size (rtx_jump_table_data *insn)
+@@ -16368,7 +15482,7 @@ get_jump_table_size (rtx_jump_table_data *insn)
{
case 1:
/* Round up size of TBB table to a halfword boundary. */
@@ -55156,7 +55662,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
break;
case 2:
/* No padding necessary for TBH. */
-@@ -16837,35 +15954,37 @@ dump_minipool (rtx_insn *scan)
+@@ -16837,35 +15951,37 @@ dump_minipool (rtx_insn *scan)
fputc ('\n', dump_file);
}
@@ -55199,7 +55705,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
break;
#endif
-@@ -17269,6 +16388,470 @@ note_invalid_constants (rtx_insn *insn, HOST_WIDE_INT address, int do_pushes)
+@@ -17269,6 +16385,470 @@ note_invalid_constants (rtx_insn *insn, HOST_WIDE_INT address, int do_pushes)
return;
}
@@ -55670,7 +56176,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* Rewrite move insn into subtract of 0 if the condition codes will
be useful in next conditional jump insn. */
-@@ -17569,6 +17152,8 @@ arm_reorg (void)
+@@ -17569,6 +17149,8 @@ arm_reorg (void)
HOST_WIDE_INT address = 0;
Mfix * fix;
@@ -55679,7 +56185,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
if (TARGET_THUMB1)
thumb1_reorg ();
else if (TARGET_THUMB2)
-@@ -17941,6 +17526,23 @@ vfp_emit_fstmd (int base_reg, int count)
+@@ -17941,6 +17523,23 @@ vfp_emit_fstmd (int base_reg, int count)
return count * 8;
}
@@ -55703,7 +56209,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* Emit a call instruction with pattern PAT. ADDR is the address of
the call target. */
-@@ -18600,6 +18202,8 @@ output_move_vfp (rtx *operands)
+@@ -18600,6 +18199,8 @@ output_move_vfp (rtx *operands)
rtx reg, mem, addr, ops[2];
int load = REG_P (operands[0]);
int dp = GET_MODE_SIZE (GET_MODE (operands[0])) == 8;
@@ -55712,7 +56218,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
int integer_p = GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT;
const char *templ;
char buff[50];
-@@ -18612,8 +18216,10 @@ output_move_vfp (rtx *operands)
+@@ -18612,8 +18213,10 @@ output_move_vfp (rtx *operands)
gcc_assert (REG_P (reg));
gcc_assert (IS_VFP_REGNUM (REGNO (reg)));
@@ -55724,7 +56230,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
|| mode == SImode
|| mode == DImode
|| (TARGET_NEON && VALID_NEON_DREG_MODE (mode)));
-@@ -18644,7 +18250,7 @@ output_move_vfp (rtx *operands)
+@@ -18644,7 +18247,7 @@ output_move_vfp (rtx *operands)
sprintf (buff, templ,
load ? "ld" : "st",
@@ -55733,7 +56239,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
dp ? "P" : "",
integer_p ? "\t%@ int" : "");
output_asm_insn (buff, ops);
-@@ -19070,7 +18676,8 @@ shift_op (rtx op, HOST_WIDE_INT *amountp)
+@@ -19070,7 +18673,8 @@ shift_op (rtx op, HOST_WIDE_INT *amountp)
return NULL;
}
@@ -55743,7 +56249,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
return ARM_LSL_NAME;
default:
-@@ -19102,22 +18709,6 @@ shift_op (rtx op, HOST_WIDE_INT *amountp)
+@@ -19102,22 +18706,6 @@ shift_op (rtx op, HOST_WIDE_INT *amountp)
return mnem;
}
@@ -55766,7 +56272,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* Output a .ascii pseudo-op, keeping track of lengths. This is
because /bin/as is horribly restrictive. The judgement about
whether or not each character is 'printable' (and can be output as
-@@ -19474,7 +19065,7 @@ arm_get_vfp_saved_size (void)
+@@ -19474,7 +19062,7 @@ arm_get_vfp_saved_size (void)
saved = 0;
/* Space for saved VFP registers. */
@@ -55775,7 +56281,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
{
count = 0;
for (regno = FIRST_VFP_REGNUM;
-@@ -19563,6 +19154,7 @@ output_return_instruction (rtx operand, bool really_return, bool reverse,
+@@ -19563,6 +19151,7 @@ output_return_instruction (rtx operand, bool really_return, bool reverse,
(e.g. interworking) then we can load the return address
directly into the PC. Otherwise we must load it into LR. */
if (really_return
@@ -55783,7 +56289,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
&& (IS_INTERRUPT (func_type) || !TARGET_INTERWORK))
return_reg = reg_names[PC_REGNUM];
else
-@@ -19703,18 +19295,93 @@ output_return_instruction (rtx operand, bool really_return, bool reverse,
+@@ -19703,18 +19292,93 @@ output_return_instruction (rtx operand, bool really_return, bool reverse,
break;
default:
@@ -55880,7 +56386,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
}
/* Write the function name into the code section, directly preceding
-@@ -19766,10 +19433,6 @@ arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
+@@ -19766,10 +19430,6 @@ arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
{
unsigned long func_type;
@@ -55891,7 +56397,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* Sanity check. */
gcc_assert (!arm_ccfsm_state && !arm_target_insn);
-@@ -19804,6 +19467,8 @@ arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
+@@ -19804,6 +19464,8 @@ arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
if (IS_STACKALIGN (func_type))
asm_fprintf (f, "\t%@ Stack Align: May be called with mis-aligned SP.\n");
@@ -55900,7 +56406,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
crtl->args.size,
-@@ -20473,7 +20138,7 @@ arm_emit_vfp_multi_reg_pop (int first_reg, int num_regs, rtx base_reg)
+@@ -20473,7 +20135,7 @@ arm_emit_vfp_multi_reg_pop (int first_reg, int num_regs, rtx base_reg)
REG_NOTES (par) = dwarf;
/* Make sure cfa doesn't leave with IP_REGNUM to allow unwinding fron FP. */
@@ -55909,7 +56415,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
{
RTX_FRAME_RELATED_P (par) = 1;
add_reg_note (par, REG_CFA_DEF_CFA, hard_frame_pointer_rtx);
-@@ -20934,7 +20599,7 @@ arm_get_frame_offsets (void)
+@@ -20934,7 +20596,7 @@ arm_get_frame_offsets (void)
func_type = arm_current_func_type ();
/* Space for saved VFP registers. */
if (! IS_VOLATILE (func_type)
@@ -55918,7 +56424,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
saved += arm_get_vfp_saved_size ();
}
else /* TARGET_THUMB1 */
-@@ -21155,7 +20820,7 @@ arm_save_coproc_regs(void)
+@@ -21155,7 +20817,7 @@ arm_save_coproc_regs(void)
saved_size += 8;
}
@@ -55927,7 +56433,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
{
start_reg = FIRST_VFP_REGNUM;
-@@ -22941,6 +22606,8 @@ maybe_get_arm_condition_code (rtx comparison)
+@@ -22941,6 +22603,8 @@ maybe_get_arm_condition_code (rtx comparison)
{
case LTU: return ARM_CS;
case GEU: return ARM_CC;
@@ -55936,7 +56442,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
default: return ARM_NV;
}
-@@ -22966,6 +22633,14 @@ maybe_get_arm_condition_code (rtx comparison)
+@@ -22966,6 +22630,14 @@ maybe_get_arm_condition_code (rtx comparison)
default: return ARM_NV;
}
@@ -55951,7 +56457,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
case CCmode:
switch (comp_code)
{
-@@ -23396,7 +23071,7 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
+@@ -23396,7 +23068,7 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
{
if (GET_MODE_CLASS (mode) == MODE_CC)
return (regno == CC_REGNUM
@@ -55960,7 +56466,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
&& regno == VFPCC_REGNUM));
if (regno == CC_REGNUM && GET_MODE_CLASS (mode) != MODE_CC)
-@@ -23410,8 +23085,7 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
+@@ -23410,8 +23082,7 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
start of an even numbered register pair. */
return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
@@ -55970,7 +56476,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
{
if (mode == SFmode || mode == SImode)
return VFP_REGNO_OK_FOR_SINGLE (regno);
-@@ -23419,10 +23093,12 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
+@@ -23419,10 +23090,12 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
if (mode == DFmode)
return VFP_REGNO_OK_FOR_DOUBLE (regno);
@@ -55986,7 +56492,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
if (TARGET_NEON)
return (VALID_NEON_DREG_MODE (mode) && VFP_REGNO_OK_FOR_DOUBLE (regno))
-@@ -23626,26 +23302,6 @@ arm_debugger_arg_offset (int value, rtx addr)
+@@ -23626,26 +23299,6 @@ arm_debugger_arg_offset (int value, rtx addr)
return value;
}
@@ -56013,7 +56519,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* Implement TARGET_PROMOTED_TYPE. */
static tree
-@@ -23885,8 +23541,8 @@ thumb_pop (FILE *f, unsigned long mask)
+@@ -23885,8 +23538,8 @@ thumb_pop (FILE *f, unsigned long mask)
if (mask & (1 << PC_REGNUM))
{
/* Catch popping the PC. */
@@ -56024,7 +56530,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
{
/* The PC is never poped directly, instead
it is popped into r3 and then BX is used. */
-@@ -23947,7 +23603,14 @@ thumb_exit (FILE *f, int reg_containing_return_addr)
+@@ -23947,7 +23600,14 @@ thumb_exit (FILE *f, int reg_containing_return_addr)
if (crtl->calls_eh_return)
asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
@@ -56040,7 +56546,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
return;
}
/* Otherwise if we are not supporting interworking and we have not created
-@@ -23956,7 +23619,8 @@ thumb_exit (FILE *f, int reg_containing_return_addr)
+@@ -23956,7 +23616,8 @@ thumb_exit (FILE *f, int reg_containing_return_addr)
else if (!TARGET_INTERWORK
&& !TARGET_BACKTRACE
&& !is_called_in_ARM_mode (current_function_decl)
@@ -56050,7 +56556,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
{
asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
return;
-@@ -24179,7 +23843,21 @@ thumb_exit (FILE *f, int reg_containing_return_addr)
+@@ -24179,7 +23840,21 @@ thumb_exit (FILE *f, int reg_containing_return_addr)
asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
/* Return to caller. */
@@ -56073,7 +56579,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
}
/* Scan INSN just before assembler is output for it.
-@@ -25044,6 +24722,149 @@ thumb1_expand_prologue (void)
+@@ -25044,6 +24719,149 @@ thumb1_expand_prologue (void)
cfun->machine->lr_save_eliminated = 0;
}
@@ -56223,7 +56729,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* Generate pattern *pop_multiple_with_stack_update_and_return if single
POP instruction can be generated. LR should be replaced by PC. All
the checks required are already done by USE_RETURN_INSN (). Hence,
-@@ -25065,6 +24886,12 @@ thumb2_expand_return (bool simple_return)
+@@ -25065,6 +24883,12 @@ thumb2_expand_return (bool simple_return)
if (!simple_return && saved_regs_mask)
{
@@ -56236,7 +56742,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
if (num_regs == 1)
{
rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
-@@ -25087,6 +24914,8 @@ thumb2_expand_return (bool simple_return)
+@@ -25087,6 +24911,8 @@ thumb2_expand_return (bool simple_return)
}
else
{
@@ -56245,7 +56751,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
emit_jump_insn (simple_return_rtx);
}
}
-@@ -25145,6 +24974,10 @@ thumb1_expand_epilogue (void)
+@@ -25145,6 +24971,10 @@ thumb1_expand_epilogue (void)
if (! df_regs_ever_live_p (LR_REGNUM))
emit_use (gen_rtx_REG (SImode, LR_REGNUM));
@@ -56256,7 +56762,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
}
/* Epilogue code for APCS frame. */
-@@ -25179,7 +25012,7 @@ arm_expand_epilogue_apcs_frame (bool really_return)
+@@ -25179,7 +25009,7 @@ arm_expand_epilogue_apcs_frame (bool really_return)
floats_from_frame += 4;
}
@@ -56265,7 +56771,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
{
int start_reg;
rtx ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
-@@ -25425,7 +25258,7 @@ arm_expand_epilogue (bool really_return)
+@@ -25425,7 +25255,7 @@ arm_expand_epilogue (bool really_return)
}
}
@@ -56274,7 +56780,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
{
/* Generate VFP register multi-pop. */
int end_reg = LAST_VFP_REGNUM + 1;
-@@ -25482,6 +25315,7 @@ arm_expand_epilogue (bool really_return)
+@@ -25482,6 +25312,7 @@ arm_expand_epilogue (bool really_return)
if (ARM_FUNC_TYPE (func_type) != ARM_FT_INTERWORKED
&& (TARGET_ARM || ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
@@ -56282,7 +56788,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
&& !IS_STACKALIGN (func_type)
&& really_return
&& crtl->args.pretend_args_size == 0
-@@ -25578,6 +25412,14 @@ arm_expand_epilogue (bool really_return)
+@@ -25578,6 +25409,14 @@ arm_expand_epilogue (bool really_return)
stack_pointer_rtx, stack_pointer_rtx);
}
@@ -56297,7 +56803,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
if (!really_return)
return;
-@@ -25874,13 +25716,6 @@ thumb_reload_out_hi (rtx *operands)
+@@ -25874,13 +25713,6 @@ thumb_reload_out_hi (rtx *operands)
emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
}
@@ -56311,7 +56817,87 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* Return the length of a function name prefix
that starts with the character 'c'. */
static int
-@@ -26018,7 +25853,7 @@ arm_file_start (void)
+@@ -25950,46 +25782,55 @@ arm_emit_eabi_attribute (const char *name, int num, int val)
+ void
+ arm_print_tune_info (void)
+ {
+- asm_fprintf (asm_out_file, "\t at .tune parameters\n");
+- asm_fprintf (asm_out_file, "\t\t at constant_limit:\t%d\n",
++ asm_fprintf (asm_out_file, "\t" ASM_COMMENT_START ".tune parameters\n");
++ asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START "constant_limit:\t%d\n",
+ current_tune->constant_limit);
+- asm_fprintf (asm_out_file, "\t\t at max_insns_skipped:\t%d\n",
+- current_tune->max_insns_skipped);
+- asm_fprintf (asm_out_file, "\t\t at prefetch.num_slots:\t%d\n",
+- current_tune->prefetch.num_slots);
+- asm_fprintf (asm_out_file, "\t\t at prefetch.l1_cache_size:\t%d\n",
++ asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START
++ "max_insns_skipped:\t%d\n", current_tune->max_insns_skipped);
++ asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START
++ "prefetch.num_slots:\t%d\n", current_tune->prefetch.num_slots);
++ asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START
++ "prefetch.l1_cache_size:\t%d\n",
+ current_tune->prefetch.l1_cache_size);
+- asm_fprintf (asm_out_file, "\t\t at prefetch.l1_cache_line_size:\t%d\n",
++ asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START
++ "prefetch.l1_cache_line_size:\t%d\n",
+ current_tune->prefetch.l1_cache_line_size);
+- asm_fprintf (asm_out_file, "\t\t at prefer_constant_pool:\t%d\n",
++ asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START
++ "prefer_constant_pool:\t%d\n",
+ (int) current_tune->prefer_constant_pool);
+- asm_fprintf (asm_out_file, "\t\t at branch_cost:\t(s:speed, p:predictable)\n");
+- asm_fprintf (asm_out_file, "\t\t\t\ts&p\tcost\n");
+- asm_fprintf (asm_out_file, "\t\t\t\t00\t%d\n",
++ asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START
++ "branch_cost:\t(s:speed, p:predictable)\n");
++ asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START "\t\ts&p\tcost\n");
++ asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START "\t\t00\t%d\n",
+ current_tune->branch_cost (false, false));
+- asm_fprintf (asm_out_file, "\t\t\t\t01\t%d\n",
++ asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START "\t\t01\t%d\n",
+ current_tune->branch_cost (false, true));
+- asm_fprintf (asm_out_file, "\t\t\t\t10\t%d\n",
++ asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START "\t\t10\t%d\n",
+ current_tune->branch_cost (true, false));
+- asm_fprintf (asm_out_file, "\t\t\t\t11\t%d\n",
++ asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START "\t\t11\t%d\n",
+ current_tune->branch_cost (true, true));
+- asm_fprintf (asm_out_file, "\t\t at prefer_ldrd_strd:\t%d\n",
++ asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START
++ "prefer_ldrd_strd:\t%d\n",
+ (int) current_tune->prefer_ldrd_strd);
+- asm_fprintf (asm_out_file, "\t\t at logical_op_non_short_circuit:\t[%d,%d]\n",
++ asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START
++ "logical_op_non_short_circuit:\t[%d,%d]\n",
+ (int) current_tune->logical_op_non_short_circuit_thumb,
+ (int) current_tune->logical_op_non_short_circuit_arm);
+- asm_fprintf (asm_out_file, "\t\t at prefer_neon_for_64bits:\t%d\n",
++ asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START
++ "prefer_neon_for_64bits:\t%d\n",
+ (int) current_tune->prefer_neon_for_64bits);
+- asm_fprintf (asm_out_file,
+- "\t\t at disparage_flag_setting_t16_encodings:\t%d\n",
++ asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START
++ "disparage_flag_setting_t16_encodings:\t%d\n",
+ (int) current_tune->disparage_flag_setting_t16_encodings);
+- asm_fprintf (asm_out_file, "\t\t at string_ops_prefer_neon:\t%d\n",
++ asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START
++ "string_ops_prefer_neon:\t%d\n",
+ (int) current_tune->string_ops_prefer_neon);
+- asm_fprintf (asm_out_file, "\t\t at max_insns_inline_memset:\t%d\n",
++ asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START
++ "max_insns_inline_memset:\t%d\n",
+ current_tune->max_insns_inline_memset);
+- asm_fprintf (asm_out_file, "\t\t at fusible_ops:\t%u\n",
++ asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START "fusible_ops:\t%u\n",
+ current_tune->fusible_ops);
+- asm_fprintf (asm_out_file, "\t\t at sched_autopref:\t%d\n",
++ asm_fprintf (asm_out_file, "\t\t" ASM_COMMENT_START "sched_autopref:\t%d\n",
+ (int) current_tune->sched_autopref);
+ }
+
+@@ -26018,7 +25859,7 @@ arm_file_start (void)
const char* pos = strchr (arm_selected_arch->name, '+');
if (pos)
{
@@ -56320,7 +56906,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
gcc_assert (strlen (arm_selected_arch->name)
<= sizeof (buf) / sizeof (*pos));
strncpy (buf, arm_selected_arch->name,
-@@ -26043,7 +25878,7 @@ arm_file_start (void)
+@@ -26043,7 +25884,7 @@ arm_file_start (void)
if (print_tune_info)
arm_print_tune_info ();
@@ -56329,7 +56915,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
{
if (TARGET_HARD_FLOAT && TARGET_VFP_SINGLE)
arm_emit_eabi_attribute ("Tag_ABI_HardFP_use", 27, 1);
-@@ -26160,11 +25995,10 @@ arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
+@@ -26160,11 +26001,10 @@ arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
/* Output code to add DELTA to the first argument, and then jump
to FUNCTION. Used for C++ multiple inheritance. */
@@ -56344,7 +56930,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
{
static int thunk_label = 0;
char label[256];
-@@ -26305,6 +26139,76 @@ arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
+@@ -26305,6 +26145,76 @@ arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
final_end_function ();
}
@@ -56421,7 +57007,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
int
arm_emit_vector_const (FILE *file, rtx x)
{
-@@ -27543,7 +27447,7 @@ arm_mangle_type (const_tree type)
+@@ -27543,7 +27453,7 @@ arm_mangle_type (const_tree type)
static const int thumb_core_reg_alloc_order[] =
{
3, 2, 1, 0, 4, 5, 6, 7,
@@ -56430,7 +57016,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
};
/* Adjust register allocation order when compiling for Thumb. */
-@@ -27689,7 +27593,7 @@ arm_conditional_register_usage (void)
+@@ -27689,7 +27599,7 @@ arm_conditional_register_usage (void)
if (TARGET_THUMB1)
fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1;
@@ -56439,7 +57025,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
{
/* VFPv3 registers are disabled when earlier VFP
versions are selected due to the definition of
-@@ -27760,7 +27664,7 @@ arm_preferred_rename_class (reg_class_t rclass)
+@@ -27760,7 +27670,7 @@ arm_preferred_rename_class (reg_class_t rclass)
return NO_REGS;
}
@@ -56448,7 +57034,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
So this function MUST be kept in sync with that insn pattern. */
int
arm_attr_length_push_multi(rtx parallel_op, rtx first_op)
-@@ -27777,6 +27681,11 @@ arm_attr_length_push_multi(rtx parallel_op, rtx first_op)
+@@ -27777,6 +27687,11 @@ arm_attr_length_push_multi(rtx parallel_op, rtx first_op)
/* Thumb2 mode. */
regno = REGNO (first_op);
@@ -56460,7 +57046,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
hi_reg = (REGNO_REG_CLASS (regno) == HI_REGS) && (regno != LR_REGNUM);
for (i = 1; i < num_saves && !hi_reg; i++)
{
-@@ -27789,6 +27698,56 @@ arm_attr_length_push_multi(rtx parallel_op, rtx first_op)
+@@ -27789,6 +27704,56 @@ arm_attr_length_push_multi(rtx parallel_op, rtx first_op)
return 4;
}
@@ -56517,7 +57103,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* Compute the number of instructions emitted by output_move_double. */
int
arm_count_output_move_double_insns (rtx *operands)
-@@ -27820,7 +27779,11 @@ vfp3_const_double_for_fract_bits (rtx operand)
+@@ -27820,7 +27785,11 @@ vfp3_const_double_for_fract_bits (rtx operand)
HOST_WIDE_INT value = real_to_integer (&r0);
value = value & 0xffffffff;
if ((value != 0) && ( (value & (value - 1)) == 0))
@@ -56530,7 +57116,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
}
}
return 0;
-@@ -27960,9 +27923,9 @@ emit_unlikely_jump (rtx insn)
+@@ -27960,9 +27929,9 @@ emit_unlikely_jump (rtx insn)
void
arm_expand_compare_and_swap (rtx operands[])
{
@@ -56542,7 +57128,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
bval = operands[0];
rval = operands[1];
-@@ -28019,43 +27982,54 @@ arm_expand_compare_and_swap (rtx operands[])
+@@ -28019,43 +27988,54 @@ arm_expand_compare_and_swap (rtx operands[])
gcc_unreachable ();
}
@@ -56612,7 +57198,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
mode = GET_MODE (mem);
bool is_armv8_sync = arm_arch8 && is_mm_sync (mod_s);
-@@ -28087,26 +28061,44 @@ arm_split_compare_and_swap (rtx operands[])
+@@ -28087,26 +28067,44 @@ arm_split_compare_and_swap (rtx operands[])
arm_emit_load_exclusive (mode, rval, mem, use_acquire);
@@ -56670,7 +57256,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
}
if (!is_mm_relaxed (mod_f))
-@@ -28121,6 +28113,15 @@ arm_split_compare_and_swap (rtx operands[])
+@@ -28121,6 +28119,15 @@ arm_split_compare_and_swap (rtx operands[])
emit_label (label2);
}
@@ -56686,7 +57272,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
void
arm_split_atomic_op (enum rtx_code code, rtx old_out, rtx new_out, rtx mem,
rtx value, rtx model_rtx, rtx cond)
-@@ -28129,6 +28130,7 @@ arm_split_atomic_op (enum rtx_code code, rtx old_out, rtx new_out, rtx mem,
+@@ -28129,6 +28136,7 @@ arm_split_atomic_op (enum rtx_code code, rtx old_out, rtx new_out, rtx mem,
machine_mode mode = GET_MODE (mem);
machine_mode wmode = (mode == DImode ? DImode : SImode);
rtx_code_label *label;
@@ -56694,7 +57280,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
rtx x;
bool is_armv8_sync = arm_arch8 && is_mm_sync (model);
-@@ -28163,6 +28165,28 @@ arm_split_atomic_op (enum rtx_code code, rtx old_out, rtx new_out, rtx mem,
+@@ -28163,6 +28171,28 @@ arm_split_atomic_op (enum rtx_code code, rtx old_out, rtx new_out, rtx mem,
arm_emit_load_exclusive (mode, old_out, mem, use_acquire);
@@ -56723,7 +57309,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
switch (code)
{
case SET:
-@@ -28377,6 +28401,8 @@ arm_evpc_neon_vuzp (struct expand_vec_perm_d *d)
+@@ -28377,6 +28407,8 @@ arm_evpc_neon_vuzp (struct expand_vec_perm_d *d)
case V8QImode: gen = gen_neon_vuzpv8qi_internal; break;
case V8HImode: gen = gen_neon_vuzpv8hi_internal; break;
case V4HImode: gen = gen_neon_vuzpv4hi_internal; break;
@@ -56732,7 +57318,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
case V4SImode: gen = gen_neon_vuzpv4si_internal; break;
case V2SImode: gen = gen_neon_vuzpv2si_internal; break;
case V2SFmode: gen = gen_neon_vuzpv2sf_internal; break;
-@@ -28450,6 +28476,8 @@ arm_evpc_neon_vzip (struct expand_vec_perm_d *d)
+@@ -28450,6 +28482,8 @@ arm_evpc_neon_vzip (struct expand_vec_perm_d *d)
case V8QImode: gen = gen_neon_vzipv8qi_internal; break;
case V8HImode: gen = gen_neon_vzipv8hi_internal; break;
case V4HImode: gen = gen_neon_vzipv4hi_internal; break;
@@ -56741,7 +57327,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
case V4SImode: gen = gen_neon_vzipv4si_internal; break;
case V2SImode: gen = gen_neon_vzipv2si_internal; break;
case V2SFmode: gen = gen_neon_vzipv2sf_internal; break;
-@@ -28502,6 +28530,8 @@ arm_evpc_neon_vrev (struct expand_vec_perm_d *d)
+@@ -28502,6 +28536,8 @@ arm_evpc_neon_vrev (struct expand_vec_perm_d *d)
case V8QImode: gen = gen_neon_vrev32v8qi; break;
case V8HImode: gen = gen_neon_vrev64v8hi; break;
case V4HImode: gen = gen_neon_vrev64v4hi; break;
@@ -56750,7 +57336,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
default:
return false;
}
-@@ -28585,6 +28615,8 @@ arm_evpc_neon_vtrn (struct expand_vec_perm_d *d)
+@@ -28585,6 +28621,8 @@ arm_evpc_neon_vtrn (struct expand_vec_perm_d *d)
case V8QImode: gen = gen_neon_vtrnv8qi_internal; break;
case V8HImode: gen = gen_neon_vtrnv8hi_internal; break;
case V4HImode: gen = gen_neon_vtrnv4hi_internal; break;
@@ -56759,7 +57345,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
case V4SImode: gen = gen_neon_vtrnv4si_internal; break;
case V2SImode: gen = gen_neon_vtrnv2si_internal; break;
case V2SFmode: gen = gen_neon_vtrnv2sf_internal; break;
-@@ -28660,6 +28692,8 @@ arm_evpc_neon_vext (struct expand_vec_perm_d *d)
+@@ -28660,6 +28698,8 @@ arm_evpc_neon_vext (struct expand_vec_perm_d *d)
case V8HImode: gen = gen_neon_vextv8hi; break;
case V2SImode: gen = gen_neon_vextv2si; break;
case V4SImode: gen = gen_neon_vextv4si; break;
@@ -56768,7 +57354,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
case V2SFmode: gen = gen_neon_vextv2sf; break;
case V4SFmode: gen = gen_neon_vextv4sf; break;
case V2DImode: gen = gen_neon_vextv2di; break;
-@@ -29185,7 +29219,7 @@ arm_validize_comparison (rtx *comparison, rtx * op1, rtx * op2)
+@@ -29185,7 +29225,7 @@ arm_validize_comparison (rtx *comparison, rtx * op1, rtx * op2)
{
enum rtx_code code = GET_CODE (*comparison);
int code_int;
@@ -56777,7 +57363,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
? GET_MODE (*op2) : GET_MODE (*op1);
gcc_assert (GET_MODE (*op1) != VOIDmode || GET_MODE (*op2) != VOIDmode);
-@@ -29213,11 +29247,19 @@ arm_validize_comparison (rtx *comparison, rtx * op1, rtx * op2)
+@@ -29213,11 +29253,19 @@ arm_validize_comparison (rtx *comparison, rtx * op1, rtx * op2)
*op2 = force_reg (mode, *op2);
return true;
@@ -56799,7 +57385,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
*op2 = force_reg (mode, *op2);
return true;
default:
-@@ -29759,11 +29801,57 @@ arm_macro_fusion_p (void)
+@@ -29759,11 +29807,57 @@ arm_macro_fusion_p (void)
return current_tune->fusible_ops != tune_params::FUSE_NOTHING;
}
@@ -56858,7 +57444,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
rtx prev_set = single_set (prev);
rtx curr_set = single_set (curr);
-@@ -29781,54 +29869,26 @@ aarch_macro_fusion_pair_p (rtx_insn* prev, rtx_insn* curr)
+@@ -29781,54 +29875,26 @@ aarch_macro_fusion_pair_p (rtx_insn* prev, rtx_insn* curr)
&& aarch_crypto_can_dual_issue (prev, curr))
return true;
@@ -56924,7 +57510,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
}
-@@ -29853,9 +29913,9 @@ arm_const_not_ok_for_debug_p (rtx p)
+@@ -29853,9 +29919,9 @@ arm_const_not_ok_for_debug_p (rtx p)
&& GET_CODE (XEXP (p, 0)) == SYMBOL_REF
&& (decl_op0 = SYMBOL_REF_DECL (XEXP (p, 0))))
{
@@ -56936,7 +57522,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
|| TREE_CODE (decl_op0) == CONST_DECL))
return (get_variable_section (decl_op1, false)
!= get_variable_section (decl_op0, false));
-@@ -29988,9 +30048,8 @@ arm_can_inline_p (tree caller, tree callee)
+@@ -29988,9 +30054,8 @@ arm_can_inline_p (tree caller, tree callee)
if ((caller_fpu->features & callee_fpu->features) != callee_fpu->features)
return false;
@@ -56948,7 +57534,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
return false;
/* OK to inline between different modes.
-@@ -30333,4 +30392,113 @@ arm_sched_fusion_priority (rtx_insn *insn, int max_pri,
+@@ -30333,4 +30398,113 @@ arm_sched_fusion_priority (rtx_insn *insn, int max_pri,
return;
}
@@ -58538,7 +59124,18 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
(set_attr "type" "alu_sreg")]
--- a/src/gcc/config/arm/arm.opt
+++ b/src/gcc/config/arm/arm.opt
-@@ -109,6 +109,10 @@ mfloat-abi=
+@@ -61,10 +61,6 @@ Generate a call to abort if a noreturn function returns.
+ mapcs
+ Target RejectNegative Mask(APCS_FRAME) Undocumented
+
+-mapcs-float
+-Target Report Mask(APCS_FLOAT)
+-Pass FP arguments in FP registers.
+-
+ mapcs-frame
+ Target Report Mask(APCS_FRAME)
+ Generate APCS conformant stack frames.
+@@ -109,6 +105,10 @@ mfloat-abi=
Target RejectNegative Joined Enum(float_abi_type) Var(arm_float_abi) Init(TARGET_DEFAULT_FLOAT_ABI)
Specify if floating point hardware should be used.
@@ -58549,7 +59146,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
Enum
Name(float_abi_type) Type(enum float_abi_type)
Known floating-point ABIs (for use with the -mfloat-abi= option):
-@@ -253,14 +257,6 @@ mrestrict-it
+@@ -253,14 +253,6 @@ mrestrict-it
Target Report Var(arm_restrict_it) Init(2) Save
Generate IT blocks appropriate for ARMv8.
@@ -83556,7 +84153,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
MULTILIB_MATCHES += march?armv8-a=mcpu?exynos-m1
MULTILIB_MATCHES += march?armv8-a=mcpu?qdf24xx
MULTILIB_MATCHES += march?armv8-a=mcpu?xgene1
-@@ -101,12 +99,17 @@ MULTILIB_MATCHES += march?armv8-a=mcpu?xgene1
+@@ -101,13 +99,20 @@ MULTILIB_MATCHES += march?armv8-a=mcpu?xgene1
MULTILIB_MATCHES += march?armv8-a=march?armv8-a+crc
MULTILIB_MATCHES += march?armv8-a=march?armv8.1-a
MULTILIB_MATCHES += march?armv8-a=march?armv8.1-a+crc
@@ -83573,9 +84170,12 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
+MULTILIB_MATCHES += mfpu?vfpv4-d16=mfpu?fpv5-d16
+MULTILIB_MATCHES += mfpu?vfpv4-d16=mfpu?fp-armv8
MULTILIB_MATCHES += mfpu?neon-fp-armv8=mfpu?crypto-neon-fp-armv8
++MULTILIB_MATCHES += mfpu?vfp=mfpu?vfpv2
++MULTILIB_MATCHES += mfpu?neon=mfpu?neon-vfpv3
-@@ -124,10 +127,6 @@ MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv8
+ # Map all requests for vfpv3 with a later CPU to vfpv3-d16 v7-a.
+@@ -124,10 +129,6 @@ MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv8
MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv8-a/mfpu.vfpv3-d16/mfloat-abi.softfp
MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.hard
MULTILIB_REUSE += march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.softfp
@@ -83586,7 +84186,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
MULTILIB_REUSE += march.armv7-a/mfpu.neon/mfloat-abi.hard=march.armv7ve/mfpu.neon/mfloat-abi.hard
-@@ -140,10 +139,6 @@ MULTILIB_REUSE += march.armv7-a/mfpu.neon/mfloat-abi.hard=march.armv7-a/mf
+@@ -140,10 +141,6 @@ MULTILIB_REUSE += march.armv7-a/mfpu.neon/mfloat-abi.hard=march.armv7-a/mf
MULTILIB_REUSE += march.armv7-a/mfpu.neon/mfloat-abi.softfp=march.armv7-a/mfpu.neon-fp-armv8/mfloat-abi.softfp
@@ -83597,7 +84197,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
MULTILIB_REUSE += march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.hard=march.armv8-a/mfpu.vfpv4-d16/mfloat-abi.hard
MULTILIB_REUSE += march.armv7ve/mfpu.vfpv4-d16/mfloat-abi.softfp=march.armv8-a/mfpu.vfpv4-d16/mfloat-abi.softfp
-@@ -163,10 +158,6 @@ MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mthu
+@@ -163,10 +160,6 @@ MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mthu
MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv8-a/mfpu.vfpv3-d16/mfloat-abi.softfp
MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.hard=mthumb/march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.hard
MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.vfpv3-d16/mfloat-abi.softfp=mthumb/march.armv7-a/mfpu.vfpv4-d16/mfloat-abi.softfp
@@ -83608,7 +84208,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.hard=mthumb/march.armv7ve/mfpu.neon/mfloat-abi.hard
-@@ -179,10 +170,6 @@ MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.hard=mthumb/ma
+@@ -179,10 +172,6 @@ MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.hard=mthumb/ma
MULTILIB_REUSE += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.softfp=mthumb/march.armv7-a/mfpu.neon-fp-armv8/mfloat-abi.softfp
@@ -85882,7 +86482,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
synthetic multiplication sequence, hence cost(a op b) is defined
--- a/src/gcc/fold-const.c
+++ b/src/gcc/fold-const.c
-@@ -7216,7 +7216,16 @@ native_encode_real (const_tree expr, unsigned char *ptr, int len, int off)
+@@ -7230,7 +7230,16 @@ native_encode_real (const_tree expr, unsigned char *ptr, int len, int off)
offset += byte % UNITS_PER_WORD;
}
else
@@ -86395,7 +86995,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
if (orig_x != x)
--- a/src/gcc/internal-fn.c
+++ b/src/gcc/internal-fn.c
-@@ -1810,11 +1810,7 @@ expand_arith_overflow (enum tree_code code, gimple *stmt)
+@@ -1812,11 +1812,7 @@ expand_arith_overflow (enum tree_code code, gimple *stmt)
/* For sub-word operations, retry with a wider type first. */
if (orig_precres == precres && precop <= BITS_PER_WORD)
{
@@ -86897,6 +87497,19 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
+ c && c->d();
+}
--- /dev/null
++++ b/src/gcc/testsuite/gcc.c-torture/compile/pr71112.c
+@@ -0,0 +1,10 @@
++/* PR target/71112. */
++/* { dg-additional-options "-fpie" { target pie } } */
++
++extern int dbs[100];
++void f (int *);
++int nscd_init (void)
++{
++ f (dbs);
++ return 0;
++}
+--- /dev/null
+++ b/src/gcc/testsuite/gcc.c-torture/compile/pr71295.c
@@ -0,0 +1,12 @@
+extern void fn2 (long long);
@@ -87989,6 +88602,17 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* { dg-final { scan-tree-dump "bar: va_list escapes 1, needs to save all GPR units" "stdarg" { target { { i?86-*-* x86_64-*-* } && ia32 } } } } */
/* { dg-final { scan-tree-dump "bar: va_list escapes 1, needs to save all GPR units" "stdarg" { target ia64-*-* } } } */
/* { dg-final { scan-tree-dump "bar: va_list escapes 1, needs to save all GPR units" "stdarg" { target { powerpc*-*-* && lp64 } } } } */
+--- a/src/gcc/testsuite/gcc.dg/uninit-pred-8_a.c
++++ b/src/gcc/testsuite/gcc.dg/uninit-pred-8_a.c
+@@ -1,6 +1,8 @@
+
+ /* { dg-do compile } */
+ /* { dg-options "-Wuninitialized -O2" } */
++/* Pick a particular tuning to pin down BRANCH_COST. */
++/* { dg-additional-options "-mtune=cortex-a15" { target arm*-*-* } } */
+
+ int g;
+ void bar();
--- /dev/null
+++ b/src/gcc/testsuite/gcc.dg/vect/aligned-section-anchors-vect-70.c
@@ -0,0 +1,33 @@
@@ -106109,6 +106733,32 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
+/* { dg-final { scan-assembler-times "ldp\tx\[0-9\]+, x\[0-9\], .*8" 1 } } */
+/* { dg-final { scan-assembler-times "stp\tx\[0-9\]+, x\[0-9\], .*8" 1 } } */
--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/popcnt.c
+@@ -0,0 +1,23 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++int
++foo (int x)
++{
++ return __builtin_popcount (x);
++}
++
++long
++foo1 (long x)
++{
++ return __builtin_popcountl (x);
++}
++
++long long
++foo2 (long long x)
++{
++ return __builtin_popcountll (x);
++}
++
++/* { dg-final { scan-assembler-not "popcount" } } */
++/* { dg-final { scan-assembler-times "cnt\t" 3 } } */
+--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/aarch64/pr37780_1.c
@@ -0,0 +1,46 @@
+/* Test that we can remove the conditional move due to CLZ
@@ -106182,6 +106832,55 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
+
+/* { dg-final { scan-assembler-not "adr*foo_weakref" } } */
+/* { dg-final { scan-assembler-not "\\.(word|xword)\tbar" } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/pr71727.c
+@@ -0,0 +1,33 @@
++/* { dg-do compile } */
++/* { dg-options "-mstrict-align -O3" } */
++
++struct test_struct_s
++{
++ long a;
++ long b;
++ long c;
++ long d;
++ unsigned long e;
++};
++
++
++char _a;
++struct test_struct_s xarray[128];
++
++void
++_start (void)
++{
++ struct test_struct_s *new_entry;
++
++ new_entry = &xarray[0];
++ new_entry->a = 1;
++ new_entry->b = 2;
++ new_entry->c = 3;
++ new_entry->d = 4;
++ new_entry->e = 5;
++
++ return;
++}
++
++/* { dg-final { scan-assembler-times "mov\tx" 5 {target lp64} } } */
++/* { dg-final { scan-assembler-not "add\tx0, x0, :" {target lp64} } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/pr78382.c
+@@ -0,0 +1,10 @@
++/* { dg-require-effective-target fpic } */
++/* { dg-options "-mtls-dialect=trad -fpic" } */
++
++__thread int abc;
++void
++foo ()
++{
++ int *p;
++ p = &abc;
++}
--- a/src/gcc/testsuite/gcc.target/aarch64/simd/vminmaxnm_1.c
+++ b/src/gcc/testsuite/gcc.target/aarch64/simd/vminmaxnm_1.c
@@ -1,4 +1,4 @@
@@ -106835,6 +107534,38 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
int f(int *a, int b)
{
--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/store_repeating_constant_1.c
+@@ -0,0 +1,11 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mtune=generic" } */
++
++void
++foo (unsigned long long *a)
++{
++ a[0] = 0x0140c0da0140c0daULL;
++}
++
++/* { dg-final { scan-assembler-times "movk\\tw.*" 1 } } */
++/* { dg-final { scan-assembler-times "stp\tw\[0-9\]+, w\[0-9\]+.*" 1 } } */
+--- /dev/null
++++ b/src/gcc/testsuite/gcc.target/aarch64/store_repeating_constant_2.c
+@@ -0,0 +1,15 @@
++/* { dg-do compile } */
++/* { dg-options "-Os" } */
++
++/* Check that for -Os we synthesize only the bottom half and then
++ store it twice with an STP rather than synthesizing it twice in each
++ half of an X-reg. */
++
++void
++foo (unsigned long long *a)
++{
++ a[0] = 0xc0da0000c0daULL;
++}
++
++/* { dg-final { scan-assembler-times "mov\\tw.*" 1 } } */
++/* { dg-final { scan-assembler-times "stp\tw\[0-9\]+, w\[0-9\]+.*" 1 } } */
+--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/aarch64/struct_return.c
@@ -0,0 +1,31 @@
+/* Test the absence of a spurious move from x8 to x0 for functions
@@ -107362,6 +108093,25 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
extern void abort ();
+--- a/src/gcc/testsuite/gcc.target/aarch64/vector_initialization_nostack.c
++++ b/src/gcc/testsuite/gcc.target/aarch64/vector_initialization_nostack.c
+@@ -38,14 +38,14 @@ f11 (void)
+ return sum;
+ }
+
+-char arr_c[100][100];
++char arr_c[100];
+ char
+ f12 (void)
+ {
+ int i;
+ char sum = 0;
+ for (i = 0; i < 100; i++)
+- sum += arr_c[i][0] * arr_c[0][i];
++ sum += arr_c[i] * arr_c[i];
+ return sum;
+ }
+
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/aarch64/vget_set_lane_1.c
@@ -0,0 +1,72 @@
@@ -157444,8 +158194,8 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/optional_thumb-1.c
@@ -0,0 +1,7 @@
-+/* { dg-do compile } */
-+/* { dg-skip-if "-marm/-mthumb/-march/-mcpu given" { *-*-*} { "-marm" "-mthumb" "-march=*" "-mcpu=*" } } */
++/* { dg-do compile { target { ! default_mode } } } */
++/* { dg-skip-if "-marm/-mthumb/-march/-mcpu given" { *-*-* } { "-marm" "-mthumb" "-march=*" "-mcpu=*" } } */
+/* { dg-options "-march=armv6-m" } */
+
+/* Check that -mthumb is not needed when compiling for a Thumb-only target. */
@@ -157454,8 +158204,8 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/optional_thumb-2.c
@@ -0,0 +1,7 @@
-+/* { dg-do compile } */
-+/* { dg-skip-if "-marm/-mthumb/-march/-mcpu given" { *-*-*} { "-marm" "-mthumb" "-march=*" "-mcpu=*" } } */
++/* { dg-do compile { target { ! default_mode } } } */
++/* { dg-skip-if "-marm/-mthumb/-march/-mcpu given" { *-*-* } { "-marm" "-mthumb" "-march=*" "-mcpu=*" } } */
+/* { dg-options "-mcpu=cortex-m4" } */
+
+/* Check that -mthumb is not needed when compiling for a Thumb-only target. */
@@ -157466,9 +158216,9 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_cortex_m } */
-+/* { dg-skip-if "-mthumb given" { *-*-*} { "-mthumb" } } */
++/* { dg-skip-if "-mthumb given" { *-*-* } { "-mthumb" } } */
+/* { dg-options "-marm" } */
-+/* { dg-error "target CPU does not support ARM mode" "missing error with -marm on Thumb-only targets" { target *-*-*} 0 } */
++/* { dg-error "target CPU does not support ARM mode" "missing error with -marm on Thumb-only targets" { target *-*-* } 0 } */
+
+/* Check that -marm gives an error when compiling for a Thumb-only target. */
+
@@ -158386,6 +159136,24 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
+}
+
+/* { dg-final { scan-assembler-times "vminnm\.f32\t\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+, ?\[qQ\]\[0-9\]+\n" 7 } } */
+--- a/src/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c
++++ b/src/gcc/testsuite/gcc.target/arm/unsigned-extend-2.c
+@@ -2,13 +2,13 @@
+ /* { dg-require-effective-target arm_thumb2_ok } */
+ /* { dg-options "-O" } */
+
+-unsigned short foo (unsigned short x)
++unsigned short foo (unsigned short x, unsigned short c)
+ {
+ unsigned char i = 0;
+ for (i = 0; i < 8; i++)
+ {
+ x >>= 1;
+- x &= 0x7fff;
++ x &= c;
+ }
+ return x;
+ }
--- /dev/null
+++ b/src/gcc/testsuite/gcc.target/arm/vect-vcvt.c
@@ -0,0 +1,27 @@
@@ -158516,7 +159284,28 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
}
--- a/src/gcc/testsuite/lib/target-supports.exp
+++ b/src/gcc/testsuite/lib/target-supports.exp
-@@ -2936,6 +2936,28 @@ proc add_options_for_arm_v8_1a_neon { flags } {
+@@ -252,6 +252,20 @@ proc check_runtime {prop args} {
+ }]
+ }
+
++# Return 1 if GCC was configured with $pattern.
++proc check_configured_with { pattern } {
++ global tool
++
++ set gcc_output [${tool}_target_compile "-v" "" "none" ""]
++ if { [ regexp "Configured with: \[^\n\]*$pattern" $gcc_output ] } {
++ verbose "Matched: $pattern" 2
++ return 1
++ }
++
++ verbose "Failed to match: $pattern" 2
++ return 0
++}
++
+ ###############################
+ # proc check_weak_available { }
+ ###############################
+@@ -2936,6 +2950,28 @@ proc add_options_for_arm_v8_1a_neon { flags } {
return "$flags $et_arm_v8_1a_neon_flags -march=armv8.1-a"
}
@@ -158545,7 +159334,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
proc add_options_for_arm_crc { flags } {
if { ! [check_effective_target_arm_crc_ok] } {
return "$flags"
-@@ -3022,23 +3044,25 @@ proc check_effective_target_arm_crc_ok { } {
+@@ -3022,23 +3058,25 @@ proc check_effective_target_arm_crc_ok { } {
proc check_effective_target_arm_neon_fp16_ok_nocache { } {
global et_arm_neon_fp16_flags
@@ -158575,7 +159364,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
return 1
}
}
-@@ -3075,6 +3099,65 @@ proc add_options_for_arm_neon_fp16 { flags } {
+@@ -3075,6 +3113,65 @@ proc add_options_for_arm_neon_fp16 { flags } {
return "$flags $et_arm_neon_fp16_flags"
}
@@ -158641,7 +159430,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
# Return 1 if this is an ARM target supporting -mfpu=neon-fp-armv8
# -mfloat-abi=softfp or equivalent options. Some multilibs may be
# incompatible with these options. Also set et_arm_v8_neon_flags to the
-@@ -3117,8 +3200,10 @@ proc check_effective_target_arm_v8_neon_ok { } {
+@@ -3117,8 +3214,10 @@ proc check_effective_target_arm_v8_neon_ok { } {
proc check_effective_target_arm_neonv2_ok_nocache { } {
global et_arm_neonv2_flags
@@ -158653,7 +159442,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon-vfpv4" "-mfpu=neon-vfpv4 -mfloat-abi=softfp"} {
if { [check_no_compiler_messages_nocache arm_neonv2_ok object {
#include "arm_neon.h"
-@@ -3127,8 +3212,8 @@ proc check_effective_target_arm_neonv2_ok_nocache { } {
+@@ -3127,8 +3226,8 @@ proc check_effective_target_arm_neonv2_ok_nocache { } {
{
return vfma_f32 (a, b, c);
}
@@ -158664,7 +159453,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
return 1
}
}
-@@ -3142,9 +3227,9 @@ proc check_effective_target_arm_neonv2_ok { } {
+@@ -3142,9 +3241,9 @@ proc check_effective_target_arm_neonv2_ok { } {
check_effective_target_arm_neonv2_ok_nocache]
}
@@ -158677,7 +159466,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
proc add_options_for_arm_fp16 { flags } {
if { ! [check_effective_target_arm_fp16_ok] } {
-@@ -3154,9 +3239,32 @@ proc add_options_for_arm_fp16 { flags } {
+@@ -3154,9 +3253,32 @@ proc add_options_for_arm_fp16 { flags } {
return "$flags $et_arm_fp16_flags"
}
@@ -158711,7 +159500,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
proc check_effective_target_arm_fp16_ok_nocache { } {
global et_arm_fp16_flags
-@@ -3164,7 +3272,10 @@ proc check_effective_target_arm_fp16_ok_nocache { } {
+@@ -3164,7 +3286,10 @@ proc check_effective_target_arm_fp16_ok_nocache { } {
if { ! [check_effective_target_arm32] } {
return 0;
}
@@ -158723,7 +159512,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
# Multilib flags would override -mfpu.
return 0
}
-@@ -3200,6 +3311,28 @@ proc check_effective_target_arm_fp16_ok { } {
+@@ -3200,6 +3325,28 @@ proc check_effective_target_arm_fp16_ok { } {
check_effective_target_arm_fp16_ok_nocache]
}
@@ -158752,7 +159541,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
# Creates a series of routines that return 1 if the given architecture
# can be selected and a routine to give the flags to select that architecture
# Note: Extra flags may be added to disable options from newer compilers
-@@ -3209,22 +3342,26 @@ proc check_effective_target_arm_fp16_ok { } {
+@@ -3209,22 +3356,26 @@ proc check_effective_target_arm_fp16_ok { } {
# Usage: /* { dg-require-effective-target arm_arch_v5_ok } */
# /* { dg-add-options arm_arch_v5 } */
# /* { dg-require-effective-target arm_arch_v5_multilib } */
@@ -158795,7 +159584,20 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
eval [string map [list FUNC $armfunc FLAG $armflag DEF $armdef ] {
proc check_effective_target_arm_arch_FUNC_ok { } {
if { [ string match "*-marm*" "FLAG" ] &&
-@@ -3352,15 +3489,60 @@ proc check_effective_target_arm_cortex_m { } {
+@@ -3274,6 +3425,12 @@ proc add_options_for_arm_arch_v7ve { flags } {
+ return "$flags -march=armv7ve"
+ }
+
++# Return 1 if GCC was configured with --with-mode=
++proc check_effective_target_default_mode { } {
++
++ return [check_configured_with "with-mode="]
++}
++
+ # Return 1 if this is an ARM target where -marm causes ARM to be
+ # used (not Thumb)
+
+@@ -3352,15 +3509,60 @@ proc check_effective_target_arm_cortex_m { } {
return 0
}
return [check_no_compiler_messages arm_cortex_m assembly {
@@ -158860,7 +159662,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
# Return 1 if this compilation turns on string_ops_prefer_neon on.
proc check_effective_target_arm_tune_string_ops_prefer_neon { } {
-@@ -3436,6 +3618,76 @@ proc check_effective_target_arm_v8_1a_neon_ok { } {
+@@ -3436,6 +3638,76 @@ proc check_effective_target_arm_v8_1a_neon_ok { } {
check_effective_target_arm_v8_1a_neon_ok_nocache]
}
@@ -158937,7 +159739,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
# Return 1 if the target supports executing ARMv8 NEON instructions, 0
# otherwise.
-@@ -3445,11 +3697,17 @@ proc check_effective_target_arm_v8_neon_hw { } {
+@@ -3445,11 +3717,17 @@ proc check_effective_target_arm_v8_neon_hw { } {
int
main (void)
{
@@ -158957,7 +159759,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
}
} [add_options_for_arm_v8_neon ""]]
}
-@@ -3492,6 +3750,81 @@ proc check_effective_target_arm_v8_1a_neon_hw { } {
+@@ -3492,6 +3770,81 @@ proc check_effective_target_arm_v8_1a_neon_hw { } {
} [add_options_for_arm_v8_1a_neon ""]]
}
@@ -159039,7 +159841,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
# Return 1 if this is a ARM target with NEON enabled.
proc check_effective_target_arm_neon { } {
-@@ -3526,6 +3859,25 @@ proc check_effective_target_arm_neonv2 { } {
+@@ -3526,6 +3879,25 @@ proc check_effective_target_arm_neonv2 { } {
}
}
@@ -159065,7 +159867,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
# Return 1 if this a Loongson-2E or -2F target using an ABI that supports
# the Loongson vector modes.
-@@ -4380,6 +4732,8 @@ proc check_effective_target_vect_widen_sum_hi_to_si_pattern { } {
+@@ -4380,6 +4752,8 @@ proc check_effective_target_vect_widen_sum_hi_to_si_pattern { } {
set et_vect_widen_sum_hi_to_si_pattern_saved 0
if { [istarget powerpc*-*-*]
|| [istarget aarch64*-*-*]
@@ -159074,7 +159876,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
|| [istarget ia64-*-*] } {
set et_vect_widen_sum_hi_to_si_pattern_saved 1
}
-@@ -5755,6 +6109,8 @@ proc check_effective_target_sync_int_long { } {
+@@ -5755,6 +6129,8 @@ proc check_effective_target_sync_int_long { } {
|| [istarget aarch64*-*-*]
|| [istarget alpha*-*-*]
|| [istarget arm*-*-linux-*]
@@ -159083,7 +159885,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
|| [istarget bfin*-*linux*]
|| [istarget hppa*-*linux*]
|| [istarget s390*-*-*]
-@@ -5788,6 +6144,8 @@ proc check_effective_target_sync_char_short { } {
+@@ -5788,6 +6164,8 @@ proc check_effective_target_sync_char_short { } {
|| [istarget i?86-*-*] || [istarget x86_64-*-*]
|| [istarget alpha*-*-*]
|| [istarget arm*-*-linux-*]
@@ -159920,7 +160722,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
--- a/src/gcc/tree-vrp.c
+++ b/src/gcc/tree-vrp.c
-@@ -3147,6 +3147,24 @@ extract_range_from_binary_expr_1 (value_range *vr,
+@@ -3165,6 +3165,24 @@ extract_range_from_binary_expr_1 (value_range *vr,
if (int_cst_range1 && tree_int_cst_sgn (vr1.min) >= 0)
wmax = wi::min (wmax, vr1.max, TYPE_SIGN (expr_type));
max = wide_int_to_tree (expr_type, wmax);
@@ -159945,7 +160747,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
}
else if (code == BIT_IOR_EXPR)
{
-@@ -3841,7 +3859,8 @@ extract_range_basic (value_range *vr, gimple *stmt)
+@@ -3859,7 +3877,8 @@ extract_range_basic (value_range *vr, gimple *stmt)
arg = gimple_call_arg (stmt, 0);
if (TREE_CODE (arg) == SSA_NAME
&& SSA_NAME_IS_DEFAULT_DEF (arg)
@@ -159955,7 +160757,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
{
set_value_range_to_null (vr, type);
return;
-@@ -9917,6 +9936,40 @@ simplify_internal_call_using_ranges (gimple_stmt_iterator *gsi, gimple *stmt)
+@@ -9935,6 +9954,40 @@ simplify_internal_call_using_ranges (gimple_stmt_iterator *gsi, gimple *stmt)
return true;
}
@@ -159996,7 +160798,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
/* Simplify STMT using ranges if possible. */
static bool
-@@ -9927,6 +9980,68 @@ simplify_stmt_using_ranges (gimple_stmt_iterator *gsi)
+@@ -9945,6 +9998,68 @@ simplify_stmt_using_ranges (gimple_stmt_iterator *gsi)
{
enum tree_code rhs_code = gimple_assign_rhs_code (stmt);
tree rhs1 = gimple_assign_rhs1 (stmt);
@@ -160177,6 +160979,110 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
NODE_NAME (token->val.node.node));
}
break;
+--- a/src/libcpp/lex.c
++++ b/src/libcpp/lex.c
+@@ -750,6 +750,101 @@ search_line_fast (const uchar *s, const uchar *end ATTRIBUTE_UNUSED)
+ }
+ }
+
++#elif defined (__ARM_NEON) && defined (__ARM_64BIT_STATE)
++#include "arm_neon.h"
++
++/* This doesn't have to be the exact page size, but no system may use
++ a size smaller than this. ARMv8 requires a minimum page size of
++ 4k. The impact of being conservative here is a small number of
++ cases will take the slightly slower entry path into the main
++ loop. */
++
++#define AARCH64_MIN_PAGE_SIZE 4096
++
++static const uchar *
++search_line_fast (const uchar *s, const uchar *end ATTRIBUTE_UNUSED)
++{
++ const uint8x16_t repl_nl = vdupq_n_u8 ('\n');
++ const uint8x16_t repl_cr = vdupq_n_u8 ('\r');
++ const uint8x16_t repl_bs = vdupq_n_u8 ('\\');
++ const uint8x16_t repl_qm = vdupq_n_u8 ('?');
++ const uint8x16_t xmask = (uint8x16_t) vdupq_n_u64 (0x8040201008040201ULL);
++
++#ifdef __AARCH64EB
++ const int16x8_t shift = {8, 8, 8, 8, 0, 0, 0, 0};
++#else
++ const int16x8_t shift = {0, 0, 0, 0, 8, 8, 8, 8};
++#endif
++
++ unsigned int found;
++ const uint8_t *p;
++ uint8x16_t data;
++ uint8x16_t t;
++ uint16x8_t m;
++ uint8x16_t u, v, w;
++
++ /* Align the source pointer. */
++ p = (const uint8_t *)((uintptr_t)s & -16);
++
++ /* Assuming random string start positions, with a 4k page size we'll take
++ the slow path about 0.37% of the time. */
++ if (__builtin_expect ((AARCH64_MIN_PAGE_SIZE
++ - (((uintptr_t) s) & (AARCH64_MIN_PAGE_SIZE - 1)))
++ < 16, 0))
++ {
++ /* Slow path: the string starts near a possible page boundary. */
++ uint32_t misalign, mask;
++
++ misalign = (uintptr_t)s & 15;
++ mask = (-1u << misalign) & 0xffff;
++ data = vld1q_u8 (p);
++ t = vceqq_u8 (data, repl_nl);
++ u = vceqq_u8 (data, repl_cr);
++ v = vorrq_u8 (t, vceqq_u8 (data, repl_bs));
++ w = vorrq_u8 (u, vceqq_u8 (data, repl_qm));
++ t = vorrq_u8 (v, w);
++ t = vandq_u8 (t, xmask);
++ m = vpaddlq_u8 (t);
++ m = vshlq_u16 (m, shift);
++ found = vaddvq_u16 (m);
++ found &= mask;
++ if (found)
++ return (const uchar*)p + __builtin_ctz (found);
++ }
++ else
++ {
++ data = vld1q_u8 ((const uint8_t *) s);
++ t = vceqq_u8 (data, repl_nl);
++ u = vceqq_u8 (data, repl_cr);
++ v = vorrq_u8 (t, vceqq_u8 (data, repl_bs));
++ w = vorrq_u8 (u, vceqq_u8 (data, repl_qm));
++ t = vorrq_u8 (v, w);
++ if (__builtin_expect (vpaddd_u64 ((uint64x2_t)t), 0))
++ goto done;
++ }
++
++ do
++ {
++ p += 16;
++ data = vld1q_u8 (p);
++ t = vceqq_u8 (data, repl_nl);
++ u = vceqq_u8 (data, repl_cr);
++ v = vorrq_u8 (t, vceqq_u8 (data, repl_bs));
++ w = vorrq_u8 (u, vceqq_u8 (data, repl_qm));
++ t = vorrq_u8 (v, w);
++ } while (!vpaddd_u64 ((uint64x2_t)t));
++
++done:
++ /* Now that we've found the terminating substring, work out precisely where
++ we need to stop. */
++ t = vandq_u8 (t, xmask);
++ m = vpaddlq_u8 (t);
++ m = vshlq_u16 (m, shift);
++ found = vaddvq_u16 (m);
++ return (((((uintptr_t) p) < (uintptr_t) s) ? s : (const uchar *)p)
++ + __builtin_ctz (found));
++}
++
+ #elif defined (__ARM_NEON)
+ #include "arm_neon.h"
+
--- a/src/libgcc/Makefile.in
+++ b/src/libgcc/Makefile.in
@@ -414,8 +414,9 @@ lib2funcs = _muldi3 _negdi2 _lshrdi3 _ashldi3 _ashrdi3 _cmpdi2 _ucmpdi2 \
@@ -160191,6 +161097,45 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
# The floating-point conversion routines that involve a single-word integer.
# XX stands for the integer mode.
+--- a/src/libgcc/config.host
++++ b/src/libgcc/config.host
+@@ -1399,4 +1399,8 @@ i[34567]86-*-linux* | x86_64-*-linux*)
+ fi
+ tm_file="${tm_file} i386/value-unwind.h"
+ ;;
++aarch64*-*-*)
++ # ILP32 needs an extra header for unwinding
++ tm_file="${tm_file} aarch64/value-unwind.h"
++ ;;
+ esac
+--- /dev/null
++++ b/src/libgcc/config/aarch64/value-unwind.h
+@@ -0,0 +1,25 @@
++/* Store register values as _Unwind_Word type in DWARF2 EH unwind context.
++ Copyright (C) 2017 Free Software Foundation, Inc.
++
++ This file is part of GCC.
++
++ GCC is free software; you can redistribute it and/or modify it
++ under the terms of the GNU General Public License as published
++ by the Free Software Foundation; either version 3, or (at your
++ option) any later version.
++
++ GCC is distributed in the hope that it will be useful, but WITHOUT
++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
++ License for more details.
++
++ You should have received a copy of the GNU General Public License and
++ a copy of the GCC Runtime Library Exception along with this program;
++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
++ <http://www.gnu.org/licenses/>. */
++
++/* Define this macro if the target stores register values as _Unwind_Word
++ type in unwind context. Only enable it for ilp32. */
++#if defined __aarch64__ && !defined __LP64__
++# define REG_VALUE_IN_UNWIND_CONTEXT
++#endif
--- a/src/libgcc/config/arm/bpabi-v6m.S
+++ b/src/libgcc/config/arm/bpabi-v6m.S
@@ -1,4 +1,5 @@
@@ -161146,7 +162091,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
fi
--- a/src/libstdc++-v3/configure
+++ b/src/libstdc++-v3/configure
-@@ -79518,8 +79518,7 @@ $as_echo "$ac_cv_x86_rdrand" >&6; }
+@@ -79519,8 +79519,7 @@ $as_echo "$ac_cv_x86_rdrand" >&6; }
# This depends on GLIBCXX_ENABLE_SYMVERS and GLIBCXX_IS_NATIVE.
@@ -161156,7 +162101,7 @@ LANG=C git diff --no-renames 9087fb2ff49a31be20f2a118a863b550ac58e26d..aad858c02
setrlimit_have_headers=yes
for ac_header in unistd.h sys/time.h sys/resource.h
-@@ -79748,6 +79747,7 @@ $as_echo "#define _GLIBCXX_RES_LIMITS 1" >>confdefs.h
+@@ -79749,6 +79748,7 @@ $as_echo "#define _GLIBCXX_RES_LIMITS 1" >>confdefs.h
$as_echo "$ac_res_limits" >&6; }
--
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