[gcc-7] 70/354: * GCC 7 snapshot build, taken from the trunk 20161208. - Revert r243346, breaking bootstrap on AArch64.
Ximin Luo
infinity0 at debian.org
Thu Nov 23 15:50:32 UTC 2017
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in repository gcc-7.
commit 4374cfed0b0836f529ded94520c6e8e50791ed59
Author: doko <doko at 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca>
Date: Thu Dec 8 11:07:37 2016 +0000
* GCC 7 snapshot build, taken from the trunk 20161208.
- Revert r243346, breaking bootstrap on AArch64.
git-svn-id: svn+ssh://svn.debian.org/svn/gcccvs/branches/sid/gcc-7@9172 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca
---
debian/changelog | 6 +-
debian/patches/r243346-revert.diff | 115 +++++++++++++++++++++++++++++++++++++
debian/rules.patch | 1 +
3 files changed, 120 insertions(+), 2 deletions(-)
diff --git a/debian/changelog b/debian/changelog
index 02ef7aa..eb09dde 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,10 +1,12 @@
-gcc-7 (7-20161201-2) UNRELEASED; urgency=medium
+gcc-7 (7-20161208-1) UNRELEASED; urgency=medium
+ * GCC 7 snapshot build, taken from the trunk 20161208.
+ - Revert r243346, breaking bootstrap on AArch64.
* Build the cilk runtime on armel, armhf, sparc and sparc64.
* Use --push-state/--pop-state for gold as well when linking libtsan.
* In GCC ICE dumps, prefix each line with the PID of the driver.
- -- Matthias Klose <doko at debian.org> Thu, 01 Dec 2016 20:10:32 +0100
+ -- Matthias Klose <doko at debian.org> Thu, 08 Dec 2016 12:02:16 +0100
gcc-7 (7-20161201-1) experimental; urgency=medium
diff --git a/debian/patches/r243346-revert.diff b/debian/patches/r243346-revert.diff
new file mode 100644
index 0000000..0d5596c
--- /dev/null
+++ b/debian/patches/r243346-revert.diff
@@ -0,0 +1,115 @@
+Index: b/src/gcc/ChangeLog
+===================================================================
+--- a/src/gcc/ChangeLog
++++ b/src/gcc/ChangeLog
+@@ -195,16 +195,6 @@
+ * gcc/ira.c (ira_setup_eliminable_regset): Initialize crtl->is_leaf.
+ (ira): Move initialization of crtl->is_leaf earlier.
+
+-2016-12-07 Wilco Dijkstra <wdijkstr at arm.com>
+-
+- * config/aarch64/aarch64.md (movti_aarch64): Change Ump to m.
+- (movtf_aarch64): Likewise.
+- * config/aarch64/aarch64.c (aarch64_classify_address):
+- Use correct intersection of offsets.
+- (aarch64_legitimize_address_displacement): Use 9-bit signed offsets.
+- (aarch64_legitimize_address): Use 9-bit signed offsets for TI/TF mode.
+- Use 7-bit signed scaled mode for modes > 16 bytes.
+-
+ 2016-12-07 James Greenhalgh <james.greenhalgh at arm.com>
+
+ PR rtl-optimization/78561
+Index: b/src/gcc/config/aarch64/aarch64.md
+===================================================================
+--- a/src/gcc/config/aarch64/aarch64.md
++++ b/src/gcc/config/aarch64/aarch64.md
+@@ -1120,9 +1120,9 @@
+
+ (define_insn "*movti_aarch64"
+ [(set (match_operand:TI 0
+- "nonimmediate_operand" "=r, *w,r ,*w,r,m,m,*w,m")
++ "nonimmediate_operand" "=r, *w,r ,*w,r ,Ump,Ump,*w,m")
+ (match_operand:TI 1
+- "aarch64_movti_operand" " rn,r ,*w,*w,m,r,Z, m,*w"))]
++ "aarch64_movti_operand" " rn,r ,*w,*w,Ump,r ,Z , m,*w"))]
+ "(register_operand (operands[0], TImode)
+ || aarch64_reg_or_zero (operands[1], TImode))"
+ "@
+@@ -1237,9 +1237,9 @@
+
+ (define_insn "*movtf_aarch64"
+ [(set (match_operand:TF 0
+- "nonimmediate_operand" "=w,?&r,w ,?r,w,?w,w,m,?r,m ,m")
++ "nonimmediate_operand" "=w,?&r,w ,?r,w,?w,w,m,?r ,Ump,Ump")
+ (match_operand:TF 1
+- "general_operand" " w,?r, ?r,w ,Y,Y ,m,w,m ,?r,Y"))]
++ "general_operand" " w,?r, ?r,w ,Y,Y ,m,w,Ump,?r ,Y"))]
+ "TARGET_FLOAT && (register_operand (operands[0], TFmode)
+ || aarch64_reg_or_fp_zero (operands[1], TFmode))"
+ "@
+Index: b/src/gcc/config/aarch64/aarch64.c
+===================================================================
+--- a/src/gcc/config/aarch64/aarch64.c
++++ b/src/gcc/config/aarch64/aarch64.c
+@@ -4335,8 +4335,7 @@ aarch64_classify_address (struct aarch64
+ instruction memory accesses. */
+ if (mode == TImode || mode == TFmode)
+ return (aarch64_offset_7bit_signed_scaled_p (DImode, offset)
+- && (offset_9bit_signed_unscaled_p (mode, offset)
+- || offset_12bit_unsigned_scaled_p (mode, offset)));
++ && offset_9bit_signed_unscaled_p (mode, offset));
+
+ /* A 7bit offset check because OImode will emit a ldp/stp
+ instruction (only big endian will get here).
+@@ -4540,19 +4539,18 @@ aarch64_legitimate_address_p (machine_mo
+ /* Split an out-of-range address displacement into a base and offset.
+ Use 4KB range for 1- and 2-byte accesses and a 16KB range otherwise
+ to increase opportunities for sharing the base address of different sizes.
+- For unaligned accesses and TI/TF mode use the signed 9-bit range. */
++ For TI/TFmode and unaligned accesses use a 256-byte range. */
+ static bool
+ aarch64_legitimize_address_displacement (rtx *disp, rtx *off, machine_mode mode)
+ {
+- HOST_WIDE_INT offset = INTVAL (*disp);
+- HOST_WIDE_INT base = offset & ~(GET_MODE_SIZE (mode) < 4 ? 0xfff : 0x3ffc);
++ HOST_WIDE_INT mask = GET_MODE_SIZE (mode) < 4 ? 0xfff : 0x3fff;
+
+- if (mode == TImode || mode == TFmode
+- || (offset & (GET_MODE_SIZE (mode) - 1)) != 0)
+- base = (offset + 0x100) & ~0x1ff;
++ if (mode == TImode || mode == TFmode ||
++ (INTVAL (*disp) & (GET_MODE_SIZE (mode) - 1)) != 0)
++ mask = 0xff;
+
+- *off = GEN_INT (base);
+- *disp = GEN_INT (offset - base);
++ *off = GEN_INT (INTVAL (*disp) & ~mask);
++ *disp = GEN_INT (INTVAL (*disp) & mask);
+ return true;
+ }
+
+@@ -5419,10 +5417,12 @@ aarch64_legitimize_address (rtx x, rtx /
+ x = gen_rtx_PLUS (Pmode, base, offset_rtx);
+ }
+
+- /* Does it look like we'll need a 16-byte load/store-pair operation? */
++ /* Does it look like we'll need a load/store-pair operation? */
+ HOST_WIDE_INT base_offset;
+- if (GET_MODE_SIZE (mode) > 16)
+- base_offset = (offset + 0x400) & ~0x7f0;
++ if (GET_MODE_SIZE (mode) > 16
++ || mode == TImode)
++ base_offset = ((offset + 64 * GET_MODE_SIZE (mode))
++ & ~((128 * GET_MODE_SIZE (mode)) - 1));
+ /* For offsets aren't a multiple of the access size, the limit is
+ -256...255. */
+ else if (offset & (GET_MODE_SIZE (mode) - 1))
+@@ -5436,8 +5436,6 @@ aarch64_legitimize_address (rtx x, rtx /
+ /* Small negative offsets are supported. */
+ else if (IN_RANGE (offset, -256, 0))
+ base_offset = 0;
+- else if (mode == TImode || mode == TFmode)
+- base_offset = (offset + 0x100) & ~0x1ff;
+ /* Use 12-bit offset by access size. */
+ else
+ base_offset = offset & (~0xfff * GET_MODE_SIZE (mode));
diff --git a/debian/rules.patch b/debian/rules.patch
index 65a6d57..1045afc 100644
--- a/debian/rules.patch
+++ b/debian/rules.patch
@@ -69,6 +69,7 @@ debian_patches += \
PR55947-revert \
libffi-pax \
libffi-race-condition \
+ r243346-revert \
ifeq ($(libstdcxx_abi),new)
--
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