[gcc-7] 260/354: * Update to SVN 20170731 (r250749) from the gcc-7-branch.
Ximin Luo
infinity0 at debian.org
Thu Nov 23 15:51:04 UTC 2017
This is an automated email from the git hooks/post-receive script.
infinity0 pushed a commit to branch master
in repository gcc-7.
commit 976c98dcb5658862635f64424c3d3bfe71700fb6
Author: doko <doko at 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca>
Date: Mon Jul 31 17:42:59 2017 +0000
* Update to SVN 20170731 (r250749) from the gcc-7-branch.
git-svn-id: svn+ssh://svn.debian.org/svn/gcccvs/branches/sid/gcc-7@9598 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca
---
debian/changelog | 2 +
debian/patches/svn-updates.diff | 15894 ++++++++++++++++++++++++++++++++++++--
debian/rules.defs | 2 +-
3 files changed, 15394 insertions(+), 504 deletions(-)
diff --git a/debian/changelog b/debian/changelog
index 66cc876..2df2223 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,5 +1,7 @@
gcc-7 (7.1.0-11) UNRELEASED; urgency=medium
+ * Update to SVN 20170731 (r250749) from the gcc-7-branch.
+
[ Matthias Klose ]
* Update sanitizer symbols for ppc64 and sparc64.
diff --git a/debian/patches/svn-updates.diff b/debian/patches/svn-updates.diff
index e87a09c..ef2b8ec 100644
--- a/debian/patches/svn-updates.diff
+++ b/debian/patches/svn-updates.diff
@@ -1,14 +1,14 @@
-# DP: updates from the 7 branch upto 20170722 (r250453).
+# DP: updates from the 7 branch upto 20170731 (r250749).
last_update()
{
cat > ${dir}LAST_UPDATED <EOF
-Sat Jul 22 12:21:58 CEST 2017
-Sat Jul 22 10:21:58 UTC 2017 (revision 250453)
+Mon Jul 31 19:33:17 CEST 2017
+Mon Jul 31 17:33:17 UTC 2017 (revision 250749)
EOF
}
-LANG=C svn diff svn://gcc.gnu.org/svn/gcc/tags/gcc_7_1_0_release svn://gcc.gnu.org/svn/gcc/branches/gcc-7-branch@249738 \
+LANG=C svn diff svn://gcc.gnu.org/svn/gcc/tags/gcc_7_1_0_release svn://gcc.gnu.org/svn/gcc/branches/gcc-7-branch \
| sed -r 's,^--- (\S+)\t(\S+)(.*)$,--- a/src/\1\t\2,;s,^\+\+\+ (\S+)\t(\S+)(.*)$,+++ b/src/\1\t\2,' \
| awk '/^Index:.*\.(class|texi)/ {skip=1; next} /^Index:/ { skip=0 } skip==0'
@@ -448,6 +448,120 @@ Index: libgomp/config/linux/affinity.c
}
void
+Index: libquadmath/ChangeLog
+===================================================================
+--- a/src/libquadmath/ChangeLog (.../tags/gcc_7_1_0_release)
++++ b/src/libquadmath/ChangeLog (.../branches/gcc-7-branch)
+@@ -1,3 +1,8 @@
++2017-07-20 Jakub Jelinek <jakub at redhat.com>
++
++ PR libquadmath/65757
++ * math/roundq.c: Cherry-pick upstream glibc 2015-04-28 change.
++
+ 2017-05-02 Release Manager
+
+ * GCC 7.1.0 released.
+Index: libquadmath/math/roundq.c
+===================================================================
+--- a/src/libquadmath/math/roundq.c (.../tags/gcc_7_1_0_release)
++++ b/src/libquadmath/math/roundq.c (.../branches/gcc-7-branch)
+@@ -1,5 +1,5 @@
+ /* Round __float128 to integer away from zero.
+- Copyright (C) 1997, 1999 Free Software Foundation, Inc.
++ Copyright (C) 1997-2017 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+ Contributed by Ulrich Drepper <drepper at cygnus.com>, 1997 and
+ Jakub Jelinek <jj at ultra.linux.cz>, 1999.
+@@ -32,7 +32,7 @@
+
+ GET_FLT128_WORDS64 (i0, i1, x);
+ j0 = ((i0 >> 48) & 0x7fff) - 0x3fff;
+- if (j0 < 31)
++ if (j0 < 48)
+ {
+ if (j0 < 0)
+ {
+Index: libsanitizer/sanitizer_common/sanitizer_linux.cc
+===================================================================
+--- a/src/libsanitizer/sanitizer_common/sanitizer_linux.cc (.../tags/gcc_7_1_0_release)
++++ b/src/libsanitizer/sanitizer_common/sanitizer_linux.cc (.../branches/gcc-7-branch)
+@@ -605,8 +605,7 @@
+ }
+ #endif
+
+-uptr internal_sigaltstack(const struct sigaltstack *ss,
+- struct sigaltstack *oss) {
++uptr internal_sigaltstack(const void *ss, void *oss) {
+ return internal_syscall(SYSCALL(sigaltstack), (uptr)ss, (uptr)oss);
+ }
+
+Index: libsanitizer/sanitizer_common/sanitizer_linux.h
+===================================================================
+--- a/src/libsanitizer/sanitizer_common/sanitizer_linux.h (.../tags/gcc_7_1_0_release)
++++ b/src/libsanitizer/sanitizer_common/sanitizer_linux.h (.../branches/gcc-7-branch)
+@@ -19,7 +19,6 @@
+ #include "sanitizer_platform_limits_posix.h"
+
+ struct link_map; // Opaque type returned by dlopen().
+-struct sigaltstack;
+
+ namespace __sanitizer {
+ // Dirent structure for getdents(). Note that this structure is different from
+@@ -28,8 +27,7 @@
+
+ // Syscall wrappers.
+ uptr internal_getdents(fd_t fd, struct linux_dirent *dirp, unsigned int count);
+-uptr internal_sigaltstack(const struct sigaltstack* ss,
+- struct sigaltstack* oss);
++uptr internal_sigaltstack(const void* ss, void* oss);
+ uptr internal_sigprocmask(int how, __sanitizer_sigset_t *set,
+ __sanitizer_sigset_t *oldset);
+
+Index: libsanitizer/sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cc
+===================================================================
+--- a/src/libsanitizer/sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cc (.../tags/gcc_7_1_0_release)
++++ b/src/libsanitizer/sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cc (.../branches/gcc-7-branch)
+@@ -273,7 +273,7 @@
+
+ // Alternate stack for signal handling.
+ InternalScopedBuffer<char> handler_stack_memory(kHandlerStackSize);
+- struct sigaltstack handler_stack;
++ stack_t handler_stack;
+ internal_memset(&handler_stack, 0, sizeof(handler_stack));
+ handler_stack.ss_sp = handler_stack_memory.data();
+ handler_stack.ss_size = kHandlerStackSize;
+Index: libsanitizer/ChangeLog
+===================================================================
+--- a/src/libsanitizer/ChangeLog (.../tags/gcc_7_1_0_release)
++++ b/src/libsanitizer/ChangeLog (.../branches/gcc-7-branch)
+@@ -1,3 +1,14 @@
++2017-07-17 Jakub Jelinek <jakub at redhat.com>
++
++ Backported from mainline
++ 2017-07-14 Jakub Jelinek <jakub at redhat.com>
++
++ PR sanitizer/81066
++ * sanitizer_common/sanitizer_linux.h: Cherry-pick upstream r307969.
++ * sanitizer_common/sanitizer_linux.cc: Likewise.
++ * sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cc: Likewise.
++ * tsan/tsan_platform_linux.cc: Likewise.
++
+ 2017-05-02 Release Manager
+
+ * GCC 7.1.0 released.
+Index: libsanitizer/tsan/tsan_platform_linux.cc
+===================================================================
+--- a/src/libsanitizer/tsan/tsan_platform_linux.cc (.../tags/gcc_7_1_0_release)
++++ b/src/libsanitizer/tsan/tsan_platform_linux.cc (.../branches/gcc-7-branch)
+@@ -287,7 +287,7 @@
+ int ExtractResolvFDs(void *state, int *fds, int nfd) {
+ #if SANITIZER_LINUX && !SANITIZER_ANDROID
+ int cnt = 0;
+- __res_state *statp = (__res_state*)state;
++ struct __res_state *statp = (struct __res_state*)state;
+ for (int i = 0; i < MAXNS && cnt < nfd; i++) {
+ if (statp->_u._ext.nsaddrs[i] && statp->_u._ext.nssocks[i] != -1)
+ fds[cnt++] = statp->_u._ext.nssocks[i];
Index: libstdc++-v3/configure
===================================================================
--- a/src/libstdc++-v3/configure (.../tags/gcc_7_1_0_release)
@@ -510,6 +624,40 @@ Index: libstdc++-v3/doc/xml/manual/allocator.xml
containers.
</para>
</listitem>
+Index: libstdc++-v3/doc/xml/manual/intro.xml
+===================================================================
+--- a/src/libstdc++-v3/doc/xml/manual/intro.xml (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/doc/xml/manual/intro.xml (.../branches/gcc-7-branch)
+@@ -1119,6 +1119,29 @@
+ arguments and store them directly as the target object.
+ </para></listitem></varlistentry>
+
++ <varlistentry><term><link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="&DR;#2802">2802</link>:
++ <emphasis>Add noexcept to several <code>shared_ptr</code> related
++ functions
++ </emphasis>
++ </term>
++ <listitem><para>Add noexcept.
++ </para></listitem></varlistentry>
++
++ <varlistentry><term><link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="&DR;#2873">2873</link>:
++ <emphasis><code>shared_ptr</code> constructor requirements for a deleter
++ </emphasis>
++ </term>
++ <listitem><para>Use rvalues for deleters.
++ </para></listitem></varlistentry>
++
++ <varlistentry><term><link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="&DR;#2942">2942</link>:
++ <emphasis>LWG 2873's resolution missed
++ <code>weak_ptr::owner_before</code>
++ </emphasis>
++ </term>
++ <listitem><para>Add noexcept.
++ </para></listitem></varlistentry>
++
+ </variablelist>
+
+ </section>
Index: libstdc++-v3/doc/xml/manual/abi.xml
===================================================================
--- a/src/libstdc++-v3/doc/xml/manual/abi.xml (.../tags/gcc_7_1_0_release)
@@ -533,6 +681,27 @@ Index: libstdc++-v3/doc/xml/manual/abi.xml
</itemizedlist>
</listitem>
+Index: libstdc++-v3/doc/xml/manual/status_cxx2017.xml
+===================================================================
+--- a/src/libstdc++-v3/doc/xml/manual/status_cxx2017.xml (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/doc/xml/manual/status_cxx2017.xml (.../branches/gcc-7-branch)
+@@ -878,7 +878,6 @@
+ </row>
+
+ <row>
+- <?dbhtml bgcolor="#C8B0B0" ?>
+ <entry>
+ <link xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2015/n4519.pdf">
+ N4519
+@@ -885,7 +884,7 @@
+ </link>
+ </entry>
+ <entry> Source-Code Information Capture </entry>
+- <entry>N</entry>
++ <entry>Y</entry>
+ <entry>Library Fundamentals 2 TS</entry>
+ </row>
+
Index: libstdc++-v3/doc/xml/manual/build_hacking.xml
===================================================================
--- a/src/libstdc++-v3/doc/xml/manual/build_hacking.xml (.../tags/gcc_7_1_0_release)
@@ -624,6 +793,24 @@ Index: libstdc++-v3/doc/xml/manual/test.xml
N.B. that set of variations could also be written as
<literal>unix/-O3\"{-std=gnu++98,-std=gnu++11,}\"</literal> so that
the third variation would use the default for <option>-std</option>
+Index: libstdc++-v3/doc/html/manual/status.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/status.html (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/status.html (.../branches/gcc-7-branch)
+@@ -824,11 +824,11 @@
+ <a class="link" href="http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2015/n4502.pdf" target="_top">
+ N4502
+ </a>
+- </td><td align="left"> Support for the C++ Detection Idiom, V2 </td><td align="left">Y</td><td align="left">Library Fundamentals 2 TS</td></tr><tr bgcolor="#C8B0B0"><td align="left">
++ </td><td align="left"> Support for the C++ Detection Idiom, V2 </td><td align="left">Y</td><td align="left">Library Fundamentals 2 TS</td></tr><tr><td align="left">
+ <a class="link" href="http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2015/n4519.pdf" target="_top">
+ N4519
+ </a>
+- </td><td align="left"> Source-Code Information Capture </td><td align="left">N</td><td align="left">Library Fundamentals 2 TS</td></tr><tr bgcolor="#C8B0B0"><td align="left">
++ </td><td align="left"> Source-Code Information Capture </td><td align="left">Y</td><td align="left">Library Fundamentals 2 TS</td></tr><tr bgcolor="#C8B0B0"><td align="left">
+ <a class="link" href="http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2015/n4521.html" target="_top">
+ N4521
+ </a>
Index: libstdc++-v3/doc/html/manual/policy_data_structures.html
===================================================================
--- a/src/libstdc++-v3/doc/html/manual/policy_data_structures.html (.../tags/gcc_7_1_0_release)
@@ -672,6 +859,30 @@ Index: libstdc++-v3/doc/html/manual/abi.html
__GXX_ABI_VERSION. This macro is defined as the version of the
compiler v3 ABI, with g++ 3.0 being version 100. This macro will
be automatically defined whenever g++ is used (the curious can
+Index: libstdc++-v3/doc/html/manual/bugs.html
+===================================================================
+--- a/src/libstdc++-v3/doc/html/manual/bugs.html (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/doc/html/manual/bugs.html (.../branches/gcc-7-branch)
+@@ -504,4 +504,18 @@
+ </em></span>
+ </span></dt><dd><p>Remove special handling for <code class="code">reference_wrapper</code>
+ arguments and store them directly as the target object.
++ </p></dd><dt><span class="term"><a class="link" href="http://www.open-std.org/jtc1/sc22/wg21/docs/lwg-defects.html#2802" target="_top">2802</a>:
++ <span class="emphasis"><em>Add noexcept to several <code class="code">shared_ptr</code> related
++ functions
++ </em></span>
++ </span></dt><dd><p>Add noexcept.
++ </p></dd><dt><span class="term"><a class="link" href="http://www.open-std.org/jtc1/sc22/wg21/docs/lwg-defects.html#2873" target="_top">2873</a>:
++ <span class="emphasis"><em><code class="code">shared_ptr</code> constructor requirements for a deleter
++ </em></span>
++ </span></dt><dd><p>Use rvalues for deleters.
++ </p></dd><dt><span class="term"><a class="link" href="http://www.open-std.org/jtc1/sc22/wg21/docs/lwg-defects.html#2942" target="_top">2942</a>:
++ <span class="emphasis"><em>LWG 2873's resolution missed
++ <code class="code">weak_ptr::owner_before</code>
++ </em></span>
++ </span></dt><dd><p>Add noexcept.
+ </p></dd></dl></div></div></div><div class="navfooter"><hr /><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="license.html">Prev</a> </td><td width="20%" align="center"><a accesskey="u" href="status.html">Up</a></td><td width="40%" align="right"> <a accesskey="n" href="setup.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">License </td><td width="20%" align="center"><a accesskey="h" href="../index.html">Home [...]
+\ No newline at end of file
Index: libstdc++-v3/doc/html/manual/memory.html
===================================================================
--- a/src/libstdc++-v3/doc/html/manual/memory.html (.../tags/gcc_7_1_0_release)
@@ -783,6 +994,18 @@ Index: libstdc++-v3/doc/html/manual/source_code_style.html
(The most tempting of these seem to be and "_T" and "__sz".)<br />
<br />
Names must never have "__" internally; it would confuse name<br />
+Index: libstdc++-v3/include/Makefile.in
+===================================================================
+--- a/src/libstdc++-v3/include/Makefile.in (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/include/Makefile.in (.../branches/gcc-7-branch)
+@@ -971,6 +971,7 @@
+ ${experimental_srcdir}/ratio \
+ ${experimental_srcdir}/regex \
+ ${experimental_srcdir}/set \
++ ${experimental_srcdir}/source_location \
+ ${experimental_srcdir}/string \
+ ${experimental_srcdir}/string_view \
+ ${experimental_srcdir}/system_error \
Index: libstdc++-v3/include/std/utility
===================================================================
--- a/src/libstdc++-v3/include/std/utility (.../tags/gcc_7_1_0_release)
@@ -823,6 +1046,187 @@ Index: libstdc++-v3/include/std/utility
/// Gives the type of the ith element of a given tuple type.
template<std::size_t __i, typename _Tp>
struct tuple_element;
+Index: libstdc++-v3/include/std/future
+===================================================================
+--- a/src/libstdc++-v3/include/std/future (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/include/std/future (.../branches/gcc-7-branch)
+@@ -471,7 +471,6 @@
+ // Used by std::promise to copy construct the result.
+ typename promise<_Res>::_Ptr_type operator()() const
+ {
+- _State_baseV2::_S_check(_M_promise->_M_future);
+ _M_promise->_M_storage->_M_set(*_M_arg);
+ return std::move(_M_promise->_M_storage);
+ }
+@@ -486,7 +485,6 @@
+ // Used by std::promise to move construct the result.
+ typename promise<_Res>::_Ptr_type operator()() const
+ {
+- _State_baseV2::_S_check(_M_promise->_M_future);
+ _M_promise->_M_storage->_M_set(std::move(*_M_arg));
+ return std::move(_M_promise->_M_storage);
+ }
+@@ -494,6 +492,18 @@
+ _Res* _M_arg;
+ };
+
++ // set void
++ template<typename _Res>
++ struct _Setter<_Res, void>
++ {
++ static_assert(is_void<_Res>::value, "Only used for promise<void>");
++
++ typename promise<_Res>::_Ptr_type operator()() const
++ { return std::move(_M_promise->_M_storage); }
++
++ promise<_Res>* _M_promise;
++ };
++
+ struct __exception_ptr_tag { };
+
+ // set exceptions
+@@ -503,7 +513,6 @@
+ // Used by std::promise to store an exception as the result.
+ typename promise<_Res>::_Ptr_type operator()() const
+ {
+- _State_baseV2::_S_check(_M_promise->_M_future);
+ _M_promise->_M_storage->_M_error = *_M_ex;
+ return std::move(_M_promise->_M_storage);
+ }
+@@ -516,6 +525,7 @@
+ static _Setter<_Res, _Arg&&>
+ __setter(promise<_Res>* __prom, _Arg&& __arg)
+ {
++ _S_check(__prom->_M_future);
+ return _Setter<_Res, _Arg&&>{ __prom, std::__addressof(__arg) };
+ }
+
+@@ -523,9 +533,18 @@
+ static _Setter<_Res, __exception_ptr_tag>
+ __setter(exception_ptr& __ex, promise<_Res>* __prom)
+ {
++ _S_check(__prom->_M_future);
+ return _Setter<_Res, __exception_ptr_tag>{ __prom, &__ex };
+ }
+
++ template<typename _Res>
++ static _Setter<_Res, void>
++ __setter(promise<_Res>* __prom)
++ {
++ _S_check(__prom->_M_future);
++ return _Setter<_Res, void>{ __prom };
++ }
++
+ template<typename _Tp>
+ static void
+ _S_check(const shared_ptr<_Tp>& __p)
+@@ -1027,6 +1046,7 @@
+ typedef __future_base::_Result<_Res> _Res_type;
+ typedef __future_base::_Ptr<_Res_type> _Ptr_type;
+ template<typename, typename> friend class _State::_Setter;
++ friend _State;
+
+ shared_ptr<_State> _M_future;
+ _Ptr_type _M_storage;
+@@ -1137,6 +1157,7 @@
+ typedef __future_base::_Result<_Res&> _Res_type;
+ typedef __future_base::_Ptr<_Res_type> _Ptr_type;
+ template<typename, typename> friend class _State::_Setter;
++ friend _State;
+
+ shared_ptr<_State> _M_future;
+ _Ptr_type _M_storage;
+@@ -1226,6 +1247,7 @@
+ typedef __future_base::_Result<void> _Res_type;
+ typedef __future_base::_Ptr<_Res_type> _Ptr_type;
+ template<typename, typename> friend class _State::_Setter;
++ friend _State;
+
+ shared_ptr<_State> _M_future;
+ _Ptr_type _M_storage;
+@@ -1286,7 +1308,9 @@
+ { return future<void>(_M_future); }
+
+ // Setting the result
+- void set_value();
++ void
++ set_value()
++ { _M_future->_M_set_result(_State::__setter(this)); }
+
+ void
+ set_exception(exception_ptr __p)
+@@ -1293,7 +1317,8 @@
+ { _M_future->_M_set_result(_State::__setter(__p, this)); }
+
+ void
+- set_value_at_thread_exit();
++ set_value_at_thread_exit()
++ { _M_future->_M_set_delayed_result(_State::__setter(this), _M_future); }
+
+ void
+ set_exception_at_thread_exit(exception_ptr __p)
+@@ -1303,30 +1328,6 @@
+ }
+ };
+
+- // set void
+- template<>
+- struct __future_base::_State_base::_Setter<void, void>
+- {
+- promise<void>::_Ptr_type operator()() const
+- {
+- _State_base::_S_check(_M_promise->_M_future);
+- return std::move(_M_promise->_M_storage);
+- }
+-
+- promise<void>* _M_promise;
+- };
+-
+- inline void
+- promise<void>::set_value()
+- { _M_future->_M_set_result(_State::_Setter<void, void>{ this }); }
+-
+- inline void
+- promise<void>::set_value_at_thread_exit()
+- {
+- _M_future->_M_set_delayed_result(_State::_Setter<void, void>{this},
+- _M_future);
+- }
+-
+ template<typename _Ptr_type, typename _Fn, typename _Res>
+ struct __future_base::_Task_setter
+ {
+Index: libstdc++-v3/include/std/mutex
+===================================================================
+--- a/src/libstdc++-v3/include/std/mutex (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/include/std/mutex (.../branches/gcc-7-branch)
+@@ -557,7 +557,7 @@
+ }
+
+ #if __cplusplus > 201402L
+-#define __cpp_lib_scoped_lock 201703
++#define __cpp_lib_scoped_lock 201707
+ /** @brief A scoped lock type for multiple lockable objects.
+ *
+ * A scoped_lock controls mutex ownership within a scope, releasing
+@@ -570,7 +570,7 @@
+ explicit scoped_lock(_MutexTypes&... __m) : _M_devices(std::tie(__m...))
+ { std::lock(__m...); }
+
+- explicit scoped_lock(_MutexTypes&... __m, adopt_lock_t) noexcept
++ explicit scoped_lock(adopt_lock_t, _MutexTypes&... __m) noexcept
+ : _M_devices(std::tie(__m...))
+ { } // calling thread owns mutex
+
+@@ -609,7 +609,7 @@
+ explicit scoped_lock(mutex_type& __m) : _M_device(__m)
+ { _M_device.lock(); }
+
+- explicit scoped_lock(mutex_type& __m, adopt_lock_t) noexcept
++ explicit scoped_lock(adopt_lock_t, mutex_type& __m) noexcept
+ : _M_device(__m)
+ { } // calling thread owns mutex
+
Index: libstdc++-v3/include/std/functional
===================================================================
--- a/src/libstdc++-v3/include/std/functional (.../tags/gcc_7_1_0_release)
@@ -925,6 +1329,92 @@ Index: libstdc++-v3/include/std/istream
}
#endif // C++11
+Index: libstdc++-v3/include/std/variant
+===================================================================
+--- a/src/libstdc++-v3/include/std/variant (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/include/std/variant (.../branches/gcc-7-branch)
+@@ -44,6 +44,9 @@
+ #include <bits/invoke.h>
+ #include <ext/aligned_buffer.h>
+ #include <bits/parse_numbers.h>
++#include <bits/stl_iterator_base_types.h>
++#include <bits/stl_iterator_base_funcs.h>
++#include <bits/stl_construct.h>
+
+ namespace std _GLIBCXX_VISIBILITY(default)
+ {
+@@ -238,30 +241,32 @@
+ // Various functions as "vtable" entries, where those vtables are used by
+ // polymorphic operations.
+ template<typename _Lhs, typename _Rhs>
+- constexpr void
++ void
+ __erased_ctor(void* __lhs, void* __rhs)
+- { ::new (__lhs) remove_reference_t<_Lhs>(__ref_cast<_Rhs>(__rhs)); }
++ {
++ using _Type = remove_reference_t<_Lhs>;
++ ::new (__lhs) _Type(__variant::__ref_cast<_Rhs>(__rhs));
++ }
+
+ template<typename _Variant, size_t _Np>
+- constexpr void
++ void
+ __erased_dtor(_Variant&& __v)
+- {
+- auto&& __element = __get<_Np>(std::forward<_Variant>(__v));
+- using _Type = std::remove_reference_t<decltype(__element)>;
+- __element.~_Type();
+- }
++ { std::_Destroy(std::__addressof(__get<_Np>(__v))); }
+
+ template<typename _Lhs, typename _Rhs>
+- constexpr void
++ void
+ __erased_assign(void* __lhs, void* __rhs)
+- { __ref_cast<_Lhs>(__lhs) = __ref_cast<_Rhs>(__rhs); }
++ {
++ __variant::__ref_cast<_Lhs>(__lhs) = __variant::__ref_cast<_Rhs>(__rhs);
++ }
+
+ template<typename _Lhs, typename _Rhs>
+- constexpr void
++ void
+ __erased_swap(void* __lhs, void* __rhs)
+ {
+ using std::swap;
+- swap(__ref_cast<_Lhs>(__lhs), __ref_cast<_Rhs>(__rhs));
++ swap(__variant::__ref_cast<_Lhs>(__lhs),
++ __variant::__ref_cast<_Rhs>(__rhs));
+ }
+
+ #define _VARIANT_RELATION_FUNCTION_TEMPLATE(__OP, __NAME) \
+@@ -283,11 +288,11 @@
+ #undef _VARIANT_RELATION_FUNCTION_TEMPLATE
+
+ template<typename _Tp>
+- constexpr size_t
++ size_t
+ __erased_hash(void* __t)
+ {
+ return std::hash<remove_cv_t<remove_reference_t<_Tp>>>{}(
+- __ref_cast<_Tp>(__t));
++ __variant::__ref_cast<_Tp>(__t));
+ }
+
+ // Defines members and ctors.
+@@ -936,9 +941,10 @@
+ noexcept((is_nothrow_move_constructible_v<_Types> && ...)) = default;
+
+ template<typename _Tp,
++ typename = enable_if_t<!is_same_v<decay_t<_Tp>, variant>>,
++ typename = enable_if_t<(sizeof...(_Types)>0)>,
+ typename = enable_if_t<__exactly_once<__accepted_type<_Tp&&>>
+- && is_constructible_v<__accepted_type<_Tp&&>, _Tp&&>
+- && !is_same_v<decay_t<_Tp>, variant>>>
++ && is_constructible_v<__accepted_type<_Tp&&>, _Tp&&>>>
+ constexpr
+ variant(_Tp&& __t)
+ noexcept(is_nothrow_constructible_v<__accepted_type<_Tp&&>, _Tp&&>)
Index: libstdc++-v3/include/std/ostream
===================================================================
--- a/src/libstdc++-v3/include/std/ostream (.../tags/gcc_7_1_0_release)
@@ -1014,6 +1504,167 @@ Index: libstdc++-v3/include/std/ostream
}
#endif // C++11
+Index: libstdc++-v3/include/experimental/memory_resource
+===================================================================
+--- a/src/libstdc++-v3/include/experimental/memory_resource (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/include/experimental/memory_resource (.../branches/gcc-7-branch)
+@@ -168,8 +168,9 @@
+ template <typename _Tp1, typename... _Args> //used here
+ void construct(_Tp1* __p, _Args&&... __args)
+ {
+- auto __use_tag = __use_alloc<_Tp1, memory_resource*,
+- _Args...>(this->resource());
++ memory_resource* const __resource = this->resource();
++ auto __use_tag
++ = __use_alloc<_Tp1, memory_resource*, _Args...>(__resource);
+ _M_construct(__use_tag, __p, std::forward<_Args>(__args)...);
+ }
+
+@@ -180,10 +181,11 @@
+ tuple<_Args1...> __x,
+ tuple<_Args2...> __y)
+ {
++ memory_resource* const __resource = this->resource();
+ auto __x_use_tag =
+- __use_alloc<_Tp1, memory_resource*, _Args1...>(this->resource());
++ __use_alloc<_Tp1, memory_resource*, _Args1...>(__resource);
+ auto __y_use_tag =
+- __use_alloc<_Tp2, memory_resource*, _Args2...>(this->resource());
++ __use_alloc<_Tp2, memory_resource*, _Args2...>(__resource);
+
+ ::new(__p) std::pair<_Tp1, _Tp2>(piecewise_construct,
+ _M_construct_p(__x_use_tag, __x),
+Index: libstdc++-v3/include/experimental/source_location
+===================================================================
+--- a/src/libstdc++-v3/include/experimental/source_location (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/include/experimental/source_location (.../branches/gcc-7-branch)
+@@ -0,0 +1,86 @@
++// <experimental/source_location> -*- C++ -*-
++
++// Copyright (C) 2015 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library. This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++// GNU General Public License for more details.
++
++// Under Section 7 of GPL version 3, you are granted additional
++// permissions described in the GCC Runtime Library Exception, version
++// 3.1, as published by the Free Software Foundation.
++
++// You should have received a copy of the GNU General Public License and
++// a copy of the GCC Runtime Library Exception along with this program;
++// see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
++// <http://www.gnu.org/licenses/>.
++
++/** @file experimental/source_location
++ * This is a TS C++ Library header.
++ */
++
++#ifndef _GLIBCXX_EXPERIMENTAL_SRCLOC
++#define _GLIBCXX_EXPERIMENTAL_SRCLOC 1
++
++#include <cstdint>
++
++namespace std {
++namespace experimental {
++inline namespace fundamentals_v2 {
++_GLIBCXX_BEGIN_NAMESPACE_VERSION
++
++#define __cpp_lib_experimental_source_location 201505
++
++ struct source_location
++ {
++#ifndef _GLIBCXX_USE_C99_STDINT_TR1
++ private:
++ using uint_least32_t = unsigned;
++ public:
++#endif
++
++ // 14.1.2, source_location creation
++ static constexpr source_location
++ current(const char* __file = __builtin_FILE(),
++ const char* __func = __builtin_FUNCTION(),
++ int __line = __builtin_LINE(),
++ int __col = 0) noexcept
++ {
++ source_location __loc;
++ __loc._M_file = __file;
++ __loc._M_func = __func;
++ __loc._M_line = __line;
++ __loc._M_col = __col;
++ return __loc;
++ }
++
++ constexpr source_location() noexcept
++ : _M_file("unknown"), _M_func(_M_file), _M_line(0), _M_col(0)
++ { }
++
++ // 14.1.3, source_location field access
++ constexpr uint_least32_t line() const noexcept { return _M_line; }
++ constexpr uint_least32_t column() const noexcept { return _M_col; }
++ constexpr const char* file_name() const noexcept { return _M_file; }
++ constexpr const char* function_name() const noexcept { return _M_func; }
++
++ private:
++ const char* _M_file;
++ const char* _M_func;
++ uint_least32_t _M_line;
++ uint_least32_t _M_col;
++ };
++
++_GLIBCXX_END_NAMESPACE_VERSION
++} // namespace fundamentals_v2
++} // namespace experimental
++} // namespace std
++
++#endif
+Index: libstdc++-v3/include/bits/shared_ptr.h
+===================================================================
+--- a/src/libstdc++-v3/include/bits/shared_ptr.h (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/include/bits/shared_ptr.h (.../branches/gcc-7-branch)
+@@ -144,7 +144,7 @@
+ template<typename _Yp, typename _Deleter,
+ typename = _Constructible<_Yp*, _Deleter>>
+ shared_ptr(_Yp* __p, _Deleter __d)
+- : __shared_ptr<_Tp>(__p, __d) { }
++ : __shared_ptr<_Tp>(__p, std::move(__d)) { }
+
+ /**
+ * @brief Construct a %shared_ptr that owns a null pointer
+@@ -161,7 +161,7 @@
+ */
+ template<typename _Deleter>
+ shared_ptr(nullptr_t __p, _Deleter __d)
+- : __shared_ptr<_Tp>(__p, __d) { }
++ : __shared_ptr<_Tp>(__p, std::move(__d)) { }
+
+ /**
+ * @brief Construct a %shared_ptr that owns the pointer @a __p
+@@ -181,7 +181,7 @@
+ template<typename _Yp, typename _Deleter, typename _Alloc,
+ typename = _Constructible<_Yp*, _Deleter, _Alloc>>
+ shared_ptr(_Yp* __p, _Deleter __d, _Alloc __a)
+- : __shared_ptr<_Tp>(__p, __d, std::move(__a)) { }
++ : __shared_ptr<_Tp>(__p, std::move(__d), std::move(__a)) { }
+
+ /**
+ * @brief Construct a %shared_ptr that owns a null pointer
+@@ -200,7 +200,7 @@
+ */
+ template<typename _Deleter, typename _Alloc>
+ shared_ptr(nullptr_t __p, _Deleter __d, _Alloc __a)
+- : __shared_ptr<_Tp>(__p, __d, std::move(__a)) { }
++ : __shared_ptr<_Tp>(__p, std::move(__d), std::move(__a)) { }
+
+ // Aliasing constructor
+
Index: libstdc++-v3/include/bits/regex_compiler.h
===================================================================
--- a/src/libstdc++-v3/include/bits/regex_compiler.h (.../tags/gcc_7_1_0_release)
@@ -1053,6 +1704,111 @@ Index: libstdc++-v3/include/bits/locale_conv.h
}
// convert the put area and write to the byte stream buffer
+Index: libstdc++-v3/include/bits/stl_uninitialized.h
+===================================================================
+--- a/src/libstdc++-v3/include/bits/stl_uninitialized.h (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/include/bits/stl_uninitialized.h (.../branches/gcc-7-branch)
+@@ -831,77 +831,54 @@
+ inline void
+ uninitialized_default_construct(_ForwardIterator __first,
+ _ForwardIterator __last)
+- {
+- __uninitialized_default_novalue(__first, __last);
+- }
++ {
++ __uninitialized_default_novalue(__first, __last);
++ }
+
+ template <typename _ForwardIterator, typename _Size>
+ inline _ForwardIterator
+ uninitialized_default_construct_n(_ForwardIterator __first, _Size __count)
+- {
+- return __uninitialized_default_novalue_n(__first, __count);
+- }
++ {
++ return __uninitialized_default_novalue_n(__first, __count);
++ }
+
+ template <typename _ForwardIterator>
+ inline void
+ uninitialized_value_construct(_ForwardIterator __first,
+ _ForwardIterator __last)
+- {
+- return __uninitialized_default(__first, __last);
+- }
++ {
++ return __uninitialized_default(__first, __last);
++ }
+
+ template <typename _ForwardIterator, typename _Size>
+ inline _ForwardIterator
+ uninitialized_value_construct_n(_ForwardIterator __first, _Size __count)
+- {
+- return __uninitialized_default_n(__first, __count);
+- }
++ {
++ return __uninitialized_default_n(__first, __count);
++ }
+
+ template <typename _InputIterator, typename _ForwardIterator>
+ inline _ForwardIterator
+ uninitialized_move(_InputIterator __first, _InputIterator __last,
+ _ForwardIterator __result)
+- {
+- return std::uninitialized_copy
+- (_GLIBCXX_MAKE_MOVE_ITERATOR(__first),
+- _GLIBCXX_MAKE_MOVE_ITERATOR(__last), __result);
+- }
++ {
++ return std::uninitialized_copy
++ (_GLIBCXX_MAKE_MOVE_ITERATOR(__first),
++ _GLIBCXX_MAKE_MOVE_ITERATOR(__last), __result);
++ }
+
+ template <typename _InputIterator, typename _Size, typename _ForwardIterator>
+ inline pair<_InputIterator, _ForwardIterator>
+ uninitialized_move_n(_InputIterator __first, _Size __count,
+ _ForwardIterator __result)
+- {
+- auto __res = std::__uninitialized_copy_n_pair
+- (_GLIBCXX_MAKE_MOVE_ITERATOR(__first),
+- __count, __result);
+- return {__res.first.base(), __res.second};
+- }
+-
+- template <typename _Tp>
+- inline void
+- destroy_at(_Tp* __location)
+- {
+- std::_Destroy(__location);
+- }
+-
+- template <typename _ForwardIterator>
+- inline void
+- destroy(_ForwardIterator __first, _ForwardIterator __last)
+- {
+- std::_Destroy(__first, __last);
+- }
+-
+- template <typename _ForwardIterator, typename _Size>
+- inline _ForwardIterator
+- destroy_n(_ForwardIterator __first, _Size __count)
+- {
+- return std::_Destroy_n(__first, __count);
+- }
+-
++ {
++ auto __res = std::__uninitialized_copy_n_pair
++ (_GLIBCXX_MAKE_MOVE_ITERATOR(__first),
++ __count, __result);
++ return {__res.first.base(), __res.second};
++ }
+ #endif
+
+-
+ _GLIBCXX_END_NAMESPACE_VERSION
+ } // namespace
+
Index: libstdc++-v3/include/bits/node_handle.h
===================================================================
--- a/src/libstdc++-v3/include/bits/node_handle.h (.../tags/gcc_7_1_0_release)
@@ -1127,6 +1883,266 @@ Index: libstdc++-v3/include/bits/stl_algo.h
}
#endif // C++17
#endif // C++14
+Index: libstdc++-v3/include/bits/shared_ptr_base.h
+===================================================================
+--- a/src/libstdc++-v3/include/bits/shared_ptr_base.h (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/include/bits/shared_ptr_base.h (.../branches/gcc-7-branch)
+@@ -411,6 +411,7 @@
+ struct _Sp_ebo_helper<_Nm, _Tp, true> : private _Tp
+ {
+ explicit _Sp_ebo_helper(const _Tp& __tp) : _Tp(__tp) { }
++ explicit _Sp_ebo_helper(_Tp&& __tp) : _Tp(std::move(__tp)) { }
+
+ static _Tp&
+ _S_get(_Sp_ebo_helper& __eboh) { return static_cast<_Tp&>(__eboh); }
+@@ -421,6 +422,7 @@
+ struct _Sp_ebo_helper<_Nm, _Tp, false>
+ {
+ explicit _Sp_ebo_helper(const _Tp& __tp) : _M_tp(__tp) { }
++ explicit _Sp_ebo_helper(_Tp&& __tp) : _M_tp(std::move(__tp)) { }
+
+ static _Tp&
+ _S_get(_Sp_ebo_helper& __eboh)
+@@ -441,7 +443,7 @@
+
+ public:
+ _Impl(_Ptr __p, _Deleter __d, const _Alloc& __a) noexcept
+- : _M_ptr(__p), _Del_base(__d), _Alloc_base(__a)
++ : _M_ptr(__p), _Del_base(std::move(__d)), _Alloc_base(__a)
+ { }
+
+ _Deleter& _M_del() noexcept { return _Del_base::_S_get(*this); }
+@@ -455,11 +457,11 @@
+
+ // __d(__p) must not throw.
+ _Sp_counted_deleter(_Ptr __p, _Deleter __d) noexcept
+- : _M_impl(__p, __d, _Alloc()) { }
++ : _M_impl(__p, std::move(__d), _Alloc()) { }
+
+ // __d(__p) must not throw.
+ _Sp_counted_deleter(_Ptr __p, _Deleter __d, const _Alloc& __a) noexcept
+- : _M_impl(__p, __d, __a) { }
++ : _M_impl(__p, std::move(__d), __a) { }
+
+ ~_Sp_counted_deleter() noexcept { }
+
+@@ -1083,7 +1085,7 @@
+
+ template<typename _Yp, typename _Deleter, typename = _SafeConv<_Yp>>
+ __shared_ptr(_Yp* __p, _Deleter __d)
+- : _M_ptr(__p), _M_refcount(__p, __d)
++ : _M_ptr(__p), _M_refcount(__p, std::move(__d))
+ {
+ static_assert(__is_invocable<_Deleter&, _Yp*&>::value,
+ "deleter expression d(p) is well-formed");
+@@ -1093,7 +1095,7 @@
+ template<typename _Yp, typename _Deleter, typename _Alloc,
+ typename = _SafeConv<_Yp>>
+ __shared_ptr(_Yp* __p, _Deleter __d, _Alloc __a)
+- : _M_ptr(__p), _M_refcount(__p, __d, std::move(__a))
++ : _M_ptr(__p), _M_refcount(__p, std::move(__d), std::move(__a))
+ {
+ static_assert(__is_invocable<_Deleter&, _Yp*&>::value,
+ "deleter expression d(p) is well-formed");
+@@ -1102,12 +1104,12 @@
+
+ template<typename _Deleter>
+ __shared_ptr(nullptr_t __p, _Deleter __d)
+- : _M_ptr(0), _M_refcount(__p, __d)
++ : _M_ptr(0), _M_refcount(__p, std::move(__d))
+ { }
+
+ template<typename _Deleter, typename _Alloc>
+ __shared_ptr(nullptr_t __p, _Deleter __d, _Alloc __a)
+- : _M_ptr(0), _M_refcount(__p, __d, std::move(__a))
++ : _M_ptr(0), _M_refcount(__p, std::move(__d), std::move(__a))
+ { }
+
+ template<typename _Yp>
+@@ -1244,12 +1246,12 @@
+ template<typename _Yp, typename _Deleter>
+ _SafeConv<_Yp>
+ reset(_Yp* __p, _Deleter __d)
+- { __shared_ptr(__p, __d).swap(*this); }
++ { __shared_ptr(__p, std::move(__d)).swap(*this); }
+
+ template<typename _Yp, typename _Deleter, typename _Alloc>
+ _SafeConv<_Yp>
+ reset(_Yp* __p, _Deleter __d, _Alloc __a)
+- { __shared_ptr(__p, __d, std::move(__a)).swap(*this); }
++ { __shared_ptr(__p, std::move(__d), std::move(__a)).swap(*this); }
+
+ element_type*
+ get() const noexcept
+@@ -1275,12 +1277,12 @@
+
+ template<typename _Tp1>
+ bool
+- owner_before(__shared_ptr<_Tp1, _Lp> const& __rhs) const
++ owner_before(__shared_ptr<_Tp1, _Lp> const& __rhs) const noexcept
+ { return _M_refcount._M_less(__rhs._M_refcount); }
+
+ template<typename _Tp1>
+ bool
+- owner_before(__weak_ptr<_Tp1, _Lp> const& __rhs) const
++ owner_before(__weak_ptr<_Tp1, _Lp> const& __rhs) const noexcept
+ { return _M_refcount._M_less(__rhs._M_refcount); }
+
+ #if __cpp_rtti
+@@ -1693,12 +1695,12 @@
+
+ template<typename _Tp1>
+ bool
+- owner_before(const __shared_ptr<_Tp1, _Lp>& __rhs) const
++ owner_before(const __shared_ptr<_Tp1, _Lp>& __rhs) const noexcept
+ { return _M_refcount._M_less(__rhs._M_refcount); }
+
+ template<typename _Tp1>
+ bool
+- owner_before(const __weak_ptr<_Tp1, _Lp>& __rhs) const
++ owner_before(const __weak_ptr<_Tp1, _Lp>& __rhs) const noexcept
+ { return _M_refcount._M_less(__rhs._M_refcount); }
+
+ void
+@@ -1743,15 +1745,15 @@
+ struct _Sp_owner_less : public binary_function<_Tp, _Tp, bool>
+ {
+ bool
+- operator()(const _Tp& __lhs, const _Tp& __rhs) const
++ operator()(const _Tp& __lhs, const _Tp& __rhs) const noexcept
+ { return __lhs.owner_before(__rhs); }
+
+ bool
+- operator()(const _Tp& __lhs, const _Tp1& __rhs) const
++ operator()(const _Tp& __lhs, const _Tp1& __rhs) const noexcept
+ { return __lhs.owner_before(__rhs); }
+
+ bool
+- operator()(const _Tp1& __lhs, const _Tp& __rhs) const
++ operator()(const _Tp1& __lhs, const _Tp& __rhs) const noexcept
+ { return __lhs.owner_before(__rhs); }
+ };
+
+@@ -1760,7 +1762,7 @@
+ {
+ template<typename _Tp, typename _Up>
+ auto
+- operator()(const _Tp& __lhs, const _Up& __rhs) const
++ operator()(const _Tp& __lhs, const _Up& __rhs) const noexcept
+ -> decltype(__lhs.owner_before(__rhs))
+ { return __lhs.owner_before(__rhs); }
+
+Index: libstdc++-v3/include/bits/std_function.h
+===================================================================
+--- a/src/libstdc++-v3/include/bits/std_function.h (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/include/bits/std_function.h (.../branches/gcc-7-branch)
+@@ -438,7 +438,7 @@
+ * The newly-created %function contains the target of @a __x
+ * (if it has one).
+ */
+- function(function&& __x) : _Function_base()
++ function(function&& __x) noexcept : _Function_base()
+ {
+ __x.swap(*this);
+ }
+@@ -495,7 +495,7 @@
+ * object, then this operation will not throw an %exception.
+ */
+ function&
+- operator=(function&& __x)
++ operator=(function&& __x) noexcept
+ {
+ function(std::move(__x)).swap(*this);
+ return *this;
+Index: libstdc++-v3/include/bits/stl_construct.h
+===================================================================
+--- a/src/libstdc++-v3/include/bits/stl_construct.h (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/include/bits/stl_construct.h (.../branches/gcc-7-branch)
+@@ -128,6 +128,11 @@
+ {
+ typedef typename iterator_traits<_ForwardIterator>::value_type
+ _Value_type;
++#if __cplusplus >= 201103L
++ // A deleted destructor is trivial, this ensures we reject such types:
++ static_assert(is_destructible<_Value_type>::value,
++ "value type is destructible");
++#endif
+ std::_Destroy_aux<__has_trivial_destructor(_Value_type)>::
+ __destroy(__first, __last);
+ }
+@@ -151,10 +156,10 @@
+ template<typename _ForwardIterator, typename _Size>
+ static _ForwardIterator
+ __destroy_n(_ForwardIterator __first, _Size __count)
+- {
+- std::advance(__first, __count);
+- return __first;
+- }
++ {
++ std::advance(__first, __count);
++ return __first;
++ }
+ };
+
+ /**
+@@ -168,6 +173,11 @@
+ {
+ typedef typename iterator_traits<_ForwardIterator>::value_type
+ _Value_type;
++#if __cplusplus >= 201103L
++ // A deleted destructor is trivial, this ensures we reject such types:
++ static_assert(is_destructible<_Value_type>::value,
++ "value type is destructible");
++#endif
+ return std::_Destroy_n_aux<__has_trivial_destructor(_Value_type)>::
+ __destroy_n(__first, __count);
+ }
+@@ -196,6 +206,29 @@
+ _Destroy(__first, __last);
+ }
+
++#if __cplusplus > 201402L
++ template <typename _Tp>
++ inline void
++ destroy_at(_Tp* __location)
++ {
++ std::_Destroy(__location);
++ }
++
++ template <typename _ForwardIterator>
++ inline void
++ destroy(_ForwardIterator __first, _ForwardIterator __last)
++ {
++ std::_Destroy(__first, __last);
++ }
++
++ template <typename _ForwardIterator, typename _Size>
++ inline _ForwardIterator
++ destroy_n(_ForwardIterator __first, _Size __count)
++ {
++ return std::_Destroy_n(__first, __count);
++ }
++#endif
++
+ _GLIBCXX_END_NAMESPACE_VERSION
+ } // namespace std
+
+Index: libstdc++-v3/include/bits/uses_allocator.h
+===================================================================
+--- a/src/libstdc++-v3/include/bits/uses_allocator.h (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/include/bits/uses_allocator.h (.../branches/gcc-7-branch)
+@@ -109,6 +109,11 @@
+ __ret._M_a = std::__addressof(__a);
+ return __ret;
+ }
++
++ template<typename _Tp, typename _Alloc, typename... _Args>
++ void
++ __use_alloc(const _Alloc&&) = delete;
++
+ #if __cplusplus > 201402L
+ template <typename _Tp, typename _Alloc>
+ inline constexpr bool uses_allocator_v =
Index: libstdc++-v3/include/bits/stl_tree.h
===================================================================
--- a/src/libstdc++-v3/include/bits/stl_tree.h (.../tags/gcc_7_1_0_release)
@@ -1142,11 +2158,204 @@ Index: libstdc++-v3/include/bits/stl_tree.h
#endif
pair<_Base_ptr, _Base_ptr>
+Index: libstdc++-v3/include/Makefile.am
+===================================================================
+--- a/src/libstdc++-v3/include/Makefile.am (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/include/Makefile.am (.../branches/gcc-7-branch)
+@@ -679,6 +679,7 @@
+ ${experimental_srcdir}/ratio \
+ ${experimental_srcdir}/regex \
+ ${experimental_srcdir}/set \
++ ${experimental_srcdir}/source_location \
+ ${experimental_srcdir}/string \
+ ${experimental_srcdir}/string_view \
+ ${experimental_srcdir}/system_error \
+Index: libstdc++-v3/libsupc++/eh_alloc.cc
+===================================================================
+--- a/src/libstdc++-v3/libsupc++/eh_alloc.cc (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/libsupc++/eh_alloc.cc (.../branches/gcc-7-branch)
+@@ -194,13 +194,17 @@
+ allocated_entry *e = reinterpret_cast <allocated_entry *>
+ (reinterpret_cast <char *> (data) - offsetof (allocated_entry, data));
+ std::size_t sz = e->size;
+- if (!first_free_entry)
++ if (!first_free_entry
++ || (reinterpret_cast <char *> (e) + sz
++ < reinterpret_cast <char *> (first_free_entry)))
+ {
+- // If the free list is empty just put the entry there.
++ // If the free list is empty or the entry is before the
++ // first element and cannot be merged with it add it as
++ // the first free entry.
+ free_entry *f = reinterpret_cast <free_entry *> (e);
+ new (f) free_entry;
+ f->size = sz;
+- f->next = NULL;
++ f->next = first_free_entry;
+ first_free_entry = f;
+ }
+ else if (reinterpret_cast <char *> (e) + sz
+@@ -224,9 +228,17 @@
+ > reinterpret_cast <char *> (e) + sz);
+ fe = &(*fe)->next)
+ ;
++ // If we can merge the next block into us do so and continue
++ // with the cases below.
++ if (reinterpret_cast <char *> (e) + sz
++ == reinterpret_cast <char *> ((*fe)->next))
++ {
++ sz += (*fe)->next->size;
++ (*fe)->next = (*fe)->next->next;
++ }
+ if (reinterpret_cast <char *> (*fe) + (*fe)->size
+ == reinterpret_cast <char *> (e))
+- /* Merge with the freelist entry. */
++ // Merge with the freelist entry.
+ (*fe)->size += sz;
+ else
+ {
Index: libstdc++-v3/ChangeLog
===================================================================
--- a/src/libstdc++-v3/ChangeLog (.../tags/gcc_7_1_0_release)
+++ b/src/libstdc++-v3/ChangeLog (.../branches/gcc-7-branch)
-@@ -1,3 +1,160 @@
+@@ -1,3 +1,297 @@
++2017-07-26 Richard Biener <rguenther at suse.de>
++
++ Backport from mainline
++ 2017-06-02 Richard Biener <rguenther at suse.de>
++ Markus Eisenmann <meisenmann.lba at fh-salzburg.ac.at>
++
++ PR libstdc++/80721
++ * libsupc++/eh_alloc.cc (pool::free): Keep list properly
++ sorted and add missing freelist item merging cases.
++
++2017-07-25 Jonathan Wakely <jwakely at redhat.com>
++
++ Backport from mainline
++ 2017-06-09 Jonathan Wakely <jwakely at redhat.com>
++
++ * doc/xml/manual/intro.xml: Document LWG 2802, 2873 and 2942 changes.
++ * include/bits/shared_ptr.h (shared_ptr): Use rvalues for deleters
++ (LWG 2802).
++ * include/bits/shared_ptr_base.h (_Sp_ebo_helper, _Sp_counted_deleter
++ (_Sp_counted_deleter::_Impl, __shared_count, __shared_ptr): Likewise.
++ * testsuite/20_util/shared_ptr/cons/lwg2802.cc: New.
++
++ Backport from mainline
++ 2017-06-05 Jonathan Wakely <jwakely at redhat.com>
++
++ * include/bits/shared_ptr_base.h (__shared_ptr::owner_before)
++ (__weak_ptr::owner_before, _Sp_owner_less::operator()): Add noexcept
++ specifiers as per LWG 2873 and LWG 2942.
++ * testsuite/20_util/owner_less/noexcept.cc: New.
++ * testsuite/20_util/shared_ptr/observers/owner_before.cc: Test
++ noexcept guarantees.
++ * testsuite/20_util/weak_ptr/observers/owner_before.cc: Likewise.
++
++ Backport from mainline
++ 2017-04-28 Jonathan Wakely <jwakely at redhat.com>
++
++ PR libstdc++/80553
++ * include/bits/stl_construct.h (_Destroy, _Destroy_n): Add static
++ assertions to ensure type is destructible.
++ (destroy_at, destroy, destroy_n): Move from stl_uninitialized.h.
++ * include/bits/stl_uninitialized.h (destroy_at, destroy, destroy_n):
++ Move to stl_construct.h.
++ * testsuite/20_util/specialized_algorithms/memory_management_tools/
++ destroy_neg.cc: New test.
++ * testsuite/23_containers/vector/cons/destructible_neg.cc: New test.
++
++ Backport from mainline
++ 2017-05-16 Jonathan Wakely <jwakely at redhat.com>
++
++ * configure: Regenerate.
++ * doc/xml/manual/status_cxx2017.xml: Update status table.
++ * doc/html/*: Regenerate.
++ * include/Makefile.am: Add new header.
++ * include/Makefile.in: Regenerate.
++ * include/experimental/source_location: New header implementing N4519.
++ * testsuite/experimental/source_location/1.cc: New test.
++
++ Backport from mainline
++ 2017-07-06 Jonathan Wakely <jwakely at redhat.com>
++
++ * include/bits/uses_allocator.h (__use_alloc(const _Alloc&&)): Add
++ deleted overload to prevent dangling references to rvalues.
++ * include/experimental/memory_resource
++ (polymorphic_allocator::construct): Do not call __use_alloc with
++ rvalue arguments.
++
++ Backport from mainline
++ 2017-06-08 Jonathan Wakely <jwakely at redhat.com>
++
++ PR libstdc++/81017
++ * include/bits/std_function.h (function::function(function&&))
++ (function::operator=(funtion&&)): Add noexcept.
++ * testsuite/20_util/function/assign/move.cc: Check for noexcept.
++ * testsuite/20_util/function/cons/move.cc: Likewise.
++
++ Backport from mainline
++ 2017-07-15 Jonathan Wakely <jwakely at redhat.com>
++
++ * include/std/mutex (scoped_lock): Reorder std::adopt_lock_t parameter
++ as per P0739R0.
++ * testsuite/30_threads/scoped_lock/cons/1.cc: Reorder arguments.
++ * testsuite/30_threads/scoped_lock/cons/deduction.cc: Test deduction
++ with std::adopt_lock_t.
++ * testsuite/30_threads/scoped_lock/requirements/typedefs.cc: Check
++ feature-test macro.
++
++ Backport from mainline
++ 2017-07-14 Jason Merrill <jason at redhat.com>
++ Jonathan Wakely <jwakely at redhat.com>
++
++ * include/std/variant (variant::variant(_Tp&&)): Constrain to remove
++ the constructor for empty variants from the candidate functions
++ during class template argument deduction.
++ * testsuite/20_util/variant/deduction.cc: New.
++
++ Backport from mainline
++ 2017-06-02 Jonathan Wakely <jwakely at redhat.com>
++
++ PR libstdc++/80939
++ * include/std/variant (__erased_ctor, __erased_assign, __erased_swap)
++ (__erased_hash): Remove constexpr specifier and qualify calls to
++ __ref_cast.
++ (__erased_dtor): Remove constexpr specifier and use _Destroy.
++
++ Backport from mainline
++ 2017-05-20 Tim Shen <timshen at google.com>
++
++ PR libstdc++/80737
++ * include/std/variant(variant::variant): SFINAE on is_same first.
++ * testsuite/20_util/variant/any.cc: test case.
++
++2017-07-11 Jonathan Wakely <jwakely at redhat.com>
++
++ Backport from mainline
++ 2017-04-21 Jonathan Wakely <jwakely at redhat.com>
++
++ PR libstdc++/80316
++ * include/std/future (_State_baseV2::_Setter::operator()): Remove
++ _S_check calls that are done after the pointer to the shared state is
++ already dereferenced.
++ (_State_baseV2::_Setter<_Res, void>): Define specialization for void
++ as partial specialization so it can be defined within the definition
++ of _State_baseV2.
++ (_State_baseV2::__setter): Call _S_check.
++ (_State_baseV2::__setter(promise<void>*)): Add overload for use by
++ promise<void>::set_value and promise<void>::set_value_at_thread_exit.
++ (promise<T>, promise<T&>, promise<void>): Make _State a friend.
++ (_State_baseV2::_Setter<void, void>): Remove explicit specialization.
++ (promise<void>::set_value, promise<void>::set_value_at_thread_exit):
++ Use new __setter overload.
++ * testsuite/30_threads/promise/members/at_thread_exit2.cc: New test.
++ * testsuite/30_threads/promise/members/set_exception.cc: Test
++ promise<T&> and promise<void> specializations.
++ * testsuite/30_threads/promise/members/set_exception2.cc: Likewise.
++ Test for no_state error condition.
++ * testsuite/30_threads/promise/members/set_value2.cc: Likewise.
++
+2017-06-27 Jonathan Wakely <jwakely at redhat.com>
+
+ PR libstdc++/81221
@@ -1421,6 +2630,842 @@ Index: libstdc++-v3/testsuite/28_regex/basic_regex/ctors/basic/iter.cc
+ std::regex r1(c.begin(), c.end());
+ std::regex r2(c.begin(), c.end(), std::regex_constants::grep);
+}
+Index: libstdc++-v3/testsuite/30_threads/scoped_lock/cons/deduction.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/scoped_lock/cons/deduction.cc (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/testsuite/30_threads/scoped_lock/cons/deduction.cc (.../branches/gcc-7-branch)
+@@ -51,3 +51,28 @@
+ std::scoped_lock l2(m2, m3);
+ check_type<std::scoped_lock<Lockable, std::mutex>>(l2);
+ }
++
++void
++test02()
++{
++ std::scoped_lock l0(std::adopt_lock);
++ check_type<std::scoped_lock<>>(l0);
++
++ struct BasicLockable {
++ void lock() { }
++ void unlock() { }
++ } m1;
++
++ std::scoped_lock l1(std::adopt_lock, m1);
++ check_type<std::scoped_lock<BasicLockable>>(l1);
++
++ struct Lockable {
++ void lock() { }
++ void unlock() { }
++ bool try_lock() { return true; }
++ } m2;
++
++ std::mutex m3;
++ std::scoped_lock l2(std::adopt_lock, m2, m3);
++ check_type<std::scoped_lock<Lockable, std::mutex>>(l2);
++}
+Index: libstdc++-v3/testsuite/30_threads/scoped_lock/cons/1.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/scoped_lock/cons/1.cc (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/testsuite/30_threads/scoped_lock/cons/1.cc (.../branches/gcc-7-branch)
+@@ -79,7 +79,7 @@
+
+ try
+ {
+- std::scoped_lock<BasicLockable> l(m, std::adopt_lock);
++ std::scoped_lock<BasicLockable> l(std::adopt_lock, m);
+ }
+ catch (...)
+ {
+@@ -113,7 +113,7 @@
+
+ try
+ {
+- std::scoped_lock<Lockable<1>, Lockable<2>> l(m1, m2, std::adopt_lock);
++ std::scoped_lock<Lockable<1>, Lockable<2>> l(std::adopt_lock, m1, m2);
+ VERIFY( m1.m.locked );
+ VERIFY( m2.m.locked );
+ }
+Index: libstdc++-v3/testsuite/30_threads/scoped_lock/requirements/typedefs.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/scoped_lock/requirements/typedefs.cc (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/testsuite/30_threads/scoped_lock/requirements/typedefs.cc (.../branches/gcc-7-branch)
+@@ -25,6 +25,12 @@
+
+ #include <mutex>
+
++#ifndef __cpp_lib_scoped_lock
++# error "Feature-test macro for scoped_lock missing"
++#elif __cpp_lib_scoped_lock != 201707
++# error "Feature-test macro for scoped_lock has wrong value"
++#endif
++
+ void test01()
+ {
+ // Check for required typedefs
+Index: libstdc++-v3/testsuite/30_threads/promise/members/set_exception2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/set_exception2.cc (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_exception2.cc (.../branches/gcc-7-branch)
+@@ -21,10 +21,13 @@
+ // with this library; see the file COPYING3. If not see
+ // <http://www.gnu.org/licenses/>.
+
++// Test that promise::set_exception throws when required.
+
+ #include <future>
+ #include <testsuite_hooks.h>
+
++// Check for promise_already_satisfied error conditions.
++
+ void test01()
+ {
+ bool test = false;
+@@ -83,9 +86,187 @@
+ VERIFY( test );
+ }
+
++void test03()
++{
++ bool test = false;
++
++ std::promise<int&> p1;
++ std::future<int&> f1 = p1.get_future();
++
++ p1.set_exception(std::make_exception_ptr(0));
++
++ try
++ {
++ p1.set_exception(std::make_exception_ptr(1));
++ VERIFY( false );
++ }
++ catch (std::future_error& e)
++ {
++ VERIFY(e.code() ==
++ std::make_error_code(std::future_errc::promise_already_satisfied));
++ test = true;
++ }
++
++ try
++ {
++ f1.get();
++ test = false;
++ }
++ catch(int i)
++ {
++ VERIFY( i == 0 );
++ }
++
++ VERIFY( test );
++}
++
++void test04()
++{
++ bool test = false;
++
++ std::promise<int&> p1;
++ std::future<int&> f1 = p1.get_future();
++
++ int i = 2;
++ p1.set_value(i);
++
++ try
++ {
++ p1.set_exception(std::make_exception_ptr(0));
++ VERIFY( false );
++ }
++ catch (std::future_error& e)
++ {
++ VERIFY(e.code() ==
++ std::make_error_code(std::future_errc::promise_already_satisfied));
++ test = true;
++ }
++
++ VERIFY( test );
++}
++
++void test05()
++{
++ bool test = false;
++
++ std::promise<void> p1;
++ std::future<void> f1 = p1.get_future();
++
++ p1.set_exception(std::make_exception_ptr(0));
++
++ try
++ {
++ p1.set_exception(std::make_exception_ptr(1));
++ VERIFY( false );
++ }
++ catch (std::future_error& e)
++ {
++ VERIFY(e.code() ==
++ std::make_error_code(std::future_errc::promise_already_satisfied));
++ test = true;
++ }
++
++ try
++ {
++ f1.get();
++ test = false;
++ }
++ catch(int i)
++ {
++ VERIFY( i == 0 );
++ }
++
++ VERIFY( test );
++}
++
++void test06()
++{
++ bool test = false;
++
++ std::promise<void> p1;
++ std::future<void> f1 = p1.get_future();
++
++ p1.set_value();
++
++ try
++ {
++ p1.set_exception(std::make_exception_ptr(0));
++ VERIFY( false );
++ }
++ catch (std::future_error& e)
++ {
++ VERIFY(e.code() ==
++ std::make_error_code(std::future_errc::promise_already_satisfied));
++ test = true;
++ }
++
++ VERIFY( test );
++}
++
++// Check for no_state error condition (PR libstdc++/80316)
++
++void test07()
++{
++ using namespace std;
++
++ promise<int> p1;
++ promise<int> p2(std::move(p1));
++ try
++ {
++ p1.set_exception(std::make_exception_ptr(1));
++ VERIFY( false );
++ }
++ catch (std::future_error& e)
++ {
++ VERIFY(e.code() == make_error_code(future_errc::no_state));
++ }
++}
++
++void test08()
++{
++ using namespace std;
++
++ promise<int&> p1;
++ promise<int&> p2(std::move(p1));
++ try
++ {
++ int i = 0;
++ p1.set_exception(std::make_exception_ptr(1));
++ VERIFY( false );
++ }
++ catch (std::future_error& e)
++ {
++ VERIFY(e.code() == make_error_code(future_errc::no_state));
++ }
++}
++
++void test09()
++{
++ using namespace std;
++
++ promise<void> p1;
++ promise<void> p2(std::move(p1));
++ try
++ {
++ p1.set_exception(std::make_exception_ptr(1));
++ VERIFY( false );
++ }
++ catch (std::future_error& e)
++ {
++ VERIFY(e.code() == make_error_code(future_errc::no_state));
++ }
++}
++
+ int main()
+ {
+ test01();
+ test02();
++ test03();
++ test04();
++ test05();
++ test06();
++ test07();
++ test08();
++ test09();
+ return 0;
+ }
+Index: libstdc++-v3/testsuite/30_threads/promise/members/at_thread_exit2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/at_thread_exit2.cc (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/at_thread_exit2.cc (.../branches/gcc-7-branch)
+@@ -0,0 +1,167 @@
++// { dg-do run { target *-*-freebsd* *-*-dragonfly* *-*-netbsd* *-*-linux* *-*-gnu* *-*-solaris* *-*-cygwin *-*-rtems* *-*-darwin* powerpc-ibm-aix* } }
++// { dg-options "-pthread" { target *-*-freebsd* *-*-dragonfly* *-*-netbsd* *-*-linux* *-*-gnu* *-*-solaris* powerpc-ibm-aix* } }
++// { dg-require-effective-target c++11 }
++// { dg-require-cstdint "" }
++// { dg-require-gthreads "" }
++
++// Copyright (C) 2014-2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library. This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3. If not see
++// <http://www.gnu.org/licenses/>.
++
++// Test set_value_at_thread_exit error conditions
++
++#include <future>
++#include <testsuite_hooks.h>
++
++void test01()
++{
++ std::promise<int> p1;
++ p1.set_value(1);
++ try
++ {
++ p1.set_value_at_thread_exit(2);
++ VERIFY( false );
++ }
++ catch (std::future_error& e)
++ {
++ VERIFY( e.code() == std::future_errc::promise_already_satisfied );
++ }
++ try
++ {
++ p1.set_exception_at_thread_exit(std::make_exception_ptr(3));
++ VERIFY( false );
++ }
++ catch (std::future_error& e)
++ {
++ VERIFY( e.code() == std::future_errc::promise_already_satisfied );
++ }
++
++ std::promise<int> p2(std::move(p1));
++ try
++ {
++ p1.set_value_at_thread_exit(2);
++ VERIFY( false );
++ }
++ catch (std::future_error& e)
++ {
++ VERIFY( e.code() == std::future_errc::no_state );
++ }
++ try
++ {
++ p1.set_exception_at_thread_exit(std::make_exception_ptr(3));
++ VERIFY( false );
++ }
++ catch (std::future_error& e)
++ {
++ VERIFY( e.code() == std::future_errc::no_state );
++ }
++}
++
++void test02()
++{
++ std::promise<int&> p1;
++ int i = 1;
++ p1.set_value(i);
++ try
++ {
++ p1.set_value_at_thread_exit(i);
++ VERIFY( false );
++ }
++ catch (std::future_error& e)
++ {
++ VERIFY( e.code() == std::future_errc::promise_already_satisfied );
++ }
++ try
++ {
++ p1.set_exception_at_thread_exit(std::make_exception_ptr(3));
++ VERIFY( false );
++ }
++ catch (std::future_error& e)
++ {
++ VERIFY( e.code() == std::future_errc::promise_already_satisfied );
++ }
++
++ std::promise<int&> p2(std::move(p1));
++ try
++ {
++ int i = 0;
++ p1.set_value_at_thread_exit(i);
++ VERIFY( false );
++ }
++ catch (std::future_error& e)
++ {
++ VERIFY( e.code() == std::future_errc::no_state );
++ }
++ try
++ {
++ p1.set_exception_at_thread_exit(std::make_exception_ptr(3));
++ VERIFY( false );
++ }
++ catch (std::future_error& e)
++ {
++ VERIFY( e.code() == std::future_errc::no_state );
++ }
++}
++
++void test03()
++{
++ std::promise<void> p1;
++ int i = 0;
++ p1.set_value();
++ try {
++ p1.set_value_at_thread_exit();
++ VERIFY( false );
++ }
++ catch (std::future_error& e)
++ {
++ VERIFY( e.code() == std::future_errc::promise_already_satisfied );
++ }
++ try
++ {
++ p1.set_exception_at_thread_exit(std::make_exception_ptr(3));
++ VERIFY( false );
++ }
++ catch (std::future_error& e)
++ {
++ VERIFY( e.code() == std::future_errc::promise_already_satisfied );
++ }
++
++ std::promise<void> p2(std::move(p1));
++ try {
++ p1.set_value_at_thread_exit();
++ VERIFY( false );
++ }
++ catch (std::future_error& e)
++ {
++ VERIFY( e.code() == std::future_errc::no_state );
++ }
++ try
++ {
++ p1.set_exception_at_thread_exit(std::make_exception_ptr(3));
++ VERIFY( false );
++ }
++ catch (std::future_error& e)
++ {
++ VERIFY( e.code() == std::future_errc::no_state );
++ }
++}
++
++int main()
++{
++ test01();
++ test02();
++ test03();
++}
+Index: libstdc++-v3/testsuite/30_threads/promise/members/set_exception.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/set_exception.cc (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_exception.cc (.../branches/gcc-7-branch)
+@@ -21,6 +21,7 @@
+ // with this library; see the file COPYING3. If not see
+ // <http://www.gnu.org/licenses/>.
+
++// Test that promise::set_exception stores an exception.
+
+ #include <future>
+ #include <testsuite_hooks.h>
+@@ -48,8 +49,56 @@
+ VERIFY( !f1.valid() );
+ }
+
++void test02()
++{
++ bool test = false;
++
++ std::promise<int&> p1;
++ std::future<int&> f1 = p1.get_future();
++
++ VERIFY( f1.valid() );
++
++ p1.set_exception(std::make_exception_ptr(0));
++
++ try
++ {
++ f1.get();
++ }
++ catch (int)
++ {
++ test = true;
++ }
++ VERIFY( test );
++ VERIFY( !f1.valid() );
++}
++
++void test03()
++{
++ bool test = false;
++
++ std::promise<void> p1;
++ std::future<void> f1 = p1.get_future();
++
++ VERIFY( f1.valid() );
++
++ p1.set_exception(std::make_exception_ptr(0));
++
++ try
++ {
++ f1.get();
++ }
++ catch (int)
++ {
++ test = true;
++ }
++ VERIFY( test );
++ VERIFY( !f1.valid() );
++}
++
+ int main()
+ {
+ test01();
++ test02();
++ test03();
+ return 0;
+ }
+Index: libstdc++-v3/testsuite/30_threads/promise/members/set_value2.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/promise/members/set_value2.cc (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/testsuite/30_threads/promise/members/set_value2.cc (.../branches/gcc-7-branch)
+@@ -21,10 +21,13 @@
+ // with this library; see the file COPYING3. If not see
+ // <http://www.gnu.org/licenses/>.
+
++// Test that promise::set_value throws when required.
+
+ #include <future>
+ #include <testsuite_hooks.h>
+
++// Check for promise_already_satisfied error conditions.
++
+ void test01()
+ {
+ bool test = false;
+@@ -79,9 +82,298 @@
+ VERIFY( test );
+ }
+
++void test03()
++{
++ bool test = false;
++
++ std::promise<int> p1;
++ std::future<int> f1 = p1.get_future();
++
++ p1.set_exception(std::make_exception_ptr(4));
++
++ try
++ {
++ p1.set_value(3);
++ VERIFY( false );
++ }
++ catch (std::future_error& e)
++ {
++ VERIFY(e.code() ==
++ std::make_error_code(std::future_errc::promise_already_satisfied));
++ test = true;
++ }
++
++ std::chrono::milliseconds delay(1);
++ VERIFY( f1.wait_for(delay) == std::future_status::ready );
++ test = false;
++ try
++ {
++ f1.get();
++ VERIFY( false );
++ }
++ catch (int e)
++ {
++ VERIFY(e == 4 );
++ test = true;
++ }
++
++ VERIFY( test );
++}
++
++void test04()
++{
++ bool test = false;
++
++ std::promise<int&> p1;
++ std::future<int&> f1 = p1.get_future();
++
++ int i = 1;
++ p1.set_value(i);
++
++ try
++ {
++ p1.set_value(i);
++ VERIFY( false );
++ }
++ catch (std::future_error& e)
++ {
++ VERIFY(e.code() ==
++ std::make_error_code(std::future_errc::promise_already_satisfied));
++ test = true;
++ }
++
++ std::chrono::milliseconds delay(1);
++ VERIFY( f1.wait_for(delay) == std::future_status::ready );
++ VERIFY( f1.get() == 1 );
++ VERIFY( test );
++}
++
++void test05()
++{
++ bool test = false;
++
++ std::promise<int&> p1;
++ std::future<int&> f1 = p1.get_future();
++
++ int i = 3;
++ p1.set_value(i);
++
++ try
++ {
++ p1.set_exception(std::make_exception_ptr(4));
++ VERIFY( false );
++ }
++ catch (std::future_error& e)
++ {
++ VERIFY(e.code() ==
++ std::make_error_code(std::future_errc::promise_already_satisfied));
++ test = true;
++ }
++
++ std::chrono::milliseconds delay(1);
++ VERIFY( f1.wait_for(delay) == std::future_status::ready );
++ VERIFY( f1.get() == 3 );
++ VERIFY( test );
++}
++
++void test06()
++{
++ bool test = false;
++
++ std::promise<int&> p1;
++ std::future<int&> f1 = p1.get_future();
++
++ p1.set_exception(std::make_exception_ptr(4));
++
++ try
++ {
++ int i = 3;
++ p1.set_value(i);
++ VERIFY( false );
++ }
++ catch (std::future_error& e)
++ {
++ VERIFY(e.code() ==
++ std::make_error_code(std::future_errc::promise_already_satisfied));
++ test = true;
++ }
++
++ std::chrono::milliseconds delay(1);
++ VERIFY( f1.wait_for(delay) == std::future_status::ready );
++ test = false;
++ try
++ {
++ f1.get();
++ VERIFY( false );
++ }
++ catch (int e)
++ {
++ VERIFY(e == 4 );
++ test = true;
++ }
++
++ VERIFY( test );
++}
++
++void test07()
++{
++ bool test = false;
++
++ std::promise<void> p1;
++ std::future<void> f1 = p1.get_future();
++
++ p1.set_value();
++
++ try
++ {
++ p1.set_value();
++ VERIFY( false );
++ }
++ catch (std::future_error& e)
++ {
++ VERIFY(e.code() ==
++ std::make_error_code(std::future_errc::promise_already_satisfied));
++ test = true;
++ }
++
++ std::chrono::milliseconds delay(1);
++ VERIFY( f1.wait_for(delay) == std::future_status::ready );
++ f1.get();
++ VERIFY( test );
++}
++
++void test08()
++{
++ bool test = false;
++
++ std::promise<void> p1;
++ std::future<void> f1 = p1.get_future();
++
++ p1.set_value();
++
++ try
++ {
++ p1.set_exception(std::make_exception_ptr(4));
++ VERIFY( false );
++ }
++ catch (std::future_error& e)
++ {
++ VERIFY(e.code() ==
++ std::make_error_code(std::future_errc::promise_already_satisfied));
++ test = true;
++ }
++
++ std::chrono::milliseconds delay(1);
++ VERIFY( f1.wait_for(delay) == std::future_status::ready );
++ f1.get();
++ VERIFY( test );
++}
++
++void test09()
++{
++ bool test = false;
++
++ std::promise<void> p1;
++ std::future<void> f1 = p1.get_future();
++
++ p1.set_exception(std::make_exception_ptr(4));
++
++ try
++ {
++ p1.set_value();
++ VERIFY( false );
++ }
++ catch (std::future_error& e)
++ {
++ VERIFY(e.code() ==
++ std::make_error_code(std::future_errc::promise_already_satisfied));
++ test = true;
++ }
++
++ std::chrono::milliseconds delay(1);
++ VERIFY( f1.wait_for(delay) == std::future_status::ready );
++ test = false;
++ try
++ {
++ f1.get();
++ VERIFY( false );
++ }
++ catch (int e)
++ {
++ VERIFY(e == 4 );
++ test = true;
++ }
++
++ VERIFY( test );
++}
++
++// Check for no_state error condition (PR libstdc++/80316)
++
++void test10()
++{
++ using namespace std;
++
++ promise<int> p1;
++ promise<int> p2(std::move(p1));
++ try
++ {
++ p1.set_value(1);
++ VERIFY( false );
++ }
++ catch (std::future_error& e)
++ {
++ VERIFY(e.code() == make_error_code(future_errc::no_state));
++ }
++}
++
++void test11()
++{
++ using namespace std;
++
++ promise<int&> p1;
++ promise<int&> p2(std::move(p1));
++ try
++ {
++ int i = 0;
++ p1.set_value(i);
++ VERIFY( false );
++ }
++ catch (std::future_error& e)
++ {
++ VERIFY(e.code() == make_error_code(future_errc::no_state));
++ }
++}
++
++void test12()
++{
++ using namespace std;
++
++ promise<void> p1;
++ promise<void> p2(std::move(p1));
++ try
++ {
++ p1.set_value();
++ VERIFY( false );
++ }
++ catch (std::future_error& e)
++ {
++ VERIFY(e.code() == make_error_code(future_errc::no_state));
++ }
++}
++
+ int main()
+ {
+ test01();
+ test02();
++ test03();
++ test04();
++ test05();
++ test06();
++ test07();
++ test08();
++ test09();
++ test10();
++ test11();
++ test12();
+ return 0;
+ }
Index: libstdc++-v3/testsuite/22_locale/conversions/buffer/2.cc
===================================================================
--- a/src/libstdc++-v3/testsuite/22_locale/conversions/buffer/2.cc (.../tags/gcc_7_1_0_release)
@@ -1526,6 +3571,55 @@ Index: libstdc++-v3/testsuite/23_containers/set/modifiers/extract.cc
int
main()
{
+Index: libstdc++-v3/testsuite/23_containers/vector/cons/destructible_neg.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/23_containers/vector/cons/destructible_neg.cc (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/testsuite/23_containers/vector/cons/destructible_neg.cc (.../branches/gcc-7-branch)
+@@ -0,0 +1,44 @@
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library. This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3. If not see
++// <http://www.gnu.org/licenses/>.
++
++// { dg-do compile { target c++11 } }
++
++#include <vector>
++
++// PR libstdc++/80553
++
++struct DeletedDtor {
++ ~DeletedDtor() = delete;
++};
++
++class PrivateDtor {
++ ~PrivateDtor() { }
++};
++
++void
++test01()
++{
++ std::vector<DeletedDtor> v; // { dg-error "here" }
++}
++
++void
++test02()
++{
++ std::vector<PrivateDtor> v; // { dg-error "here" }
++}
++
++// { dg-error "value type is destructible" "" { target *-*-* } 0 }
Index: libstdc++-v3/testsuite/23_containers/unordered_set/modifiers/extract.cc
===================================================================
--- a/src/libstdc++-v3/testsuite/23_containers/unordered_set/modifiers/extract.cc (.../tags/gcc_7_1_0_release)
@@ -1770,6 +3864,128 @@ Index: libstdc++-v3/testsuite/21_strings/basic_string/cons/char/8.cc
}
void
+Index: libstdc++-v3/testsuite/experimental/source_location/1.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/experimental/source_location/1.cc (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/testsuite/experimental/source_location/1.cc (.../branches/gcc-7-branch)
+@@ -0,0 +1,117 @@
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library. This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3. If not see
++// <http://www.gnu.org/licenses/>.
++
++// { dg-do run { target c++14 } }
++
++#include <experimental/source_location>
++#include <experimental/string_view>
++#include <testsuite_hooks.h>
++
++using std::experimental::source_location;
++using std::experimental::string_view;
++
++void
++test01()
++{
++ constexpr source_location loc = source_location::current();
++ static_assert( loc.line() == 30 );
++ // static_assert( loc.column() == 35 );
++ VERIFY( loc.file_name() == __FILE__ );
++ VERIFY( loc.function_name() == string_view(__FUNCTION__) );
++}
++
++struct S {
++ string_view func;
++ source_location loc = source_location::current();
++
++ S(source_location loc = source_location::current())
++ : func(__FUNCTION__), loc(loc) // values of loc will be from call-site
++ {}
++
++ S(int)
++ : func(__FUNCTION__) // values of loc should be hereabouts
++ {}
++};
++
++void test02()
++{
++ S s0;
++ VERIFY( s0.loc.line() == 52 );
++ // static_assert( s0.loc.column() == 7 );
++ VERIFY( s0.loc.file_name() == __FILE__ );
++ VERIFY( s0.loc.function_name() == string_view(__FUNCTION__) );
++
++ S s1(1);
++ VERIFY( s1.loc.line() == 46 );
++ VERIFY( s1.loc.file_name() == __FILE__ );
++ VERIFY( s1.loc.function_name() == s1.func );
++}
++
++source_location f(source_location a = source_location::current()) {
++ return a;
++}
++
++source_location g(string_view& func) {
++ source_location a = source_location::current();
++ func = __FUNCTION__;
++ return a;
++}
++
++void test03()
++{
++ auto loc = f(); // f's first argument corresponds to this line of code
++ VERIFY( loc.line() == 76 );
++ // static_assert( loc.column() == 16 );
++ VERIFY( loc.file_name() == __FILE__ );
++ VERIFY( loc.function_name() == string_view(__FUNCTION__) );
++
++ source_location c = source_location::current();
++ loc = f(c); // f's first argument gets the same values as c, above
++ VERIFY( loc.line() == 82 );
++ // static_assert( loc.column() == 23 );
++ VERIFY( loc.file_name() == __FILE__ );
++ VERIFY( loc.function_name() == string_view(__FUNCTION__) );
++
++ string_view func;
++ loc = g(func);
++ VERIFY( loc.line() == 69 );
++ // static_assert( loc.column() == 23 );
++ VERIFY( loc.file_name() == __FILE__ );
++ VERIFY( loc.function_name() == func );
++}
++
++void
++test04()
++{
++ using std::is_same;
++ using std::uint_least32_t;
++ auto loc = source_location::current();
++ static_assert(is_same<decltype(loc), source_location>::value, "");
++ static_assert(is_same<decltype(loc.line()), uint_least32_t>::value, "");
++ static_assert(is_same<decltype(loc.column()), uint_least32_t>::value, "");
++ static_assert(is_same<decltype(loc.file_name()), const char*>::value, "");
++ static_assert(is_same<decltype(loc.function_name()), const char*>::value, "");
++}
++
++int
++main()
++{
++ test01();
++ test02();
++ test03();
++ test04();
++}
Index: libstdc++-v3/testsuite/util/testsuite_abi.cc
===================================================================
--- a/src/libstdc++-v3/testsuite/util/testsuite_abi.cc (.../tags/gcc_7_1_0_release)
@@ -1791,11 +4007,11 @@ Index: libstdc++-v3/testsuite/util/testsuite_abi.cc
|| test.version_name == "CXXABI_1.3.11"
|| test.version_name == "CXXABI_FLOAT128"
|| test.version_name == "CXXABI_TM_1");
-Index: libstdc++-v3/testsuite/20_util/function_objects/mem_fn/80478.cc
+Index: libstdc++-v3/testsuite/20_util/owner_less/noexcept.cc
===================================================================
---- a/src/libstdc++-v3/testsuite/20_util/function_objects/mem_fn/80478.cc (.../tags/gcc_7_1_0_release)
-+++ b/src/libstdc++-v3/testsuite/20_util/function_objects/mem_fn/80478.cc (.../branches/gcc-7-branch)
-@@ -0,0 +1,27 @@
+--- a/src/libstdc++-v3/testsuite/20_util/owner_less/noexcept.cc (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/testsuite/20_util/owner_less/noexcept.cc (.../branches/gcc-7-branch)
+@@ -0,0 +1,40 @@
+// Copyright (C) 2017 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library. This library is free
@@ -1813,21 +4029,34 @@ Index: libstdc++-v3/testsuite/20_util/function_objects/mem_fn/80478.cc
+// with this library; see the file COPYING3. If not see
+// <http://www.gnu.org/licenses/>.
+
-+// { dg-options "-std=gnu++17" }
-+// { dg-do compile { target c++1z } }
-+
-+#include <functional>
-+
-+struct X {
-+ void f() noexcept { }
-+};
++// { dg-do compile { target c++11 } }
+
-+auto f = std::mem_fn(&X::f);
-Index: libstdc++-v3/testsuite/20_util/tuple/78939.cc
++#include <memory>
++
++const std::shared_ptr<int> si;
++const std::weak_ptr<int> wi;
++const std::owner_less<std::shared_ptr<int>> osi;
++static_assert( noexcept(osi(si, si)), "" );
++static_assert( noexcept(osi(si, wi)), "" );
++static_assert( noexcept(osi(wi, si)), "" );
++const std::owner_less<std::weak_ptr<int>> owi;
++static_assert( noexcept(owi(wi, wi)), "" );
++static_assert( noexcept(owi(si, wi)), "" );
++static_assert( noexcept(owi(wi, si)), "" );
++const std::shared_ptr<long> sl;
++const std::weak_ptr<char> wc;
++const std::owner_less<void> ov;
++static_assert( noexcept(ov(si, si)), "" );
++static_assert( noexcept(ov(si, sl)), "" );
++static_assert( noexcept(ov(sl, si)), "" );
++static_assert( noexcept(ov(si, wc)), "" );
++static_assert( noexcept(ov(wc, si)), "" );
++static_assert( noexcept(ov(wc, wi)), "" );
+Index: libstdc++-v3/testsuite/20_util/shared_ptr/cons/lwg2802.cc
===================================================================
---- a/src/libstdc++-v3/testsuite/20_util/tuple/78939.cc (.../tags/gcc_7_1_0_release)
-+++ b/src/libstdc++-v3/testsuite/20_util/tuple/78939.cc (.../branches/gcc-7-branch)
-@@ -0,0 +1,49 @@
+--- a/src/libstdc++-v3/testsuite/20_util/shared_ptr/cons/lwg2802.cc (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/testsuite/20_util/shared_ptr/cons/lwg2802.cc (.../branches/gcc-7-branch)
+@@ -0,0 +1,51 @@
+// Copyright (C) 2017 Free Software Foundation, Inc.
+//
+// This file is part of the GNU ISO C++ Library. This library is free
@@ -1845,45 +4074,362 @@ Index: libstdc++-v3/testsuite/20_util/tuple/78939.cc
+// with this library; see the file COPYING3. If not see
+// <http://www.gnu.org/licenses/>.
+
-+// { dg-options "-std=gnu++17" }
-+// { dg-do compile { target c++1z } }
-+
-+// PR libstdc++/78939
++// { dg-do compile { target c++11 } }
+
-+#include <utility>
++#include <memory>
+
-+struct A { int i, j; };
++// LWG 2802. shared_ptr constructor requirements for a deleter
+
-+int
-+test01()
++struct D
+{
-+ A a{};
-+ const auto [i, j] = a;
-+ return i + j;
-+}
++ D() { }
++ D(D&&) { }
++ void operator()(int* p) const { delete p; }
++};
+
-+int
-+test02()
++std::allocator<int> a;
++
++std::shared_ptr<int> s1((int*)nullptr, D());
++std::shared_ptr<int> s2((int*)nullptr, D(), a);
++std::shared_ptr<int> s3(nullptr, D());
++std::shared_ptr<int> s4(nullptr, D(), a);
++
++void test01()
+{
-+ A a{};
-+ volatile auto [i, j] = a;
-+ return i + j;
++ s1.reset((int*)nullptr, D());
++ s1.reset((int*)nullptr, D(), a);
+}
+
-+int
-+test03()
++struct D2 final
+{
-+ A a{};
-+ const volatile auto [i, j] = a;
-+ return i + j;
-+}
-Index: libstdc++-v3/config/abi/post/x86_64-linux-gnu/32/baseline_symbols.txt
++ D2() { }
++ D2(D2&&) { }
++ void operator()(int* p) const { delete p; }
++};
++
++std::shared_ptr<int> s5(nullptr, D2());
+Index: libstdc++-v3/testsuite/20_util/shared_ptr/observers/owner_before.cc
===================================================================
---- a/src/libstdc++-v3/config/abi/post/x86_64-linux-gnu/32/baseline_symbols.txt (.../tags/gcc_7_1_0_release)
-+++ b/src/libstdc++-v3/config/abi/post/x86_64-linux-gnu/32/baseline_symbols.txt (.../branches/gcc-7-branch)
-@@ -1329,6 +1329,7 @@
- FUNC:_ZNSbIwSt11char_traitsIwESaIwEEC1EPKwjRKS1_@@GLIBCXX_3.4
- FUNC:_ZNSbIwSt11char_traitsIwESaIwEEC1ERKS1_@@GLIBCXX_3.4
+--- a/src/libstdc++-v3/testsuite/20_util/shared_ptr/observers/owner_before.cc (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/testsuite/20_util/shared_ptr/observers/owner_before.cc (.../branches/gcc-7-branch)
+@@ -67,6 +67,12 @@
+ VERIFY( !a1.owner_before(w1) && !w1.owner_before(a1) );
+ std::weak_ptr<A> w2(a2);
+ VERIFY( !b1.owner_before(w2) && !w2.owner_before(b1) );
++
++ static_assert( noexcept(a1.owner_before(a0)), "" );
++ static_assert( noexcept(a1.owner_before(b1)), "" );
++ static_assert( noexcept(b1.owner_before(a1)), "" );
++ static_assert( noexcept(a1.owner_before(w1)), "" );
++ static_assert( noexcept(b1.owner_before(w1)), "" );
+ }
+
+ // Aliasing
+Index: libstdc++-v3/testsuite/20_util/function/assign/move.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/20_util/function/assign/move.cc (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/testsuite/20_util/function/assign/move.cc (.../branches/gcc-7-branch)
+@@ -38,11 +38,12 @@
+ fo2 = (std::move(fo));
+ VERIFY( static_cast<bool>(fo2) );
+ VERIFY( fo2() == 2 );
++
++ static_assert(std::is_nothrow_move_assignable<function>::value,
++ "PR libstdc++/81017");
+ }
+
+ int main()
+ {
+ test01();
+-
+- return 0;
+ }
+Index: libstdc++-v3/testsuite/20_util/function/cons/move.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/20_util/function/cons/move.cc (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/testsuite/20_util/function/cons/move.cc (.../branches/gcc-7-branch)
+@@ -36,11 +36,12 @@
+ function fo2(std::move(fo));
+ VERIFY( static_cast<bool>(fo2) );
+ VERIFY( fo2() == 2 );
++
++ static_assert(std::is_nothrow_move_constructible<function>::value,
++ "PR libstdc++/81017");
+ }
+
+ int main()
+ {
+ test01();
+-
+- return 0;
+ }
+Index: libstdc++-v3/testsuite/20_util/function_objects/mem_fn/80478.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/20_util/function_objects/mem_fn/80478.cc (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/testsuite/20_util/function_objects/mem_fn/80478.cc (.../branches/gcc-7-branch)
+@@ -0,0 +1,27 @@
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library. This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3. If not see
++// <http://www.gnu.org/licenses/>.
++
++// { dg-options "-std=gnu++17" }
++// { dg-do compile { target c++1z } }
++
++#include <functional>
++
++struct X {
++ void f() noexcept { }
++};
++
++auto f = std::mem_fn(&X::f);
+Index: libstdc++-v3/testsuite/20_util/specialized_algorithms/memory_management_tools/destroy_neg.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/20_util/specialized_algorithms/memory_management_tools/destroy_neg.cc (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/testsuite/20_util/specialized_algorithms/memory_management_tools/destroy_neg.cc (.../branches/gcc-7-branch)
+@@ -0,0 +1,50 @@
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library. This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3. If not see
++// <http://www.gnu.org/licenses/>.
++
++// { dg-options "-std=gnu++17" }
++// { dg-do compile { target c++1z } }
++
++#include <memory>
++
++// This has a trivial destructor, but should not be destructible!
++struct DeletedDtor {
++ ~DeletedDtor() = delete;
++};
++
++void
++test01()
++{
++ alignas(DeletedDtor) unsigned char buf[sizeof(DeletedDtor)];
++ auto p = ::new (buf) DeletedDtor();
++ std::destroy(p, p + 1); // { dg-error "here" }
++ std::destroy_n(p, 1); // { dg-error "here" }
++}
++
++class PrivateDtor {
++ ~PrivateDtor() { }
++};
++
++void
++test02()
++{
++ alignas(PrivateDtor) unsigned char buf[sizeof(PrivateDtor)];
++ auto p = ::new (buf) PrivateDtor();
++ std::destroy(p, p + 1); // { dg-error "here" }
++ std::destroy_n(p, 1); // { dg-error "here" }
++}
++
++// { dg-error "value type is destructible" "" { target *-*-* } 0 }
+Index: libstdc++-v3/testsuite/20_util/variant/deduction.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/20_util/variant/deduction.cc (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/testsuite/20_util/variant/deduction.cc (.../branches/gcc-7-branch)
+@@ -0,0 +1,39 @@
++// { dg-options "-std=gnu++17" }
++// { dg-do compile { target c++1z } }
++
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library. This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3. If not see
++// <http://www.gnu.org/licenses/>.
++
++#include <variant>
++
++template<typename T, typename U> struct require_same;
++template<typename T> struct require_same<T, T> { using type = void; };
++
++template<typename T, typename U>
++ typename require_same<T, U>::type
++ check_type(U&) { }
++
++void
++test01()
++{
++ std::variant<int, double> x(3);
++
++ std::variant copy = x;
++ check_type<decltype(x)>(copy);
++ std::variant move = std::move(x);
++ check_type<decltype(x)>(move);
++}
+Index: libstdc++-v3/testsuite/20_util/variant/any.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/20_util/variant/any.cc (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/testsuite/20_util/variant/any.cc (.../branches/gcc-7-branch)
+@@ -0,0 +1,31 @@
++// { dg-options "-std=gnu++17" }
++// { dg-do compile }
++
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library. This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3. If not see
++// <http://www.gnu.org/licenses/>.
++
++#include <any>
++#include <variant>
++
++struct A { std::variant<std::any> a; };
++
++void Bar(const A&);
++
++void Foo() {
++ A a;
++ Bar(a);
++}
+Index: libstdc++-v3/testsuite/20_util/weak_ptr/observers/owner_before.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/20_util/weak_ptr/observers/owner_before.cc (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/testsuite/20_util/weak_ptr/observers/owner_before.cc (.../branches/gcc-7-branch)
+@@ -27,7 +27,7 @@
+
+ // 20.6.6.3.5 weak_ptr observers [util.smartptr.weak.obs]
+
+-int
++void
+ test01()
+ {
+ // test empty weak_ptrs compare equivalent
+@@ -38,11 +38,14 @@
+ std::shared_ptr<B> p3;
+ VERIFY( !p1.owner_before(p3) && !p3.owner_before(p1) );
+
+- return 0;
++ static_assert( noexcept(p1.owner_before(p1)), "" );
++ static_assert( noexcept(p1.owner_before(p2)), "" );
++ static_assert( noexcept(p1.owner_before(p3)), "" );
++ static_assert( noexcept(p2.owner_before(p1)), "" );
+ }
+
+
+-int
++void
+ test02()
+ {
+ std::shared_ptr<A> a0;
+@@ -60,8 +63,6 @@
+
+ std::shared_ptr<B> b1(new B);
+ VERIFY( w1.owner_before(b1) || b1.owner_before(w1) );
+-
+- return 0;
+ }
+
+ int
+Index: libstdc++-v3/testsuite/20_util/tuple/78939.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/20_util/tuple/78939.cc (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/testsuite/20_util/tuple/78939.cc (.../branches/gcc-7-branch)
+@@ -0,0 +1,49 @@
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library. This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3. If not see
++// <http://www.gnu.org/licenses/>.
++
++// { dg-options "-std=gnu++17" }
++// { dg-do compile { target c++1z } }
++
++// PR libstdc++/78939
++
++#include <utility>
++
++struct A { int i, j; };
++
++int
++test01()
++{
++ A a{};
++ const auto [i, j] = a;
++ return i + j;
++}
++
++int
++test02()
++{
++ A a{};
++ volatile auto [i, j] = a;
++ return i + j;
++}
++
++int
++test03()
++{
++ A a{};
++ const volatile auto [i, j] = a;
++ return i + j;
++}
+Index: libstdc++-v3/config/abi/post/x86_64-linux-gnu/32/baseline_symbols.txt
+===================================================================
+--- a/src/libstdc++-v3/config/abi/post/x86_64-linux-gnu/32/baseline_symbols.txt (.../tags/gcc_7_1_0_release)
++++ b/src/libstdc++-v3/config/abi/post/x86_64-linux-gnu/32/baseline_symbols.txt (.../branches/gcc-7-branch)
+@@ -1329,6 +1329,7 @@
+ FUNC:_ZNSbIwSt11char_traitsIwESaIwEEC1EPKwjRKS1_@@GLIBCXX_3.4
+ FUNC:_ZNSbIwSt11char_traitsIwESaIwEEC1ERKS1_@@GLIBCXX_3.4
FUNC:_ZNSbIwSt11char_traitsIwESaIwEEC1ERKS2_@@GLIBCXX_3.4
+FUNC:_ZNSbIwSt11char_traitsIwESaIwEEC1ERKS2_jRKS1_@@GLIBCXX_3.4.24
FUNC:_ZNSbIwSt11char_traitsIwESaIwEEC1ERKS2_jj@@GLIBCXX_3.4
@@ -2313,6 +4859,51 @@ Index: libstdc++-v3/acinclude.m4
# Everything parsed; figure out what files and settings to use.
case $enable_symvers in
+Index: lto-plugin/ChangeLog
+===================================================================
+--- a/src/lto-plugin/ChangeLog (.../tags/gcc_7_1_0_release)
++++ b/src/lto-plugin/ChangeLog (.../branches/gcc-7-branch)
+@@ -1,3 +1,12 @@
++2017-07-26 Georg-Johann Lay <avr at gjlay.de>
++
++ Backport from 2017-07-21 trunk r250428.
++
++ PR lto/81487
++ * lto-plugin.c (claim_file_handler): Use xasprintf instead of
++ asprintf.
++ [hi!=0]: Swap hi and lo arguments supplied to xasprintf.
++
+ 2017-05-02 Release Manager
+
+ * GCC 7.1.0 released.
+Index: lto-plugin/lto-plugin.c
+===================================================================
+--- a/src/lto-plugin/lto-plugin.c (.../tags/gcc_7_1_0_release)
++++ b/src/lto-plugin/lto-plugin.c (.../branches/gcc-7-branch)
+@@ -975,17 +975,16 @@
+
+ if (file->offset != 0)
+ {
+- char *objname;
+ /* We pass the offset of the actual file, not the archive header.
+ Can't use PRIx64, because that's C99, so we have to print the
+- 64-bit hex int as two 32-bit ones. */
+- int lo, hi, t;
++ 64-bit hex int as two 32-bit ones. Use xasprintf instead of
++ asprintf because asprintf doesn't work as expected on some older
++ mingw32 hosts. */
++ int lo, hi;
+ lo = file->offset & 0xffffffff;
+ hi = ((int64_t)file->offset >> 32) & 0xffffffff;
+- t = hi ? asprintf (&objname, "%s at 0x%x%08x", file->name, lo, hi)
+- : asprintf (&objname, "%s at 0x%x", file->name, lo);
+- check (t >= 0, LDPL_FATAL, "asprintf failed");
+- lto_file.name = objname;
++ lto_file.name = hi ? xasprintf ("%s at 0x%x%08x", file->name, hi, lo)
++ : xasprintf ("%s at 0x%x", file->name, lo);
+ }
+ else
+ {
Index: maintainer-scripts/ChangeLog
===================================================================
--- a/src/maintainer-scripts/ChangeLog (.../tags/gcc_7_1_0_release)
@@ -2539,7 +5130,42 @@ Index: libgcc/ChangeLog
===================================================================
--- a/src/libgcc/ChangeLog (.../tags/gcc_7_1_0_release)
+++ b/src/libgcc/ChangeLog (.../branches/gcc-7-branch)
-@@ -1,3 +1,42 @@
+@@ -1,3 +1,77 @@
++2017-07-28 Sebastian Huber <sebastian.huber at embedded-brains.de>
++
++ Backport from mainline
++ 2017-07-28 Sebastian Huber <sebastian.huber at embedded-brains.de>
++
++ * config/rs6000/ibm-ldouble.c: Disable if defined __rtems__.
++
++2017-07-20 Peter Bergner <bergner at vnet.ibm.com>
++
++ Backport from mainline
++ 2017-07-07 Peter Bergner <bergner at vnet.ibm.com>
++
++ * config/rs6000/float128-ifunc.c: Don't include auxv.h.
++ (have_ieee_hw_p): Delete function.
++ (SW_OR_HW) Use __builtin_cpu_supports().
++
++2017-07-19 John Marino <gnugcc at marino.st>
++
++ * config/i386/dragonfly-unwind.h: Handle sigtramp relocation.
++
++2017-07-04 Joseph Myers <joseph at codesourcery.com>
++
++ * config/aarch64/linux-unwind.h (aarch64_fallback_frame_state),
++ config/alpha/linux-unwind.h (alpha_fallback_frame_state),
++ config/bfin/linux-unwind.h (bfin_fallback_frame_state),
++ config/i386/linux-unwind.h (x86_64_fallback_frame_state,
++ x86_fallback_frame_state), config/m68k/linux-unwind.h (struct
++ uw_ucontext), config/nios2/linux-unwind.h (struct nios2_ucontext),
++ config/pa/linux-unwind.h (pa32_fallback_frame_state),
++ config/riscv/linux-unwind.h (riscv_fallback_frame_state),
++ config/sh/linux-unwind.h (sh_fallback_frame_state),
++ config/tilepro/linux-unwind.h (tile_fallback_frame_state),
++ config/xtensa/linux-unwind.h (xtensa_fallback_frame_state): Use
++ ucontext_t instead of struct ucontext.
++
+2017-06-28 Richard Biener <rguenther at suse.de>
+
+ Backport from mainline
@@ -2593,6 +5219,19 @@ Index: libgcc/config/alpha/t-alpha
+# When GAS-generated unwind tables are created, they get created
+# after the __FRAME_END__ terminator, which causes an ld error.
+CRTSTUFF_T_CFLAGS = -fno-unwind-tables
+Index: libgcc/config/alpha/linux-unwind.h
+===================================================================
+--- a/src/libgcc/config/alpha/linux-unwind.h (.../tags/gcc_7_1_0_release)
++++ b/src/libgcc/config/alpha/linux-unwind.h (.../branches/gcc-7-branch)
+@@ -51,7 +51,7 @@
+ {
+ struct rt_sigframe {
+ siginfo_t info;
+- struct ucontext uc;
++ ucontext_t uc;
+ } *rt_ = context->cfa;
+ sc = &rt_->uc.uc_mcontext;
+ }
Index: libgcc/config/sparc/lb1spc.S
===================================================================
--- a/src/libgcc/config/sparc/lb1spc.S (.../tags/gcc_7_1_0_release)
@@ -2610,6 +5249,250 @@ Index: libgcc/config/sparc/lb1spc.S
#ifdef L_mulsi3
.text
.align 4
+Index: libgcc/config/m68k/linux-unwind.h
+===================================================================
+--- a/src/libgcc/config/m68k/linux-unwind.h (.../tags/gcc_7_1_0_release)
++++ b/src/libgcc/config/m68k/linux-unwind.h (.../branches/gcc-7-branch)
+@@ -33,7 +33,7 @@
+ /* <sys/ucontext.h> is unfortunately broken right now. */
+ struct uw_ucontext {
+ unsigned long uc_flags;
+- struct ucontext *uc_link;
++ ucontext_t *uc_link;
+ stack_t uc_stack;
+ mcontext_t uc_mcontext;
+ unsigned long uc_filler[80];
+Index: libgcc/config/riscv/linux-unwind.h
+===================================================================
+--- a/src/libgcc/config/riscv/linux-unwind.h (.../tags/gcc_7_1_0_release)
++++ b/src/libgcc/config/riscv/linux-unwind.h (.../branches/gcc-7-branch)
+@@ -42,7 +42,7 @@
+ struct rt_sigframe
+ {
+ siginfo_t info;
+- struct ucontext uc;
++ ucontext_t uc;
+ };
+
+ struct rt_sigframe *rt_;
+Index: libgcc/config/aarch64/linux-unwind.h
+===================================================================
+--- a/src/libgcc/config/aarch64/linux-unwind.h (.../tags/gcc_7_1_0_release)
++++ b/src/libgcc/config/aarch64/linux-unwind.h (.../branches/gcc-7-branch)
+@@ -55,7 +55,7 @@
+ struct rt_sigframe
+ {
+ siginfo_t info;
+- struct ucontext uc;
++ ucontext_t uc;
+ };
+
+ struct rt_sigframe *rt_;
+Index: libgcc/config/i386/linux-unwind.h
+===================================================================
+--- a/src/libgcc/config/i386/linux-unwind.h (.../tags/gcc_7_1_0_release)
++++ b/src/libgcc/config/i386/linux-unwind.h (.../branches/gcc-7-branch)
+@@ -58,7 +58,7 @@
+ if (*(unsigned char *)(pc+0) == 0x48
+ && *(unsigned long long *)(pc+1) == RT_SIGRETURN_SYSCALL)
+ {
+- struct ucontext *uc_ = context->cfa;
++ ucontext_t *uc_ = context->cfa;
+ /* The void * cast is necessary to avoid an aliasing warning.
+ The aliasing warning is correct, but should not be a problem
+ because it does not alias anything. */
+@@ -138,7 +138,7 @@
+ siginfo_t *pinfo;
+ void *puc;
+ siginfo_t info;
+- struct ucontext uc;
++ ucontext_t uc;
+ } *rt_ = context->cfa;
+ /* The void * cast is necessary to avoid an aliasing warning.
+ The aliasing warning is correct, but should not be a problem
+Index: libgcc/config/i386/dragonfly-unwind.h
+===================================================================
+--- a/src/libgcc/config/i386/dragonfly-unwind.h (.../tags/gcc_7_1_0_release)
++++ b/src/libgcc/config/i386/dragonfly-unwind.h (.../branches/gcc-7-branch)
+@@ -28,9 +28,13 @@
+
+ #include <sys/types.h>
+ #include <sys/sysctl.h>
++#include <sys/param.h>
+ #include <signal.h>
+ #include <sys/ucontext.h>
+ #include <machine/sigframe.h>
++#if __DragonFly_version > 400800
++#include <sys/kinfo.h>
++#endif
+
+
+ #define REG_NAME(reg) sf_uc.uc_mcontext.mc_## reg
+@@ -39,20 +43,44 @@
+ #define MD_FALLBACK_FRAME_STATE_FOR x86_64_dragonfly_fallback_frame_state
+
+
+-static void
+-x86_64_sigtramp_range (unsigned char **start, unsigned char **end)
++static int
++x86_64_outside_sigtramp_range (unsigned char *pc)
+ {
+- unsigned long ps_strings;
+- int mib[2];
+- size_t len;
++ static int sigtramp_range_determined = 0;
++ static unsigned char *sigtramp_start, *sigtramp_end;
+
+- mib[0] = CTL_KERN;
+- mib[1] = KERN_PS_STRINGS;
+- len = sizeof (ps_strings);
+- sysctl (mib, 2, &ps_strings, &len, NULL, 0);
++ if (sigtramp_range_determined == 0)
++ {
++#if __DragonFly_version > 400800
++ struct kinfo_sigtramp kst = {0};
++ size_t len = sizeof (kst);
++ int mib[3] = { CTL_KERN, KERN_PROC, KERN_PROC_SIGTRAMP };
+
+- *start = (unsigned char *)ps_strings - 32;
+- *end = (unsigned char *)ps_strings;
++ sigtramp_range_determined = 1;
++ if (sysctl (mib, 3, &kst, &len, NULL, 0) == 0)
++ {
++ sigtramp_range_determined = 2;
++ sigtramp_start = kst.ksigtramp_start;
++ sigtramp_end = kst.ksigtramp_end;
++ }
++#else
++ unsigned long ps_strings;
++ size_t len = sizeof (ps_strings);
++ int mib[2] = { CTL_KERN, KERN_PS_STRINGS };
++
++ sigtramp_range_determined = 1;
++ if (sysctl (mib, 2, &ps_strings, &len, NULL, 0) == 0)
++ {
++ sigtramp_range_determined = 2;
++ sigtramp_start = (unsigned char *)ps_strings - 32;
++ sigtramp_end = (unsigned char *)ps_strings;
++ }
++#endif
++ }
++ if (sigtramp_range_determined < 2) /* sysctl failed if < 2 */
++ return 1;
++
++ return (pc < sigtramp_start || pc >= sigtramp_end );
+ }
+
+
+@@ -60,13 +88,10 @@
+ x86_64_dragonfly_fallback_frame_state
+ (struct _Unwind_Context *context, _Unwind_FrameState *fs)
+ {
+- unsigned char *pc = context->ra;
+- unsigned char *sigtramp_start, *sigtramp_end;
+ struct sigframe *sf;
+ long new_cfa;
+
+- x86_64_sigtramp_range(&sigtramp_start, &sigtramp_end);
+- if (pc >= sigtramp_end || pc < sigtramp_start)
++ if (x86_64_outside_sigtramp_range(context->ra))
+ return _URC_END_OF_STACK;
+
+ sf = (struct sigframe *) context->cfa;
+Index: libgcc/config/rs6000/float128-ifunc.c
+===================================================================
+--- a/src/libgcc/config/rs6000/float128-ifunc.c (.../tags/gcc_7_1_0_release)
++++ b/src/libgcc/config/rs6000/float128-ifunc.c (.../branches/gcc-7-branch)
+@@ -45,48 +45,8 @@
+ #error "This module must not be compiled with IEEE 128-bit hardware support"
+ #endif
+
+-#include <sys/auxv.h>
++#define SW_OR_HW(SW, HW) (__builtin_cpu_supports ("ieee128") ? HW : SW)
+
+-/* Use the namespace clean version of getauxval. However, not all versions of
+- sys/auxv.h declare it, so declare it here. This code is intended to be
+- temporary until a suitable version of __builtin_cpu_supports is added that
+- allows us to tell quickly if the machine supports IEEE 128-bit hardware. */
+-extern unsigned long __getauxval (unsigned long);
+-
+-static int
+-have_ieee_hw_p (void)
+-{
+- static int ieee_hw_p = -1;
+-
+- if (ieee_hw_p < 0)
+- {
+- char *p = (char *) __getauxval (AT_PLATFORM);
+-
+- ieee_hw_p = 0;
+-
+- /* Don't use atoi/strtol/strncmp/etc. These may require the normal
+- environment to be setup to set errno to 0, and the ifunc resolvers run
+- before the whole glibc environment is initialized. */
+- if (p && p[0] == 'p' && p[1] == 'o' && p[2] == 'w' && p[3] == 'e'
+- && p[4] == 'r')
+- {
+- long n = 0;
+- char ch;
+-
+- p += 5;
+- while ((ch = *p++) >= '0' && (ch <= '9'))
+- n = (n * 10) + (ch - '0');
+-
+- if (n >= 9)
+- ieee_hw_p = 1;
+- }
+- }
+-
+- return ieee_hw_p;
+-}
+-
+-#define SW_OR_HW(SW, HW) (have_ieee_hw_p () ? HW : SW)
+-
+ /* Resolvers. */
+
+ /* We do not provide ifunc resolvers for __fixkfti, __fixunskfti, __floattikf,
+Index: libgcc/config/rs6000/ibm-ldouble.c
+===================================================================
+--- a/src/libgcc/config/rs6000/ibm-ldouble.c (.../tags/gcc_7_1_0_release)
++++ b/src/libgcc/config/rs6000/ibm-ldouble.c (.../branches/gcc-7-branch)
+@@ -45,7 +45,8 @@
+ This code currently assumes the most significant double is in
+ the lower numbered register or lower addressed memory. */
+
+-#if defined (__MACH__) || defined (__powerpc__) || defined (_AIX)
++#if (defined (__MACH__) || defined (__powerpc__) || defined (_AIX)) \
++ && !defined (__rtems__)
+
+ #define fabs(x) __builtin_fabs(x)
+ #define isless(x, y) __builtin_isless (x, y)
+Index: libgcc/config/sh/linux-unwind.h
+===================================================================
+--- a/src/libgcc/config/sh/linux-unwind.h (.../tags/gcc_7_1_0_release)
++++ b/src/libgcc/config/sh/linux-unwind.h (.../branches/gcc-7-branch)
+@@ -82,7 +82,7 @@
+ {
+ struct rt_sigframe {
+ siginfo_t info;
+- struct ucontext uc;
++ ucontext_t uc;
+ } *rt_ = context->cfa;
+ /* The void * cast is necessary to avoid an aliasing warning.
+ The aliasing warning is correct, but should not be a problem
+Index: libgcc/config/tilepro/linux-unwind.h
+===================================================================
+--- a/src/libgcc/config/tilepro/linux-unwind.h (.../tags/gcc_7_1_0_release)
++++ b/src/libgcc/config/tilepro/linux-unwind.h (.../branches/gcc-7-branch)
+@@ -61,7 +61,7 @@
+ struct rt_sigframe {
+ unsigned char save_area[C_ABI_SAVE_AREA_SIZE];
+ siginfo_t info;
+- struct ucontext uc;
++ ucontext_t uc;
+ } *rt_;
+
+ /* Return if this is not a signal handler. */
Index: libgcc/config/arm/unwind-arm.c
===================================================================
--- a/src/libgcc/config/arm/unwind-arm.c (.../tags/gcc_7_1_0_release)
@@ -2665,6 +5548,58 @@ Index: libgcc/config/arm/unwind-arm.h
#ifdef __cplusplus
} /* extern "C" */
+Index: libgcc/config/pa/linux-unwind.h
+===================================================================
+--- a/src/libgcc/config/pa/linux-unwind.h (.../tags/gcc_7_1_0_release)
++++ b/src/libgcc/config/pa/linux-unwind.h (.../branches/gcc-7-branch)
+@@ -80,7 +80,7 @@
+ struct sigcontext *sc;
+ struct rt_sigframe {
+ siginfo_t info;
+- struct ucontext uc;
++ ucontext_t uc;
+ } *frame;
+
+ /* rt_sigreturn trampoline:
+Index: libgcc/config/xtensa/linux-unwind.h
+===================================================================
+--- a/src/libgcc/config/xtensa/linux-unwind.h (.../tags/gcc_7_1_0_release)
++++ b/src/libgcc/config/xtensa/linux-unwind.h (.../branches/gcc-7-branch)
+@@ -67,7 +67,7 @@
+
+ struct rt_sigframe {
+ siginfo_t info;
+- struct ucontext uc;
++ ucontext_t uc;
+ } *rt_;
+
+ /* movi a2, __NR_rt_sigreturn; syscall */
+Index: libgcc/config/nios2/linux-unwind.h
+===================================================================
+--- a/src/libgcc/config/nios2/linux-unwind.h (.../tags/gcc_7_1_0_release)
++++ b/src/libgcc/config/nios2/linux-unwind.h (.../branches/gcc-7-branch)
+@@ -38,7 +38,7 @@
+
+ struct nios2_ucontext {
+ unsigned long uc_flags;
+- struct ucontext *uc_link;
++ ucontext_t *uc_link;
+ stack_t uc_stack;
+ struct nios2_mcontext uc_mcontext;
+ sigset_t uc_sigmask; /* mask last for extensibility */
+Index: libgcc/config/bfin/linux-unwind.h
+===================================================================
+--- a/src/libgcc/config/bfin/linux-unwind.h (.../tags/gcc_7_1_0_release)
++++ b/src/libgcc/config/bfin/linux-unwind.h (.../branches/gcc-7-branch)
+@@ -52,7 +52,7 @@
+ void *puc;
+ char retcode[8];
+ siginfo_t info;
+- struct ucontext uc;
++ ucontext_t uc;
+ } *rt_ = context->cfa;
+
+ /* The void * cast is necessary to avoid an aliasing warning.
Index: libgcc/configure
===================================================================
--- a/src/libgcc/configure (.../tags/gcc_7_1_0_release)
@@ -2892,6 +5827,35 @@ Index: libgcc/configure
# The cast to long int works around a bug in the HP C Compiler
# version HP92453-01 B.11.11.23709.GP, which incorrectly rejects
# declarations like `int a3[[(sizeof (unsigned char)) >= 0]];'.
+Index: gcc/dwarf2asm.c
+===================================================================
+--- a/src/gcc/dwarf2asm.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/dwarf2asm.c (.../branches/gcc-7-branch)
+@@ -345,7 +345,9 @@
+ for (i = 0; i < len; i++)
+ {
+ int c = str[i];
+- if (c == '\"' || c == '\\')
++ if (c == '\"')
++ fputc (XCOFF_DEBUGGING_INFO ? '\"' : '\\', asm_out_file);
++ else if (c == '\\')
+ fputc ('\\', asm_out_file);
+ if (ISPRINT (c))
+ fputc (c, asm_out_file);
+Index: gcc/tree-ssa-tail-merge.c
+===================================================================
+--- a/src/gcc/tree-ssa-tail-merge.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/tree-ssa-tail-merge.c (.../branches/gcc-7-branch)
+@@ -808,6 +808,9 @@
+ same_succ_flush_bb (basic_block bb)
+ {
+ same_succ *same = BB_SAME_SUCC (bb);
++ if (! same)
++ return;
++
+ BB_SAME_SUCC (bb) = NULL;
+ if (bitmap_single_bit_set_p (same->bbs))
+ same_succ_htab->remove_elt_with_hash (same, same->hashval);
Index: gcc/graphite-isl-ast-to-gimple.c
===================================================================
--- a/src/gcc/graphite-isl-ast-to-gimple.c (.../tags/gcc_7_1_0_release)
@@ -2992,6 +5956,148 @@ Index: gcc/graphite-isl-ast-to-gimple.c
else
codegen_error = !copy_cond_phi_args (old_phi, new_phi, iv_map, false);
+Index: gcc/tree-ssa-loop-niter.c
+===================================================================
+--- a/src/gcc/tree-ssa-loop-niter.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/tree-ssa-loop-niter.c (.../branches/gcc-7-branch)
+@@ -1142,8 +1142,12 @@
+ tree niter_type = TREE_TYPE (step);
+ tree mod = fold_build2 (FLOOR_MOD_EXPR, niter_type, *delta, step);
+ tree tmod;
+- tree assumption = boolean_true_node, bound;
+- tree type1 = (POINTER_TYPE_P (type)) ? sizetype : type;
++ mpz_t mmod;
++ tree assumption = boolean_true_node, bound, noloop;
++ bool ret = false, fv_comp_no_overflow;
++ tree type1 = type;
++ if (POINTER_TYPE_P (type))
++ type1 = sizetype;
+
+ if (TREE_CODE (mod) != INTEGER_CST)
+ return false;
+@@ -1151,51 +1155,96 @@
+ mod = fold_build2 (MINUS_EXPR, niter_type, step, mod);
+ tmod = fold_convert (type1, mod);
+
++ mpz_init (mmod);
++ wi::to_mpz (mod, mmod, UNSIGNED);
++ mpz_neg (mmod, mmod);
++
+ /* If the induction variable does not overflow and the exit is taken,
+- then the computation of the final value does not overflow. There
+- are three cases:
+- 1) The case if the new final value is equal to the current one.
+- 2) Induction varaible has pointer type, as the code cannot rely
+- on the object to that the pointer points being placed at the
+- end of the address space (and more pragmatically,
+- TYPE_{MIN,MAX}_VALUE is not defined for pointers).
+- 3) EXIT_MUST_BE_TAKEN is true, note it implies that the induction
+- variable does not overflow. */
+- if (!integer_zerop (mod) && !POINTER_TYPE_P (type) && !exit_must_be_taken)
++ then the computation of the final value does not overflow. This is
++ also obviously the case if the new final value is equal to the
++ current one. Finally, we postulate this for pointer type variables,
++ as the code cannot rely on the object to that the pointer points being
++ placed at the end of the address space (and more pragmatically,
++ TYPE_{MIN,MAX}_VALUE is not defined for pointers). */
++ if (integer_zerop (mod) || POINTER_TYPE_P (type))
++ fv_comp_no_overflow = true;
++ else if (!exit_must_be_taken)
++ fv_comp_no_overflow = false;
++ else
++ fv_comp_no_overflow =
++ (iv0->no_overflow && integer_nonzerop (iv0->step))
++ || (iv1->no_overflow && integer_nonzerop (iv1->step));
++
++ if (integer_nonzerop (iv0->step))
+ {
+- if (integer_nonzerop (iv0->step))
++ /* The final value of the iv is iv1->base + MOD, assuming that this
++ computation does not overflow, and that
++ iv0->base <= iv1->base + MOD. */
++ if (!fv_comp_no_overflow)
+ {
+- /* The final value of the iv is iv1->base + MOD, assuming
+- that this computation does not overflow, and that
+- iv0->base <= iv1->base + MOD. */
+ bound = fold_build2 (MINUS_EXPR, type1,
+ TYPE_MAX_VALUE (type1), tmod);
+ assumption = fold_build2 (LE_EXPR, boolean_type_node,
+ iv1->base, bound);
++ if (integer_zerop (assumption))
++ goto end;
+ }
++ if (mpz_cmp (mmod, bnds->below) < 0)
++ noloop = boolean_false_node;
++ else if (POINTER_TYPE_P (type))
++ noloop = fold_build2 (GT_EXPR, boolean_type_node,
++ iv0->base,
++ fold_build_pointer_plus (iv1->base, tmod));
+ else
++ noloop = fold_build2 (GT_EXPR, boolean_type_node,
++ iv0->base,
++ fold_build2 (PLUS_EXPR, type1,
++ iv1->base, tmod));
++ }
++ else
++ {
++ /* The final value of the iv is iv0->base - MOD, assuming that this
++ computation does not overflow, and that
++ iv0->base - MOD <= iv1->base. */
++ if (!fv_comp_no_overflow)
+ {
+- /* The final value of the iv is iv0->base - MOD, assuming
+- that this computation does not overflow, and that
+- iv0->base - MOD <= iv1->base. */
+ bound = fold_build2 (PLUS_EXPR, type1,
+ TYPE_MIN_VALUE (type1), tmod);
+ assumption = fold_build2 (GE_EXPR, boolean_type_node,
+ iv0->base, bound);
++ if (integer_zerop (assumption))
++ goto end;
+ }
+- if (integer_zerop (assumption))
+- return false;
+- else if (!integer_nonzerop (assumption))
+- niter->assumptions = fold_build2 (TRUTH_AND_EXPR, boolean_type_node,
+- niter->assumptions, assumption);
++ if (mpz_cmp (mmod, bnds->below) < 0)
++ noloop = boolean_false_node;
++ else if (POINTER_TYPE_P (type))
++ noloop = fold_build2 (GT_EXPR, boolean_type_node,
++ fold_build_pointer_plus (iv0->base,
++ fold_build1 (NEGATE_EXPR,
++ type1, tmod)),
++ iv1->base);
++ else
++ noloop = fold_build2 (GT_EXPR, boolean_type_node,
++ fold_build2 (MINUS_EXPR, type1,
++ iv0->base, tmod),
++ iv1->base);
+ }
+
+- /* Since we are transforming LT to NE and DELTA is constant, there
+- is no need to compute may_be_zero because this loop must roll. */
+-
++ if (!integer_nonzerop (assumption))
++ niter->assumptions = fold_build2 (TRUTH_AND_EXPR, boolean_type_node,
++ niter->assumptions,
++ assumption);
++ if (!integer_zerop (noloop))
++ niter->may_be_zero = fold_build2 (TRUTH_OR_EXPR, boolean_type_node,
++ niter->may_be_zero,
++ noloop);
+ bounds_add (bnds, wi::to_widest (mod), type);
+ *delta = fold_build2 (PLUS_EXPR, niter_type, *delta, mod);
+- return true;
++
++ ret = true;
++end:
++ mpz_clear (mmod);
++ return ret;
+ }
+
+ /* Add assertions to NITER that ensure that the control variable of the loop
Index: gcc/c-family/c-warn.c
===================================================================
--- a/src/gcc/c-family/c-warn.c (.../tags/gcc_7_1_0_release)
@@ -3068,6 +6174,40 @@ Index: gcc/ipa-polymorphic-call.c
continue;
pos = int_bit_position (fld);
+Index: gcc/tree-ssa-loop-unswitch.c
+===================================================================
+--- a/src/gcc/tree-ssa-loop-unswitch.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/tree-ssa-loop-unswitch.c (.../branches/gcc-7-branch)
+@@ -580,8 +580,9 @@
+ gcond *cond;
+ do
+ {
++ basic_block next = NULL;
+ if (single_succ_p (header))
+- header = single_succ (header);
++ next = single_succ (header);
+ else
+ {
+ cond = dyn_cast <gcond *> (last_stmt (header));
+@@ -591,12 +592,16 @@
+ /* Make sure to skip earlier hoisted guards that are left
+ in place as if (true). */
+ if (gimple_cond_true_p (cond))
+- header = te->dest;
++ next = te->dest;
+ else if (gimple_cond_false_p (cond))
+- header = fe->dest;
++ next = fe->dest;
+ else
+ break;
+ }
++ /* Never traverse a backedge. */
++ if (header->loop_father->header == next)
++ return NULL;
++ header = next;
+ }
+ while (1);
+ if (!flow_bb_inside_loop_p (loop, te->dest)
Index: gcc/c/ChangeLog
===================================================================
--- a/src/gcc/c/ChangeLog (.../tags/gcc_7_1_0_release)
@@ -3155,13 +6295,76 @@ Index: gcc/c/c-decl.c
if (specs->complex_p)
{
pedwarn (specs->locations[cdw_complex], OPT_Wpedantic,
+Index: gcc/optabs.c
+===================================================================
+--- a/src/gcc/optabs.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/optabs.c (.../branches/gcc-7-branch)
+@@ -3844,9 +3844,9 @@
+ if (cfun->can_throw_non_call_exceptions)
+ {
+ if (may_trap_p (x))
+- x = force_reg (mode, x);
++ x = copy_to_reg (x);
+ if (may_trap_p (y))
+- y = force_reg (mode, y);
++ y = copy_to_reg (y);
+ }
+
+ if (GET_MODE_CLASS (mode) == MODE_CC)
Index: gcc/DATESTAMP
===================================================================
--- a/src/gcc/DATESTAMP (.../tags/gcc_7_1_0_release)
+++ b/src/gcc/DATESTAMP (.../branches/gcc-7-branch)
@@ -1 +1 @@
-20170502
-+20170628
++20170731
+Index: gcc/configure
+===================================================================
+--- a/src/gcc/configure (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/configure (.../branches/gcc-7-branch)
+@@ -25217,7 +25217,42 @@
+
+ fi
+
++ { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for SPARC6 instructions" >&5
++$as_echo_n "checking assembler for SPARC6 instructions... " >&6; }
++if test "${gcc_cv_as_sparc_sparc6+set}" = set; then :
++ $as_echo_n "(cached) " >&6
++else
++ gcc_cv_as_sparc_sparc6=no
++ if test x$gcc_cv_as != x; then
++ $as_echo '.text
++ .register %g2, #scratch
++ .register %g3, #scratch
++ .align 4
++ rd %entropy, %g1
++ fpsll64x %f0, %f2, %f4' > conftest.s
++ if { ac_try='$gcc_cv_as $gcc_cv_as_flags -xarch=sparc6 -o conftest.o conftest.s >&5'
++ { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
++ (eval $ac_try) 2>&5
++ ac_status=$?
++ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
++ test $ac_status = 0; }; }
++ then
++ gcc_cv_as_sparc_sparc6=yes
++ else
++ echo "configure: failed program was" >&5
++ cat conftest.s >&5
++ fi
++ rm -f conftest.o conftest.s
++ fi
++fi
++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_sparc_sparc6" >&5
++$as_echo "$gcc_cv_as_sparc_sparc6" >&6; }
++if test $gcc_cv_as_sparc_sparc6 = yes; then
+
++$as_echo "#define HAVE_AS_SPARC6 1" >>confdefs.h
++
++fi
++
+ { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for LEON instructions" >&5
+ $as_echo_n "checking assembler for LEON instructions... " >&6; }
+ if test "${gcc_cv_as_sparc_leon+set}" = set; then :
Index: gcc/builtins.c
===================================================================
--- a/src/gcc/builtins.c (.../tags/gcc_7_1_0_release)
@@ -3205,6 +6408,17 @@ Index: gcc/fold-const.c
&& (tem = negate_expr (op1)) != op1
&& ! TREE_OVERFLOW (tem))
return fold_build2_loc (loc, MULT_EXPR, type,
+@@ -13726,8 +13727,8 @@
+ bool overflow;
+ wide_int val = wi::neg (arg0, &overflow);
+ t = force_fit_type (type, val, 1,
+- (overflow | TREE_OVERFLOW (arg0))
+- && !TYPE_UNSIGNED (type));
++ (overflow && ! TYPE_UNSIGNED (type))
++ || TREE_OVERFLOW (arg0));
+ break;
+ }
+
Index: gcc/omp-low.c
===================================================================
--- a/src/gcc/omp-low.c (.../tags/gcc_7_1_0_release)
@@ -3530,7 +6744,779 @@ Index: gcc/ChangeLog
===================================================================
--- a/src/gcc/ChangeLog (.../tags/gcc_7_1_0_release)
+++ b/src/gcc/ChangeLog (.../branches/gcc-7-branch)
-@@ -1,3 +1,708 @@
+@@ -1,3 +1,1480 @@
++2017-07-31 Andreas Krebbel <krebbel at linux.vnet.ibm.com>
++
++ Backport from mainline
++ 2017-07-31 Andreas Krebbel <krebbel at linux.vnet.ibm.com>
++
++ * config.gcc: Add z14.
++ * config/s390/driver-native.c (s390_host_detect_local_cpu): Add
++ CPU model numbers for z13s and z14.
++ * config/s390/s390-c.c (s390_resolve_overloaded_builtin): Replace
++ arch12 with z14.
++ * config/s390/s390-opts.h (enum processor_type): Rename
++ PROCESSOR_ARCH12 to PROCESSOR_3906_Z14.
++ * config/s390/s390.c (processor_table): Add field for CPU name to
++ be passed to Binutils.
++ (s390_asm_output_machine_for_arch): Use the new field in
++ processor_table for Binutils.
++ (s390_expand_builtin): Replace arch12 with z14.
++ (s390_issue_rate): Rename PROCESSOR_ARCH12 to PROCESSOR_3906_Z14.
++ (s390_get_sched_attrmask): Likewise.
++ (s390_get_unit_mask): Likewise.
++ * config/s390/s390.opt: Add z14 to processor_type enum.
++
++2017-07-31 Jakub Jelinek <jakub at redhat.com>
++
++ PR sanitizer/81604
++ * ubsan.c (ubsan_type_descriptor): For UBSAN_PRINT_ARRAY don't
++ change type to the element type, instead add eltype variable and
++ use it where we are interested in the element type.
++
++2017-07-28 Peter Bergner <bergner at vnet.ibm.com>
++
++ Backport from mainline
++ 2017-07-28 Peter Bergner <bergner at vnet.ibm.com>
++
++ * config/rs6000/ppc-auxv.h (PPC_FEATURE2_DARN): New define.
++ (PPC_FEATURE2_SCV): Likewise.
++ * config/rs6000/rs6000.c (cpu_supports_info): Use them.
++
++2017-07-28 David Edelsohn <dje.gcc at gmail.com>
++
++ Backport from mainline
++ 2017-07-25 David Edelsohn <dje.gcc at gmail.com>
++
++ * dwarf2asm.c (dw2_asm_output_nstring): Encode double quote
++ character for AIX.
++ * dwarf2out.c (output_macinfo): Copy debug_line_section_label
++ to dl_section_ref. On AIX, append an expression to subtract
++ the size of the section length to dl_section_ref.
++
++2017-07-28 Bin Cheng <bin.cheng at arm.com>
++
++ Backport from mainline r250496
++ 2017-07-25 Bin Cheng <bin.cheng at arm.com>
++
++ PR target/81414
++ * config/aarch64/cortex-a57-fma-steering.c (analyze): Skip fmul/fmac
++ instructions if no du chain is found.
++
++2017-07-28 Sebastian Huber <sebastian.huber at embedded-brains.de>
++
++ Backport from mainline
++ 2017-07-28 Sebastian Huber <sebastian.huber at embedded-brains.de>
++
++ * config.gcc (powerpc-*-rtems*): Remove rs6000/eabi.h. Add
++ rs6000/biarch64.h.
++ * config/rs6000/rtems.h (ASM_DECLARE_FUNCTION_SIZE): New macro.
++ (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P): Likewise.
++ (CRT_CALL_STATIC_FUNCTION): Likewise.
++ (ASM_DEFAULT_SPEC): New define.
++ (ASM_SPEC32): Likewise.
++ (ASM_SPEC64): Likewise.
++ (ASM_SPEC_COMMON): Likewise.
++ (ASM_SPEC): Likewise.
++ (INVALID_64BIT): Likewise.
++ (LINK_OS_DEFAULT_SPEC): Likewise.
++ (LINK_OS_SPEC32): Likewise.
++ (LINK_OS_SPEC64): Likewise.
++ (POWERPC_LINUX): Likewise.
++ (PTRDIFF_TYPE): Likewise.
++ (RESTORE_FP_PREFIX): Likewise.
++ (RESTORE_FP_SUFFIX): Likewise.
++ (SAVE_FP_PREFIX): Likewise.
++ (SAVE_FP_SUFFIX): Likewise.
++ (SIZE_TYPE): Likewise.
++ (SUBSUBTARGET_OVERRIDE_OPTIONS): Likewise.
++ (TARGET_64BIT): Likewise.
++ (TARGET_64BIT): Likewise.
++ (TARGET_AIX): Likewise.
++ (WCHAR_TYPE_SIZE): Likewise.
++ (WCHAR_TYPE): Undefine.
++ (TARGET_OS_CPP_BUILTINS): Add 64-bit PowerPC defines.
++ (CPP_OS_DEFAULT_SPEC): Use previous CPP_OS_RTEMS_SPEC.
++ (CPP_OS_RTEMS_SPEC): Delete.
++ (SUBSUBTARGET_EXTRA_SPECS): Remove cpp_os_rtems. Add
++ asm_spec_common, asm_spec32, asm_spec64, link_os_spec32, and
++ link_os_spec64.
++ * config/rs6000/t-rtems: Add mcpu=e6500/m64 multilibs.
++
++2017-07-28 Sebastian Huber <sebastian.huber at embedded-brains.de>
++
++ Backport from mainline
++ 2017-07-27 Sebastian Huber <sebastian.huber at embedded-brains.de>
++
++ * config.gcc (riscv*-*-elf*): Add (riscv*-*-rtems*).
++ * config/riscv/rtems.h: New file.
++
++2017-07-27 Eric Botcazou <ebotcazou at adacore.com>
++
++ * config/sparc/sparc.c (sparc_option_override): Set MASK_FSMULD flag
++ earlier and only if MASK_FPU is set. Adjust formatting.
++
++2017-07-27 Andreas Krebbel <krebbel at linux.vnet.ibm.com>
++
++ Backport from mainline
++ 2017-07-27 Andreas Krebbel <krebbel at linux.vnet.ibm.com>
++
++ PR target/81534
++ * config/s390/s390.md ("*atomic_compare_and_swap<mode>_1")
++ ("*atomic_compare_and_swapdi_2", "*atomic_compare_and_swapsi_3"):
++ Change s_operand to memory_operand.
++
++2017-07-27 Jakub Jelinek <jakub at redhat.com>
++
++ PR tree-optimization/81555
++ PR tree-optimization/81556
++ * tree-ssa-reassoc.c (rewrite_expr_tree): Add NEXT_CHANGED argument,
++ if true, force CHANGED for the recursive invocation.
++ (reassociate_bb): Remember original length of ops array, pass
++ len != orig_len as NEXT_CHANGED in rewrite_expr_tree call.
++
++2017-07-27 Martin Liska <mliska at suse.cz>
++
++ Backport from mainline
++ 2017-07-17 Martin Liska <mliska at suse.cz>
++
++ PR sanitizer/81302
++ * opts.c (finish_options): Do not allow -fgnu-tm
++ w/ -fsanitize={kernel-,}address. Say sorry.
++
++2017-07-27 Martin Liska <mliska at suse.cz>
++
++ Backport from mainline
++ 2017-07-26 Martin Liska <mliska at suse.cz>
++
++ PR sanitize/81186
++ * function.c (expand_function_start): Make expansion of
++ nonlocal_goto_save_area after parm_birth_insn.
++
++2017-07-27 Martin Liska <mliska at suse.cz>
++
++ Backport from mainline
++ 2017-06-30 Martin Liska <mliska at suse.cz>
++
++ PR sanitizer/81021
++ * tree-eh.c (lower_resx): Call BUILT_IN_ASAN_HANDLE_NO_RETURN
++ before BUILT_IN_UNWIND_RESUME when ASAN is used.
++
++2017-07-27 Martin Liska <mliska at suse.cz>
++
++ Backport from mainline
++ 2017-06-28 Martin Liska <mliska at suse.cz>
++
++ PR sanitizer/81224
++ * asan.c (instrument_derefs): Bail out inner references
++ that are hard register variables.
++
++2017-07-26 Sebastian Huber <sebastian.huber at embedded-brains.de>
++
++ Backport from mainline
++ 2017-07-26 Sebastian Huber <sebastian.huber at embedded-brains.de>
++
++ * config/sparc/sparc.c (dump_target_flag_bits): Dump MASK_FSMULD.
++ (sparc_option_override): Honour MASK_FSMULD.
++ * config/sparc/sparc.h (MASK_FEATURES): Add MASK_FSMULD.
++ * config/sparc/sparc.md (muldf3_extend): Use TARGET_FSMULD.
++ * config/sparc/sparc.opt (mfsmuld): New option.
++ * doc/invoke.texi (mfsmuld): Document option.
++
++2017-07-26 Georg-Johann Lay <avr at gjlay.de>
++
++ Backport from 2017-07-25 trunk r250499.
++
++ PR 81487
++ * hsa-brig.c (brig_init): Use xasprintf instead of asprintf.
++ * gimple-pretty-print.c (dump_probability): Same.
++ * tree-ssa-structalias.c (alias_get_name): Same.
++
++2017-07-26 Richard Biener <rguenther at suse.de>
++
++ Backport from mainline
++ 2017-06-18 Richard Biener <rguenther at suse.de>
++
++ PR tree-optimization/81410
++ * tree-vect-stmts.c (vectorizable_load): Properly adjust for
++ the gap in the ! slp_perm SLP case after each group.
++
++ 2017-07-25 Richard Biener <rguenther at suse.de>
++
++ PR tree-optimization/81455
++ * tree-ssa-loop-unswitch.c (find_loop_guard): Make sure to
++ not walk in cycles when looking for guards.
++
++ 2017-07-25 Richard Biener <rguenther at suse.de>
++
++ PR middle-end/81505
++ * fold-const.c (fold_negate_const): TREE_OVERFLOW should be
++ sticky.
++
++ 2017-06-28 Jakub Jelinek <jakub at redhat.com>
++
++ PR target/81175
++ * config/i386/i386.c (ix86_init_mmx_sse_builtins): Use def_builtin
++ rather than def_builtin_pure for __builtin_ia32_gatherpf*.
++
++ 2017-06-26 Richard Biener <rguenther at suse.de>
++
++ PR target/81175
++ * config/i386/i386.c (ix86_init_mmx_sse_builtins):
++ Use def_builtin_pure for all gather builtins.
++
++ 2017-06-21 Marc Glisse <marc.glisse at inria.fr>
++
++ * config/i386/i386.c (struct builtin_isa): New field pure_p.
++ Reorder for compactness.
++ (def_builtin, def_builtin2, ix86_add_new_builtins): Handle pure_p.
++ (def_builtin_pure, def_builtin_pure2): New functions.
++ (ix86_init_mmx_sse_builtins) [__builtin_ia32_stmxcsr]: Mark as pure.
++
++2017-07-26 Sebastian Huber <sebastian.huber at embedded-brains.de>
++
++ Backport from mainline
++ 2017-07-26 Sebastian Huber <sebastian.huber at embedded-brains.de>
++
++ * config/sparc/sparc.c (sparc_option_override): Remove MASK_FPU
++ from all CPU target flags enable members.
++
++2017-07-26 Sebastian Huber <sebastian.huber at embedded-brains.de>
++
++ Backport from mainline
++ 2017-07-25 Sebastian Huber <sebastian.huber at embedded-brains.de>
++
++ PR libgcc/61152
++ * config/aarch64/rtems.h: Add GCC Runtime Library Exception.
++ Format changes.
++ * config/arm/rtems.h: Likewise.
++ * config/bfin/rtems.h: Likewise.
++ * config/i386/rtemself.h: Likewise.
++ * config/lm32/rtems.h: Likewise.
++ * config/m32c/rtems.h: Likewise.
++ * config/m68k/rtemself.h: Likewise.
++ * config/microblaze/rtems.h: Likewise.
++ * config/mips/rtems.h: Likewise.
++ * config/moxie/rtems.h: Likewise.
++ * config/nios2/rtems.h: Likewise.
++ * config/rs6000/rtems.h: Likewise.
++ * config/rtems.h: Likewise.
++ * config/sh/rtems.h: Likewise.
++ * config/sh/rtemself.h: Likewise.
++ * config/sparc/rtemself.h: Likewise.
++
++2017-07-25 Bill Schmidt <wschmidt at linux.vnet.ibm.com>
++
++ Backport from mainline
++ 2017-07-14 Bill Schmidt <wschmidt at linux.vnet.ibm.com>
++
++ PR tree-optimization/81162
++ * gimple-ssa-strength-reduction.c (replace_mult_candidate): Don't
++ replace a negate with an add.
++
++2017-07-25 Georg-Johann Lay <avr at gjlay.de>
++
++ Backport from 2017-07-12 trunk r250151.
++
++ PR target/81407
++ * config/avr/avr.c (avr_encode_section_info)
++ [progmem && !TREE_READONLY]: Error if progmem object needs
++ constructing.
++
++2017-07-25 Wilco Dijkstra <wdijkstr at arm.com>
++
++ PR target/79041
++ * config/aarch64/aarch64.c (aarch64_classify_symbol):
++ Avoid SYMBOL_SMALL_ABSOLUTE for literals with pc-relative literals.
++
++2017-07-25 Georg-Johann Lay <avr at gjlay.de>
++
++ Backport from trunk r247719.
++
++ 2017-05-06 Richard Sandiford <richard.sandiford at linaro.org>
++
++ PR rtl-optimization/75964
++ * simplify-rtx.c (simplify_const_relational_operation): Remove
++ invalid handling of comparisons of integer ABS.
++
++2017-07-25 Bin Cheng <bin.cheng at arm.com>
++
++ Backport from 2017-07-20 trunk r250384.
++
++ PR tree-optimization/81388
++ Revert r238585:
++ 2016-07-21 Bin Cheng <bin.cheng at arm.com>
++
++ * tree-ssa-loop-niter.c (number_of_iterations_lt_to_ne): Clean up
++ by removing computation of may_be_zero.
++
++2017-07-23 Uros Bizjak <ubizjak at gmail.com>
++
++ PR target/80569
++ * config/i386/i386.c (ix86_option_override_internal): Disable
++ BMI, BMI2 and TBM instructions for -m16.
++
++2017-07-19 Michael Meissner <meissner at linux.vnet.ibm.com>
++
++ Back port from trunk
++ 2017-07-12 Michael Meissner <meissner at linux.vnet.ibm.com>
++
++ PR target/81193
++ * config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): If GLIBC
++ provides the hardware capability bits, define the macro
++ __BUILTIN_CPU_SUPPORTS__.
++ * config/rs6000/rs6000.c (cpu_expand_builtin): Generate a warning
++ if GLIBC does not provide the hardware capability bits. Add a
++ gcc_unreachable call if the built-in cpu function is neither
++ __builtin_cpu_is nor __builtin_cpu_supports.
++ * doc/extend.texi (PowerPC built-in functions): Document that
++ GLIBC 2.23 or newer is needed by __builtin_cpu_is and
++ __builtin_cpu_supports. Document the macros defined by GCC if the
++ newer GLIBC is available.
++
++2017-07-18 Uros Bizjak <ubizjak at gmail.com>
++
++ PR target/81471
++ * config/i386/i386.md (rorx_immediate_operand): New mode attribute.
++ (*bmi2_rorx<mode>3_1): Use rorx_immediate_operand as
++ operand 2 predicate.
++ (*bmi2_rorxsi3_1_zext): Use const_0_to_31_operand as
++ operand 2 predicate.
++ (ror,rol -> rorx splitters): Use const_int_operand as
++ operand 2 predicate.
++
++2017-07-18 Tom de Vries <tom at codesourcery.com>
++
++ backport from mainline:
++ PR target/81069
++ 2017-07-17 Tom de Vries <tom at codesourcery.com>
++
++ * config/nvptx/nvptx.c (nvptx_single): Insert diverging branch as late
++ as possible.
++
++2017-07-18 Georg-Johann Lay <avr at gjlay.de>
++
++ Backport from 2017-07-18 trunk r250301.
++
++ PR target/81473
++ * config/avr/avr.c (avr_optimize_casesi): Don't use
++ INT8_MIN, INT8_MAX, UINT8_MAX, INT16_MIN, INT16_MAX, UINT16_MAX.
++
++2017-07-17 Jakub Jelinek <jakub at redhat.com>
++
++ PR tree-optimization/81428
++ * match.pd (X / X -> one): Don't optimize _Fract divisions, as 1
++ can't be built for those types.
++
++ PR tree-optimization/81365
++ * tree-ssa-phiprop.c (propagate_with_phi): When considering hoisting
++ aggregate moves onto bb predecessor edges, make sure there are no
++ loads that could alias the lhs in between the start of bb and the
++ loads from *phi.
++
++ Backported from mainline
++ 2017-06-30 Jakub Jelinek <jakub at redhat.com>
++
++ PR target/81225
++ * config/i386/sse.md (vec_extract_lo_<mode><mask_name>): For
++ V8FI, V16FI and VI8F_256 iterators, use <store_mask_predicate> instead
++ of nonimmediate_operand and <store_mask_constraint> instead of m for
++ the input operand. For V8FI iterator, always split if input is a MEM.
++ For V16FI and V8SF_256 iterators, don't test if both operands are MEM
++ if <mask_applied>. For VI4F_256 iterator, use <store_mask_predicate>
++ instead of register_operand and <store_mask_constraint> instead of v for
++ the input operand. Make sure both operands aren't MEMs for if not
++ <mask_applied>.
++
++2017-07-17 Georg-Johann Lay <avr at gjlay.de>
++
++ Backport from 2017-07-17 trunk r250258.
++
++ PR 80929
++ * config/avr/avr.c (avr_mul_highpart_cost): New static function.
++ (avr_rtx_costs_1) [TRUNCATE]: Use it to compute mul_highpart cost.
++ [LSHIFTRT, outer_code = TRUNCATE]: Same.
++
++2017-07-17 Sebastian Huber <sebastian.huber at embedded-brains.de>
++
++ Backport from mainline
++ 2017-07-17 Sebastian Huber <sebastian.huber at embedded-brains.de>
++
++ * gcc/config/sparc/rtemself.h (TARGET_OS_CPP_BUILTINS): Add
++ conditional builtin define __FIX_LEON3FT_B2BST.
++
++2017-07-17 Daniel Cederman <cederman at gaisler.com>
++
++ Backport from mainline
++ 2017-07-17 Daniel Cederman <cederman at gaisler.com>
++
++ * config/sparc/t-rtems: Add mfix-gr712rc multilibs. Replace
++ MULTILIB_EXCEPTIONS with MULTILIB_REQUIRED. Match -mfix-gr712rc
++ with -mfix-ut700.
++
++2017-07-16 Eric Botcazou <ebotcazou at adacore.com>
++
++ PR rtl-optimization/81424
++ * optabs.c (prepare_cmp_insn): Use copy_to_reg instead of force_reg
++ to remove potential trapping from operands if -fnon-call-exceptions.
++
++2017-07-16 Daniel Cederman <cederman at gaisler.com>
++
++ * config/sparc/sparc.md (divdf3_fix): Add NOP to prevent back
++ to back store errata sensitive sequence from being generated.
++ (sqrtdf2_fix): Likewise.
++
++2017-07-12 Georg-Johann Lay <avr at gjlay.de>
++
++ Backport from 2017-07-12 trunk r250156.
++
++ PR target/79883
++ * config/avr/avr.c (avr_set_current_function): In diagnostic
++ messages: Quote keywords and (parts of) identifiers.
++ [WITH_AVRLIBC]: Warn for functions named "ISR", "SIGNAL" or
++ "INTERRUPT".
++
++2017-07-11 Daniel Cederman <cederman at gaisler.com>
++
++ * config/sparc/sparc.opt (mfix-ut700): New option.
++ (mfix-gr712rc): Likewise.
++ (sparc_fix_b2bst): New variable.
++ * doc/invoke.texi (SPARC options): Document them.
++ (ARM options): Fix warnings.
++ * config/sparc/sparc.c (sparc_do_work_around_errata): Insert NOP
++ instructions to prevent sequences that can trigger the store-store
++ errata for certain LEON3FT processors.
++ (pass_work_around_errata::gate): Also test sparc_fix_b2bst.
++ (sparc_option_override): Set sparc_fix_b2bst appropriately.
++ * config/sparc/sparc.md (fix_b2bst): New attribute.
++ (in_branch_delay): Prevent stores in delay slot if fix_b2bst.
++
++2017-07-10 Uros Bizjak <ubizjak at gmail.com>
++
++ PR target/81375
++ * config/i386/i386.md (divsf3): Add TARGET_SSE to TARGET_SSE_MATH.
++ (rcpps): Ditto.
++ (*rsqrtsf2_sse): Ditto.
++ (rsqrtsf2): Ditto.
++ (div<mode>3): Macroize insn from divdf3 and divsf3
++ using MODEF mode iterator.
++
++2017-07-07 Michael Meissner <meissner at linux.vnet.ibm.com>
++
++ Backport from mainline
++ 2017-07-07 Michael Meissner <meissner at linux.vnet.ibm.com>
++
++ PR target/81348
++ * config/rs6000/rs6000.md (HI sign_extend splitter): Use the
++ correct operand in doing the split.
++
++2017-07-07 Jose E. Marchesi <jose.marchesi at oracle.com>
++
++ * config/sparc/m8.md: New file.
++ * config/sparc/sparc.md: Include m8.md.
++
++2017-07-07 Jose E. Marchesi <jose.marchesi at oracle.com>
++
++ * config/sparc/sparc.opt: New option -mvis4b.
++ * config/sparc/sparc.c (dump_target_flag_bits): Handle MASK_VIS4B.
++ (sparc_option_override): Handle VIS4B.
++ (enum sparc_builtins): Define
++ SPARC_BUILTIN_DICTUNPACK{8,16,32},
++ SPARC_BUILTIN_FPCMP{LE,GT,EQ,NE}{8,16,32}SHL,
++ SPARC_BUILTIN_FPCMPU{LE,GT}{8,16,32}SHL,
++ SPARC_BUILTIN_FPCMPDE{8,16,32}SHL and
++ SPARC_BUILTIN_FPCMPUR{8,16,32}SHL.
++ (check_constant_argument): New function.
++ (sparc_vis_init_builtins): Define builtins
++ __builtin_vis_dictunpack{8,16,32},
++ __builtin_vis_fpcmp{le,gt,eq,ne}{8,16,32}shl,
++ __builtin_vis_fpcmpu{le,gt}{8,16,32}shl,
++ __builtin_vis_fpcmpde{8,16,32}shl and
++ __builtin_vis_fpcmpur{8,16,32}shl.
++ (sparc_expand_builtin): Check that the constant operands to
++ __builtin_vis_fpcmp*shl and _builtin_vis_dictunpack* are indeed
++ constant and in range.
++ * config/sparc/sparc-c.c (sparc_target_macros): Handle
++ TARGET_VIS4B.
++ * config/sparc/sparc.h (SPARC_IMM2_P): Define.
++ (SPARC_IMM5_P): Likewise.
++ * config/sparc/sparc.md (cpu_feature): Add new feagure "vis4b".
++ (enabled): Handle vis4b.
++ (UNSPEC_DICTUNPACK): New unspec.
++ (UNSPEC_FPCMPSHL): Likewise.
++ (UNSPEC_FPUCMPSHL): Likewise.
++ (UNSPEC_FPCMPDESHL): Likewise.
++ (UNSPEC_FPCMPURSHL): Likewise.
++ (cpu_feature): New CPU feature `vis4b'.
++ (dictunpack{8,16,32}): New insns.
++ (FPCSMODE): New mode iterator.
++ (fpcscond): New code iterator.
++ (fpcsucond): Likewise.
++ (fpcmp{le,gt,eq,ne}{8,16,32}{si,di}shl): New insns.
++ (fpcmpu{le,gt}{8,16,32}{si,di}shl): Likewise.
++ (fpcmpde{8,16,32}{si,di}shl): Likewise.
++ (fpcmpur{8,16,32}{si,di}shl): Likewise.
++ * config/sparc/constraints.md: Define constraints `q' for unsigned
++ 2-bit integer constants and `t' for unsigned 5-bit integer
++ constants.
++ * config/sparc/predicates.md (imm5_operand_dictunpack8): New
++ predicate.
++ (imm5_operand_dictunpack16): Likewise.
++ (imm5_operand_dictunpack32): Likewise.
++ (imm2_operand): Likewise.
++ * doc/invoke.texi (SPARC Options): Document -mvis4b.
++ * doc/extend.texi (SPARC VIS Built-in Functions): Document the
++ ditunpack* and fpcmp*shl builtins.
++
++2017-07-07 Jose E. Marchesi <jose.marchesi at oracle.com>
++
++ * config.gcc: Handle m8 in --with-{cpu,tune} options.
++ * config.in: Add HAVE_AS_SPARC6 define.
++ * config/sparc/driver-sparc.c (cpu_names): Add entry for the SPARC
++ M8.
++ * config/sparc/sol2.h (CPP_CPU64_DEFAULT_SPEC): Define for
++ TARGET_CPU_m8.
++ (ASM_CPU32_DEFAUILT_SPEC): Likewise.
++ (CPP_CPU_SPEC): Handle m8.
++ (ASM_CPU_SPEC): Likewise.
++ * config/sparc/sparc-opts.h (enum processor_type): Add
++ PROCESSOR_M8.
++ * config/sparc/sparc.c (m8_costs): New struct.
++ (sparc_option_override): Handle TARGET_CPU_m8.
++ (sparc32_initialize_trampoline): Likewise.
++ (sparc64_initialize_trampoline): Likewise.
++ (sparc_issue_rate): Likewise.
++ (sparc_register_move_cost): Likewise.
++ * config/sparc/sparc.h (TARGET_CPU_m8): Define.
++ (CPP_CPU64_DEFAULT_SPEC): Define for M8.
++ (ASM_CPU64_DEFAULT_SPEC): Likewise.
++ (CPP_CPU_SPEC): Handle M8.
++ (ASM_CPU_SPEC): Likewise.
++ (AS_M8_FLAG): Define.
++ * config/sparc/sparc.md: Add m8 to the cpu attribute.
++ * config/sparc/sparc.opt: New option -mcpu=m8 for sparc targets.
++ * configure.ac (HAVE_AS_SPARC6): Check for assembler support for
++ M8 instructions.
++ * configure: Regenerate.
++ * doc/invoke.texi (SPARC Options): Document -mcpu=m8 and
++ -mtune=m8.
++
++2017-07-07 Jose E. Marchesi <jose.marchesi at oracle.com>
++
++ * config/sparc/niagara7.md: Rework the DFA scheduler to use insn
++ subtypes.
++ * config/sparc/sparc.md: Remove the `v3pipe' insn attribute.
++ ("*movdi_insn_sp32"): Do not set v3pipe.
++ ("*movsi_insn"): Likewise.
++ ("*movdi_insn_sp64"): Likewise.
++ ("*movsf_insn"): Likewise.
++ ("*movdf_insn_sp32"): Likewise.
++ ("*movdf_insn_sp64"): Likewise.
++ ("*zero_extendsidi2_insn_sp64"): Likewise.
++ ("*sign_extendsidi2_insn"): Likewise.
++ ("*mov<VM32:mode>_insn"): Likewise.
++ ("*mov<VM64:mode>_insn_sp64"): Likewise.
++ ("*mov<VM64:mode>_insn_sp32"): Likewise.
++ ("<plusminus_insn><VADDSUB:mode>3"): Likewise.
++ ("<vlop:code><VL:mode>3"): Likewise.
++ ("*not_<vlop:code><VL:mode>3"): Likewise.
++ ("*nand<VL:mode>_vis"): Likewise.
++ ("*<vlnotop:code>_not1<VL:mode>_vis"): Likewise.
++ ("*<vlnotop:code>_not2<VL:mode>_vis"): Likewise.
++ ("one_cmpl<VL:mode>2"): Likewise.
++ ("faligndata<VM64:mode>_vis"): Likewise.
++ ("alignaddrsi_vis"): Likewise.
++ ("alignaddrdi_vis"): Likweise.
++ ("alignaddrlsi_vis"): Likewise.
++ ("alignaddrldi_vis"): Likewise.
++ ("fcmp<gcond:code><GCM:gcm_name><P:mode>_vis"): Likewise.
++ ("bmaskdi_vis"): Likewise.
++ ("bmasksi_vis"): Likewise.
++ ("bshuffle<VM64:mode>_vis"): Likewise.
++ ("cmask8<P:mode>_vis"): Likewise.
++ ("cmask16<P:mode>_vis"): Likewise.
++ ("cmask32<P:mode>_vis"): Likewise.
++ ("pdistn<P:mode>_vis"): Likewise.
++ ("<vis3_addsub_ss_patname><VASS:mode>3"): Likewise.
++
++2017-07-07 Jose E. Marchesi <jose.marchesi at oracle.com>
++
++ * config/sparc/sparc.md ("subtype"): New insn attribute.
++ ("*wrgsr_sp64"): Set insn subtype.
++ ("*rdgsr_sp64"): Likewise.
++ ("alignaddrsi_vis"): Likewise.
++ ("alignaddrdi_vis"): Likewise.
++ ("alignaddrlsi_vis"): Likewise.
++ ("alignaddrldi_vis"): Likewise.
++ ("<plusminus_insn><VADDSUB:mode>3"): Likewise.
++ ("fexpand_vis"): Likewise.
++ ("fpmerge_vis"): Likewise.
++ ("faligndata<VM64:mode>_vis"): Likewise.
++ ("bshuffle<VM64:mode>_vis"): Likewise.
++ ("cmask8<P:mode>_vis"): Likewise.
++ ("cmask16<P:mode>_vis"): Likewise.
++ ("cmask32<P:mode>_vis"): Likewise.
++ ("fchksm16_vis"): Likewise.
++ ("v<vis3_shift_patname><GCM:mode>3"): Likewise.
++ ("fmean16_vis"): Likewise.
++ ("fp<plusminus_insn>64_vis"): Likewise.
++ ("<plusminus_insn>v8qi3"): Likewise.
++ ("<vis3_addsub_ss_patname><VASS:mode>3"): Likewise.
++ ("<vis4_minmax_patname><VMMAX:mode>3"): Likewise.
++ ("<vis4_uminmax_patname><VMMAX:mode>3"): Likewise.
++ ("<vis3_addsub_ss_patname>v8qi3"): Likewise.
++ ("<vis4_addsub_us_patname><VAUS:mode>3"): Likewise.
++ ("*movqi_insn"): Likewise.
++ ("*movhi_insn"): Likewise.
++ ("*movsi_insn"): Likewise.
++ ("movsi_pic_gotdata_op"): Likewise.
++ ("*movdi_insn_sp32"): Likewise.
++ ("*movdi_insn_sp64"): Likewise.
++ ("movdi_pic_gotdata_op"): Likewise.
++ ("*movsf_insn"): Likewise.
++ ("*movdf_insn_sp32"): Likewise.
++ ("*movdf_insn_sp64"): Likewise.
++ ("*zero_extendhisi2_insn"): Likewise.
++ ("*zero_extendqihi2_insn"): Likewise.
++ ("*zero_extendqisi2_insn"): Likewise.
++ ("*zero_extendqidi2_insn"): Likewise.
++ ("*zero_extendhidi2_insn"): Likewise.
++ ("*zero_extendsidi2_insn_sp64"): Likewise.
++ ("ldfsr"): Likewise.
++ ("prefetch_64"): Likewise.
++ ("prefetch_32"): Likewise.
++ ("tie_ld32"): Likewise.
++ ("tie_ld64"): Likewise.
++ ("*tldo_ldub_sp32"): Likewise.
++ ("*tldo_ldub1_sp32"): Likewise.
++ ("*tldo_ldub2_sp32"): Likewise.
++ ("*tldo_ldub_sp64"): Likewise.
++ ("*tldo_ldub1_sp64"): Likewise.
++ ("*tldo_ldub2_sp64"): Likewise.
++ ("*tldo_ldub3_sp64"): Likewise.
++ ("*tldo_lduh_sp32"): Likewise.
++ ("*tldo_lduh1_sp32"): Likewise.
++ ("*tldo_lduh_sp64"): Likewise.
++ ("*tldo_lduh1_sp64"): Likewise.
++ ("*tldo_lduh2_sp64"): Likewise.
++ ("*tldo_lduw_sp32"): Likewise.
++ ("*tldo_lduw_sp64"): Likewise.
++ ("*tldo_lduw1_sp64"): Likewise.
++ ("*tldo_ldx_sp64"): Likewise.
++ ("*mov<VM32:mode>_insn"): Likewise.
++ ("*mov<VM64:mode>_insn_sp64"): Likewise.
++ ("*mov<VM64:mode>_insn_sp32"): Likewise.
++
++2017-07-07 Jose E. Marchesi <jose.marchesi at oracle.com>
++
++ * config/sparc/sparc.md ("type"): New insn type viscmp.
++ ("fcmp<gcond:code><GCM:gcm_name><P:mode>_vis"): Set insn type to
++ viscmp.
++ ("fpcmp<gcond:code>8<P:mode>_vis"): Likewise.
++ ("fucmp<gcond:code>8<P:mode>_vis"): Likewise.
++ ("fpcmpu<gcond:code><GCM:gcm_name><P:mode>_vis"): Likewise.
++ * config/sparc/niagara7.md ("n7_vis_logical_v3pipe"): Handle
++ viscmp.
++ ("n7_vis_logical_11cycle"): Likewise.
++ * config/sparc/niagara4.md ("n4_vis_logical"): Likewise.
++ * config/sparc/niagara2.md ("niag3_vis": Likewise.
++ * config/sparc/niagara.md ("niag_vis"): Likewise.
++ * config/sparc/ultra3.md ("us3_fga"): Likewise.
++ * config/sparc/ultra1_2.md ("us1_fga_double"): Likewise.
++
++2017-07-07 Jose E. Marchesi <jose.marchesi at oracle.com>
++
++ * config/sparc/sparc.md: New instruction type `bmask'.
++ (bmaskdi_vis): Use the `bmask' type.
++ (bmasksi_vis): Likewise.
++ * config/sparc/ultra3.md (us3_array): Likewise.
++ * config/sparc/niagara7.md (n7_array): Likewise.
++ * config/sparc/niagara4.md (n4_array): Likewise.
++ * config/sparc/niagara2.md (niag2_vis): Likewise.
++ (niag3_vis): Likewise.
++ * config/sparc/niagara.md (niag_vis): Likewise.
++
++2017-07-05 Georg-Johann Lay <avr at gjlay.de>
++
++ Backport from 2017-07-05 trunk r249995.
++
++ PR target/81305
++ * config/avr/avr.c (avr_out_movhi_mr_r_xmega) [CONSTANT_ADDRESS_P]:
++ Don't depend on "optimize > 0".
++ (out_movhi_r_mr, out_movqi_mr_r): Same.
++ (out_movhi_mr_r, out_movqi_r_mr): Same.
++ (avr_address_cost) [CONSTANT_ADDRESS_P]: Don't depend cost for
++ io_address_operand on "optimize > 0".
++
++2017-07-04 Uros Bizjak <ubizjak at gmail.com>
++
++ PR target/81300
++ * config/i386/i386.md (setcc + movzbl/and to xor + setcc peepholes):
++ Require dead FLAGS_REG at the beginning of a peephole.
++
++2017-07-04 Uros Bizjak <ubizjak at gmail.com>
++
++ PR target/81294
++ * config/i386/adxintrin.h (_subborrow_u32): Swap _X and _Y
++ arguments in the call to __builtin_ia32_sbb_u32.
++ (_subborrow_u64): Swap _X and _Y arguments in the call to
++ __builtin_ia32_sbb_u64.
++
++2017-07-03 Segher Boessenkool <segher at kernel.crashing.org>
++
++ Backport from trunk:
++
++ 2017-06-15 Segher Boessenkool <segher at kernel.crashing.org>
++
++ * config/rs6000/rs6000.md (add<mode>3): Use reg_or_subregno instead
++ of REGNO.
++
++2017-07-03 Tom de Vries <tom at codesourcery.com>
++
++ backport from mainline:
++ PR tree-optimization/81192
++ 2017-07-03 Tom de Vries <tom at codesourcery.com>
++
++ * tree-ssa-tail-merge.c (same_succ_flush_bb): Handle
++ BB_SAME_SUCC (bb) == NULL.
++
++2017-06-29 Michael Meissner <meissner at linux.vnet.ibm.com>
++
++ Backport from mainline
++ 2017-06-23 Michael Meissner <meissner at linux.vnet.ibm.com>
++
++ PR target/80510
++ * config/rs6000/rs6000.md (ALTIVEC_DFORM): Do not allow DImode in
++ 32-bit, since indexed is not valid for DImode.
++ (mov<mode>_hardfloat32): Reorder ISA 2.07 load/stores before ISA
++ 3.0 d-form load/stores to be the same as mov<mode>_hardfloat64.
++ (define_peephole2 for Altivec d-form load): Add 32-bit support.
++ (define_peephole2 for Altivec d-form store): Likewise.
++
++ Backport from mainline
++ 2017-06-20 Michael Meissner <meissner at linux.vnet.ibm.com>
++
++ PR target/79799
++ * config/rs6000/rs6000.c (rs6000_expand_vector_init): Add support
++ for doing vector set of SFmode on ISA 3.0.
++ * config/rs6000/vsx.md (vsx_set_v4sf_p9): Likewise.
++ (vsx_set_v4sf_p9_zero): Special case setting 0.0f to a V4SF
++ element.
++ (vsx_insert_extract_v4sf_p9): Add an optimization for inserting a
++ SFmode value into a V4SF variable that was extracted from another
++ V4SF variable without converting the element to double precision
++ and back to single precision vector format.
++ (vsx_insert_extract_v4sf_p9_2): Likewise.
++
++2017-06-29 Richard Biener <rguenther at suse.de>
++
++ Backport from mainline
++ 2017-06-19 Richard Biener <rguenther at suse.de>
++
++ PR ipa/81112
++ * ipa-prop.c (find_constructor_constant_at_offset): Handle
++ RANGE_EXPR conservatively.
++
+2017-06-28 Richard Biener <rguenther at suse.de>
+
+ Backport from mainline
@@ -3615,7 +7601,7 @@ Index: gcc/ChangeLog
+ Backport from mainline
+ 2017-05-04 Prakhar Bahuguna <prakhar.bahuguna at arm.com>
+
-+ * gcc/config/arm/arm-builtins.c (arm_init_builtins): Rename
++ * config/arm/arm-builtins.c (arm_init_builtins): Rename
+ __builtin_arm_ldfscr to __builtin_arm_get_fpscr, and rename
+ __builtin_arm_stfscr to __builtin_arm_set_fpscr.
+
@@ -4239,7 +8225,7 @@ Index: gcc/ChangeLog
2017-05-02 Release Manager
* GCC 7.1.0 released.
-@@ -110,9 +819,9 @@
+@@ -110,9 +1591,9 @@
Backport from mainline
2017-04-25 Andreas Krebbel <krebbel at linux.vnet.ibm.com>
@@ -4252,7 +8238,7 @@ Index: gcc/ChangeLog
2017-04-25 Andreas Krebbel <krebbel at linux.vnet.ibm.com>
-@@ -119,11 +828,11 @@
+@@ -119,11 +1600,11 @@
Backport from mainline
2017-04-25 Andreas Krebbel <krebbel at linux.vnet.ibm.com>
@@ -4269,7 +8255,7 @@ Index: gcc/ChangeLog
2017-04-25 Dominik Vogt <vogt at linux.vnet.ibm.com>
-@@ -130,30 +839,30 @@
+@@ -130,30 +1611,30 @@
Backport from maineline
2017-04-25 Dominik Vogt <vogt at linux.vnet.ibm.com>
@@ -4324,7 +8310,7 @@ Index: gcc/ChangeLog
2017-04-25 Dominik Vogt <vogt at linux.vnet.ibm.com>
-@@ -160,8 +869,8 @@
+@@ -160,8 +1641,8 @@
Backport from mainline
2017-04-25 Dominik Vogt <vogt at linux.vnet.ibm.com>
@@ -4335,7 +8321,7 @@ Index: gcc/ChangeLog
2017-04-25 Dominik Vogt <vogt at linux.vnet.ibm.com>
-@@ -169,8 +878,8 @@
+@@ -169,8 +1650,8 @@
Backport from mainline
2017-04-25 Dominik Vogt <vogt at linux.vnet.ibm.com>
@@ -4346,7 +8332,7 @@ Index: gcc/ChangeLog
2017-04-25 Jakub Jelinek <jakub at redhat.com>
-@@ -229,7 +938,7 @@
+@@ -229,7 +1710,7 @@
(build_array_type): Likewise. Add typeless_storage argument.
2017-04-19 Eric Botcazou <ebotcazou at adacore.com>
@@ -4355,7 +8341,7 @@ Index: gcc/ChangeLog
PR tree-optimization/80426
* tree-vrp.c (extract_range_from_binary_expr_1): For an additive
-@@ -271,7 +980,7 @@
+@@ -271,7 +1752,7 @@
are only used in debug insns.
2017-04-19 Eric Botcazou <ebotcazou at adacore.com>
@@ -4364,6 +8350,90 @@ Index: gcc/ChangeLog
* config/sparc/predicates.md (input_operand): Add comment. Return
true for any memory operand when LRA is in progress.
+Index: gcc/testsuite/gcc.target/powerpc/pr79799-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/pr79799-1.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/pr79799-1.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,43 @@
++/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-options "-mcpu=power9 -O2" } */
++
++#include <altivec.h>
++
++/* GCC 7.1 did not have a specialized method for inserting 32-bit floating
++ point on ISA 3.0 (power9) systems. */
++
++vector float
++insert_arg_0 (vector float vf, float f)
++{
++ return vec_insert (f, vf, 0);
++}
++
++vector float
++insert_arg_1 (vector float vf, float f)
++{
++ return vec_insert (f, vf, 1);
++}
++
++vector float
++insert_arg_2 (vector float vf, float f)
++{
++ return vec_insert (f, vf, 2);
++}
++
++vector float
++insert_arg_3 (vector float vf, float f)
++{
++ return vec_insert (f, vf, 3);
++}
++
++/* { dg-final { scan-assembler {\mxscvdpspn\M} } } */
++/* { dg-final { scan-assembler {\mxxinsertw\M} } } */
++/* { dg-final { scan-assembler-not {\mlvewx\M} } } */
++/* { dg-final { scan-assembler-not {\mlvx\M} } } */
++/* { dg-final { scan-assembler-not {\mvperm\M} } } */
++/* { dg-final { scan-assembler-not {\mvpermr\M} } } */
++/* { dg-final { scan-assembler-not {\mstfs\M} } } */
++/* { dg-final { scan-assembler-not {\mstxssp\M} } } */
++/* { dg-final { scan-assembler-not {\mstxsspx\M} } } */
+Index: gcc/testsuite/gcc.target/powerpc/pr79799-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/pr79799-2.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/pr79799-2.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,31 @@
++/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-options "-mcpu=power9 -O2" } */
++
++#include <altivec.h>
++
++/* Optimize x = vec_insert (vec_extract (v2, N), v1, M) for SFmode if N is the default
++ scalar position. */
++
++#if __ORDER_LITTLE_ENDIAN__
++#define ELE 2
++#else
++#define ELE 1
++#endif
++
++vector float
++foo (vector float v1, vector float v2)
++{
++ return vec_insert (vec_extract (v2, ELE), v1, 0);
++}
++
++/* { dg-final { scan-assembler {\mxxinsertw\M} } } */
++/* { dg-final { scan-assembler-not {\mxxextractuw\M} } } */
++/* { dg-final { scan-assembler-not {\mlvewx\M} } } */
++/* { dg-final { scan-assembler-not {\mlvx\M} } } */
++/* { dg-final { scan-assembler-not {\mvperm\M} } } */
++/* { dg-final { scan-assembler-not {\mvpermr\M} } } */
++/* { dg-final { scan-assembler-not {\mstfs\M} } } */
++/* { dg-final { scan-assembler-not {\mstxssp\M} } } */
++/* { dg-final { scan-assembler-not {\mstxsspx\M} } } */
Index: gcc/testsuite/gcc.target/powerpc/p8-vec-xl-xst.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/powerpc/p8-vec-xl-xst.c (.../tags/gcc_7_1_0_release)
@@ -4431,6 +8501,35 @@ Index: gcc/testsuite/gcc.target/powerpc/p8-vec-xl-xst.c
+/* { dg-final { scan-assembler-times "lxvd2x" 4 } } */
+/* { dg-final { scan-assembler-times "stxvd2x" 4 } } */
+/* { dg-final { scan-assembler-times "xxpermdi" 8 } } */
+Index: gcc/testsuite/gcc.target/powerpc/pr79799-3.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/pr79799-3.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/pr79799-3.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,24 @@
++/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-options "-mcpu=power9 -O2" } */
++
++#include <altivec.h>
++
++/* Optimize x = vec_insert (vec_extract (v2, N), v1, M) for SFmode. */
++
++vector float
++foo (vector float v1, vector float v2)
++{
++ return vec_insert (vec_extract (v2, 4), v1, 0);
++}
++
++/* { dg-final { scan-assembler {\mxxinsertw\M} } } */
++/* { dg-final { scan-assembler {\mxxextractuw\M} } } */
++/* { dg-final { scan-assembler-not {\mlvewx\M} } } */
++/* { dg-final { scan-assembler-not {\mlvx\M} } } */
++/* { dg-final { scan-assembler-not {\mvperm\M} } } */
++/* { dg-final { scan-assembler-not {\mvpermr\M} } } */
++/* { dg-final { scan-assembler-not {\mstfs\M} } } */
++/* { dg-final { scan-assembler-not {\mstxssp\M} } } */
++/* { dg-final { scan-assembler-not {\mstxsspx\M} } } */
Index: gcc/testsuite/gcc.target/powerpc/pr68163.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/powerpc/pr68163.c (.../tags/gcc_7_1_0_release)
@@ -4645,6 +8744,116 @@ Index: gcc/testsuite/gcc.target/powerpc/pr68163.c
+
+/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */
+/* { dg-final { scan-assembler-not {\mstw\M} } } */
+Index: gcc/testsuite/gcc.target/powerpc/pr79799-4.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/pr79799-4.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/pr79799-4.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,105 @@
++/* { dg-do run { target { powerpc*-*-linux* } } } */
++/* { dg-require-effective-target vsx_hw } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-require-effective-target p9vector_hw } */
++/* { dg-options "-mcpu=power9 -O2" } */
++
++#include <altivec.h>
++#include <stdlib.h>
++
++__attribute__ ((__noinline__))
++vector float
++insert_0 (vector float v, float f)
++{
++ return vec_insert (f, v, 0);
++}
++
++__attribute__ ((__noinline__))
++vector float
++insert_1 (vector float v, float f)
++{
++ return vec_insert (f, v, 1);
++}
++
++__attribute__ ((__noinline__))
++vector float
++insert_2 (vector float v, float f)
++{
++ return vec_insert (f, v, 2);
++}
++
++__attribute__ ((__noinline__))
++vector float
++insert_3 (vector float v, float f)
++{
++ return vec_insert (f, v, 3);
++}
++
++__attribute__ ((__noinline__))
++void
++test_insert (void)
++{
++ vector float v1 = { 1.0f, 2.0f, 3.0f, 4.0f };
++ vector float v2 = { 5.0f, 6.0f, 7.0f, 8.0f };
++
++ v1 = insert_0 (v1, 5.0f);
++ v1 = insert_1 (v1, 6.0f);
++ v1 = insert_2 (v1, 7.0f);
++ v1 = insert_3 (v1, 8.0f);
++
++ if (vec_any_ne (v1, v2))
++ abort ();
++}
++
++__attribute__ ((__noinline__))
++vector float
++insert_extract_0_3 (vector float v1, vector float v2)
++{
++ return vec_insert (vec_extract (v2, 3), v1, 0);
++}
++
++__attribute__ ((__noinline__))
++vector float
++insert_extract_1_2 (vector float v1, vector float v2)
++{
++ return vec_insert (vec_extract (v2, 2), v1, 1);
++}
++
++__attribute__ ((__noinline__))
++vector float
++insert_extract_2_1 (vector float v1, vector float v2)
++{
++ return vec_insert (vec_extract (v2, 1), v1, 2);
++}
++
++__attribute__ ((__noinline__))
++vector float
++insert_extract_3_0 (vector float v1, vector float v2)
++{
++ return vec_insert (vec_extract (v2, 0), v1, 3);
++}
++
++__attribute__ ((__noinline__))
++void
++test_insert_extract (void)
++{
++ vector float v1 = { 1.0f, 2.0f, 3.0f, 4.0f };
++ vector float v2 = { 5.0f, 6.0f, 7.0f, 8.0f };
++ vector float v3 = { 8.0f, 7.0f, 6.0f, 5.0f };
++
++ v1 = insert_extract_0_3 (v1, v2);
++ v1 = insert_extract_1_2 (v1, v2);
++ v1 = insert_extract_2_1 (v1, v2);
++ v1 = insert_extract_3_0 (v1, v2);
++
++ if (vec_any_ne (v1, v3))
++ abort ();
++}
++
++int
++main (void)
++{
++ test_insert ();
++ test_insert_extract ();
++ return 0;
++}
Index: gcc/testsuite/gcc.target/powerpc/versioned-copy-loop.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/powerpc/versioned-copy-loop.c (.../tags/gcc_7_1_0_release)
@@ -4680,6 +8889,36 @@ Index: gcc/testsuite/gcc.target/powerpc/versioned-copy-loop.c
+}
+
+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" } } */
+Index: gcc/testsuite/gcc.target/powerpc/pr79799-5.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/pr79799-5.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/pr79799-5.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,25 @@
++/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-options "-mcpu=power9 -O2" } */
++
++#include <altivec.h>
++
++/* Insure setting 0.0f to a V4SFmode element does not do a FP conversion. */
++
++vector float
++insert_arg_0 (vector float vf)
++{
++ return vec_insert (0.0f, vf, 0);
++}
++
++/* { dg-final { scan-assembler {\mxxinsertw\M} } } */
++/* { dg-final { scan-assembler-not {\mlvewx\M} } } */
++/* { dg-final { scan-assembler-not {\mlvx\M} } } */
++/* { dg-final { scan-assembler-not {\mvperm\M} } } */
++/* { dg-final { scan-assembler-not {\mvpermr\M} } } */
++/* { dg-final { scan-assembler-not {\mstfs\M} } } */
++/* { dg-final { scan-assembler-not {\mstxssp\M} } } */
++/* { dg-final { scan-assembler-not {\mstxsspx\M} } } */
++/* { dg-final { scan-assembler-not {\mxscvdpspn\M} } } */
++/* { dg-final { scan-assembler-not {\mxxextractuw\M} } } */
Index: gcc/testsuite/gcc.target/powerpc/ppc-round2.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/powerpc/ppc-round2.c (.../tags/gcc_7_1_0_release)
@@ -4767,22 +9006,62 @@ Index: gcc/testsuite/gcc.target/powerpc/ppc-round3.c
+{
+ return (float)(unsigned int)a;
+}
+Index: gcc/testsuite/gcc.target/powerpc/cpu-builtin-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/cpu-builtin-1.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/cpu-builtin-1.c (.../branches/gcc-7-branch)
+@@ -4,6 +4,11 @@
+ void
+ use_cpu_is_builtins (unsigned int *p)
+ {
++ /* If GCC was configured to use an old GLIBC (before 2.23), the
++ __builtin_cpu_is and __builtin_cpu_supports built-in functions return 0,
++ and the compiler issues a warning that you need a newer glibc to use them.
++ Use #ifdef to avoid the warning. */
++#ifdef __BUILTIN_CPU_SUPPORTS__
+ p[0] = __builtin_cpu_is ("power9");
+ p[1] = __builtin_cpu_is ("power8");
+ p[2] = __builtin_cpu_is ("power7");
+@@ -19,11 +24,15 @@
+ p[12] = __builtin_cpu_is ("ppc440");
+ p[13] = __builtin_cpu_is ("ppc405");
+ p[14] = __builtin_cpu_is ("ppc-cell-be");
++#else
++ p[0] = 0;
++#endif
+ }
+
+ void
+ use_cpu_supports_builtins (unsigned int *p)
+ {
++#ifdef __BUILTIN_CPU_SUPPORTS__
+ p[0] = __builtin_cpu_supports ("4xxmac");
+ p[1] = __builtin_cpu_supports ("altivec");
+ p[2] = __builtin_cpu_supports ("arch_2_05");
+@@ -62,4 +71,9 @@
+ p[35] = __builtin_cpu_supports ("ucache");
+ p[36] = __builtin_cpu_supports ("vcrypto");
+ p[37] = __builtin_cpu_supports ("vsx");
++ p[38] = __builtin_cpu_supports ("darn");
++ p[39] = __builtin_cpu_supports ("scv");
++#else
++ p[0] = 0;
++#endif
+ }
Index: gcc/testsuite/gcc.target/powerpc/pr80510-1.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/powerpc/pr80510-1.c (.../tags/gcc_7_1_0_release)
+++ b/src/gcc/testsuite/gcc.target/powerpc/pr80510-1.c (.../branches/gcc-7-branch)
-@@ -0,0 +1,213 @@
-+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+@@ -0,0 +1,211 @@
++/* { dg-do compile { target { powerpc*-*-* } } } */
++/* { dg-skip-if "" { powerpc*-*-darwin* } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
+/* { dg-options "-mcpu=power7 -O2" } */
+
+/* Make sure that STXSDX is generated for double scalars in Altivec registers
+ on power7 instead of moving the value to a FPR register and doing a X-FORM
-+ store.
-+
-+ 32-bit currently does not have support for STXSDX in the mov{df,dd} patterns. */
++ store. */
+
+#ifndef TYPE
+#define TYPE double
@@ -4989,18 +9268,16 @@ Index: gcc/testsuite/gcc.target/powerpc/pr80510-2.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/powerpc/pr80510-2.c (.../tags/gcc_7_1_0_release)
+++ b/src/gcc/testsuite/gcc.target/powerpc/pr80510-2.c (.../branches/gcc-7-branch)
-@@ -0,0 +1,214 @@
-+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
-+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+@@ -0,0 +1,212 @@
++/* { dg-do compile { target { powerpc*-*-* } } } */
++/* { dg-skip-if "" { powerpc*-*-darwin* } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+/* { dg-options "-mcpu=power8 -O2" } */
+
+/* Make sure that STXSSPX is generated for float scalars in Altivec registers
+ on power7 instead of moving the value to a FPR register and doing a X-FORM
-+ store.
-+
-+ 32-bit currently does not have support for STXSSPX in the mov{sf,sd} patterns. */
++ store. */
+
+#ifndef TYPE
+#define TYPE float
@@ -5219,6 +9496,35 @@ Index: gcc/testsuite/gcc.target/powerpc/stack-limit.c
+
+ arr[i] = 0;
+}
+Index: gcc/testsuite/gcc.target/powerpc/pr81348.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/powerpc/pr81348.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/powerpc/pr81348.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,24 @@
++/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
++/* { dg-require-effective-target powerpc_p9vector_ok } */
++/* { dg-options "-mcpu=power9 -Og" } */
++
++/* PR target/81348: Compiler died in doing short->float conversion due to using
++ the wrong register in a define_split. */
++
++int a;
++short b;
++float ***c;
++
++void d(void)
++{
++ int e = 3;
++
++ if (a)
++ e = b;
++
++ ***c = e;
++}
++
++/* { dg-final { scan-assembler {\mlxsihzx\M} } } */
++/* { dg-final { scan-assembler {\mvextsh2d\M} } } */
Index: gcc/testsuite/gcc.target/powerpc/pr80718.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/powerpc/pr80718.c (.../tags/gcc_7_1_0_release)
@@ -5704,6 +10010,634 @@ Index: gcc/testsuite/gcc.target/arm/tls-disable-literal-pool.c
+ return x; /* { dg-message "sorry, unimplemented: accessing thread-local storage is not currently supported with -mpure-code or -mslow-flash-data" } */
+}
+
+Index: gcc/testsuite/gcc.target/avr/isr-test.h
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/avr/isr-test.h (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/avr/isr-test.h (.../branches/gcc-7-branch)
+@@ -0,0 +1,282 @@
++#ifndef ISR_TEST_H
++#define ISR_TEST_H
++
++#include <string.h>
++
++#define ISR(N,...) \
++__attribute__ ((used, externally_visible , ## __VA_ARGS__)) \
++ void __vector_##N (void); \
++ void __vector_##N (void)
++
++#define SFR(ADDR) (*(unsigned char volatile*) (__AVR_SFR_OFFSET__ + (ADDR)))
++#define CORE_SFRS SFR (0x38)
++#define SREG SFR (0x3F)
++#define SPL SFR (0x3D)
++#define EIND SFR (0x3C)
++#define RAMPZ SFR (0x3B)
++#define RAMPY SFR (0x3A)
++#define RAMPX SFR (0x39)
++#define RAMPD SFR (0x38)
++
++#ifdef __AVR_HAVE_JMP_CALL__
++#define VEC_SIZE 4
++#else
++#define VEC_SIZE 2
++#endif
++
++#ifdef __AVR_TINY__
++#define FIRST_REG 16
++#else
++#define FIRST_REG 0
++#endif
++
++#define CR "\n\t"
++
++typedef struct
++{
++ unsigned char sfrs[8];
++ unsigned char gprs[32 - FIRST_REG];
++} regs_t;
++
++regs_t reginfo1, reginfo2;
++
++__attribute__((noinline))
++static void clear_reginfo (void)
++{
++ memset (reginfo1.sfrs, 0, sizeof (reginfo1.sfrs));
++ memset (reginfo2.sfrs, 0, sizeof (reginfo2.sfrs));
++}
++
++__attribute__((noinline))
++static void compare_reginfo (unsigned long gpr_ignore)
++{
++ signed char regno;
++ const unsigned char *preg1 = ®info1.gprs[0];
++ const unsigned char *preg2 = ®info2.gprs[0];
++
++ if (memcmp (®info1, ®info2, 8))
++ __builtin_abort();
++
++ gpr_ignore >>= FIRST_REG;
++
++ for (regno = FIRST_REG; regno < 32;
++ regno++, preg1++, preg2++, gpr_ignore >>= 1)
++ {
++ if (gpr_ignore & 1)
++ continue;
++
++ if (*preg1 != *preg2)
++ {
++ static signed char volatile failed_regno;
++ failed_regno = regno;
++ __builtin_abort();
++ }
++ }
++}
++
++/* STore GPR */
++#define ST(regno,M) \
++ CR "sts %[" #M "]+8-%[first]+" #regno ", r" #regno
++
++/* STore SFR */
++#define ST_SFR(sfr, n_sfr, M) \
++ CR "in __tmp_reg__,%i[s_" #sfr "]" \
++ CR "sts %[" #M "]+" #n_sfr ", __tmp_reg__"
++
++/* Named asm OPerand for SFR */
++#define OP_SFR(sfr) \
++ , [s_ ## sfr] "n" (&(sfr))
++
++/* Write funny value to SFR */
++#define XX_SFR(sfr) \
++ CR "dec r31 $ out %i[s_" #sfr "], r31"
++
++/* Write 0 to SFR */
++#define OO_SFR(sfr) \
++ CR "out %i[s_" #sfr "], __zero_reg__"
++
++/* Macros for SREG */
++#define ST_SREG(M) ST_SFR (SREG,0,M)
++#define OP_SREG OP_SFR (SREG)
++#define XX_SREG XX_SFR (SREG)
++
++/* Macros for EIND */
++#if defined __AVR_HAVE_EIJMP_EICALL__
++#define ST_EIND(M) ST_SFR (EIND,1,M)
++#define OP_EIND OP_SFR (EIND)
++#else
++#define ST_EIND(M) /* empty */
++#define OP_EIND /* empty */
++#endif
++
++/* Macros for RAMPX */
++#if defined (__AVR_HAVE_RAMPX__)
++#define ST_RAMPX(M) ST_SFR (RAMPX,2,M)
++#define OP_RAMPX OP_SFR (RAMPX)
++#define XX_RAMPX XX_SFR (RAMPX)
++#define OO_RAMPX OO_SFR (RAMPX)
++#else
++#define ST_RAMPX(M) /* empty */
++#define OP_RAMPX /* empty */
++#define XX_RAMPX /* empty */
++#define OO_RAMPX /* empty */
++#endif
++
++/* Macros for RAMPY */
++#if defined (__AVR_HAVE_RAMPY__)
++#define ST_RAMPY(M) ST_SFR (RAMPY,3,M)
++#define OP_RAMPY OP_SFR (RAMPY)
++#define XX_RAMPY XX_SFR (RAMPY)
++#define OO_RAMPY OO_SFR (RAMPY)
++#else
++#define ST_RAMPY(M) /* empty */
++#define OP_RAMPY /* empty */
++#define XX_RAMPY /* empty */
++#define OO_RAMPY /* empty */
++#endif
++
++/* Macros for RAMPZ */
++#if defined (__AVR_HAVE_RAMPZ__)
++#define ST_RAMPZ(M) ST_SFR (RAMPZ,4,M)
++#define OP_RAMPZ OP_SFR (RAMPZ)
++#define XX_RAMPZ XX_SFR (RAMPZ)
++#define OO_RAMPZ OO_SFR (RAMPZ)
++#else
++#define ST_RAMPZ(M) /* empty */
++#define OP_RAMPZ /* empty */
++#define XX_RAMPZ /* empty */
++#define OO_RAMPZ /* empty */
++#endif
++
++/* Macros for RAMPD */
++#if defined (__AVR_HAVE_RAMPD__)
++#define ST_RAMPD(M) ST_SFR (RAMPD,5,M)
++#define OP_RAMPD OP_SFR (RAMPD)
++#else
++#define ST_RAMPD(M) /* empty */
++#define OP_RAMPD /* empty */
++#endif
++
++/* Macros for all GPRs */
++#if defined __AVR_TINY__
++#define ST_REGS_LO(M) /* empty */
++#else
++#define ST_REGS_LO(M) \
++ ST(0,M) ST(1,M) ST(2,M) ST(3,M) \
++ ST(4,M) ST(5,M) ST(6,M) ST(7,M) \
++ ST(8,M) ST(9,M) ST(10,M) ST(11,M) \
++ ST(12,M) ST(13,M) ST(14,M) ST(15,M)
++#endif /* AVR_TINY */
++
++#define ST_REGS_HI(M) \
++ ST(16,M) ST(17,M) ST(18,M) ST(19,M) \
++ ST(20,M) ST(21,M) ST(22,M) ST(23,M) \
++ ST(24,M) ST(25,M) ST(26,M) ST(27,M) \
++ ST(28,M) ST(29,M) ST(30,M) ST(31,M)
++
++__attribute__((used,naked,noinline,noclone))
++static void host_store1 (void)
++{
++ __asm __volatile__
++ ("nop"
++ CR ".global do_stores_before"
++ CR ".type do_stores_before, at function"
++ CR "do_stores_before:"
++ /* Funny values to some SFRs */
++ CR "ldi r31, 1 + 'Z'"
++ XX_RAMPZ
++ XX_RAMPY
++ XX_RAMPX
++ CR "dec __zero_reg__"
++ CR "clr r31"
++ XX_SREG
++ /* Must set I-flag due to RETI of ISR */
++ CR "sei"
++ /* Store core regs before ISR */
++ ST_RAMPX (mem1)
++ ST_RAMPY (mem1)
++ ST_RAMPZ (mem1)
++ ST_RAMPD (mem1)
++ ST_EIND (mem1)
++ ST_SREG (mem1)
++ CR "ldi r31, 0xaa"
++ CR "mov __tmp_reg__, r31"
++ CR "ldi r31, 31"
++ ST_REGS_LO (mem1)
++ ST_REGS_HI (mem1)
++ CR "ret"
++ : /* No outputs */
++ : [mem1] "i" (®info1), [first] "n" (FIRST_REG)
++ OP_RAMPX
++ OP_RAMPY
++ OP_RAMPZ
++ OP_RAMPD
++ OP_EIND
++ OP_SREG
++ : "memory", "r31");
++}
++
++__attribute__((used,naked,noinline,noclone))
++static void host_store2 (void)
++{
++ __asm __volatile__
++ ("nop"
++ CR ".global do_stores_after"
++ CR ".type do_stores_after, at function"
++ CR "do_stores_after:"
++ /* Store core regs after ISR */
++ ST_REGS_LO (mem2)
++ ST_REGS_HI (mem2)
++ ST_RAMPX (mem2)
++ ST_RAMPY (mem2)
++ ST_RAMPZ (mem2)
++ ST_RAMPD (mem2)
++ ST_EIND (mem2)
++ ST_SREG (mem2)
++ /* Undo funny values */
++ CR "clr __zero_reg__"
++ OO_RAMPX
++ OO_RAMPY
++ OO_RAMPZ
++ CR "ret"
++ : /* No outputs */
++ : [mem2] "i" (®info2), [first] "n" (FIRST_REG)
++ OP_RAMPX
++ OP_RAMPY
++ OP_RAMPZ
++ OP_RAMPD
++ OP_EIND
++ OP_SREG
++ : "memory");
++}
++
++#define MK_CALL_ISR(vecno) \
++ __asm __volatile__ \
++ (/* Funny values to some SFRs */ \
++ /* Must set I-flag due to RETI of ISR */ \
++ /* Store core regs before ISR */ \
++ CR "%~call do_stores_before" \
++ /* Execute ISR */ \
++ CR "%~call __vectors + %[vect]" \
++ /* Store core regs after ISR */ \
++ /* Undo funny values */ \
++ CR "%~call do_stores_after" \
++ : /* No outputs */ \
++ : [vect] "i" (VEC_SIZE * (vecno)) \
++ , "i" (host_store1) \
++ , "i" (host_store2) \
++ : "memory", "r31")
++
++
++#define MK_RUN_ISR(N, IGMSK) \
++ \
++__attribute__((noinline,noclone)) \
++void run_isr_ ## N (void) \
++{ \
++ clear_reginfo(); \
++ MK_CALL_ISR (N); \
++ compare_reginfo (IGMSK); \
++}
++
++#endif /* ISR_TEST_H */
++
+Index: gcc/testsuite/gcc.target/avr/torture/isr-01-simple.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/avr/torture/isr-01-simple.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/avr/torture/isr-01-simple.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,98 @@
++/* { dg-do run } */
++/* { dg-options "-std=c99" } */
++
++#include "../isr-test.h"
++
++int volatile v;
++
++/**********************************************************************/
++
++ISR (1, signal)
++{
++}
++
++MK_RUN_ISR (1, 0)
++
++void test1 (void)
++{
++ run_isr_1();
++}
++
++/**********************************************************************/
++
++ISR (2, signal)
++{
++ v++;
++}
++
++MK_RUN_ISR (2, 0)
++
++void test2 (void)
++{
++ v = 0;
++ run_isr_2();
++ if (v != 1)
++ __builtin_abort();
++}
++
++
++/**********************************************************************/
++
++ISR (3, signal)
++{
++ __asm __volatile__ ("$ lds r27, v"
++ "$ swap r27"
++ "$ sts v, r27"
++ ::: "memory", "r27");
++}
++
++MK_RUN_ISR (3, 0)
++
++void test3 (void)
++{
++ run_isr_3();
++ if (v != 0x10)
++ __builtin_abort();
++}
++
++/**********************************************************************/
++
++ISR (4, signal)
++{
++ __asm __volatile__ ("sts v,__zero_reg__" ::: "memory");
++}
++
++MK_RUN_ISR (4, 0)
++
++void test4 (void)
++{
++ run_isr_4();
++ if (v != 0)
++ __builtin_abort();
++}
++
++/**********************************************************************/
++
++ISR (5, signal)
++{
++ __asm __volatile__ ("clt");
++}
++
++MK_RUN_ISR (5, 0)
++
++void test5 (void)
++{
++ run_isr_5();
++}
++
++/**********************************************************************/
++
++int main (void)
++{
++ test1();
++ test2();
++ test3();
++ test4();
++ test5();
++ return 0;
++}
+Index: gcc/testsuite/gcc.target/avr/torture/isr-02-call.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/avr/torture/isr-02-call.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/avr/torture/isr-02-call.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,60 @@
++/* { dg-do run } */
++/* { dg-options "-std=c99" } */
++
++#include "../isr-test.h"
++
++int volatile v;
++
++__attribute__((noinline,noclone))
++void inc_v (void)
++{
++ v++;
++}
++
++/**********************************************************************/
++
++ISR (1, signal)
++{
++ inc_v();
++}
++
++MK_RUN_ISR (1, 0)
++
++void test1 (void)
++{
++ run_isr_1();
++ if (v != 1)
++ __builtin_abort();
++}
++
++/**********************************************************************/
++
++ISR (2, signal)
++{
++ if (v == 1)
++ inc_v();
++ else
++ v += 2;
++}
++
++MK_RUN_ISR (2, 0)
++
++void test2 (void)
++{
++ run_isr_2();
++ if (v != 2)
++ __builtin_abort();
++ run_isr_2();
++ if (v != 4)
++ __builtin_abort();
++}
++
++
++/**********************************************************************/
++
++int main (void)
++{
++ test1();
++ test2();
++ return 0;
++}
+Index: gcc/testsuite/gcc.target/avr/torture/isr-03-fixed.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/avr/torture/isr-03-fixed.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/avr/torture/isr-03-fixed.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,146 @@
++/* { dg-do run } */
++/* { dg-options "-std=gnu99 -fno-lto -fno-toplevel-reorder" } */
++
++// No LTO for now due to PR lto/68384.
++
++#ifdef __AVR_TINY__
++unsigned char reg2;
++#else
++register unsigned char reg2 __asm("r2");
++#endif
++
++#include "../isr-test.h"
++
++#define SET_REG(reg,val) \
++ do { \
++ reg = (val); \
++ __asm __volatile__("" : "+r" (reg)); \
++ } while (0) \
++
++#define GET_REG(reg) \
++ ({ \
++ __asm __volatile__("" : "+r" (reg)); \
++ reg; \
++ })
++
++/**********************************************************************/
++
++ISR (1, signal)
++{
++ reg2++;
++}
++
++MK_RUN_ISR (1, 1ul << 2)
++
++void test1 (void)
++{
++ SET_REG (reg2, 0);
++ run_isr_1();
++ if (GET_REG (reg2) != 1)
++ __builtin_abort();
++}
++
++/**********************************************************************/
++
++__attribute__((noinline,noclone))
++void inc_r2 (void)
++{
++ reg2++;
++}
++
++ISR (2, signal)
++{
++ inc_r2 ();
++}
++
++MK_RUN_ISR (2, 1ul << 2)
++
++void test2 (void)
++{
++ run_isr_2();
++ if (GET_REG (reg2) != 2)
++ __builtin_abort();
++}
++
++
++/**********************************************************************/
++
++ISR (3, signal)
++{
++#ifndef __AVR_TINY__
++ register char r4 __asm ("r4");
++ __asm __volatile ("inc %0" : "+r" (r4));
++ __asm __volatile ("inc r5" ::: "r5");
++#endif
++}
++
++MK_RUN_ISR (3, 0)
++
++void test3 (void)
++{
++ run_isr_3();
++}
++
++
++/**********************************************************************/
++
++#define CLOBB(reg) \
++ do { \
++ __asm __volatile__ ("inc " #reg ::: #reg); \
++ } while (0)
++
++ISR (4, signal)
++{
++ char volatile v;
++ v = 1;
++
++#ifndef __AVR_TINY__
++ CLOBB (r3);
++ CLOBB (r4);
++ CLOBB (r5);
++ CLOBB (r6);
++ CLOBB (r7);
++ CLOBB (r8);
++ CLOBB (r9);
++ CLOBB (r10);
++ CLOBB (r11);
++ CLOBB (r12);
++ CLOBB (r13);
++ CLOBB (r14);
++ CLOBB (r15);
++ CLOBB (r16);
++ CLOBB (r17);
++#endif
++
++ CLOBB (r18);
++ CLOBB (r19);
++ CLOBB (r20);
++ CLOBB (r21);
++ CLOBB (r22);
++ CLOBB (r23);
++ CLOBB (r24);
++ CLOBB (r25);
++ CLOBB (r26);
++ CLOBB (r27);
++ CLOBB (r30);
++ CLOBB (r31);
++}
++
++MK_RUN_ISR (4, 0)
++
++void test4 (void)
++{
++ run_isr_4();
++}
++
++
++/**********************************************************************/
++
++int main (void)
++{
++ test1();
++ test2();
++ test3();
++ test4();
++ return 0;
++}
+Index: gcc/testsuite/gcc.target/s390/pr81534.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/s390/pr81534.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/s390/pr81534.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,17 @@
++/* PR81534 This testcase used to fail because the HI/QI
++ "atomic_fetch_<atomic><mode>" expander accepted symbolic references
++ and emitted CAS patterns whose insn definition rejected them. */
++
++/* { dg-do compile } */
++/* { dg-options "-O2 -march=zEC12" } */
++
++struct {
++ short b;
++ long c;
++} a = {};
++
++void
++d ()
++{
++ __atomic_fetch_add(&a.b, 0, 5);
++}
Index: gcc/testsuite/gcc.target/s390/pr80725.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/s390/pr80725.c (.../tags/gcc_7_1_0_release)
@@ -5735,6 +10669,230 @@ Index: gcc/testsuite/gcc.target/s390/pr80725.c
+ c = (char) (long) foo;
+ }
+}
+Index: gcc/testsuite/gcc.target/sparc/fpcmpshl.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/sparc/fpcmpshl.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/sparc/fpcmpshl.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,81 @@
++/* { dg-do compile } */
++/* { dg-options "-mvis4b" } */
++
++typedef unsigned char vec8 __attribute__((vector_size(8)));
++typedef short vec16 __attribute__((vector_size(8)));
++typedef int vec32 __attribute__((vector_size(8)));
++
++long test_fpcmple8shl (vec8 a, vec8 b)
++{
++ return __builtin_vis_fpcmple8shl (a, b, 2);
++}
++
++long test_fpcmpgt8shl (vec8 a, vec8 b)
++{
++ return __builtin_vis_fpcmpgt8shl (a, b, 2);
++}
++
++long test_fpcmpeq8shl (vec8 a, vec8 b)
++{
++ return __builtin_vis_fpcmpeq8shl (a, b, 2);
++}
++
++long test_fpcmpne8shl (vec8 a, vec8 b)
++{
++ return __builtin_vis_fpcmpne8shl (a, b, 2);
++}
++
++long test_fpcmple16shl (vec16 a, vec16 b)
++{
++ return __builtin_vis_fpcmple16shl (a, b, 2);
++}
++
++long test_fpcmpgt16shl (vec16 a, vec16 b)
++{
++ return __builtin_vis_fpcmpgt16shl (a, b, 2);
++}
++
++long test_fpcmpeq16shl (vec16 a, vec16 b)
++{
++ return __builtin_vis_fpcmpeq16shl (a, b, 2);
++}
++
++long test_fpcmpne16shl (vec16 a, vec16 b)
++{
++ return __builtin_vis_fpcmpne16shl (a, b, 2);
++}
++
++long test_fpcmple32shl (vec32 a, vec32 b)
++{
++ return __builtin_vis_fpcmple32shl (a, b, 2);
++}
++
++long test_fpcmpgt32shl (vec32 a, vec32 b)
++{
++ return __builtin_vis_fpcmpgt32shl (a, b, 2);
++}
++
++long test_fpcmpeq32shl (vec32 a, vec32 b)
++{
++ return __builtin_vis_fpcmpeq32shl (a, b, 2);
++}
++
++long test_fpcmpne32shl (vec32 a, vec32 b)
++{
++ return __builtin_vis_fpcmpne32shl (a, b, 2);
++}
++
++/* { dg-final { scan-assembler "fpcmple8shl\t%" } } */
++/* { dg-final { scan-assembler "fpcmpgt8shl\t%" } } */
++/* { dg-final { scan-assembler "fpcmpeq8shl\t%" } } */
++/* { dg-final { scan-assembler "fpcmpne8shl\t%" } } */
++
++/* { dg-final { scan-assembler "fpcmple16shl\t%" } } */
++/* { dg-final { scan-assembler "fpcmpgt16shl\t%" } } */
++/* { dg-final { scan-assembler "fpcmpeq16shl\t%" } } */
++/* { dg-final { scan-assembler "fpcmpne16shl\t%" } } */
++
++/* { dg-final { scan-assembler "fpcmple32shl\t%" } } */
++/* { dg-final { scan-assembler "fpcmpgt32shl\t%" } } */
++/* { dg-final { scan-assembler "fpcmpeq32shl\t%" } } */
++/* { dg-final { scan-assembler "fpcmpne32shl\t%" } } */
+Index: gcc/testsuite/gcc.target/sparc/fpcmpushl.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/sparc/fpcmpushl.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/sparc/fpcmpushl.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,43 @@
++/* { dg-do compile } */
++/* { dg-options "-mvis4b" } */
++
++typedef unsigned char vec8 __attribute__((vector_size(8)));
++typedef short vec16 __attribute__((vector_size(8)));
++typedef int vec32 __attribute__((vector_size(8)));
++
++long test_fpcmpule8shl (vec8 a, vec8 b)
++{
++ return __builtin_vis_fpcmpule8shl (a, b, 2);
++}
++
++long test_fpcmpugt8shl (vec8 a, vec8 b)
++{
++ return __builtin_vis_fpcmpugt8shl (a, b, 2);
++}
++
++long test_fpcmpule16shl (vec16 a, vec16 b)
++{
++ return __builtin_vis_fpcmpule16shl (a, b, 2);
++}
++
++long test_fpcmpugt16shl (vec16 a, vec16 b)
++{
++ return __builtin_vis_fpcmpugt16shl (a, b, 2);
++}
++
++long test_fpcmpule32shl (vec32 a, vec32 b)
++{
++ return __builtin_vis_fpcmpule32shl (a, b, 2);
++}
++
++long test_fpcmpugt32shl (vec32 a, vec32 b)
++{
++ return __builtin_vis_fpcmpugt32shl (a, b, 2);
++}
++
++/* { dg-final { scan-assembler "fpcmpule8shl\t%" } } */
++/* { dg-final { scan-assembler "fpcmpugt8shl\t%" } } */
++/* { dg-final { scan-assembler "fpcmpule16shl\t%" } } */
++/* { dg-final { scan-assembler "fpcmpugt16shl\t%" } } */
++/* { dg-final { scan-assembler "fpcmpule32shl\t%" } } */
++/* { dg-final { scan-assembler "fpcmpugt32shl\t%" } } */
+Index: gcc/testsuite/gcc.target/sparc/fpcmpurshl.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/sparc/fpcmpurshl.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/sparc/fpcmpurshl.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,25 @@
++/* { dg-do compile } */
++/* { dg-options "-mvis4b" } */
++
++typedef unsigned char vec8 __attribute__((vector_size(8)));
++typedef short vec16 __attribute__((vector_size(8)));
++typedef int vec32 __attribute__((vector_size(8)));
++
++long test_fpcmpur8shl (vec8 a, vec8 b)
++{
++ return __builtin_vis_fpcmpur8shl (a, b, 2);
++}
++
++long test_fpcmpur16shl (vec16 a, vec16 b)
++{
++ return __builtin_vis_fpcmpur16shl (a, b, 2);
++}
++
++long test_fpcmpur32shl (vec32 a, vec32 b)
++{
++ return __builtin_vis_fpcmpur32shl (a, b, 2);
++}
++
++/* { dg-final { scan-assembler "fpcmpur8shl\t%" } } */
++/* { dg-final { scan-assembler "fpcmpur16shl\t%" } } */
++/* { dg-final { scan-assembler "fpcmpur32shl\t%" } } */
+Index: gcc/testsuite/gcc.target/sparc/fpcmpdeshl.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/sparc/fpcmpdeshl.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/sparc/fpcmpdeshl.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,25 @@
++/* { dg-do compile } */
++/* { dg-options "-mvis4b" } */
++
++typedef unsigned char vec8 __attribute__((vector_size(8)));
++typedef short vec16 __attribute__((vector_size(8)));
++typedef int vec32 __attribute__((vector_size(8)));
++
++long test_fpcmpde8shl (vec8 a, vec8 b)
++{
++ return __builtin_vis_fpcmpde8shl (a, b, 2);
++}
++
++long test_fpcmpde16shl (vec16 a, vec16 b)
++{
++ return __builtin_vis_fpcmpde16shl (a, b, 2);
++}
++
++long test_fpcmpde32shl (vec32 a, vec32 b)
++{
++ return __builtin_vis_fpcmpde32shl (a, b, 2);
++}
++
++/* { dg-final { scan-assembler "fpcmpde8shl\t%" } } */
++/* { dg-final { scan-assembler "fpcmpde16shl\t%" } } */
++/* { dg-final { scan-assembler "fpcmpde32shl\t%" } } */
+Index: gcc/testsuite/gcc.target/sparc/dictunpack.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/sparc/dictunpack.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/sparc/dictunpack.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,25 @@
++/* { dg-do compile } */
++/* { dg-options "-mvis4b" } */
++
++typedef unsigned char vec8 __attribute__((vector_size(8)));
++typedef short vec16 __attribute__((vector_size(8)));
++typedef int vec32 __attribute__((vector_size(8)));
++
++vec8 test_dictunpack8 (double a)
++{
++ return __builtin_vis_dictunpack8 (a, 6);
++}
++
++vec16 test_dictunpack16 (double a)
++{
++ return __builtin_vis_dictunpack16 (a, 14);
++}
++
++vec32 test_dictunpack32 (double a)
++{
++ return __builtin_vis_dictunpack32 (a, 30);
++}
++
++/* { dg-final { scan-assembler "dictunpack\t%" } } */
++/* { dg-final { scan-assembler "dictunpack\t%" } } */
++/* { dg-final { scan-assembler "dictunpack\t%" } } */
Index: gcc/testsuite/gcc.target/sparc/sparc-ret-3.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/sparc/sparc-ret-3.c (.../tags/gcc_7_1_0_release)
@@ -5813,6 +10971,37 @@ Index: gcc/testsuite/gcc.target/sparc/niagara7-align.c
+/* { dg-options "-falign-functions -mcpu=niagara7" } */
+/* { dg-final { scan-assembler "\.align 64" } } */
+void foo(void) {}
+Index: gcc/testsuite/gcc.target/aarch64/pr79041-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/aarch64/pr79041-2.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/aarch64/pr79041-2.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,12 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mcmodel=large -mpc-relative-literal-loads" } */
++/* { dg-require-effective-target lp64 } */
++
++__int128
++t (void)
++{
++ return (__int128)1 << 80;
++}
++
++/* { dg-final { scan-assembler "adr" } } */
++/* { dg-final { scan-assembler-not "adrp" } } */
+Index: gcc/testsuite/gcc.target/aarch64/pr81414.C
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/aarch64/pr81414.C (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/aarch64/pr81414.C (.../branches/gcc-7-branch)
+@@ -0,0 +1,9 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mcpu=cortex-a57" } */
++
++typedef __Float32x2_t float32x2_t;
++float32x2_t
++foo1 (float32x2_t __a, float32x2_t __b, float32x2_t __c) {
++ return __b * __c + __a;
++}
++
Index: gcc/testsuite/gcc.target/i386/pr81121.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/i386/pr81121.c (.../tags/gcc_7_1_0_release)
@@ -5858,6 +11047,22 @@ Index: gcc/testsuite/gcc.target/i386/pr22152.c
return sum;
}
+Index: gcc/testsuite/gcc.target/i386/adx-addcarryx64-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/adx-addcarryx64-2.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/adx-addcarryx64-2.c (.../branches/gcc-7-branch)
+@@ -44,9 +44,9 @@
+ sum_ref = 0x0LL;
+
+ /* X = 0x0000000000000001, Y = 0x0000000000000000, C = 0. */
+- c = _subborrow_u64 (c, x, y, &x);
++ c = _subborrow_u64 (c, y, x, &x);
+ /* X = 0xFFFFFFFFFFFFFFFF, Y = 0x0000000000000000, C = 1. */
+- c = _subborrow_u64 (c, x, y, &x);
++ c = _subborrow_u64 (c, y, x, &x);
+ /* X = 0x0000000000000000, Y = 0x0000000000000000, C = 1. */
+
+ if (x != sum_ref)
Index: gcc/testsuite/gcc.target/i386/pr80706.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/i386/pr80706.c (.../tags/gcc_7_1_0_release)
@@ -5893,6 +11098,94 @@ Index: gcc/testsuite/gcc.target/i386/pr80706.c
+ __builtin_abort ();
+ return 0;
+}
+Index: gcc/testsuite/gcc.target/i386/pr81471.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr81471.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr81471.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,13 @@
++/* PR target/81471 */
++/* { dg-do compile { target { ! ia32 } } } */
++/* { dg-options "-O2 -mbmi2" } */
++
++static inline unsigned int rotl (unsigned int x, int k)
++{
++ return (x << k) | (x >> (32 - k));
++}
++
++unsigned long long test (unsigned int z)
++{
++ return rotl (z, 55);
++}
+Index: gcc/testsuite/gcc.target/i386/pr81225.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr81225.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr81225.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,14 @@
++/* PR target/81225 */
++/* { dg-do compile } */
++/* { dg-options "-mavx512ifma -O3 -ffloat-store" } */
++
++long a[24];
++float b[4], c[24];
++int d;
++
++void
++foo ()
++{
++ for (d = 0; d < 24; d++)
++ c[d] = (float) d ? : b[a[d]];
++}
+Index: gcc/testsuite/gcc.target/i386/pr69255-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr69255-2.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr69255-2.c (.../branches/gcc-7-branch)
+@@ -12,8 +12,9 @@
+ void
+ foo (const long long *p)
+ {
+- __builtin_ia32_gather3siv4di (a, p, b, 1, 1); /* { dg-error "needs isa option -m32 -mavx512vl" } */
++ volatile __attribute__ ((__vector_size__ (32))) long long c;
++ c = __builtin_ia32_gather3siv4di (a, p, b, 1, 1); /* { dg-error "needs isa option -m32 -mavx512vl" } */
+ }
+
+-/* { dg-warning "AVX vector return without AVX enabled changes the ABI" "" { target *-*-* } 15 } */
+-/* { dg-warning "AVX vector argument without AVX enabled changes the ABI" "" { target *-*-* } 15 } */
++/* { dg-warning "AVX vector return without AVX enabled changes the ABI" "" { target *-*-* } 16 } */
++/* { dg-warning "AVX vector argument without AVX enabled changes the ABI" "" { target *-*-* } 16 } */
+Index: gcc/testsuite/gcc.target/i386/pr81294-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr81294-1.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr81294-1.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,29 @@
++/* PR target/81294 */
++/* { dg-do run } */
++/* { dg-options "-O2" } */
++
++#include <x86intrin.h>
++
++int
++main ()
++{
++ volatile unsigned char c;
++ unsigned int x;
++ volatile unsigned int y, sum_ref;
++
++ c = 0;
++ x = 1;
++ y = 0;
++ sum_ref = 0x0;
++
++ /* X = 0x00000001, Y = 0x00000000, C = 0. */
++ c = _subborrow_u32 (c, y, x, &x);
++ /* X = 0xFFFFFFFF, Y = 0x00000000, C = 1. */
++ c = _subborrow_u32 (c, y, x, &x);
++ /* X = 0xFFFFFFFF, Y = 0xFFFFFFFF, C = 1. */
++
++ if (x != sum_ref)
++ __builtin_abort ();
++
++ return 0;
++}
Index: gcc/testsuite/gcc.target/i386/pr81015.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/i386/pr81015.c (.../tags/gcc_7_1_0_release)
@@ -5919,6 +11212,107 @@ Index: gcc/testsuite/gcc.target/i386/pr81015.c
+ if (res != 31)
+ abort ();
+}
+Index: gcc/testsuite/gcc.target/i386/pr80569.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr80569.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr80569.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,9 @@
++/* PR target/80569 */
++/* { dg-do assemble } */
++/* { dg-options "-O2 -m16 -march=haswell" } */
++
++void load_kernel(void *setup_addr)
++{
++ unsigned int seg = (unsigned int)setup_addr >> 4;
++ asm("movl %0, %%es" : : "r"(seg));
++}
+Index: gcc/testsuite/gcc.target/i386/getround.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/getround.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/getround.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-options "-O -msse" } */
++
++#include <xmmintrin.h>
++
++unsigned save;
++
++void f(unsigned mode){
++ unsigned tmp = _MM_GET_ROUNDING_MODE();
++ _MM_SET_ROUNDING_MODE(mode);
++ save = tmp;
++}
++
++/* { dg-final { scan-assembler-times "stmxcsr" 1 } } */
+Index: gcc/testsuite/gcc.target/i386/pr81294-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr81294-2.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr81294-2.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,28 @@
++/* PR target/81294 */
++/* { dg-do run { target { ! ia32 } } } */
++/* { dg-options "-O2" } */
++
++#include <x86intrin.h>
++
++int main ()
++{
++ volatile unsigned char c;
++ unsigned long long x;
++ volatile unsigned long long y, sum_ref;
++
++ c = 0;
++ x = 1LL;
++ y = 0LL;
++ sum_ref = 0x0LL;
++
++ /* X = 0x0000000000000001, Y = 0x0000000000000000, C = 0. */
++ c = _subborrow_u64 (c, y, x, &x);
++ /* X = 0xFFFFFFFFFFFFFFFF, Y = 0x0000000000000000, C = 1. */
++ c = _subborrow_u64 (c, y, x, &x);
++ /* X = 0x0000000000000000, Y = 0x0000000000000000, C = 1. */
++
++ if (x != sum_ref)
++ __builtin_abort ();
++
++ return 0;
++}
+Index: gcc/testsuite/gcc.target/i386/pr81300.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr81300.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr81300.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,30 @@
++/* PR target/81300 */
++/* { dg-do run { target { ! ia32 } } } */
++/* { dg-options "-O2" } */
++
++int
++__attribute__((noinline, noclone))
++foo (void)
++{
++ unsigned long long _discard = 0, zero = 0, maxull = 0;
++ unsigned char zero1 = __builtin_ia32_addcarryx_u64 (0, 0, 0, &_discard);
++ unsigned char zero2 = __builtin_ia32_addcarryx_u64 (zero1, 0, 0, &zero);
++ __builtin_ia32_sbb_u64 (0x0, 2, -1, &_discard);
++ unsigned char one = __builtin_ia32_sbb_u64 (0, zero, 1, &maxull);
++ unsigned long long x = __builtin_ia32_sbb_u64 (one, zero2, 0, &_discard);
++
++ unsigned long long z1 = 0;
++ __asm__ ("mov{q}\t{%1, %0|%0, %1}" : "+r" (z1) : "r" (x));
++ unsigned long long z2 = 3;
++ __asm__ ("mov{q}\t{%1, %0|%0, %1}" : "+r" (z2) : "r" (x));
++
++ return 1 - (z1 | z2);
++}
++
++int main ()
++{
++ if (foo ())
++ __builtin_abort ();
++
++ return 0;
++}
Index: gcc/testsuite/gcc.target/i386/pr59874-1.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/i386/pr59874-1.c (.../tags/gcc_7_1_0_release)
@@ -5930,6 +11324,22 @@ Index: gcc/testsuite/gcc.target/i386/pr59874-1.c
- return x ? __builtin_ctz (x) : 16U;
+ return x ? __builtin_ctzs (x) : 16U;
}
+Index: gcc/testsuite/gcc.target/i386/adx-addcarryx32-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/adx-addcarryx32-2.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/adx-addcarryx32-2.c (.../branches/gcc-7-branch)
+@@ -44,9 +44,9 @@
+ sum_ref = 0x0;
+
+ /* X = 0x00000001, Y = 0x00000000, C = 0. */
+- c = _subborrow_u32 (c, x, y, &x);
++ c = _subborrow_u32 (c, y, x, &x);
+ /* X = 0xFFFFFFFF, Y = 0x00000000, C = 1. */
+- c = _subborrow_u32 (c, x, y, &x);
++ c = _subborrow_u32 (c, y, x, &x);
+ /* X = 0xFFFFFFFF, Y = 0xFFFFFFFF, C = 1. */
+
+ if (x != sum_ref)
Index: gcc/testsuite/gcc.target/i386/pr59874-2.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/i386/pr59874-2.c (.../tags/gcc_7_1_0_release)
@@ -5941,6 +11351,19 @@ Index: gcc/testsuite/gcc.target/i386/pr59874-2.c
- return x ? __builtin_clz (x) : 16U;
+ return x ? __builtin_clzs (x) : 16U;
}
+Index: gcc/testsuite/gcc.target/i386/pr81375.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/i386/pr81375.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.target/i386/pr81375.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,8 @@
++/* PR target/81375 */
++/* { dg-do compile { target ia32 } } */
++/* { dg-options "-mno-80387 -mno-sse -mfpmath=sse" } */
++
++float foo (float a, float b)
++{
++ return a / b;
++}
Index: gcc/testsuite/gfortran.dg/gomp/pr80918.f90
===================================================================
--- a/src/gcc/testsuite/gfortran.dg/gomp/pr80918.f90 (.../tags/gcc_7_1_0_release)
@@ -6106,6 +11529,34 @@ Index: gcc/testsuite/gfortran.dg/namelist_92.f90
+ WRITE (*, nml) ! { dg-error "has ALLOCATABLE or POINTER components and thus requires a defined input/output" }
+ READ (*, nml) ! { dg-error "has ALLOCATABLE or POINTER components and thus requires a defined input/output" }
+END PROGRAM p
+Index: gcc/testsuite/gfortran.dg/pr81175.f
+===================================================================
+--- a/src/gcc/testsuite/gfortran.dg/pr81175.f (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gfortran.dg/pr81175.f (.../branches/gcc-7-branch)
+@@ -0,0 +1,23 @@
++! { dg-do compile }
++! { dg-options "-Ofast -fwrapv" }
++! { dg-additional-options "-march=broadwell" { target x86_64-*-* i?86-*-* } }
++ SUBROUTINE ECPDRA(IC4C,FP,FQ,G)
++ IMPLICIT DOUBLE PRECISION (A-H,O-Z)
++ DIMENSION FP(*),FQ(*),G(*)
++ DIMENSION CKLU(23,12,12)
++!
++ DO 240 I=IAMIN,IAMAX
++ DO 240 J=JAMIN,MMAX
++ DO 230 K=1,NPNP
++ DO 230 L=1,K
++ DO 230 MU=1,2*L-1
++ CKLTEM= CKLU(MU,L,K)
++ IF(IC4C.LE.0) THEN
++ IF(ABS(CKLTEM).GT.TOL) SUM= SUM+FP(N)*CKLTEM
++ ELSE
++ IF(ABS(CKLTEM).GT.TOL) SUM= SUM+FQ(N)*CKLTEM
++ END IF
++ 230 N= N+1
++ G(NN)= G(NN)+DUMJ*SUM
++ 240 NN= NN+1
++ END
Index: gcc/testsuite/gfortran.dg/proc_ptr_comp_49.f90
===================================================================
--- a/src/gcc/testsuite/gfortran.dg/proc_ptr_comp_49.f90 (.../tags/gcc_7_1_0_release)
@@ -6467,6 +11918,63 @@ Index: gcc/testsuite/gfortran.dg/matmul_16.f90
+ call abort
+ end if
+end program bogus_matmul
+Index: gcc/testsuite/gcc.c-torture/execute/pr81555.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.c-torture/execute/pr81555.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.c-torture/execute/pr81555.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,24 @@
++/* PR tree-optimization/81555 */
++
++unsigned int a = 1, d = 0xfaeU, e = 0xe376U;
++_Bool b = 0, f = 1;
++unsigned char g = 1;
++
++void
++foo (void)
++{
++ _Bool c = a != b;
++ if (c)
++ f = 0;
++ if (e & c & (unsigned char)d & c)
++ g = 0;
++}
++
++int
++main ()
++{
++ foo ();
++ if (f || g != 1)
++ __builtin_abort ();
++ return 0;
++}
+Index: gcc/testsuite/gcc.c-torture/execute/pr81556.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.c-torture/execute/pr81556.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.c-torture/execute/pr81556.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,23 @@
++/* PR tree-optimization/81556 */
++
++unsigned long long int b = 0xb82ff73c5c020599ULL;
++unsigned long long int c = 0xd4e8188733a29d8eULL;
++unsigned long long int d = 2, f = 1, g = 0, h = 0;
++unsigned long long int e = 0xf27771784749f32bULL;
++
++__attribute__((noinline, noclone)) void
++foo (void)
++{
++ _Bool a = d > 1;
++ g = f % ((d > 1) << 9);
++ h = a & (e & (a & b & c));
++}
++
++int
++main ()
++{
++ foo ();
++ if (g != 1 || h != 0)
++ __builtin_abort ();
++ return 0;
++}
Index: gcc/testsuite/gcc.c-torture/execute/pr80692.c
===================================================================
--- a/src/gcc/testsuite/gcc.c-torture/execute/pr80692.c (.../tags/gcc_7_1_0_release)
@@ -6503,6 +12011,46 @@ Index: gcc/testsuite/gcc.c-torture/compile/pr81207.c
+ return 1;
+ return 0;
+}
+Index: gcc/testsuite/gnat.dg/opt65.adb
+===================================================================
+--- a/src/gcc/testsuite/gnat.dg/opt65.adb (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gnat.dg/opt65.adb (.../branches/gcc-7-branch)
+@@ -0,0 +1,30 @@
++-- { dg-do run }
++-- { dg-options "-O2" }
++
++with Ada.Command_Line; use Ada.Command_Line;
++
++procedure Opt65 is
++
++ procedure Check_Version_And_Help (Version_String : String) is
++ Help_Switch_Present : Boolean := False;
++ Next_Arg : Natural := 1;
++ begin
++ while Next_Arg <= Argument_Count loop
++ declare
++ Next_Argv : constant String := Argument (Next_Arg);
++ begin
++ if Next_Argv = "--help" then
++ Help_Switch_Present := True;
++ end if;
++ Next_Arg := Next_Arg + 1;
++ end;
++ end loop;
++
++ if Help_Switch_Present then
++ raise Program_Error;
++ end if;
++ end;
++
++begin
++ Check_Version_And_Help ("version");
++end;
+
+Property changes on: gcc/testsuite/gnat.dg/opt65.adb
+___________________________________________________________________
+Added: svn:mergeinfo
+## -0,0 +0,0 ##
Index: gcc/testsuite/gnat.dg/specs/not_null1.ads
===================================================================
--- a/src/gcc/testsuite/gnat.dg/specs/not_null1.ads (.../tags/gcc_7_1_0_release)
@@ -6534,6 +12082,50 @@ Index: gcc/testsuite/gcc.dg/pr80468.c
+ __attribute__ ((__vector_size__ (4 * sizeof (unsigned)))) __int128 b; /* { dg-error "is not supported on this target" } */
+ 0 != b;
+}
+Index: gcc/testsuite/gcc.dg/ubsan/pr81162.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/ubsan/pr81162.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.dg/ubsan/pr81162.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,17 @@
++/* PR tree-optimization/81162 */
++/* { dg-do run } */
++/* { dg-options "-fsanitize=undefined -O2" } */
++
++short s;
++int i1 = 1;
++int i2 = 1;
++unsigned char uc = 147;
++
++int main() {
++ s = (-uc + 2147483647) << 0;
++ if (9031239389974324562ULL >= (-((i1 && i2) + uc) ^ -21096) ) {
++ return 0;
++ } else {
++ return -1;
++ }
++}
+Index: gcc/testsuite/gcc.dg/ubsan/pr81505.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/ubsan/pr81505.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.dg/ubsan/pr81505.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,17 @@
++/* { dg-do compile } */
++/* { dg-options "-O3 -fsanitize=signed-integer-overflow" } */
++
++int a, b, c, h;
++
++int i[5][5];
++
++void
++fn1 ()
++{
++ int l = 0;
++
++ for (a = 0; a <= 3; a++)
++ for (b = 1; b >= 0; b -= 1)
++ l |= i[0][b];
++ c = l;
++}
Index: gcc/testsuite/gcc.dg/asan/use-after-scope-switch-4.c
===================================================================
--- a/src/gcc/testsuite/gcc.dg/asan/use-after-scope-switch-4.c (.../tags/gcc_7_1_0_release)
@@ -6574,6 +12166,45 @@ Index: gcc/testsuite/gcc.dg/asan/use-after-scope-switch-4.c
+}
+
+/* { dg-final { scan-tree-dump-times "ASAN_MARK \\(UNPOISON, &resxxx, \[0-9\]\\);" 2 "gimple" } } */
+Index: gcc/testsuite/gcc.dg/asan/pr81224.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/asan/pr81224.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.dg/asan/pr81224.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,11 @@
++/* PR sanitizer/80659 */
++/* { dg-do compile { target { i?86-*-* x86_64-*-* } } } */
++/* { dg-additional-options "-msse2" } */
++
++int a;
++int
++b ()
++{
++ register __attribute__ ((__vector_size__ (4 * sizeof (int)))) int c asm("xmm0");
++ return c[a];
++}
+Index: gcc/testsuite/gcc.dg/asan/pr81186.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/asan/pr81186.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.dg/asan/pr81186.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,18 @@
++/* PR sanitizer/81186 */
++/* { dg-do run } */
++
++int
++main ()
++{
++ __label__ l;
++ void f ()
++ {
++ int a[123];
++
++ goto l;
++ }
++
++ f ();
++l:
++ return 0;
++}
Index: gcc/testsuite/gcc.dg/asan/pr80659.c
===================================================================
--- a/src/gcc/testsuite/gcc.dg/asan/pr80659.c (.../tags/gcc_7_1_0_release)
@@ -6592,6 +12223,20 @@ Index: gcc/testsuite/gcc.dg/asan/pr80659.c
+ int h;
+ }
+}
+Index: gcc/testsuite/gcc.dg/fixed-point/pr81428.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/fixed-point/pr81428.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.dg/fixed-point/pr81428.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,9 @@
++/* PR tree-optimization/81428 */
++/* { dg-do compile } */
++/* { dg-options "-O2" } */
++
++void
++foo (long _Fract *a, long _Fract *b)
++{
++ *b = *a / *a;
++}
Index: gcc/testsuite/gcc.dg/graphite/pr80906.c
===================================================================
--- a/src/gcc/testsuite/gcc.dg/graphite/pr80906.c (.../tags/gcc_7_1_0_release)
@@ -6625,6 +12270,33 @@ Index: gcc/testsuite/gcc.dg/graphite/pr80906.c
+}
+
+/* { dg-final { scan-tree-dump "isl AST to Gimple succeeded" "graphite" } } */
+Index: gcc/testsuite/gcc.dg/pr81192.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/pr81192.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.dg/pr81192.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,22 @@
++/* { dg-options "-Os -fdump-tree-pre-details" } */
++
++unsigned a;
++int b, c;
++
++static int
++fn1 (int p1, int p2)
++{
++ return p1 > 2147483647 - p2 ? p1 : p1 + p2;
++}
++
++void
++fn2 (void)
++{
++ int j;
++ a = 30;
++ for (; a;)
++ for (; c; b = fn1 (j, 1))
++ ;
++}
++
++/* { dg-final { scan-tree-dump-times "(?n)find_duplicates: <bb .*> duplicate of <bb .*>" 1 "pre" } } */
Index: gcc/testsuite/gcc.dg/pr80903.c
===================================================================
--- a/src/gcc/testsuite/gcc.dg/pr80903.c (.../tags/gcc_7_1_0_release)
@@ -6664,6 +12336,39 @@ Index: gcc/testsuite/gcc.dg/pr80903.c
+
+ goto lab;
+}
+Index: gcc/testsuite/gcc.dg/torture/pr75964.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/torture/pr75964.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.dg/torture/pr75964.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,28 @@
++/* { dg-do run } */
++
++typedef __UINT8_TYPE__ uint8_t;
++
++uint8_t __attribute__ ((noinline, noclone))
++abs8 (uint8_t x)
++{
++ if (x & 0x80)
++ x = -x;
++
++ if (x & 0x80)
++ x = 0x7f;
++
++ return x;
++}
++
++int
++main (void)
++{
++ if (abs8 (0) != 0
++ || abs8 (1) != 1
++ || abs8 (127) != 127
++ || abs8 (128) != 127
++ || abs8 (129) != 127
++ || abs8 (255) != 1)
++ __builtin_abort ();
++ return 0;
++}
Index: gcc/testsuite/gcc.dg/torture/pr80549.c
===================================================================
--- a/src/gcc/testsuite/gcc.dg/torture/pr80549.c (.../tags/gcc_7_1_0_release)
@@ -6815,6 +12520,44 @@ Index: gcc/testsuite/gcc.dg/torture/pr80842.c
+ if (d & (b %= *h) < f * d / (d -= 0))
+ goto l1;
+}
+Index: gcc/testsuite/gcc.dg/tree-ssa/pr81388-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/pr81388-1.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/pr81388-1.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fno-strict-overflow -fdump-tree-ivcanon-details" } */
++
++void bar();
++void foo(char *dst)
++{
++ char *const end = dst;
++ do {
++ bar();
++ dst += 2;
++ } while (dst < end);
++}
++
++/* { dg-final { scan-tree-dump " zero if " "ivcanon" } } */
+Index: gcc/testsuite/gcc.dg/tree-ssa/pr81388-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/tree-ssa/pr81388-2.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/pr81388-2.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,14 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -fdump-tree-ivcanon-details" } */
++
++void bar();
++void foo(unsigned dst)
++{
++ unsigned end = dst;
++ do {
++ bar();
++ dst += 2;
++ } while (dst < end);
++}
++
++/* { dg-final { scan-tree-dump " zero if " "ivcanon" } } */
Index: gcc/testsuite/gcc.dg/pr80492.c
===================================================================
--- a/src/gcc/testsuite/gcc.dg/pr80492.c (.../tags/gcc_7_1_0_release)
@@ -6867,6 +12610,48 @@ Index: gcc/testsuite/gcc.dg/ipa/pr48195.c
/* { dg-require-effective-target lto } */
extern void abort(void);
+Index: gcc/testsuite/gcc.dg/vect/pr81410.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/vect/pr81410.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.dg/vect/pr81410.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,37 @@
++/* { dg-do run } */
++/* { dg-require-effective-target vect_long_long } */
++
++#include "tree-vect.h"
++
++long long x[24];
++long long y[16];
++long long z[8];
++
++void __attribute__((noinline)) foo()
++{
++ for (int i = 0; i < 8; ++i)
++ {
++ y[2*i] = x[3*i];
++ y[2*i + 1] = x[3*i + 1];
++ z[i] = 1;
++ }
++}
++
++int main()
++{
++ check_vect ();
++
++ for (int i = 0; i < 24; ++i)
++ {
++ x[i] = i;
++ __asm__ volatile ("" : : : "memory");
++ }
++ foo ();
++ for (int i = 0; i < 8; ++i)
++ if (y[2*i] != 3*i || y[2*i+1] != 3*i + 1)
++ __builtin_abort ();
++
++ return 0;
++}
++
++/* { dg-final { scan-tree-dump "vectorized 1 loops" "vect" } } */
Index: gcc/testsuite/gcc.dg/vect/bb-slp-pr80705.c
===================================================================
--- a/src/gcc/testsuite/gcc.dg/vect/bb-slp-pr80705.c (.../tags/gcc_7_1_0_release)
@@ -6916,6 +12701,26 @@ Index: gcc/testsuite/gcc.dg/vect/bb-slp-pr80705.c
+
+/* { dg-final { scan-tree-dump "base object not addressable" "slp1" } } */
+/* { dg-final { scan-tree-dump-not "MEM\[^\r\n\]*__gcov\[^\r\n\]* = vect_cst" "slp1" } } */
+Index: gcc/testsuite/gcc.dg/pr81455.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.dg/pr81455.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/gcc.dg/pr81455.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,15 @@
++/* { dg-do compile } */
++/* { dg-options "-O -funswitch-loops" } */
++
++void
++jh (unsigned int aw, int sn)
++{
++ int xs;
++
++ for (xs = 0; xs < 1; ++xs)
++ aw &= 1;
++
++ while (aw < 1 || ++sn < 1)
++ {
++ }
++}
Index: gcc/testsuite/gcc.dg/format/pr80919.c
===================================================================
--- a/src/gcc/testsuite/gcc.dg/format/pr80919.c (.../tags/gcc_7_1_0_release)
@@ -6941,7 +12746,265 @@ Index: gcc/testsuite/ChangeLog
===================================================================
--- a/src/gcc/testsuite/ChangeLog (.../tags/gcc_7_1_0_release)
+++ b/src/gcc/testsuite/ChangeLog (.../branches/gcc-7-branch)
-@@ -1,3 +1,432 @@
+@@ -1,3 +1,690 @@
++2017-07-31 Jakub Jelinek <jakub at redhat.com>
++
++ PR sanitizer/81604
++ * c-c++-common/ubsan/pr81604.c: New test.
++
++2017-07-28 Peter Bergner <bergner at vnet.ibm.com>
++
++ Backport from mainline
++ 2017-07-28 Peter Bergner <bergner at vnet.ibm.com>
++
++ * gcc.target/powerpc/cpu-builtin-1.c (darn, scv): Add tests.
++
++2017-07-28 Bin Cheng <bin.cheng at arm.com>
++
++ Backport from mainline r250496
++ 2017-07-25 Kyrylo Tkachov <kyrylo.tkachov at arm.com>
++
++ PR target/81414
++ * gcc.target/aarch64/pr81414.C: New.
++
++2017-07-27 Andreas Krebbel <krebbel at linux.vnet.ibm.com>
++
++ Backport from mainline
++ 2017-07-27 Andreas Krebbel <krebbel at linux.vnet.ibm.com>
++
++ PR target/81534
++ * gcc.target/s390/pr81534.c: New test.
++
++2017-07-27 Paolo Carlini <paolo.carlini at oracle.com>
++
++ PR c++/71570
++ * g++.dg/cpp0x/lambda/lambda-ice17.C: New.
++
++2017-07-27 Jakub Jelinek <jakub at redhat.com>
++
++ PR tree-optimization/81555
++ PR tree-optimization/81556
++ * gcc.c-torture/execute/pr81555.c: New test.
++ * gcc.c-torture/execute/pr81556.c: New test.
++
++2017-07-27 Martin Liska <mliska at suse.cz>
++
++ Backport from mainline
++ 2017-07-26 Martin Liska <mliska at suse.cz>
++
++ PR sanitize/81186
++ * gcc.dg/asan/pr81186.c: New test.
++
++2017-07-27 Martin Liska <mliska at suse.cz>
++
++ Backport from mainline
++ 2017-06-30 Martin Liska <mliska at suse.cz>
++
++ PR sanitizer/81021
++ * g++.dg/asan/pr81021.C: New test.
++
++2017-07-27 Martin Liska <mliska at suse.cz>
++
++ Backport from mainline
++ 2017-06-28 Martin Liska <mliska at suse.cz>
++
++ PR sanitizer/81224
++ * gcc.dg/asan/pr81224.c: New test.
++
++2017-07-26 Wilco Dijkstra <wdijkstr at arm.com>
++
++ PR target/79041
++ * gcc.target/aarch64/pr79041-2.c: Don't run in ILP32.
++
++2017-07-26 Richard Biener <rguenther at suse.de>
++
++ Backport from mainline
++ 2017-06-18 Richard Biener <rguenther at suse.de>
++
++ PR tree-optimization/81410
++ * gcc.dg/vect/pr81410.c: New testcase.
++
++ 2017-07-25 Richard Biener <rguenther at suse.de>
++
++ PR tree-optimization/81455
++ * gcc.dg/pr81455.c: New testcase.
++
++ 2017-07-25 Richard Biener <rguenther at suse.de>
++
++ PR middle-end/81505
++ * gcc.dg/ubsan/pr81505.c: New testcase.
++
++ 2017-07-04 Jakub Jelinek <jakub at redhat.com>
++
++ PR target/81175
++ * gcc.target/i386/pr69255-2.c (foo): Use the return value of the
++ gather.
++
++ 2017-06-26 Richard Biener <rguenther at suse.de>
++
++ PR target/81175
++ * gfortran.dg/pr81175.f: New testcase.
++
++ 2017-06-21 Marc Glisse <marc.glisse at inria.fr>
++
++ * gcc.dg/tree-ssa/addadd.c: Un-XFAIL.
++ * gcc.dg/tree-ssa/addadd-2.c: New file.
++
++2016-07-25 Bill Schmidt <wschmidt at linux.vnet.ibm.com>
++
++ Backport from mainline
++ 2016-07-14 Bill Schmidt <wschmidt at linux.vnet.ibm.com>
++
++ PR tree-optimization/81162
++ * gcc.dg/ubsan/pr81162.c: New file.
++
++2017-07-25 Wilco Dijkstra <wdijkstr at arm.com>
++
++ PR target/79041
++ * gcc.target/aarch64/pr79041-2.c: New test.
++
++2017-07-25 Georg-Johann Lay <avr at gjlay.de>
++
++ Backport from trunk r247719.
++
++ 2017-05-06 Richard Sandiford <richard.sandiford at linaro.org>
++
++ PR rtl-optimization/75964
++ * gcc.dg/torture/pr75964.c: New test.
++
++2017-07-25 Bin Cheng <bin.cheng at arm.com>
++
++ Backport from 2017-07-20 trunk r250384.
++
++ PR tree-optimization/81388
++ * gcc.dg/tree-ssa/pr81388-1.c: New test.
++ * gcc.dg/tree-ssa/pr81388-2.c: New test.
++
++2017-07-23 Uros Bizjak <ubizjak at gmail.com>
++
++ PR target/80569
++ * gcc.target/i386/pr80569.c: New test.
++
++2017-07-19 Michael Meissner <meissner at linux.vnet.ibm.com>
++
++ Back port from trunk
++ 2017-07-12 Michael Meissner <meissner at linux.vnet.ibm.com>
++
++ PR target/81193
++ * gcc.target/powerpc/cpu-builtin-1.c: Change test to use #ifdef
++ __BUILTIN_CPU_SUPPORTS to see if the GLIBC is new enough that
++ __builtin_cpu_is and __builtin_cpu_supports are supported.
++
++2017-07-18 Uros Bizjak <ubizjak at gmail.com>
++
++ PR target/81471
++ * gcc.target/i386/pr81471.c: New test.
++
++2017-07-17 Jakub Jelinek <jakub at redhat.com>
++
++ PR tree-optimization/81428
++ * gcc.dg/fixed-point/pr81428.c: New test.
++
++ PR tree-optimization/81365
++ * g++.dg/torture/pr81365.C: New test.
++
++ Backported from mainline
++ 2017-07-04 Jakub Jelinek <jakub at redhat.com>
++
++ PR c++/81258
++ * g++.dg/cpp1z/decomp21.C (foo): Adjust expected diagnostics.
++ * g++.dg/cpp1z/decomp30.C: New test.
++
++ 2017-06-30 Jakub Jelinek <jakub at redhat.com>
++
++ PR target/81225
++ * gcc.target/i386/pr81225.c: New test.
++
++2017-07-16 Eric Botcazou <ebotcazou at adacore.com>
++
++ * gnat.dg/opt65.adb: New test.
++
++2017-07-10 Uros Bizjak <ubizjak at gmail.com>
++
++ PR target/81375
++ * gcc.target/i386/pr81375.c: New test.
++
++2017-07-07 Michael Meissner <meissner at linux.vnet.ibm.com>
++
++ Backport from mainline
++ 2017-07-07 Michael Meissner <meissner at linux.vnet.ibm.com>
++
++ PR target/81348
++ * gcc.target/powerpc/pr81348.c: New test.
++
++2017-07-07 Jose E. Marchesi <jose.marchesi at oracle.com>
++
++ * gcc.target/sparc/dictunpack.c: New file.
++ * gcc.target/sparc/fpcmpdeshl.c: Likewise.
++ * gcc.target/sparc/fpcmpshl.c: Likewise.
++ * gcc.target/sparc/fpcmpurshl.c: Likewise.
++ * gcc.target/sparc/fpcmpushl.c: Likewise.
++
++2017-07-05 Georg-Johann Lay <avr at gjlay.de>
++
++ Backport from 2017-07-05 trunk r249995, r249996.
++
++ PR target/81305
++ * gcc.target/avr/isr-test.h: New file.
++ * gcc.target/avr/torture/isr-01-simple.c: New test.
++ * gcc.target/avr/torture/isr-02-call.c: New test.
++ * gcc.target/avr/torture/isr-03-fixed.c: New test.
++
++2017-07-04 Uros Bizjak <ubizjak at gmail.com>
++
++ PR target/81300
++ * gcc.target/i386/pr81300.c: New test.
++
++2017-07-04 Uros Bizjak <ubizjak at gmail.com>
++
++ PR target/81294
++ * gcc.target/i386/adx-addcarryx32-2.c (adx_test): Swap
++ x and y arguments in the call to _subborrow_u32.
++ * gcc.target/i386/adx-addcarryx64-2.c (adx_test): Swap
++ x and y arguments in the call to _subborrow_u64.
++ * gcc.target/i386/pr81294-1.c: New test.
++ * gcc.target/i386/pr81294-2.c: Ditto.
++
++2017-07-03 Tom de Vries <tom at codesourcery.com>
++
++ backport from mainline:
++ PR tree-optimization/81192
++ 2017-07-03 Tom de Vries <tom at codesourcery.com>
++
++ * gcc.dg/pr81192.c: New test.
++
++2017-06-29 Michael Meissner <meissner at linux.vnet.ibm.com>
++
++ Backport from mainline
++ 2017-06-23 Michael Meissner <meissner at linux.vnet.ibm.com>
++
++ PR target/80510
++ * gcc.target/powerpc/pr80510-1.c: Allow test to run on 32-bit.
++ * gcc.target/powerpc/pr80510-2.c: Likewise.
++
++ Backport from mainline
++ 2017-06-20 Michael Meissner <meissner at linux.vnet.ibm.com>
++
++ PR target/79799
++ * gcc.target/powerpc/pr79799-1.c: New test.
++ * gcc.target/powerpc/pr79799-2.c: Likewise.
++ * gcc.target/powerpc/pr79799-3.c: Likewise.
++ * gcc.target/powerpc/pr79799-4.c: Likewise.
++ * gcc.target/powerpc/pr79799-5.c: Likewise.
++
++2017-06-29 Richard Biener <rguenther at suse.de>
++
++ Backport from mainline
++ 2017-06-19 Richard Biener <rguenther at suse.de>
++
++ PR ipa/81112
++ * g++.dg/torture/pr81112.C: New testcase.
++
+2017-06-28 Richard Biener <rguenther at suse.de>
+
+ Backport from mainline
@@ -7374,7 +13437,7 @@ Index: gcc/testsuite/ChangeLog
2017-05-02 Release Manager
* GCC 7.1.0 released.
-@@ -52,8 +481,8 @@
+@@ -52,8 +739,8 @@
Backport from mainline
2017-04-25 Andreas Krebbel <krebbel at linux.vnet.ibm.com>
@@ -7385,7 +13448,7 @@ Index: gcc/testsuite/ChangeLog
2017-04-25 Andreas Krebbel <krebbel at linux.vnet.ibm.com>
-@@ -60,8 +489,8 @@
+@@ -60,8 +747,8 @@
Backport from mainline
2017-04-25 Andreas Krebbel <krebbel at linux.vnet.ibm.com>
@@ -7396,7 +13459,7 @@ Index: gcc/testsuite/ChangeLog
2017-04-25 Dominik Vogt <vogt at linux.vnet.ibm.com>
-@@ -68,10 +497,10 @@
+@@ -68,10 +755,10 @@
Backport from maineline
2017-04-25 Dominik Vogt <vogt at linux.vnet.ibm.com>
@@ -7411,7 +13474,7 @@ Index: gcc/testsuite/ChangeLog
2017-04-25 Jakub Jelinek <jakub at redhat.com>
-@@ -132,7 +561,7 @@
+@@ -132,7 +819,7 @@
* gcc.dg/torture/pr80341.c: Require int32plus.
2017-04-19 Eric Botcazou <ebotcazou at adacore.com>
@@ -7579,6 +13642,14 @@ Index: gcc/testsuite/g++.dg/ubsan/pr81125.C
+{
+ long b = a % c;
+}
+Index: gcc/testsuite/g++.dg/parse/template-keyword1.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/parse/template-keyword1.C (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/g++.dg/parse/template-keyword1.C (.../branches/gcc-7-branch)
+@@ -0,0 +1,3 @@
++// PR c++/81257
++
++template < typename ::template A < int > >; // { dg-error "" }
Index: gcc/testsuite/g++.dg/parse/template28.C
===================================================================
--- a/src/gcc/testsuite/g++.dg/parse/template28.C (.../tags/gcc_7_1_0_release)
@@ -7594,6 +13665,37 @@ Index: gcc/testsuite/g++.dg/parse/template28.C
+{
+ foo(A<int>()); // { dg-error "" }
+}
+Index: gcc/testsuite/g++.dg/cpp0x/variadic-mem_fn2.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp0x/variadic-mem_fn2.C (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp0x/variadic-mem_fn2.C (.../branches/gcc-7-branch)
+@@ -0,0 +1,9 @@
++// { dg-do compile { target c++11 } }
++
++template <class A0, class... As> struct tuple
++{
++ tuple<As...> tail;
++ template <int Offset, class... More> int apply(const More&... more) {
++ return tail.apply<1>(more...); // { dg-error "" } needs .template
++ }
++};
+Index: gcc/testsuite/g++.dg/cpp0x/lambda/lambda-ice17.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-ice17.C (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-ice17.C (.../branches/gcc-7-branch)
+@@ -0,0 +1,12 @@
++// PR c++/71570
++// { dg-do compile { target c++11 } }
++
++void foo (int);
++
++void foo (void)
++{
++ [&foo] // { dg-error "cannot capture" }
++ {
++ foo (0);
++ };
++}
Index: gcc/testsuite/g++.dg/cpp0x/constexpr-diag3.C
===================================================================
--- a/src/gcc/testsuite/g++.dg/cpp0x/constexpr-diag3.C (.../tags/gcc_7_1_0_release)
@@ -7616,6 +13718,38 @@ Index: gcc/testsuite/g++.dg/cpp0x/constexpr-diag3.C
// --------------------
+Index: gcc/testsuite/g++.dg/cpp0x/variadic-ttp8.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp0x/variadic-ttp8.C (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp0x/variadic-ttp8.C (.../branches/gcc-7-branch)
+@@ -0,0 +1,27 @@
++// PR c++/69111
++// { dg-do compile { target c++11 } }
++
++template <template <typename> class ...>
++struct template_list {};
++
++template <typename T>
++struct A
++{};
++
++template <typename>
++struct B
++{
++ template <typename T>
++ using type = A<T>;
++};
++
++template <typename ... Types>
++struct C
++{
++ using type = template_list<B<Types>::template type...>;
++};
++
++int main()
++{
++ return 0;
++}
Index: gcc/testsuite/g++.dg/cpp0x/constexpr-data1.C
===================================================================
--- a/src/gcc/testsuite/g++.dg/cpp0x/constexpr-data1.C (.../tags/gcc_7_1_0_release)
@@ -7629,6 +13763,18 @@ Index: gcc/testsuite/g++.dg/cpp0x/constexpr-data1.C
private:
bool flag;
};
+Index: gcc/testsuite/g++.dg/cpp0x/inh-ctor28.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp0x/inh-ctor28.C (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp0x/inh-ctor28.C (.../branches/gcc-7-branch)
+@@ -0,0 +1,7 @@
++// PR c++/81164
++// { dg-do compile { target c++11 } }
++
++struct A {};
++struct B : virtual A {};
++struct C : virtual A {};
++struct D : B,C { using A::A; }; // { dg-error "indirect" }
Index: gcc/testsuite/g++.dg/cpp0x/constexpr-base5.C
===================================================================
--- a/src/gcc/testsuite/g++.dg/cpp0x/constexpr-base5.C (.../tags/gcc_7_1_0_release)
@@ -7662,6 +13808,33 @@ Index: gcc/testsuite/g++.dg/cpp0x/constexpr-neg1.C
private:
bool flag;
};
+Index: gcc/testsuite/g++.dg/cpp0x/variadic-partial1.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp0x/variadic-partial1.C (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp0x/variadic-partial1.C (.../branches/gcc-7-branch)
+@@ -0,0 +1,22 @@
++// PR c++/72801
++// { dg-do compile { target c++11 } }
++
++template < typename, typename > struct A {};
++
++template < typename ... T > struct B
++{
++ template < typename > struct C
++ {
++ static const int a = 0;
++ };
++
++ template < typename R, typename ... S >
++ struct C < R (A < T, S > ...) >
++ {
++ static const int a = 1;
++ };
++};
++
++#define SA(X) static_assert ((X), #X)
++SA(B <>::C<int()>::a == 1);
++
Index: gcc/testsuite/g++.dg/cpp0x/variadic-ttp7.C
===================================================================
--- a/src/gcc/testsuite/g++.dg/cpp0x/variadic-ttp7.C (.../tags/gcc_7_1_0_release)
@@ -7701,6 +13874,24 @@ Index: gcc/testsuite/g++.dg/cpp0x/inh-ctor27.C
+};
+
+derived d(0);
+Index: gcc/testsuite/g++.dg/cpp0x/decltype-call4.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp0x/decltype-call4.C (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp0x/decltype-call4.C (.../branches/gcc-7-branch)
+@@ -0,0 +1,13 @@
++// PR c++/81188
++// { dg-do compile { target c++11 } }
++
++template <class F>
++struct C {
++ F fast(long i) const;
++ auto operator[](long i) const -> decltype(this->fast(i));
++};
++
++template <class F>
++auto C<F>::operator[](long i) const -> decltype(this->fast(i)) {
++ return fast(i);
++}
Index: gcc/testsuite/g++.dg/cpp0x/constexpr-memfn1.C
===================================================================
--- a/src/gcc/testsuite/g++.dg/cpp0x/constexpr-memfn1.C (.../tags/gcc_7_1_0_release)
@@ -7735,6 +13926,123 @@ Index: gcc/testsuite/g++.dg/cpp0x/constexpr-diag1.C
template <class T>
constexpr int f (T t) { return 42; } // { dg-error "parameter" }
+Index: gcc/testsuite/g++.dg/torture/pr81365.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/torture/pr81365.C (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/g++.dg/torture/pr81365.C (.../branches/gcc-7-branch)
+@@ -0,0 +1,39 @@
++// PR tree-optimization/81365
++// { dg-do run }
++
++struct A { unsigned a; };
++
++struct B {
++ B (const A *x)
++ {
++ __builtin_memcpy (b, x, 3 * sizeof (A));
++ __builtin_memcpy (c, x + 3, sizeof (A));
++ __builtin_memset (c + 1, 0, sizeof (A));
++ }
++ bool
++ foo (unsigned x)
++ {
++ A *it = c;
++ if (it->a == x || (++it)->a == x)
++ {
++ A t(b[0]);
++ b[0] = *it;
++ *it = t;
++ return true;
++ }
++ return false;
++ }
++ A b[3];
++ A c[2];
++};
++
++int
++main ()
++{
++ A x[] = { 4, 8, 12, 18 };
++ B y(x);
++ if (!y.foo (18))
++ __builtin_abort ();
++ if (!y.foo (4))
++ __builtin_abort ();
++}
+Index: gcc/testsuite/g++.dg/torture/pr81112.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/torture/pr81112.C (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/g++.dg/torture/pr81112.C (.../branches/gcc-7-branch)
+@@ -0,0 +1,68 @@
++// { dg-do compile }
++// { dg-additional-options "-Wno-psabi" }
++
++class AssertionResult {
++ bool success_;
++};
++
++AssertionResult AssertionSuccess();
++
++template <typename T1>
++AssertionResult EXPECT_EQ(const T1& expected, const T1& actual) {
++ if (expected == actual) {
++ return AssertionSuccess();
++ }
++ return AssertionSuccess();
++}
++
++struct uuid
++{
++ unsigned char data[16];
++};
++
++bool operator== (uuid const& lhs, uuid const& rhs);
++
++typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
++typedef int __v4si __attribute__ ((__vector_size__ (16)));
++typedef char __v16qi __attribute__ ((__vector_size__ (16)));
++typedef long long __m128i_u __attribute__ ((__vector_size__ (16), __may_alias__, __aligned__ (1)));
++
++int foo (__v16qi);
++
++extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
++ _mm_loadu_si128 (__m128i_u const *__P)
++{
++ return *__P;
++}
++extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
++ _mm_cmpeq_epi32 (__m128i __A, __m128i __B)
++{
++ return (__m128i) ((__v4si)__A == (__v4si)__B);
++}
++extern __inline int __attribute__((__gnu_inline__, __always_inline__, __artificial__))
++ _mm_movemask_epi8 (__m128i __A)
++{
++ return foo ((__v16qi)__A);
++}
++
++
++__m128i load_unaligned_si128(const unsigned char* p)
++{
++ return _mm_loadu_si128(reinterpret_cast< const __m128i* >(p));
++}
++
++inline bool operator== (uuid const& lhs, uuid const& rhs)
++{
++ __m128i mm_left = load_unaligned_si128(lhs.data);
++ __m128i mm_right = load_unaligned_si128(rhs.data);
++
++ __m128i mm_cmp = _mm_cmpeq_epi32(mm_left, mm_right);
++
++ return _mm_movemask_epi8(mm_cmp) == 0xFFFF;
++}
++
++void crash_gcc7()
++{
++ static const uuid u = uuid();
++ EXPECT_EQ(u, u);
++}
Index: gcc/testsuite/g++.dg/ipa/pr80212.C
===================================================================
--- a/src/gcc/testsuite/g++.dg/ipa/pr80212.C (.../tags/gcc_7_1_0_release)
@@ -7902,6 +14210,42 @@ Index: gcc/testsuite/g++.dg/cpp1z/constexpr-if12.C
+ }
+ return true;
+}
+Index: gcc/testsuite/g++.dg/cpp1z/class-deduction40.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp1z/class-deduction40.C (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp1z/class-deduction40.C (.../branches/gcc-7-branch)
+@@ -0,0 +1,19 @@
++// PR c++/81180
++// { dg-options -std=c++1z }
++
++template < int I > struct int_{};
++
++template < typename T >
++struct A{
++ template < typename U, int I >
++ struct B{
++ B(U u, int_< I >){}
++ };
++};
++
++
++int main(){
++ A< int >::B v(0, int_< 0 >());
++ (void)v;
++}
++
+Index: gcc/testsuite/g++.dg/cpp1z/decomp21.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp1z/decomp21.C (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp1z/decomp21.C (.../branches/gcc-7-branch)
+@@ -12,5 +12,6 @@
+ auto [ n, o, p ] { a };
+ auto [ q, r, t ] ( s );
+ auto [ u, v, w ] ( s, ); // { dg-error "expected primary-expression before '.' token" }
+- auto [ x, y, z ] ( a ); // { dg-error "expression list treated as compound expression in initializer" "" { target *-*-* } .-1 }
++ // { dg-error "invalid initializer for structured binding declaration" "" { target *-*-* } .-1 }
++ auto [ x, y, z ] ( a );
+ }
Index: gcc/testsuite/g++.dg/cpp1z/noexcept-type17.C
===================================================================
--- a/src/gcc/testsuite/g++.dg/cpp1z/noexcept-type17.C (.../tags/gcc_7_1_0_release)
@@ -7914,6 +14258,23 @@ Index: gcc/testsuite/g++.dg/cpp1z/noexcept-type17.C
+int main() {
+ [](auto a) noexcept(noexcept(foo(a))){}(42);
+}
+Index: gcc/testsuite/g++.dg/cpp1z/decomp30.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/cpp1z/decomp30.C (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/g++.dg/cpp1z/decomp30.C (.../branches/gcc-7-branch)
+@@ -0,0 +1,12 @@
++// PR c++/81258
++// { dg-options -std=c++1z }
++
++int a[2];
++auto [b, c] (a);
++auto [d, e] { a };
++auto [f, g] = a;
++auto [h, i] ( a, a ); // { dg-error "invalid initializer for structured binding declaration" }
++auto [j, k] { a, a }; // { dg-error "invalid initializer for structured binding declaration" }
++auto [l, m] = { a }; // { dg-error "deducing from brace-enclosed initializer list requires" }
++auto [n, o] {}; // { dg-error "invalid initializer for structured binding declaration" }
++auto [p, q] (); // { dg-error "invalid initializer for structured binding declaration" }
Index: gcc/testsuite/g++.dg/ext/flexary24.C
===================================================================
--- a/src/gcc/testsuite/g++.dg/ext/flexary24.C (.../tags/gcc_7_1_0_release)
@@ -8294,6 +14655,44 @@ Index: gcc/testsuite/g++.dg/warn/Wstrict-aliasing-bogus-char-2.C
+{
+ *reinterpret_cast<int*>(&storage) = 42; // { dg-bogus "break strict-aliasing" }
+}
+Index: gcc/testsuite/g++.dg/asan/pr81021.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/asan/pr81021.C (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/g++.dg/asan/pr81021.C (.../branches/gcc-7-branch)
+@@ -0,0 +1,33 @@
++// { dg-do run }
++
++#include <string>
++
++struct ConfigFile {
++ ConfigFile(std::string filename, std::string delimiter) { throw "error"; }
++ ConfigFile(std::string filename) {}
++};
++
++struct Configuration {
++ ConfigFile _configFile;
++
++ Configuration(const std::string &root, const char *baseName)
++ : _configFile(root + baseName, "=") { }
++ Configuration(const std::string &root, const char *a, const char *b)
++ : _configFile(root + a + b) { }
++};
++
++
++void test() {
++ std::string root("etc");
++ try {
++ Configuration config(root, "notthere");
++ }
++ catch (...) {
++ // exception is thrown, caught here and ignored...
++ }
++ Configuration config(root, "a", "b"); // ASAN error during constructor here
++}
++
++int main(int argc, const char *argv[]) {
++ test();
++}
Index: gcc/testsuite/g++.dg/template/ptrmem31.C
===================================================================
--- a/src/gcc/testsuite/g++.dg/template/ptrmem31.C (.../tags/gcc_7_1_0_release)
@@ -8340,6 +14739,22 @@ Index: gcc/testsuite/g++.dg/template/ref10.C
+};
+
+int main() {}
+Index: gcc/testsuite/g++.dg/template/lookup11.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/template/lookup11.C (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/g++.dg/template/lookup11.C (.../branches/gcc-7-branch)
+@@ -0,0 +1,11 @@
++// PR c++/81026
++
++namespace std {
++ template<class> struct extent;
++}
++using namespace std;
++
++template <class T>
++struct S {
++ void f() { T().template extent<42>(); }
++};
Index: gcc/testsuite/g++.dg/template/partial-specialization6.C
===================================================================
--- a/src/gcc/testsuite/g++.dg/template/partial-specialization6.C (.../tags/gcc_7_1_0_release)
@@ -8405,6 +14820,23 @@ Index: gcc/testsuite/g++.dg/template/nontype-array1.C
+ char const s8[] = "hi";
+ Message<s8> m8; // { dg-error "" }
+}
+Index: gcc/testsuite/g++.dg/template/lookup10.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/template/lookup10.C (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/g++.dg/template/lookup10.C (.../branches/gcc-7-branch)
+@@ -0,0 +1,12 @@
++// PR c++/81204
++
++namespace std {
++ template<typename, typename> struct set { };
++}
++using namespace std;
++
++template <int I, typename Result>
++inline void set(Result & res)
++{
++ res.template set<I>();
++}
Index: gcc/testsuite/g++.dg/template/partial5.C
===================================================================
--- a/src/gcc/testsuite/g++.dg/template/partial5.C (.../tags/gcc_7_1_0_release)
@@ -8505,6 +14937,42 @@ Index: gcc/testsuite/g++.dg/template/partial-specialization7.C
+{
+ return 0;
+}
+Index: gcc/testsuite/c-c++-common/ubsan/pr81604.c
+===================================================================
+--- a/src/gcc/testsuite/c-c++-common/ubsan/pr81604.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/testsuite/c-c++-common/ubsan/pr81604.c (.../branches/gcc-7-branch)
+@@ -0,0 +1,31 @@
++/* PR sanitizer/81604 */
++/* { dg-do run } */
++/* { dg-options "-fsanitize=bounds,signed-integer-overflow" } */
++
++long a[10];
++
++__attribute__((noinline, noclone)) long *
++foo (int i)
++{
++ return &a[i];
++}
++
++__attribute__((noinline, noclone)) long
++bar (long x, long y)
++{
++ return x * y;
++}
++
++int
++main ()
++{
++ volatile int i = -1;
++ volatile long l = __LONG_MAX__;
++ long *volatile p;
++ p = foo (i);
++ l = bar (l, l);
++ return 0;
++}
++
++/* { dg-output "index -1 out of bounds for type 'long int \\\[10\\\]'\[^\n\r]*(\n|\r\n|\r)" } */
++/* { dg-output "\[^\n\r]*signed integer overflow: \[0-9]+ \\* \[0-9]+ cannot be represented in type 'long int'" } */
Index: gcc/testsuite/c-c++-common/ubsan/sanitize-recover-7.c
===================================================================
--- a/src/gcc/testsuite/c-c++-common/ubsan/sanitize-recover-7.c (.../tags/gcc_7_1_0_release)
@@ -8720,11 +15188,80 @@ Index: gcc/cp/constexpr.c
{
if (DECL_CONTEXT (x)
&& !DECL_DECLARED_CONSTEXPR_P (DECL_CONTEXT (x)))
+Index: gcc/cp/tree.c
+===================================================================
+--- a/src/gcc/cp/tree.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/cp/tree.c (.../branches/gcc-7-branch)
+@@ -3272,11 +3272,6 @@
+ return false;
+ return cp_tree_equal (TREE_OPERAND (t1, 1), TREE_OPERAND (t1, 1));
+
+- case COMPONENT_REF:
+- if (TREE_OPERAND (t1, 1) != TREE_OPERAND (t2, 1))
+- return false;
+- return cp_tree_equal (TREE_OPERAND (t1, 0), TREE_OPERAND (t2, 0));
+-
+ case PARM_DECL:
+ /* For comparing uses of parameters in late-specified return types
+ with an out-of-class definition of the function, but can also come
Index: gcc/cp/ChangeLog
===================================================================
--- a/src/gcc/cp/ChangeLog (.../tags/gcc_7_1_0_release)
+++ b/src/gcc/cp/ChangeLog (.../branches/gcc-7-branch)
-@@ -1,3 +1,148 @@
+@@ -1,3 +1,201 @@
++2017-07-27 Paolo Carlini <paolo.carlini at oracle.com>
++
++ PR c++/71570
++ * lambda.c (add_capture): Early return if we cannot capture by
++ reference.
++
++2017-07-17 Jakub Jelinek <jakub at redhat.com>
++
++ Backported from mainline
++ 2017-07-04 Jakub Jelinek <jakub at redhat.com>
++
++ PR c++/81258
++ * parser.c (cp_parser_decomposition_declaration): Diagnose invalid
++ forms of structured binding initializers.
++
++2017-07-06 Jason Merrill <jason at redhat.com>
++
++ PR c++/81204 - parse error with dependent template-name
++ * parser.c (cp_parser_lookup_name): Revert previous change.
++
++2017-06-30 Jason Merrill <jason at redhat.com>
++
++ PR c++/54769 - wrong lookup of dependent template-name.
++ PR c++/81257 - ICE with invalid ::template.
++ * parser.c (cp_parser_template_name): Handle dependent object type.
++ (cp_parser_nested_name_specifier_opt): Make template_keyword_p a
++ parameter.
++ (cp_parser_id_expression): Pass it.
++
++2017-06-29 Jason Merrill <jason at redhat.com>
++
++ PR c++/81180 - ICE with C++17 deduction of member class template.
++ * pt.c (build_deduction_guide): Correct member template handling.
++
++ PR c++/81188 - matching decltype of member function call.
++ * tree.c (cp_tree_equal): Remove COMPONENT_REF special case.
++
++ PR c++/81164 - ICE with invalid inherited constructor.
++ * search.c (binfo_direct_p): New.
++ * name-lookup.c (do_class_using_decl): Use it.
++
++2017-06-28 Jason Merrill <jason at redhat.com>
++
++ PR c++/61022 - error with variadic template template parm
++ * pt.c (convert_template_argument): Keep the TYPE_PACK_EXPANSION.
++
++ PR c++/72801 - ICE with variadic partial specialization
++ * pt.c (unify_pack_expansion): Use PACK_EXPANSION_EXTRA_ARGS.
++
++ PR c++/81204 - parse error with dependent template-name
++ * parser.c (cp_parser_lookup_name): Disqualify function templates
++ after lookup.
++
+2017-06-26 Jason Merrill <jason at redhat.com>
+
+ PR c++/81215
@@ -9087,7 +15624,26 @@ Index: gcc/cp/pt.c
return 0;
}
-@@ -20563,18 +20645,6 @@
+@@ -7552,7 +7634,7 @@
+ else if (TREE_CODE (TREE_TYPE (arg)) == UNBOUND_CLASS_TEMPLATE)
+ /* The number of argument required is not known yet.
+ Just accept it for now. */
+- val = TREE_TYPE (arg);
++ val = orig_arg;
+ else
+ {
+ tree parmparm = DECL_INNERMOST_TEMPLATE_PARMS (parm);
+@@ -19954,6 +20036,9 @@
+ tree pack, packs = NULL_TREE;
+ int i, start = TREE_VEC_LENGTH (packed_parms) - 1;
+
++ /* Add in any args remembered from an earlier partial instantiation. */
++ targs = add_to_template_args (PACK_EXPANSION_EXTRA_ARGS (parm), targs);
++
+ packed_args = expand_template_argument_pack (packed_args);
+
+ int len = TREE_VEC_LENGTH (packed_args);
+@@ -20563,18 +20648,6 @@
return x;
}
@@ -9106,7 +15662,7 @@ Index: gcc/cp/pt.c
/* [temp.deduct.type] If, in the declaration of a function template
with a non-type template-parameter, the non-type
template-parameter is used in an expression in the function
-@@ -20595,7 +20665,8 @@
+@@ -20595,7 +20668,8 @@
/* Template-parameter dependent expression. Just accept it for now.
It will later be processed in convert_template_argument. */
;
@@ -9116,7 +15672,7 @@ Index: gcc/cp/pt.c
/* OK */;
else if ((strict & UNIFY_ALLOW_INTEGER)
&& CP_INTEGRAL_TYPE_P (tparm))
-@@ -20604,9 +20675,22 @@
+@@ -20604,9 +20678,22 @@
corresponding parameter. */
arg = fold (build_nop (tparm, arg));
else if (uses_template_parms (tparm))
@@ -9142,7 +15698,7 @@ Index: gcc/cp/pt.c
else
return unify_type_mismatch (explain_p, tparm, TREE_TYPE (arg));
-@@ -21598,10 +21682,12 @@
+@@ -21598,10 +21685,12 @@
`T' is `A' but unify () does not check whether `typename T::X'
is `int'. */
spec_args = tsubst (spec_args, deduced_args, tf_none, NULL_TREE);
@@ -9158,7 +15714,7 @@ Index: gcc/cp/pt.c
pop_tinst_level ();
if (spec_args == error_mark_node
-@@ -23372,6 +23458,14 @@
+@@ -23372,6 +23461,14 @@
arg_type = TREE_CHAIN (arg_type))
if (dependent_type_p (TREE_VALUE (arg_type)))
return true;
@@ -9173,7 +15729,7 @@ Index: gcc/cp/pt.c
return false;
}
/* -- an array type constructed from any dependent type or whose
-@@ -23920,18 +24014,35 @@
+@@ -23920,18 +24017,35 @@
return true;
/* A function or variable template-id is type-dependent if it has any
@@ -9218,7 +15774,7 @@ Index: gcc/cp/pt.c
/* Always dependent, on the number of arguments if nothing else. */
if (TREE_CODE (expression) == EXPR_PACK_EXPANSION)
return true;
-@@ -24697,6 +24808,14 @@
+@@ -24697,6 +24811,14 @@
return t;
}
@@ -9233,6 +15789,50 @@ Index: gcc/cp/pt.c
/* Make a "constrained auto" type-specifier. This is an
auto type with constraints that must be associated after
deduction. The constraint is formed from the given
+@@ -25054,17 +25176,16 @@
+ }
+ else
+ {
++ ++processing_template_decl;
++
++ tree fn_tmpl
++ = (TREE_CODE (ctor) == TEMPLATE_DECL ? ctor
++ : DECL_TI_TEMPLATE (ctor));
+ if (outer_args)
+- ctor = tsubst (ctor, outer_args, complain, ctor);
++ fn_tmpl = tsubst (fn_tmpl, outer_args, complain, ctor);
++ ctor = DECL_TEMPLATE_RESULT (fn_tmpl);
++
+ type = DECL_CONTEXT (ctor);
+- tree fn_tmpl;
+- if (TREE_CODE (ctor) == TEMPLATE_DECL)
+- {
+- fn_tmpl = ctor;
+- ctor = DECL_TEMPLATE_RESULT (fn_tmpl);
+- }
+- else
+- fn_tmpl = DECL_TI_TEMPLATE (ctor);
+
+ tparms = DECL_TEMPLATE_PARMS (fn_tmpl);
+ /* If type is a member class template, DECL_TI_ARGS (ctor) will have
+@@ -25086,7 +25207,6 @@
+ /* For a member template constructor, we need to flatten the two
+ template parameter lists into one, and then adjust the function
+ signature accordingly. This gets...complicated. */
+- ++processing_template_decl;
+ tree save_parms = current_template_parms;
+
+ /* For a member template we should have two levels of parms/args, one
+@@ -25147,8 +25267,8 @@
+ ci = tsubst_constraint_info (ci, tsubst_args, complain, ctor);
+
+ current_template_parms = save_parms;
+- --processing_template_decl;
+ }
++ --processing_template_decl;
+ }
+
+ if (!memtmpl)
Index: gcc/cp/semantics.c
===================================================================
--- a/src/gcc/cp/semantics.c (.../tags/gcc_7_1_0_release)
@@ -9410,6 +16010,15 @@ Index: gcc/cp/parser.c
===================================================================
--- a/src/gcc/cp/parser.c (.../tags/gcc_7_1_0_release)
+++ b/src/gcc/cp/parser.c (.../branches/gcc-7-branch)
+@@ -2039,7 +2039,7 @@
+ static cp_expr cp_parser_unqualified_id
+ (cp_parser *, bool, bool, bool, bool);
+ static tree cp_parser_nested_name_specifier_opt
+- (cp_parser *, bool, bool, bool, bool);
++ (cp_parser *, bool, bool, bool, bool, bool = false);
+ static tree cp_parser_nested_name_specifier
+ (cp_parser *, bool, bool, bool, bool);
+ static tree cp_parser_qualifying_entity
@@ -2983,7 +2983,9 @@
if (cp_lexer_next_token_is (parser->lexer, CPP_LESS))
@@ -9421,7 +16030,60 @@ Index: gcc/cp/parser.c
error_at (location, "%qT is not a template", type);
else if (identifier_p (type))
{
-@@ -9447,10 +9449,14 @@
+@@ -5406,8 +5408,11 @@
+
+ /* Look for the optional `::' operator. */
+ global_scope_p
+- = (cp_parser_global_scope_opt (parser, /*current_scope_valid_p=*/false)
+- != NULL_TREE);
++ = (!template_keyword_p
++ && (cp_parser_global_scope_opt (parser,
++ /*current_scope_valid_p=*/false)
++ != NULL_TREE));
++
+ /* Look for the optional nested-name-specifier. */
+ nested_name_specifier_p
+ = (cp_parser_nested_name_specifier_opt (parser,
+@@ -5414,8 +5419,10 @@
+ /*typename_keyword_p=*/false,
+ check_dependency_p,
+ /*type_p=*/false,
+- declarator_p)
++ declarator_p,
++ template_keyword_p)
+ != NULL_TREE);
++
+ /* If there is a nested-name-specifier, then we are looking at
+ the first qualified-id production. */
+ if (nested_name_specifier_p)
+@@ -5860,7 +5867,8 @@
+ bool typename_keyword_p,
+ bool check_dependency_p,
+ bool type_p,
+- bool is_declaration)
++ bool is_declaration,
++ bool template_keyword_p /* = false */)
+ {
+ bool success = false;
+ cp_token_position start = 0;
+@@ -5878,7 +5886,6 @@
+ tree new_scope;
+ tree old_scope;
+ tree saved_qualifying_scope;
+- bool template_keyword_p;
+
+ /* Spot cases that cannot be the beginning of a
+ nested-name-specifier. */
+@@ -5950,8 +5957,6 @@
+ first time through the loop. */
+ if (success)
+ template_keyword_p = cp_parser_optional_template_keyword (parser);
+- else
+- template_keyword_p = false;
+
+ /* Save the old scope since the name lookup we are about to do
+ might destroy it. */
+@@ -9447,10 +9452,14 @@
/* Require an rvalue constant expression here; that's what our
callers expect. Reference constant expressions are handled
separately in e.g. cp_parser_template_argument. */
@@ -9438,7 +16100,52 @@ Index: gcc/cp/parser.c
}
if (allow_non_constant_p)
*non_constant_p = parser->non_integral_constant_expression_p;
-@@ -16942,7 +16948,7 @@
+@@ -13036,6 +13045,16 @@
+ *init_loc = cp_lexer_peek_token (parser->lexer)->location;
+ tree initializer = cp_parser_initializer (parser, &is_direct_init,
+ &non_constant_p);
++ if (initializer == NULL_TREE
++ || (TREE_CODE (initializer) == TREE_LIST
++ && TREE_CHAIN (initializer))
++ || (TREE_CODE (initializer) == CONSTRUCTOR
++ && CONSTRUCTOR_NELTS (initializer) != 1))
++ {
++ error_at (loc, "invalid initializer for structured binding "
++ "declaration");
++ initializer = error_mark_node;
++ }
+
+ if (decl != error_mark_node)
+ {
+@@ -15710,15 +15729,19 @@
+ no point in doing name-lookup, so we just return IDENTIFIER.
+ But, if the qualifying scope is non-dependent then we can
+ (and must) do name-lookup normally. */
+- if (template_keyword_p
+- && (!parser->scope
+- || (TYPE_P (parser->scope)
+- && dependent_type_p (parser->scope))))
++ if (template_keyword_p)
+ {
+- /* We're optimizing away the call to cp_parser_lookup_name, but we
+- still need to do this. */
+- parser->context->object_type = NULL_TREE;
+- return identifier;
++ tree scope = (parser->scope ? parser->scope
++ : parser->context->object_type);
++ if (scope && TYPE_P (scope)
++ && (!CLASS_TYPE_P (scope)
++ || (check_dependency_p && dependent_type_p (scope))))
++ {
++ /* We're optimizing away the call to cp_parser_lookup_name, but
++ we still need to do this. */
++ parser->context->object_type = NULL_TREE;
++ return identifier;
++ }
+ }
+ }
+
+@@ -16942,7 +16965,7 @@
/* There is no valid C++ program where a non-template type is
followed by a "<". That usually indicates that the user
thought that the type was a template. */
@@ -9447,7 +16154,7 @@ Index: gcc/cp/parser.c
none_type,
token->location);
}
-@@ -23677,7 +23683,7 @@
+@@ -23677,7 +23700,7 @@
if (virtual_p && !duplicate_virtual_error_issued_p)
{
cp_parser_error (parser,
@@ -9456,7 +16163,7 @@ Index: gcc/cp/parser.c
duplicate_virtual_error_issued_p = true;
}
-@@ -23697,7 +23703,7 @@
+@@ -23697,7 +23720,7 @@
&& !duplicate_access_error_issued_p)
{
cp_parser_error (parser,
@@ -9492,7 +16199,19 @@ Index: gcc/cp/lambda.c
===================================================================
--- a/src/gcc/cp/lambda.c (.../tags/gcc_7_1_0_release)
+++ b/src/gcc/cp/lambda.c (.../branches/gcc-7-branch)
-@@ -999,6 +999,8 @@
+@@ -538,7 +538,10 @@
+ else if (id != this_identifier && by_reference_p)
+ {
+ if (!lvalue_p (initializer))
+- error ("cannot capture %qE by reference", initializer);
++ {
++ error ("cannot capture %qE by reference", initializer);
++ return error_mark_node;
++ }
+ }
+ else
+ {
+@@ -999,6 +1002,8 @@
null_pointer_node);
if (generic_lambda_p)
{
@@ -9501,7 +16220,7 @@ Index: gcc/cp/lambda.c
/* Prepare the dependent member call for the static member function
'_FUN' and, potentially, prepare another call to be used in a decltype
return expression for a deduced return call op to allow for simple
-@@ -1048,9 +1050,7 @@
+@@ -1048,9 +1053,7 @@
if (generic_lambda_p)
{
@@ -9511,7 +16230,7 @@ Index: gcc/cp/lambda.c
CALL_EXPR_ARG (call, ix) = a;
if (decltype_call)
-@@ -1074,11 +1074,9 @@
+@@ -1074,11 +1077,9 @@
{
if (decltype_call)
{
@@ -9523,7 +16242,7 @@ Index: gcc/cp/lambda.c
}
}
else
-@@ -1096,6 +1094,9 @@
+@@ -1096,6 +1097,9 @@
&& TYPE_NOTHROW_P (TREE_TYPE (callop)))
stattype = build_exception_variant (stattype, noexcept_true_spec);
@@ -9569,6 +16288,61 @@ Index: gcc/cp/cp-tree.h
extern tree do_auto_deduction (tree, tree, tree);
extern tree do_auto_deduction (tree, tree, tree,
tsubst_flags_t,
+@@ -6344,6 +6344,7 @@
+ extern tree dfs_walk_once (tree, tree (*) (tree, void *),
+ tree (*) (tree, void *), void *);
+ extern tree binfo_via_virtual (tree, tree);
++extern bool binfo_direct_p (tree);
+ extern tree build_baselink (tree, tree, tree, tree);
+ extern tree adjust_result_of_qualified_name_lookup
+ (tree, tree, tree);
+Index: gcc/cp/search.c
+===================================================================
+--- a/src/gcc/cp/search.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/cp/search.c (.../branches/gcc-7-branch)
+@@ -2754,6 +2754,28 @@
+ return NULL_TREE;
+ }
+
++/* BINFO is for a base class in some hierarchy. Return true iff it is a
++ direct base. */
++
++bool
++binfo_direct_p (tree binfo)
++{
++ tree d_binfo = BINFO_INHERITANCE_CHAIN (binfo);
++ if (BINFO_INHERITANCE_CHAIN (d_binfo))
++ /* A second inheritance chain means indirect. */
++ return false;
++ if (!BINFO_VIRTUAL_P (binfo))
++ /* Non-virtual, so only one inheritance chain means direct. */
++ return true;
++ /* A virtual base looks like a direct base, so we need to look through the
++ direct bases to see if it's there. */
++ tree b_binfo;
++ for (int i = 0; BINFO_BASE_ITERATE (d_binfo, i, b_binfo); ++i)
++ if (b_binfo == binfo)
++ return true;
++ return false;
++}
++
+ /* BINFO is a base binfo in the complete type BINFO_TYPE (HERE).
+ Find the equivalent binfo within whatever graph HERE is located.
+ This is the inverse of original_binfo. */
+Index: gcc/cp/name-lookup.c
+===================================================================
+--- a/src/gcc/cp/name-lookup.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/cp/name-lookup.c (.../branches/gcc-7-branch)
+@@ -3453,8 +3453,7 @@
+ return NULL_TREE;
+ }
+ }
+- else if (name == ctor_identifier
+- && BINFO_INHERITANCE_CHAIN (BINFO_INHERITANCE_CHAIN (binfo)))
++ else if (name == ctor_identifier && !binfo_direct_p (binfo))
+ {
+ error ("cannot inherit constructors from indirect base %qT", scope);
+ return NULL_TREE;
Index: gcc/tree-ssa-ccp.c
===================================================================
--- a/src/gcc/tree-ssa-ccp.c (.../tags/gcc_7_1_0_release)
@@ -9599,6 +16373,21 @@ Index: gcc/passes.def
TERMINATE_PASS_LIST (all_lowering_passes)
/* Interprocedural optimization passes. */
+Index: gcc/config.in
+===================================================================
+--- a/src/gcc/config.in (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config.in (.../branches/gcc-7-branch)
+@@ -660,6 +660,10 @@
+ #undef HAVE_AS_SPARC5_VIS4
+ #endif
+
++/* Define if your assembler supports SPARC6 instructions. */
++#ifndef USED_FOR_TARGET
++#undef HAVE_AS_SPARC6
++#endif
+
+ /* Define if your assembler and linker support GOTDATA_OP relocs. */
+ #ifndef USED_FOR_TARGET
Index: gcc/dwarf2out.c
===================================================================
--- a/src/gcc/dwarf2out.c (.../tags/gcc_7_1_0_release)
@@ -9614,7 +16403,37 @@ Index: gcc/dwarf2out.c
/* Round SIZE up to the nearest BOUNDARY. */
#define DWARF_ROUND(SIZE,BOUNDARY) \
((((SIZE) + (BOUNDARY) - 1) / (BOUNDARY)) * (BOUNDARY))
-@@ -29649,6 +29653,7 @@
+@@ -27072,6 +27076,7 @@
+ macinfo_entry *ref;
+ vec<macinfo_entry, va_gc> *files = NULL;
+ macinfo_hash_type *macinfo_htab = NULL;
++ char dl_section_ref[MAX_ARTIFICIAL_LABEL_BYTES];
+
+ if (! length)
+ return;
+@@ -27082,6 +27087,12 @@
+ && (int) DW_MACINFO_start_file == (int) DW_MACRO_start_file
+ && (int) DW_MACINFO_end_file == (int) DW_MACRO_end_file);
+
++ /* AIX Assembler inserts the length, so adjust the reference to match the
++ offset expected by debuggers. */
++ strcpy (dl_section_ref, debug_line_section_label);
++ if (XCOFF_DEBUGGING_INFO)
++ strcat (dl_section_ref, DWARF_INITIAL_LENGTH_SIZE_STR);
++
+ /* For .debug_macro emit the section header. */
+ if (!dwarf_strict || dwarf_version >= 5)
+ {
+@@ -27092,7 +27103,7 @@
+ else
+ dw2_asm_output_data (1, 2, "Flags: 32-bit, lineptr present");
+ dw2_asm_output_offset (DWARF_OFFSET_SIZE,
+- (!dwarf_split_debug_info ? debug_line_section_label
++ (!dwarf_split_debug_info ? dl_section_ref
+ : debug_skeleton_line_section_label),
+ debug_line_section, NULL);
+ }
+@@ -29649,6 +29660,7 @@
comdat_type_node *ctnode;
dw_die_ref main_comp_unit_die;
unsigned char checksum[16];
@@ -9622,7 +16441,7 @@ Index: gcc/dwarf2out.c
/* Flush out any latecomers to the limbo party. */
flush_limbo_die_list ();
-@@ -29766,9 +29771,15 @@
+@@ -29766,9 +29778,15 @@
}
}
@@ -9639,7 +16458,7 @@ Index: gcc/dwarf2out.c
if (have_macinfo)
add_AT_macptr (comp_unit_die (),
-@@ -29844,7 +29855,7 @@
+@@ -29844,7 +29862,7 @@
if (debug_info_level >= DINFO_LEVEL_TERSE)
add_AT_lineptr (ctnode->root_die, DW_AT_stmt_list,
(!dwarf_split_debug_info
@@ -9648,6 +16467,22 @@ Index: gcc/dwarf2out.c
: debug_skeleton_line_section_label));
output_comdat_type_unit (ctnode);
+Index: gcc/match.pd
+===================================================================
+--- a/src/gcc/match.pd (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/match.pd (.../branches/gcc-7-branch)
+@@ -165,8 +165,9 @@
+ /* X / X is one. */
+ (simplify
+ (div @0 @0)
+- /* But not for 0 / 0 so that we can get the proper warnings and errors. */
+- (if (!integer_zerop (@0))
++ /* But not for 0 / 0 so that we can get the proper warnings and errors.
++ And not for _Fract types where we can't build 1. */
++ (if (!integer_zerop (@0) && !ALL_FRACT_MODE_P (TYPE_MODE (type)))
+ { build_one_cst (type); }))
+ /* X / abs (X) is X < 0 ? -1 : 1. */
+ (simplify
Index: gcc/expr.c
===================================================================
--- a/src/gcc/expr.c (.../tags/gcc_7_1_0_release)
@@ -10165,6 +17000,24 @@ Index: gcc/go/gofrontend/types.cc
{
if (reason != NULL)
{
+Index: gcc/opts.c
+===================================================================
+--- a/src/gcc/opts.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/opts.c (.../branches/gcc-7-branch)
+@@ -1007,6 +1007,13 @@
+
+ opts->x_flag_stack_reuse = SR_NONE;
+ }
++
++ if ((opts->x_flag_sanitize & SANITIZE_USER_ADDRESS) && opts->x_flag_tm)
++ sorry ("transactional memory is not supported with %<-fsanitize=address%>");
++
++ if ((opts->x_flag_sanitize & SANITIZE_KERNEL_ADDRESS) && opts->x_flag_tm)
++ sorry ("transactional memory is not supported with "
++ "%<-fsanitize=kernel-address%>");
+ }
+
+ #define LEFT_COLUMN 27
Index: gcc/ada/s-tpopsp-rtems.adb
===================================================================
--- a/src/gcc/ada/s-tpopsp-rtems.adb (.../tags/gcc_7_1_0_release)
@@ -11570,7 +18423,13 @@ Index: gcc/ada/ChangeLog
===================================================================
--- a/src/gcc/ada/ChangeLog (.../tags/gcc_7_1_0_release)
+++ b/src/gcc/ada/ChangeLog (.../branches/gcc-7-branch)
-@@ -1,3 +1,69 @@
+@@ -1,3 +1,75 @@
++2017-07-15 John Paul Adrian Glaubitz <glaubitz at physik.fu-berlin.de>
++
++ PR ada/81446
++ * system-linux-m68k.ads: Add pragma No_Elaboration_Code_All.
++ (Backend_Overflow_Checks): Set to True.
++
+2017-06-15 Nicolas Boulenguez <nicolas.boulenguez at free.fr>
+
+ PR ada/81105
@@ -11640,6 +18499,38 @@ Index: gcc/ada/ChangeLog
2017-05-02 Release Manager
* GCC 7.1.0 released.
+Index: gcc/ada/system-linux-m68k.ads
+===================================================================
+--- a/src/gcc/ada/system-linux-m68k.ads (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/ada/system-linux-m68k.ads (.../branches/gcc-7-branch)
+@@ -7,7 +7,7 @@
+ -- S p e c --
+ -- (GNU/Linux/m68k Version) --
+ -- --
+--- Copyright (C) 2014-2016, Free Software Foundation, Inc. --
++-- Copyright (C) 2014-2017, Free Software Foundation, Inc. --
+ -- --
+ -- This specification is derived from the Ada Reference Manual for use with --
+ -- GNAT. The copyright notice above, and the license provisions that follow --
+@@ -40,6 +40,9 @@
+ -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada
+ -- 2005, this is Pure in any case (AI-362).
+
++ pragma No_Elaboration_Code_All;
++ -- Allow the use of that restriction in units that WITH this unit
++
+ type Name is (SYSTEM_NAME_GNAT);
+ System_Name : constant Name := SYSTEM_NAME_GNAT;
+
+@@ -126,7 +129,7 @@
+ -- of the individual switch values.
+
+ Backend_Divide_Checks : constant Boolean := False;
+- Backend_Overflow_Checks : constant Boolean := False;
++ Backend_Overflow_Checks : constant Boolean := True;
+ Command_Line_Args : constant Boolean := True;
+ Configurable_Run_Time : constant Boolean := False;
+ Denorm : constant Boolean := True;
Index: gcc/ada/system-linux-x86.ads
===================================================================
--- a/src/gcc/ada/system-linux-x86.ads (.../tags/gcc_7_1_0_release)
@@ -11806,6 +18697,20 @@ Index: gcc/ada/exp_ch3.adb
end if;
if Mode_Set then
+Index: gcc/asan.c
+===================================================================
+--- a/src/gcc/asan.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/asan.c (.../branches/gcc-7-branch)
+@@ -1877,6 +1877,9 @@
+ || bitsize != size_in_bytes * BITS_PER_UNIT)
+ return;
+
++ if (VAR_P (inner) && DECL_HARD_REGISTER (inner))
++ return;
++
+ if (VAR_P (inner)
+ && offset == NULL_TREE
+ && bitpos >= 0
Index: gcc/lra-remat.c
===================================================================
--- a/src/gcc/lra-remat.c (.../tags/gcc_7_1_0_release)
@@ -11860,6 +18765,60 @@ Index: gcc/lra-remat.c
}
if (reg == NULL)
+Index: gcc/gimple-ssa-strength-reduction.c
+===================================================================
+--- a/src/gcc/gimple-ssa-strength-reduction.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/gimple-ssa-strength-reduction.c (.../branches/gcc-7-branch)
+@@ -2051,13 +2051,14 @@
+ types but allows for safe negation without twisted logic. */
+ if (wi::fits_shwi_p (bump)
+ && bump.to_shwi () != HOST_WIDE_INT_MIN
+- /* It is not useful to replace casts, copies, or adds of
++ /* It is not useful to replace casts, copies, negates, or adds of
+ an SSA name and a constant. */
+ && cand_code != SSA_NAME
+ && !CONVERT_EXPR_CODE_P (cand_code)
+ && cand_code != PLUS_EXPR
+ && cand_code != POINTER_PLUS_EXPR
+- && cand_code != MINUS_EXPR)
++ && cand_code != MINUS_EXPR
++ && cand_code != NEGATE_EXPR)
+ {
+ enum tree_code code = PLUS_EXPR;
+ tree bump_tree;
+Index: gcc/tree-eh.c
+===================================================================
+--- a/src/gcc/tree-eh.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/tree-eh.c (.../branches/gcc-7-branch)
+@@ -43,6 +43,7 @@
+ #include "langhooks.h"
+ #include "cfgloop.h"
+ #include "gimple-low.h"
++#include "asan.h"
+
+ /* In some instances a tree and a gimple need to be stored in a same table,
+ i.e. in hash tables. This is a structure to do this. */
+@@ -3304,6 +3305,20 @@
+ gimple_call_set_lhs (x, var);
+ gsi_insert_before (&gsi, x, GSI_SAME_STMT);
+
++ /* When exception handling is delegated to a caller function, we
++ have to guarantee that shadow memory variables living on stack
++ will be cleaner before control is given to a parent function. */
++ if ((flag_sanitize & SANITIZE_ADDRESS) != 0
++ && !lookup_attribute ("no_sanitize_address",
++ DECL_ATTRIBUTES (current_function_decl)))
++ {
++ tree decl
++ = builtin_decl_implicit (BUILT_IN_ASAN_HANDLE_NO_RETURN);
++ gimple *g = gimple_build_call (decl, 0);
++ gimple_set_location (g, gimple_location (stmt));
++ gsi_insert_before (&gsi, g, GSI_SAME_STMT);
++ }
++
+ fn = builtin_decl_implicit (BUILT_IN_UNWIND_RESUME);
+ x = gimple_build_call (fn, 1, var);
+ gsi_insert_before (&gsi, x, GSI_SAME_STMT);
Index: gcc/fortran/openmp.c
===================================================================
--- a/src/gcc/fortran/openmp.c (.../tags/gcc_7_1_0_release)
@@ -12450,6 +19409,19 @@ Index: gcc/fortran/trans-io.c
tmp = build_call_expr_loc (input_location,
iocall[IOCALL_SET_NML_VAL], 6,
dt_parm_addr, addr_expr, string,
+Index: gcc/gimple-pretty-print.c
+===================================================================
+--- a/src/gcc/gimple-pretty-print.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/gimple-pretty-print.c (.../branches/gcc-7-branch)
+@@ -89,7 +89,7 @@
+ return "[0.01%]";
+
+ char *buf;
+- asprintf (&buf, "[%.2f%%]", fvalue);
++ buf = xasprintf ("[%.2f%%]", fvalue);
+ const char *ret = xstrdup_for_dump (buf);
+ free (buf);
+
Index: gcc/ipa-devirt.c
===================================================================
--- a/src/gcc/ipa-devirt.c (.../tags/gcc_7_1_0_release)
@@ -12472,6 +19444,67 @@ Index: gcc/ipa-devirt.c
"in another translation unit"));
return false;
}
+Index: gcc/configure.ac
+===================================================================
+--- a/src/gcc/configure.ac (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/configure.ac (.../branches/gcc-7-branch)
+@@ -3969,6 +3969,18 @@
+ [AC_DEFINE(HAVE_AS_SPARC5_VIS4, 1,
+ [Define if your assembler supports SPARC5 and VIS 4.0 instructions.])])
+
++ gcc_GAS_CHECK_FEATURE([SPARC6 instructions],
++ gcc_cv_as_sparc_sparc6,,
++ [-xarch=sparc6],
++ [.text
++ .register %g2, #scratch
++ .register %g3, #scratch
++ .align 4
++ rd %entropy, %g1
++ fpsll64x %f0, %f2, %f4],,
++ [AC_DEFINE(HAVE_AS_SPARC6, 1,
++ [Define if your assembler supports SPARC6 instructions.])])
++
+ gcc_GAS_CHECK_FEATURE([LEON instructions],
+ gcc_cv_as_sparc_leon,,
+ [-Aleon],
+Index: gcc/function.c
+===================================================================
+--- a/src/gcc/function.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/function.c (.../branches/gcc-7-branch)
+@@ -5263,6 +5263,16 @@
+ }
+ }
+
++ /* The following was moved from init_function_start.
++ The move is supposed to make sdb output more accurate. */
++ /* Indicate the beginning of the function body,
++ as opposed to parm setup. */
++ emit_note (NOTE_INSN_FUNCTION_BEG);
++
++ gcc_assert (NOTE_P (get_last_insn ()));
++
++ parm_birth_insn = get_last_insn ();
++
+ /* If the function receives a non-local goto, then store the
+ bits we need to restore the frame pointer. */
+ if (cfun->nonlocal_goto_save_area)
+@@ -5284,16 +5294,6 @@
+ update_nonlocal_goto_save_area ();
+ }
+
+- /* The following was moved from init_function_start.
+- The move is supposed to make sdb output more accurate. */
+- /* Indicate the beginning of the function body,
+- as opposed to parm setup. */
+- emit_note (NOTE_INSN_FUNCTION_BEG);
+-
+- gcc_assert (NOTE_P (get_last_insn ()));
+-
+- parm_birth_insn = get_last_insn ();
+-
+ if (crtl->profile)
+ {
+ #ifdef PROFILE_HOOK
Index: gcc/auto-profile.c
===================================================================
--- a/src/gcc/auto-profile.c (.../tags/gcc_7_1_0_release)
@@ -12753,6 +19786,49 @@ Index: gcc/tree-cfgcleanup.c
changed |= cleanup_tree_cfg_1 ();
gcc_assert (dom_info_available_p (CDI_DOMINATORS));
+Index: gcc/simplify-rtx.c
+===================================================================
+--- a/src/gcc/simplify-rtx.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/simplify-rtx.c (.../branches/gcc-7-branch)
+@@ -5314,34 +5314,14 @@
+ {
+ case LT:
+ /* Optimize abs(x) < 0.0. */
+- if (!HONOR_SNANS (mode)
+- && (!INTEGRAL_MODE_P (mode)
+- || (!flag_wrapv && !flag_trapv && flag_strict_overflow)))
+- {
+- if (INTEGRAL_MODE_P (mode)
+- && (issue_strict_overflow_warning
+- (WARN_STRICT_OVERFLOW_CONDITIONAL)))
+- warning (OPT_Wstrict_overflow,
+- ("assuming signed overflow does not occur when "
+- "assuming abs (x) < 0 is false"));
+- return const0_rtx;
+- }
++ if (!INTEGRAL_MODE_P (mode) && !HONOR_SNANS (mode))
++ return const0_rtx;
+ break;
+
+ case GE:
+ /* Optimize abs(x) >= 0.0. */
+- if (!HONOR_NANS (mode)
+- && (!INTEGRAL_MODE_P (mode)
+- || (!flag_wrapv && !flag_trapv && flag_strict_overflow)))
+- {
+- if (INTEGRAL_MODE_P (mode)
+- && (issue_strict_overflow_warning
+- (WARN_STRICT_OVERFLOW_CONDITIONAL)))
+- warning (OPT_Wstrict_overflow,
+- ("assuming signed overflow does not occur when "
+- "assuming abs (x) >= 0 is true"));
+- return const_true_rtx;
+- }
++ if (!INTEGRAL_MODE_P (mode) && !HONOR_NANS (mode))
++ return const_true_rtx;
+ break;
+
+ case UNGE:
Index: gcc/gcov-tool.c
===================================================================
--- a/src/gcc/gcov-tool.c (.../tags/gcc_7_1_0_release)
@@ -12931,7 +20007,52 @@ Index: gcc/ubsan.c
}
else
return build_fold_addr_expr (t);
-@@ -708,9 +726,9 @@
+@@ -382,6 +400,7 @@
+ /* We weren't able to determine the type name. */
+ tname = "<unknown>";
+
++ tree eltype = type;
+ if (pstyle == UBSAN_PRINT_POINTER)
+ {
+ pp_printf (&pretty_name, "'%s%s%s%s%s%s%s",
+@@ -432,12 +451,12 @@
+ pp_quote (&pretty_name);
+
+ /* Save the tree with stripped types. */
+- type = t;
++ eltype = t;
+ }
+ else
+ pp_printf (&pretty_name, "'%s'", tname);
+
+- switch (TREE_CODE (type))
++ switch (TREE_CODE (eltype))
+ {
+ case BOOLEAN_TYPE:
+ case ENUMERAL_TYPE:
+@@ -447,9 +466,9 @@
+ case REAL_TYPE:
+ /* FIXME: libubsan right now only supports float, double and
+ long double type formats. */
+- if (TYPE_MODE (type) == TYPE_MODE (float_type_node)
+- || TYPE_MODE (type) == TYPE_MODE (double_type_node)
+- || TYPE_MODE (type) == TYPE_MODE (long_double_type_node))
++ if (TYPE_MODE (eltype) == TYPE_MODE (float_type_node)
++ || TYPE_MODE (eltype) == TYPE_MODE (double_type_node)
++ || TYPE_MODE (eltype) == TYPE_MODE (long_double_type_node))
+ tkind = 0x0001;
+ else
+ tkind = 0xffff;
+@@ -458,7 +477,7 @@
+ tkind = 0xffff;
+ break;
+ }
+- tinfo = get_ubsan_type_info_for_type (type);
++ tinfo = get_ubsan_type_info_for_type (eltype);
+
+ /* Create a new VAR_DECL of type descriptor. */
+ const char *tmp = pp_formatted_text (&pretty_name);
+@@ -708,9 +727,9 @@
? BUILT_IN_UBSAN_HANDLE_OUT_OF_BOUNDS
: BUILT_IN_UBSAN_HANDLE_OUT_OF_BOUNDS_ABORT;
tree fn = builtin_decl_explicit (bcode);
@@ -12944,7 +20065,7 @@ Index: gcc/ubsan.c
g = gimple_build_call (fn, 2, data, val);
}
gimple_set_location (g, loc);
-@@ -1266,9 +1284,11 @@
+@@ -1266,9 +1285,11 @@
tree fn = builtin_decl_explicit (fn_code);
return build_call_expr_loc (loc, fn, 2 + (code != NEGATE_EXPR),
build_fold_addr_expr_loc (loc, data),
@@ -12959,7 +20080,7 @@ Index: gcc/ubsan.c
}
/* Perform the signed integer instrumentation. GSI is the iterator
-@@ -1458,9 +1478,9 @@
+@@ -1458,9 +1479,9 @@
: BUILT_IN_UBSAN_HANDLE_LOAD_INVALID_VALUE_ABORT;
tree fn = builtin_decl_explicit (bcode);
@@ -12972,7 +20093,7 @@ Index: gcc/ubsan.c
g = gimple_build_call (fn, 2, data, val);
}
gimple_set_location (g, loc);
-@@ -1624,7 +1644,7 @@
+@@ -1624,7 +1645,7 @@
fn = builtin_decl_explicit (bcode);
fn = build_call_expr_loc (loc, fn, 2,
build_fold_addr_expr_loc (loc, data),
@@ -13012,11 +20133,36 @@ Index: gcc/ubsan.h
extern bool is_ubsan_builtin_p (tree);
extern tree ubsan_build_overflow_builtin (tree_code, location_t, tree, tree,
tree, tree *);
+Index: gcc/ipa-prop.c
+===================================================================
+--- a/src/gcc/ipa-prop.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/ipa-prop.c (.../branches/gcc-7-branch)
+@@ -3030,7 +3030,10 @@
+
+ if (index)
+ {
+- off = wi::to_offset (index);
++ if (TREE_CODE (index) == RANGE_EXPR)
++ off = wi::to_offset (TREE_OPERAND (index, 0));
++ else
++ off = wi::to_offset (index);
+ if (TYPE_DOMAIN (type) && TYPE_MIN_VALUE (TYPE_DOMAIN (type)))
+ {
+ tree low_bound = TYPE_MIN_VALUE (TYPE_DOMAIN (type));
+@@ -3039,6 +3042,8 @@
+ TYPE_PRECISION (TREE_TYPE (index)));
+ }
+ off *= wi::to_offset (unit_size);
++ /* ??? Handle more than just the first index of a
++ RANGE_EXPR. */
+ }
+ else
+ off = wi::to_offset (unit_size) * ix;
Index: gcc/po/es.po
===================================================================
--- a/src/gcc/po/es.po (.../tags/gcc_7_1_0_release)
+++ b/src/gcc/po/es.po (.../branches/gcc-7-branch)
-@@ -17,6 +17,7 @@
+@@ -17,9 +17,11 @@
# dereference - desreferencia
# hardware - hardware
# hotness - calentura
@@ -13024,7 +20170,11 @@ Index: gcc/po/es.po
# insns - instrucciones #: config/frv/frv.opt:126
# instruction - instrucción
# iv optimization - optimización iv
-@@ -35,10 +36,10 @@
++# multiply - TBD
+ # omp (OpenMP) - omp
+ # OS - S.O.
+ # reallocate - reubicar
+@@ -35,10 +37,10 @@
#
msgid ""
msgstr ""
@@ -13034,11 +20184,11 @@ Index: gcc/po/es.po
-"POT-Creation-Date: 2017-04-24 20:38+0000\n"
-"PO-Revision-Date: 2017-04-16 10:33+0200\n"
+"POT-Creation-Date: 2017-05-01 22:24+0000\n"
-+"PO-Revision-Date: 2017-05-29 00:00+0200\n"
++"PO-Revision-Date: 2017-07-26 08:25+0200\n"
"Last-Translator: Antonio Ceballos <aceballos at gmail.com>\n"
"Language-Team: Spanish <es at tp.org.es>\n"
"Language: es\n"
-@@ -794,15 +795,12 @@
+@@ -794,15 +796,12 @@
"\n"
#: gcov.c:656
@@ -13056,7 +20206,7 @@ Index: gcc/po/es.po
"\n"
#: gcov.c:657
-@@ -1996,10 +1994,9 @@
+@@ -1996,10 +1995,9 @@
msgstr "Límite en el número de revisiones de tiempo de ejecución insertadas por las versiones de bucle del vectorizador para revisión de alias."
#: params.def:568
@@ -13069,7 +20219,7 @@ Index: gcc/po/es.po
#: params.def:573
#, no-c-format
-@@ -2398,16 +2395,14 @@
+@@ -2398,16 +2396,14 @@
msgstr "Cantidad máxima de bbs similares con las cuales comparar un bb."
#: params.def:1104
@@ -13090,7 +20240,7 @@ Index: gcc/po/es.po
#: params.def:1116
#, no-c-format
-@@ -2837,42 +2832,42 @@
+@@ -2837,42 +2833,42 @@
msgid "<command-line>"
msgstr "<línea-de-orden>"
@@ -13145,7 +20295,7 @@ Index: gcc/po/es.po
#, c-format
msgid "invalid operand prefix '%%%c'"
msgstr "prefijo de operando no válido '%%%c'"
-@@ -3030,29 +3025,29 @@
+@@ -3030,29 +3026,29 @@
msgid "invalid UNSPEC as operand: %d"
msgstr "UNSPEC no válido como operando: %d"
@@ -13186,7 +20336,7 @@ Index: gcc/po/es.po
#: config/bfin/bfin.c:1444 config/bfin/bfin.c:1451 config/bfin/bfin.c:1458
#: config/bfin/bfin.c:1467 config/bfin/bfin.c:1474 config/bfin/bfin.c:1481
#: config/bfin/bfin.c:1488
-@@ -3060,13 +3055,13 @@
+@@ -3060,13 +3056,13 @@
msgid "invalid operand for code '%c'"
msgstr "operando no válido para el código '%c'"
@@ -13202,7 +20352,7 @@ Index: gcc/po/es.po
#, c-format
msgid "obsolete Maverick format code '%c'"
msgstr "código de formato Maverick obsoleto '%c'"
-@@ -3139,34 +3134,24 @@
+@@ -3139,34 +3135,24 @@
msgstr "conversión de coma fija no admitida"
#: config/avr/avr.c:9803
@@ -13242,7 +20392,7 @@ Index: gcc/po/es.po
#: config/avr/driver-avr.c:48
#, c-format
-@@ -3476,10 +3461,9 @@
+@@ -3476,10 +3462,9 @@
msgstr "el operando no es un entero, código de operando 'R' no válido"
#: config/i386/i386.c:18261
@@ -13255,7 +20405,7 @@ Index: gcc/po/es.po
#: config/i386/i386.c:18357
#, c-format
-@@ -3885,98 +3869,98 @@
+@@ -3885,98 +3870,98 @@
msgid "emit_fusion_p9_store not MEM"
msgstr "emit_fusion_p9_store no MEM"
@@ -13374,7 +20524,7 @@ Index: gcc/po/es.po
msgid "binary operator does not support mixing vector bool with floating point vector operands"
msgstr "el operador binario no admite que se mezclen operandos bool vector y vector de coma flotante"
-@@ -6204,10 +6188,8 @@
+@@ -6204,10 +6189,8 @@
msgstr "Advierte de 'new' de tipos con alineamiento extendido sin -faligned-new."
#: c-family/c.opt:296
@@ -13386,7 +20536,7 @@ Index: gcc/po/es.po
#: c-family/c.opt:300 ada/gcc-interface/lang.opt:57
msgid "Enable most warning messages."
-@@ -6226,10 +6208,8 @@
+@@ -6226,10 +6209,8 @@
msgstr "-Walloc-zero Advierte de llamadas a funciones de reserva que especifican cero bytes."
#: c-family/c.opt:317
@@ -13398,7 +20548,7 @@ Index: gcc/po/es.po
#: c-family/c.opt:331
msgid "Warn whenever an Objective-C assignment is being intercepted by the garbage collector."
-@@ -6380,10 +6360,8 @@
+@@ -6380,10 +6361,8 @@
msgstr "Avisa sobre un cuerpo vacío en una declaración if o else."
#: c-family/c.opt:489
@@ -13410,7 +20560,7 @@ Index: gcc/po/es.po
#: c-family/c.opt:493
msgid "Warn about comparison of different enum types."
-@@ -6898,10 +6876,8 @@
+@@ -6898,10 +6877,8 @@
msgstr "Avisa si se usa una matriz de longitud variable."
#: c-family/c.opt:1104
@@ -13422,7 +20572,7 @@ Index: gcc/po/es.po
#: c-family/c.opt:1110
msgid "Warn when a register variable is declared volatile."
-@@ -8953,10 +8929,8 @@
+@@ -8953,10 +8930,8 @@
msgstr "Las ramificaciones son así de caras (1-5, unidades arbitrarias)."
#: config/i386/i386.opt:275
@@ -13434,7 +20584,7 @@ Index: gcc/po/es.po
#: config/i386/i386.opt:279
msgid "Use given x86-64 code model."
-@@ -12753,17 +12727,15 @@
+@@ -12753,17 +12728,15 @@
#: config/mips/mips.opt:393
msgid "Use lwxc1/swxc1/ldxc1/sdxc1 instructions where applicable."
@@ -13455,7 +20605,7 @@ Index: gcc/po/es.po
#: config/mips/mips.opt:413
msgid "Use eXtended Physical Address (XPA) instructions."
-@@ -13346,10 +13318,8 @@
+@@ -13346,10 +13319,8 @@
msgstr "Avisa cuando no se está usando la protección contra destrucción de la pila por alguna razón."
#: common.opt:693
@@ -13467,7 +20617,7 @@ Index: gcc/po/es.po
#: common.opt:697 common.opt:701
msgid "Warn about code which might break strict aliasing rules."
-@@ -13810,10 +13780,8 @@
+@@ -13810,10 +13781,8 @@
msgstr "Realiza el paso de la propagación hacia adelante en RTL."
#: common.opt:1379
@@ -13479,7 +20629,7 @@ Index: gcc/po/es.po
#: common.opt:1382
#, c-format
-@@ -13914,10 +13882,8 @@
+@@ -13914,10 +13883,8 @@
msgstr "Realiza la conversión de saltos condicionales a ejecución condicional."
#: common.opt:1531
@@ -13491,7 +20641,7 @@ Index: gcc/po/es.po
#: common.opt:1534
#, c-format
-@@ -14017,10 +13983,8 @@
+@@ -14017,10 +13984,8 @@
msgstr "Realiza la Propagación de Rango Valor IPA."
#: common.opt:1664
@@ -13503,7 +20653,7 @@ Index: gcc/po/es.po
#: common.opt:1667
#, c-format
-@@ -14028,10 +13992,8 @@
+@@ -14028,10 +13993,8 @@
msgstr "algoritmo IRA %qs desconocido"
#: common.opt:1677
@@ -13515,7 +20665,7 @@ Index: gcc/po/es.po
#: common.opt:1680
#, c-format
-@@ -14367,10 +14329,8 @@
+@@ -14367,10 +14330,8 @@
msgstr "Reordena los bloques básicos para mejorar la ubicación del código."
#: common.opt:2076
@@ -13527,7 +20677,7 @@ Index: gcc/po/es.po
#: common.opt:2079
#, c-format
-@@ -14739,10 +14699,8 @@
+@@ -14739,10 +14700,8 @@
msgstr "Activa las optimizaciones de bucles a nivel de árbol."
#: common.opt:2526
@@ -13539,7 +20689,7 @@ Index: gcc/po/es.po
#: common.opt:2530
msgid "Enable hoisting loads from conditional pointers."
-@@ -14870,13 +14828,11 @@
+@@ -14870,13 +14829,11 @@
#: common.opt:2693
msgid "Specifies the cost model for vectorization. -fvect-cost-model=[unlimited|dynamic|cheap]\tSpecifies the cost model for vectorization."
@@ -13555,7 +20705,7 @@ Index: gcc/po/es.po
#: common.opt:2701
#, c-format
-@@ -15569,10 +15525,9 @@
+@@ -15569,10 +15526,9 @@
msgstr "se descartan los atributos de tipo después de que el tipo ya se definió"
#: auto-profile.c:347
@@ -13568,7 +20718,7 @@ Index: gcc/po/es.po
#: auto-profile.c:854
#, gcc-internal-format
-@@ -15580,40 +15535,34 @@
+@@ -15580,40 +15536,34 @@
msgstr "No se esperaba TAG."
#: auto-profile.c:920
@@ -13621,7 +20771,7 @@ Index: gcc/po/es.po
#: bt-load.c:1564
#, gcc-internal-format
-@@ -17367,7 +17316,7 @@
+@@ -17367,7 +17317,7 @@
msgid "assuming signed overflow does not occur when combining constants around a comparison"
msgstr "se asume que el desbordamiento con signo no sucede cuando se combinan constantes alrededor de una comparación"
@@ -13630,7 +20780,7 @@ Index: gcc/po/es.po
#, gcc-internal-format
msgid "fold check: original tree changed by fold"
msgstr "fold check: el árbol original cambió por un pliegue"
-@@ -17903,8 +17852,8 @@
+@@ -17903,8 +17853,8 @@
msgid "null pointer dereference"
msgstr "desreferencia a puntero nulo"
@@ -13641,7 +20791,7 @@ Index: gcc/po/es.po
#: c/c-typeck.c:9930 c/gimple-parser.c:1556 c/gimple-parser.c:1564
#: cp/call.c:6454 cp/call.c:7933 cp/constexpr.c:777 cp/constexpr.c:2174
#: cp/cvt.c:992 cp/cvt.c:1019 cp/decl.c:7224 cp/decl2.c:5072 cp/pt.c:7993
-@@ -17918,297 +17867,297 @@
+@@ -17918,297 +17868,297 @@
msgid "nonnull argument %qD compared to NULL"
msgstr "argumento %qD no nulo comparado con NULL"
@@ -13998,7 +21148,7 @@ Index: gcc/po/es.po
#, gcc-internal-format
msgid "null format string"
msgstr "cadena de formato nula"
-@@ -18364,16 +18313,14 @@
+@@ -18364,16 +18314,14 @@
msgstr "tarea contenedora"
#: gimplify.c:6852
@@ -14019,7 +21169,7 @@ Index: gcc/po/es.po
#: gimplify.c:6965
#, gcc-internal-format
-@@ -18742,10 +18689,9 @@
+@@ -18742,10 +18690,9 @@
msgstr "el tipo incompatible definido en otra unidad de traducción"
#: ipa-devirt.c:1142
@@ -14032,7 +21182,7 @@ Index: gcc/po/es.po
#: ipa-devirt.c:1146 ipa-devirt.c:1238
#, gcc-internal-format
-@@ -18763,10 +18709,9 @@
+@@ -18763,10 +18710,9 @@
msgstr "no coincide el tipo del valor de retorno"
#: ipa-devirt.c:1204
@@ -14045,7 +21195,7 @@ Index: gcc/po/es.po
#: ipa-devirt.c:1207
#, gcc-internal-format, gfc-internal-format
-@@ -18981,16 +18926,14 @@
+@@ -18981,16 +18927,14 @@
msgstr "falta el resumen de inclusión en línea ipa en el fichero de entrada"
#: ipa-pure-const.c:187
@@ -14066,7 +21216,7 @@ Index: gcc/po/es.po
#: ipa-reference.c:1182
#, gcc-internal-format
-@@ -19149,10 +19092,9 @@
+@@ -19149,10 +19093,9 @@
msgstr "flujo de bytecode: sección LTO %s inesperada"
#: lto-streamer.c:383
@@ -14079,7 +21229,7 @@ Index: gcc/po/es.po
#: lto-wrapper.c:114
#, gcc-internal-format
-@@ -19467,10 +19409,9 @@
+@@ -19467,10 +19410,9 @@
msgstr "operando -fopenacc-dim defectuoso en '%s'"
#: omp-offload.c:1157
@@ -14092,7 +21242,7 @@ Index: gcc/po/es.po
#: omp-offload.c:1161 omp-offload.c:1193
#, gcc-internal-format
-@@ -19478,16 +19419,14 @@
+@@ -19478,16 +19420,14 @@
msgstr "bucle que lo contiene aquí"
#: omp-offload.c:1166
@@ -14113,7 +21263,7 @@ Index: gcc/po/es.po
#: omp-offload.c:1173
#, gcc-internal-format
-@@ -19511,10 +19450,9 @@
+@@ -19511,10 +19451,9 @@
msgstr "insuficiente paralelismo disponible para paralelizar bucle de elemento"
#: omp-offload.c:1337
@@ -14126,7 +21276,7 @@ Index: gcc/po/es.po
#: omp-simd-clone.c:192
#, gcc-internal-format
-@@ -19713,8 +19651,7 @@
+@@ -19713,8 +19652,7 @@
msgstr "la opción -fsanitize=all no es válida"
#: opts.c:1642
@@ -14136,7 +21286,7 @@ Index: gcc/po/es.po
msgid "unrecognized argument to -f%ssanitize%s= option: %q.*s; did you mean %qs?"
msgstr "no se reconoce el argumento para la opción -f%ssanitize%s=: %q.*s; ¿quiso decir %qs?"
-@@ -20043,10 +19980,9 @@
+@@ -20043,10 +19981,9 @@
msgstr "insn con UID %i no encontrada para el operando %i de insn %i"
#: read-rtl-function.c:409
@@ -14149,7 +21299,7 @@ Index: gcc/po/es.po
#: read-rtl-function.c:710
#, gcc-internal-format, gfc-internal-format
-@@ -20395,159 +20331,159 @@
+@@ -20395,159 +20332,159 @@
msgid "%D renamed after being referenced in assembly"
msgstr "se renombró %D después de ser referenciado en el ensamblado"
@@ -14340,7 +21490,7 @@ Index: gcc/po/es.po
#, gcc-internal-format
msgid "section of alias %q+D must match section of its target"
msgstr "la sección del alias %q+D debe cuadrar con la sección de su objetivo"
-@@ -20648,34 +20584,29 @@
+@@ -20648,34 +20585,29 @@
msgstr "No se pueden usar las optimizaciones de bucle Graphite (isl no está disponible) (-fgraphite, -fgraphite-identity, -floop-nest-optimize, -floop-parallelize-all"
#: toplev.c:1273
@@ -14385,7 +21535,7 @@ Index: gcc/po/es.po
#: toplev.c:1320
#, gcc-internal-format
-@@ -21644,10 +21575,9 @@
+@@ -21644,10 +21576,9 @@
msgstr "la comprebación de acceso de memoria siempre falla"
#: tree-chkp.c:1996
@@ -14398,7 +21548,7 @@ Index: gcc/po/es.po
#: tree-chkp.c:2774
#, gcc-internal-format, gfc-internal-format
-@@ -21866,10 +21796,9 @@
+@@ -21866,10 +21797,9 @@
msgstr "dentro de este bucle"
#: tree-ssa-loop-prefetch.c:2045
@@ -14411,7 +21561,7 @@ Index: gcc/po/es.po
#: tree-ssa-operands.c:975
#, gcc-internal-format
-@@ -22215,8 +22144,8 @@
+@@ -22215,8 +22145,8 @@
#: c-family/c-attribs.c:2898 c-family/c-attribs.c:2937
#: c-family/c-attribs.c:3019 c-family/c-attribs.c:3062
#: c-family/c-attribs.c:3078 c-family/c-attribs.c:3172
@@ -14422,7 +21572,7 @@ Index: gcc/po/es.po
#: config/h8300/h8300.c:5480 config/h8300/h8300.c:5504 config/i386/i386.c:7715
#: config/i386/i386.c:41425 config/ia64/ia64.c:762
#: config/rs6000/rs6000.c:35369 config/spu/spu.c:3741
-@@ -22252,92 +22181,92 @@
+@@ -22252,92 +22182,92 @@
msgid "%qE implies default visibility, but %qD has already been declared with a different visibility"
msgstr "%qE implica visibilidad por defecto, pero %qD ya se había declarado con una visibilidad diferente"
@@ -14533,7 +21683,7 @@ Index: gcc/po/es.po
#, gcc-internal-format
msgid "type is deprecated"
msgstr "el tipo es obsoleto"
-@@ -22364,262 +22293,262 @@
+@@ -22364,262 +22294,262 @@
#. main variant only.
#.
#. Convenience macro for matching individual fields.
@@ -14848,7 +21998,7 @@ Index: gcc/po/es.po
#, gcc-internal-format
msgid "verify_type failed"
msgstr "falló verify_type"
-@@ -23616,13 +23545,13 @@
+@@ -23616,13 +23546,13 @@
msgid "%<fallthrough%> attribute specified with a parameter"
msgstr "el atributo %<fallthrough%> se especificó con un parámetro"
@@ -14864,7 +22014,7 @@ Index: gcc/po/es.po
#, gcc-internal-format
msgid "too many arguments to function %qE"
msgstr "demasiados argumentos para la función %qE"
-@@ -23707,72 +23636,72 @@
+@@ -23707,72 +23637,72 @@
msgid "index %E denotes an offset greater than size of %qT"
msgstr "el índice %E denota un desplazamiento mayor que el tamaño de %qT"
@@ -14951,7 +22101,7 @@ Index: gcc/po/es.po
#: cp/call.c:4836 cp/call.c:4843
#, gcc-internal-format
msgid "conversion of scalar %qT to vector %qT involves truncation"
-@@ -23780,22 +23709,22 @@
+@@ -23780,22 +23710,22 @@
#. Reject arguments that are built-in functions with
#. no library fallback.
@@ -14978,7 +22128,7 @@ Index: gcc/po/es.po
#, gcc-internal-format
msgid "environment variable SOURCE_DATE_EPOCH must expand to a non-negative integer less than or equal to %wd"
msgstr ""
-@@ -23816,10 +23745,9 @@
+@@ -23816,10 +23746,9 @@
msgstr "el argumento de la cadena de formato no es un tipo de cadena"
#: c-family/c-format.c:210
@@ -14991,7 +22141,7 @@ Index: gcc/po/es.po
#: c-family/c-format.c:213
#, gcc-internal-format
-@@ -23827,16 +23755,14 @@
+@@ -23827,16 +23756,14 @@
msgstr "se encontró un %qT pero el argumento de formato debe ser una cadena"
#: c-family/c-format.c:223
@@ -15012,7 +22162,7 @@ Index: gcc/po/es.po
#: c-family/c-format.c:289
#, gcc-internal-format
-@@ -24585,20 +24511,19 @@
+@@ -24585,20 +24512,19 @@
msgstr "no se admite la declaración %<#pragma weak%> de %q+D; se ignorará"
#: c-family/c-pragma.c:418
@@ -15037,7 +22187,7 @@ Index: gcc/po/es.po
#: c-family/c-pragma.c:485 c-family/c-pragma.c:487
#, gcc-internal-format
-@@ -24661,10 +24586,9 @@
+@@ -24661,10 +24587,9 @@
msgstr "basura al final de %<#pragma GCC visibility%>"
#: c-family/c-pragma.c:750
@@ -15050,7 +22200,7 @@ Index: gcc/po/es.po
#: c-family/c-pragma.c:776
#, gcc-internal-format
-@@ -24682,16 +24606,14 @@
+@@ -24682,16 +24607,14 @@
msgstr "opción desconocida después del tipo %<#pragma GCC diagnostic%>"
#: c-family/c-pragma.c:802
@@ -15071,7 +22221,7 @@ Index: gcc/po/es.po
#: c-family/c-pragma.c:842
#, gcc-internal-format
-@@ -24905,28 +24827,24 @@
+@@ -24905,28 +24828,24 @@
msgstr "un %<and%> de pruebas equivalentes mutuamente exclusivas siempre es falso"
#: c-family/c-warn.c:248
@@ -15108,7 +22258,7 @@ Index: gcc/po/es.po
#: c-family/c-warn.c:374
#, gcc-internal-format
-@@ -24962,82 +24880,82 @@
+@@ -24962,82 +24881,82 @@
#: c-family/c-warn.c:687
#, gcc-internal-format
msgid "argument to %<sizeof%> in %qD call is the same expression as the destination; did you mean to remove the addressof?"
@@ -15207,7 +22357,7 @@ Index: gcc/po/es.po
#: c-family/c-warn.c:860 c-family/c-warn.c:867
#, fuzzy, gcc-internal-format
-@@ -25066,10 +24984,9 @@
+@@ -25066,10 +24985,9 @@
msgstr "%q+D sólo toma cero o dos argumentos"
#: c-family/c-warn.c:910
@@ -15220,7 +22370,7 @@ Index: gcc/po/es.po
#: c-family/c-warn.c:952
#, gcc-internal-format
-@@ -25087,10 +25004,9 @@
+@@ -25087,10 +25005,9 @@
msgstr "la conversión de %qT desde %qT puede alterar su valor"
#: c-family/c-warn.c:989
@@ -15233,7 +22383,7 @@ Index: gcc/po/es.po
#: c-family/c-warn.c:1024
#, gcc-internal-format
-@@ -25118,10 +25034,9 @@
+@@ -25118,10 +25035,9 @@
msgstr "falta el case por defecto para un switch"
#: c-family/c-warn.c:1179
@@ -15246,7 +22396,7 @@ Index: gcc/po/es.po
#: c-family/c-warn.c:1252
#, gcc-internal-format
-@@ -25319,10 +25234,9 @@
+@@ -25319,10 +25235,9 @@
msgstr "argumento de tipo no válido de %<->%> (se tiene %qT)"
#: c-family/c-warn.c:1414
@@ -15259,7 +22409,7 @@ Index: gcc/po/es.po
#: c-family/c-warn.c:1419
#, gcc-internal-format
-@@ -25471,10 +25385,9 @@
+@@ -25471,10 +25386,9 @@
msgstr "comparación de un ~unsigned promovido con unsigned"
#: c-family/c-warn.c:1897
@@ -15272,7 +22422,7 @@ Index: gcc/po/es.po
#: c-family/c-warn.c:1959
#, gcc-internal-format
-@@ -25482,16 +25395,14 @@
+@@ -25482,16 +25396,14 @@
msgstr "se define tipo %qD localmente pero no se usa"
#: c-family/c-warn.c:1994
@@ -15293,7 +22443,7 @@ Index: gcc/po/es.po
#: c-family/c-warn.c:2031
#, gcc-internal-format
-@@ -25505,28 +25416,24 @@
+@@ -25505,28 +25417,24 @@
#: c-family/c-warn.c:2040 c-family/c-warn.c:2045 c-family/c-warn.c:2050
#: c-family/c-warn.c:2055
@@ -15330,7 +22480,7 @@ Index: gcc/po/es.po
#: c-family/c-warn.c:2210
#, fuzzy
-@@ -25537,16 +25444,14 @@
+@@ -25537,16 +25445,14 @@
msgstr[1] "el paso del argumento %d de %qE descarta el calificador %qv del tipo del destino del puntero"
#: c-family/c-warn.c:2275 c/c-typeck.c:5217 cp/call.c:5316
@@ -15351,7 +22501,7 @@ Index: gcc/po/es.po
#: c-family/cilk.c:106
#, fuzzy, gcc-internal-format
-@@ -25555,10 +25460,9 @@
+@@ -25555,10 +25461,9 @@
msgstr "su función será mal compilada"
#: c-family/cilk.c:250
@@ -15364,7 +22514,7 @@ Index: gcc/po/es.po
#: c-family/cilk.c:393
#, fuzzy, gcc-internal-format
-@@ -25572,15 +25476,14 @@
+@@ -25572,15 +25477,14 @@
msgstr ""
#: c-family/cilk.c:495
@@ -15383,7 +22533,7 @@ Index: gcc/po/es.po
#: c-family/cppspec.c:93
#, gcc-internal-format
-@@ -25592,11 +25495,10 @@
+@@ -25592,11 +25496,10 @@
msgid "too many input files"
msgstr "demasiados ficheros de entrada"
@@ -15398,7 +22548,7 @@ Index: gcc/po/es.po
#: common/config/alpha/alpha-common.c:76
#, gcc-internal-format
-@@ -25604,16 +25506,14 @@
+@@ -25604,16 +25507,14 @@
msgstr "valor %qs erróneo para el interruptor -mtls-size"
#: common/config/arc/arc-common.c:82
@@ -15419,7 +22569,7 @@ Index: gcc/po/es.po
#: common/config/bfin/bfin-common.c:304 common/config/m68k/m68k-common.c:60
#, gcc-internal-format, gfc-internal-format
-@@ -25681,35 +25581,34 @@
+@@ -25681,35 +25582,34 @@
msgstr "valor erróneo %<%s%> para el interruptor -mtls-size="
#: common/config/msp430/msp430-common.c:57
@@ -15462,7 +22612,7 @@ Index: gcc/po/es.po
#: common/config/rs6000/rs6000-common.c:174 config/sparc/sparc.c:1371
#, gcc-internal-format, gfc-internal-format
-@@ -25732,10 +25631,9 @@
+@@ -25732,10 +25632,9 @@
msgstr "se descarta la opción -msimple-fpu"
#: common/config/rs6000/rs6000-common.c:314
@@ -15475,7 +22625,7 @@ Index: gcc/po/es.po
#: common/config/rx/rx-common.c:61
#, gcc-internal-format
-@@ -25743,10 +25641,9 @@
+@@ -25743,10 +25642,9 @@
msgstr "la cpu RX200 no tiene FPU de hardware"
#: common/config/rx/rx-common.c:63
@@ -15488,7 +22638,7 @@ Index: gcc/po/es.po
#: common/config/s390/s390-common.c:98
#, gcc-internal-format
-@@ -25836,16 +25733,14 @@
+@@ -25836,16 +25734,14 @@
#. Arbitrary limit, number should be like xx.yy.zz
#: config/darwin-driver.c:125
@@ -15509,7 +22659,7 @@ Index: gcc/po/es.po
#: config/darwin-driver.c:233
#, fuzzy, gcc-internal-format
-@@ -25902,10 +25797,9 @@
+@@ -25902,10 +25798,9 @@
msgstr "el atributo de compatibilidad vtable 2.95 %qE sólo aplica a clases C++"
#: config/darwin.c:2758
@@ -15522,7 +22672,7 @@ Index: gcc/po/es.po
#: config/darwin.c:2947
#, gcc-internal-format, gfc-internal-format
-@@ -26039,16 +25933,14 @@
+@@ -26039,16 +25934,14 @@
msgstr "soporte de análisis de perfil para VxWorks"
#: config/aarch64/aarch64-builtins.c:1089 config/arm/arm-builtins.c:2246
@@ -15543,7 +22693,7 @@ Index: gcc/po/es.po
#: config/aarch64/aarch64-builtins.c:1163
#, fuzzy, gcc-internal-format
-@@ -26057,10 +25949,9 @@
+@@ -26057,10 +25950,9 @@
msgstr "el segundo argumento debe ser un inmediato de 4-bit"
#: config/aarch64/aarch64.c:927
@@ -15556,7 +22706,7 @@ Index: gcc/po/es.po
#: config/aarch64/aarch64.c:929
#, fuzzy, gcc-internal-format
-@@ -26068,203 +25959,187 @@
+@@ -26068,203 +25960,187 @@
msgid "%qs feature modifier is incompatible with %s %s"
msgstr "%qs es incompatible con %qs"
@@ -15832,7 +22982,7 @@ Index: gcc/po/es.po
#, fuzzy, gcc-internal-format
#| msgid "line number out of range"
msgid "lane %wd out of range %wd - %wd"
-@@ -26338,10 +26213,9 @@
+@@ -26338,10 +26214,9 @@
msgstr ""
#: config/arc/arc.c:720
@@ -15845,7 +22995,7 @@ Index: gcc/po/es.po
#: config/arc/arc.c:725
#, fuzzy, gcc-internal-format
-@@ -26352,17 +26226,17 @@
+@@ -26352,17 +26227,17 @@
#: config/arc/arc.c:729
#, gcc-internal-format
msgid "-mspfp_fast not available on ARC600 or ARC601"
@@ -15866,7 +23016,7 @@ Index: gcc/po/es.po
#. Check options against architecture options. Throw an error if
#. option is not allowed.
-@@ -26370,18 +26244,17 @@
+@@ -26370,18 +26245,17 @@
#, fuzzy, gcc-internal-format, gfc-internal-format
#| msgid "%qD is not a variable in clause %qs"
msgid "%s is not available for %s architecture"
@@ -15889,7 +23039,7 @@ Index: gcc/po/es.po
#: config/arc/arc.c:1601 config/epiphany/epiphany.c:492
#: config/epiphany/epiphany.c:532
-@@ -26395,73 +26268,69 @@
+@@ -26395,73 +26269,69 @@
msgstr "el argumento del atributo %qE no es \"ilink1\" o \"ilink2\""
#: config/arc/arc.c:1618
@@ -15980,7 +23130,7 @@ Index: gcc/po/es.po
#: config/arc/arc.c:6127
#, fuzzy, gcc-internal-format, gfc-internal-format
-@@ -26470,22 +26339,19 @@
+@@ -26470,22 +26340,19 @@
msgstr "se usó un símbolo como un operando inmediato"
#: config/arc/arc.c:6132
@@ -16009,7 +23159,7 @@ Index: gcc/po/es.po
#: config/arc/arc.c:6143
#, gcc-internal-format, gfc-internal-format
-@@ -26495,23 +26361,22 @@
+@@ -26495,23 +26362,22 @@
#: config/arc/arc.c:6194
#, gcc-internal-format
msgid "register number must be a compile-time constant. Try giving higher optimization levels"
@@ -16038,7 +23188,7 @@ Index: gcc/po/es.po
#: config/arm/arm-builtins.c:2349
#, fuzzy, gcc-internal-format
-@@ -26522,17 +26387,17 @@
+@@ -26522,17 +26388,17 @@
#: config/arm/arm-builtins.c:2454
#, gcc-internal-format
msgid "You must enable NEON instructions (e.g. -mfloat-abi=softfp -mfpu=neon) to use these intrinsics."
@@ -16059,7 +23209,7 @@ Index: gcc/po/es.po
#. @@@ better error message
#: config/arm/arm-builtins.c:2610 config/arm/arm-builtins.c:2714
-@@ -26544,17 +26409,17 @@
+@@ -26544,17 +26410,17 @@
#: config/arm/arm-builtins.c:2721 config/arm/arm-builtins.c:2730
#, gcc-internal-format
msgid "the range of selector should be in 0 to 7"
@@ -16080,7 +23230,7 @@ Index: gcc/po/es.po
#: config/arm/arm-builtins.c:2800
#, gcc-internal-format
-@@ -26562,10 +26427,9 @@
+@@ -26562,10 +26428,9 @@
msgstr "la máscara debe ser un inmediato"
#: config/arm/arm-builtins.c:2805
@@ -16093,7 +23243,7 @@ Index: gcc/po/es.po
#: config/arm/arm-builtins.c:2993
#, gcc-internal-format
-@@ -26687,63 +26551,62 @@
+@@ -26687,63 +26552,62 @@
msgid "the count should be no less than 0. please check the intrinsic _mm_sra_si64 in code."
msgstr ""
@@ -16172,7 +23322,7 @@ Index: gcc/po/es.po
#, gcc-internal-format
msgid "target CPU does not support unaligned accesses"
msgstr "el CPU objetivo no admite accesos sin alinear"
-@@ -26750,131 +26613,133 @@
+@@ -26750,131 +26614,133 @@
#. To support this we need to be able to parse FPU feature options
#. from the architecture string.
@@ -16343,7 +23493,7 @@ Index: gcc/po/es.po
#: config/avr/avr.c:9480 config/avr/avr.c:9496 config/bfin/bfin.c:4673
#: config/bfin/bfin.c:4734 config/bfin/bfin.c:4763
#: config/epiphany/epiphany.c:475 config/h8300/h8300.c:5456
-@@ -26890,123 +26755,110 @@
+@@ -26890,123 +26756,110 @@
msgid "%qE attribute only applies to functions"
msgstr "el atributo %qE se aplica solamente a funciones"
@@ -16512,7 +23662,7 @@ Index: gcc/po/es.po
#: config/avr/avr-c.c:105 config/avr/avr-c.c:171 config/avr/avr-c.c:228
#, fuzzy, gcc-internal-format
-@@ -27015,28 +26867,24 @@
+@@ -27015,28 +26868,24 @@
msgstr "no se encontró una plantilla coincidente para %qD"
#: config/avr/avr-c.c:122
@@ -16549,7 +23699,7 @@ Index: gcc/po/es.po
#: config/avr/avr-devices.c:212
#, fuzzy, gcc-internal-format, gfc-internal-format
-@@ -27065,16 +26913,14 @@
+@@ -27065,16 +26914,14 @@
msgstr "no se admite -fPIC"
#: config/avr/avr.c:773
@@ -16570,7 +23720,7 @@ Index: gcc/po/es.po
#: config/avr/avr.c:1040
#, gcc-internal-format
-@@ -27097,16 +26943,14 @@
+@@ -27097,16 +26944,14 @@
msgstr "la función %qs no puede devolver un valor"
#: config/avr/avr.c:1084
@@ -16591,7 +23741,7 @@ Index: gcc/po/es.po
#: config/avr/avr.c:2543
#, gcc-internal-format
-@@ -27134,16 +26978,14 @@
+@@ -27134,16 +26979,14 @@
msgstr "no se admite escribir al espacio de direcciones %qs"
#: config/avr/avr.c:9515
@@ -16612,7 +23762,7 @@ Index: gcc/po/es.po
#: config/avr/avr.c:9539 config/bfin/bfin.c:4795 config/i386/winnt.c:59
#: config/nvptx/nvptx.c:4301
-@@ -27157,33 +26999,29 @@
+@@ -27157,33 +27000,29 @@
msgstr "el atributo %qE sólo permite una constante entera como argumento"
#: config/avr/avr.c:9560
@@ -16655,7 +23805,7 @@ Index: gcc/po/es.po
#: config/avr/avr.c:9831
#, gcc-internal-format
-@@ -27201,16 +27039,14 @@
+@@ -27201,16 +27040,14 @@
msgstr "la variable %q+D debe ser const para que se ponga en la sección de sólo lectura a través de %qs"
#: config/avr/avr.c:9919
@@ -16676,7 +23826,7 @@ Index: gcc/po/es.po
#: config/avr/avr.c:10058
#, gcc-internal-format
-@@ -27223,22 +27059,19 @@
+@@ -27223,22 +27060,19 @@
msgstr "se colocó la variable %q+D sin inicializar en el área de memoria del programa"
#: config/avr/avr.c:10224
@@ -16705,7 +23855,7 @@ Index: gcc/po/es.po
#: config/avr/avr.c:13916 config/avr/avr.c:13929
#, gcc-internal-format, gfc-internal-format
-@@ -27253,30 +27086,27 @@
+@@ -27253,30 +27087,27 @@
#: config/avr/avr.c:13971
#, gcc-internal-format, gfc-internal-format
msgid "rounding to %d bits has no effect for fixed-point value with %d fractional bits"
@@ -16744,7 +23894,7 @@ Index: gcc/po/es.po
#: config/bfin/bfin.c:2349
#, gcc-internal-format
-@@ -27502,10 +27332,9 @@
+@@ -27502,10 +27333,9 @@
msgstr "no hay FUNCTION_PROFILER para CRIS"
#: config/epiphany/epiphany.c:483
@@ -16757,7 +23907,7 @@ Index: gcc/po/es.po
#: config/epiphany/epiphany.c:507
#, gcc-internal-format
-@@ -27583,28 +27412,24 @@
+@@ -27583,28 +27413,24 @@
msgstr "esta función interna sólo está disponible en el fr450"
#: config/ft32/ft32.c:177
@@ -16794,7 +23944,7 @@ Index: gcc/po/es.po
#: config/h8300/h8300.c:348
#, gcc-internal-format
-@@ -27612,39 +27437,34 @@
+@@ -27612,39 +27438,34 @@
msgstr "se usó -ms2600 sin -ms"
#: config/h8300/h8300.c:354
@@ -16845,7 +23995,7 @@ Index: gcc/po/es.po
#: config/i386/host-cygwin.c:62
#, gcc-internal-format
-@@ -27657,69 +27477,60 @@
+@@ -27657,69 +27478,60 @@
msgstr "no se puede establecer la posición en el fichero PCH: %m"
#: config/i386/i386.c:4692
@@ -16935,7 +24085,7 @@ Index: gcc/po/es.po
#. rep; movq isn't available in 32-bit code.
#: config/i386/i386.c:5299
-@@ -27728,10 +27539,9 @@
+@@ -27728,10 +27540,9 @@
msgstr "no se admite -mstringop-stategy=rep_8byte para código de 32-bit"
#: config/i386/i386.c:5316
@@ -16948,7 +24098,7 @@ Index: gcc/po/es.po
#: config/i386/i386.c:5342 config/i386/i386.c:5351 config/i386/i386.c:5363
#: config/i386/i386.c:5374 config/i386/i386.c:5385
-@@ -27760,28 +27570,24 @@
+@@ -27760,28 +27571,24 @@
msgstr "no está compilado el modo bit-%i"
#: config/i386/i386.c:5423
@@ -16985,7 +24135,7 @@ Index: gcc/po/es.po
#: config/i386/i386.c:5442 config/i386/i386.c:5718
#, gcc-internal-format
-@@ -27789,82 +27595,69 @@
+@@ -27789,82 +27596,69 @@
msgstr "el CPU que seleccionó no admite el conjunto de instrucciones x86-64"
#: config/i386/i386.c:5655 config/i386/i386.c:5658
@@ -17094,7 +24244,7 @@ Index: gcc/po/es.po
#: config/i386/i386.c:5826
#, gcc-internal-format
-@@ -27872,10 +27665,9 @@
+@@ -27872,10 +27666,9 @@
msgstr "se descarta -mregparm en modo de 64-bit"
#: config/i386/i386.c:5828
@@ -17107,7 +24257,7 @@ Index: gcc/po/es.po
#: config/i386/i386.c:5831
#, gcc-internal-format, gfc-internal-format
-@@ -27883,16 +27675,14 @@
+@@ -27883,16 +27676,14 @@
msgstr "-mregparm=%d no está entre 0 y %d"
#: config/i386/i386.c:5864
@@ -17128,7 +24278,7 @@ Index: gcc/po/es.po
#: config/i386/i386.c:5938
#, gcc-internal-format
-@@ -27910,28 +27700,24 @@
+@@ -27910,28 +27701,24 @@
msgstr "-mincoming-stack-boundary=%d no está entre %d y 12"
#: config/i386/i386.c:5977
@@ -17165,7 +24315,7 @@ Index: gcc/po/es.po
#: config/i386/i386.c:5997
#, gcc-internal-format
-@@ -27944,28 +27730,24 @@
+@@ -27944,28 +27731,24 @@
msgstr "el conjunto de instrucciones 387 está desactivado, usando la aritmética SSE"
#: config/i386/i386.c:6054
@@ -17202,7 +24352,7 @@ Index: gcc/po/es.po
#: config/i386/i386.c:6178
#, gcc-internal-format
-@@ -27990,19 +27772,17 @@
+@@ -27990,19 +27773,17 @@
#: config/i386/i386.c:7168
#, gcc-internal-format
msgid "Only DWARF debug format is supported for interrupt service routine."
@@ -17227,7 +24377,7 @@ Index: gcc/po/es.po
#: config/i386/i386.c:7683 config/i386/i386.c:7734
#, gcc-internal-format
-@@ -28060,10 +27840,9 @@
+@@ -28060,10 +27841,9 @@
msgstr "los atributos cdecl y thiscall no son compatibles"
#: config/i386/i386.c:7779
@@ -17240,7 +24390,7 @@ Index: gcc/po/es.po
#: config/i386/i386.c:8023
#, gcc-internal-format
-@@ -28076,10 +27855,9 @@
+@@ -28076,10 +27856,9 @@
msgstr "se llama a %qT con el atributo sseregparm sin activar SSE/SSE2"
#: config/i386/i386.c:8342
@@ -17253,7 +24403,7 @@ Index: gcc/po/es.po
#: config/i386/i386.c:8374
#, gcc-internal-format
-@@ -28087,16 +27865,14 @@
+@@ -28087,16 +27866,14 @@
msgstr "ms_hook_prologue no es compatible con la función anidada"
#: config/i386/i386.c:8687
@@ -17274,7 +24424,7 @@ Index: gcc/po/es.po
#: config/i386/i386.c:8707
#, gcc-internal-format
-@@ -28104,10 +27880,9 @@
+@@ -28104,10 +27881,9 @@
msgstr "el argumento de vector AVX sin AVX activado cambia la ABI"
#: config/i386/i386.c:8713
@@ -17287,7 +24437,7 @@ Index: gcc/po/es.po
#: config/i386/i386.c:8729
#, gcc-internal-format
-@@ -28160,15 +27935,14 @@
+@@ -28160,15 +27936,14 @@
msgstr "se devuelve el registro x87 con x87 desactivado"
#: config/i386/i386.c:9655 config/i386/i386.c:9926 config/i386/i386.c:10449
@@ -17306,7 +24456,7 @@ Index: gcc/po/es.po
#: config/i386/i386.c:10351
#, gcc-internal-format, gfc-internal-format
-@@ -28183,7 +27957,7 @@
+@@ -28183,7 +27958,7 @@
#: config/i386/i386.c:13824
#, gcc-internal-format
msgid "Dynamic Realign Argument Pointer (DRAP) not supported in interrupt service routine. This may be worked around by avoiding functions with aggregate return."
@@ -17315,7 +24465,7 @@ Index: gcc/po/es.po
#: config/i386/i386.c:14836
#, gcc-internal-format
-@@ -28191,8 +27965,7 @@
+@@ -28191,8 +27966,7 @@
msgstr "-fsplit-stack no admite fastcall con funciones anidadas"
#: config/i386/i386.c:14856
@@ -17325,7 +24475,7 @@ Index: gcc/po/es.po
msgid "-fsplit-stack does not support 2 register parameters for a nested function"
msgstr "-fsplit-stack no admite 2 parámetros de registro para una función anidada"
-@@ -28204,10 +27977,9 @@
+@@ -28204,10 +27978,9 @@
msgstr "-fsplit-stack no admite 3 parámetros de registro"
#: config/i386/i386.c:17672 config/i386/i386.c:17686
@@ -17338,7 +24488,7 @@ Index: gcc/po/es.po
#: config/i386/i386.c:17718
#, gcc-internal-format
-@@ -28220,72 +27992,64 @@
+@@ -28220,72 +27993,64 @@
msgstr "no se admite el tamaño de operando para el registro extendido"
#: config/i386/i386.c:17924
@@ -17431,7 +24581,7 @@ Index: gcc/po/es.po
#: config/i386/i386.c:34294 config/i386/i386.c:35692
#, gcc-internal-format
-@@ -28308,10 +28072,9 @@
+@@ -28308,10 +28073,9 @@
msgstr "el último argumento debe ser un inmediato de 1-bit"
#: config/i386/i386.c:35638
@@ -17444,7 +24594,7 @@ Index: gcc/po/es.po
#: config/i386/i386.c:35671
#, gcc-internal-format
-@@ -28339,40 +28102,34 @@
+@@ -28339,40 +28103,34 @@
msgstr "el último argumento debe ser un inmediato de 8-bit"
#: config/i386/i386.c:35907
@@ -17497,7 +24647,7 @@ Index: gcc/po/es.po
#: config/i386/i386.c:36527
#, gcc-internal-format
-@@ -28400,16 +28157,14 @@
+@@ -28400,28 +28158,24 @@
msgstr "el último argumento debe ser un inmediato"
#: config/i386/i386.c:38270 config/i386/i386.c:38452
@@ -17517,8 +24667,549 @@ Index: gcc/po/es.po
+msgstr "el argumento delantero debe ser un escalar 1, 2, 4, 8"
#: config/i386/i386.c:38511
+-#, fuzzy, gcc-internal-format
+-#| msgid "incorrect insn:"
++#, gcc-internal-format
+ msgid "incorrect hint operand"
+-msgstr "insn incorrecta:"
++msgstr "operando de pista incorrecto"
+
+ #: config/i386/i386.c:38530
+-#, fuzzy, gcc-internal-format
+-#| msgid "the last argument must be an 8-bit immediate"
++#, gcc-internal-format
+ msgid "the xabort's argument must be an 8-bit immediate"
+-msgstr "el último argumento debe ser un inmediato de 8-bit"
++msgstr "el argumento de xabort debe ser un inmediato de 8-bit"
+
+ #: config/i386/i386.c:41336
+ #, gcc-internal-format
+@@ -28446,7 +28200,7 @@
+ #: config/i386/i386.c:41479
+ #, gcc-internal-format
+ msgid "interrupt service routine should have a pointer as the first argument"
+-msgstr ""
++msgstr "la rutina de servicio de interrupciones debería tener un puntero como primer argumento"
+
+ #: config/i386/i386.c:41486
+ #, gcc-internal-format, gfc-internal-format
+@@ -28456,106 +28210,93 @@
+ #: config/i386/i386.c:41496
+ #, gcc-internal-format
+ msgid "interrupt service routine can only have a pointer argument and an optional integer argument"
+-msgstr ""
++msgstr "la rutina de servicio de interrupciones solo puede tener un argumento puntero y un argumento entero opcional"
+
+ #: config/i386/i386.c:41499
+-#, fuzzy, gcc-internal-format
+-#| msgid "interrupt Service Routines cannot be coded in Thumb mode"
++#, gcc-internal-format
+ msgid "interrupt service routine can't have non-void return value"
+-msgstr "no se pueden codificar las Rutinas de Servicios de Interrupción en el modo Thumb"
++msgstr "ls rutina de servicio de interrupción no puede tener valor de retorno que no sea void"
+
+ #: config/i386/i386.c:44401
+-#, fuzzy, gcc-internal-format
+-#| msgid "By-value argument at %L is not allowed in this context"
++#, gcc-internal-format
+ msgid "alternatives not allowed in asm flag output"
+-msgstr "El argumento por valor en %L no se permite en este contexto"
++msgstr "no se permiten alternativas en la salida del indicador asm"
+
+ #: config/i386/i386.c:44465
+-#, fuzzy, gcc-internal-format
+-#| msgid "unknown IRA algorithm %qs"
++#, gcc-internal-format
+ msgid "unknown asm flag output %qs"
+-msgstr "algoritmo IRA %qs desconocido"
++msgstr "salida del indicador asm %qs desconocida"
+
+ #: config/i386/i386.c:44494
+-#, fuzzy, gcc-internal-format
+-#| msgid "invalid type for make function"
++#, gcc-internal-format
+ msgid "invalid type for asm flag output"
+-msgstr "tipo no válido para la función make"
++msgstr "tipo no válido para la salida del indicador asm"
+
+ #: config/i386/i386.c:50765
+-#, fuzzy, gcc-internal-format
+-#| msgid "unknown architecture %qs"
++#, gcc-internal-format
+ msgid "Unknown architecture specific memory model"
+-msgstr "arquitectura %qs desconocida"
++msgstr "Modelo de memoria específico de la arquitectura desconocido"
+
+ #: config/i386/i386.c:50772
+ #, gcc-internal-format
+ msgid "HLE_ACQUIRE not used with ACQUIRE or stronger memory model"
+-msgstr ""
++msgstr "HLE_ACQUIRE no se usa con ACQUIRE o modelos de memoria más fuertes"
+
+ #: config/i386/i386.c:50778
+ #, gcc-internal-format
+ msgid "HLE_RELEASE not used with RELEASE or stronger memory model"
+-msgstr ""
++msgstr "HLE_RELEASE no se usa con RELEASE o modelos de memoria más fuertes"
+
+ #: config/i386/i386.c:50802 config/i386/i386.c:50923
+-#, fuzzy, gcc-internal-format, gfc-internal-format
+-#| msgid "unsupported version"
++#, gcc-internal-format, gfc-internal-format
+ msgid "unsupported simdlen %d"
+-msgstr "versión sin soporte"
++msgstr "simdlen %d no admitido"
+
+ #: config/i386/i386.c:50821
+ #, gcc-internal-format
+ msgid "unsupported return type %qT for simd\n"
+-msgstr ""
++msgstr "no se admite el tipo de retorno %qT para simd\n"
+
+ #: config/i386/i386.c:50843
+-#, fuzzy, gcc-internal-format
+-#| msgid "unsupported argument type to builtin function"
++#, gcc-internal-format
+ msgid "unsupported argument type %qT for simd\n"
+-msgstr "no se admite el tipo de argumento para la función interna"
++msgstr "no se admite el tipo de argumento %qT para simd\n"
+
+ #: config/i386/i386.c:51169
+ #, gcc-internal-format
+ msgid "Pointer Checker requires MPX support on this target. Use -mmpx options to enable MPX."
+-msgstr ""
++msgstr "El Comprobador de Punteros requiere suporte MPX en este objetivo. Utilice las opciones -mmpx para activar MPX."
+
+ #: config/i386/intelmic-mkoffload.c:71 config/nvptx/mkoffload.c:85
+-#, fuzzy, gcc-internal-format
+-#| msgid "deleting LTRANS input file %s: %m"
++#, gcc-internal-format
+ msgid "deleting file %s: %m"
+-msgstr "se borra el fichero de entrada LTRANS %s: %m"
++msgstr "se borra el fichero %s: %m"
+
+ #: config/i386/intelmic-mkoffload.c:253 config/i386/intelmic-mkoffload.c:317
+ #: config/i386/intelmic-mkoffload.c:358 config/nvptx/mkoffload.c:524
+-#, fuzzy, gcc-internal-format, gfc-internal-format
+-#| msgid "cannot open %s"
++#, gcc-internal-format, gfc-internal-format
+ msgid "cannot open '%s'"
+-msgstr "no se puede abrir %s"
++msgstr "no se puede abrir '%s'"
+
+ #: config/i386/intelmic-mkoffload.c:465
+-#, fuzzy, gcc-internal-format
+-#| msgid "no input file specified"
++#, gcc-internal-format
+ msgid "output file not specified"
+-msgstr "no se especificaron ficheros de entrada"
++msgstr "no se ha especificado el fichero de salida"
+
+ #: config/i386/intelmic-mkoffload.c:558
+-#, fuzzy, gcc-internal-format
+-#| msgid "COLLECT_LTO_WRAPPER must be set"
++#, gcc-internal-format
+ msgid "COLLECT_GCC must be set"
+-msgstr "se debe definir COLLECT_LTO_WRAPPER"
++msgstr "se debe definir COLLECT_GCC"
+
+ #: config/i386/intelmic-mkoffload.c:563 config/nvptx/mkoffload.c:455
+-#, fuzzy, gcc-internal-format, gfc-internal-format
+-#| msgid "field %qs not found"
++#, gcc-internal-format, gfc-internal-format
+ msgid "offload compiler %s not found"
+-msgstr "no se encontró el campo %qs"
++msgstr "no se ha encontrado el compilador %s"
+
+ #: config/i386/intelmic-mkoffload.c:582 config/nvptx/mkoffload.c:475
+-#, fuzzy, gcc-internal-format
+-#| msgid "unrecognized argument in option %qs"
++#, gcc-internal-format
+ msgid "unrecognizable argument of option "
+-msgstr "no se reconoce el argumento en la opción %qs"
++msgstr "No se reconoce el argumento de la opción "
+
+ #: config/i386/winnt.c:79
+ #, gcc-internal-format
+@@ -28738,10 +28479,9 @@
+ msgstr "no se admite -falign-loops=%d"
+
+ #: config/m68k/m68k.c:649
+-#, fuzzy, gcc-internal-format
+-#| msgid "stack limits not supported on this target"
++#, gcc-internal-format
+ msgid "-fstack-limit- options are not supported on this cpu"
+-msgstr "no se admiten límites de la pila en este objetivo"
++msgstr "no se admiten las opciones -fstack-limit- en esta cpu"
+
+ #: config/m68k/m68k.c:767
+ #, gcc-internal-format
+@@ -28764,10 +28504,9 @@
+ msgstr "la variable inicializada %q+D se marcó como dllimport"
+
+ #: config/microblaze/microblaze.c:1690
+-#, fuzzy, gcc-internal-format
+-#| msgid "-fstack-protector not supported for this target"
++#, gcc-internal-format
+ msgid "-fPIC/-fpic not supported for this target"
+-msgstr "no se admite -fstack-protector para este objetivo"
++msgstr "no se admite -fPIC/-fpic para este objetivo"
+
+ #: config/microblaze/microblaze.c:1702
+ #, gcc-internal-format
+@@ -28780,10 +28519,9 @@
+ msgstr "sólo se puede usar -mxl-multiply-high con -mcpu=v6.00.a o superior"
+
+ #: config/microblaze/microblaze.c:1767
+-#, fuzzy, gcc-internal-format
+-#| msgid "-mxl-multiply-high can be used only with -mcpu=v6.00.a or greater"
++#, gcc-internal-format
+ msgid "-mxl-reorder can be used only with -mcpu=v8.30.a or greater"
+-msgstr "sólo se puede usar -mxl-multiply-high con -mcpu=v6.00.a o superior"
++msgstr "-mxl-reorder solo puede usarse con -mcpu=v8.30.a o superior"
+
+ #: config/microblaze/microblaze.c:1773
+ #, gcc-internal-format
+@@ -28801,10 +28539,9 @@
+ msgstr "el atributo %qs se aplica solamente a funciones"
+
+ #: config/mips/mips.c:1405 config/mips/mips.c:1411
+-#, fuzzy, gcc-internal-format
+-#| msgid "%qE cannot have both %<mips16%> and %<nomips16%> attributes"
++#, gcc-internal-format
+ msgid "%qE cannot have both %qs and %qs attributes"
+-msgstr "%qE no puede tener atributos %<mips16%> y %<nomips16%> al mismo tiempo"
++msgstr "%qE no puede tener los atributos %qs y %qs al mismo tiempo"
+
+ #: config/mips/mips.c:1440 config/mips/mips.c:1446 config/nios2/nios2.c:3994
+ #, gcc-internal-format
+@@ -28812,27 +28549,24 @@
+ msgstr "%qE se redeclaró con los atributos %qs en conflicto"
+
+ #: config/mips/mips.c:1478 config/mips/mips.c:1532
+-#, fuzzy, gcc-internal-format
+-#| msgid "%qE attribute requires a string constant argument"
++#, gcc-internal-format
+ msgid "%qE attribute requires a string argument"
+-msgstr "el atributo %qE requiere una constante entera como argumento"
++msgstr "el atributo %qE requiere una cadena como argumento"
+
+ #: config/mips/mips.c:1486
+-#, fuzzy, gcc-internal-format
+-#| msgid "argument to %qE attribute is neither zero, nor one"
++#, gcc-internal-format
+ msgid "argument to %qE attribute is neither eic, nor vector=<line>"
+-msgstr "el argumento del atributo %qE no es cero ni uno"
++msgstr "el argumento del atributo %qE no es ni eic ni vector=<línea>"
+
+ #: config/mips/mips.c:1502
+ #, gcc-internal-format
+ msgid "interrupt vector to %qE attribute is not vector=(sw0|sw1|hw0|hw1|hw2|hw3|hw4|hw5)"
+-msgstr ""
++msgstr "el vector de interrupciones para %qE no es vector=(sw0|sw1|hw0|hw1|hw2|hw3|hw4|hw5)"
+
+ #: config/mips/mips.c:1539
+-#, fuzzy, gcc-internal-format
+-#| msgid "argument of %qE attribute is not a string constant"
++#, gcc-internal-format
+ msgid "argument to %qE attribute is not intstack"
+-msgstr "el argumento del atributo %qE no es una cadena constante"
++msgstr "el argumento del atributo %qE no es intstack"
+
+ #: config/mips/mips.c:7692
+ #, gcc-internal-format
+@@ -28840,10 +28574,9 @@
+ msgstr "no se pueden manejar llamadas inconsistentes a %qs"
+
+ #: config/mips/mips.c:10928
+-#, fuzzy, gcc-internal-format
+-#| msgid "the %<interrupt%> attribute requires a MIPS32r2 processor"
++#, gcc-internal-format
+ msgid "the %<interrupt%> attribute requires a MIPS32r2 processor or greater"
+-msgstr "el atributo %<interrupt%> requiere un procesador MIPS32r2"
++msgstr "el atributo %<interrupt%> requiere un procesador MIPS32r2 o superior"
+
+ #: config/mips/mips.c:10930
+ #, gcc-internal-format
+@@ -28853,13 +28586,12 @@
+ #: config/mips/mips.c:11921
+ #, gcc-internal-format
+ msgid "-fstack-check=specific not implemented for MIPS16"
+-msgstr ""
++msgstr "-fstack-check=specific no implementado para MIPS16"
+
+ #: config/mips/mips.c:16838
+-#, fuzzy, gcc-internal-format, gfc-internal-format
+-#| msgid "argument must be a constant"
++#, gcc-internal-format, gfc-internal-format
+ msgid "argument %d to the built-in must be a constant in range %d to %d"
+-msgstr "el argumento debe ser una constante"
++msgstr "el argumento %d para la función interna debe ser una constante en el rango entre %d y %d"
+
+ #: config/mips/mips.c:16844 config/nds32/nds32-intrinsic.c:60
+ #: config/nds32/nds32-intrinsic.c:88 config/nds32/nds32-intrinsic.c:118
+@@ -28869,10 +28601,9 @@
+ msgstr "argumento no válido para la función interna"
+
+ #: config/mips/mips.c:16958
+-#, fuzzy, gcc-internal-format
+-#| msgid "failed to reclaim unneeded function"
++#, gcc-internal-format
+ msgid "failed to expand built-in function"
+-msgstr "falló al reclamar una función innecesaria"
++msgstr "fallo al expandir función interna"
+
+ #: config/mips/mips.c:17089
+ #, gcc-internal-format
+@@ -28900,10 +28631,9 @@
+ msgstr "código MIPS16 de coma flotante hard para ABIs diferentes de o32 y o64"
+
+ #: config/mips/mips.c:19443
+-#, fuzzy, gcc-internal-format
+-#| msgid "Generate MIPS16 code."
++#, gcc-internal-format
+ msgid "MSA MIPS16 code"
+-msgstr "Genera código MIPS16."
++msgstr "código MSA MIPS16"
+
+ #: config/mips/mips.c:19618 config/mips/mips.c:19623 config/mips/mips.c:19705
+ #: config/mips/mips.c:19707 config/mips/mips.c:19737 config/mips/mips.c:19747
+@@ -28938,10 +28668,9 @@
+ msgstr "se utiliza %<-mgp64%> con una ABI de 32-bit"
+
+ #: config/mips/mips.c:19702
+-#, fuzzy, gcc-internal-format
+-#| msgid "the %qs architecture does not support the synci instruction"
++#, gcc-internal-format
+ msgid "the %qs architecture does not support %<-mfp32%>"
+-msgstr "la arquitectura %qs no admite la instrucción synci"
++msgstr "la arquitectura %qs no admite %<-mfp32%>"
+
+ #: config/mips/mips.c:19711
+ #, gcc-internal-format
+@@ -28954,22 +28683,19 @@
+ msgstr "%<-mgp32%> y %<-mfp64%> sólo se pueden combinar al usar la ABI o32"
+
+ #: config/mips/mips.c:19735
+-#, fuzzy, gcc-internal-format
+-#| msgid "%<-mgp32%> and %<-mfp64%> can only be combined when using the o32 ABI"
++#, gcc-internal-format
+ msgid "%<-mfpxx%> can only be used with the o32 ABI"
+-msgstr "%<-mgp32%> y %<-mfp64%> sólo se pueden combinar al usar la ABI o32"
++msgstr "%<-mfpxx%> solo se puede usar con la ABI o32"
+
+ #: config/mips/mips.c:19739
+-#, fuzzy, gcc-internal-format
+-#| msgid "%<-mips3d%> requires %<-mpaired-single%>"
++#, gcc-internal-format
+ msgid "%<-march=%s%> requires %<-mfp32%>"
+-msgstr "%<-mips3d%> requiere %<-mpaired-single%>"
++msgstr "%<-march=%s%> requiere %<-mfp32%>"
+
+ #: config/mips/mips.c:19741
+-#, fuzzy, gcc-internal-format
+-#| msgid "%<-mips3d%> requires %<-mpaired-single%>"
++#, gcc-internal-format
+ msgid "%<-mfpxx%> requires %<-mlra%>"
+-msgstr "%<-mips3d%> requiere %<-mpaired-single%>"
++msgstr "%<-mfpxx%> requiere %<-mlra%>"
+
+ #: config/mips/mips.c:19757 config/mips/mips.c:19759 config/mips/mips.c:19772
+ #, gcc-internal-format
+@@ -28992,10 +28718,9 @@
+ msgstr "la arquitectura %qs no admite las instrucciones con probabilidad de ramificación"
+
+ #: config/mips/mips.c:19834
+-#, fuzzy, gcc-internal-format
+-#| msgid "the %qs architecture does not support the synci instruction"
++#, gcc-internal-format
+ msgid "the %qs architecture does not support madd or msub instructions"
+-msgstr "la arquitectura %qs no admite la instrucción synci"
++msgstr "la arquitectura %qs no admite las instrucciones madd ni msub"
+
+ #: config/mips/mips.c:19848
+ #, fuzzy, gcc-internal-format
+@@ -29004,28 +28729,24 @@
+ msgstr "la arquitectura %qs no admite las instrucciones par-sencillo"
+
+ #: config/mips/mips.c:19861 config/mips/mips.c:19867
+-#, fuzzy, gcc-internal-format
+-#| msgid "unsupported combination: %s"
++#, gcc-internal-format
+ msgid "unsupported combination: %qs%s %s"
+-msgstr "no se admite la combinación: %s"
++msgstr "no se admite la combinación: %qs%s %s"
+
+ #: config/mips/mips.c:19876
+-#, fuzzy, gcc-internal-format
+-#| msgid "unsupported combination: %s"
++#, gcc-internal-format
+ msgid "unsupported combination: %qs %s"
+-msgstr "no se admite la combinación: %s"
++msgstr "no se admite la combinación: %qs %s"
+
+ #: config/mips/mips.c:19891
+-#, fuzzy, gcc-internal-format
+-#| msgid "Generate position-independent code if possible (large mode)"
++#, gcc-internal-format
+ msgid "cannot generate position-independent code for %qs"
+-msgstr "Genera código independiente de posición si es posible (modo large)"
++msgstr "no se puede generar código independiente de posición para %qs"
+
+ #: config/mips/mips.c:19894
+-#, fuzzy, gcc-internal-format
+-#| msgid "Disable position-independent code (PIC) for use in OS kernel code"
++#, gcc-internal-format
+ msgid "position-independent code requires %qs"
+-msgstr "Desactiva el código independiente de posición (PIC) para su uso en código de núcleo de SO"
++msgstr "el código independiente de posición requiere %qs"
+
+ #: config/mips/mips.c:19927
+ #, gcc-internal-format
+@@ -29038,16 +28759,14 @@
+ msgstr "no se pueden usar accesos de data small para %qs"
+
+ #: config/mips/mips.c:19953
+-#, fuzzy, gcc-internal-format
+-#| msgid "the %qs architecture does not support paired-single instructions"
++#, gcc-internal-format
+ msgid "the %qs architecture does not support %<-m%s=legacy%>"
+-msgstr "la arquitectura %qs no admite las instrucciones par-sencillo"
++msgstr "la arquitectura %qs no admite %<-m%s=legacy%>"
+
+ #: config/mips/mips.c:19960
+-#, fuzzy, gcc-internal-format
+-#| msgid "the %qs architecture does not support the synci instruction"
++#, gcc-internal-format
+ msgid "the %qs architecture does not support %<-m%s=2008%>"
+-msgstr "la arquitectura %qs no admite la instrucción synci"
++msgstr "la arquitectura %qs no admite %<-m%s=2008%>"
+
+ #: config/mips/mips.c:19978
+ #, gcc-internal-format
+@@ -29060,10 +28779,9 @@
+ msgstr "%qs se debe usar con %qs"
+
+ #: config/mips/mips.c:19998
+-#, fuzzy, gcc-internal-format
+-#| msgid "-mips3d/-mpaired-single must be used with -mfp64 -mhard-float"
++#, gcc-internal-format
+ msgid "%<-mmsa%> must be used with %<-mfp64%> and %<-mhard-float%>"
+-msgstr "-mips3d/-mpaired-single se deben usar con -mfp64 -mhard-float"
++msgstr "%<-mmsa%> debe usarse con %<-mfp64%> y %<-mhard-float%>"
+
+ #: config/mips/mips.c:20005
+ #, gcc-internal-format
+@@ -29076,10 +28794,9 @@
+ msgstr "%qs requiere un objetivo que provea la instrucción %qs"
+
+ #: config/mips/mips.c:20025
+-#, fuzzy, gcc-internal-format
+-#| msgid "the %qs architecture does not support the synci instruction"
++#, gcc-internal-format
+ msgid "the %qs architecture does not support DSP instructions"
+-msgstr "la arquitectura %qs no admite la instrucción synci"
++msgstr "la arquitectura %qs no admite las instrucciones DSP"
+
+ #: config/mips/mips.c:20127
+ #, gcc-internal-format
+@@ -29155,22 +28872,22 @@
+ #: config/msp430/driver-msp430.c:659
+ #, gcc-internal-format, gfc-internal-format
+ msgid "unexpected argument to msp430_select_hwmult_lib: %s"
+-msgstr ""
++msgstr "argumento inesperado para msp430_select_hwmult_lib: %s"
+
+ #: config/msp430/driver-msp430.c:700
+ #, gcc-internal-format, gfc-internal-format
+ msgid "unrecognized hwpy field in msp430_mcu_data[%d]: %d"
+-msgstr ""
++msgstr "campo hwpy no reconocido en msp430_mcu_data[%d]: %d"
+
+ #: config/msp430/driver-msp430.c:707
+ #, gcc-internal-format, gfc-internal-format
+ msgid "unexpected first argument to msp430_select_hwmult_lib: %s"
+-msgstr ""
++msgstr "primer argumento inesperado para msp430_select_hwmult_lib: %s"
+
+ #: config/msp430/driver-msp430.c:711
+ #, gcc-internal-format
+ msgid "msp430_select_hwmult_lib needs one or more arguments"
+-msgstr ""
++msgstr "msp430_select_hwmult_lib necesita uno o más argumentos"
+
+ #: config/msp430/msp430.c:776
+ #, gcc-internal-format, gfc-internal-format
+@@ -29217,27 +28934,28 @@
+ "Unrecognized MCU name '%s', assuming that it just supports the MSP430 ISA.\n"
+ "Use the -mcpu option to set the ISA explicitly."
+ msgstr ""
++"No se reconoce el nombre MCU '%s'; se asume que solo admite el ISA MSP430.\n"
++"Utilice la opción -mcpu para poner el ISA explícitamente."
+
+ #: config/msp430/msp430.c:838
+-#, fuzzy, gcc-internal-format, gfc-internal-format
+-#| msgid "unrecognized register name %qs"
++#, gcc-internal-format, gfc-internal-format
+ msgid "Unrecognized MCU name '%s'."
+-msgstr "no se reconoce el nombre de registro %qs."
++msgstr "No se reconoce el nombre MCU '%s'."
+
+ #: config/msp430/msp430.c:847
+ #, gcc-internal-format
+ msgid "-mlarge requires a 430X-compatible -mmcu="
+-msgstr ""
++msgstr "-mlarge requiere una -mmcu= compatible con 430X"
+
+ #: config/msp430/msp430.c:850
+ #, gcc-internal-format
+ msgid "-mcode-region=upper requires 430X-compatible cpu"
+-msgstr ""
++msgstr "-mcode-region=upper requiere una -mmcu= compatible con 430X"
+
+ #: config/msp430/msp430.c:852
+ #, gcc-internal-format
+ msgid "-mdata-region=upper requires 430X-compatible cpu"
+-msgstr ""
++msgstr "-mdata-region=upper requiere una -mmcu= compatible con 430X"
+
+ #: config/msp430/msp430.c:1859
+ #, fuzzy, gcc-internal-format
+@@ -29246,16 +28964,14 @@
+ msgstr "argumento no válido del atributo %qE"
+
+ #: config/msp430/msp430.c:1868
+-#, fuzzy, gcc-internal-format
+-#| msgid "argument %d of %qE must be in the range %d...%d"
++#, gcc-internal-format
+ msgid "numeric argument of %qE attribute must be in range 0..63"
+-msgstr "el argumento %d de %qE debe estar dentro del rango %d...%d"
++msgstr "el argumento numérico del atributo %qE debe estar dentro del rango 0..63"
+
+ #: config/msp430/msp430.c:1874
+-#, fuzzy, gcc-internal-format
+-#| msgid "argument of %qE attribute is not a string constant"
++#, gcc-internal-format
+ msgid "argument of %qE attribute is not a string constant or number"
+-msgstr "el argumento del atributo %qE no es una cadena constante"
++msgstr "el argumento del atributo %qE no es una cadena constante ni un número"
+
+ #: config/msp430/msp430.c:2124
+ #, fuzzy, gcc-internal-format
+@@ -29264,10 +28980,9 @@
+ msgstr "no se puede establecer el atributo de interrupción: no hay una función actual"
+
+ #: config/msp430/msp430.c:2494
+-#, fuzzy, gcc-internal-format
+-#| msgid "%qE attribute allows only an integer constant argument"
++#, gcc-internal-format
+ msgid "__delay_cycles() only takes constant arguments"
+-msgstr "el atributo %qE sólo permite una constante entera como argumento"
++msgstr "__delay_cycles() solo toma argumentos constantes"
+
+ #: config/msp430/msp430.c:2504
#, fuzzy, gcc-internal-format
-@@ -29775,7 +29530,7 @@
+@@ -29775,7 +29490,7 @@
msgid "vec_cmpne only accepts 2 arguments"
msgstr "vec_insert sólo acepta 3 argumentos"
@@ -17527,7 +25218,7 @@ Index: gcc/po/es.po
#, fuzzy, gcc-internal-format
#| msgid "vec_insert only accepts 3 arguments"
msgid "vec_adde only accepts 3 arguments"
-@@ -29787,44 +29542,44 @@
+@@ -29787,44 +29502,44 @@
msgid "vec_addec only accepts 3 arguments"
msgstr "vec_insert sólo acepta 3 argumentos"
@@ -17580,7 +25271,7 @@ Index: gcc/po/es.po
#, fuzzy, gcc-internal-format, gfc-internal-format
#| msgid "invalid parameter combination for AltiVec intrinsic"
msgid "invalid parameter combination for AltiVec intrinsic %s"
-@@ -30935,112 +30690,112 @@
+@@ -30935,112 +30650,112 @@
msgid "requested %qE attribute is not a comma separated pair of non-negative integer constants or too large (max. %d)"
msgstr ""
@@ -17714,7 +25405,7 @@ Index: gcc/po/es.po
#, fuzzy, gcc-internal-format
#| msgid "argument to %qE attribute larger than %d"
msgid "argument to %qs is too large (max. %d)"
-@@ -31047,7 +30802,7 @@
+@@ -31047,7 +30762,7 @@
msgstr "el argumento para el atributo %qE es más grande que %d"
#. Value is not allowed for the target attribute.
@@ -24162,7 +31853,11 @@ Index: gcc/po/ChangeLog
===================================================================
--- a/src/gcc/po/ChangeLog (.../tags/gcc_7_1_0_release)
+++ b/src/gcc/po/ChangeLog (.../branches/gcc-7-branch)
-@@ -1,3 +1,40 @@
+@@ -1,3 +1,44 @@
++2017-07-31 Joseph Myers <joseph at codesourcery.com>
++
++ * es.po, uk.po: Update.
++
+2017-06-01 Joseph Myers <joseph at codesourcery.com>
+
+ * es.po: Update.
@@ -26352,15 +34047,73 @@ Index: gcc/po/uk.po
===================================================================
--- a/src/gcc/po/uk.po (.../tags/gcc_7_1_0_release)
+++ b/src/gcc/po/uk.po (.../branches/gcc-7-branch)
-@@ -7,7 +7,7 @@
+@@ -2,13 +2,13 @@
+ # Copyright (C) 2015 Free Software Foundation, Inc.
+ # This file is distributed under the same license as the gcc package.
+ #
+-# Yuri Chornoivan <yurchor at ukr.net>, 2015, 2016.
++# Yuri Chornoivan <yurchor at ukr.net>, 2015, 2016, 2017.
+ msgid ""
msgstr ""
- "Project-Id-Version: gcc 6.2.0\n"
+-"Project-Id-Version: gcc 6.2.0\n"
++"Project-Id-Version: gcc 7.1.0\n"
"Report-Msgid-Bugs-To: https://gcc.gnu.org/bugs/\n"
-"POT-Creation-Date: 2017-04-24 20:38+0000\n"
+-"PO-Revision-Date: 2016-08-24 18:46+0300\n"
+"POT-Creation-Date: 2017-05-01 22:24+0000\n"
- "PO-Revision-Date: 2016-08-24 18:46+0300\n"
++"PO-Revision-Date: 2017-07-18 13:34+0200\n"
"Last-Translator: Yuri Chornoivan <yurchor at ukr.net>\n"
"Language-Team: Ukrainian <translation-team-uk at lists.sourceforge.net>\n"
+ "Language: uk\n"
+@@ -17,7 +17,7 @@
+ "Content-Transfer-Encoding: 8bit\n"
+ "X-Bugs: Report translation errors to the Language-Team address.\n"
+ "Plural-Forms: nplurals=3; plural=(n%10==1 && n%100!=11 ? 0 : n%10>=2 && n%10<=4 && (n%100<10 || n%100>=20) ? 1 : 2);\n"
+-"X-Generator: Lokalize 1.5\n"
++"X-Generator: Lokalize 2.0\n"
+
+ #: cfgrtl.c:2661
+ msgid "flow control insn inside a basic block"
+@@ -65,9 +65,9 @@
+ #, c-format
+ msgid "%d frame table found\n"
+ msgid_plural "%d frame tables found\n"
+-msgstr[0] ""
+-msgstr[1] ""
+-msgstr[2] ""
++msgstr[0] "знайдено %d таблицю кадрів\n"
++msgstr[1] "знайдено %d таблиці кадрів\n"
++msgstr[2] "знайдено %d таблиць кадрів\n"
+
+ #: collect2.c:1836
+ #, c-format
+@@ -94,7 +94,7 @@
+
+ #: cprop.c:1756
+ msgid "const/copy propagation disabled"
+-msgstr ""
++msgstr "передавання const/copy вимкнено"
+
+ #: diagnostic.c:224
+ #, c-format
+@@ -1042,7 +1042,7 @@
+ #: gimple-ssa-isolate-paths.c:526 gimple-ssa-isolate-paths.c:410
+ #, gcc-internal-format
+ msgid "function may return address of local variable"
+-msgstr ""
++msgstr "функція може повертати адресу локальної змінної"
+
+ #: incpath.c:72
+ #, c-format
+@@ -1091,7 +1091,7 @@
+ #: langhooks.c:386 cp/error.c:3372
+ #, c-format
+ msgid "In member function %qs"
+-msgstr ""
++msgstr "У функції-члені %qs"
+
+ #: langhooks.c:390 cp/error.c:3375
+ #, c-format
@@ -2735,42 +2735,42 @@
msgid "<command-line>"
msgstr ""
@@ -26416,6 +34169,96 @@ Index: gcc/po/uk.po
#, c-format
msgid "invalid operand prefix '%%%c'"
msgstr ""
+@@ -2779,75 +2779,75 @@
+ #: config/rs6000/rs6000.c:23938 config/sparc/sparc.c:8854
+ #, c-format
+ msgid "'%%&' used without any local dynamic TLS references"
+-msgstr ""
++msgstr "'%%&' використано без будь-яких локальних динамічних посилань TLS"
+
+ #: config/alpha/alpha.c:5150 config/bfin/bfin.c:1424
+ #, c-format
+ msgid "invalid %%J value"
+-msgstr ""
++msgstr "некоректне значення %%J"
+
+ #: config/alpha/alpha.c:5180 config/ia64/ia64.c:5488
+ #, c-format
+ msgid "invalid %%r value"
+-msgstr ""
++msgstr "некоректне значення %%r"
+
+ #: config/alpha/alpha.c:5190 config/ia64/ia64.c:5442
+ #: config/rs6000/rs6000.c:23618 config/xtensa/xtensa.c:2363
+ #, c-format
+ msgid "invalid %%R value"
+-msgstr ""
++msgstr "некоректне значення %%R"
+
+ #: config/alpha/alpha.c:5196 config/rs6000/rs6000.c:23538
+ #: config/xtensa/xtensa.c:2330
+ #, c-format
+ msgid "invalid %%N value"
+-msgstr ""
++msgstr "некоректне значення %%N"
+
+ #: config/alpha/alpha.c:5204 config/rs6000/rs6000.c:23566
+ #, c-format
+ msgid "invalid %%P value"
+-msgstr ""
++msgstr "некоректне значення %%P"
+
+ #: config/alpha/alpha.c:5212
+ #, c-format
+ msgid "invalid %%h value"
+-msgstr ""
++msgstr "некоректне значення %%h"
+
+ #: config/alpha/alpha.c:5220 config/xtensa/xtensa.c:2356
+ #, c-format
+ msgid "invalid %%L value"
+-msgstr ""
++msgstr "некоректне значення %%L"
+
+ #: config/alpha/alpha.c:5239
+ #, c-format
+ msgid "invalid %%m value"
+-msgstr ""
++msgstr "некоректне значення %%m"
+
+ #: config/alpha/alpha.c:5245
+ #, c-format
+ msgid "invalid %%M value"
+-msgstr ""
++msgstr "некоректне значення %%M"
+
+ #: config/alpha/alpha.c:5282
+ #, c-format
+ msgid "invalid %%U value"
+-msgstr ""
++msgstr "некоректне значення %%U"
+
+ #: config/alpha/alpha.c:5290 config/alpha/alpha.c:5301
+ #: config/rs6000/rs6000.c:23626
+ #, c-format
+ msgid "invalid %%s value"
+-msgstr ""
++msgstr "некоректне значення %%s"
+
+ #: config/alpha/alpha.c:5312
+ #, c-format
+ msgid "invalid %%C value"
+-msgstr ""
++msgstr "некоректне значення %%C"
+
+ #: config/alpha/alpha.c:5349 config/rs6000/rs6000.c:23402
+ #, c-format
+ msgid "invalid %%E value"
+-msgstr ""
++msgstr "некоректне значення %%E"
+
+ #: config/alpha/alpha.c:5374 config/alpha/alpha.c:5424
+ #, c-format
@@ -2928,29 +2928,29 @@
msgid "invalid UNSPEC as operand: %d"
msgstr ""
@@ -26473,7 +34316,69 @@ Index: gcc/po/uk.po
#, c-format
msgid "obsolete Maverick format code '%c'"
msgstr ""
-@@ -3774,98 +3774,98 @@
+@@ -3041,24 +3041,20 @@
+ msgstr ""
+
+ #: config/avr/avr.c:9808
+-#, fuzzy
+-#| msgid "expected function name"
+ msgid "function parameter"
+-msgstr "мало бути вказано назву функції"
++msgstr "параметр функції"
+
+ #: config/avr/avr.c:9813
+ msgid "structure field"
+-msgstr ""
++msgstr "поле структури"
+
+ #: config/avr/avr.c:9819
+ msgid "return type of function"
+-msgstr ""
++msgstr "тип значення, яке повертає функція"
+
+ #: config/avr/avr.c:9824
+-#, fuzzy
+-#| msgid "null pointer"
+ msgid "pointer"
+-msgstr "нульовий вказівник"
++msgstr "вказівник"
+
+ #: config/avr/driver-avr.c:48
+ #, c-format
+@@ -3645,27 +3641,27 @@
+
+ #: config/rs6000/rs6000.c:23199
+ msgid "Bad 128-bit move"
+-msgstr ""
++msgstr "Помилкове 128-бітове пересування"
+
+ #: config/rs6000/rs6000.c:23390
+ #, c-format
+ msgid "invalid %%e value"
+-msgstr ""
++msgstr "некоректне значення %%e"
+
+ #: config/rs6000/rs6000.c:23411
+ #, c-format
+ msgid "invalid %%f value"
+-msgstr ""
++msgstr "некоректне значення %%f"
+
+ #: config/rs6000/rs6000.c:23420
+ #, c-format
+ msgid "invalid %%F value"
+-msgstr ""
++msgstr "некоректне значення %%F"
+
+ #: config/rs6000/rs6000.c:23429
+ #, c-format
+ msgid "invalid %%G value"
+-msgstr ""
++msgstr "некоректне значення %%G"
+
+ #: config/rs6000/rs6000.c:23464
+ #, c-format
+@@ -3774,98 +3770,98 @@
msgid "emit_fusion_p9_store not MEM"
msgstr ""
@@ -26592,7 +34497,409 @@ Index: gcc/po/uk.po
msgid "binary operator does not support mixing vector bool with floating point vector operands"
msgstr ""
-@@ -17225,7 +17225,7 @@
+@@ -4311,10 +4307,8 @@
+ msgstr "мало бути %<<%>"
+
+ #: c/gimple-parser.c:1428 c/gimple-parser.c:1455 c/gimple-parser.c:1483
+-#, fuzzy
+-#| msgid "expected %<__label__%>"
+ msgid "expected label"
+-msgstr "мало бути %<__label__%>"
++msgstr "мало бути вказано мітку"
+
+ #: cp/call.c:9927
+ msgid "candidate 1:"
+@@ -4342,7 +4336,7 @@
+
+ #: cp/error.c:421
+ msgid "<unresolved overloaded function type>"
+-msgstr ""
++msgstr "<невизначений перевантажений тип функції>"
+
+ #: cp/error.c:583
+ msgid "<type error>"
+@@ -4351,13 +4345,12 @@
+ #: cp/error.c:684 objc/objc-act.c:6180 cp/cxx-pretty-print.c:161
+ #, gcc-internal-format
+ msgid "<unnamed>"
+-msgstr ""
++msgstr "<неназваний>"
+
+ #: cp/error.c:686
+-#, fuzzy, c-format
+-#| msgid "<anonymous %s>"
++#, c-format
+ msgid "<unnamed %s>"
+-msgstr "<анонімний %s>"
++msgstr "<неназваний %s>"
+
+ #. A lambda's "type" is essentially its signature.
+ #: cp/error.c:691
+@@ -5302,10 +5295,8 @@
+ msgstr ""
+
+ #: config/darwin.h:171
+-#, fuzzy
+-#| msgid "%<-Wabi=1%> is not supported, using =2"
+ msgid "rdynamic is not supported"
+-msgstr "Підтримки %<-Wabi=1%> не передбачено, використовуємо =2"
++msgstr "підтримки rdynamic не передбачено"
+
+ #: config/darwin.h:260
+ msgid "-current_version only allowed with -dynamiclib"
+@@ -5498,11 +5489,11 @@
+
+ #: objc/lang-specs.h:55
+ msgid "objc-cpp-output is deprecated; please use objective-c-cpp-output instead"
+-msgstr ""
++msgstr "objc-cpp-output вважається застарілим; будь ласка, скористайтеся замість нього objective-c-cpp-output"
+
+ #: objcp/lang-specs.h:58
+ msgid "objc++-cpp-output is deprecated; please use objective-c++-cpp-output instead"
+-msgstr ""
++msgstr "objc++-cpp-output вважається застарілим; будь ласка, скористайтеся замість нього objective-c++-cpp-output"
+
+ #: fortran/lang.opt:146
+ msgid "-J<directory>\tPut MODULE files in 'directory'."
+@@ -6104,11 +6095,11 @@
+
+ #: c-family/c.opt:300 ada/gcc-interface/lang.opt:57
+ msgid "Enable most warning messages."
+-msgstr ""
++msgstr "Увімкнути якнайбільше повідомлень із попередженнями."
+
+ #: c-family/c.opt:304
+ msgid "Warn on any use of alloca."
+-msgstr ""
++msgstr "Попереджати про усі використання alloca."
+
+ #: c-family/c.opt:308
+ msgid "-Walloc-size-larger-than=<bytes> Warn for calls to allocation functions that attempt to allocate objects larger than the specified number of bytes."
+@@ -6128,7 +6119,7 @@
+
+ #: c-family/c.opt:335
+ msgid "Warn about casting functions to incompatible types."
+-msgstr ""
++msgstr "Попереджати про виклик функцій із несумісними типами параметрів."
+
+ #: c-family/c.opt:339
+ msgid "Warn about boolean expression compared with an integer value different from true/false."
+@@ -6135,10 +6126,8 @@
+ msgstr ""
+
+ #: c-family/c.opt:343
+-#, fuzzy
+-#| msgid "Warn about creation of array temporaries."
+ msgid "Warn about certain operations on boolean expressions."
+-msgstr "Попереджати щодо створення тимчасових масивів."
++msgstr "Попереджати щодо певних дій із булевими виразами."
+
+ #: c-family/c.opt:347
+ msgid "Warn when __builtin_frame_address or __builtin_return_address is used unsafely."
+@@ -6198,7 +6187,7 @@
+
+ #: c-family/c.opt:409
+ msgid "Synonym for -Wcomment."
+-msgstr ""
++msgstr "Синонім -Wcomment."
+
+ #: c-family/c.opt:413
+ msgid "Warn for conditionally-supported constructs."
+@@ -6206,7 +6195,7 @@
+
+ #: c-family/c.opt:417
+ msgid "Warn for implicit type conversions that may change a value."
+-msgstr ""
++msgstr "Попереджати про неявні перетворення типів, які можуть призвести до зміни значення."
+
+ #: c-family/c.opt:421
+ msgid "Warn for converting NULL from/to a non-pointer type."
+@@ -6214,7 +6203,7 @@
+
+ #: c-family/c.opt:429
+ msgid "Warn when all constructors and destructors are private."
+-msgstr ""
++msgstr "Попереджати, якщо усі конструктори і деструктори є закритими (private)."
+
+ #: c-family/c.opt:433
+ msgid "Warn about dangling else."
+@@ -6226,11 +6215,11 @@
+
+ #: c-family/c.opt:441
+ msgid "Warn when a declaration is found after a statement."
+-msgstr ""
++msgstr "Попереджати, якщо оголошення виявлено після інструкції."
+
+ #: c-family/c.opt:445
+ msgid "Warn when deleting a pointer to incomplete type."
+-msgstr ""
++msgstr "Попереджати щодо вилучення вказівника на неповний тип."
+
+ #: c-family/c.opt:449
+ msgid "Warn about deleting polymorphic objects with non-virtual destructors."
+@@ -6238,7 +6227,7 @@
+
+ #: c-family/c.opt:453
+ msgid "Warn if a deprecated compiler feature, class, method, or field is used."
+-msgstr ""
++msgstr "Попереджати щодо використання застарілої можливості компілятора, застарілого класу, методу або поля."
+
+ #: c-family/c.opt:457
+ msgid "Warn about positional initialization of structs requiring designated initializers."
+@@ -6258,19 +6247,19 @@
+
+ #: c-family/c.opt:473
+ msgid "Warn about duplicated branches in if-else statements."
+-msgstr ""
++msgstr "Попереджати про дублювання гілок у інструкціях if-else."
+
+ #: c-family/c.opt:477
+ msgid "Warn about duplicated conditions in an if-else-if chain."
+-msgstr ""
++msgstr "Попереджати про дублювання умов у ланцюжку if-else-if."
+
+ #: c-family/c.opt:481
+ msgid "Warn about violations of Effective C++ style rules."
+-msgstr ""
++msgstr "Попереджати про порушення правил стилю Effective C++."
+
+ #: c-family/c.opt:485
+ msgid "Warn about an empty body in an if or else statement."
+-msgstr ""
++msgstr "Попереджати щодо порожнього комплекту інструкцій у if або else."
+
+ #: c-family/c.opt:489
+ msgid "Warn about stray tokens after #else and #endif."
+@@ -6278,11 +6267,11 @@
+
+ #: c-family/c.opt:493
+ msgid "Warn about comparison of different enum types."
+-msgstr ""
++msgstr "Попереджати про порівняння різних типів числових даних."
+
+ #: c-family/c.opt:501
+ msgid "This switch is deprecated; use -Werror=implicit-function-declaration instead."
+-msgstr ""
++msgstr "Цей перемикач вважається застарілим; скористайтеся замість нього перемикачем -Werror=implicit-function-declaration."
+
+ #: c-family/c.opt:509
+ msgid "Warn for implicit type conversions that cause loss of floating point precision."
+@@ -6290,15 +6279,15 @@
+
+ #: c-family/c.opt:513
+ msgid "Warn if testing floating point numbers for equality."
+-msgstr ""
++msgstr "Попереджати про перевірки на рівність чисел із рухомою крапкою."
+
+ #: c-family/c.opt:517 c-family/c.opt:559
+ msgid "Warn about printf/scanf/strftime/strfmon format string anomalies."
+-msgstr ""
++msgstr "Попереджати про некоректності у рядках форматування printf/scanf/strftime/strfmon."
+
+ #: c-family/c.opt:521
+ msgid "Warn about format strings that contain NUL bytes."
+-msgstr ""
++msgstr "Попереджати щодо рядків форматування, які містять байти NUL."
+
+ #: c-family/c.opt:525
+ msgid "Warn if passing too many arguments to a function for its format string."
+@@ -6306,7 +6295,7 @@
+
+ #: c-family/c.opt:529
+ msgid "Warn about format strings that are not literals."
+-msgstr ""
++msgstr "Попереджати, якщо рядки форматування не є літералами."
+
+ #: c-family/c.opt:533
+ msgid "Warn about function calls with format strings that write past the end of the destination region. Same as -Wformat-overflow=1."
+@@ -6318,7 +6307,7 @@
+
+ #: c-family/c.opt:542
+ msgid "Warn about sign differences with format functions."
+-msgstr ""
++msgstr "Попереджати про відмінності у знаку у функціях форматування."
+
+ #: c-family/c.opt:546
+ msgid "Warn about calls to snprintf and similar functions that truncate output. Same as -Wformat-truncation=1."
+@@ -6330,7 +6319,7 @@
+
+ #: c-family/c.opt:555
+ msgid "Warn about zero-length formats."
+-msgstr ""
++msgstr "Попереджати про формати нульової довжини."
+
+ #: c-family/c.opt:563
+ msgid "Warn about function calls with format strings that write past the end of the destination region."
+@@ -6346,7 +6335,7 @@
+
+ #: c-family/c.opt:576
+ msgid "Warn whenever attributes are ignored."
+-msgstr ""
++msgstr "Попереджати про ігнорування атрибутів."
+
+ #: c-family/c.opt:580
+ msgid "Warn when there is a conversion between pointers that have incompatible types."
+@@ -6354,27 +6343,27 @@
+
+ #: c-family/c.opt:584
+ msgid "Warn about variables which are initialized to themselves."
+-msgstr ""
++msgstr "Попереджати про самоініціалізацію змінних."
+
+ #: c-family/c.opt:588
+ msgid "Warn about implicit declarations."
+-msgstr ""
++msgstr "Попереджати про неявні оголошення."
+
+ #: c-family/c.opt:596
+ msgid "Warn about implicit conversions from \"float\" to \"double\"."
+-msgstr ""
++msgstr "Попереджати про неявні перетворення з float на double."
+
+ #: c-family/c.opt:600
+ msgid "Warn if \"defined\" is used outside #if."
+-msgstr ""
++msgstr "Попереджати, якщо defined використано поза #if."
+
+ #: c-family/c.opt:604
+ msgid "Warn about implicit function declarations."
+-msgstr ""
++msgstr "Попереджати про неявні оголошення функцій."
+
+ #: c-family/c.opt:608
+ msgid "Warn when a declaration does not specify a type."
+-msgstr ""
++msgstr "Попереджати, якщо оголошення не визначає типу."
+
+ #: c-family/c.opt:615
+ msgid "Warn about C++11 inheriting constructors when the base has a variadic constructor."
+@@ -8855,7 +8844,7 @@
+
+ #: config/i386/i386.opt:315
+ msgid "%<-mcpu=%> is deprecated; use %<-mtune=%> or %<-march=%> instead"
+-msgstr ""
++msgstr "%<-mcpu=%> вважається застарілим; скористайтеся замість нього %<-mtune=%> або %<-march=%>"
+
+ #: config/i386/i386.opt:319
+ msgid "Generate sin, cos, sqrt for FPU."
+@@ -11587,7 +11576,7 @@
+
+ #: config/fused-madd.opt:22
+ msgid "%<-mfused-madd%> is deprecated; use %<-ffp-contract=%> instead"
+-msgstr ""
++msgstr "%<-mfused-madd%> вважається застарілим; скористайтеся замість нього %<-ffp-contract=%>"
+
+ #: config/sol2.opt:32
+ msgid "Clear hardware capabilities when linking."
+@@ -11644,7 +11633,7 @@
+ #: config/microblaze/microblaze.opt:87
+ #, c-format
+ msgid "%qs is deprecated; use -fstack-check"
+-msgstr ""
++msgstr "%qs вважається застарілим; скористайтеся -fstack-check"
+
+ #: config/microblaze/microblaze.opt:88
+ msgid "Check for stack overflow at runtime."
+@@ -12780,7 +12769,7 @@
+ #: config/arc/arc.opt:356 config/arc/arc.opt:373
+ #, c-format
+ msgid "%qs is deprecated"
+-msgstr ""
++msgstr "%qs вважається застарілим"
+
+ #: config/arc/arc.opt:170
+ msgid "Do not generate mpy instructions for ARC700."
+@@ -13437,17 +13426,15 @@
+
+ #: common.opt:1065
+ msgid "Check the return value of new in C++."
+-msgstr ""
++msgstr "Перевіряти повернуте значення new у C++."
+
+ #: common.opt:1069 common.opt:1073
+ msgid "Perform internal consistency checkings."
+-msgstr ""
++msgstr "Виконувати внутрішні перевірки сумісності."
+
+ #: common.opt:1077
+-#, fuzzy
+-#| msgid "Enable debug output."
+ msgid "Enable code hoisting."
+-msgstr "Увімкнути виведення діагностичних даних."
++msgstr "Увімкнути підняття коду."
+
+ #: common.opt:1081
+ msgid "Looks for opportunities to reduce stack adjustments and stack references."
+@@ -15438,10 +15425,9 @@
+ msgstr ""
+
+ #: auto-profile.c:920
+-#, fuzzy, gcc-internal-format, gfc-internal-format
+-#| msgid "can't open input file: %s"
++#, gcc-internal-format, gfc-internal-format
+ msgid "cannot open profile file %s"
+-msgstr "не вдалося відкрити вхідний файл %s"
++msgstr "не вдалося відкрити файл профілювання %s"
+
+ #: auto-profile.c:926
+ #, gcc-internal-format
+@@ -15454,22 +15440,19 @@
+ msgstr ""
+
+ #: auto-profile.c:946
+-#, fuzzy, gcc-internal-format, gfc-internal-format
+-#| msgid "cannot read %s: %m"
++#, gcc-internal-format, gfc-internal-format
+ msgid "cannot read string table from %s"
+-msgstr "не вдалося прочитати %s: %m"
++msgstr "не вдалося прочитати таблицю рядків з %s"
+
+ #: auto-profile.c:954
+-#, fuzzy, gcc-internal-format, gfc-internal-format
+-#| msgid "cannot call function %qD"
++#, gcc-internal-format, gfc-internal-format
+ msgid "cannot read function profile from %s"
+-msgstr "не вдалося викликати функцію %qD"
++msgstr "не вдалося прочитати профіль функції з %s"
+
+ #: auto-profile.c:964
+-#, fuzzy, gcc-internal-format, gfc-internal-format
+-#| msgid "cannot read %s: %m"
++#, gcc-internal-format, gfc-internal-format
+ msgid "cannot read working set from %s"
+-msgstr "не вдалося прочитати %s: %m"
++msgstr "не вдалося прочитати робочий набір з %s"
+
+ #: bt-load.c:1564
+ #, gcc-internal-format
+@@ -15765,21 +15748,19 @@
+ msgstr ""
+
+ #: calls.c:1491
+-#, fuzzy, gcc-internal-format
+-#| msgid "cannot call function %qD"
++#, gcc-internal-format
+ msgid "in a call to built-in allocation function %qD"
+-msgstr "не вдалося викликати функцію %qD"
++msgstr "у виклику до вбудованої функції розподілу пам'яті %qD"
+
+ #: calls.c:1494
+ #, gcc-internal-format
+ msgid "in a call to allocation function %qD declared here"
+-msgstr ""
++msgstr "у виклику до функції отримання області пам'яті %qD оголошено тут"
+
+ #: calls.c:1508
+-#, fuzzy, gcc-internal-format, gfc-internal-format
+-#| msgid "[cannot find %s]"
++#, gcc-internal-format, gfc-internal-format
+ msgid "cannot tail-call: %s"
+-msgstr "[не вдалося знайти %s]"
++msgstr "хвостовий виклик неможливий: %s"
+
+ #: calls.c:3071
+ #, gcc-internal-format
+@@ -17225,7 +17206,7 @@
msgid "assuming signed overflow does not occur when combining constants around a comparison"
msgstr ""
@@ -26601,7 +34908,7 @@ Index: gcc/po/uk.po
#, gcc-internal-format
msgid "fold check: original tree changed by fold"
msgstr ""
-@@ -17761,8 +17761,8 @@
+@@ -17761,8 +17742,8 @@
msgid "null pointer dereference"
msgstr "розіменування нульового вказівника"
@@ -26612,7 +34919,16 @@ Index: gcc/po/uk.po
#: c/c-typeck.c:9930 c/gimple-parser.c:1556 c/gimple-parser.c:1564
#: cp/call.c:6454 cp/call.c:7933 cp/constexpr.c:777 cp/constexpr.c:2174
#: cp/cvt.c:992 cp/cvt.c:1019 cp/decl.c:7224 cp/decl2.c:5072 cp/pt.c:7993
-@@ -17776,299 +17776,299 @@
+@@ -17769,7 +17750,7 @@
+ #: cp/semantics.c:1764 cp/typeck.c:1648 cp/typeck.c:1843 cp/typeck.c:3718
+ #, gcc-internal-format
+ msgid "declared here"
+-msgstr ""
++msgstr "оголошено тут"
+
+ #: gimple-ssa-nonnull-compare.c:102
+ #, gcc-internal-format
+@@ -17776,299 +17757,297 @@
msgid "nonnull argument %qD compared to NULL"
msgstr ""
@@ -26893,11 +35209,13 @@ Index: gcc/po/uk.po
msgstr ""
-#: gimple-ssa-sprintf.c:2775
+-#, fuzzy, gcc-internal-format
+-#| msgid "unexpected argument"
+#: gimple-ssa-sprintf.c:2776
- #, fuzzy, gcc-internal-format
- #| msgid "unexpected argument"
++#, gcc-internal-format
msgid "directive argument %qE"
- msgstr "несподіваний аргумент"
+-msgstr "несподіваний аргумент"
++msgstr "аргумент директиви %qE"
-#: gimple-ssa-sprintf.c:2777
+#: gimple-ssa-sprintf.c:2778
@@ -26954,11 +35272,13 @@ Index: gcc/po/uk.po
msgstr ""
-#: gimple-ssa-sprintf.c:3647
+-#, fuzzy, gcc-internal-format
+-#| msgid "null pointer"
+#: gimple-ssa-sprintf.c:3650
- #, fuzzy, gcc-internal-format
- #| msgid "null pointer"
++#, gcc-internal-format
msgid "null destination pointer"
- msgstr "нульовий вказівник"
+-msgstr "нульовий вказівник"
++msgstr "нульовий вказівник призначення"
-#: gimple-ssa-sprintf.c:3664
+#: gimple-ssa-sprintf.c:3667
@@ -26971,7 +35291,59 @@ Index: gcc/po/uk.po
#, gcc-internal-format
msgid "null format string"
msgstr ""
-@@ -20241,157 +20241,157 @@
+@@ -18224,10 +18203,9 @@
+ msgstr ""
+
+ #: gimplify.c:6852
+-#, fuzzy, gcc-internal-format
+-#| msgid "%qs tag used in naming %q#T"
++#, gcc-internal-format
+ msgid "%qE not specified in enclosing %qs"
+-msgstr "теґ %qs використано у назві %q#T"
++msgstr "%qE не задано у замиканні %qs"
+
+ #: gimplify.c:6854
+ #, gcc-internal-format
+@@ -19547,10 +19525,9 @@
+ msgstr ""
+
+ #: opts.c:976
+-#, fuzzy, gcc-internal-format, gfc-internal-format
+-#| msgid "%<-fabi-compat-version=1%> is not supported, using =2"
++#, gcc-internal-format, gfc-internal-format
+ msgid "-fsanitize-recover=%s is not supported"
+-msgstr "Підтримки %<-fabi-compat-version=1%> не передбачено, використовуємо =2"
++msgstr "підтримки -fsanitize-recover=%s не передбачено"
+
+ #: opts.c:1005
+ #, gcc-internal-format
+@@ -19623,10 +19600,9 @@
+ msgstr ""
+
+ #: opts.c:2371
+-#, fuzzy, gcc-internal-format
+-#| msgid "invalid --param name %qs"
++#, gcc-internal-format
+ msgid "invalid --param name %qs; did you mean %qs?"
+-msgstr "некоректна назва --param %qs"
++msgstr "некоректна назва --param %qs; ви мали на увазі %qs?"
+
+ #: opts.c:2374
+ #, gcc-internal-format
+@@ -19914,10 +19890,9 @@
+ msgstr ""
+
+ #: read-rtl-function.c:1575
+-#, fuzzy, gcc-internal-format, gfc-internal-format
+-#| msgid "duplicate definition of '%s'"
++#, gcc-internal-format, gfc-internal-format
+ msgid "duplicate insn UID: %i"
+-msgstr "повторне визначення «%s»"
++msgstr "UID інструкції-дубліката: %i"
+
+ #: read-rtl-function.c:1635
+ #, gcc-internal-format
+@@ -20241,157 +20216,157 @@
msgid "%D renamed after being referenced in assembly"
msgstr ""
@@ -27160,7 +35532,49 @@ Index: gcc/po/uk.po
#, gcc-internal-format
msgid "section of alias %q+D must match section of its target"
msgstr ""
-@@ -22054,8 +22054,8 @@
+@@ -21525,17 +21500,17 @@
+ #: tree-diagnostic.c:202
+ #, gcc-internal-format
+ msgid "in definition of macro %qs"
+-msgstr ""
++msgstr "у оголошенні макросу %qs"
+
+ #: tree-diagnostic.c:219
+ #, gcc-internal-format
+ msgid "in expansion of macro %qs"
+-msgstr ""
++msgstr "у розгортанні макросу %qs"
+
+ #: tree-eh.c:4669
+ #, gcc-internal-format, gfc-internal-format
+ msgid "BB %i has multiple EH edges"
+-msgstr ""
++msgstr "BB %i має декілька країв EH"
+
+ #: tree-eh.c:4681
+ #, gcc-internal-format, gfc-internal-format
+@@ -21679,16 +21654,14 @@
+ msgstr ""
+
+ #: tree-ssa-ccp.c:3427
+-#, fuzzy, gcc-internal-format
+-#| msgid "cannot call function %qD"
++#, gcc-internal-format
+ msgid "in a call to built-in function %qD"
+-msgstr "не вдалося викликати функцію %qD"
++msgstr "у виклику вбудованої функції %qD"
+
+ #: tree-ssa-ccp.c:3431
+-#, fuzzy, gcc-internal-format
+-#| msgid "cannot call function %qD"
++#, gcc-internal-format
+ msgid "in a call to function %qD declared here"
+-msgstr "не вдалося викликати функцію %qD"
++msgstr "у виклику функції %qD, оголошено тут"
+
+ #: tree-ssa-loop-niter.c:2367
+ #, gcc-internal-format
+@@ -22054,8 +22027,8 @@
#: c-family/c-attribs.c:2898 c-family/c-attribs.c:2937
#: c-family/c-attribs.c:3019 c-family/c-attribs.c:3062
#: c-family/c-attribs.c:3078 c-family/c-attribs.c:3172
@@ -27171,7 +35585,7 @@ Index: gcc/po/uk.po
#: config/h8300/h8300.c:5480 config/h8300/h8300.c:5504 config/i386/i386.c:7715
#: config/i386/i386.c:41425 config/ia64/ia64.c:762
#: config/rs6000/rs6000.c:35369 config/spu/spu.c:3741
-@@ -22091,92 +22091,92 @@
+@@ -22091,95 +22064,95 @@
msgid "%qE implies default visibility, but %qD has already been declared with a different visibility"
msgstr ""
@@ -27251,38 +35665,47 @@ Index: gcc/po/uk.po
+#: tree.c:12875
#, gcc-internal-format
msgid "%qD is deprecated: %s"
- msgstr ""
+-msgstr ""
++msgstr "%qD вважається застарілим: %s"
-#: tree.c:12870
+#: tree.c:12878
#, gcc-internal-format
msgid "%qD is deprecated"
- msgstr ""
+-msgstr ""
++msgstr "%qD вважається застарілим"
-#: tree.c:12894 tree.c:12916
+#: tree.c:12902 tree.c:12924
#, gcc-internal-format
msgid "%qE is deprecated: %s"
- msgstr ""
+-msgstr ""
++msgstr "%qE вважається застарілим: %s"
-#: tree.c:12897 tree.c:12919
+#: tree.c:12905 tree.c:12927
#, gcc-internal-format
msgid "%qE is deprecated"
- msgstr ""
+-msgstr ""
++msgstr "%qE вважається застарілим"
-#: tree.c:12903 tree.c:12924
+#: tree.c:12911 tree.c:12932
#, gcc-internal-format, gfc-internal-format
msgid "type is deprecated: %s"
- msgstr ""
+-msgstr ""
++msgstr "тип вважається застарілим: %s"
-#: tree.c:12906 tree.c:12927
+#: tree.c:12914 tree.c:12935
#, gcc-internal-format
msgid "type is deprecated"
- msgstr ""
-@@ -22203,262 +22203,262 @@
+-msgstr ""
++msgstr "тип вважається застарілим"
+
+ #. Type variant can differ by:
+ #.
+@@ -22203,262 +22176,262 @@
#. main variant only.
#.
#. Convenience macro for matching individual fields.
@@ -27597,7 +36020,34 @@ Index: gcc/po/uk.po
#, gcc-internal-format
msgid "verify_type failed"
msgstr "помилка verify_type"
-@@ -23455,13 +23455,13 @@
+@@ -23358,7 +23331,7 @@
+ #: c-family/c-common.c:4869
+ #, gcc-internal-format
+ msgid "pointers are not permitted as case values"
+-msgstr ""
++msgstr "вказівники не можуть бути значеннями випадків"
+
+ #: c-family/c-common.c:4876
+ #, gcc-internal-format
+@@ -23373,7 +23346,7 @@
+ #: c-family/c-common.c:4963
+ #, gcc-internal-format
+ msgid "duplicate (or overlapping) case value"
+-msgstr ""
++msgstr "дублювання (або перекривання) значення випадку"
+
+ #: c-family/c-common.c:4965
+ #, gcc-internal-format
+@@ -23383,7 +23356,7 @@
+ #: c-family/c-common.c:4969
+ #, gcc-internal-format
+ msgid "duplicate case value"
+-msgstr ""
++msgstr "дублювання значення випадку"
+
+ #: c-family/c-common.c:4970 c-family/c-warn.c:1995
+ #, gcc-internal-format
+@@ -23455,13 +23428,13 @@
msgid "%<fallthrough%> attribute specified with a parameter"
msgstr ""
@@ -27613,7 +36063,7 @@ Index: gcc/po/uk.po
#, gcc-internal-format
msgid "too many arguments to function %qE"
msgstr ""
-@@ -23546,72 +23546,72 @@
+@@ -23546,72 +23519,72 @@
msgid "index %E denotes an offset greater than size of %qT"
msgstr ""
@@ -27700,7 +36150,7 @@ Index: gcc/po/uk.po
#: cp/call.c:4836 cp/call.c:4843
#, gcc-internal-format
msgid "conversion of scalar %qT to vector %qT involves truncation"
-@@ -23619,22 +23619,22 @@
+@@ -23619,22 +23592,22 @@
#. Reject arguments that are built-in functions with
#. no library fallback.
@@ -27727,7 +36177,31 @@ Index: gcc/po/uk.po
#, gcc-internal-format
msgid "environment variable SOURCE_DATE_EPOCH must expand to a non-negative integer less than or equal to %wd"
msgstr ""
-@@ -25395,7 +25395,7 @@
+@@ -24924,12 +24897,12 @@
+ #: c-family/c-warn.c:1068
+ #, gcc-internal-format
+ msgid "case value %qs not in enumerated type"
+-msgstr ""
++msgstr "значення випадку %qs не належить до перераховного типу"
+
+ #: c-family/c-warn.c:1073
+ #, gcc-internal-format
+ msgid "case value %qs not in enumerated type %qT"
+-msgstr ""
++msgstr "значення випадку %qs не належить до перераховного типу %qT"
+
+ #: c-family/c-warn.c:1134
+ #, gcc-internal-format
+@@ -25290,7 +25263,7 @@
+ #: c-family/c-warn.c:1897
+ #, gcc-internal-format
+ msgid "unused parameter %qD"
+-msgstr ""
++msgstr "невикористаний параметр %qD"
+
+ #: c-family/c-warn.c:1959
+ #, gcc-internal-format
+@@ -25395,7 +25368,7 @@
msgid "too many input files"
msgstr ""
@@ -27736,7 +36210,7 @@ Index: gcc/po/uk.po
#, gcc-internal-format
msgid "unknown value %qs for -mcpu"
msgstr ""
-@@ -25853,180 +25853,180 @@
+@@ -25853,180 +25826,179 @@
msgid "%qs feature modifier is incompatible with %s %s"
msgstr ""
@@ -27765,11 +36239,13 @@ Index: gcc/po/uk.po
msgstr "невідомий параметр регулювання (%s)"
-#: config/aarch64/aarch64.c:8707
+-#, fuzzy, gcc-internal-format
+-#| msgid "Invalid argument %d for builtin %qF"
+#: config/aarch64/aarch64.c:8715
- #, fuzzy, gcc-internal-format
- #| msgid "Invalid argument %d for builtin %qF"
++#, gcc-internal-format
msgid "valid arguments are: %s; did you mean %qs?"
- msgstr "Некоректний аргумент %d до вбудованої %qF"
+-msgstr "Некоректний аргумент %d до вбудованої %qF"
++msgstr "коректними аргументами є такі: %s; ви мали на увазі %qs?"
-#: config/aarch64/aarch64.c:8748
+#: config/aarch64/aarch64.c:8756
@@ -27953,7 +36429,7 @@ Index: gcc/po/uk.po
#, gcc-internal-format
msgid "lane %wd out of range %wd - %wd"
msgstr ""
-@@ -26433,62 +26433,62 @@
+@@ -26433,62 +26405,62 @@
msgid "the count should be no less than 0. please check the intrinsic _mm_sra_si64 in code."
msgstr ""
@@ -28028,7 +36504,7 @@ Index: gcc/po/uk.po
#, gcc-internal-format
msgid "target CPU does not support unaligned accesses"
msgstr ""
-@@ -26495,127 +26495,133 @@
+@@ -26495,127 +26467,133 @@
#. To support this we need to be able to parse FPU feature options
#. from the architecture string.
@@ -28187,7 +36663,7 @@ Index: gcc/po/uk.po
#: config/avr/avr.c:9480 config/avr/avr.c:9496 config/bfin/bfin.c:4673
#: config/bfin/bfin.c:4734 config/bfin/bfin.c:4763
#: config/epiphany/epiphany.c:475 config/h8300/h8300.c:5456
-@@ -26631,72 +26637,72 @@
+@@ -26631,72 +26609,72 @@
msgid "%qE attribute only applies to functions"
msgstr ""
@@ -28209,285 +36685,1270 @@ Index: gcc/po/uk.po
msgid "%qE attribute not available to functions that return value on the stack"
msgstr ""
--#: config/arm/arm.c:6857 config/arm/arm.c:6909
-+#: config/arm/arm.c:6894 config/arm/arm.c:6946
+-#: config/arm/arm.c:6857 config/arm/arm.c:6909
++#: config/arm/arm.c:6894 config/arm/arm.c:6946
+ #, gcc-internal-format
+ msgid "%qE attribute ignored without -mcmse option."
+ msgstr ""
+
+-#: config/arm/arm.c:6876
++#: config/arm/arm.c:6913
+ #, gcc-internal-format
+ msgid "%qE attribute has no effect on functions with static linkage"
+ msgstr ""
+
+-#: config/arm/arm.c:6925
++#: config/arm/arm.c:6962
+ #, gcc-internal-format
+ msgid "%qE attribute only applies to base type of a function pointer"
+ msgstr ""
+
+-#: config/arm/arm.c:12208
++#: config/arm/arm.c:12245
+ #, gcc-internal-format
+ msgid "%K%s %wd out of range %wd - %wd"
+ msgstr ""
+
+-#: config/arm/arm.c:12211
++#: config/arm/arm.c:12248
+ #, gcc-internal-format
+ msgid "%s %wd out of range %wd - %wd"
+ msgstr ""
+
+-#: config/arm/arm.c:23458
++#: config/arm/arm.c:23495
+ #, gcc-internal-format
+ msgid "unable to compute real location of stacked parameter"
+ msgstr ""
+
+-#: config/arm/arm.c:24111
++#: config/arm/arm.c:24148
+ #, gcc-internal-format
+ msgid "Unexpected thumb1 far jump"
+ msgstr ""
+
+-#: config/arm/arm.c:24375
++#: config/arm/arm.c:24412
+ #, gcc-internal-format
+ msgid "no low registers available for popping high registers"
+ msgstr ""
+
+-#: config/arm/arm.c:24624
++#: config/arm/arm.c:24661
+ #, gcc-internal-format
+ msgid "interrupt Service Routines cannot be coded in Thumb mode"
+ msgstr ""
+
+-#: config/arm/arm.c:24853
++#: config/arm/arm.c:24890
+ #, gcc-internal-format
+ msgid "-fstack-check=specific for Thumb-1"
+ msgstr ""
+
+-#: config/arm/arm.c:30391
++#: config/arm/arm.c:30435
+ #, gcc-internal-format, gfc-internal-format
+ msgid "invalid fpu for attribute(target(\"%s\"))"
+ msgstr ""
+@@ -26704,13 +26682,13 @@
+ #. This doesn't really make sense until we support
+ #. general dynamic selection of the architecture and all
+ #. sub-features.
+-#: config/arm/arm.c:30399
++#: config/arm/arm.c:30443
+ #, gcc-internal-format
+ msgid "auto fpu selection not currently permitted here"
+ msgstr ""
+
+-#: config/arm/arm.c:30406 config/i386/i386.c:6838 config/i386/i386.c:6885
+-#: config/s390/s390.c:14915 config/s390/s390.c:14965 config/s390/s390.c:14982
++#: config/arm/arm.c:30450 config/i386/i386.c:6838 config/i386/i386.c:6885
++#: config/s390/s390.c:15083 config/s390/s390.c:15133 config/s390/s390.c:15150
+ #, gcc-internal-format, gfc-internal-format
+ msgid "attribute(target(\"%s\")) is unknown"
+ msgstr ""
+@@ -27349,10 +27327,9 @@
+ msgstr ""
+
+ #: config/i386/i386.c:4692
+-#, fuzzy, gcc-internal-format
+-#| msgid "Invalid argument %d for builtin %qF"
++#, gcc-internal-format
+ msgid "wrong argument %qs to option %qs"
+-msgstr "Некоректний аргумент %d до вбудованої %qF"
++msgstr "помилковий аргумент %qs параметра %qs"
+
+ #: config/i386/i386.c:4698
+ #, gcc-internal-format
+@@ -27403,7 +27380,7 @@
+ #: config/i386/i386.c:5272
+ #, gcc-internal-format
+ msgid "%<target(\"tune=x86-64\")%> is deprecated; use %<target(\"tune=k8\")%> or %<target(\"tune=generic\")%> instead as appropriate"
+-msgstr ""
++msgstr "%<target(\"tune=x86-64\")%> вважається застарілим; скористайтеся одним із відповідників: %<target(\"tune=k8\")%> або %<target(\"tune=generic\")%>"
+
+ #. rep; movq isn't available in 32-bit code.
+ #: config/i386/i386.c:5299
+@@ -27495,7 +27472,7 @@
+ #: config/i386/i386.c:5688
+ #, gcc-internal-format
+ msgid "valid arguments to %<-march=%> switch are: %s"
+-msgstr ""
++msgstr "коректними аргументами перемикача %<-march=%> є такі: %s"
+
+ #: config/i386/i386.c:5689
+ #, gcc-internal-format
+@@ -27523,10 +27500,9 @@
+ msgstr ""
+
+ #: config/i386/i386.c:5759
+-#, fuzzy, gcc-internal-format
+-#| msgid "invalid argument to %<__builtin_return_address%>"
++#, gcc-internal-format
+ msgid "valid arguments to %<-mtune=%> switch are: %s"
+-msgstr "некоректний аргумент %<__builtin_return_address%>"
++msgstr "коректними аргументами перемикача %<-mtune=%> є такі: %s"
+
+ #: config/i386/i386.c:5760
+ #, gcc-internal-format
+@@ -28925,10 +28901,9 @@
+ msgstr ""
+
+ #: config/nds32/nds32.c:2707
+-#, fuzzy, gcc-internal-format
+-#| msgid "Generate position-independent code if possible (small mode)."
++#, gcc-internal-format
+ msgid "position-independent code not supported"
+-msgstr "Створити виконуваний файл з незалежним позиціюванням, якщо можливо (малий режим)"
++msgstr "підтримки коду із незалежним позиціюванням не передбачено"
+
+ #: config/nios2/nios2.c:561
+ #, gcc-internal-format
+@@ -29320,7 +29295,7 @@
+ msgid "vec_cmpne only accepts 2 arguments"
+ msgstr ""
+
+-#: config/rs6000/rs6000-c.c:5711
++#: config/rs6000/rs6000-c.c:5710
+ #, gcc-internal-format
+ msgid "vec_adde only accepts 3 arguments"
+ msgstr ""
+@@ -29330,42 +29305,42 @@
+ msgid "vec_addec only accepts 3 arguments"
+ msgstr ""
+
+-#: config/rs6000/rs6000-c.c:5861
++#: config/rs6000/rs6000-c.c:5862
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s only accepts %d arguments"
+ msgstr ""
+
+-#: config/rs6000/rs6000-c.c:5866
++#: config/rs6000/rs6000-c.c:5867
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s only accepts 1 argument"
+ msgstr ""
+
+-#: config/rs6000/rs6000-c.c:5871
++#: config/rs6000/rs6000-c.c:5872
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%s only accepts 2 arguments"
+ msgstr ""
+
+-#: config/rs6000/rs6000-c.c:5937
++#: config/rs6000/rs6000-c.c:5938
+ #, gcc-internal-format
+ msgid "vec_extract only accepts 2 arguments"
+ msgstr ""
+
+-#: config/rs6000/rs6000-c.c:6106
++#: config/rs6000/rs6000-c.c:6107
+ #, gcc-internal-format
+ msgid "vec_insert only accepts 3 arguments"
+ msgstr ""
+
+-#: config/rs6000/rs6000-c.c:6380
++#: config/rs6000/rs6000-c.c:6381
+ #, gcc-internal-format
+ msgid "passing arg %d of %qE discards qualifiers from pointer target type"
+ msgstr ""
+
+-#: config/rs6000/rs6000-c.c:6434
++#: config/rs6000/rs6000-c.c:6435
+ #, gcc-internal-format, gfc-internal-format
+ msgid "Builtin function %s not supported in this compiler configuration"
+ msgstr ""
+
+-#: config/rs6000/rs6000-c.c:6442
++#: config/rs6000/rs6000-c.c:6443
+ #, gcc-internal-format, gfc-internal-format
+ msgid "invalid parameter combination for AltiVec intrinsic %s"
+ msgstr ""
+@@ -30329,13 +30304,12 @@
+ #: config/s390/s390-c.c:879
+ #, gcc-internal-format
+ msgid "builtin %qF is deprecated."
+-msgstr ""
++msgstr "вбудований %qF вважається застарілим."
+
+ #: config/s390/s390-c.c:883
+-#, fuzzy, gcc-internal-format
+-#| msgid "%E requires %<-fgnu-tm%>"
++#, gcc-internal-format
+ msgid "%qF requires -mvx"
+-msgstr "%E потребує %<-fgnu-tm%>"
++msgstr "%qF потребує -mvx"
+
+ #: config/s390/s390-c.c:889
+ #, gcc-internal-format
+@@ -30409,10 +30383,9 @@
+ msgstr ""
+
+ #: config/s390/s390.c:1004
+-#, fuzzy, gcc-internal-format
+-#| msgid "Invalid argument %d for builtin %qF"
++#, gcc-internal-format
+ msgid "invalid argument %d for builtin %qF"
+-msgstr "Некоректний аргумент %d до вбудованої %qF"
++msgstr "некоректний аргумент %d для вбудованої %qF"
+
+ #: config/s390/s390.c:1105
+ #, gcc-internal-format
+@@ -30419,114 +30392,114 @@
+ msgid "requested %qE attribute is not a comma separated pair of non-negative integer constants or too large (max. %d)"
+ msgstr ""
+
+-#: config/s390/s390.c:9812
++#: config/s390/s390.c:9980
+ #, gcc-internal-format
+ msgid "total size of local variables exceeds architecture limit"
+ msgstr ""
+
+-#: config/s390/s390.c:10926
++#: config/s390/s390.c:11094
+ #, gcc-internal-format
+ msgid "frame size of function %qs is %wd bytes exceeding user provided stack limit of %d bytes. An unconditional trap is added."
+ msgstr ""
+
+-#: config/s390/s390.c:10942
++#: config/s390/s390.c:11110
+ #, gcc-internal-format
+ msgid "frame size of function %qs is %wd bytes which is more than half the stack size. The dynamic check would not be reliable. No check emitted for this function."
+ msgstr ""
+
+-#: config/s390/s390.c:10970
++#: config/s390/s390.c:11138
+ #, gcc-internal-format
+ msgid "frame size of %qs is %wd bytes"
+ msgstr ""
+
+-#: config/s390/s390.c:10974
++#: config/s390/s390.c:11142
+ #, gcc-internal-format
+ msgid "%qs uses dynamic stack allocation"
+ msgstr ""
+
+-#: config/s390/s390.c:11352
++#: config/s390/s390.c:11520
+ #, gcc-internal-format
+ msgid "CPUs older than z900 are not supported for -fsplit-stack"
+ msgstr ""
+
+-#: config/s390/s390.c:14498
++#: config/s390/s390.c:14666
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%sarch=%s%s is deprecated and will be removed in future releases; use at least %sarch=z900%s"
+ msgstr ""
+
+-#: config/s390/s390.c:14510
++#: config/s390/s390.c:14678
+ #, gcc-internal-format, gfc-internal-format
+ msgid "%stune=%s%s is deprecated and will be removed in future releases; use at least %stune=z900%s"
+ msgstr ""
+
+-#: config/s390/s390.c:14522
++#: config/s390/s390.c:14690
+ #, gcc-internal-format, gfc-internal-format
+ msgid "z/Architecture mode not supported on %s"
+ msgstr ""
+
+-#: config/s390/s390.c:14525
++#: config/s390/s390.c:14693
+ #, gcc-internal-format
+ msgid "64-bit ABI not supported in ESA/390 mode"
+ msgstr ""
+
+-#: config/s390/s390.c:14542
++#: config/s390/s390.c:14710
+ #, gcc-internal-format, gfc-internal-format
+ msgid "hardware vector support not available on %s"
+ msgstr ""
+
+-#: config/s390/s390.c:14545
++#: config/s390/s390.c:14713
+ #, gcc-internal-format
+ msgid "hardware vector support not available with -msoft-float"
+ msgstr ""
+
+-#: config/s390/s390.c:14573
++#: config/s390/s390.c:14741
+ #, gcc-internal-format, gfc-internal-format
+ msgid "hardware decimal floating point instructions not available on %s"
+ msgstr ""
+
+-#: config/s390/s390.c:14577
++#: config/s390/s390.c:14745
+ #, gcc-internal-format
+ msgid "hardware decimal floating point instructions not available in ESA/390 mode"
+ msgstr ""
+
+-#: config/s390/s390.c:14589
++#: config/s390/s390.c:14757
+ #, gcc-internal-format
+ msgid "-mhard-dfp can%'t be used in conjunction with -msoft-float"
+ msgstr ""
+
+-#: config/s390/s390.c:14597
++#: config/s390/s390.c:14765
+ #, gcc-internal-format
+ msgid "-mbackchain -mpacked-stack -mhard-float are not supported in combination"
+ msgstr ""
+
+-#: config/s390/s390.c:14603
++#: config/s390/s390.c:14771
+ #, gcc-internal-format
+ msgid "stack size must be greater than the stack guard value"
+ msgstr ""
+
+-#: config/s390/s390.c:14605
++#: config/s390/s390.c:14773
+ #, gcc-internal-format
+ msgid "stack size must not be greater than 64k"
+ msgstr ""
+
+-#: config/s390/s390.c:14608
++#: config/s390/s390.c:14776
+ #, gcc-internal-format
+ msgid "-mstack-guard implies use of -mstack-size"
+ msgstr ""
+
+ #. argument is not a plain number
+-#: config/s390/s390.c:14706
++#: config/s390/s390.c:14874
+ #, gcc-internal-format
+ msgid "arguments to %qs should be non-negative integers"
+ msgstr ""
+
+-#: config/s390/s390.c:14713
++#: config/s390/s390.c:14881
+ #, gcc-internal-format
+ msgid "argument to %qs is too large (max. %d)"
+ msgstr ""
+
+ #. Value is not allowed for the target attribute.
+-#: config/s390/s390.c:14921
++#: config/s390/s390.c:15089
+ #, gcc-internal-format
+ msgid "value %qs is not supported by attribute %<target%>"
+ msgstr ""
+@@ -31152,7 +31125,7 @@
+ #: c/c-decl.c:1794
+ #, gcc-internal-format
+ msgid "previous implicit declaration of %q+D was here"
+-msgstr ""
++msgstr "попереднє неявне оголошення %q+D було тут"
+
+ #: c/c-decl.c:1796
+ #, gcc-internal-format
+@@ -31323,17 +31296,17 @@
+ #: c/c-decl.c:3144 c/c-decl.c:3157
+ #, gcc-internal-format
+ msgid "implicit declaration of function %qE; did you mean %qs?"
+-msgstr ""
++msgstr "неявне оголошення функції %qE; ви мали на увазі %qs?"
+
+ #: c/c-decl.c:3149 c/c-decl.c:3162
+ #, gcc-internal-format
+ msgid "implicit declaration of function %qE"
+-msgstr ""
++msgstr "неявне оголошення функції %qE"
+
+ #: c/c-decl.c:3408
+ #, gcc-internal-format
+ msgid "incompatible implicit declaration of built-in function %qD"
+-msgstr ""
++msgstr "несумісне неявне оголошення вбудованої функції %qD"
+
+ #: c/c-decl.c:3415
+ #, gcc-internal-format
+@@ -31343,7 +31316,7 @@
+ #: c/c-decl.c:3424
+ #, gcc-internal-format
+ msgid "incompatible implicit declaration of function %qD"
+-msgstr ""
++msgstr "несумісне неявне оголошення функції %qD"
+
+ #: c/c-decl.c:3484
+ #, gcc-internal-format
+@@ -32612,10 +32585,9 @@
+ msgstr ""
+
+ #: c/c-decl.c:10452
+-#, fuzzy, gcc-internal-format
+-#| msgid "ISO C++ 1998 does not support %<long long%>"
++#, gcc-internal-format
+ msgid "ISO C does not support the %<_Float%d%s%> type"
+-msgstr "У ISO C++ 1998 не передбачено підтримки %<long long%>"
++msgstr "У ISO C не передбачено підтримки типу %<_Float%d%s%>"
+
+ #: c/c-decl.c:10502
+ #, gcc-internal-format
+@@ -33216,10 +33188,9 @@
+ msgstr ""
+
+ #: c/c-parser.c:6175
+-#, fuzzy, gcc-internal-format
+-#| msgid "expected %<,%> or %<)%>"
++#, gcc-internal-format
+ msgid "expected %<:%> or %<)%>"
+-msgstr "мало бути %<,%> або %<)%>"
++msgstr "мало бути %<:%> або %<)%>"
+
+ #: c/c-parser.c:6487
+ #, gcc-internal-format
+@@ -33340,7 +33311,7 @@
+ #: c/c-parser.c:7912
+ #, gcc-internal-format
+ msgid "wrong number of arguments to %<__builtin_choose_expr%>"
+-msgstr ""
++msgstr "помилкова кількість аргументів %<__builtin_choose_expr%>"
+
+ #: c/c-parser.c:7928
+ #, gcc-internal-format
+@@ -33350,7 +33321,7 @@
+ #: c/c-parser.c:7999
+ #, gcc-internal-format
+ msgid "wrong number of arguments to %<__builtin_call_with_static_chain%>"
+-msgstr ""
++msgstr "помилкова кількість аргументів %<__builtin_call_with_static_chain%>"
+
+ #: c/c-parser.c:8012
+ #, gcc-internal-format
+@@ -33365,7 +33336,7 @@
+ #: c/c-parser.c:8042
+ #, gcc-internal-format
+ msgid "wrong number of arguments to %<__builtin_complex%>"
+-msgstr ""
++msgstr "помилкова кількість аргументів %<__builtin_complex%>"
+
+ #: c/c-parser.c:8064
+ #, gcc-internal-format
+@@ -33380,7 +33351,7 @@
+ #: c/c-parser.c:8121 cp/parser.c:6676
+ #, gcc-internal-format
+ msgid "wrong number of arguments to %<__builtin_shuffle%>"
+-msgstr ""
++msgstr "помилкова кількість аргументів %<__builtin_shuffle%>"
+
+ #: c/c-parser.c:8202 cp/parser.c:6587
+ #, gcc-internal-format
+@@ -33482,10 +33453,9 @@
+ msgstr ""
+
+ #: c/c-parser.c:10214 cp/parser.c:38233
+-#, fuzzy, gcc-internal-format
+-#| msgid "%<#pragma acc routine%> %s"
++#, gcc-internal-format
+ msgid "%<#pragma acc routine%> must be at file scope"
+-msgstr "%<#pragma acc routine%> %s"
++msgstr "%<#pragma acc routine%> має перебувати у області видимості файла"
+
+ #: c/c-parser.c:10292 cp/parser.c:38314
+ #, gcc-internal-format
+@@ -33677,10 +33647,9 @@
+ msgstr ""
+
+ #: c/c-parser.c:12297 cp/semantics.c:6395
+-#, fuzzy, gcc-internal-format
+-#| msgid "%qs value must be positive"
++#, gcc-internal-format
+ msgid "chunk size value must be positive"
+-msgstr "значення %qs має бути додатним"
++msgstr "значення розміру фрагмента має бути додатним"
+
+ #: c/c-parser.c:12320 cp/parser.c:32207
+ #, gcc-internal-format
+@@ -33803,10 +33772,9 @@
+ msgstr ""
+
+ #: c/c-parser.c:13933 cp/parser.c:36305
+-#, fuzzy, gcc-internal-format
+-#| msgid "expected %<for%> after %qs"
++#, gcc-internal-format
+ msgid "expected %<data%> after %<#pragma acc %s%>"
+-msgstr "мало бути %<for%> після %qs"
++msgstr "мало бути %<data%> після %<#pragma acc %s%>"
+
+ #: c/c-parser.c:13949 cp/parser.c:36322
+ #, gcc-internal-format
+@@ -33839,22 +33807,19 @@
+ msgstr ""
+
+ #: c/c-parser.c:14268 cp/parser.c:37576
+-#, fuzzy, gcc-internal-format
+-#| msgid "%<#pragma acc routine%> %s"
++#, gcc-internal-format
+ msgid "%<#pragma acc routine%> already applied to %qD"
+-msgstr "%<#pragma acc routine%> %s"
++msgstr "%<#pragma acc routine%> вже застосовано до %qD"
+
+ #: c/c-parser.c:14277 cp/parser.c:37585
+-#, fuzzy, gcc-internal-format
+-#| msgid "%<#pragma acc routine%> %s"
++#, gcc-internal-format
+ msgid "%<#pragma acc routine%> must be applied before use"
+-msgstr "%<#pragma acc routine%> %s"
++msgstr "%<#pragma acc routine%> має бути застосовано до використання"
+
+ #: c/c-parser.c:14278 cp/parser.c:37586
+-#, fuzzy, gcc-internal-format
+-#| msgid "%<#pragma acc routine%> %s"
++#, gcc-internal-format
+ msgid "%<#pragma acc routine%> must be applied before definition"
+-msgstr "%<#pragma acc routine%> %s"
++msgstr "%<#pragma acc routine%> має бути застосовано до визначення"
+
+ #: c/c-parser.c:14321 cp/parser.c:36497
+ #, gcc-internal-format
+@@ -34047,10 +34012,9 @@
+ msgstr ""
+
+ #: c/c-parser.c:16998
+-#, fuzzy, gcc-internal-format
+-#| msgid "previous %<#pragma omp declare reduction%>"
++#, gcc-internal-format
+ msgid "%<_Atomic%> qualified type in %<#pragma omp declare reduction%>"
+-msgstr "попереднє %<#pragma omp declare reduction%>"
++msgstr "тип класу %<_Atomic%> у %<#pragma omp declare reduction%>"
+
+ #: c/c-parser.c:17001
+ #, gcc-internal-format
+@@ -34502,10 +34466,9 @@
+ msgstr ""
+
+ #: c/c-typeck.c:4244
+-#, fuzzy, gcc-internal-format
+-#| msgid "%<goto%> is not a constant-expression"
++#, gcc-internal-format
+ msgid "%<~%> on a boolean expression"
+-msgstr "%<goto%> не є сталим виразом"
++msgstr "%<~%> над булевим виразом"
+
+ #: c/c-typeck.c:4248
+ #, gcc-internal-format
+@@ -35771,51 +35734,44 @@
+ msgstr ""
+
+ #: c/gimple-parser.c:850
+-#, fuzzy, gcc-internal-format
+-#| msgid "invalid operand"
++#, gcc-internal-format
+ msgid "invalid _Literal"
+-msgstr "некоректний операнд"
++msgstr "некоректне _Literal"
+
+ #: c/gimple-parser.c:869
+-#, fuzzy, gcc-internal-format
+-#| msgid "invalid operand to %%R"
++#, gcc-internal-format
+ msgid "invalid number of operands to __FMA"
+-msgstr "некоректний операнд %%R"
++msgstr "некоректна кількість операндів __FMA"
+
+ #: c/gimple-parser.c:904
+ #, gcc-internal-format
+ msgid "anonymous SSA name cannot have default definition"
+-msgstr ""
++msgstr "анонімна назва SSA не може мати типового визначення"
+
+ #: c/gimple-parser.c:1153
+-#, fuzzy, gcc-internal-format
+-#| msgid "expected type-name"
++#, gcc-internal-format
+ msgid "expected pass name"
+-msgstr "мало бути вказано тип-назву"
++msgstr ""
+
+ #: c/gimple-parser.c:1165
+-#, fuzzy, gcc-internal-format
+-#| msgid "invalid operand"
++#, gcc-internal-format
+ msgid "invalid operation"
+-msgstr "некоректний операнд"
++msgstr "некоректна дія"
+
+ #: c/gimple-parser.c:1325 c/gimple-parser.c:1349
+-#, fuzzy, gcc-internal-format
+-#| msgid "expected expression"
++#, gcc-internal-format
+ msgid "expected goto expression"
+-msgstr "мало бути вказано вираз"
++msgstr "мало бути вказано вираз goto"
+
+ #: c/gimple-parser.c:1333
+-#, fuzzy, gcc-internal-format
+-#| msgid "unexpected argument"
++#, gcc-internal-format
+ msgid "expected else statement"
+-msgstr "несподіваний аргумент"
++msgstr "мало бути використано інструкцію else"
+
+ #: c/gimple-parser.c:1478
+-#, fuzzy, gcc-internal-format
+-#| msgid "expected expression"
++#, gcc-internal-format
+ msgid "expected semicolon"
+-msgstr "мало бути вказано вираз"
++msgstr "мало бути використано крапку з комою"
+
+ #: c/gimple-parser.c:1488
+ #, gcc-internal-format
+@@ -36392,16 +36348,14 @@
+ msgstr ""
+
+ #: cp/call.c:9877
+-#, fuzzy, gcc-internal-format
+-#| msgid "candidate 1:"
++#, gcc-internal-format
+ msgid " candidate 1: %q#F"
+-msgstr "кандидат 1:"
++msgstr " кандидат 1: %q#F"
+
+ #: cp/call.c:9879
+-#, fuzzy, gcc-internal-format
+-#| msgid "candidate 2:"
++#, gcc-internal-format
+ msgid " candidate 2: %q#F"
+-msgstr "кандидат 2:"
++msgstr " кандидат 2: %q#F"
+
+ #: cp/call.c:9924
+ #, gcc-internal-format
+@@ -36832,10 +36786,9 @@
+ msgstr ""
+
+ #: cp/class.c:7016
+-#, fuzzy, gcc-internal-format
+-#| msgid "template %qD declared"
++#, gcc-internal-format
+ msgid "array member %q#D declared here"
+-msgstr "оголошено шаблон %qD"
++msgstr "член масиву %q#D оголошено тут"
+
+ #: cp/class.c:7043
+ #, gcc-internal-format
+@@ -37028,10 +36981,9 @@
+ msgstr ""
+
+ #: cp/constexpr.c:1363 cp/constexpr.c:5115
+-#, fuzzy, gcc-internal-format
+-#| msgid "cannot call function %qD"
++#, gcc-internal-format
+ msgid "call to internal function %qE"
+-msgstr "не вдалося викликати функцію %qD"
++msgstr "виклик внутрішньої функції %qE"
+
+ #: cp/constexpr.c:1426
+ #, gcc-internal-format
+@@ -37139,10 +37091,9 @@
+ msgstr ""
+
+ #: cp/constexpr.c:3122 cp/constexpr.c:4412
+-#, fuzzy, gcc-internal-format
+-#| msgid "null pointer"
++#, gcc-internal-format
+ msgid "dereferencing a null pointer"
+-msgstr "нульовий вказівник"
++msgstr "розіменування нульового вказівника"
+
+ #: cp/constexpr.c:3141
+ #, gcc-internal-format
+@@ -37185,10 +37136,9 @@
+ msgstr ""
+
+ #: cp/constexpr.c:3410
+-#, fuzzy, gcc-internal-format
+-#| msgid "%<goto%> is not a constant-expression"
++#, gcc-internal-format
+ msgid "modification of %qE is not a constant expression"
+-msgstr "%<goto%> не є сталим виразом"
++msgstr "зміна %qE не є сталим виразом"
+
+ #: cp/constexpr.c:3782
+ #, gcc-internal-format, gfc-internal-format
+@@ -37196,10 +37146,9 @@
+ msgstr ""
+
+ #: cp/constexpr.c:3921
+-#, fuzzy, gcc-internal-format
+-#| msgid "%<goto%> is not a constant-expression"
++#, gcc-internal-format
+ msgid "value %qE of type %qT is not a constant expression"
+-msgstr "%<goto%> не є сталим виразом"
++msgstr "значення %qE типу %qT не є сталим виразом"
+
+ #: cp/constexpr.c:4049 cp/constexpr.c:5562
+ #, gcc-internal-format
+@@ -37207,34 +37156,29 @@
+ msgstr ""
+
+ #: cp/constexpr.c:4398
+-#, fuzzy, gcc-internal-format
+-#| msgid "%<delete[]%> is not a constant-expression"
++#, gcc-internal-format
+ msgid "a reinterpret_cast is not a constant expression"
+-msgstr "%<delete[]%> не є сталим виразом"
++msgstr "reinterpret_cast не є сталим виразом"
+
+ #: cp/constexpr.c:4424
+-#, fuzzy, gcc-internal-format
+-#| msgid "%<goto%> is not a constant-expression"
++#, gcc-internal-format
+ msgid "conversion of %qT null pointer to %qT is not a constant expression"
+-msgstr "%<goto%> не є сталим виразом"
++msgstr "перетворення нульового вказівника %qT на %qT не є сталим виразом"
+
+ #: cp/constexpr.c:4439
+-#, fuzzy, gcc-internal-format
+-#| msgid "%<delete[]%> is not a constant-expression"
++#, gcc-internal-format
+ msgid "%<reinterpret_cast<%T>(%E)%> is not a constant expression"
+-msgstr "%<delete[]%> не є сталим виразом"
++msgstr "%<reinterpret_cast<%T>(%E)%> не є сталим виразом"
+
+ #: cp/constexpr.c:4502 cp/constexpr.c:5423 cp/constexpr.c:5738
+-#, fuzzy, gcc-internal-format
+-#| msgid "%<goto%> is not a constant-expression"
++#, gcc-internal-format
+ msgid "expression %qE is not a constant expression"
+-msgstr "%<goto%> не є сталим виразом"
++msgstr "вираз %qE не є сталим виразом"
+
+ #: cp/constexpr.c:4579
+-#, fuzzy, gcc-internal-format
+-#| msgid "%<delete[]%> is not a constant-expression"
++#, gcc-internal-format
+ msgid "statement is not a constant expression"
+-msgstr "%<delete[]%> не є сталим виразом"
++msgstr "інструкція не є сталим виразом"
+
+ #: cp/constexpr.c:4582
+ #, gcc-internal-format
+@@ -37302,14 +37246,12 @@
+ msgstr ""
+
+ #: cp/constexpr.c:5611
+-#, fuzzy, gcc-internal-format
+-#| msgid "%<goto%> is not a constant-expression"
++#, gcc-internal-format
+ msgid "division by zero is not a constant expression"
+-msgstr "%<goto%> не є сталим виразом"
++msgstr "ділення на нуль не є сталим виразом"
+
+ #: cp/constexpr.c:5715
+-#, fuzzy, gcc-internal-format
+-#| msgid "%<delete[]%> is not a constant-expression"
++#, gcc-internal-format
+ msgid "%<delete[]%> is not a constant expression"
+ msgstr "%<delete[]%> не є сталим виразом"
+
+@@ -37319,8 +37261,7 @@
+ msgstr ""
+
+ #: cp/constexpr.c:5767
+-#, fuzzy, gcc-internal-format
+-#| msgid "%<goto%> is not a constant-expression"
++#, gcc-internal-format
+ msgid "%<goto%> is not a constant expression"
+ msgstr "%<goto%> не є сталим виразом"
+
+@@ -37496,10 +37437,9 @@
+ msgstr ""
+
+ #: cp/cvt.c:1003
+-#, fuzzy, gcc-internal-format
+-#| msgid "template %qD declared"
++#, gcc-internal-format
+ msgid "in call to %qD, declared here"
+-msgstr "оголошено шаблон %qD"
++msgstr "у виклику %qD, оголошено тут"
+
+ #: cp/cvt.c:1082
+ #, gcc-internal-format
+@@ -37792,27 +37732,24 @@
+ msgstr ""
+
+ #: cp/decl.c:1277
+-#, fuzzy, gcc-internal-format
+-#| msgid "due to different exception specifications"
++#, gcc-internal-format
+ msgid "declaration of %qF has a different exception specifier"
+-msgstr "через різні специфікації виключення"
++msgstr "оголошення %qF містить інше визначення виключення"
+
+ #: cp/decl.c:1290
+-#, fuzzy, gcc-internal-format
+-#| msgid "previous declaration"
++#, gcc-internal-format
+ msgid "from previous declaration %qF"
+-msgstr "попереднє оголошення"
++msgstr "з попереднього оголошення %qF"
+
+ #: cp/decl.c:1325
+ #, gcc-internal-format
+ msgid "redeclaration %qD differs in %<constexpr%> from previous declaration"
+-msgstr ""
++msgstr "повторне оголошення %qD відрізняється у %<constexpr%> від попереднього оголошення"
+
+ #: cp/decl.c:1328 cp/decl.c:13702
+-#, fuzzy, gcc-internal-format
+-#| msgid "previous declaration"
++#, gcc-internal-format
+ msgid "previous declaration %qD"
+-msgstr "попереднє оголошення"
++msgstr "попереднє оголошення %qD"
+
+ #: cp/decl.c:1357
#, gcc-internal-format
- msgid "%qE attribute ignored without -mcmse option."
+@@ -37835,16 +37772,14 @@
msgstr ""
--#: config/arm/arm.c:6876
-+#: config/arm/arm.c:6913
+ #: cp/decl.c:1442
+-#, fuzzy, gcc-internal-format
+-#| msgid "previous definition of %q+#T"
++#, gcc-internal-format
+ msgid "previous definition of %qD was here"
+-msgstr "попереднє визначення %q+#T"
++msgstr "попереднє визначення %qD було тут"
+
+ #: cp/decl.c:1445
+-#, fuzzy, gcc-internal-format
+-#| msgid "previous declaration"
++#, gcc-internal-format
+ msgid "previous declaration of %qD was here"
+-msgstr "попереднє оголошення"
++msgstr "попереднє оголошення %qD було тут"
+
+ #: cp/decl.c:1467 cp/decl.c:1579
#, gcc-internal-format
- msgid "%qE attribute has no effect on functions with static linkage"
+@@ -38649,10 +38584,9 @@
msgstr ""
--#: config/arm/arm.c:6925
-+#: config/arm/arm.c:6962
+ #: cp/decl.c:7533
+-#, fuzzy, gcc-internal-format
+-#| msgid "%<delete[]%> is not a constant-expression"
++#, gcc-internal-format
+ msgid "%<std::tuple_size<%T>::value%> is not an integral constant expression"
+-msgstr "%<delete[]%> не є сталим виразом"
++msgstr "%<std::tuple_size<%T>::value%> не є інтегральним сталим виразом"
+
+ #: cp/decl.c:7553
#, gcc-internal-format
- msgid "%qE attribute only applies to base type of a function pointer"
+@@ -38660,10 +38594,9 @@
msgstr ""
--#: config/arm/arm.c:12208
-+#: config/arm/arm.c:12245
+ #: cp/decl.c:7575
+-#, fuzzy, gcc-internal-format
+-#| msgid "cannot call function %qD"
++#, gcc-internal-format
+ msgid "cannot decompose union type %qT"
+-msgstr "не вдалося викликати функцію %qD"
++msgstr "не вдалося розкласти тип об'єднання %qT"
+
+ #: cp/decl.c:7580
#, gcc-internal-format
- msgid "%K%s %wd out of range %wd - %wd"
+@@ -38927,10 +38860,9 @@
msgstr ""
--#: config/arm/arm.c:12211
-+#: config/arm/arm.c:12248
+ #: cp/decl.c:8936
+-#, fuzzy, gcc-internal-format
+-#| msgid "%q#D previously declared here"
++#, gcc-internal-format
+ msgid "%q#D explicitly defaulted here"
+-msgstr "%q#D раніше оголошено тут"
++msgstr "%q#D явним чином типово визначено тут"
+
+ #: cp/decl.c:8953 cp/decl2.c:713
#, gcc-internal-format
- msgid "%s %wd out of range %wd - %wd"
+@@ -40205,10 +40137,9 @@
msgstr ""
--#: config/arm/arm.c:23458
-+#: config/arm/arm.c:23495
+ #: cp/decl.c:13428 cp/decl.c:13435
+-#, fuzzy, gcc-internal-format
+-#| msgid "previous declaration"
++#, gcc-internal-format
+ msgid "%qT has a previous declaration here"
+-msgstr "попереднє оголошення"
++msgstr "%qT має попереднє оголошення тут"
+
+ #: cp/decl.c:13434
#, gcc-internal-format
- msgid "unable to compute real location of stacked parameter"
+@@ -42363,16 +42294,14 @@
msgstr ""
--#: config/arm/arm.c:24111
-+#: config/arm/arm.c:24148
+ #: cp/parser.c:6647
+-#, fuzzy, gcc-internal-format
+-#| msgid "invalid argument to %<__builtin_return_address%>"
++#, gcc-internal-format
+ msgid "wrong number of arguments to %<__builtin_addressof%>"
+-msgstr "некоректний аргумент %<__builtin_return_address%>"
++msgstr "помилкова кількість аргументів %<__builtin_addressof%>"
+
+ #: cp/parser.c:6659 cp/pt.c:17319
+-#, fuzzy, gcc-internal-format
+-#| msgid "invalid argument to %<__builtin_return_address%>"
++#, gcc-internal-format
+ msgid "wrong number of arguments to %<__builtin_launder%>"
+-msgstr "некоректний аргумент %<__builtin_return_address%>"
++msgstr "помилкова кількість аргументів %<__builtin_launder%>"
+
+ #: cp/parser.c:6751
#, gcc-internal-format
- msgid "Unexpected thumb1 far jump"
+@@ -42535,21 +42464,19 @@
msgstr ""
--#: config/arm/arm.c:24375
-+#: config/arm/arm.c:24412
+ #: cp/parser.c:10186
+-#, fuzzy, gcc-internal-format
+-#| msgid "ISO C++ 1998 does not support %<long long%>"
++#, gcc-internal-format
+ msgid "ISO C++ does not support lambda templates"
+-msgstr "У ISO C++ 1998 не передбачено підтримки %<long long%>"
++msgstr "у ISO C++ не передбачено підтримки шаблонів лямбд"
+
+ #: cp/parser.c:10216
#, gcc-internal-format
- msgid "no low registers available for popping high registers"
- msgstr ""
+ msgid "default argument specified for lambda parameter"
+-msgstr ""
++msgstr "визначено типовий аргумент для лямбда-параметра"
--#: config/arm/arm.c:24624
-+#: config/arm/arm.c:24661
+ #: cp/parser.c:10234
+-#, fuzzy, gcc-internal-format
+-#| msgid "duplicate %<volatile%>"
++#, gcc-internal-format
+ msgid "duplicate %<mutable%>"
+-msgstr "дублювання %<volatile%>"
++msgstr "дублювання %<mutable%>"
+
+ #: cp/parser.c:10282
#, gcc-internal-format
- msgid "interrupt Service Routines cannot be coded in Thumb mode"
+@@ -42703,10 +42630,9 @@
msgstr ""
--#: config/arm/arm.c:24853
-+#: config/arm/arm.c:24890
+ #: cp/parser.c:13028
+-#, fuzzy, gcc-internal-format
+-#| msgid "previous declaration"
++#, gcc-internal-format
+ msgid "empty decomposition declaration"
+-msgstr "попереднє оголошення"
++msgstr "порожнє оголошення розкладання"
+
+ #: cp/parser.c:13201
#, gcc-internal-format
- msgid "-fstack-check=specific for Thumb-1"
+@@ -42726,10 +42652,9 @@
msgstr ""
--#: config/arm/arm.c:30391
-+#: config/arm/arm.c:30435
- #, gcc-internal-format, gfc-internal-format
- msgid "invalid fpu for attribute(target(\"%s\"))"
- msgstr ""
-@@ -26704,13 +26710,13 @@
- #. This doesn't really make sense until we support
- #. general dynamic selection of the architecture and all
- #. sub-features.
--#: config/arm/arm.c:30399
-+#: config/arm/arm.c:30443
+ #: cp/parser.c:13307
+-#, fuzzy, gcc-internal-format
+-#| msgid "invalid mask"
++#, gcc-internal-format
+ msgid "%qD invalid in lambda"
+-msgstr "некоректна маска"
++msgstr "%qD є некоректним у лямбді"
+
+ #: cp/parser.c:13400
#, gcc-internal-format
- msgid "auto fpu selection not currently permitted here"
+@@ -43040,10 +42965,9 @@
msgstr ""
--#: config/arm/arm.c:30406 config/i386/i386.c:6838 config/i386/i386.c:6885
--#: config/s390/s390.c:14915 config/s390/s390.c:14965 config/s390/s390.c:14982
-+#: config/arm/arm.c:30450 config/i386/i386.c:6838 config/i386/i386.c:6885
-+#: config/s390/s390.c:15083 config/s390/s390.c:15133 config/s390/s390.c:15150
- #, gcc-internal-format, gfc-internal-format
- msgid "attribute(target(\"%s\")) is unknown"
- msgstr ""
-@@ -29320,7 +29326,7 @@
- msgid "vec_cmpne only accepts 2 arguments"
- msgstr ""
+ #: cp/parser.c:17927
+-#, fuzzy, gcc-internal-format
+-#| msgid "ISO C forbids nested functions"
++#, gcc-internal-format
+ msgid "ISO C++ forbids empty unnamed enum"
+-msgstr "У стандарті ISO C заборонено вкладеність функцій"
++msgstr "У ISO C++ заборонено порожні enum без назви"
--#: config/rs6000/rs6000-c.c:5711
-+#: config/rs6000/rs6000-c.c:5710
+ #: cp/parser.c:17947
#, gcc-internal-format
- msgid "vec_adde only accepts 3 arguments"
- msgstr ""
-@@ -29330,42 +29336,42 @@
- msgid "vec_addec only accepts 3 arguments"
- msgstr ""
+@@ -43373,10 +43297,9 @@
+ msgstr "не вдалося визначити тип typename"
--#: config/rs6000/rs6000-c.c:5861
-+#: config/rs6000/rs6000-c.c:5862
- #, gcc-internal-format, gfc-internal-format
- msgid "%s only accepts %d arguments"
- msgstr ""
+ #: cp/parser.c:22775
+-#, fuzzy, gcc-internal-format
+-#| msgid "previous definition of %q+#T"
++#, gcc-internal-format
+ msgid "previous definition of %q#T"
+-msgstr "попереднє визначення %q+#T"
++msgstr "попереднє визначення %q#T"
--#: config/rs6000/rs6000-c.c:5866
-+#: config/rs6000/rs6000-c.c:5867
- #, gcc-internal-format, gfc-internal-format
- msgid "%s only accepts 1 argument"
+ #: cp/parser.c:22865 cp/parser.c:27878
+ #, gcc-internal-format
+@@ -43459,10 +43382,9 @@
msgstr ""
--#: config/rs6000/rs6000-c.c:5871
-+#: config/rs6000/rs6000-c.c:5872
- #, gcc-internal-format, gfc-internal-format
- msgid "%s only accepts 2 arguments"
- msgstr ""
+ #: cp/parser.c:23905
+-#, fuzzy, gcc-internal-format
+-#| msgid "due to different exception specifications"
++#, gcc-internal-format
+ msgid "ISO C++1z does not allow dynamic exception specifications"
+-msgstr "через різні специфікації виключення"
++msgstr "У ISO C++1z не можна визначати динамічні специфікації виключень"
--#: config/rs6000/rs6000-c.c:5937
-+#: config/rs6000/rs6000-c.c:5938
+ #: cp/parser.c:23911
#, gcc-internal-format
- msgid "vec_extract only accepts 2 arguments"
+@@ -43505,10 +43427,9 @@
msgstr ""
--#: config/rs6000/rs6000-c.c:6106
-+#: config/rs6000/rs6000-c.c:6107
+ #: cp/parser.c:24847
+-#, fuzzy, gcc-internal-format
+-#| msgid "expected %<:%> or %<...%>"
++#, gcc-internal-format
+ msgid "expected attribute before %<...%>"
+-msgstr "мало бути %<:%> або %<...%>"
++msgstr "мав бути атрибут перед %<...%>"
+
+ #: cp/parser.c:24908
#, gcc-internal-format
- msgid "vec_insert only accepts 3 arguments"
+@@ -45576,10 +45497,9 @@
msgstr ""
--#: config/rs6000/rs6000-c.c:6380
-+#: config/rs6000/rs6000-c.c:6381
+ #: cp/semantics.c:3524
+-#, fuzzy, gcc-internal-format
+-#| msgid "unexpected argument"
++#, gcc-internal-format
+ msgid "missing template arguments"
+-msgstr "несподіваний аргумент"
++msgstr "пропущено аргументи шаблона"
+
+ #: cp/semantics.c:3551
#, gcc-internal-format
- msgid "passing arg %d of %qE discards qualifiers from pointer target type"
+@@ -45711,8 +45631,7 @@
msgstr ""
--#: config/rs6000/rs6000-c.c:6434
-+#: config/rs6000/rs6000-c.c:6435
- #, gcc-internal-format, gfc-internal-format
- msgid "Builtin function %s not supported in this compiler configuration"
- msgstr ""
+ #: cp/semantics.c:6246
+-#, fuzzy, gcc-internal-format
+-#| msgid "%<gang%> static value must bepositive"
++#, gcc-internal-format
+ msgid "%<gang%> static value must be positive"
+ msgstr "статичне значення %<gang%> має бути додатним"
--#: config/rs6000/rs6000-c.c:6442
-+#: config/rs6000/rs6000-c.c:6443
- #, gcc-internal-format, gfc-internal-format
- msgid "invalid parameter combination for AltiVec intrinsic %s"
- msgstr ""
-@@ -30419,114 +30425,114 @@
- msgid "requested %qE attribute is not a comma separated pair of non-negative integer constants or too large (max. %d)"
- msgstr ""
+@@ -45742,14 +45661,12 @@
+ msgstr "значення num %<gang%> має бути додатним"
--#: config/s390/s390.c:9812
-+#: config/s390/s390.c:9980
- #, gcc-internal-format
- msgid "total size of local variables exceeds architecture limit"
- msgstr ""
+ #: cp/semantics.c:6313
+-#, fuzzy, gcc-internal-format
+-#| msgid "%<vector%> length value must bepositive"
++#, gcc-internal-format
+ msgid "%<vector%> length value must be positive"
+-msgstr "значення length %<vector%> має бути додатним"
++msgstr "значення довжини %<vector%> має бути додатним"
--#: config/s390/s390.c:10926
-+#: config/s390/s390.c:11094
- #, gcc-internal-format
- msgid "frame size of function %qs is %wd bytes exceeding user provided stack limit of %d bytes. An unconditional trap is added."
- msgstr ""
+ #: cp/semantics.c:6318
+-#, fuzzy, gcc-internal-format
+-#| msgid "%<worker%> num value must bepositive"
++#, gcc-internal-format
+ msgid "%<worker%> num value must be positive"
+ msgstr "значення num %<worker%> має бути додатним"
--#: config/s390/s390.c:10942
-+#: config/s390/s390.c:11110
- #, gcc-internal-format
- msgid "frame size of function %qs is %wd bytes which is more than half the stack size. The dynamic check would not be reliable. No check emitted for this function."
+@@ -45914,10 +45831,9 @@
msgstr ""
--#: config/s390/s390.c:10970
-+#: config/s390/s390.c:11138
- #, gcc-internal-format
- msgid "frame size of %qs is %wd bytes"
- msgstr ""
+ #: cp/semantics.c:9519
+-#, fuzzy, gcc-internal-format
+-#| msgid "invalid argument to %<__builtin_return_address%>"
++#, gcc-internal-format
+ msgid "non-pointer argument to %<__builtin_launder%>"
+-msgstr "некоректний аргумент %<__builtin_return_address%>"
++msgstr "аргумент, який не є вказівником, у %<__builtin_launder%>"
--#: config/s390/s390.c:10974
-+#: config/s390/s390.c:11142
+ #: cp/tree.c:1245
#, gcc-internal-format
- msgid "%qs uses dynamic stack allocation"
+@@ -47727,10 +47643,9 @@
msgstr ""
--#: config/s390/s390.c:11352
-+#: config/s390/s390.c:11520
+ #: fortran/check.c:310
+-#, fuzzy, gcc-internal-format
+-#| msgid "%qs value must be positive"
++#, gcc-internal-format
+ msgid "%qs argument of %qs intrinsic at %L must be positive"
+-msgstr "значення %qs має бути додатним"
++msgstr "аргумент %qs внутрішньої частини %qs у %L має бути додатним"
+
+ #: fortran/check.c:343
#, gcc-internal-format
- msgid "CPUs older than z900 are not supported for -fsplit-stack"
+@@ -49371,10 +49286,9 @@
msgstr ""
--#: config/s390/s390.c:14498
-+#: config/s390/s390.c:14666
+ #: fortran/decl.c:4911
+-#, fuzzy, gcc-internal-format, gfc-internal-format
+-#| msgid "Syntax error in nested structure declaration at %C"
++#, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in anonymous structure declaration at %C"
+-msgstr "Синтаксична помилка у оголошенні вкладеної структури у %C"
++msgstr "Синтаксична помилка у оголошенні анонімної структури у %C"
+
+ #: fortran/decl.c:4920
#, gcc-internal-format, gfc-internal-format
- msgid "%sarch=%s%s is deprecated and will be removed in future releases; use at least %sarch=z900%s"
+@@ -49846,10 +49760,9 @@
msgstr ""
--#: config/s390/s390.c:14510
-+#: config/s390/s390.c:14678
+ #: fortran/decl.c:7932
+-#, fuzzy, gcc-internal-format, gfc-internal-format
+-#| msgid "Syntax error in SUBMODULE statement at %C"
++#, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in AUTOMATIC statement at %C"
+-msgstr "Синтаксична помилка у інструкції SUBMODULE у %C"
++msgstr "Синтаксична помилка у інструкції AUTOMATIC у %C"
+
+ #: fortran/decl.c:7946
#, gcc-internal-format, gfc-internal-format
- msgid "%stune=%s%s is deprecated and will be removed in future releases; use at least %stune=z900%s"
+@@ -49862,10 +49775,9 @@
msgstr ""
--#: config/s390/s390.c:14522
-+#: config/s390/s390.c:14690
+ #: fortran/decl.c:7986
+-#, fuzzy, gcc-internal-format, gfc-internal-format
+-#| msgid "Syntax error in SUBMODULE statement at %C"
++#, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in STATIC statement at %C"
+-msgstr "Синтаксична помилка у інструкції SUBMODULE у %C"
++msgstr "Синтаксична помилка у інструкції STATIC у %C"
+
+ #: fortran/decl.c:8005
#, gcc-internal-format, gfc-internal-format
- msgid "z/Architecture mode not supported on %s"
+@@ -50916,10 +50828,9 @@
msgstr ""
--#: config/s390/s390.c:14525
-+#: config/s390/s390.c:14693
+ #: fortran/frontend-passes.c:182
+-#, fuzzy, gcc-internal-format, gfc-internal-format
+-#| msgid "Syntax error in expression at %C"
++#, gcc-internal-format, gfc-internal-format
+ msgid "No location in expression near %L"
+-msgstr "Синтаксична помилка у виразі у %C"
++msgstr "Не вказано місця у виразі поряд із %L"
+
+ #: fortran/frontend-passes.c:381
#, gcc-internal-format
- msgid "64-bit ABI not supported in ESA/390 mode"
+@@ -52676,10 +52587,9 @@
msgstr ""
--#: config/s390/s390.c:14542
-+#: config/s390/s390.c:14710
+ #: fortran/match.c:2886
+-#, fuzzy, gcc-internal-format, gfc-internal-format
+-#| msgid "Junk after MAP statement at %C"
++#, gcc-internal-format, gfc-internal-format
+ msgid "Blank required in %s statement near %C"
+-msgstr "Зайві команди після інструкції MAP у %C"
++msgstr "Потрібен пробіл у інструкції %s поряд із %C"
+
+ #: fortran/match.c:2904
#, gcc-internal-format, gfc-internal-format
- msgid "hardware vector support not available on %s"
+@@ -52784,10 +52694,9 @@
msgstr ""
--#: config/s390/s390.c:14545
-+#: config/s390/s390.c:14713
- #, gcc-internal-format
- msgid "hardware vector support not available with -msoft-float"
- msgstr ""
+ #: fortran/match.c:3274
+-#, fuzzy, gcc-internal-format, gfc-internal-format
+-#| msgid "Junk after MAP statement at %C"
++#, gcc-internal-format, gfc-internal-format
+ msgid "FAIL IMAGE statement at %C"
+-msgstr "Зайві команди після інструкції MAP у %C"
++msgstr "Інструкція FAIL IMAGE у %C"
--#: config/s390/s390.c:14573
-+#: config/s390/s390.c:14741
+ #: fortran/match.c:3309
#, gcc-internal-format, gfc-internal-format
- msgid "hardware decimal floating point instructions not available on %s"
+@@ -53530,10 +53439,9 @@
msgstr ""
--#: config/s390/s390.c:14577
-+#: config/s390/s390.c:14745
- #, gcc-internal-format
- msgid "hardware decimal floating point instructions not available in ESA/390 mode"
- msgstr ""
+ #: fortran/openmp.c:499
+-#, fuzzy, gcc-internal-format, gfc-internal-format
+-#| msgid "Syntax error in !$ACC DECLARE list at %C"
++#, gcc-internal-format, gfc-internal-format
+ msgid "Syntax error in OpenMP DEPEND SINK list at %C"
+-msgstr "Синтаксична помилка у списку !$ACC DECLARE у %C"
++msgstr "Синтаксична помилка у списку OpenMP DEPEND SINK у %C"
--#: config/s390/s390.c:14589
-+#: config/s390/s390.c:14757
- #, gcc-internal-format
- msgid "-mhard-dfp can%'t be used in conjunction with -msoft-float"
+ #: fortran/openmp.c:561
+ #, gcc-internal-format, gfc-internal-format
+@@ -53596,10 +53504,9 @@
msgstr ""
--#: config/s390/s390.c:14597
-+#: config/s390/s390.c:14765
- #, gcc-internal-format
- msgid "-mbackchain -mpacked-stack -mhard-float are not supported in combination"
+ #: fortran/openmp.c:2175
+-#, fuzzy, gcc-internal-format, gfc-internal-format
+-#| msgid "invalid argument to %qD"
++#, gcc-internal-format, gfc-internal-format
+ msgid "Invalid argument to !$ACC WAIT at %L"
+-msgstr "некоректний аргумент %qD"
++msgstr "Некоректний аргумент !$ACC WAIT у %L"
+
+ #: fortran/openmp.c:2184
+ #, gcc-internal-format, gfc-internal-format
+@@ -53792,10 +53699,9 @@
msgstr ""
--#: config/s390/s390.c:14603
-+#: config/s390/s390.c:14771
+ #: fortran/openmp.c:3721
+-#, fuzzy, gcc-internal-format, gfc-internal-format
+-#| msgid "%<priority%> value must be non-negative"
++#, gcc-internal-format, gfc-internal-format
+ msgid "INTEGER expression of %s clause at %L must be non-negative"
+-msgstr "значення %<priority%> має бути невід’ємним"
++msgstr "Вираз INTEGER пункту %s у %L має бути невід'ємним"
+
+ #: fortran/openmp.c:3732
#, gcc-internal-format
- msgid "stack size must be greater than the stack guard value"
+@@ -54142,10 +54048,9 @@
msgstr ""
--#: config/s390/s390.c:14605
-+#: config/s390/s390.c:14773
+ #: fortran/openmp.c:4870
+-#, fuzzy, gcc-internal-format, gfc-internal-format
+-#| msgid "expected expression"
++#, gcc-internal-format, gfc-internal-format
+ msgid "unexpected !$OMP ATOMIC expression at %L"
+-msgstr "мало бути вказано вираз"
++msgstr "неочікуваний вираз !$OMP ATOMIC у %L"
+
+ #: fortran/openmp.c:4899
+ #, gcc-internal-format, gfc-internal-format
+@@ -58831,12 +58736,12 @@
+ #: fortran/trans-decl.c:5512
#, gcc-internal-format
- msgid "stack size must not be greater than 64k"
- msgstr ""
+ msgid "Unused parameter %qs declared at %L"
+-msgstr ""
++msgstr "Невикористаний параметр %qs, оголошено у %L"
--#: config/s390/s390.c:14608
-+#: config/s390/s390.c:14776
+ #: fortran/trans-decl.c:5516
#, gcc-internal-format
- msgid "-mstack-guard implies use of -mstack-size"
- msgstr ""
+ msgid "Unused parameter %qs which has been explicitly imported at %L"
+-msgstr ""
++msgstr "Невикористаний параметр %qs, який було явно імпортовано у %L"
- #. argument is not a plain number
--#: config/s390/s390.c:14706
-+#: config/s390/s390.c:14874
+ #: fortran/trans-decl.c:5542
#, gcc-internal-format
- msgid "arguments to %qs should be non-negative integers"
- msgstr ""
+@@ -59453,7 +59358,7 @@
+ #: objc/objc-act.c:1679 objc/objc-act.c:6817 objc/objc-act.c:6948
+ #, gcc-internal-format
+ msgid "class %qE is deprecated"
+-msgstr ""
++msgstr "клас %qE вважається застарілим"
--#: config/s390/s390.c:14713
-+#: config/s390/s390.c:14881
+ #: objc/objc-act.c:1708
#, gcc-internal-format
- msgid "argument to %qs is too large (max. %d)"
- msgstr ""
+@@ -60065,7 +59970,7 @@
+ #: objc/objc-act.c:8074
+ #, gcc-internal-format
+ msgid "protocol %qE is deprecated"
+-msgstr ""
++msgstr "протокол %qE вважається застарілим"
- #. Value is not allowed for the target attribute.
--#: config/s390/s390.c:14921
-+#: config/s390/s390.c:15089
+ #: objc/objc-act.c:8193
#, gcc-internal-format
- msgid "value %qs is not supported by attribute %<target%>"
- msgstr ""
Index: gcc/po/sr.po
===================================================================
--- a/src/gcc/po/sr.po (.../tags/gcc_7_1_0_release)
@@ -60533,6 +69994,191 @@ Index: gcc/common.opt
being used in a way forbidden by a returns_nonnull or nonnull
attribute. Isolate those paths from the main control flow and turn the
statement with erroneous or undefined behavior into a trap.
+Index: gcc/tree-vect-stmts.c
+===================================================================
+--- a/src/gcc/tree-vect-stmts.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/tree-vect-stmts.c (.../branches/gcc-7-branch)
+@@ -7109,6 +7109,7 @@
+ {
+ first_stmt = GROUP_FIRST_ELEMENT (stmt_info);
+ group_size = GROUP_SIZE (vinfo_for_stmt (first_stmt));
++ int group_gap = GROUP_GAP (vinfo_for_stmt (first_stmt));
+ /* For SLP vectorization we directly vectorize a subchain
+ without permutation. */
+ if (slp && ! SLP_TREE_LOAD_PERMUTATION (slp_node).exists ())
+@@ -7144,10 +7145,15 @@
+ not only the number of vector stmts the permutation result
+ fits in. */
+ if (slp_perm)
+- vec_num = (group_size * vf + nunits - 1) / nunits;
++ {
++ vec_num = (group_size * vf + nunits - 1) / nunits;
++ group_gap_adj = vf * group_size - nunits * vec_num;
++ }
+ else
+- vec_num = SLP_TREE_NUMBER_OF_VEC_STMTS (slp_node);
+- group_gap_adj = vf * group_size - nunits * vec_num;
++ {
++ vec_num = SLP_TREE_NUMBER_OF_VEC_STMTS (slp_node);
++ group_gap_adj = group_gap;
++ }
+ }
+ else
+ vec_num = group_size;
+@@ -7308,6 +7314,7 @@
+ aggr_type = vectype;
+
+ prev_stmt_info = NULL;
++ int group_elt = 0;
+ for (j = 0; j < ncopies; j++)
+ {
+ /* 1. Create the vector or array pointer update chain. */
+@@ -7599,10 +7606,27 @@
+ /* Store vector loads in the corresponding SLP_NODE. */
+ if (slp && !slp_perm)
+ SLP_TREE_VEC_STMTS (slp_node).quick_push (new_stmt);
++
++ /* With SLP permutation we load the gaps as well, without
++ we need to skip the gaps after we manage to fully load
++ all elements. group_gap_adj is GROUP_SIZE here. */
++ group_elt += nunits;
++ if (group_gap_adj != 0 && ! slp_perm
++ && group_elt == group_size - group_gap_adj)
++ {
++ bool ovf;
++ tree bump
++ = wide_int_to_tree (sizetype,
++ wi::smul (TYPE_SIZE_UNIT (elem_type),
++ group_gap_adj, &ovf));
++ dataref_ptr = bump_vector_ptr (dataref_ptr, ptr_incr, gsi,
++ stmt, bump);
++ group_elt = 0;
++ }
+ }
+ /* Bump the vector pointer to account for a gap or for excess
+ elements loaded for a permuted SLP load. */
+- if (group_gap_adj != 0)
++ if (group_gap_adj != 0 && slp_perm)
+ {
+ bool ovf;
+ tree bump
+Index: gcc/tree-ssa-phiprop.c
+===================================================================
+--- a/src/gcc/tree-ssa-phiprop.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/tree-ssa-phiprop.c (.../branches/gcc-7-branch)
+@@ -327,7 +327,7 @@
+ if (!dominated_by_p (CDI_POST_DOMINATORS,
+ bb, gimple_bb (use_stmt)))
+ continue;
+-
++
+ /* Check whether this is a load of *ptr. */
+ if (!(is_gimple_assign (use_stmt)
+ && gimple_assign_rhs_code (use_stmt) == MEM_REF
+@@ -356,6 +356,9 @@
+ insert aggregate copies on the edges instead. */
+ if (!is_gimple_reg_type (TREE_TYPE (TREE_TYPE (ptr))))
+ {
++ if (!gimple_vdef (use_stmt))
++ goto next;
++
+ /* As we replicate the lhs on each incoming edge all
+ used SSA names have to be available there. */
+ if (! for_each_index (gimple_assign_lhs_ptr (use_stmt),
+@@ -363,6 +366,28 @@
+ get_immediate_dominator (CDI_DOMINATORS,
+ gimple_bb (phi))))
+ goto next;
++
++ gimple *vuse_stmt;
++ imm_use_iterator vui;
++ use_operand_p vuse_p;
++ /* In order to move the aggregate copies earlier, make sure
++ there are no statements that could read from memory
++ aliasing the lhs in between the start of bb and use_stmt.
++ As we require use_stmt to have a VDEF above, loads after
++ use_stmt will use a different virtual SSA_NAME. */
++ FOR_EACH_IMM_USE_FAST (vuse_p, vui, vuse)
++ {
++ vuse_stmt = USE_STMT (vuse_p);
++ if (vuse_stmt == use_stmt)
++ continue;
++ if (!dominated_by_p (CDI_DOMINATORS,
++ gimple_bb (vuse_stmt), bb))
++ continue;
++ if (ref_maybe_used_by_stmt_p (vuse_stmt,
++ gimple_assign_lhs (use_stmt)))
++ goto next;
++ }
++
+ phiprop_insert_phi (bb, phi, use_stmt, phivn, n);
+
+ /* Remove old stmt. The phi is taken care of by DCE. */
+Index: gcc/hsa-brig.c
+===================================================================
+--- a/src/gcc/hsa-brig.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/hsa-brig.c (.../branches/gcc-7-branch)
+@@ -499,7 +499,7 @@
+ else
+ part++;
+ char *modname2;
+- asprintf (&modname2, "%s_%s", modname, part);
++ modname2 = xasprintf ("%s_%s", modname, part);
+ free (modname);
+ modname = modname2;
+ }
+Index: gcc/config.gcc
+===================================================================
+--- a/src/gcc/config.gcc (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config.gcc (.../branches/gcc-7-branch)
+@@ -2031,7 +2031,7 @@
+ # automatically detect that GAS supports it, yet we require it.
+ gcc_cv_initfini_array=yes
+ ;;
+-riscv*-*-elf*)
++riscv*-*-elf* | riscv*-*-rtems*)
+ tm_file="elfos.h newlib-stdint.h ${tm_file} riscv/elf.h"
+ case "x${enable_multilib}" in
+ xno) ;;
+@@ -2044,6 +2044,11 @@
+ # Force .init_array support. The configure script cannot always
+ # automatically detect that GAS supports it, yet we require it.
+ gcc_cv_initfini_array=yes
++ case ${target} in
++ riscv*-*-rtems*)
++ tm_file="${tm_file} rtems.h riscv/rtems.h"
++ ;;
++ esac
+ ;;
+ mips*-*-netbsd*) # NetBSD/mips, either endian.
+ target_cpu_default="MASK_ABICALLS"
+@@ -2410,7 +2415,7 @@
+ use_gcc_stdint=wrap
+ ;;
+ powerpc-*-rtems*)
+- tm_file="${tm_file} dbxelf.h elfos.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/rtems.h rtems.h"
++ tm_file="rs6000/biarch64.h ${tm_file} dbxelf.h elfos.h freebsd-spec.h newlib-stdint.h rs6000/sysv4.h rs6000/e500.h rs6000/rtems.h rtems.h"
+ extra_options="${extra_options} rs6000/sysv4.opt"
+ tmake_file="${tmake_file} rs6000/t-fprules rs6000/t-rtems rs6000/t-ppccomm"
+ ;;
+@@ -4331,7 +4336,7 @@
+ for which in arch tune; do
+ eval "val=\$with_$which"
+ case ${val} in
+- "" | native | g5 | g6 | z900 | z990 | z9-109 | z9-ec | z10 | z196 | zEC12 | z13 | arch3 | arch5 | arch6 | arch7 | arch8 | arch9 | arch10 | arch11 | arch12)
++ "" | native | g5 | g6 | z900 | z990 | z9-109 | z9-ec | z10 | z196 | zEC12 | z13 | z14 | arch3 | arch5 | arch6 | arch7 | arch8 | arch9 | arch10 | arch11 | arch12)
+ # OK
+ ;;
+ *)
+@@ -4383,7 +4388,7 @@
+ | sparclite | f930 | f934 | sparclite86x \
+ | sparclet | tsc701 \
+ | v9 | ultrasparc | ultrasparc3 | niagara | niagara2 \
+- | niagara3 | niagara4 | niagara7)
++ | niagara3 | niagara4 | niagara7 | m8)
+ # OK
+ ;;
+ *)
Index: gcc/Makefile.in
===================================================================
--- a/src/gcc/Makefile.in (.../tags/gcc_7_1_0_release)
@@ -60545,6 +70191,137 @@ Index: gcc/Makefile.in
$(AWK) -f $(srcdir)/opt-gather.awk $(ALL_OPT_FILES) > tmp-optionlist
$(SHELL) $(srcdir)/../move-if-change tmp-optionlist optionlist
$(STAMP) s-options
+Index: gcc/tree-ssa-structalias.c
+===================================================================
+--- a/src/gcc/tree-ssa-structalias.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/tree-ssa-structalias.c (.../branches/gcc-7-branch)
+@@ -2827,7 +2827,6 @@
+ {
+ const char *res = NULL;
+ char *temp;
+- int num_printed = 0;
+
+ if (!dump_file)
+ return "NULL";
+@@ -2836,14 +2835,11 @@
+ {
+ res = get_name (decl);
+ if (res)
+- num_printed = asprintf (&temp, "%s_%u", res, SSA_NAME_VERSION (decl));
++ temp = xasprintf ("%s_%u", res, SSA_NAME_VERSION (decl));
+ else
+- num_printed = asprintf (&temp, "_%u", SSA_NAME_VERSION (decl));
+- if (num_printed > 0)
+- {
+- res = ggc_strdup (temp);
+- free (temp);
+- }
++ temp = xasprintf ("_%u", SSA_NAME_VERSION (decl));
++ res = ggc_strdup (temp);
++ free (temp);
+ }
+ else if (DECL_P (decl))
+ {
+@@ -2854,12 +2850,9 @@
+ res = get_name (decl);
+ if (!res)
+ {
+- num_printed = asprintf (&temp, "D.%u", DECL_UID (decl));
+- if (num_printed > 0)
+- {
+- res = ggc_strdup (temp);
+- free (temp);
+- }
++ temp = xasprintf ("D.%u", DECL_UID (decl));
++ res = ggc_strdup (temp);
++ free (temp);
+ }
+ }
+ }
+Index: gcc/tree-ssa-reassoc.c
+===================================================================
+--- a/src/gcc/tree-ssa-reassoc.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/tree-ssa-reassoc.c (.../branches/gcc-7-branch)
+@@ -4188,11 +4188,15 @@
+
+ /* Recursively rewrite our linearized statements so that the operators
+ match those in OPS[OPINDEX], putting the computation in rank
+- order. Return new lhs. */
++ order. Return new lhs.
++ CHANGED is true if we shouldn't reuse the lhs SSA_NAME both in
++ the current stmt and during recursive invocations.
++ NEXT_CHANGED is true if we shouldn't reuse the lhs SSA_NAME in
++ recursive invocations. */
+
+ static tree
+ rewrite_expr_tree (gimple *stmt, unsigned int opindex,
+- vec<operand_entry *> ops, bool changed)
++ vec<operand_entry *> ops, bool changed, bool next_changed)
+ {
+ tree rhs1 = gimple_assign_rhs1 (stmt);
+ tree rhs2 = gimple_assign_rhs2 (stmt);
+@@ -4283,7 +4287,8 @@
+ be the non-leaf side. */
+ tree new_rhs1
+ = rewrite_expr_tree (SSA_NAME_DEF_STMT (rhs1), opindex + 1, ops,
+- changed || oe->op != rhs2);
++ changed || oe->op != rhs2 || next_changed,
++ false);
+
+ if (oe->op != rhs2 || new_rhs1 != rhs1)
+ {
+@@ -5637,6 +5642,7 @@
+ gimple_set_visited (stmt, true);
+ linearize_expr_tree (&ops, stmt, true, true);
+ ops.qsort (sort_by_operand_rank);
++ int orig_len = ops.length ();
+ optimize_ops_list (rhs_code, &ops);
+ if (undistribute_ops_list (rhs_code, &ops,
+ loop_containing_stmt (stmt)))
+@@ -5727,7 +5733,8 @@
+
+ new_lhs = rewrite_expr_tree (stmt, 0, ops,
+ powi_result != NULL
+- || negate_result);
++ || negate_result,
++ len != orig_len);
+ }
+
+ /* If we combined some repeated factors into a
+Index: gcc/config/nvptx/nvptx.c
+===================================================================
+--- a/src/gcc/config/nvptx/nvptx.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/nvptx/nvptx.c (.../branches/gcc-7-branch)
+@@ -3860,10 +3860,26 @@
+ rtx_insn *tail = BB_END (to);
+ unsigned skip_mask = mask;
+
+- /* Find first insn of from block */
+- while (head != BB_END (from) && !INSN_P (head))
+- head = NEXT_INSN (head);
++ while (true)
++ {
++ /* Find first insn of from block. */
++ while (head != BB_END (from) && !INSN_P (head))
++ head = NEXT_INSN (head);
+
++ if (from == to)
++ break;
++
++ if (!(JUMP_P (head) && single_succ_p (from)))
++ break;
++
++ basic_block jump_target = single_succ (from);
++ if (!single_pred_p (jump_target))
++ break;
++
++ from = jump_target;
++ head = BB_HEAD (from);
++ }
++
+ /* Find last insn of to block */
+ rtx_insn *limit = from == to ? head : BB_HEAD (to);
+ while (tail != limit && !INSN_P (tail) && !LABEL_P (tail))
Index: gcc/config/s390/s390.md
===================================================================
--- a/src/gcc/config/s390/s390.md (.../tags/gcc_7_1_0_release)
@@ -60570,11 +70347,160 @@ Index: gcc/config/s390/s390.md
(set_attr "type" "branch")
(set_attr "atype" "agen")
(set_attr "cpu_facility" "*")])
+@@ -10278,7 +10280,7 @@
+ ; cdsg, csg
+ (define_insn "*atomic_compare_and_swap<mode>_1"
+ [(set (match_operand:TDI 0 "register_operand" "=r")
+- (match_operand:TDI 1 "s_operand" "+S"))
++ (match_operand:TDI 1 "memory_operand" "+S"))
+ (set (match_dup 1)
+ (unspec_volatile:TDI
+ [(match_dup 1)
+@@ -10296,7 +10298,7 @@
+ ; cds, cdsy
+ (define_insn "*atomic_compare_and_swapdi_2"
+ [(set (match_operand:DI 0 "register_operand" "=r,r")
+- (match_operand:DI 1 "s_operand" "+Q,S"))
++ (match_operand:DI 1 "memory_operand" "+Q,S"))
+ (set (match_dup 1)
+ (unspec_volatile:DI
+ [(match_dup 1)
+@@ -10317,7 +10319,7 @@
+ ; cs, csy
+ (define_insn "*atomic_compare_and_swapsi_3"
+ [(set (match_operand:SI 0 "register_operand" "=r,r")
+- (match_operand:SI 1 "s_operand" "+Q,S"))
++ (match_operand:SI 1 "memory_operand" "+Q,S"))
+ (set (match_dup 1)
+ (unspec_volatile:SI
+ [(match_dup 1)
+Index: gcc/config/s390/s390.opt
+===================================================================
+--- a/src/gcc/config/s390/s390.opt (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/s390/s390.opt (.../branches/gcc-7-branch)
+@@ -113,9 +113,12 @@
+ Enum(processor_type) String(arch11) Value(PROCESSOR_2964_Z13)
+
+ EnumValue
+-Enum(processor_type) String(arch12) Value(PROCESSOR_ARCH12)
++Enum(processor_type) String(z14) Value(PROCESSOR_3906_Z14)
+
+ EnumValue
++Enum(processor_type) String(arch12) Value(PROCESSOR_3906_Z14)
++
++EnumValue
+ Enum(processor_type) String(native) Value(PROCESSOR_NATIVE) DriverOnly
+
+ mbackchain
+Index: gcc/config/s390/s390-c.c
+===================================================================
+--- a/src/gcc/config/s390/s390-c.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/s390/s390-c.c (.../branches/gcc-7-branch)
+@@ -886,7 +886,7 @@
+
+ if (!TARGET_VXE && (ob_flags & B_VXE))
+ {
+- error_at (loc, "%qF requires -march=arch12 or higher", ob_fndecl);
++ error_at (loc, "%qF requires z14 or higher", ob_fndecl);
+ return error_mark_node;
+ }
+
+@@ -963,7 +963,7 @@
+ if (!TARGET_VXE
+ && bflags_overloaded_builtin_var[last_match_index] & B_VXE)
+ {
+- error_at (loc, "%qs matching variant requires -march=arch12 or higher",
++ error_at (loc, "%qs matching variant requires z14 or higher",
+ IDENTIFIER_POINTER (DECL_NAME (ob_fndecl)));
+ return error_mark_node;
+ }
+Index: gcc/config/s390/driver-native.c
+===================================================================
+--- a/src/gcc/config/s390/driver-native.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/s390/driver-native.c (.../branches/gcc-7-branch)
+@@ -112,10 +112,14 @@
+ cpu = "zEC12";
+ break;
+ case 0x2964:
++ case 0x2965:
+ cpu = "z13";
+ break;
++ case 0x3906:
++ cpu = "z14";
++ break;
+ default:
+- cpu = "arch12";
++ cpu = "z14";
+ break;
+ }
+ }
+Index: gcc/config/s390/s390-opts.h
+===================================================================
+--- a/src/gcc/config/s390/s390-opts.h (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/s390/s390-opts.h (.../branches/gcc-7-branch)
+@@ -38,7 +38,7 @@
+ PROCESSOR_2817_Z196,
+ PROCESSOR_2827_ZEC12,
+ PROCESSOR_2964_Z13,
+- PROCESSOR_ARCH12,
++ PROCESSOR_3906_Z14,
+ PROCESSOR_NATIVE,
+ PROCESSOR_max
+ };
Index: gcc/config/s390/s390.c
===================================================================
--- a/src/gcc/config/s390/s390.c (.../tags/gcc_7_1_0_release)
+++ b/src/gcc/config/s390/s390.c (.../branches/gcc-7-branch)
-@@ -3102,6 +3102,9 @@
+@@ -318,24 +318,27 @@
+
+ static struct
+ {
++ /* The preferred name to be used in user visible output. */
+ const char *const name;
++ /* CPU name as it should be passed to Binutils via .machine */
++ const char *const binutils_name;
+ const enum processor_type processor;
+ const struct processor_costs *cost;
+ }
+ const processor_table[] =
+ {
+- { "g5", PROCESSOR_9672_G5, &z900_cost },
+- { "g6", PROCESSOR_9672_G6, &z900_cost },
+- { "z900", PROCESSOR_2064_Z900, &z900_cost },
+- { "z990", PROCESSOR_2084_Z990, &z990_cost },
+- { "z9-109", PROCESSOR_2094_Z9_109, &z9_109_cost },
+- { "z9-ec", PROCESSOR_2094_Z9_EC, &z9_109_cost },
+- { "z10", PROCESSOR_2097_Z10, &z10_cost },
+- { "z196", PROCESSOR_2817_Z196, &z196_cost },
+- { "zEC12", PROCESSOR_2827_ZEC12, &zEC12_cost },
+- { "z13", PROCESSOR_2964_Z13, &zEC12_cost },
+- { "arch12", PROCESSOR_ARCH12, &zEC12_cost },
+- { "native", PROCESSOR_NATIVE, NULL }
++ { "g5", "g5", PROCESSOR_9672_G5, &z900_cost },
++ { "g6", "g6", PROCESSOR_9672_G6, &z900_cost },
++ { "z900", "z900", PROCESSOR_2064_Z900, &z900_cost },
++ { "z990", "z990", PROCESSOR_2084_Z990, &z990_cost },
++ { "z9-109", "z9-109", PROCESSOR_2094_Z9_109, &z9_109_cost },
++ { "z9-ec", "z9-ec", PROCESSOR_2094_Z9_EC, &z9_109_cost },
++ { "z10", "z10", PROCESSOR_2097_Z10, &z10_cost },
++ { "z196", "z196", PROCESSOR_2817_Z196, &z196_cost },
++ { "zEC12", "zEC12", PROCESSOR_2827_ZEC12, &zEC12_cost },
++ { "z13", "z13", PROCESSOR_2964_Z13, &zEC12_cost },
++ { "z14", "arch12", PROCESSOR_3906_Z14, &zEC12_cost },
++ { "native", "", PROCESSOR_NATIVE, NULL }
+ };
+
+ extern int reload_completed;
+@@ -847,7 +850,7 @@
+
+ if ((bflags & B_VXE) && !TARGET_VXE)
+ {
+- error ("Builtin %qF requires arch12 or higher.", fndecl);
++ error ("Builtin %qF requires z14 or higher.", fndecl);
+ return const0_rtx;
+ }
+ }
+@@ -3102,6 +3105,9 @@
struct s390_address addr;
bool decomposed = false;
@@ -60584,6 +70510,126 @@ Index: gcc/config/s390/s390.c
/* This check makes sure that no symbolic address (except literal
pool references) are accepted by the R or T constraints. */
if (s390_loadrelative_operand_p (op, NULL, NULL))
+@@ -7279,7 +7285,8 @@
+ {
+ fprintf (asm_out_file, "\t.machinemode %s\n",
+ (TARGET_ZARCH) ? "zarch" : "esa");
+- fprintf (asm_out_file, "\t.machine \"%s", processor_table[s390_arch].name);
++ fprintf (asm_out_file, "\t.machine \"%s",
++ processor_table[s390_arch].binutils_name);
+ if (S390_USE_ARCHITECTURE_MODIFIERS)
+ {
+ int cpu_flags;
+@@ -8013,7 +8020,7 @@
+ instruction gets issued per cycle. */
+ case PROCESSOR_2827_ZEC12:
+ case PROCESSOR_2964_Z13:
+- case PROCESSOR_ARCH12:
++ case PROCESSOR_3906_Z14:
+ default:
+ return 1;
+ }
+@@ -14234,7 +14241,7 @@
+ mask |= S390_SCHED_ATTR_MASK_GROUPALONE;
+ break;
+ case PROCESSOR_2964_Z13:
+- case PROCESSOR_ARCH12:
++ case PROCESSOR_3906_Z14:
+ if (get_attr_z13_cracked (insn))
+ mask |= S390_SCHED_ATTR_MASK_CRACKED;
+ if (get_attr_z13_expanded (insn))
+@@ -14258,7 +14265,7 @@
+ switch (s390_tune)
+ {
+ case PROCESSOR_2964_Z13:
+- case PROCESSOR_ARCH12:
++ case PROCESSOR_3906_Z14:
+ *units = 3;
+ if (get_attr_z13_unit_lsu (insn))
+ mask |= 1 << 0;
+Index: gcc/config/m32c/rtems.h
+===================================================================
+--- a/src/gcc/config/m32c/rtems.h (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/m32c/rtems.h (.../branches/gcc-7-branch)
+@@ -2,22 +2,27 @@
+ Copyright (C) 2008-2017 Free Software Foundation, Inc.
+ Contributed by Joel Sherrill (joel at OARcorp.com).
+
+-This file is part of GCC.
++ This file is part of GCC.
+
+-GCC is free software; you can redistribute it and/or modify
+-it under the terms of the GNU General Public License as published by
+-the Free Software Foundation; either version 3, or (at your option)
+-any later version.
++ GCC is free software; you can redistribute it and/or modify it
++ under the terms of the GNU General Public License as published
++ by the Free Software Foundation; either version 3, or (at your
++ option) any later version.
+
+-GCC is distributed in the hope that it will be useful,
+-but WITHOUT ANY WARRANTY; without even the implied warranty of
+-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-GNU General Public License for more details.
++ GCC is distributed in the hope that it will be useful, but WITHOUT
++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
++ License for more details.
+
+-You should have received a copy of the GNU General Public License
+-along with GCC; see the file COPYING3. If not see
+-<http://www.gnu.org/licenses/>. */
++ Under Section 7 of GPL version 3, you are granted additional
++ permissions described in the GCC Runtime Library Exception, version
++ 3.1, as published by the Free Software Foundation.
+
++ You should have received a copy of the GNU General Public License and
++ a copy of the GCC Runtime Library Exception along with this program;
++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
++ <http://www.gnu.org/licenses/>. */
++
+ /* Target OS builtins. */
+ #undef TARGET_OS_CPP_BUILTINS
+ #define TARGET_OS_CPP_BUILTINS() \
+Index: gcc/config/sparc/predicates.md
+===================================================================
+--- a/src/gcc/config/sparc/predicates.md (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/sparc/predicates.md (.../branches/gcc-7-branch)
+@@ -328,7 +328,34 @@
+ (and (match_code "const_int")
+ (match_test "SPARC_SIMM5_P (INTVAL (op))"))))
+
++;; Return true if OP is a constant in the range 0..7. This is an
++;; acceptable second operand for dictunpack instructions setting a
++;; V8QI mode in the destination register.
++(define_predicate "imm5_operand_dictunpack8"
++ (and (match_code "const_int")
++ (match_test "(INTVAL (op) >= 0 && INTVAL (op) < 8)")))
+
++;; Return true if OP is a constant in the range 7..15. This is an
++;; acceptable second operand for dictunpack instructions setting a
++;; V4HI mode in the destination register.
++(define_predicate "imm5_operand_dictunpack16"
++ (and (match_code "const_int")
++ (match_test "(INTVAL (op) >= 8 && INTVAL (op) < 16)")))
++
++;; Return true if OP is a constant in the range 15..31. This is an
++;; acceptable second operand for dictunpack instructions setting a
++;; V2SI mode in the destination register.
++(define_predicate "imm5_operand_dictunpack32"
++ (and (match_code "const_int")
++ (match_test "(INTVAL (op) >= 16 && INTVAL (op) < 32)")))
++
++;; Return true if OP is a constant that is representable by a 2-bit
++;; unsigned field. This is an acceptable third operand for
++;; fpcmp*shl instructions.
++(define_predicate "imm2_operand"
++ (and (match_code "const_int")
++ (match_test "SPARC_IMM2_P (INTVAL (op))")))
++
+ ;; Predicates for miscellaneous instructions.
+
+ ;; Return true if OP is valid for the lhs of a comparison insn.
Index: gcc/config/sparc/driver-sparc.c
===================================================================
--- a/src/gcc/config/sparc/driver-sparc.c (.../tags/gcc_7_1_0_release)
@@ -60596,7 +70642,7 @@ Index: gcc/config/sparc/driver-sparc.c
#else
{ "SuperSparc", "supersparc" },
{ "HyperSparc", "hypersparc" },
-@@ -73,6 +74,7 @@
+@@ -73,10 +74,12 @@
{ "UltraSparc T2", "niagara2" },
{ "UltraSparc T3", "niagara3" },
{ "UltraSparc T4", "niagara4" },
@@ -60604,11 +70650,727 @@ Index: gcc/config/sparc/driver-sparc.c
{ "LEON", "leon3" },
#endif
{ "SPARC-M7", "niagara7" },
+ { "SPARC-S7", "niagara7" },
++ { "SPARC-M8", "m8" },
+ { NULL, NULL }
+ };
+
+Index: gcc/config/sparc/m8.md
+===================================================================
+--- a/src/gcc/config/sparc/m8.md (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/sparc/m8.md (.../branches/gcc-7-branch)
+@@ -0,0 +1,242 @@
++;; Scheduling description for the SPARC M8.
++;; Copyright (C) 2017 Free Software Foundation, Inc.
++;;
++;; This file is part of GCC.
++;;
++;; GCC is free software; you can redistribute it and/or modify
++;; it under the terms of the GNU General Public License as published by
++;; the Free Software Foundation; either version 3, or (at your option)
++;; any later version.
++;;
++;; GCC is distributed in the hope that it will be useful,
++;; but WITHOUT ANY WARRANTY; without even the implied warranty of
++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++;; GNU General Public License for more details.
++;;
++;; You should have received a copy of the GNU General Public License
++;; along with GCC; see the file COPYING3. If not see
++;; <http://www.gnu.org/licenses/>.
++
++;; Thigs to improve:
++;;
++;; - Store instructions are implemented by micro-ops, one of which
++;; generates the store address and is executed in the store address
++;; generation unit in the slot0. We need to model that.
++;;
++;; - There are two V3 pipes connected to different slots. The current
++;; implementation assumes that all the instructions executing in a
++;; V3 pipe are issued to the unit in slot3.
++;;
++;; - Single-issue ALU operations incur an additional cycle of latency to
++;; slot 0 and slot 1 instructions. This is not currently reflected
++;; in the DFA.
++
++(define_automaton "m8_0")
++
++;; The S5 core has two dual-issue queues, PQLS and PQEX. Each queue
++;; is divided into two slots: PQLS corresponds to slots 0 and 1, and
++;; PQEX corresponds to slots 2 and 3. The core can issue 4
++;; instructions per-cycle, and up to 4 instructions are committed each
++;; cycle.
++;;
++;;
++;; m8_slot0 - Load Unit.
++;; - Store address gen. Unit.
++;;
++;;
++;; === PQLS ==> m8_slot1 - Store data unit.
++;; - Branch unit.
++;;
++;;
++;; === PQEX ==> m8_slot2 - Integer Unit (EXU2).
++;; - 3-cycles Crypto Unit (SPU2).
++;;
++;; m8_slot3 - Integer Unit (EXU3).
++;; - 3-cycles Crypto Unit (SPU3).
++;; - Floating-point and graphics unit (FPG).
++;; - Long-latency Crypto Unit.
++;; - Oracle Numbers Unit (ONU).
++
++(define_cpu_unit "m8_slot0,m8_slot1,m8_slot2,m8_slot3" "m8_0")
++
++;; Some instructions stall the pipeline and avoid any other
++;; instruction to be issued in the same cycle. We assume the same for
++;; multi-instruction insns.
++
++(define_reservation "m8_single_issue" "m8_slot0 + m8_slot1 + m8_slot2 + m8_slot3")
++
++(define_insn_reservation "m8_single" 1
++ (and (eq_attr "cpu" "m8")
++ (eq_attr "type" "multi,savew,flushw,trap,bmask"))
++ "m8_single_issue")
++
++;; Most of the instructions executing in the integer units have a
++;; latency of 1.
++
++(define_insn_reservation "m8_integer" 1
++ (and (eq_attr "cpu" "m8")
++ (eq_attr "type" "ialu,ialuX,shift,cmove,compare,bmask"))
++ "(m8_slot2 | m8_slot3)")
++
++;; Flushing the instruction memory takes 27 cycles.
++
++
++(define_insn_reservation "m8_iflush" 27
++ (and (eq_attr "cpu" "m8")
++ (eq_attr "type" "iflush"))
++ "(m8_slot2 | m8_slot3), nothing*26")
++
++;; The integer multiplication instructions have a latency of 10 cycles
++;; and execute in integer units.
++;;
++;; Likewise for array*, edge* and pdistn instructions.
++;;
++;; However, the latency is only 9 cycles if the consumer of the
++;; operation is also capable of 9 cycles latency. We model this with
++;; a bypass.
++
++(define_insn_reservation "m8_imul" 10
++ (and (eq_attr "cpu" "m8")
++ (eq_attr "type" "imul,array,edge,edgen,pdistn"))
++ "(m8_slot2 | m8_slot3), nothing*12")
++
++(define_bypass 9 "m8_imul" "m8_imul")
++
++;; The integer division instructions `sdiv' and `udivx' have a latency
++;; of 30 cycles and execute in integer units.
++
++(define_insn_reservation "m8_idiv" 30
++ (and (eq_attr "cpu" "m8")
++ (eq_attr "type" "idiv"))
++ "(m8_slot2 | m8_slot3), nothing*29")
++
++;; Both integer and floating-point load instructions have a latency of
++;; only 3 cycles,and execute in the slot0.
++;;
++;; Misaligned load instructions feature a latency of 11 cycles.
++;;
++;; The prefetch instruction also executes in the load unit, but it's
++;; latency is only 1 cycle.
++
++(define_insn_reservation "m8_load" 3
++ (and (eq_attr "cpu" "m8")
++ (ior (eq_attr "type" "fpload,sload")
++ (and (eq_attr "type" "load")
++ (eq_attr "subtype" "regular"))))
++ "m8_slot0, nothing*2")
++
++;; (define_insn_reservation "m8_load_misalign" 11
++;; (and (eq_attr "cpu" "m8")
++;; (eq_attr "type" "load_mis,fpload_mis"))
++;; "m8_slot0, nothing*10")
++
++(define_insn_reservation "m8_prefetch" 1
++ (and (eq_attr "cpu" "m8")
++ (eq_attr "type" "load")
++ (eq_attr "subtype" "prefetch"))
++ "m8_slot0")
++
++;; Both integer and floating-point store instructions have a latency
++;; of 1 cycle, and execute in the store data unit in slot1.
++;;
++;; However, misaligned store instructions feature a latency of 3
++;; cycles.
++
++(define_insn_reservation "m8_store" 1
++ (and (eq_attr "cpu" "m8")
++ (eq_attr "type" "store,fpstore"))
++ "m8_slot1")
++
++;; (define_insn_reservation "m8_store_misalign" 3
++;; (and (eq_attr "cpu" "m8")
++;; (eq_attr "type" "store_mis,fpstore_mis"))
++;; "m8_slot1, nothing*2")
++
++;; Control-transfer instructions execute in the Branch Unit in the
++;; slot1.
++
++(define_insn_reservation "m8_cti" 1
++ (and (eq_attr "cpu" "m8")
++ (eq_attr "type" "cbcond,uncond_cbcond,branch,call,sibcall,call_no_delay_slot,uncond_branch,return"))
++ "m8_slot1")
++
++;; Many instructions executing in the Floating-point and Graphics Unit
++;; (FGU) serving slot3 feature a default latency of 9 cycles.
++
++(define_insn_reservation "m8_fp" 9
++ (and (eq_attr "cpu" "m8")
++ (ior (eq_attr "type" "fpmove,fpcmove,fpcrmove,fp,fpcmp,fpmul,fgm_pack,fgm_mul,pdist")
++ (and (eq_attr "type" "fga")
++ (eq_attr "subtype" "fpu"))))
++ "m8_slot3, nothing*8")
++
++;; Floating-point division and floating-point square-root instructions
++;; have high latencies. They execute in the FGU.
++
++(define_insn_reservation "m8_fpdivs" 26
++ (and (eq_attr "cpu" "m8")
++ (eq_attr "type" "fpdivs"))
++ "m8_slot3, nothing*25")
++
++(define_insn_reservation "m8_fpsqrts" 33
++ (and (eq_attr "cpu" "m8")
++ (eq_attr "type" "fpsqrts"))
++ "m8_slot3, nothing*32")
++
++(define_insn_reservation "m8_fpdivd" 30
++ (and (eq_attr "cpu" "m8")
++ (eq_attr "type" "fpdivd"))
++ "m8_slot3, nothing*29")
++
++(define_insn_reservation "m8_fpsqrtd" 41
++ (and (eq_attr "cpu" "m8")
++ (eq_attr "type" "fpsqrtd"))
++ "m8_slot3, nothing*40")
++
++;; SIMD VIS instructions executing in the Floating-point and graphics
++;; unit (FPG) in slot3 usually have a latency of 5 cycles.
++;;
++;; However, the latency for many instructions is only 3 cycles if the
++;; consumer can also be executed in 3 cycles. We model this with a
++;; bypass. In these cases the instructions are executed in one of the
++;; two 3-cycle crypto units (SPU, also known as "v3-pipes") in slots 2
++;; and 3.
++
++(define_insn_reservation "m8_vis" 5
++ (and (eq_attr "cpu" "m8")
++ (ior (eq_attr "type" "viscmp,lzd")
++ (and (eq_attr "type" "fga")
++ (eq_attr "subtype" "maxmin,cmask,other"))
++ (and (eq_attr "type" "vismv")
++ (eq_attr "subtype" "single,movstouw"))
++ (and (eq_attr "type" "visl")
++ (eq_attr "subtype" "single"))))
++ "m8_slot3, nothing*4")
++
++(define_bypass 3 "m8_vis" "m8_vis")
++
++(define_insn_reservation "m8_gsr" 5
++ (and (eq_attr "cpu" "m8")
++ (eq_attr "type" "gsr")
++ (eq_attr "subtype" "alignaddr"))
++ "m8_slot3, nothing*4")
++
++;; A few VIS instructions have a latency of 1.
++
++(define_insn_reservation "m8_vis_1cycle" 1
++ (and (eq_attr "cpu" "m8")
++ (ior (and (eq_attr "type" "vismv")
++ (eq_attr "subtype" "double,movxtod,movdtox"))
++ (and (eq_attr "type" "visl")
++ (eq_attr "subtype" "double"))
++ (and (eq_attr "type" "fga")
++ (eq_attr "subtype" "addsub64"))))
++ "m8_slot3")
++
++;; Reading and writing to the gsr register takes more than 70 cycles.
++
++(define_insn_reservation "m8_gsr_reg" 70
++ (and (eq_attr "cpu" "m8")
++ (eq_attr "type" "gsr")
++ (eq_attr "subtype" "reg"))
++ "m8_slot3, nothing*69")
+Index: gcc/config/sparc/niagara7.md
+===================================================================
+--- a/src/gcc/config/sparc/niagara7.md (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/sparc/niagara7.md (.../branches/gcc-7-branch)
+@@ -19,20 +19,36 @@
+
+ (define_automaton "niagara7_0")
+
+-(define_cpu_unit "n7_slot0,n7_slot1,n7_slot2" "niagara7_0")
+-(define_reservation "n7_single_issue" "n7_slot0 + n7_slot1 + n7_slot2")
++;; The S4 core has a dual-issue queue. This queue is divided into two
++;; slots. One instruction can be issued each cycle to each slot, and
++;; up to 2 instructions are committed each cycle. Each slot serves
++;; several execution units, as depicted below:
++;;
++;;
++;; m7_slot0 - Integer unit.
++;; - Load/Store unit.
++;; === QUEUE ==>
++;;
++;; m7_slot1 - Integer unit.
++;; - Branch unit.
++;; - Floating-point and graphics unit.
++;; - 3-cycles crypto unit.
+
+-(define_cpu_unit "n7_load_store" "niagara7_0")
++(define_cpu_unit "n7_slot0,n7_slot1" "niagara7_0")
+
++;; Some instructions stall the pipeline and avoid any other
++;; instruction to be issued in the same cycle. We assume the same for
++;; multi-instruction insns.
++
++(define_reservation "n7_single_issue" "n7_slot0 + n7_slot1")
++
+ (define_insn_reservation "n7_single" 1
+ (and (eq_attr "cpu" "niagara7")
+ (eq_attr "type" "multi,savew,flushw,trap"))
+ "n7_single_issue")
+
+-(define_insn_reservation "n7_iflush" 27
+- (and (eq_attr "cpu" "niagara7")
+- (eq_attr "type" "iflush"))
+- "(n7_slot0 | n7_slot1), nothing*26")
++;; Most of the instructions executing in the integer unit have a
++;; latency of 1.
+
+ (define_insn_reservation "n7_integer" 1
+ (and (eq_attr "cpu" "niagara7")
+@@ -39,44 +55,84 @@
+ (eq_attr "type" "ialu,ialuX,shift,cmove,compare"))
+ "(n7_slot0 | n7_slot1)")
+
++;; Flushing the instruction memory takes 27 cycles.
++
++(define_insn_reservation "n7_iflush" 27
++ (and (eq_attr "cpu" "niagara7")
++ (eq_attr "type" "iflush"))
++ "(n7_slot0 | n7_slot1), nothing*26")
++
++;; The integer multiplication instructions have a latency of 12 cycles
++;; and execute in the integer unit.
++;;
++;; Likewise for array*, edge* and pdistn instructions.
++
+ (define_insn_reservation "n7_imul" 12
+ (and (eq_attr "cpu" "niagara7")
+- (eq_attr "type" "imul"))
+- "n7_slot1, nothing*11")
++ (eq_attr "type" "imul,array,edge,edgen,pdistn"))
++ "(n7_slot0 | n7_slot1), nothing*11")
+
++;; The integer division instructions have a latency of 35 cycles and
++;; execute in the integer unit.
++
+ (define_insn_reservation "n7_idiv" 35
+ (and (eq_attr "cpu" "niagara7")
+ (eq_attr "type" "idiv"))
+- "n7_slot1, nothing*34")
++ "(n7_slot0 | n7_slot1), nothing*34")
+
++;; Both integer and floating-point load instructions have a latency of
++;; 5 cycles, and execute in the slot0.
++;;
++;; The prefetch instruction also executes in the load/store unit, but
++;; its latency is only 1 cycle.
++
+ (define_insn_reservation "n7_load" 5
+ (and (eq_attr "cpu" "niagara7")
+- (eq_attr "type" "load,fpload,sload"))
+- "(n7_slot0 + n7_load_store), nothing*4")
++ (ior (eq_attr "type" "fpload,sload")
++ (and (eq_attr "type" "load")
++ (eq_attr "subtype" "regular"))))
++ "n7_slot0, nothing*4")
+
++(define_insn_reservation "n7_prefetch" 1
++ (and (eq_attr "cpu" "niagara7")
++ (eq_attr "type" "load")
++ (eq_attr "subtype" "prefetch"))
++ "n7_slot0")
++
++;; Both integer and floating-point store instructions have a latency
++;; of 1 cycle, and execute in the load/store unit in slot0.
++
+ (define_insn_reservation "n7_store" 1
+ (and (eq_attr "cpu" "niagara7")
+ (eq_attr "type" "store,fpstore"))
+- "(n7_slot0 | n7_slot2) + n7_load_store")
++ "n7_slot0")
+
++;; Control-transfer instructions execute in the Branch Unit in the
++;; slot1.
++
+ (define_insn_reservation "n7_cti" 1
+ (and (eq_attr "cpu" "niagara7")
+ (eq_attr "type" "cbcond,uncond_cbcond,branch,call,sibcall,call_no_delay_slot,uncond_branch,return"))
+ "n7_slot1")
+
++;; Many instructions executing in the Floating-point and Graphics unit
++;; in the slot1 feature a latency of 11 cycles.
++
+ (define_insn_reservation "n7_fp" 11
+ (and (eq_attr "cpu" "niagara7")
+- (eq_attr "type" "fpmove,fpcmove,fpcrmove,fp,fpcmp,fpmul"))
++ (ior (eq_attr "type" "fpmove,fpcmove,fpcrmove,fp,fpcmp,fpmul,fgm_pack,fgm_mul,pdist")
++ (and (eq_attr "type" "fga")
++ (eq_attr "subtype" "fpu,maxmin"))))
+ "n7_slot1, nothing*10")
+
+-(define_insn_reservation "n7_array" 12
+- (and (eq_attr "cpu" "niagara7")
+- (eq_attr "type" "array,edge,edgen"))
+- "n7_slot1, nothing*11")
++;; Floating-point division and floating-point square-root instructions
++;; have high latencies. They execute in the floating-point and
++;; graphics unit in the slot1.
+
++
+ (define_insn_reservation "n7_fpdivs" 24
+ (and (eq_attr "cpu" "niagara7")
+- (eq_attr "type" "fpdivs,fpsqrts"))
++ (eq_attr "type" "fpdivs,fpsqrts"))
+ "n7_slot1, nothing*23")
+
+ (define_insn_reservation "n7_fpdivd" 37
+@@ -84,53 +140,66 @@
+ (eq_attr "type" "fpdivd,fpsqrtd"))
+ "n7_slot1, nothing*36")
+
+-(define_insn_reservation "n7_lzd" 12
+- (and (eq_attr "cpu" "niagara7")
+- (eq_attr "type" "lzd"))
+- "(n7_slot0 | n7_slot1), nothing*11")
+-
+-;; There is an internal unit called the "V3 pipe", that was originally
+-;; intended to process some of the short cryptographic instructions.
+-;; However, as soon as in the T4 several of the VIS instructions
+-;; (notably non-FP instructions) have been moved to the V3 pipe.
+-;; Consequently, these instructions feature a latency of 3 instead of
+-;; 11 or 12 cycles, provided their consumers also execute in the V3
+-;; pipe.
++;; SIMD VIS instructions executing in the Floating-point and graphics
++;; unit (FPG) in slot1 usually have a latency of either 11 or 12
++;; cycles.
+ ;;
+-;; This is modelled here with a bypass.
++;; However, the latency for many instructions is only 3 cycles if the
++;; consumer can also be executed in 3 cycles. We model this with a
++;; bypass. In these cases the instructions are executed in the
++;; 3-cycle crypto unit which also serves slot1.
+
+-(define_insn_reservation "n7_vis_fga" 11
++(define_insn_reservation "n7_vis_11cycles" 11
+ (and (eq_attr "cpu" "niagara7")
+- (eq_attr "type" "fga,gsr"))
++ (ior (and (eq_attr "type" "fga")
++ (eq_attr "subtype" "addsub64,other"))
++ (and (eq_attr "type" "vismv")
++ (eq_attr "subtype" "double,single"))
++ (and (eq_attr "type" "visl")
++ (eq_attr "subtype" "double,single"))))
+ "n7_slot1, nothing*10")
+
+-(define_insn_reservation "n7_vis_fgm" 11
++(define_insn_reservation "n7_vis_12cycles" 12
+ (and (eq_attr "cpu" "niagara7")
+- (eq_attr "type" "fgm_pack,fgm_mul,pdist"))
+- "n7_slot1, nothing*10")
++ (ior (eq_attr "type" "bmask,viscmp")
++ (and (eq_attr "type" "fga")
++ (eq_attr "subtype" "cmask"))
++ (and (eq_attr "type" "vismv")
++ (eq_attr "subtype" "movstouw"))))
++ "n7_slot1, nothing*11")
+
+-(define_insn_reservation "n7_vis_move_v3pipe" 11
++(define_bypass 3 "n7_vis_*" "n7_vis_*")
++
++;; Some other VIS instructions have a latency of 12 cycles, and won't
++;; be executed in the 3-cycle crypto pipe.
++
++(define_insn_reservation "n7_lzd" 12
+ (and (eq_attr "cpu" "niagara7")
+- (and (eq_attr "type" "vismv")
+- (eq_attr "v3pipe" "true")))
+- "n7_slot1")
++ (ior (eq_attr "type" "lzd,")
++ (and (eq_attr "type" "gsr")
++ (eq_attr "subtype" "alignaddr"))))
++ "n7_slot1, nothing*11")
+
+-(define_insn_reservation "n7_vis_move_11cycle" 11
++;; A couple of VIS instructions feature very low latencies in the M7.
++
++(define_insn_reservation "n7_single_vis" 1
+ (and (eq_attr "cpu" "niagara7")
+- (and (eq_attr "type" "vismv")
+- (eq_attr "v3pipe" "false")))
+- "n7_slot1, nothing*10")
++ (eq_attr "type" "vismv")
++ (eq_attr "subtype" "movxtod"))
++ "n7_slot1")
+
+-(define_insn_reservation "n7_vis_logical_v3pipe" 11
++(define_insn_reservation "n7_double_vis" 2
+ (and (eq_attr "cpu" "niagara7")
+- (and (eq_attr "type" "visl,pdistn")
+- (eq_attr "v3pipe" "true")))
+- "n7_slot1, nothing*2")
++ (eq_attr "type" "vismv")
++ (eq_attr "subtype" "movdtox"))
++ "n7_slot1, nothing")
+
+-(define_insn_reservation "n7_vis_logical_11cycle" 11
++;; Reading and writing to the gsr register takes a high number of
++;; cycles that is not documented in the PRM. Let's use the same value
++;; than the M8.
++
++(define_insn_reservation "n7_gsr_reg" 70
+ (and (eq_attr "cpu" "niagara7")
+- (and (eq_attr "type" "visl")
+- (eq_attr "v3pipe" "false")))
+- "n7_slot1, nothing*10")
+-
+-(define_bypass 3 "*_v3pipe" "*_v3pipe")
++ (eq_attr "type" "gsr")
++ (eq_attr "subtype" "reg"))
++ "n7_slot1, nothing*70")
+Index: gcc/config/sparc/t-rtems
+===================================================================
+--- a/src/gcc/config/sparc/t-rtems (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/sparc/t-rtems (.../branches/gcc-7-branch)
+@@ -18,19 +18,25 @@
+ #
+
+ MULTILIB_OPTIONS = msoft-float mcpu=v8/mcpu=leon3/mcpu=leon3v7/mcpu=leon \
+- mfix-ut699/mfix-at697f
+-MULTILIB_DIRNAMES = soft v8 leon3 leon3v7 leon ut699 at697f
+-MULTILIB_MATCHES = msoft-float=mno-fpu
++ mfix-ut699/mfix-at697f/mfix-gr712rc
++MULTILIB_DIRNAMES = soft v8 leon3 leon3v7 leon ut699 at697f gr712rc
++MULTILIB_MATCHES = msoft-float=mno-fpu mfix-gr712rc=mfix-ut700
+
+-MULTILIB_EXCEPTIONS = mfix-ut699
+-MULTILIB_EXCEPTIONS += msoft-float/mfix-ut699
+-MULTILIB_EXCEPTIONS += msoft-float/mcpu=v8/mfix-ut699
+-MULTILIB_EXCEPTIONS += msoft-float/mcpu=leon3*/mfix-ut699
+-MULTILIB_EXCEPTIONS += mcpu=v8/mfix-ut699
+-MULTILIB_EXCEPTIONS += mcpu=leon3*/mfix-ut699
+-MULTILIB_EXCEPTIONS += mfix-at697f
+-MULTILIB_EXCEPTIONS += msoft-float/mfix-at697f
+-MULTILIB_EXCEPTIONS += msoft-float/mcpu=v8/mfix-at697f
+-MULTILIB_EXCEPTIONS += msoft-float/mcpu=leon3*/mfix-at697f
+-MULTILIB_EXCEPTIONS += mcpu=v8/mfix-at697f
+-MULTILIB_EXCEPTIONS += mcpu=leon3*/mfix-at697f
++MULTILIB_REQUIRED =
++MULTILIB_REQUIRED += msoft-float
++MULTILIB_REQUIRED += mcpu=v8
++MULTILIB_REQUIRED += mcpu=leon3
++MULTILIB_REQUIRED += mcpu=leon3v7
++MULTILIB_REQUIRED += mcpu=leon
++MULTILIB_REQUIRED += mcpu=leon3/mfix-gr712rc
++MULTILIB_REQUIRED += mcpu=leon3v7/mfix-gr712rc
++MULTILIB_REQUIRED += mcpu=leon/mfix-ut699
++MULTILIB_REQUIRED += mcpu=leon/mfix-at697f
++MULTILIB_REQUIRED += msoft-float/mcpu=v8
++MULTILIB_REQUIRED += msoft-float/mcpu=leon3
++MULTILIB_REQUIRED += msoft-float/mcpu=leon3v7
++MULTILIB_REQUIRED += msoft-float/mcpu=leon
++MULTILIB_REQUIRED += msoft-float/mcpu=leon3/mfix-gr712rc
++MULTILIB_REQUIRED += msoft-float/mcpu=leon3v7/mfix-gr712rc
++MULTILIB_REQUIRED += msoft-float/mcpu=leon/mfix-ut699
++MULTILIB_REQUIRED += msoft-float/mcpu=leon/mfix-at697f
+Index: gcc/config/sparc/niagara.md
+===================================================================
+--- a/src/gcc/config/sparc/niagara.md (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/sparc/niagara.md (.../branches/gcc-7-branch)
+@@ -114,5 +114,5 @@
+ */
+ (define_insn_reservation "niag_vis" 8
+ (and (eq_attr "cpu" "niagara")
+- (eq_attr "type" "fga,visl,vismv,fgm_pack,fgm_mul,pdist,edge,edgen,gsr,array"))
++ (eq_attr "type" "fga,visl,viscmp,vismv,fgm_pack,fgm_mul,pdist,edge,edgen,gsr,array,bmask"))
+ "niag_pipe*8")
Index: gcc/config/sparc/sparc.md
===================================================================
--- a/src/gcc/config/sparc/sparc.md (.../tags/gcc_7_1_0_release)
+++ b/src/gcc/config/sparc/sparc.md (.../branches/gcc-7-branch)
-@@ -338,7 +338,8 @@
+@@ -94,6 +94,12 @@
+ UNSPEC_ADDV
+ UNSPEC_SUBV
+ UNSPEC_NEGV
++
++ UNSPEC_DICTUNPACK
++ UNSPEC_FPCMPSHL
++ UNSPEC_FPUCMPSHL
++ UNSPEC_FPCMPDESHL
++ UNSPEC_FPCMPURSHL
+ ])
+
+ (define_c_enum "unspecv" [
+@@ -238,7 +244,8 @@
+ niagara2,
+ niagara3,
+ niagara4,
+- niagara7"
++ niagara7,
++ m8"
+ (const (symbol_ref "sparc_cpu_attr")))
+
+ ;; Attribute for the instruction set.
+@@ -251,7 +258,7 @@
+ (symbol_ref "TARGET_SPARCLET") (const_string "sparclet")]
+ (const_string "v7"))))
+
+-(define_attr "cpu_feature" "none,fpu,fpunotv9,v9,vis,vis3,vis4"
++(define_attr "cpu_feature" "none,fpu,fpunotv9,v9,vis,vis3,vis4,vis4b"
+ (const_string "none"))
+
+ (define_attr "lra" "disabled,enabled"
+@@ -265,10 +272,92 @@
+ (eq_attr "cpu_feature" "v9") (symbol_ref "TARGET_V9")
+ (eq_attr "cpu_feature" "vis") (symbol_ref "TARGET_VIS")
+ (eq_attr "cpu_feature" "vis3") (symbol_ref "TARGET_VIS3")
+- (eq_attr "cpu_feature" "vis4") (symbol_ref "TARGET_VIS4")]
++ (eq_attr "cpu_feature" "vis4") (symbol_ref "TARGET_VIS4")
++ (eq_attr "cpu_feature" "vis4b") (symbol_ref "TARGET_VIS4B")]
+ (const_int 0)))
+
+-;; Insn type.
++;; The SPARC instructions used by the backend are organized into a
++;; hierarchy using the insn attributes "type" and "subtype".
++;;
++;; The mnemonics used in the list below are the architectural names
++;; used in the Oracle SPARC Architecture specs. A / character
++;; separates the type from the subtype where appropriate. For
++;; brevity, text enclosed in {} denotes alternatives, while text
++;; enclosed in [] is optional.
++;;
++;; Please keep this list updated. It is of great help for keeping the
++;; correctness and coherence of the DFA schedulers.
++;;
++;; ialu: <empty>
++;; ialuX: ADD[X]C SUB[X]C
++;; shift: SLL[X] SRL[X] SRA[X]
++;; cmove: MOV{A,N,NE,E,G,LE,GE,L,GU,LEU,CC,CS,POS,NEG,VC,VS}
++;; MOVF{A,N,U,G,UG,L,UL,LG,NE,E,UE,GE,UGE,LE,ULE,O}
++;; MOVR{Z,LEZ,LZ,NZ,GZ,GEZ}
++;; compare: ADDcc ADDCcc ANDcc ORcc SUBcc SUBCcc XORcc XNORcc
++;; imul: MULX SMUL[cc] UMUL UMULXHI XMULX XMULXHI
++;; idiv: UDIVX SDIVX
++;; flush: FLUSH
++;; load/regular: LD{UB,UH,UW} LDFSR
++;; load/prefetch: PREFETCH
++;; fpload: LDF LDDF LDQF
++;; sload: LD{SB,SH,SW}
++;; store: ST{B,H,W,X} STFSR
++;; fpstore: STF STDF STQF
++;; cbcond: CWB{NE,E,G,LE,GE,L,GU,LEU,CC,CS,POS,NEG,VC,VS}
++;; CXB{NE,E,G,LE,GE,L,GU,LEU,CC,CS,POS,NEG,VC,VS}
++;; uncond_branch: BA BPA JMPL
++;; branch: B{NE,E,G,LE,GE,L,GU,LEU,CC,CS,POS,NEG,VC,VS}
++;; BP{NE,E,G,LE,GE,L,GU,LEU,CC,CS,POS,NEG,VC,VS}
++;; FB{U,G,UG,L,UL,LG,NE,BE,UE,GE,UGE,LE,ULE,O}
++;; call: CALL
++;; return: RESTORE RETURN
++;; fpmove: FABS{s,d,q} FMOV{s,d,q} FNEG{s,d,q}
++;; fpcmove: FMOV{S,D,Q}{icc,xcc,fcc}
++;; fpcrmove: FMOVR{s,d,q}{Z,LEZ,LZ,NZ,GZ,GEZ}
++;; fp: FADD{s,d,q} FSUB{s,d,q} FHSUB{s,d} FNHADD{s,d} FNADD{s,d}
++;; FiTO{s,d,q} FsTO{i,x,d,q} FdTO{i,x,s,q} FxTO{d,s,q} FqTO{i,x,s,d}
++;; fpcmp: FCMP{s,d,q} FCMPE{s,d,q}
++;; fpmul: FMADD{s,d} FMSUB{s,d} FMUL{s,d,q} FNMADD{s,d}
++;; FNMSUB{s,d} FNMUL{s,d} FNsMULd FsMULd
++;; FdMULq
++;; array: ARRAY{8,16,32}
++;; bmask: BMASK
++;; edge: EDGE{8,16,32}[L]cc
++;; edgen: EDGE{8,16,32}[L]n
++;; fpdivs: FDIV{s,q}
++;; fpsqrts: FSQRT{s,q}
++;; fpdivd: FDIVd
++;; fpsqrtd: FSQRTd
++;; lzd: LZCNT
++;; fga/addsub64: FP{ADD,SUB}64
++;; fga/fpu: FCHKSM16 FEXPANd FMEAN16 FPMERGE
++;; FS{LL,RA,RL}{16,32}
++;; fga/maxmin: FP{MAX,MIN}[U]{8,16,32}
++;; fga/cmask: CMASK{8,16,32}
++;; fga/other: BSHUFFLE FALIGNDATAg FP{ADD,SUB}[S]{8,16,32}
++;; FP{ADD,SUB}US{8,16} DICTUNPACK
++;; gsr/reg: RDGSR WRGSR
++;; gsr/alignaddr: ALIGNADDRESS[_LITTLE]
++;; vismv/double: FSRC2d
++;; vismv/single: MOVwTOs FSRC2s
++;; vismv/movstouw: MOVsTOuw
++;; vismv/movxtod: MOVxTOd
++;; vismv/movdtox: MOVdTOx
++;; visl/single: F{AND,NAND,NOR,OR,NOT1}s
++;; F{AND,OR}NOT{1,2}s
++;; FONEs F{ZERO,XNOR,XOR}s FNOT2s
++;; visl/double: FONEd FZEROd FNOT1d F{OR,AND,XOR}d F{NOR,NAND,XNOR}d
++;; F{OR,AND}NOT1d F{OR,AND}NOT2d
++;; viscmp: FPCMP{LE,GT,NE,EQ}{8,16,32} FPCMPU{LE,GT,NE,EQ}{8,16,32}
++;; FPCMP{LE,GT,EQ,NE}{8,16,32}SHL FPCMPU{LE,GT,EQ,NE}{8,16,32}SHL
++;; FPCMPDE{8,16,32}SHL FPCMPUR{8,16,32}SHL
++;; fgm_pack: FPACKFIX FPACK{8,16,32}
++;; fgm_mul: FMUL8SUx16 FMUL8ULx16 FMUL8x16 FMUL8x16AL
++;; FMUL8x16AU FMULD8SUx16 FMULD8ULx16
++;; pdist: PDIST
++;; pdistn: PDISTN
++
+ (define_attr "type"
+ "ialu,compare,shift,
+ load,sload,store,
+@@ -281,12 +370,20 @@
+ fpcmp,
+ fpmul,fpdivs,fpdivd,
+ fpsqrts,fpsqrtd,
+- fga,visl,vismv,fgm_pack,fgm_mul,pdist,pdistn,edge,edgen,gsr,array,
++ fga,visl,vismv,viscmp,
++ fgm_pack,fgm_mul,pdist,pdistn,edge,edgen,gsr,array,bmask,
+ cmove,
+ ialuX,
+ multi,savew,flushw,iflush,trap,lzd"
+ (const_string "ialu"))
+
++(define_attr "subtype"
++ "single,double,movstouw,movxtod,movdtox,
++ addsub64,cmask,fpu,maxmin,other,
++ reg,alignaddr,
++ prefetch,regular"
++ (const_string "single"))
++
+ ;; True if branch/call has empty delay slot and will emit a nop in it
+ (define_attr "empty_delay_slot" "false,true"
+ (symbol_ref "(empty_delay_slot (insn)
+@@ -329,6 +426,10 @@
+ (symbol_ref "(sparc_fix_ut699 != 0
+ ? FIX_UT699_TRUE : FIX_UT699_FALSE)"))
+
++(define_attr "fix_b2bst" "false,true"
++ (symbol_ref "(sparc_fix_b2bst != 0
++ ? FIX_B2BST_TRUE : FIX_B2BST_FALSE)"))
++
+ ;; Length (in # of insns).
+ ;; Beware that setting a length greater or equal to 3 for conditional branches
+ ;; has a side-effect (see output_cbranch and output_v9branch).
+@@ -338,7 +439,8 @@
(const_int 2)
(const_int 1))
(eq_attr "type" "sibcall")
@@ -60618,7 +71380,242 @@ Index: gcc/config/sparc/sparc.md
(if_then_else (eq_attr "empty_delay_slot" "true")
(const_int 3)
(const_int 2))
-@@ -7097,7 +7098,10 @@
+@@ -475,6 +577,8 @@
+ (define_attr "in_branch_delay" "false,true"
+ (cond [(eq_attr "type" "uncond_branch,branch,cbcond,uncond_cbcond,call,sibcall,call_no_delay_slot,multi")
+ (const_string "false")
++ (and (eq_attr "fix_b2bst" "true") (eq_attr "type" "store,fpstore"))
++ (const_string "false")
+ (and (eq_attr "fix_ut699" "true") (eq_attr "type" "load,sload"))
+ (const_string "false")
+ (and (eq_attr "fix_ut699" "true")
+@@ -486,9 +590,6 @@
+ (const_string "true")
+ ] (const_string "false")))
+
+-;; True if the instruction executes in the V3 pipeline, in M7 and later processors.
+-(define_attr "v3pipe" "false,true" (const_string "false"))
+-
+ (define_delay (eq_attr "type" "call")
+ [(eq_attr "in_call_delay" "true") (nil) (nil)])
+
+@@ -518,6 +619,7 @@
+ (include "niagara2.md")
+ (include "niagara4.md")
+ (include "niagara7.md")
++(include "m8.md")
+
+
+ ;; Operand and operator predicates and constraints
+@@ -1506,6 +1608,7 @@
+ ldub\t%1, %0
+ stb\t%r1, %0"
+ [(set_attr "type" "*,load,store")
++ (set_attr "subtype" "*,regular,*")
+ (set_attr "us3load_type" "*,3cycle,*")])
+
+ (define_expand "movhi"
+@@ -1528,6 +1631,7 @@
+ lduh\t%1, %0
+ sth\t%r1, %0"
+ [(set_attr "type" "*,*,load,store")
++ (set_attr "subtype" "*,*,regular,*")
+ (set_attr "us3load_type" "*,*,3cycle,*")])
+
+ ;; We always work with constants here.
+@@ -1565,8 +1669,8 @@
+ fzeros\t%0
+ fones\t%0"
+ [(set_attr "type" "*,*,load,store,vismv,vismv,fpmove,fpload,fpstore,visl,visl")
+- (set_attr "cpu_feature" "*,*,*,*,vis3,vis3,*,*,*,vis,vis")
+- (set_attr "v3pipe" "*,*,*,*,true,true,*,*,*,true,true")])
++ (set_attr "subtype" "*,*,regular,*,movstouw,single,*,*,*,single,single")
++ (set_attr "cpu_feature" "*,*,*,*,vis3,vis3,*,*,*,vis,vis")])
+
+ (define_insn "*movsi_lo_sum"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+@@ -1623,7 +1727,8 @@
+ return "ld\t[%1 + %2], %0";
+ #endif
+ }
+- [(set_attr "type" "load")])
++ [(set_attr "type" "load")
++ (set_attr "subtype" "regular")])
+
+ (define_expand "movsi_pic_label_ref"
+ [(set (match_dup 3) (high:SI
+@@ -1732,11 +1837,12 @@
+ std\t%1, %0
+ fzero\t%0
+ fone\t%0"
+- [(set_attr "type" "store,*,load,store,load,store,*,*,fpload,fpstore,*,*,fpmove,*,*,*,fpload,fpstore,visl,visl")
++ [(set_attr "type" "store,*,load,store,load,store,*,*,fpload,fpstore,*,*,fpmove,*,*,*,fpload,fpstore,visl,
++visl")
++ (set_attr "subtype" "*,*,regular,*,regular,*,*,*,*,*,*,*,*,*,*,*,*,*,double,double")
+ (set_attr "length" "*,2,*,*,*,*,2,2,*,*,2,2,*,2,2,2,*,*,*,*")
+ (set_attr "fptype" "*,*,*,*,*,*,*,*,*,*,*,*,double,*,*,*,*,*,double,double")
+ (set_attr "cpu_feature" "v9,*,*,*,*,*,*,*,fpu,fpu,fpu,fpu,v9,fpunotv9,vis3,vis3,fpu,fpu,vis,vis")
+- (set_attr "v3pipe" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,true,true")
+ (set_attr "lra" "*,*,disabled,disabled,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*")])
+
+ (define_insn "*movdi_insn_sp64"
+@@ -1758,9 +1864,9 @@
+ fzero\t%0
+ fone\t%0"
+ [(set_attr "type" "*,*,load,store,vismv,vismv,fpmove,fpload,fpstore,visl,visl")
++ (set_attr "subtype" "*,*,regular,*,movdtox,movxtod,*,*,*,double,double")
+ (set_attr "fptype" "*,*,*,*,*,*,double,*,*,double,double")
+- (set_attr "cpu_feature" "*,*,*,*,vis3,vis3,*,*,*,vis,vis")
+- (set_attr "v3pipe" "*,*,*,*,*,*,*,*,*,true,true")])
++ (set_attr "cpu_feature" "*,*,*,*,vis3,vis3,*,*,*,vis,vis")])
+
+ (define_expand "movdi_pic_label_ref"
+ [(set (match_dup 3) (high:DI
+@@ -1846,7 +1952,8 @@
+ return "ldx\t[%1 + %2], %0";
+ #endif
+ }
+- [(set_attr "type" "load")])
++ [(set_attr "type" "load")
++ (set_attr "subtype" "regular")])
+
+ (define_insn "*sethi_di_medlow_embmedany_pic"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+@@ -2288,8 +2395,8 @@
+ }
+ }
+ [(set_attr "type" "visl,visl,fpmove,*,*,*,vismv,vismv,fpload,load,fpstore,store")
+- (set_attr "cpu_feature" "vis,vis,fpu,*,*,*,vis3,vis3,fpu,*,fpu,*")
+- (set_attr "v3pipe" "true,true,*,*,*,*,true,true,*,*,*,*")])
++ (set_attr "subtype" "single,single,*,*,*,*,movstouw,single,*,regular,*,*")
++ (set_attr "cpu_feature" "vis,vis,fpu,*,*,*,vis3,vis3,fpu,*,fpu,*")])
+
+ ;; The following 3 patterns build SFmode constants in integer registers.
+
+@@ -2361,10 +2468,10 @@
+ ldd\t%1, %0
+ std\t%1, %0"
+ [(set_attr "type" "store,*,visl,visl,fpmove,*,*,*,fpload,fpstore,load,store,*,*,*,load,store")
++ (set_attr "subtype" "*,*,double,double,*,*,*,*,*,*,regular,*,*,*,*,regular,*")
+ (set_attr "length" "*,2,*,*,*,2,2,2,*,*,*,*,2,2,2,*,*")
+ (set_attr "fptype" "*,*,double,double,double,*,*,*,*,*,*,*,*,*,*,*,*")
+ (set_attr "cpu_feature" "v9,*,vis,vis,v9,fpunotv9,vis3,vis3,fpu,fpu,*,*,fpu,fpu,*,*,*")
+- (set_attr "v3pipe" "*,*,true,true,*,*,*,*,*,*,*,*,*,*,*,*,*")
+ (set_attr "lra" "*,*,*,*,*,*,*,*,*,*,disabled,disabled,*,*,*,*,*")])
+
+ (define_insn "*movdf_insn_sp64"
+@@ -2386,10 +2493,10 @@
+ stx\t%r1, %0
+ #"
+ [(set_attr "type" "visl,visl,fpmove,vismv,vismv,load,store,*,load,store,*")
++ (set_attr "subtype" "double,double,*,movdtox,movxtod,regular,*,*,regular,*,*")
+ (set_attr "length" "*,*,*,*,*,*,*,*,*,*,2")
+ (set_attr "fptype" "double,double,double,double,double,*,*,*,*,*,*")
+- (set_attr "cpu_feature" "vis,vis,fpu,vis3,vis3,fpu,fpu,*,*,*,*")
+- (set_attr "v3pipe" "true,true,*,*,*,*,*,*,*,*,*")])
++ (set_attr "cpu_feature" "vis,vis,fpu,vis3,vis3,fpu,fpu,*,*,*,*")])
+
+ ;; This pattern builds DFmode constants in integer registers.
+ (define_split
+@@ -2915,6 +3022,7 @@
+ ""
+ "lduh\t%1, %0"
+ [(set_attr "type" "load")
++ (set_attr "subtype" "regular")
+ (set_attr "us3load_type" "3cycle")])
+
+ (define_expand "zero_extendqihi2"
+@@ -2931,6 +3039,7 @@
+ and\t%1, 0xff, %0
+ ldub\t%1, %0"
+ [(set_attr "type" "*,load")
++ (set_attr "subtype" "*,regular")
+ (set_attr "us3load_type" "*,3cycle")])
+
+ (define_expand "zero_extendqisi2"
+@@ -2947,6 +3056,7 @@
+ and\t%1, 0xff, %0
+ ldub\t%1, %0"
+ [(set_attr "type" "*,load")
++ (set_attr "subtype" "*,regular")
+ (set_attr "us3load_type" "*,3cycle")])
+
+ (define_expand "zero_extendqidi2"
+@@ -2963,6 +3073,7 @@
+ and\t%1, 0xff, %0
+ ldub\t%1, %0"
+ [(set_attr "type" "*,load")
++ (set_attr "subtype" "*,regular")
+ (set_attr "us3load_type" "*,3cycle")])
+
+ (define_expand "zero_extendhidi2"
+@@ -2994,6 +3105,7 @@
+ "TARGET_ARCH64"
+ "lduh\t%1, %0"
+ [(set_attr "type" "load")
++ (set_attr "subtype" "regular")
+ (set_attr "us3load_type" "3cycle")])
+
+ ;; ??? Write truncdisi pattern using sra?
+@@ -3014,9 +3126,10 @@
+ lduw\t%1, %0
+ movstouw\t%1, %0"
+ [(set_attr "type" "shift,load,*")
+- (set_attr "cpu_feature" "*,*,vis3")
+- (set_attr "v3pipe" "*,*,true")])
++ (set_attr "subtype" "*,regular,movstouw")
++ (set_attr "cpu_feature" "*,*,vis3")])
+
++
+ (define_insn_and_split "*zero_extendsidi2_insn_sp32"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
+@@ -3330,8 +3443,7 @@
+ movstosw\t%1, %0"
+ [(set_attr "type" "shift,sload,*")
+ (set_attr "us3load_type" "*,3cycle,*")
+- (set_attr "cpu_feature" "*,*,vis3")
+- (set_attr "v3pipe" "*,*,true")])
++ (set_attr "cpu_feature" "*,*,vis3")])
+
+
+ ;; Special pattern for optimizing bit-field compares. This is needed
+@@ -6010,7 +6122,7 @@
+ [(set (match_operand:DF 0 "register_operand" "=e")
+ (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "f"))
+ (float_extend:DF (match_operand:SF 2 "register_operand" "f"))))]
+- "(TARGET_V8 || TARGET_V9) && TARGET_FPU && !sparc_fix_ut699"
++ "TARGET_FSMULD"
+ "fsmuld\t%1, %2, %0"
+ [(set_attr "type" "fpmul")
+ (set_attr "fptype" "double")])
+@@ -6060,10 +6172,10 @@
+ (div:DF (match_operand:DF 1 "register_operand" "e")
+ (match_operand:DF 2 "register_operand" "e")))]
+ "TARGET_FPU && sparc_fix_ut699"
+- "fdivd\t%1, %2, %0\n\tstd\t%0, [%%sp-8]"
++ "fdivd\t%1, %2, %0\n\tstd\t%0, [%%sp-8]\n\tnop"
+ [(set_attr "type" "fpdivd")
+ (set_attr "fptype" "double")
+- (set_attr "length" "2")])
++ (set_attr "length" "3")])
+
+ (define_insn "divsf3"
+ [(set (match_operand:SF 0 "register_operand" "=f")
+@@ -6312,10 +6424,10 @@
+ [(set (match_operand:DF 0 "register_operand" "=e")
+ (sqrt:DF (match_operand:DF 1 "register_operand" "e")))]
+ "TARGET_FPU && sparc_fix_ut699"
+- "fsqrtd\t%1, %0\n\tstd\t%0, [%%sp-8]"
++ "fsqrtd\t%1, %0\n\tstd\t%0, [%%sp-8]\n\tnop"
+ [(set_attr "type" "fpsqrtd")
+ (set_attr "fptype" "double")
+- (set_attr "length" "2")])
++ (set_attr "length" "3")])
+
+ (define_insn "sqrtsf2"
+ [(set (match_operand:SF 0 "register_operand" "=f")
+@@ -7097,7 +7209,10 @@
(define_expand "return"
[(return)]
"sparc_can_use_return_insn_p ()"
@@ -60630,11 +71627,1029 @@ Index: gcc/config/sparc/sparc.md
(define_insn "*return_internal"
[(return)]
+@@ -7352,7 +7467,8 @@
+ [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] UNSPECV_LDFSR)]
+ "TARGET_FPU"
+ "ld\t%0, %%fsr"
+- [(set_attr "type" "load")])
++ [(set_attr "type" "load")
++ (set_attr "subtype" "regular")])
+
+ (define_insn "stfsr"
+ [(set (match_operand:SI 0 "memory_operand" "=m")
+@@ -7716,7 +7832,8 @@
+ gcc_assert (locality >= 0 && locality < 4);
+ return prefetch_instr [read_or_write][locality == 0 ? 0 : 1];
+ }
+- [(set_attr "type" "load")])
++ [(set_attr "type" "load")
++ (set_attr "subtype" "prefetch")])
+
+ (define_insn "prefetch_32"
+ [(prefetch (match_operand:SI 0 "address_operand" "p")
+@@ -7741,7 +7858,8 @@
+ gcc_assert (locality >= 0 && locality < 4);
+ return prefetch_instr [read_or_write][locality == 0 ? 0 : 1];
+ }
+- [(set_attr "type" "load")])
++ [(set_attr "type" "load")
++ (set_attr "subtype" "prefetch")])
+
+
+ ;; Trap instructions.
+@@ -7962,7 +8080,8 @@
+ UNSPEC_TLSIE))]
+ "TARGET_TLS && TARGET_ARCH32"
+ "ld\\t[%1 + %2], %0, %%tie_ld(%a3)"
+- [(set_attr "type" "load")])
++ [(set_attr "type" "load")
++ (set_attr "subtype" "regular")])
+
+ (define_insn "tie_ld64"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+@@ -7972,7 +8091,8 @@
+ UNSPEC_TLSIE))]
+ "TARGET_TLS && TARGET_ARCH64"
+ "ldx\\t[%1 + %2], %0, %%tie_ldx(%a3)"
+- [(set_attr "type" "load")])
++ [(set_attr "type" "load")
++ (set_attr "subtype" "regular")])
+
+ (define_insn "tie_add32"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+@@ -8032,6 +8152,7 @@
+ "TARGET_TLS && TARGET_ARCH32"
+ "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
+ [(set_attr "type" "load")
++ (set_attr "subtype" "regular")
+ (set_attr "us3load_type" "3cycle")])
+
+ (define_insn "*tldo_ldub1_sp32"
+@@ -8044,6 +8165,7 @@
+ "TARGET_TLS && TARGET_ARCH32"
+ "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
+ [(set_attr "type" "load")
++ (set_attr "subtype" "regular")
+ (set_attr "us3load_type" "3cycle")])
+
+ (define_insn "*tldo_ldub2_sp32"
+@@ -8056,6 +8178,7 @@
+ "TARGET_TLS && TARGET_ARCH32"
+ "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
+ [(set_attr "type" "load")
++ (set_attr "subtype" "regular")
+ (set_attr "us3load_type" "3cycle")])
+
+ (define_insn "*tldo_ldsb1_sp32"
+@@ -8091,6 +8214,7 @@
+ "TARGET_TLS && TARGET_ARCH64"
+ "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
+ [(set_attr "type" "load")
++ (set_attr "subtype" "regular")
+ (set_attr "us3load_type" "3cycle")])
+
+ (define_insn "*tldo_ldub1_sp64"
+@@ -8103,6 +8227,7 @@
+ "TARGET_TLS && TARGET_ARCH64"
+ "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
+ [(set_attr "type" "load")
++ (set_attr "subtype" "regular")
+ (set_attr "us3load_type" "3cycle")])
+
+ (define_insn "*tldo_ldub2_sp64"
+@@ -8115,6 +8240,7 @@
+ "TARGET_TLS && TARGET_ARCH64"
+ "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
+ [(set_attr "type" "load")
++ (set_attr "subtype" "regular")
+ (set_attr "us3load_type" "3cycle")])
+
+ (define_insn "*tldo_ldub3_sp64"
+@@ -8127,6 +8253,7 @@
+ "TARGET_TLS && TARGET_ARCH64"
+ "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
+ [(set_attr "type" "load")
++ (set_attr "subtype" "regular")
+ (set_attr "us3load_type" "3cycle")])
+
+ (define_insn "*tldo_ldsb1_sp64"
+@@ -8174,6 +8301,7 @@
+ "TARGET_TLS && TARGET_ARCH32"
+ "lduh\t[%1 + %2], %0, %%tldo_add(%3)"
+ [(set_attr "type" "load")
++ (set_attr "subtype" "regular")
+ (set_attr "us3load_type" "3cycle")])
+
+ (define_insn "*tldo_lduh1_sp32"
+@@ -8186,6 +8314,7 @@
+ "TARGET_TLS && TARGET_ARCH32"
+ "lduh\t[%1 + %2], %0, %%tldo_add(%3)"
+ [(set_attr "type" "load")
++ (set_attr "subtype" "regular")
+ (set_attr "us3load_type" "3cycle")])
+
+ (define_insn "*tldo_ldsh1_sp32"
+@@ -8209,6 +8338,7 @@
+ "TARGET_TLS && TARGET_ARCH64"
+ "lduh\t[%1 + %2], %0, %%tldo_add(%3)"
+ [(set_attr "type" "load")
++ (set_attr "subtype" "regular")
+ (set_attr "us3load_type" "3cycle")])
+
+ (define_insn "*tldo_lduh1_sp64"
+@@ -8221,6 +8351,7 @@
+ "TARGET_TLS && TARGET_ARCH64"
+ "lduh\t[%1 + %2], %0, %%tldo_add(%3)"
+ [(set_attr "type" "load")
++ (set_attr "subtype" "regular")
+ (set_attr "us3load_type" "3cycle")])
+
+ (define_insn "*tldo_lduh2_sp64"
+@@ -8233,6 +8364,7 @@
+ "TARGET_TLS && TARGET_ARCH64"
+ "lduh\t[%1 + %2], %0, %%tldo_add(%3)"
+ [(set_attr "type" "load")
++ (set_attr "subtype" "regular")
+ (set_attr "us3load_type" "3cycle")])
+
+ (define_insn "*tldo_ldsh1_sp64"
+@@ -8267,7 +8399,8 @@
+ (match_operand:SI 1 "register_operand" "r"))))]
+ "TARGET_TLS && TARGET_ARCH32"
+ "ld\t[%1 + %2], %0, %%tldo_add(%3)"
+- [(set_attr "type" "load")])
++ [(set_attr "type" "load")
++ (set_attr "subtype" "regular")])
+
+ (define_insn "*tldo_lduw_sp64"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+@@ -8277,7 +8410,8 @@
+ (match_operand:DI 1 "register_operand" "r"))))]
+ "TARGET_TLS && TARGET_ARCH64"
+ "lduw\t[%1 + %2], %0, %%tldo_add(%3)"
+- [(set_attr "type" "load")])
++ [(set_attr "type" "load")
++ (set_attr "subtype" "regular")])
+
+ (define_insn "*tldo_lduw1_sp64"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+@@ -8288,7 +8422,8 @@
+ (match_operand:DI 1 "register_operand" "r")))))]
+ "TARGET_TLS && TARGET_ARCH64"
+ "lduw\t[%1 + %2], %0, %%tldo_add(%3)"
+- [(set_attr "type" "load")])
++ [(set_attr "type" "load")
++ (set_attr "subtype" "regular")])
+
+ (define_insn "*tldo_ldsw1_sp64"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+@@ -8310,7 +8445,8 @@
+ (match_operand:DI 1 "register_operand" "r"))))]
+ "TARGET_TLS && TARGET_ARCH64"
+ "ldx\t[%1 + %2], %0, %%tldo_add(%3)"
+- [(set_attr "type" "load")])
++ [(set_attr "type" "load")
++ (set_attr "subtype" "regular")])
+
+ (define_insn "*tldo_stb_sp32"
+ [(set (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
+@@ -8515,8 +8651,8 @@
+ movstouw\t%1, %0
+ movwtos\t%1, %0"
+ [(set_attr "type" "visl,visl,vismv,fpload,fpstore,store,load,store,*,vismv,vismv")
+- (set_attr "cpu_feature" "vis,vis,vis,*,*,*,*,*,*,vis3,vis3")
+- (set_attr "v3pipe" "true,true,true,*,*,*,*,*,*,true,true")])
++ (set_attr "subtype" "single,single,single,*,*,*,regular,*,*,movstouw,single")
++ (set_attr "cpu_feature" "vis,vis,vis,*,*,*,*,*,*,vis3,vis3")])
+
+ (define_insn "*mov<VM64:mode>_insn_sp64"
+ [(set (match_operand:VM64 0 "nonimmediate_operand" "=e,e,e,e,W,m,*r, m,*r, e,*r")
+@@ -8538,8 +8674,8 @@
+ movxtod\t%1, %0
+ mov\t%1, %0"
+ [(set_attr "type" "visl,visl,vismv,fpload,fpstore,store,load,store,vismv,vismv,*")
+- (set_attr "cpu_feature" "vis,vis,vis,*,*,*,*,*,vis3,vis3,*")
+- (set_attr "v3pipe" "true,true,true,*,*,*,*,*,*,*,*")])
++ (set_attr "subtype" "double,double,double,*,*,*,regular,*,movdtox,movxtod,*")
++ (set_attr "cpu_feature" "vis,vis,vis,*,*,*,*,*,vis3,vis3,*")])
+
+ (define_insn "*mov<VM64:mode>_insn_sp32"
+ [(set (match_operand:VM64 0 "nonimmediate_operand"
+@@ -8568,9 +8704,9 @@
+ ldd\t%1, %0
+ std\t%1, %0"
+ [(set_attr "type" "store,*,visl,visl,vismv,*,*,fpload,fpstore,load,store,*,*,*,load,store")
++ (set_attr "subtype" "*,*,double,double,double,*,*,*,*,regular,*,*,*,*,regular,*")
+ (set_attr "length" "*,2,*,*,*,2,2,*,*,*,*,2,2,2,*,*")
+ (set_attr "cpu_feature" "*,*,vis,vis,vis,vis3,vis3,*,*,*,*,*,*,*,*,*")
+- (set_attr "v3pipe" "*,*,true,true,true,*,*,*,*,*,*,*,*,*,*,*")
+ (set_attr "lra" "*,*,*,*,*,*,*,*,*,disabled,disabled,*,*,*,*,*")])
+
+ (define_split
+@@ -8648,8 +8784,8 @@
+ "TARGET_VIS"
+ "fp<plusminus_insn><vbits>\t%1, %2, %0"
+ [(set_attr "type" "fga")
+- (set_attr "fptype" "<vfptype>")
+- (set_attr "v3pipe" "true")])
++ (set_attr "subtype" "other")
++ (set_attr "fptype" "<vfptype>")])
+
+ (define_mode_iterator VL [V1SI V2HI V4QI V1DI V2SI V4HI V8QI])
+ (define_mode_attr vlsuf [(V1SI "s") (V2HI "s") (V4QI "s")
+@@ -8665,8 +8801,7 @@
+ "TARGET_VIS"
+ "f<vlinsn><vlsuf>\t%1, %2, %0"
+ [(set_attr "type" "visl")
+- (set_attr "fptype" "<vfptype>")
+- (set_attr "v3pipe" "true")])
++ (set_attr "fptype" "<vfptype>")])
+
+ (define_insn "*not_<vlop:code><VL:mode>3"
+ [(set (match_operand:VL 0 "register_operand" "=<vconstr>")
+@@ -8675,8 +8810,7 @@
+ "TARGET_VIS"
+ "f<vlninsn><vlsuf>\t%1, %2, %0"
+ [(set_attr "type" "visl")
+- (set_attr "fptype" "<vfptype>")
+- (set_attr "v3pipe" "true")])
++ (set_attr "fptype" "<vfptype>")])
+
+ ;; (ior (not (op1)) (not (op2))) is the canonical form of NAND.
+ (define_insn "*nand<VL:mode>_vis"
+@@ -8686,8 +8820,7 @@
+ "TARGET_VIS"
+ "fnand<vlsuf>\t%1, %2, %0"
+ [(set_attr "type" "visl")
+- (set_attr "fptype" "<vfptype>")
+- (set_attr "v3pipe" "true")])
++ (set_attr "fptype" "<vfptype>")])
+
+ (define_code_iterator vlnotop [ior and])
+
+@@ -8698,8 +8831,7 @@
+ "TARGET_VIS"
+ "f<vlinsn>not1<vlsuf>\t%1, %2, %0"
+ [(set_attr "type" "visl")
+- (set_attr "fptype" "<vfptype>")
+- (set_attr "v3pipe" "true")])
++ (set_attr "fptype" "<vfptype>")])
+
+ (define_insn "*<vlnotop:code>_not2<VL:mode>_vis"
+ [(set (match_operand:VL 0 "register_operand" "=<vconstr>")
+@@ -8708,8 +8840,7 @@
+ "TARGET_VIS"
+ "f<vlinsn>not2<vlsuf>\t%1, %2, %0"
+ [(set_attr "type" "visl")
+- (set_attr "fptype" "<vfptype>")
+- (set_attr "v3pipe" "true")])
++ (set_attr "fptype" "<vfptype>")])
+
+ (define_insn "one_cmpl<VL:mode>2"
+ [(set (match_operand:VL 0 "register_operand" "=<vconstr>")
+@@ -8717,8 +8848,7 @@
+ "TARGET_VIS"
+ "fnot1<vlsuf>\t%1, %0"
+ [(set_attr "type" "visl")
+- (set_attr "fptype" "<vfptype>")
+- (set_attr "v3pipe" "true")])
++ (set_attr "fptype" "<vfptype>")])
+
+ ;; Hard to generate VIS instructions. We have builtins for these.
+
+@@ -8760,6 +8890,7 @@
+ "TARGET_VIS"
+ "fexpand\t%1, %0"
+ [(set_attr "type" "fga")
++ (set_attr "subtype" "fpu")
+ (set_attr "fptype" "double")])
+
+ (define_insn "fpmerge_vis"
+@@ -8774,6 +8905,7 @@
+ "TARGET_VIS"
+ "fpmerge\t%1, %2, %0"
+ [(set_attr "type" "fga")
++ (set_attr "subtype" "fpu")
+ (set_attr "fptype" "double")])
+
+ ;; Partitioned multiply instructions
+@@ -8862,7 +8994,8 @@
+ [(set (reg:DI GSR_REG) (match_operand:DI 0 "arith_operand" "rI"))]
+ "TARGET_VIS && TARGET_ARCH64"
+ "wr\t%%g0, %0, %%gsr"
+- [(set_attr "type" "gsr")])
++ [(set_attr "type" "gsr")
++ (set_attr "subtype" "reg")])
+
+ (define_insn "wrgsr_v8plus"
+ [(set (reg:DI GSR_REG) (match_operand:DI 0 "arith_operand" "I,r"))
+@@ -8893,7 +9026,8 @@
+ [(set (match_operand:DI 0 "register_operand" "=r") (reg:DI GSR_REG))]
+ "TARGET_VIS && TARGET_ARCH64"
+ "rd\t%%gsr, %0"
+- [(set_attr "type" "gsr")])
++ [(set_attr "type" "gsr")
++ (set_attr "subtype" "reg")])
+
+ (define_insn "rdgsr_v8plus"
+ [(set (match_operand:DI 0 "register_operand" "=r") (reg:DI GSR_REG))
+@@ -8916,8 +9050,8 @@
+ "TARGET_VIS"
+ "faligndata\t%1, %2, %0"
+ [(set_attr "type" "fga")
+- (set_attr "fptype" "double")
+- (set_attr "v3pipe" "true")])
++ (set_attr "subtype" "other")
++ (set_attr "fptype" "double")])
+
+ (define_insn "alignaddrsi_vis"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+@@ -8928,7 +9062,7 @@
+ "TARGET_VIS"
+ "alignaddr\t%r1, %r2, %0"
+ [(set_attr "type" "gsr")
+- (set_attr "v3pipe" "true")])
++ (set_attr "subtype" "alignaddr")])
+
+ (define_insn "alignaddrdi_vis"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+@@ -8939,7 +9073,7 @@
+ "TARGET_VIS"
+ "alignaddr\t%r1, %r2, %0"
+ [(set_attr "type" "gsr")
+- (set_attr "v3pipe" "true")])
++ (set_attr "subtype" "alignaddr")])
+
+ (define_insn "alignaddrlsi_vis"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+@@ -8951,7 +9085,7 @@
+ "TARGET_VIS"
+ "alignaddrl\t%r1, %r2, %0"
+ [(set_attr "type" "gsr")
+- (set_attr "v3pipe" "true")])
++ (set_attr "subtype" "alignaddr")])
+
+ (define_insn "alignaddrldi_vis"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+@@ -8963,7 +9097,7 @@
+ "TARGET_VIS"
+ "alignaddrl\t%r1, %r2, %0"
+ [(set_attr "type" "gsr")
+- (set_attr "v3pipe" "true")])
++ (set_attr "subtype" "alignaddr")])
+
+ (define_insn "pdist_vis"
+ [(set (match_operand:DI 0 "register_operand" "=e")
+@@ -9055,9 +9189,7 @@
+ UNSPEC_FCMP))]
+ "TARGET_VIS"
+ "fcmp<gcond:code><GCM:gcm_name>\t%1, %2, %0"
+- [(set_attr "type" "visl")
+- (set_attr "fptype" "double")
+- (set_attr "v3pipe" "true")])
++ [(set_attr "type" "viscmp")])
+
+ (define_insn "fpcmp<gcond:code>8<P:mode>_vis"
+ [(set (match_operand:P 0 "register_operand" "=r")
+@@ -9066,8 +9198,7 @@
+ UNSPEC_FCMP))]
+ "TARGET_VIS4"
+ "fpcmp<gcond:code>8\t%1, %2, %0"
+- [(set_attr "type" "visl")
+- (set_attr "fptype" "double")])
++ [(set_attr "type" "viscmp")])
+
+ (define_expand "vcond<GCM:mode><GCM:mode>"
+ [(match_operand:GCM 0 "register_operand" "")
+@@ -9130,8 +9261,7 @@
+ (plus:DI (match_dup 1) (match_dup 2)))]
+ "TARGET_VIS2 && TARGET_ARCH64"
+ "bmask\t%r1, %r2, %0"
+- [(set_attr "type" "array")
+- (set_attr "v3pipe" "true")])
++ [(set_attr "type" "bmask")])
+
+ (define_insn "bmasksi_vis"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+@@ -9141,8 +9271,7 @@
+ (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
+ "TARGET_VIS2"
+ "bmask\t%r1, %r2, %0"
+- [(set_attr "type" "array")
+- (set_attr "v3pipe" "true")])
++ [(set_attr "type" "bmask")])
+
+ (define_insn "bshuffle<VM64:mode>_vis"
+ [(set (match_operand:VM64 0 "register_operand" "=e")
+@@ -9153,8 +9282,8 @@
+ "TARGET_VIS2"
+ "bshuffle\t%1, %2, %0"
+ [(set_attr "type" "fga")
+- (set_attr "fptype" "double")
+- (set_attr "v3pipe" "true")])
++ (set_attr "subtype" "other")
++ (set_attr "fptype" "double")])
+
+ ;; The rtl expanders will happily convert constant permutations on other
+ ;; modes down to V8QI. Rely on this to avoid the complexity of the byte
+@@ -9257,7 +9386,7 @@
+ "TARGET_VIS3"
+ "cmask8\t%r0"
+ [(set_attr "type" "fga")
+- (set_attr "v3pipe" "true")])
++ (set_attr "subtype" "cmask")])
+
+ (define_insn "cmask16<P:mode>_vis"
+ [(set (reg:DI GSR_REG)
+@@ -9267,7 +9396,7 @@
+ "TARGET_VIS3"
+ "cmask16\t%r0"
+ [(set_attr "type" "fga")
+- (set_attr "v3pipe" "true")])
++ (set_attr "subtype" "cmask")])
+
+ (define_insn "cmask32<P:mode>_vis"
+ [(set (reg:DI GSR_REG)
+@@ -9277,7 +9406,7 @@
+ "TARGET_VIS3"
+ "cmask32\t%r0"
+ [(set_attr "type" "fga")
+- (set_attr "v3pipe" "true")])
++ (set_attr "subtype" "cmask")])
+
+ (define_insn "fchksm16_vis"
+ [(set (match_operand:V4HI 0 "register_operand" "=e")
+@@ -9286,7 +9415,8 @@
+ UNSPEC_FCHKSM16))]
+ "TARGET_VIS3"
+ "fchksm16\t%1, %2, %0"
+- [(set_attr "type" "fga")])
++ [(set_attr "type" "fga")
++ (set_attr "subtype" "fpu")])
+
+ (define_code_iterator vis3_shift [ashift ss_ashift lshiftrt ashiftrt])
+ (define_code_attr vis3_shift_insn
+@@ -9300,7 +9430,8 @@
+ (match_operand:GCM 2 "register_operand" "<vconstr>")))]
+ "TARGET_VIS3"
+ "<vis3_shift_insn><vbits>\t%1, %2, %0"
+- [(set_attr "type" "fga")])
++ [(set_attr "type" "fga")
++ (set_attr "subtype" "fpu")])
+
+ (define_insn "pdistn<P:mode>_vis"
+ [(set (match_operand:P 0 "register_operand" "=r")
+@@ -9310,8 +9441,7 @@
+ "TARGET_VIS3"
+ "pdistn\t%1, %2, %0"
+ [(set_attr "type" "pdistn")
+- (set_attr "fptype" "double")
+- (set_attr "v3pipe" "true")])
++ (set_attr "fptype" "double")])
+
+ (define_insn "fmean16_vis"
+ [(set (match_operand:V4HI 0 "register_operand" "=e")
+@@ -9328,7 +9458,8 @@
+ (const_int 1))))]
+ "TARGET_VIS3"
+ "fmean16\t%1, %2, %0"
+- [(set_attr "type" "fga")])
++ [(set_attr "type" "fga")
++ (set_attr "subtype" "fpu")])
+
+ (define_insn "fp<plusminus_insn>64_vis"
+ [(set (match_operand:V1DI 0 "register_operand" "=e")
+@@ -9336,7 +9467,8 @@
+ (match_operand:V1DI 2 "register_operand" "e")))]
+ "TARGET_VIS3"
+ "fp<plusminus_insn>64\t%1, %2, %0"
+- [(set_attr "type" "fga")])
++ [(set_attr "type" "fga")
++ (set_attr "subtype" "addsub64")])
+
+ (define_insn "<plusminus_insn>v8qi3"
+ [(set (match_operand:V8QI 0 "register_operand" "=e")
+@@ -9344,7 +9476,8 @@
+ (match_operand:V8QI 2 "register_operand" "e")))]
+ "TARGET_VIS4"
+ "fp<plusminus_insn>8\t%1, %2, %0"
+- [(set_attr "type" "fga")])
++ [(set_attr "type" "fga")
++ (set_attr "subtype" "other")])
+
+ (define_mode_iterator VASS [V4HI V2SI V2HI V1SI])
+ (define_code_iterator vis3_addsub_ss [ss_plus ss_minus])
+@@ -9360,7 +9493,7 @@
+ "TARGET_VIS3"
+ "<vis3_addsub_ss_insn><vbits>\t%1, %2, %0"
+ [(set_attr "type" "fga")
+- (set_attr "v3pipe" "true")])
++ (set_attr "subtype" "other")])
+
+ (define_mode_iterator VMMAX [V8QI V4HI V2SI])
+ (define_code_iterator vis4_minmax [smin smax])
+@@ -9375,7 +9508,8 @@
+ (match_operand:VMMAX 2 "register_operand" "<vconstr>")))]
+ "TARGET_VIS4"
+ "<vis4_minmax_insn><vbits>\t%1, %2, %0"
+- [(set_attr "type" "fga")])
++ [(set_attr "type" "fga")
++ (set_attr "subtype" "maxmin")])
+
+ (define_code_iterator vis4_uminmax [umin umax])
+ (define_code_attr vis4_uminmax_insn
+@@ -9389,7 +9523,8 @@
+ (match_operand:VMMAX 2 "register_operand" "<vconstr>")))]
+ "TARGET_VIS4"
+ "<vis4_uminmax_insn><vbits>\t%1, %2, %0"
+- [(set_attr "type" "fga")])
++ [(set_attr "type" "fga")
++ (set_attr "subtype" "maxmin")])
+
+ ;; The use of vis3_addsub_ss_patname in the VIS4 instruction below is
+ ;; intended.
+@@ -9399,7 +9534,8 @@
+ (match_operand:V8QI 2 "register_operand" "e")))]
+ "TARGET_VIS4"
+ "<vis3_addsub_ss_insn>8\t%1, %2, %0"
+- [(set_attr "type" "fga")])
++ [(set_attr "type" "fga")
++ (set_attr "subtype" "other")])
+
+ (define_mode_iterator VAUS [V4HI V8QI])
+ (define_code_iterator vis4_addsub_us [us_plus us_minus])
+@@ -9414,7 +9550,8 @@
+ (match_operand:VAUS 2 "register_operand" "<vconstr>")))]
+ "TARGET_VIS4"
+ "<vis4_addsub_us_insn><vbits>\t%1, %2, %0"
+- [(set_attr "type" "fga")])
++ [(set_attr "type" "fga")
++ (set_attr "subtype" "other")])
+
+ (define_insn "fucmp<gcond:code>8<P:mode>_vis"
+ [(set (match_operand:P 0 "register_operand" "=r")
+@@ -9423,8 +9560,7 @@
+ UNSPEC_FUCMP))]
+ "TARGET_VIS3"
+ "fucmp<gcond:code>8\t%1, %2, %0"
+- [(set_attr "type" "visl")
+- (set_attr "v3pipe" "true")])
++ [(set_attr "type" "viscmp")])
+
+ (define_insn "fpcmpu<gcond:code><GCM:gcm_name><P:mode>_vis"
+ [(set (match_operand:P 0 "register_operand" "=r")
+@@ -9433,8 +9569,7 @@
+ UNSPEC_FUCMP))]
+ "TARGET_VIS4"
+ "fpcmpu<gcond:code><GCM:gcm_name>\t%1, %2, %0"
+- [(set_attr "type" "visl")
+- (set_attr "fptype" "double")])
++ [(set_attr "type" "viscmp")])
+
+ (define_insn "*naddsf3"
+ [(set (match_operand:SF 0 "register_operand" "=f")
+@@ -9538,4 +9673,62 @@
+ [(set_attr "type" "fp")
+ (set_attr "fptype" "double")])
+
++;; VIS4B instructions.
++
++(define_mode_iterator DUMODE [V2SI V4HI V8QI])
++
++(define_insn "dictunpack<DUMODE:vbits>"
++ [(set (match_operand:DUMODE 0 "register_operand" "=e")
++ (unspec:DUMODE [(match_operand:DF 1 "register_operand" "e")
++ (match_operand:SI 2 "imm5_operand_dictunpack<DUMODE:vbits>" "t")]
++ UNSPEC_DICTUNPACK))]
++ "TARGET_VIS4B"
++ "dictunpack\t%1, %2, %0"
++ [(set_attr "type" "fga")
++ (set_attr "subtype" "other")])
++
++(define_mode_iterator FPCSMODE [V2SI V4HI V8QI])
++(define_code_iterator fpcscond [le gt eq ne])
++(define_code_iterator fpcsucond [le gt])
++
++(define_insn "fpcmp<fpcscond:code><FPCSMODE:vbits><P:mode>shl"
++ [(set (match_operand:P 0 "register_operand" "=r")
++ (unspec:P [(fpcscond:FPCSMODE (match_operand:FPCSMODE 1 "register_operand" "e")
++ (match_operand:FPCSMODE 2 "register_operand" "e"))
++ (match_operand:SI 3 "imm2_operand" "q")]
++ UNSPEC_FPCMPSHL))]
++ "TARGET_VIS4B"
++ "fpcmp<fpcscond:code><FPCSMODE:vbits>shl\t%1, %2, %3, %0"
++ [(set_attr "type" "viscmp")])
++
++(define_insn "fpcmpu<fpcsucond:code><FPCSMODE:vbits><P:mode>shl"
++ [(set (match_operand:P 0 "register_operand" "=r")
++ (unspec:P [(fpcsucond:FPCSMODE (match_operand:FPCSMODE 1 "register_operand" "e")
++ (match_operand:FPCSMODE 2 "register_operand" "e"))
++ (match_operand:SI 3 "imm2_operand" "q")]
++ UNSPEC_FPUCMPSHL))]
++ "TARGET_VIS4B"
++ "fpcmpu<fpcsucond:code><FPCSMODE:vbits>shl\t%1, %2, %3, %0"
++ [(set_attr "type" "viscmp")])
++
++(define_insn "fpcmpde<FPCSMODE:vbits><P:mode>shl"
++ [(set (match_operand:P 0 "register_operand" "=r")
++ (unspec:P [(match_operand:FPCSMODE 1 "register_operand" "e")
++ (match_operand:FPCSMODE 2 "register_operand" "e")
++ (match_operand:SI 3 "imm2_operand" "q")]
++ UNSPEC_FPCMPDESHL))]
++ "TARGET_VIS4B"
++ "fpcmpde<FPCSMODE:vbits>shl\t%1, %2, %3, %0"
++ [(set_attr "type" "viscmp")])
++
++(define_insn "fpcmpur<FPCSMODE:vbits><P:mode>shl"
++ [(set (match_operand:P 0 "register_operand" "=r")
++ (unspec:P [(match_operand:FPCSMODE 1 "register_operand" "e")
++ (match_operand:FPCSMODE 2 "register_operand" "e")
++ (match_operand:SI 3 "imm2_operand" "q")]
++ UNSPEC_FPCMPURSHL))]
++ "TARGET_VIS4B"
++ "fpcmpur<FPCSMODE:vbits>shl\t%1, %2, %3, %0"
++ [(set_attr "type" "viscmp")])
++
+ (include "sync.md")
+Index: gcc/config/sparc/ultra3.md
+===================================================================
+--- a/src/gcc/config/sparc/ultra3.md (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/sparc/ultra3.md (.../branches/gcc-7-branch)
+@@ -56,7 +56,7 @@
+
+ (define_insn_reservation "us3_array" 2
+ (and (eq_attr "cpu" "ultrasparc3")
+- (eq_attr "type" "array,edgen"))
++ (eq_attr "type" "array,edgen,bmask"))
+ "us3_ms + us3_slotany, nothing")
+
+ ;; ??? Not entirely accurate.
+@@ -176,7 +176,7 @@
+ (define_insn_reservation "us3_fga"
+ 3
+ (and (eq_attr "cpu" "ultrasparc3")
+- (eq_attr "type" "fga,visl,vismv"))
++ (eq_attr "type" "fga,visl,viscmp,vismv"))
+ "us3_fpa + us3_slotany, nothing*2")
+
+ (define_insn_reservation "us3_fgm"
+Index: gcc/config/sparc/sparc.opt
+===================================================================
+--- a/src/gcc/config/sparc/sparc.opt (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/sparc/sparc.opt (.../branches/gcc-7-branch)
+@@ -81,6 +81,10 @@
+ Target Report Mask(VIS4)
+ Use UltraSPARC Visual Instruction Set version 4.0 extensions.
+
++mvis4b
++Target Report Mask(VIS4B)
++Use additional VIS instructions introduced in OSA2017.
++
+ mcbcond
+ Target Report Mask(CBCOND)
+ Use UltraSPARC Compare-and-Branch extensions.
+@@ -89,6 +93,10 @@
+ Target Report Mask(FMAF)
+ Use UltraSPARC Fused Multiply-Add extensions.
+
++mfsmuld
++Target Report Mask(FSMULD)
++Use Floating-point Multiply Single to Double (FsMULd) instruction.
++
+ mpopc
+ Target Report Mask(POPC)
+ Use UltraSPARC Population-Count instruction.
+@@ -209,6 +217,9 @@
+ EnumValue
+ Enum(sparc_processor_type) String(niagara7) Value(PROCESSOR_NIAGARA7)
+
++EnumValue
++Enum(sparc_processor_type) String(m8) Value(PROCESSOR_M8)
++
+ mcmodel=
+ Target RejectNegative Joined Var(sparc_cmodel_string)
+ Use given SPARC-V9 code model.
+@@ -230,6 +241,18 @@
+ Target Report RejectNegative Var(sparc_fix_ut699)
+ Enable workarounds for the errata of the UT699 processor.
+
++mfix-ut700
++Target Report RejectNegative Var(sparc_fix_ut700)
++Enable workarounds for the errata of the UT699E/UT700 processor.
++
++mfix-gr712rc
++Target Report RejectNegative Var(sparc_fix_gr712rc)
++Enable workarounds for the errata of the GR712RC processor.
++
++;; Enable workaround for back-to-back store errata
++TargetVariable
++unsigned int sparc_fix_b2bst
++
+ Mask(LONG_DOUBLE_128)
+ ;; Use 128-bit long double
+
+Index: gcc/config/sparc/sparc-c.c
+===================================================================
+--- a/src/gcc/config/sparc/sparc-c.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/sparc/sparc-c.c (.../branches/gcc-7-branch)
+@@ -40,8 +40,13 @@
+ cpp_assert (parse_in, "machine=sparc");
+ }
+
+- if (TARGET_VIS4)
++ if (TARGET_VIS4B)
+ {
++ cpp_define (parse_in, "__VIS__=0x410");
++ cpp_define (parse_in, "__VIS=0x410");
++ }
++ else if (TARGET_VIS4)
++ {
+ cpp_define (parse_in, "__VIS__=0x400");
+ cpp_define (parse_in, "__VIS=0x400");
+ }
+Index: gcc/config/sparc/sparc-opts.h
+===================================================================
+--- a/src/gcc/config/sparc/sparc-opts.h (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/sparc/sparc-opts.h (.../branches/gcc-7-branch)
+@@ -46,6 +46,7 @@
+ PROCESSOR_NIAGARA3,
+ PROCESSOR_NIAGARA4,
+ PROCESSOR_NIAGARA7,
++ PROCESSOR_M8,
+ PROCESSOR_NATIVE
+ };
+
+Index: gcc/config/sparc/niagara2.md
+===================================================================
+--- a/src/gcc/config/sparc/niagara2.md (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/sparc/niagara2.md (.../branches/gcc-7-branch)
+@@ -111,10 +111,10 @@
+
+ (define_insn_reservation "niag2_vis" 6
+ (and (eq_attr "cpu" "niagara2")
+- (eq_attr "type" "fga,vismv,visl,fgm_pack,fgm_mul,pdist,edge,edgen,array,gsr"))
++ (eq_attr "type" "fga,vismv,visl,viscmp,fgm_pack,fgm_mul,pdist,edge,edgen,array,bmask,gsr"))
+ "niag2_pipe*6")
+
+ (define_insn_reservation "niag3_vis" 9
+ (and (eq_attr "cpu" "niagara3")
+- (eq_attr "type" "fga,vismv,visl,fgm_pack,fgm_mul,pdist,pdistn,edge,edgen,array,gsr"))
++ (eq_attr "type" "fga,vismv,visl,viscmp,fgm_pack,fgm_mul,pdist,pdistn,edge,edgen,array,bmask,gsr"))
+ "niag2_pipe*9")
+Index: gcc/config/sparc/niagara4.md
+===================================================================
+--- a/src/gcc/config/sparc/niagara4.md (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/sparc/niagara4.md (.../branches/gcc-7-branch)
+@@ -66,7 +66,7 @@
+
+ (define_insn_reservation "n4_array" 12
+ (and (eq_attr "cpu" "niagara4")
+- (eq_attr "type" "array,edge,edgen"))
++ (eq_attr "type" "array,bmask,edge,edgen"))
+ "n4_slot1, nothing*11")
+
+ (define_insn_reservation "n4_vis_move_1cycle" 1
+@@ -90,8 +90,9 @@
+
+ (define_insn_reservation "n4_vis_logical" 3
+ (and (eq_attr "cpu" "niagara4")
+- (and (eq_attr "type" "visl,pdistn")
+- (eq_attr "fptype" "double")))
++ (ior (and (eq_attr "type" "visl,pdistn")
++ (eq_attr "fptype" "double"))
++ (eq_attr "type" "viscmp")))
+ "n4_slot1, nothing*2")
+
+ (define_insn_reservation "n4_vis_logical_11cycle" 11
+Index: gcc/config/sparc/ultra1_2.md
+===================================================================
+--- a/src/gcc/config/sparc/ultra1_2.md (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/sparc/ultra1_2.md (.../branches/gcc-7-branch)
+@@ -263,10 +263,10 @@
+
+ (define_insn_reservation "us1_fga_double"
+ 2
+- (and (and
+- (eq_attr "cpu" "ultrasparc")
+- (eq_attr "type" "fga,visl,vismv"))
+- (eq_attr "fptype" "double"))
++ (and (eq_attr "cpu" "ultrasparc")
++ (ior (and (eq_attr "type" "fga,visl,vismv")
++ (eq_attr "fptype" "double"))
++ (eq_attr "type" "viscmp")))
+ "us1_fpa + us1_fp_double + us1_slotany, nothing")
+
+ (define_bypass 1 "us1_fga_double" "us1_fga_double")
Index: gcc/config/sparc/sparc.c
===================================================================
--- a/src/gcc/config/sparc/sparc.c (.../tags/gcc_7_1_0_release)
+++ b/src/gcc/config/sparc/sparc.c (.../branches/gcc-7-branch)
-@@ -1341,7 +1341,6 @@
+@@ -448,6 +448,30 @@
+ 0, /* shift penalty */
+ };
+
++static const
++struct processor_costs m8_costs = {
++ COSTS_N_INSNS (3), /* int load */
++ COSTS_N_INSNS (3), /* int signed load */
++ COSTS_N_INSNS (3), /* int zeroed load */
++ COSTS_N_INSNS (3), /* float load */
++ COSTS_N_INSNS (9), /* fmov, fneg, fabs */
++ COSTS_N_INSNS (9), /* fadd, fsub */
++ COSTS_N_INSNS (9), /* fcmp */
++ COSTS_N_INSNS (9), /* fmov, fmovr */
++ COSTS_N_INSNS (9), /* fmul */
++ COSTS_N_INSNS (26), /* fdivs */
++ COSTS_N_INSNS (30), /* fdivd */
++ COSTS_N_INSNS (33), /* fsqrts */
++ COSTS_N_INSNS (41), /* fsqrtd */
++ COSTS_N_INSNS (12), /* imul */
++ COSTS_N_INSNS (10), /* imulX */
++ 0, /* imul bit factor */
++ COSTS_N_INSNS (57), /* udiv/sdiv */
++ COSTS_N_INSNS (30), /* udivx/sdivx */
++ COSTS_N_INSNS (1), /* movcc/movr */
++ 0, /* shift penalty */
++};
++
+ static const struct processor_costs *sparc_costs = &cypress_costs;
+
+ #ifdef HAVE_AS_RELAX_OPTION
+@@ -896,6 +920,12 @@
+ to properly detect the various hazards. Therefore, this machine specific
+ pass runs as late as possible. */
+
++/* True if INSN is a md pattern or asm statement. */
++#define USEFUL_INSN_P(INSN) \
++ (NONDEBUG_INSN_P (INSN) \
++ && GET_CODE (PATTERN (INSN)) != USE \
++ && GET_CODE (PATTERN (INSN)) != CLOBBER)
++
+ static unsigned int
+ sparc_do_work_around_errata (void)
+ {
+@@ -915,6 +945,81 @@
+ if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (PATTERN (insn)))
+ insn = seq->insn (1);
+
++ /* Look for either of these two sequences:
++
++ Sequence A:
++ 1. store of word size or less (e.g. st / stb / sth / stf)
++ 2. any single instruction that is not a load or store
++ 3. any store instruction (e.g. st / stb / sth / stf / std / stdf)
++
++ Sequence B:
++ 1. store of double word size (e.g. std / stdf)
++ 2. any store instruction (e.g. st / stb / sth / stf / std / stdf) */
++ if (sparc_fix_b2bst
++ && NONJUMP_INSN_P (insn)
++ && (set = single_set (insn)) != NULL_RTX
++ && MEM_P (SET_DEST (set)))
++ {
++ /* Sequence B begins with a double-word store. */
++ bool seq_b = GET_MODE_SIZE (GET_MODE (SET_DEST (set))) == 8;
++ rtx_insn *after;
++ int i;
++
++ next = next_active_insn (insn);
++ if (!next)
++ break;
++
++ for (after = next, i = 0; i < 2; i++)
++ {
++ /* Skip empty assembly statements. */
++ if ((GET_CODE (PATTERN (after)) == UNSPEC_VOLATILE)
++ || (USEFUL_INSN_P (after)
++ && (asm_noperands (PATTERN (after))>=0)
++ && !strcmp (decode_asm_operands (PATTERN (after),
++ NULL, NULL, NULL,
++ NULL, NULL), "")))
++ after = next_active_insn (after);
++ if (!after)
++ break;
++
++ /* If the insn is a branch, then it cannot be problematic. */
++ if (!NONJUMP_INSN_P (after)
++ || GET_CODE (PATTERN (after)) == SEQUENCE)
++ break;
++
++ /* Sequence B is only two instructions long. */
++ if (seq_b)
++ {
++ /* Add NOP if followed by a store. */
++ if ((set = single_set (after)) != NULL_RTX
++ && MEM_P (SET_DEST (set)))
++ insert_nop = true;
++
++ /* Otherwise it is ok. */
++ break;
++ }
++
++ /* If the second instruction is a load or a store,
++ then the sequence cannot be problematic. */
++ if (i == 0)
++ {
++ if (((set = single_set (after)) != NULL_RTX)
++ && (MEM_P (SET_DEST (set)) || MEM_P (SET_SRC (set))))
++ break;
++
++ after = next_active_insn (after);
++ if (!after)
++ break;
++ }
++
++ /* Add NOP if third instruction is a store. */
++ if (i == 1
++ && ((set = single_set (after)) != NULL_RTX)
++ && MEM_P (SET_DEST (set)))
++ insert_nop = true;
++ }
++ }
++ else
+ /* Look for a single-word load into an odd-numbered FP register. */
+ if (sparc_fix_at697f
+ && NONJUMP_INSN_P (insn)
+@@ -1167,8 +1272,7 @@
+ /* opt_pass methods: */
+ virtual bool gate (function *)
+ {
+- /* The only errata we handle are those of the AT697F and UT699. */
+- return sparc_fix_at697f != 0 || sparc_fix_ut699 != 0;
++ return sparc_fix_at697f || sparc_fix_ut699 || sparc_fix_b2bst;
+ }
+
+ virtual unsigned int execute (function *)
+@@ -1200,6 +1304,8 @@
+ fprintf (stderr, "FLAT ");
+ if (flags & MASK_FMAF)
+ fprintf (stderr, "FMAF ");
++ if (flags & MASK_FSMULD)
++ fprintf (stderr, "FSMULD ");
+ if (flags & MASK_FPU)
+ fprintf (stderr, "FPU ");
+ if (flags & MASK_HARD_QUAD)
+@@ -1222,6 +1328,8 @@
+ fprintf (stderr, "VIS3 ");
+ if (flags & MASK_VIS4)
+ fprintf (stderr, "VIS4 ");
++ if (flags & MASK_VIS4B)
++ fprintf (stderr, "VIS4B ");
+ if (flags & MASK_CBCOND)
+ fprintf (stderr, "CBCOND ");
+ if (flags & MASK_DEPRECATED_V8_INSNS)
+@@ -1286,6 +1394,7 @@
+ { TARGET_CPU_niagara3, PROCESSOR_NIAGARA3 },
+ { TARGET_CPU_niagara4, PROCESSOR_NIAGARA4 },
+ { TARGET_CPU_niagara7, PROCESSOR_NIAGARA7 },
++ { TARGET_CPU_m8, PROCESSOR_M8 },
+ { -1, PROCESSOR_V7 }
+ };
+ const struct cpu_default *def;
+@@ -1296,24 +1405,24 @@
+ const int disable;
+ const int enable;
+ } const cpu_table[] = {
+- { "v7", MASK_ISA, 0 },
+- { "cypress", MASK_ISA, 0 },
++ { "v7", MASK_ISA|MASK_FSMULD, 0 },
++ { "cypress", MASK_ISA|MASK_FSMULD, 0 },
+ { "v8", MASK_ISA, MASK_V8 },
+ /* TI TMS390Z55 supersparc */
+ { "supersparc", MASK_ISA, MASK_V8 },
+- { "hypersparc", MASK_ISA, MASK_V8|MASK_FPU },
+- { "leon", MASK_ISA, MASK_V8|MASK_LEON|MASK_FPU },
+- { "leon3", MASK_ISA, MASK_V8|MASK_LEON3|MASK_FPU },
+- { "leon3v7", MASK_ISA, MASK_LEON3|MASK_FPU },
+- { "sparclite", MASK_ISA, MASK_SPARCLITE },
++ { "hypersparc", MASK_ISA, MASK_V8 },
++ { "leon", MASK_ISA|MASK_FSMULD, MASK_V8|MASK_LEON },
++ { "leon3", MASK_ISA, MASK_V8|MASK_LEON3 },
++ { "leon3v7", MASK_ISA|MASK_FSMULD, MASK_LEON3 },
++ { "sparclite", MASK_ISA|MASK_FSMULD, MASK_SPARCLITE },
+ /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
+ { "f930", MASK_ISA|MASK_FPU, MASK_SPARCLITE },
+ /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
+- { "f934", MASK_ISA, MASK_SPARCLITE|MASK_FPU },
++ { "f934", MASK_ISA|MASK_FSMULD, MASK_SPARCLITE },
+ { "sparclite86x", MASK_ISA|MASK_FPU, MASK_SPARCLITE },
+- { "sparclet", MASK_ISA, MASK_SPARCLET },
++ { "sparclet", MASK_ISA|MASK_FSMULD, MASK_SPARCLET },
+ /* TEMIC sparclet */
+- { "tsc701", MASK_ISA, MASK_SPARCLET },
++ { "tsc701", MASK_ISA|MASK_FSMULD, MASK_SPARCLET },
+ { "v9", MASK_ISA, MASK_V9 },
+ /* UltraSPARC I, II, IIi */
+ { "ultrasparc", MASK_ISA,
+@@ -1337,11 +1446,13 @@
+ MASK_V9|MASK_POPC|MASK_VIS3|MASK_FMAF|MASK_CBCOND },
+ /* UltraSPARC M7 */
+ { "niagara7", MASK_ISA,
+- MASK_V9|MASK_POPC|MASK_VIS4|MASK_FMAF|MASK_CBCOND|MASK_SUBXC }
++ MASK_V9|MASK_POPC|MASK_VIS4|MASK_FMAF|MASK_CBCOND|MASK_SUBXC },
++ /* UltraSPARC M8 */
++ { "m8", MASK_ISA,
++ MASK_V9|MASK_POPC|MASK_VIS4|MASK_FMAF|MASK_CBCOND|MASK_SUBXC|MASK_VIS4B }
};
const struct cpu_table *cpu;
unsigned int i;
@@ -60642,16 +72657,62 @@ Index: gcc/config/sparc/sparc.c
if (sparc_debug_string != NULL)
{
-@@ -1433,8 +1432,6 @@
+@@ -1377,6 +1488,11 @@
+ }
+ }
+
++ /* Enable the FsMULd instruction by default if not explicitly specified by
++ the user. It may be later disabled by the CPU (explicitly or not). */
++ if (TARGET_FPU && !(target_flags_explicit & MASK_FSMULD))
++ target_flags |= MASK_FSMULD;
++
+ if (TARGET_DEBUG_OPTIONS)
+ {
+ dump_target_flags("Initial target_flags", target_flags);
+@@ -1422,7 +1538,7 @@
+ sparc_cmodel = cmodel->value;
+ }
+ else
+- error ("-mcmodel= is not supported on 32 bit systems");
++ error ("-mcmodel= is not supported on 32-bit systems");
+ }
+
+ /* Check that -fcall-saved-REG wasn't specified for out registers. */
+@@ -1433,9 +1549,7 @@
call_used_regs [i] = 1;
}
- fpu = target_flags & MASK_FPU; /* save current -mfpu status */
-
- /* Set the default CPU. */
+- /* Set the default CPU. */
++ /* Set the default CPU if no -mcpu option was specified. */
if (!global_options_set.x_sparc_cpu_and_features)
{
-@@ -1473,22 +1470,18 @@
+ for (def = &cpu_default[0]; def->cpu != -1; ++def)
+@@ -1445,6 +1559,7 @@
+ sparc_cpu_and_features = def->processor;
+ }
+
++ /* Set the default CPU if no -mtune option was specified. */
+ if (!global_options_set.x_sparc_cpu)
+ sparc_cpu = sparc_cpu_and_features;
+
+@@ -1453,8 +1568,6 @@
+ if (TARGET_DEBUG_OPTIONS)
+ {
+ fprintf (stderr, "sparc_cpu_and_features: %s\n", cpu->name);
+- fprintf (stderr, "sparc_cpu: %s\n",
+- cpu_table[(int) sparc_cpu].name);
+ dump_target_flags ("cpu->disable", cpu->disable);
+ dump_target_flags ("cpu->enable", cpu->enable);
+ }
+@@ -1470,37 +1583,39 @@
+ #ifndef HAVE_AS_SPARC5_VIS4
+ & ~(MASK_VIS4 | MASK_SUBXC)
+ #endif
++#ifndef HAVE_AS_SPARC6
++ & ~(MASK_VIS4B)
++#endif
#ifndef HAVE_AS_LEON
& ~(MASK_LEON | MASK_LEON3)
#endif
@@ -60678,8 +72739,19 @@ Index: gcc/config/sparc/sparc.c
if (TARGET_VIS4)
target_flags |= MASK_VIS3 | MASK_VIS2 | MASK_VIS;
-@@ -1499,8 +1492,7 @@
- | MASK_FMAF);
+- /* Don't allow -mvis, -mvis2, -mvis3, -mvis4 or -mfmaf if FPU is
+- disabled. */
+- if (! TARGET_FPU)
++ /* -mvis4b implies -mvis4, -mvis3, -mvis2 and -mvis */
++ if (TARGET_VIS4B)
++ target_flags |= MASK_VIS4 | MASK_VIS3 | MASK_VIS2 | MASK_VIS;
++
++ /* Don't allow -mvis, -mvis2, -mvis3, -mvis4, -mvis4b, -mfmaf and -mfsmuld if
++ FPU is disabled. */
++ if (!TARGET_FPU)
+ target_flags &= ~(MASK_VIS | MASK_VIS2 | MASK_VIS3 | MASK_VIS4
+- | MASK_FMAF);
++ | MASK_VIS4B | MASK_FMAF | MASK_FSMULD);
/* -mvis assumes UltraSPARC+, so we are sure v9 instructions
- are available.
@@ -60688,18 +72760,44 @@ Index: gcc/config/sparc/sparc.c
if (TARGET_VIS || TARGET_ARCH64)
{
target_flags |= MASK_V9;
-@@ -1507,7 +1499,7 @@
+@@ -1507,19 +1622,19 @@
target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
}
- /* -mvis also implies -mv8plus on 32-bit */
+- if (TARGET_VIS && ! TARGET_ARCH64)
+ /* -mvis also implies -mv8plus on 32-bit. */
- if (TARGET_VIS && ! TARGET_ARCH64)
++ if (TARGET_VIS && !TARGET_ARCH64)
target_flags |= MASK_V8PLUS;
-@@ -1528,15 +1520,18 @@
+- /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
++ /* Use the deprecated v8 insns for sparc64 in 32-bit mode. */
+ if (TARGET_V9 && TARGET_ARCH32)
+ target_flags |= MASK_DEPRECATED_V8_INSNS;
+
+- /* V8PLUS requires V9, makes no sense in 64 bit mode. */
+- if (! TARGET_V9 || TARGET_ARCH64)
++ /* V8PLUS requires V9 and makes no sense in 64-bit mode. */
++ if (!TARGET_V9 || TARGET_ARCH64)
+ target_flags &= ~MASK_V8PLUS;
+
+- /* Don't use stack biasing in 32 bit mode. */
++ /* Don't use stack biasing in 32-bit mode. */
+ if (TARGET_ARCH32)
+ target_flags &= ~MASK_STACK_BIAS;
+
+@@ -1527,16 +1642,28 @@
+ if (!(target_flags_explicit & MASK_LRA))
target_flags |= MASK_LRA;
++ /* Enable the back-to-back store errata workaround for LEON3FT. */
++ if (sparc_fix_ut699 || sparc_fix_ut700 || sparc_fix_gr712rc)
++ sparc_fix_b2bst = 1;
++
++ /* Disable FsMULd for the UT699 since it doesn't work correctly. */
++ if (sparc_fix_ut699)
++ target_flags &= ~MASK_FSMULD;
++
/* Supply a default value for align_functions. */
- if (align_functions == 0
- && (sparc_cpu == PROCESSOR_ULTRASPARC
@@ -60715,13 +72813,83 @@ Index: gcc/config/sparc/sparc.c
- align_functions = 32;
+ || sparc_cpu == PROCESSOR_NIAGARA4)
+ align_functions = 32;
-+ else if (sparc_cpu == PROCESSOR_NIAGARA7)
++ else if (sparc_cpu == PROCESSOR_NIAGARA7
++ || sparc_cpu == PROCESSOR_M8)
+ align_functions = 64;
+ }
/* Validate PCC_STRUCT_RETURN. */
if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
-@@ -5789,6 +5784,9 @@
+@@ -1602,6 +1729,9 @@
+ case PROCESSOR_NIAGARA7:
+ sparc_costs = &niagara7_costs;
+ break;
++ case PROCESSOR_M8:
++ sparc_costs = &m8_costs;
++ break;
+ case PROCESSOR_NATIVE:
+ gcc_unreachable ();
+ };
+@@ -1664,13 +1794,14 @@
+ || sparc_cpu == PROCESSOR_NIAGARA4)
+ ? 2
+ : (sparc_cpu == PROCESSOR_ULTRASPARC3
+- ? 8 : (sparc_cpu == PROCESSOR_NIAGARA7
++ ? 8 : ((sparc_cpu == PROCESSOR_NIAGARA7
++ || sparc_cpu == PROCESSOR_M8)
+ ? 32 : 3))),
+ global_options.x_param_values,
+ global_options_set.x_param_values);
+
+- /* For PARAM_L1_CACHE_LINE_SIZE we use the default 32 bytes (see
+- params.def), so no maybe_set_param_value is needed.
++ /* PARAM_L1_CACHE_LINE_SIZE is the size of the L1 cache line, in
++ bytes.
+
+ The Oracle SPARC Architecture (previously the UltraSPARC
+ Architecture) specification states that when a PREFETCH[A]
+@@ -1686,6 +1817,11 @@
+ L2 and L3, but only 32B are brought into the L1D$. (Assuming it
+ is a read_n prefetch, which is the only type which allocates to
+ the L1.) */
++ maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
++ (sparc_cpu == PROCESSOR_M8
++ ? 64 : 32),
++ global_options.x_param_values,
++ global_options_set.x_param_values);
+
+ /* PARAM_L1_CACHE_SIZE is the size of the L1D$ (most SPARC chips use
+ Hardvard level-1 caches) in kilobytes. Both UltraSPARC and
+@@ -1697,7 +1833,8 @@
+ || sparc_cpu == PROCESSOR_NIAGARA2
+ || sparc_cpu == PROCESSOR_NIAGARA3
+ || sparc_cpu == PROCESSOR_NIAGARA4
+- || sparc_cpu == PROCESSOR_NIAGARA7)
++ || sparc_cpu == PROCESSOR_NIAGARA7
++ || sparc_cpu == PROCESSOR_M8)
+ ? 16 : 64),
+ global_options.x_param_values,
+ global_options_set.x_param_values);
+@@ -1706,7 +1843,8 @@
+ /* PARAM_L2_CACHE_SIZE is the size fo the L2 in kilobytes. Note
+ that 512 is the default in params.def. */
+ maybe_set_param_value (PARAM_L2_CACHE_SIZE,
+- (sparc_cpu == PROCESSOR_NIAGARA4
++ ((sparc_cpu == PROCESSOR_NIAGARA4
++ || sparc_cpu == PROCESSOR_M8)
+ ? 128 : (sparc_cpu == PROCESSOR_NIAGARA7
+ ? 256 : 512)),
+ global_options.x_param_values,
+@@ -4834,7 +4972,7 @@
+ ??? Note that, despite the settings, non-double-aligned parameter
+ registers can hold double-word quantities in 32-bit mode. */
+
+-/* This points to either the 32 bit or the 64 bit version. */
++/* This points to either the 32-bit or the 64-bit version. */
+ const int *hard_regno_mode_classes;
+
+ static const int hard_32bit_mode_classes[] = {
+@@ -5789,6 +5927,9 @@
{
HOST_WIDE_INT size = sparc_frame_size;
@@ -60731,11 +72899,395 @@ Index: gcc/config/sparc/sparc.c
if (sparc_n_global_fp_regs > 0)
emit_save_or_restore_global_fp_regs (sparc_frame_base_reg,
sparc_frame_base_offset
+@@ -7165,7 +7306,7 @@
+ }
+
+ /* Handle the FUNCTION_ARG_PADDING macro.
+- For the 64 bit ABI structs are always stored left shifted in their
++ For the 64-bit ABI structs are always stored left shifted in their
+ argument slot. */
+
+ enum direction
+@@ -8283,7 +8424,7 @@
+ if (reversed ^ far)
+ code = reverse_condition (code);
+
+- /* Only 64 bit versions of these instructions exist. */
++ /* Only 64-bit versions of these instructions exist. */
+ gcc_assert (mode == DImode);
+
+ /* Start by writing the branch condition. */
+@@ -8711,7 +8852,7 @@
+ return 0;
+
+ /* The first offset must be evenly divisible by 8 to ensure the
+- address is 64 bit aligned. */
++ address is 64-bit aligned. */
+ if (offset1 % 8 != 0)
+ return 0;
+
+@@ -9480,7 +9621,8 @@
+ && sparc_cpu != PROCESSOR_NIAGARA2
+ && sparc_cpu != PROCESSOR_NIAGARA3
+ && sparc_cpu != PROCESSOR_NIAGARA4
+- && sparc_cpu != PROCESSOR_NIAGARA7)
++ && sparc_cpu != PROCESSOR_NIAGARA7
++ && sparc_cpu != PROCESSOR_M8)
+ emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp, SImode, 8))));
+
+ /* Call __enable_execute_stack after writing onto the stack to make sure
+@@ -9526,7 +9668,8 @@
+ && sparc_cpu != PROCESSOR_NIAGARA2
+ && sparc_cpu != PROCESSOR_NIAGARA3
+ && sparc_cpu != PROCESSOR_NIAGARA4
+- && sparc_cpu != PROCESSOR_NIAGARA7)
++ && sparc_cpu != PROCESSOR_NIAGARA7
++ && sparc_cpu != PROCESSOR_M8)
+ emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 8))));
+
+ /* Call __enable_execute_stack after writing onto the stack to make sure
+@@ -9726,7 +9869,8 @@
+ || sparc_cpu == PROCESSOR_NIAGARA3)
+ return 0;
+ if (sparc_cpu == PROCESSOR_NIAGARA4
+- || sparc_cpu == PROCESSOR_NIAGARA7)
++ || sparc_cpu == PROCESSOR_NIAGARA7
++ || sparc_cpu == PROCESSOR_M8)
+ return 2;
+ if (sparc_cpu == PROCESSOR_ULTRASPARC
+ || sparc_cpu == PROCESSOR_ULTRASPARC3)
+@@ -9760,6 +9904,7 @@
+ return 2;
+ case PROCESSOR_ULTRASPARC:
+ case PROCESSOR_ULTRASPARC3:
++ case PROCESSOR_M8:
+ return 4;
+ }
+ }
+@@ -10342,6 +10487,45 @@
+ SPARC_BUILTIN_FPSUBS8,
+ SPARC_BUILTIN_FPSUBUS8,
+ SPARC_BUILTIN_FPSUBUS16,
++
++ /* VIS 4.0B builtins. */
++
++ /* Note that all the DICTUNPACK* entries should be kept
++ contiguous. */
++ SPARC_BUILTIN_FIRST_DICTUNPACK,
++ SPARC_BUILTIN_DICTUNPACK8 = SPARC_BUILTIN_FIRST_DICTUNPACK,
++ SPARC_BUILTIN_DICTUNPACK16,
++ SPARC_BUILTIN_DICTUNPACK32,
++ SPARC_BUILTIN_LAST_DICTUNPACK = SPARC_BUILTIN_DICTUNPACK32,
++
++ /* Note that all the FPCMP*SHL entries should be kept
++ contiguous. */
++ SPARC_BUILTIN_FIRST_FPCMPSHL,
++ SPARC_BUILTIN_FPCMPLE8SHL = SPARC_BUILTIN_FIRST_FPCMPSHL,
++ SPARC_BUILTIN_FPCMPGT8SHL,
++ SPARC_BUILTIN_FPCMPEQ8SHL,
++ SPARC_BUILTIN_FPCMPNE8SHL,
++ SPARC_BUILTIN_FPCMPLE16SHL,
++ SPARC_BUILTIN_FPCMPGT16SHL,
++ SPARC_BUILTIN_FPCMPEQ16SHL,
++ SPARC_BUILTIN_FPCMPNE16SHL,
++ SPARC_BUILTIN_FPCMPLE32SHL,
++ SPARC_BUILTIN_FPCMPGT32SHL,
++ SPARC_BUILTIN_FPCMPEQ32SHL,
++ SPARC_BUILTIN_FPCMPNE32SHL,
++ SPARC_BUILTIN_FPCMPULE8SHL,
++ SPARC_BUILTIN_FPCMPUGT8SHL,
++ SPARC_BUILTIN_FPCMPULE16SHL,
++ SPARC_BUILTIN_FPCMPUGT16SHL,
++ SPARC_BUILTIN_FPCMPULE32SHL,
++ SPARC_BUILTIN_FPCMPUGT32SHL,
++ SPARC_BUILTIN_FPCMPDE8SHL,
++ SPARC_BUILTIN_FPCMPDE16SHL,
++ SPARC_BUILTIN_FPCMPDE32SHL,
++ SPARC_BUILTIN_FPCMPUR8SHL,
++ SPARC_BUILTIN_FPCMPUR16SHL,
++ SPARC_BUILTIN_FPCMPUR32SHL,
++ SPARC_BUILTIN_LAST_FPCMPSHL = SPARC_BUILTIN_FPCMPUR32SHL,
+
+ SPARC_BUILTIN_MAX
+ };
+@@ -10349,6 +10533,27 @@
+ static GTY (()) tree sparc_builtins[(int) SPARC_BUILTIN_MAX];
+ static enum insn_code sparc_builtins_icode[(int) SPARC_BUILTIN_MAX];
+
++/* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
++ The instruction should require a constant operand of some sort. The
++ function prints an error if OPVAL is not valid. */
++
++static int
++check_constant_argument (enum insn_code icode, int opnum, rtx opval)
++{
++ if (GET_CODE (opval) != CONST_INT)
++ {
++ error ("%qs expects a constant argument", insn_data[icode].name);
++ return false;
++ }
++
++ if (!(*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode))
++ {
++ error ("constant argument out of range for %qs", insn_data[icode].name);
++ return false;
++ }
++ return true;
++}
++
+ /* Add a SPARC builtin function with NAME, ICODE, CODE and TYPE. Return the
+ function decl or NULL_TREE if the builtin was not added. */
+
+@@ -10442,6 +10647,12 @@
+ v8qi, v8qi, 0);
+ tree si_ftype_v8qi_v8qi = build_function_type_list (intSI_type_node,
+ v8qi, v8qi, 0);
++ tree v8qi_ftype_df_si = build_function_type_list (v8qi, double_type_node,
++ intSI_type_node, 0);
++ tree v4hi_ftype_df_si = build_function_type_list (v4hi, double_type_node,
++ intSI_type_node, 0);
++ tree v2si_ftype_df_si = build_function_type_list (v2si, double_type_node,
++ intDI_type_node, 0);
+ tree di_ftype_di_di = build_function_type_list (intDI_type_node,
+ intDI_type_node,
+ intDI_type_node, 0);
+@@ -10896,6 +11107,156 @@
+ def_builtin_const ("__builtin_vis_fpsubus16", CODE_FOR_ussubv4hi3,
+ SPARC_BUILTIN_FPSUBUS16, v4hi_ftype_v4hi_v4hi);
+ }
++
++ if (TARGET_VIS4B)
++ {
++ def_builtin_const ("__builtin_vis_dictunpack8", CODE_FOR_dictunpack8,
++ SPARC_BUILTIN_DICTUNPACK8, v8qi_ftype_df_si);
++ def_builtin_const ("__builtin_vis_dictunpack16", CODE_FOR_dictunpack16,
++ SPARC_BUILTIN_DICTUNPACK16, v4hi_ftype_df_si);
++ def_builtin_const ("__builtin_vis_dictunpack32", CODE_FOR_dictunpack32,
++ SPARC_BUILTIN_DICTUNPACK32, v2si_ftype_df_si);
++
++ if (TARGET_ARCH64)
++ {
++ tree di_ftype_v8qi_v8qi_si = build_function_type_list (intDI_type_node,
++ v8qi, v8qi,
++ intSI_type_node, 0);
++ tree di_ftype_v4hi_v4hi_si = build_function_type_list (intDI_type_node,
++ v4hi, v4hi,
++ intSI_type_node, 0);
++ tree di_ftype_v2si_v2si_si = build_function_type_list (intDI_type_node,
++ v2si, v2si,
++ intSI_type_node, 0);
++
++ def_builtin_const ("__builtin_vis_fpcmple8shl", CODE_FOR_fpcmple8dishl,
++ SPARC_BUILTIN_FPCMPLE8SHL, di_ftype_v8qi_v8qi_si);
++ def_builtin_const ("__builtin_vis_fpcmpgt8shl", CODE_FOR_fpcmpgt8dishl,
++ SPARC_BUILTIN_FPCMPGT8SHL, di_ftype_v8qi_v8qi_si);
++ def_builtin_const ("__builtin_vis_fpcmpeq8shl", CODE_FOR_fpcmpeq8dishl,
++ SPARC_BUILTIN_FPCMPEQ8SHL, di_ftype_v8qi_v8qi_si);
++ def_builtin_const ("__builtin_vis_fpcmpne8shl", CODE_FOR_fpcmpne8dishl,
++ SPARC_BUILTIN_FPCMPNE8SHL, di_ftype_v8qi_v8qi_si);
++
++ def_builtin_const ("__builtin_vis_fpcmple16shl", CODE_FOR_fpcmple16dishl,
++ SPARC_BUILTIN_FPCMPLE16SHL, di_ftype_v4hi_v4hi_si);
++ def_builtin_const ("__builtin_vis_fpcmpgt16shl", CODE_FOR_fpcmpgt16dishl,
++ SPARC_BUILTIN_FPCMPGT16SHL, di_ftype_v4hi_v4hi_si);
++ def_builtin_const ("__builtin_vis_fpcmpeq16shl", CODE_FOR_fpcmpeq16dishl,
++ SPARC_BUILTIN_FPCMPEQ16SHL, di_ftype_v4hi_v4hi_si);
++ def_builtin_const ("__builtin_vis_fpcmpne16shl", CODE_FOR_fpcmpne16dishl,
++ SPARC_BUILTIN_FPCMPNE16SHL, di_ftype_v4hi_v4hi_si);
++
++ def_builtin_const ("__builtin_vis_fpcmple32shl", CODE_FOR_fpcmple32dishl,
++ SPARC_BUILTIN_FPCMPLE32SHL, di_ftype_v2si_v2si_si);
++ def_builtin_const ("__builtin_vis_fpcmpgt32shl", CODE_FOR_fpcmpgt32dishl,
++ SPARC_BUILTIN_FPCMPGT32SHL, di_ftype_v2si_v2si_si);
++ def_builtin_const ("__builtin_vis_fpcmpeq32shl", CODE_FOR_fpcmpeq32dishl,
++ SPARC_BUILTIN_FPCMPEQ32SHL, di_ftype_v2si_v2si_si);
++ def_builtin_const ("__builtin_vis_fpcmpne32shl", CODE_FOR_fpcmpne32dishl,
++ SPARC_BUILTIN_FPCMPNE32SHL, di_ftype_v2si_v2si_si);
++
++
++ def_builtin_const ("__builtin_vis_fpcmpule8shl", CODE_FOR_fpcmpule8dishl,
++ SPARC_BUILTIN_FPCMPULE8SHL, di_ftype_v8qi_v8qi_si);
++ def_builtin_const ("__builtin_vis_fpcmpugt8shl", CODE_FOR_fpcmpugt8dishl,
++ SPARC_BUILTIN_FPCMPUGT8SHL, di_ftype_v8qi_v8qi_si);
++
++ def_builtin_const ("__builtin_vis_fpcmpule16shl", CODE_FOR_fpcmpule16dishl,
++ SPARC_BUILTIN_FPCMPULE16SHL, di_ftype_v4hi_v4hi_si);
++ def_builtin_const ("__builtin_vis_fpcmpugt16shl", CODE_FOR_fpcmpugt16dishl,
++ SPARC_BUILTIN_FPCMPUGT16SHL, di_ftype_v4hi_v4hi_si);
++
++ def_builtin_const ("__builtin_vis_fpcmpule32shl", CODE_FOR_fpcmpule32dishl,
++ SPARC_BUILTIN_FPCMPULE32SHL, di_ftype_v2si_v2si_si);
++ def_builtin_const ("__builtin_vis_fpcmpugt32shl", CODE_FOR_fpcmpugt32dishl,
++ SPARC_BUILTIN_FPCMPUGT32SHL, di_ftype_v2si_v2si_si);
++
++ def_builtin_const ("__builtin_vis_fpcmpde8shl", CODE_FOR_fpcmpde8dishl,
++ SPARC_BUILTIN_FPCMPDE8SHL, di_ftype_v8qi_v8qi_si);
++ def_builtin_const ("__builtin_vis_fpcmpde16shl", CODE_FOR_fpcmpde16dishl,
++ SPARC_BUILTIN_FPCMPDE16SHL, di_ftype_v4hi_v4hi_si);
++ def_builtin_const ("__builtin_vis_fpcmpde32shl", CODE_FOR_fpcmpde32dishl,
++ SPARC_BUILTIN_FPCMPDE32SHL, di_ftype_v2si_v2si_si);
++
++ def_builtin_const ("__builtin_vis_fpcmpur8shl", CODE_FOR_fpcmpur8dishl,
++ SPARC_BUILTIN_FPCMPUR8SHL, di_ftype_v8qi_v8qi_si);
++ def_builtin_const ("__builtin_vis_fpcmpur16shl", CODE_FOR_fpcmpur16dishl,
++ SPARC_BUILTIN_FPCMPUR16SHL, di_ftype_v4hi_v4hi_si);
++ def_builtin_const ("__builtin_vis_fpcmpur32shl", CODE_FOR_fpcmpur32dishl,
++ SPARC_BUILTIN_FPCMPUR32SHL, di_ftype_v2si_v2si_si);
++
++ }
++ else
++ {
++ tree si_ftype_v8qi_v8qi_si = build_function_type_list (intSI_type_node,
++ v8qi, v8qi,
++ intSI_type_node, 0);
++ tree si_ftype_v4hi_v4hi_si = build_function_type_list (intSI_type_node,
++ v4hi, v4hi,
++ intSI_type_node, 0);
++ tree si_ftype_v2si_v2si_si = build_function_type_list (intSI_type_node,
++ v2si, v2si,
++ intSI_type_node, 0);
++
++ def_builtin_const ("__builtin_vis_fpcmple8shl", CODE_FOR_fpcmple8sishl,
++ SPARC_BUILTIN_FPCMPLE8SHL, si_ftype_v8qi_v8qi_si);
++ def_builtin_const ("__builtin_vis_fpcmpgt8shl", CODE_FOR_fpcmpgt8sishl,
++ SPARC_BUILTIN_FPCMPGT8SHL, si_ftype_v8qi_v8qi_si);
++ def_builtin_const ("__builtin_vis_fpcmpeq8shl", CODE_FOR_fpcmpeq8sishl,
++ SPARC_BUILTIN_FPCMPEQ8SHL, si_ftype_v8qi_v8qi_si);
++ def_builtin_const ("__builtin_vis_fpcmpne8shl", CODE_FOR_fpcmpne8sishl,
++ SPARC_BUILTIN_FPCMPNE8SHL, si_ftype_v8qi_v8qi_si);
++
++ def_builtin_const ("__builtin_vis_fpcmple16shl", CODE_FOR_fpcmple16sishl,
++ SPARC_BUILTIN_FPCMPLE16SHL, si_ftype_v4hi_v4hi_si);
++ def_builtin_const ("__builtin_vis_fpcmpgt16shl", CODE_FOR_fpcmpgt16sishl,
++ SPARC_BUILTIN_FPCMPGT16SHL, si_ftype_v4hi_v4hi_si);
++ def_builtin_const ("__builtin_vis_fpcmpeq16shl", CODE_FOR_fpcmpeq16sishl,
++ SPARC_BUILTIN_FPCMPEQ16SHL, si_ftype_v4hi_v4hi_si);
++ def_builtin_const ("__builtin_vis_fpcmpne16shl", CODE_FOR_fpcmpne16sishl,
++ SPARC_BUILTIN_FPCMPNE16SHL, si_ftype_v4hi_v4hi_si);
++
++ def_builtin_const ("__builtin_vis_fpcmple32shl", CODE_FOR_fpcmple32sishl,
++ SPARC_BUILTIN_FPCMPLE32SHL, si_ftype_v2si_v2si_si);
++ def_builtin_const ("__builtin_vis_fpcmpgt32shl", CODE_FOR_fpcmpgt32sishl,
++ SPARC_BUILTIN_FPCMPGT32SHL, si_ftype_v2si_v2si_si);
++ def_builtin_const ("__builtin_vis_fpcmpeq32shl", CODE_FOR_fpcmpeq32sishl,
++ SPARC_BUILTIN_FPCMPEQ32SHL, si_ftype_v2si_v2si_si);
++ def_builtin_const ("__builtin_vis_fpcmpne32shl", CODE_FOR_fpcmpne32sishl,
++ SPARC_BUILTIN_FPCMPNE32SHL, si_ftype_v2si_v2si_si);
++
++
++ def_builtin_const ("__builtin_vis_fpcmpule8shl", CODE_FOR_fpcmpule8sishl,
++ SPARC_BUILTIN_FPCMPULE8SHL, si_ftype_v8qi_v8qi_si);
++ def_builtin_const ("__builtin_vis_fpcmpugt8shl", CODE_FOR_fpcmpugt8sishl,
++ SPARC_BUILTIN_FPCMPUGT8SHL, si_ftype_v8qi_v8qi_si);
++
++ def_builtin_const ("__builtin_vis_fpcmpule16shl", CODE_FOR_fpcmpule16sishl,
++ SPARC_BUILTIN_FPCMPULE16SHL, si_ftype_v4hi_v4hi_si);
++ def_builtin_const ("__builtin_vis_fpcmpugt16shl", CODE_FOR_fpcmpugt16sishl,
++ SPARC_BUILTIN_FPCMPUGT16SHL, si_ftype_v4hi_v4hi_si);
++
++ def_builtin_const ("__builtin_vis_fpcmpule32shl", CODE_FOR_fpcmpule32sishl,
++ SPARC_BUILTIN_FPCMPULE32SHL, si_ftype_v2si_v2si_si);
++ def_builtin_const ("__builtin_vis_fpcmpugt32shl", CODE_FOR_fpcmpugt32sishl,
++ SPARC_BUILTIN_FPCMPUGT32SHL, si_ftype_v2si_v2si_si);
++
++ def_builtin_const ("__builtin_vis_fpcmpde8shl", CODE_FOR_fpcmpde8sishl,
++ SPARC_BUILTIN_FPCMPDE8SHL, si_ftype_v8qi_v8qi_si);
++ def_builtin_const ("__builtin_vis_fpcmpde16shl", CODE_FOR_fpcmpde16sishl,
++ SPARC_BUILTIN_FPCMPDE16SHL, si_ftype_v4hi_v4hi_si);
++ def_builtin_const ("__builtin_vis_fpcmpde32shl", CODE_FOR_fpcmpde32sishl,
++ SPARC_BUILTIN_FPCMPDE32SHL, si_ftype_v2si_v2si_si);
++
++ def_builtin_const ("__builtin_vis_fpcmpur8shl", CODE_FOR_fpcmpur8sishl,
++ SPARC_BUILTIN_FPCMPUR8SHL, si_ftype_v8qi_v8qi_si);
++ def_builtin_const ("__builtin_vis_fpcmpur16shl", CODE_FOR_fpcmpur16sishl,
++ SPARC_BUILTIN_FPCMPUR16SHL, si_ftype_v4hi_v4hi_si);
++ def_builtin_const ("__builtin_vis_fpcmpur32shl", CODE_FOR_fpcmpur32sishl,
++ SPARC_BUILTIN_FPCMPUR32SHL, si_ftype_v2si_v2si_si);
++ }
++ }
+ }
+
+ /* Implement TARGET_BUILTIN_DECL hook. */
+@@ -10950,6 +11311,19 @@
+ insn_op = &insn_data[icode].operand[idx];
+ op[arg_count] = expand_normal (arg);
+
++ /* Some of the builtins require constant arguments. We check
++ for this here. */
++ if ((code >= SPARC_BUILTIN_FIRST_FPCMPSHL
++ && code <= SPARC_BUILTIN_LAST_FPCMPSHL
++ && arg_count == 3)
++ || (code >= SPARC_BUILTIN_FIRST_DICTUNPACK
++ && code <= SPARC_BUILTIN_LAST_DICTUNPACK
++ && arg_count == 2))
++ {
++ if (!check_constant_argument (icode, idx, op[arg_count]))
++ return const0_rtx;
++ }
++
+ if (code == SPARC_BUILTIN_LDFSR || code == SPARC_BUILTIN_STFSR)
+ {
+ if (!address_operand (op[arg_count], SImode))
+@@ -11460,7 +11834,8 @@
+ || sparc_cpu == PROCESSOR_NIAGARA2
+ || sparc_cpu == PROCESSOR_NIAGARA3
+ || sparc_cpu == PROCESSOR_NIAGARA4
+- || sparc_cpu == PROCESSOR_NIAGARA7)
++ || sparc_cpu == PROCESSOR_NIAGARA7
++ || sparc_cpu == PROCESSOR_M8)
+ return 12;
+
+ return 6;
Index: gcc/config/sparc/sparc.h
===================================================================
--- a/src/gcc/config/sparc/sparc.h (.../tags/gcc_7_1_0_release)
+++ b/src/gcc/config/sparc/sparc.h (.../branches/gcc-7-branch)
-@@ -423,10 +423,15 @@
+@@ -143,6 +143,7 @@
+ #define TARGET_CPU_niagara3 15
+ #define TARGET_CPU_niagara4 16
+ #define TARGET_CPU_niagara7 19
++#define TARGET_CPU_m8 20
+
+ #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
+ || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
+@@ -151,7 +152,8 @@
+ || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 \
+ || TARGET_CPU_DEFAULT == TARGET_CPU_niagara3 \
+ || TARGET_CPU_DEFAULT == TARGET_CPU_niagara4 \
+- || TARGET_CPU_DEFAULT == TARGET_CPU_niagara7
++ || TARGET_CPU_DEFAULT == TARGET_CPU_niagara7 \
++ || TARGET_CPU_DEFAULT == TARGET_CPU_m8
+
+ #define CPP_CPU32_DEFAULT_SPEC ""
+ #define ASM_CPU32_DEFAULT_SPEC ""
+@@ -192,6 +194,10 @@
+ #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
+ #define ASM_CPU64_DEFAULT_SPEC AS_NIAGARA7_FLAG
+ #endif
++#if TARGET_CPU_DEFAULT == TARGET_CPU_m8
++#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
++#define ASM_CPU64_DEFAULT_SPEC AS_M8_FLAG
++#endif
+
+ #else
+
+@@ -295,6 +301,7 @@
+ %{mcpu=niagara3:-D__sparc_v9__} \
+ %{mcpu=niagara4:-D__sparc_v9__} \
+ %{mcpu=niagara7:-D__sparc_v9__} \
++%{mcpu=m8:-D__sparc_v9__} \
+ %{!mcpu*:%(cpp_cpu_default)} \
+ "
+ #define CPP_ARCH32_SPEC ""
+@@ -347,6 +354,7 @@
+ %{mcpu=niagara3:%{!mv8plus:-Av9" AS_NIAGARA3_FLAG "}} \
+ %{mcpu=niagara4:%{!mv8plus:" AS_NIAGARA4_FLAG "}} \
+ %{mcpu=niagara7:%{!mv8plus:" AS_NIAGARA7_FLAG "}} \
++%{mcpu=m8:%{!mv8plus:" AS_M8_FLAG "}} \
+ %{!mcpu*:%(asm_cpu_default)} \
+ "
+
+@@ -423,10 +431,16 @@
#define WCHAR_TYPE_SIZE 16
/* Mask of all CPU selection flags. */
@@ -60748,12 +73300,24 @@ Index: gcc/config/sparc/sparc.h
+/* Mask of all CPU feature flags. */
+#define MASK_FEATURES \
+ (MASK_FPU + MASK_HARD_QUAD + MASK_VIS + MASK_VIS2 + MASK_VIS3 \
-+ + MASK_VIS4 + MASK_CBCOND + MASK_FMAF + MASK_POPC + MASK_SUBXC)
++ + MASK_VIS4 + MASK_CBCOND + MASK_FMAF + MASK_FSMULD \
++ + MASK_POPC + MASK_SUBXC)
+
/* TARGET_HARD_MUL: Use 32-bit hardware multiply instructions but not %y. */
#define TARGET_HARD_MUL \
(TARGET_SPARCLITE || TARGET_SPARCLET \
-@@ -1566,8 +1571,11 @@
+@@ -1034,6 +1048,10 @@
+ /* Local macro to handle the two v9 classes of FP regs. */
+ #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
+
++/* Predicate for 2-bit and 5-bit unsigned constants. */
++#define SPARC_IMM2_P(X) (((unsigned HOST_WIDE_INT) (X) & ~0x3) == 0)
++#define SPARC_IMM5_P(X) (((unsigned HOST_WIDE_INT) (X) & ~0x1F) == 0)
++
+ /* Predicates for 5-bit, 10-bit, 11-bit and 13-bit signed constants. */
+ #define SPARC_SIMM5_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x10 < 0x20)
+ #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
+@@ -1566,8 +1584,11 @@
and annulled branches insert 4 bubbles.
On Niagara-2 and Niagara-3, a not-taken branch costs 1 cycle whereas
@@ -60766,7 +73330,7 @@ Index: gcc/config/sparc/sparc.h
#define BRANCH_COST(speed_p, predictable_p) \
((sparc_cpu == PROCESSOR_V9 \
|| sparc_cpu == PROCESSOR_ULTRASPARC) \
-@@ -1579,7 +1587,11 @@
+@@ -1579,7 +1600,11 @@
: ((sparc_cpu == PROCESSOR_NIAGARA2 \
|| sparc_cpu == PROCESSOR_NIAGARA3) \
? 5 \
@@ -60779,11 +73343,24 @@ Index: gcc/config/sparc/sparc.h
/* Control the assembler format that we output. */
+@@ -1787,6 +1812,12 @@
+ #define AS_NIAGARA7_FLAG AS_NIAGARA4_FLAG
+ #endif
+
++#ifdef HAVE_AS_SPARC6
++#define AS_M8_FLAG "-xarch=sparc6"
++#else
++#define AS_M8_FLAG AS_NIAGARA7_FLAG
++#endif
++
+ #ifdef HAVE_AS_LEON
+ #define AS_LEON_FLAG "-Aleon"
+ #define AS_LEONV7_FLAG "-Aleon"
Index: gcc/config/sparc/sol2.h
===================================================================
--- a/src/gcc/config/sparc/sol2.h (.../tags/gcc_7_1_0_release)
+++ b/src/gcc/config/sparc/sol2.h (.../branches/gcc-7-branch)
-@@ -169,7 +169,7 @@
+@@ -169,11 +169,20 @@
#undef CPP_CPU64_DEFAULT_SPEC
#define CPP_CPU64_DEFAULT_SPEC ""
#undef ASM_CPU32_DEFAULT_SPEC
@@ -60792,6 +73369,121 @@ Index: gcc/config/sparc/sol2.h
#undef ASM_CPU64_DEFAULT_SPEC
#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG AS_NIAGARA7_FLAG
#endif
+
++#if TARGET_CPU_DEFAULT == TARGET_CPU_m8
++#undef CPP_CPU64_DEFAULT_SPEC
++#define CPP_CPU64_DEFAULT_SPEC ""
++#undef ASM_CPU32_DEFAULT_SPEC
++#define ASM_CPU32_DEFAULT_SPEC AS_SPARC32_FLAG AS_M8_FLAG
++#undef ASM_CPU64_DEFAULT_SPEC
++#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG AS_M8_FLAG
++#endif
++
+ #undef CPP_CPU_SPEC
+ #define CPP_CPU_SPEC "\
+ %{mcpu=sparclet|mcpu=tsc701:-D__sparclet__} \
+@@ -180,7 +189,7 @@
+ %{mcpu=sparclite|mcpu-f930|mcpu=f934:-D__sparclite__} \
+ %{mcpu=v8:" DEF_ARCH32_SPEC("-D__sparcv8") "} \
+ %{mcpu=supersparc:-D__supersparc__ " DEF_ARCH32_SPEC("-D__sparcv8") "} \
+-%{mcpu=v9|mcpu=ultrasparc|mcpu=ultrasparc3|mcpu=niagara|mcpu=niagara2|mcpu=niagara3|mcpu=niagara4|mcpu=niagara7:" DEF_ARCH32_SPEC("-D__sparcv8") "} \
++%{mcpu=v9|mcpu=ultrasparc|mcpu=ultrasparc3|mcpu=niagara|mcpu=niagara2|mcpu=niagara3|mcpu=niagara4|mcpu=niagara7|mcpu=m8:" DEF_ARCH32_SPEC("-D__sparcv8") "} \
+ %{!mcpu*:%(cpp_cpu_default)} \
+ "
+
+@@ -290,7 +299,8 @@
+ %{mcpu=niagara3:" DEF_ARCH32_SPEC("-xarch=v8plus" AS_NIAGARA3_FLAG) DEF_ARCH64_SPEC("-xarch=v9" AS_NIAGARA3_FLAG) "} \
+ %{mcpu=niagara4:" DEF_ARCH32_SPEC(AS_SPARC32_FLAG AS_NIAGARA4_FLAG) DEF_ARCH64_SPEC(AS_SPARC64_FLAG AS_NIAGARA4_FLAG) "} \
+ %{mcpu=niagara7:" DEF_ARCH32_SPEC(AS_SPARC32_FLAG AS_NIAGARA7_FLAG) DEF_ARCH64_SPEC(AS_SPARC64_FLAG AS_NIAGARA7_FLAG) "} \
+-%{!mcpu=niagara7:%{!mcpu=niagara4:%{!mcpu=niagara3:%{!mcpu=niagara2:%{!mcpu=niagara:%{!mcpu=ultrasparc3:%{!mcpu=ultrasparc:%{!mcpu=v9:%{mcpu*:" DEF_ARCH32_SPEC("-xarch=v8") DEF_ARCH64_SPEC("-xarch=v9") "}}}}}}}}} \
++%{mcpu=m8:" DEF_ARCH32_SPEC(AS_SPARC32_FLAG AS_M8_FLAG) DEF_ARCH64_SPEC(AS_SPARC64_FLAG AS_M8_FLAG) "} \
++%{!mcpu=m8:%{!mcpu=niagara7:%{!mcpu=niagara4:%{!mcpu=niagara3:%{!mcpu=niagara2:%{!mcpu=niagara:%{!mcpu=ultrasparc3:%{!mcpu=ultrasparc:%{!mcpu=v9:%{mcpu*:" DEF_ARCH32_SPEC("-xarch=v8") DEF_ARCH64_SPEC("-xarch=v9") "}}}}}}}}}} \
+ %{!mcpu*:%(asm_cpu_default)} \
+ "
+
+Index: gcc/config/sparc/constraints.md
+===================================================================
+--- a/src/gcc/config/sparc/constraints.md (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/sparc/constraints.md (.../branches/gcc-7-branch)
+@@ -19,7 +19,7 @@
+
+ ;;; Unused letters:
+ ;;; B
+-;;; a jkl q tuv xyz
++;;; a jkl uv xyz
+
+
+ ;; Register constraints
+@@ -58,6 +58,16 @@
+
+ ;; Integer constant constraints
+
++(define_constraint "q"
++ "Unsigned 2-bit integer constant"
++ (and (match_code "const_int")
++ (match_test "SPARC_IMM2_P (ival)")))
++
++(define_constraint "t"
++ "Unsigned 5-bit integer constant"
++ (and (match_code "const_int")
++ (match_test "SPARC_IMM5_P (ival)")))
++
+ (define_constraint "A"
+ "Signed 5-bit integer constant"
+ (and (match_code "const_int")
+Index: gcc/config/sparc/rtemself.h
+===================================================================
+--- a/src/gcc/config/sparc/rtemself.h (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/sparc/rtemself.h (.../branches/gcc-7-branch)
+@@ -2,22 +2,27 @@
+ Copyright (C) 1996-2017 Free Software Foundation, Inc.
+ Contributed by Joel Sherrill (joel at OARcorp.com).
+
+-This file is part of GCC.
++ This file is part of GCC.
+
+-GCC is free software; you can redistribute it and/or modify
+-it under the terms of the GNU General Public License as published by
+-the Free Software Foundation; either version 3, or (at your option)
+-any later version.
++ GCC is free software; you can redistribute it and/or modify it
++ under the terms of the GNU General Public License as published
++ by the Free Software Foundation; either version 3, or (at your
++ option) any later version.
+
+-GCC is distributed in the hope that it will be useful,
+-but WITHOUT ANY WARRANTY; without even the implied warranty of
+-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-GNU General Public License for more details.
++ GCC is distributed in the hope that it will be useful, but WITHOUT
++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
++ License for more details.
+
+-You should have received a copy of the GNU General Public License
+-along with GCC; see the file COPYING3. If not see
+-<http://www.gnu.org/licenses/>. */
++ Under Section 7 of GPL version 3, you are granted additional
++ permissions described in the GCC Runtime Library Exception, version
++ 3.1, as published by the Free Software Foundation.
+
++ You should have received a copy of the GNU General Public License and
++ a copy of the GCC Runtime Library Exception along with this program;
++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
++ <http://www.gnu.org/licenses/>. */
++
+ /* Target OS builtins. */
+ #undef TARGET_OS_CPP_BUILTINS
+ #define TARGET_OS_CPP_BUILTINS() \
+@@ -26,6 +31,8 @@
+ builtin_define ("__rtems__"); \
+ builtin_define ("__USE_INIT_FINI__"); \
+ builtin_assert ("system=rtems"); \
++ if (sparc_fix_b2bst) \
++ builtin_define ("__FIX_LEON3FT_B2BST"); \
+ } \
+ while (0)
+
Index: gcc/config/i386/i386.md
===================================================================
--- a/src/gcc/config/i386/i386.md (.../tags/gcc_7_1_0_release)
@@ -61063,7 +73755,149 @@ Index: gcc/config/i386/i386.md
&& optimize_function_for_speed_p (cfun)
&& reload_completed
&& (MEM_P (operands[1]) || TARGET_INTER_UNIT_MOVES_TO_VEC)
-@@ -12730,24 +12691,6 @@
+@@ -5471,7 +5432,7 @@
+ (define_expand "floatunsdisf2"
+ [(use (match_operand:SF 0 "register_operand"))
+ (use (match_operand:DI 1 "nonimmediate_operand"))]
+- "TARGET_64BIT && TARGET_SSE_MATH"
++ "TARGET_64BIT && TARGET_SSE && TARGET_SSE_MATH"
+ "x86_emit_floatuns (operands); DONE;")
+
+ (define_expand "floatunsdidf2"
+@@ -7512,21 +7473,15 @@
+ (match_operand:XF 2 "register_operand")))]
+ "TARGET_80387")
+
+-(define_expand "divdf3"
+- [(set (match_operand:DF 0 "register_operand")
+- (div:DF (match_operand:DF 1 "register_operand")
+- (match_operand:DF 2 "nonimmediate_operand")))]
+- "(TARGET_80387 && X87_ENABLE_ARITH (DFmode))
+- || (TARGET_SSE2 && TARGET_SSE_MATH)")
+-
+-(define_expand "divsf3"
+- [(set (match_operand:SF 0 "register_operand")
+- (div:SF (match_operand:SF 1 "register_operand")
+- (match_operand:SF 2 "nonimmediate_operand")))]
+- "(TARGET_80387 && X87_ENABLE_ARITH (SFmode))
+- || TARGET_SSE_MATH"
++(define_expand "div<mode>3"
++ [(set (match_operand:MODEF 0 "register_operand")
++ (div:MODEF (match_operand:MODEF 1 "register_operand")
++ (match_operand:MODEF 2 "nonimmediate_operand")))]
++ "(TARGET_80387 && X87_ENABLE_ARITH (<MODE>mode))
++ || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
+ {
+- if (TARGET_SSE_MATH
++ if (<MODE>mode == SFmode
++ && TARGET_SSE && TARGET_SSE_MATH
+ && TARGET_RECIP_DIV
+ && optimize_insn_for_speed_p ()
+ && flag_finite_math_only && !flag_trapping_math
+@@ -10705,10 +10660,15 @@
+ split_double_mode (<DWI>mode, &operands[0], 1, &operands[4], &operands[5]);
+ })
+
++(define_mode_attr rorx_immediate_operand
++ [(SI "const_0_to_31_operand")
++ (DI "const_0_to_63_operand")])
++
+ (define_insn "*bmi2_rorx<mode>3_1"
+ [(set (match_operand:SWI48 0 "register_operand" "=r")
+- (rotatert:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm")
+- (match_operand:QI 2 "immediate_operand" "<S>")))]
++ (rotatert:SWI48
++ (match_operand:SWI48 1 "nonimmediate_operand" "rm")
++ (match_operand:QI 2 "<rorx_immediate_operand>" "<S>")))]
+ "TARGET_BMI2"
+ "rorx\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "type" "rotatex")
+@@ -10751,7 +10711,7 @@
+ (define_split
+ [(set (match_operand:SWI48 0 "register_operand")
+ (rotate:SWI48 (match_operand:SWI48 1 "nonimmediate_operand")
+- (match_operand:QI 2 "immediate_operand")))
++ (match_operand:QI 2 "const_int_operand")))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_BMI2 && reload_completed"
+ [(set (match_dup 0)
+@@ -10765,7 +10725,7 @@
+ (define_split
+ [(set (match_operand:SWI48 0 "register_operand")
+ (rotatert:SWI48 (match_operand:SWI48 1 "nonimmediate_operand")
+- (match_operand:QI 2 "immediate_operand")))
++ (match_operand:QI 2 "const_int_operand")))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_BMI2 && reload_completed"
+ [(set (match_dup 0)
+@@ -10775,7 +10735,7 @@
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI
+ (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "rm")
+- (match_operand:QI 2 "immediate_operand" "I"))))]
++ (match_operand:QI 2 "const_0_to_31_operand" "I"))))]
+ "TARGET_64BIT && TARGET_BMI2"
+ "rorx\t{%2, %1, %k0|%k0, %1, %2}"
+ [(set_attr "type" "rotatex")
+@@ -10819,7 +10779,7 @@
+ [(set (match_operand:DI 0 "register_operand")
+ (zero_extend:DI
+ (rotate:SI (match_operand:SI 1 "nonimmediate_operand")
+- (match_operand:QI 2 "immediate_operand"))))
++ (match_operand:QI 2 "const_int_operand"))))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT && TARGET_BMI2 && reload_completed"
+ [(set (match_dup 0)
+@@ -10834,7 +10794,7 @@
+ [(set (match_operand:DI 0 "register_operand")
+ (zero_extend:DI
+ (rotatert:SI (match_operand:SI 1 "nonimmediate_operand")
+- (match_operand:QI 2 "immediate_operand"))))
++ (match_operand:QI 2 "const_int_operand"))))
+ (clobber (reg:CC FLAGS_REG))]
+ "TARGET_64BIT && TARGET_BMI2 && reload_completed"
+ [(set (match_dup 0)
+@@ -11721,7 +11681,8 @@
+ (zero_extend (match_dup 1)))]
+ "(peep2_reg_dead_p (3, operands[1])
+ || operands_match_p (operands[1], operands[3]))
+- && ! reg_overlap_mentioned_p (operands[3], operands[0])"
++ && ! reg_overlap_mentioned_p (operands[3], operands[0])
++ && peep2_regno_dead_p (0, FLAGS_REG)"
+ [(set (match_dup 4) (match_dup 0))
+ (set (strict_low_part (match_dup 5))
+ (match_dup 2))]
+@@ -11742,7 +11703,8 @@
+ "(peep2_reg_dead_p (3, operands[1])
+ || operands_match_p (operands[1], operands[3]))
+ && ! reg_overlap_mentioned_p (operands[3], operands[0])
+- && ! reg_set_p (operands[3], operands[4])"
++ && ! reg_set_p (operands[3], operands[4])
++ && peep2_regno_dead_p (0, FLAGS_REG)"
+ [(parallel [(set (match_dup 5) (match_dup 0))
+ (match_dup 4)])
+ (set (strict_low_part (match_dup 6))
+@@ -11764,7 +11726,8 @@
+ (and:SI (match_dup 3) (const_int 255)))
+ (clobber (reg:CC FLAGS_REG))])]
+ "REGNO (operands[1]) == REGNO (operands[3])
+- && ! reg_overlap_mentioned_p (operands[3], operands[0])"
++ && ! reg_overlap_mentioned_p (operands[3], operands[0])
++ && peep2_regno_dead_p (0, FLAGS_REG)"
+ [(set (match_dup 4) (match_dup 0))
+ (set (strict_low_part (match_dup 5))
+ (match_dup 2))]
+@@ -11786,7 +11749,8 @@
+ "(peep2_reg_dead_p (3, operands[1])
+ || operands_match_p (operands[1], operands[3]))
+ && ! reg_overlap_mentioned_p (operands[3], operands[0])
+- && ! reg_set_p (operands[3], operands[4])"
++ && ! reg_set_p (operands[3], operands[4])
++ && peep2_regno_dead_p (0, FLAGS_REG)"
+ [(parallel [(set (match_dup 5) (match_dup 0))
+ (match_dup 4)])
+ (set (strict_low_part (match_dup 6))
+@@ -12730,24 +12694,6 @@
(set_attr "znver1_decode" "vector")
(set_attr "mode" "<MODE>")])
@@ -61088,7 +73922,7 @@ Index: gcc/config/i386/i386.md
(define_insn_and_split "ctz<mode>2"
[(set (match_operand:SWI48 0 "register_operand" "=r")
(ctz:SWI48
-@@ -12867,24 +12810,6 @@
+@@ -12867,24 +12813,6 @@
operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)-1);
})
@@ -61113,6 +73947,42 @@ Index: gcc/config/i386/i386.md
(define_insn_and_split "clz<mode>2_lzcnt"
[(set (match_operand:SWI48 0 "register_operand" "=r")
(clz:SWI48
+@@ -14049,7 +13977,7 @@
+ [(set (match_operand:SF 0 "register_operand" "=x")
+ (unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "xm")]
+ UNSPEC_RCP))]
+- "TARGET_SSE_MATH"
++ "TARGET_SSE && TARGET_SSE_MATH"
+ "%vrcpss\t{%1, %d0|%d0, %1}"
+ [(set_attr "type" "sse")
+ (set_attr "atom_sse_attr" "rcp")
+@@ -14351,7 +14279,7 @@
+ [(set (match_operand:SF 0 "register_operand" "=x")
+ (unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "xm")]
+ UNSPEC_RSQRT))]
+- "TARGET_SSE_MATH"
++ "TARGET_SSE && TARGET_SSE_MATH"
+ "%vrsqrtss\t{%1, %d0|%d0, %1}"
+ [(set_attr "type" "sse")
+ (set_attr "atom_sse_attr" "rcp")
+@@ -14363,7 +14291,7 @@
+ [(set (match_operand:SF 0 "register_operand")
+ (unspec:SF [(match_operand:SF 1 "nonimmediate_operand")]
+ UNSPEC_RSQRT))]
+- "TARGET_SSE_MATH"
++ "TARGET_SSE && TARGET_SSE_MATH"
+ {
+ ix86_emit_swsqrtsf (operands[0], operands[1], SFmode, 1);
+ DONE;
+@@ -14392,7 +14320,7 @@
+ || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
+ {
+ if (<MODE>mode == SFmode
+- && TARGET_SSE_MATH
++ && TARGET_SSE && TARGET_SSE_MATH
+ && TARGET_RECIP_SQRT
+ && !optimize_function_for_size_p (cfun)
+ && flag_finite_math_only && !flag_trapping_math
Index: gcc/config/i386/mmx.md
===================================================================
--- a/src/gcc/config/i386/mmx.md (.../tags/gcc_7_1_0_release)
@@ -61174,6 +74044,50 @@ Index: gcc/config/i386/mmx.md
(ior (match_test "<MODE>mode == V2SFmode")
(not (match_test "TARGET_SSE2"))))
(const_string "V2SF")
+Index: gcc/config/i386/rtemself.h
+===================================================================
+--- a/src/gcc/config/i386/rtemself.h (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/i386/rtemself.h (.../branches/gcc-7-branch)
+@@ -2,22 +2,27 @@
+ Copyright (C) 1996-2017 Free Software Foundation, Inc.
+ Contributed by Joel Sherrill (joel at OARcorp.com).
+
+-This file is part of GCC.
++ This file is part of GCC.
+
+-GCC is free software; you can redistribute it and/or modify
+-it under the terms of the GNU General Public License as published by
+-the Free Software Foundation; either version 3, or (at your option)
+-any later version.
++ GCC is free software; you can redistribute it and/or modify it
++ under the terms of the GNU General Public License as published
++ by the Free Software Foundation; either version 3, or (at your
++ option) any later version.
+
+-GCC is distributed in the hope that it will be useful,
+-but WITHOUT ANY WARRANTY; without even the implied warranty of
+-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-GNU General Public License for more details.
++ GCC is distributed in the hope that it will be useful, but WITHOUT
++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
++ License for more details.
+
+-You should have received a copy of the GNU General Public License
+-along with GCC; see the file COPYING3. If not see
+-<http://www.gnu.org/licenses/>. */
++ Under Section 7 of GPL version 3, you are granted additional
++ permissions described in the GCC Runtime Library Exception, version
++ 3.1, as published by the Free Software Foundation.
+
++ You should have received a copy of the GNU General Public License and
++ a copy of the GCC Runtime Library Exception along with this program;
++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
++ <http://www.gnu.org/licenses/>. */
++
+ /* Specify predefined symbols in preprocessor. */
+
+ #define TARGET_OS_CPP_BUILTINS() \
Index: gcc/config/i386/cpuid.h
===================================================================
--- a/src/gcc/config/i386/cpuid.h (.../tags/gcc_7_1_0_release)
@@ -61209,11 +74123,103 @@ Index: gcc/config/i386/cpuid.h
return 0;
__cpuid_count (__leaf, __subleaf, *__eax, *__ebx, *__ecx, *__edx);
+Index: gcc/config/i386/adxintrin.h
+===================================================================
+--- a/src/gcc/config/i386/adxintrin.h (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/i386/adxintrin.h (.../branches/gcc-7-branch)
+@@ -33,7 +33,7 @@
+ _subborrow_u32 (unsigned char __CF, unsigned int __X,
+ unsigned int __Y, unsigned int *__P)
+ {
+- return __builtin_ia32_sbb_u32 (__CF, __Y, __X, __P);
++ return __builtin_ia32_sbb_u32 (__CF, __X, __Y, __P);
+ }
+
+ extern __inline unsigned char
+@@ -58,7 +58,7 @@
+ _subborrow_u64 (unsigned char __CF, unsigned long long __X,
+ unsigned long long __Y, unsigned long long *__P)
+ {
+- return __builtin_ia32_sbb_u64 (__CF, __Y, __X, __P);
++ return __builtin_ia32_sbb_u64 (__CF, __X, __Y, __P);
+ }
+
+ extern __inline unsigned char
Index: gcc/config/i386/sse.md
===================================================================
--- a/src/gcc/config/i386/sse.md (.../tags/gcc_7_1_0_release)
+++ b/src/gcc/config/i386/sse.md (.../branches/gcc-7-branch)
-@@ -13508,13 +13508,12 @@
+@@ -7324,13 +7324,13 @@
+ (define_insn "vec_extract_lo_<mode><mask_name>"
+ [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=<store_mask_constraint>,v")
+ (vec_select:<ssehalfvecmode>
+- (match_operand:V8FI 1 "nonimmediate_operand" "v,m")
++ (match_operand:V8FI 1 "<store_mask_predicate>" "v,<store_mask_constraint>")
+ (parallel [(const_int 0) (const_int 1)
+ (const_int 2) (const_int 3)])))]
+ "TARGET_AVX512F
+ && (<mask_applied> || !(MEM_P (operands[0]) && MEM_P (operands[1])))"
+ {
+- if (<mask_applied> || !TARGET_AVX512VL)
++ if (<mask_applied> || (!TARGET_AVX512VL && !MEM_P (operands[1])))
+ return "vextract<shuffletype>64x4\t{$0x0, %1, %0<mask_operand2>|%0<mask_operand2>, %1, 0x0}";
+ else
+ return "#";
+@@ -7480,7 +7480,8 @@
+ (define_insn "vec_extract_lo_<mode><mask_name>"
+ [(set (match_operand:<ssehalfvecmode> 0 "nonimmediate_operand" "=v,m")
+ (vec_select:<ssehalfvecmode>
+- (match_operand:V16FI 1 "nonimmediate_operand" "vm,v")
++ (match_operand:V16FI 1 "<store_mask_predicate>"
++ "<store_mask_constraint>,v")
+ (parallel [(const_int 0) (const_int 1)
+ (const_int 2) (const_int 3)
+ (const_int 4) (const_int 5)
+@@ -7487,7 +7488,7 @@
+ (const_int 6) (const_int 7)])))]
+ "TARGET_AVX512F
+ && <mask_mode512bit_condition>
+- && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
++ && (<mask_applied> || !(MEM_P (operands[0]) && MEM_P (operands[1])))"
+ {
+ if (<mask_applied>)
+ return "vextract<shuffletype>32x8\t{$0x0, %1, %0<mask_operand2>|%0<mask_operand2>, %1, 0x0}";
+@@ -7511,11 +7512,12 @@
+ (define_insn "vec_extract_lo_<mode><mask_name>"
+ [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=v,m")
+ (vec_select:<ssehalfvecmode>
+- (match_operand:VI8F_256 1 "nonimmediate_operand" "vm,v")
++ (match_operand:VI8F_256 1 "<store_mask_predicate>"
++ "<store_mask_constraint>,v")
+ (parallel [(const_int 0) (const_int 1)])))]
+ "TARGET_AVX
+ && <mask_avx512vl_condition> && <mask_avx512dq_condition>
+- && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
++ && (<mask_applied> || !(MEM_P (operands[0]) && MEM_P (operands[1])))"
+ {
+ if (<mask_applied>)
+ return "vextract<shuffletype>64x2\t{$0x0, %1, %0%{%3%}|%0%{%3%}, %1, 0x0}";
+@@ -7575,12 +7577,16 @@
+ "operands[1] = gen_lowpart (<ssehalfvecmode>mode, operands[1]);")
+
+ (define_insn "vec_extract_lo_<mode><mask_name>"
+- [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>" "=<store_mask_constraint>")
++ [(set (match_operand:<ssehalfvecmode> 0 "<store_mask_predicate>"
++ "=<store_mask_constraint>,v")
+ (vec_select:<ssehalfvecmode>
+- (match_operand:VI4F_256 1 "register_operand" "v")
++ (match_operand:VI4F_256 1 "<store_mask_predicate>"
++ "v,<store_mask_constraint>")
+ (parallel [(const_int 0) (const_int 1)
+ (const_int 2) (const_int 3)])))]
+- "TARGET_AVX && <mask_avx512vl_condition> && <mask_avx512dq_condition>"
++ "TARGET_AVX
++ && <mask_avx512vl_condition> && <mask_avx512dq_condition>
++ && (<mask_applied> || !(MEM_P (operands[0]) && MEM_P (operands[1])))"
+ {
+ if (<mask_applied>)
+ return "vextract<shuffletype>32x4\t{$0x0, %1, %0<mask_operand2>|%0<mask_operand2>, %1, 0x0}";
+@@ -13508,13 +13514,12 @@
"#")
(define_insn "*vec_extract<ssevecmodelower>_0"
@@ -61230,7 +74236,7 @@ Index: gcc/config/i386/sse.md
(define_insn "*vec_extractv2di_0_sse"
[(set (match_operand:DI 0 "nonimmediate_operand" "=v,m")
-@@ -13842,10 +13841,10 @@
+@@ -13842,10 +13847,10 @@
;; movd instead of movq is required to handle broken assemblers.
(define_insn "vec_concatv2di"
[(set (match_operand:V2DI 0 "register_operand"
@@ -61243,7 +74249,7 @@ Index: gcc/config/i386/sse.md
(match_operand:DI 2 "vector_move_operand"
"*rm,rm,rm,rm,C ,C ,C ,x,Yv,x,m,m")))]
"TARGET_SSE"
-@@ -15618,13 +15617,13 @@
+@@ -15618,13 +15623,13 @@
(set_attr "mode" "<MODE>")])
(define_expand "round<mode>2"
@@ -61260,7 +74266,7 @@ Index: gcc/config/i386/sse.md
UNSPEC_ROUND))]
"TARGET_ROUND && !flag_trapping_math"
{
-@@ -15644,11 +15643,11 @@
+@@ -15644,11 +15649,11 @@
vec_half = ix86_build_const_vector (<MODE>mode, true, half);
vec_half = force_reg (<MODE>mode, vec_half);
@@ -61276,7 +74282,7 @@ Index: gcc/config/i386/sse.md
})
(define_expand "round<mode>2_sfix"
-@@ -17105,12 +17104,12 @@
+@@ -17105,12 +17110,12 @@
(set_attr "mode" "TI")])
(define_insn "xop_vpermil2<mode>3"
@@ -61507,6 +74513,867 @@ Index: gcc/config/i386/i386.c
rtx_insn *seq = get_insns ();
end_sequence ();
emit_conversion_insns (seq, insn);
+@@ -5923,6 +5923,12 @@
+ opts->x_ix86_isa_flags
+ |= OPTION_MASK_ISA_LZCNT & ~opts->x_ix86_isa_flags_explicit;
+
++ /* Disable BMI, BMI2 and TBM instructions for -m16. */
++ if (TARGET_16BIT_P(opts->x_ix86_isa_flags))
++ opts->x_ix86_isa_flags
++ &= ~((OPTION_MASK_ISA_BMI | OPTION_MASK_ISA_BMI2 | OPTION_MASK_ISA_TBM)
++ & ~opts->x_ix86_isa_flags_explicit);
++
+ /* Validate -mpreferred-stack-boundary= value or default it to
+ PREFERRED_STACK_BOUNDARY_DEFAULT. */
+ ix86_preferred_stack_boundary = PREFERRED_STACK_BOUNDARY_DEFAULT;
+@@ -31069,11 +31075,12 @@
+ but are waiting to be built until a function is declared to use that
+ ISA. */
+ struct builtin_isa {
++ HOST_WIDE_INT isa; /* isa_flags this builtin is defined for */
++ HOST_WIDE_INT isa2; /* additional isa_flags this builtin is defined for */
+ const char *name; /* function name */
+ enum ix86_builtin_func_type tcode; /* type to use in the declaration */
+- HOST_WIDE_INT isa; /* isa_flags this builtin is defined for */
+- HOST_WIDE_INT isa2; /* additional isa_flags this builtin is defined for */
+- bool const_p; /* true if the declaration is constant */
++ unsigned char const_p:1; /* true if the declaration is constant */
++ unsigned char pure_p:1; /* true if the declaration has pure attribute */
+ bool leaf_p; /* true if the declaration has leaf attribute */
+ bool nothrow_p; /* true if the declaration has nothrow attribute */
+ bool set_and_not_built_p;
+@@ -31144,6 +31151,7 @@
+ ix86_builtins_isa[(int) code].leaf_p = false;
+ ix86_builtins_isa[(int) code].nothrow_p = false;
+ ix86_builtins_isa[(int) code].const_p = false;
++ ix86_builtins_isa[(int) code].pure_p = false;
+ ix86_builtins_isa[(int) code].set_and_not_built_p = true;
+ }
+ }
+@@ -31166,6 +31174,21 @@
+ return decl;
+ }
+
++/* Like def_builtin, but also marks the function decl "pure". */
++
++static inline tree
++def_builtin_pure (HOST_WIDE_INT mask, const char *name,
++ enum ix86_builtin_func_type tcode, enum ix86_builtins code)
++{
++ tree decl = def_builtin (mask, name, tcode, code);
++ if (decl)
++ DECL_PURE_P (decl) = 1;
++ else
++ ix86_builtins_isa[(int) code].pure_p = true;
++
++ return decl;
++}
++
+ /* Like def_builtin, but for additional isa2 flags. */
+
+ static inline tree
+@@ -31200,6 +31223,7 @@
+ ix86_builtins_isa[(int) code].leaf_p = false;
+ ix86_builtins_isa[(int) code].nothrow_p = false;
+ ix86_builtins_isa[(int) code].const_p = false;
++ ix86_builtins_isa[(int) code].pure_p = false;
+ ix86_builtins_isa[(int) code].set_and_not_built_p = true;
+ }
+
+@@ -31221,6 +31245,21 @@
+ return decl;
+ }
+
++/* Like def_builtin, but also marks the function decl "pure". */
++
++static inline tree
++def_builtin_pure2 (HOST_WIDE_INT mask, const char *name,
++ enum ix86_builtin_func_type tcode, enum ix86_builtins code)
++{
++ tree decl = def_builtin2 (mask, name, tcode, code);
++ if (decl)
++ DECL_PURE_P (decl) = 1;
++ else
++ ix86_builtins_isa[(int) code].pure_p = true;
++
++ return decl;
++}
++
+ /* Add any new builtin functions for a given ISA that may not have been
+ declared. This saves a bit of space compared to adding all of the
+ declarations to the tree, even if we didn't use them. */
+@@ -31259,6 +31298,8 @@
+ ix86_builtins[i] = decl;
+ if (ix86_builtins_isa[i].const_p)
+ TREE_READONLY (decl) = 1;
++ if (ix86_builtins_isa[i].pure_p)
++ DECL_PURE_P (decl) = 1;
+ if (ix86_builtins_isa[i].leaf_p)
+ DECL_ATTRIBUTES (decl) = build_tree_list (get_identifier ("leaf"),
+ NULL_TREE);
+@@ -31612,8 +31653,8 @@
+ /* SSE */
+ def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_ldmxcsr",
+ VOID_FTYPE_UNSIGNED, IX86_BUILTIN_LDMXCSR);
+- def_builtin (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr",
+- UNSIGNED_FTYPE_VOID, IX86_BUILTIN_STMXCSR);
++ def_builtin_pure (OPTION_MASK_ISA_SSE, "__builtin_ia32_stmxcsr",
++ UNSIGNED_FTYPE_VOID, IX86_BUILTIN_STMXCSR);
+
+ /* SSE or 3DNow!A */
+ def_builtin (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A,
+@@ -31663,134 +31704,134 @@
+ IX86_BUILTIN_RDRAND64_STEP);
+
+ /* AVX2 */
+- def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv2df",
+- V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
+- IX86_BUILTIN_GATHERSIV2DF);
++ def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv2df",
++ V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
++ IX86_BUILTIN_GATHERSIV2DF);
+
+- def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv4df",
+- V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
+- IX86_BUILTIN_GATHERSIV4DF);
++ def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv4df",
++ V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
++ IX86_BUILTIN_GATHERSIV4DF);
+
+- def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv2df",
+- V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
+- IX86_BUILTIN_GATHERDIV2DF);
++ def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv2df",
++ V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
++ IX86_BUILTIN_GATHERDIV2DF);
+
+- def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4df",
+- V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
+- IX86_BUILTIN_GATHERDIV4DF);
++ def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4df",
++ V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
++ IX86_BUILTIN_GATHERDIV4DF);
+
+- def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv4sf",
+- V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
+- IX86_BUILTIN_GATHERSIV4SF);
++ def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv4sf",
++ V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
++ IX86_BUILTIN_GATHERSIV4SF);
+
+- def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv8sf",
+- V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
+- IX86_BUILTIN_GATHERSIV8SF);
++ def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv8sf",
++ V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
++ IX86_BUILTIN_GATHERSIV8SF);
+
+- def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4sf",
+- V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
+- IX86_BUILTIN_GATHERDIV4SF);
++ def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4sf",
++ V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
++ IX86_BUILTIN_GATHERDIV4SF);
+
+- def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4sf256",
+- V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
+- IX86_BUILTIN_GATHERDIV8SF);
++ def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4sf256",
++ V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
++ IX86_BUILTIN_GATHERDIV8SF);
+
+- def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv2di",
+- V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
+- IX86_BUILTIN_GATHERSIV2DI);
++ def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv2di",
++ V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
++ IX86_BUILTIN_GATHERSIV2DI);
+
+- def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv4di",
+- V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
+- IX86_BUILTIN_GATHERSIV4DI);
++ def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv4di",
++ V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
++ IX86_BUILTIN_GATHERSIV4DI);
+
+- def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv2di",
+- V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
+- IX86_BUILTIN_GATHERDIV2DI);
++ def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv2di",
++ V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
++ IX86_BUILTIN_GATHERDIV2DI);
+
+- def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4di",
+- V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
+- IX86_BUILTIN_GATHERDIV4DI);
++ def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4di",
++ V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
++ IX86_BUILTIN_GATHERDIV4DI);
+
+- def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv4si",
+- V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
+- IX86_BUILTIN_GATHERSIV4SI);
++ def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv4si",
++ V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
++ IX86_BUILTIN_GATHERSIV4SI);
+
+- def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv8si",
+- V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
+- IX86_BUILTIN_GATHERSIV8SI);
++ def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv8si",
++ V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
++ IX86_BUILTIN_GATHERSIV8SI);
+
+- def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4si",
+- V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
+- IX86_BUILTIN_GATHERDIV4SI);
++ def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4si",
++ V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
++ IX86_BUILTIN_GATHERDIV4SI);
+
+- def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4si256",
+- V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
+- IX86_BUILTIN_GATHERDIV8SI);
++ def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4si256",
++ V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
++ IX86_BUILTIN_GATHERDIV8SI);
+
+- def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatheraltsiv4df ",
+- V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
+- IX86_BUILTIN_GATHERALTSIV4DF);
++ def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatheraltsiv4df ",
++ V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
++ IX86_BUILTIN_GATHERALTSIV4DF);
+
+- def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatheraltdiv4sf256 ",
+- V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
+- IX86_BUILTIN_GATHERALTDIV8SF);
++ def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatheraltdiv4sf256 ",
++ V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
++ IX86_BUILTIN_GATHERALTDIV8SF);
+
+- def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatheraltsiv4di ",
+- V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
+- IX86_BUILTIN_GATHERALTSIV4DI);
++ def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatheraltsiv4di ",
++ V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
++ IX86_BUILTIN_GATHERALTSIV4DI);
+
+- def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatheraltdiv4si256 ",
+- V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
+- IX86_BUILTIN_GATHERALTDIV8SI);
++ def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatheraltdiv4si256 ",
++ V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
++ IX86_BUILTIN_GATHERALTDIV8SI);
+
+ /* AVX512F */
+- def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gathersiv16sf",
+- V16SF_FTYPE_V16SF_PCVOID_V16SI_HI_INT,
+- IX86_BUILTIN_GATHER3SIV16SF);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gathersiv16sf",
++ V16SF_FTYPE_V16SF_PCVOID_V16SI_HI_INT,
++ IX86_BUILTIN_GATHER3SIV16SF);
+
+- def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gathersiv8df",
+- V8DF_FTYPE_V8DF_PCVOID_V8SI_QI_INT,
+- IX86_BUILTIN_GATHER3SIV8DF);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gathersiv8df",
++ V8DF_FTYPE_V8DF_PCVOID_V8SI_QI_INT,
++ IX86_BUILTIN_GATHER3SIV8DF);
+
+- def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatherdiv16sf",
+- V8SF_FTYPE_V8SF_PCVOID_V8DI_QI_INT,
+- IX86_BUILTIN_GATHER3DIV16SF);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatherdiv16sf",
++ V8SF_FTYPE_V8SF_PCVOID_V8DI_QI_INT,
++ IX86_BUILTIN_GATHER3DIV16SF);
+
+- def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatherdiv8df",
+- V8DF_FTYPE_V8DF_PCVOID_V8DI_QI_INT,
+- IX86_BUILTIN_GATHER3DIV8DF);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatherdiv8df",
++ V8DF_FTYPE_V8DF_PCVOID_V8DI_QI_INT,
++ IX86_BUILTIN_GATHER3DIV8DF);
+
+- def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gathersiv16si",
+- V16SI_FTYPE_V16SI_PCVOID_V16SI_HI_INT,
+- IX86_BUILTIN_GATHER3SIV16SI);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gathersiv16si",
++ V16SI_FTYPE_V16SI_PCVOID_V16SI_HI_INT,
++ IX86_BUILTIN_GATHER3SIV16SI);
+
+- def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gathersiv8di",
+- V8DI_FTYPE_V8DI_PCVOID_V8SI_QI_INT,
+- IX86_BUILTIN_GATHER3SIV8DI);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gathersiv8di",
++ V8DI_FTYPE_V8DI_PCVOID_V8SI_QI_INT,
++ IX86_BUILTIN_GATHER3SIV8DI);
+
+- def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatherdiv16si",
+- V8SI_FTYPE_V8SI_PCVOID_V8DI_QI_INT,
+- IX86_BUILTIN_GATHER3DIV16SI);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatherdiv16si",
++ V8SI_FTYPE_V8SI_PCVOID_V8DI_QI_INT,
++ IX86_BUILTIN_GATHER3DIV16SI);
+
+- def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatherdiv8di",
+- V8DI_FTYPE_V8DI_PCVOID_V8DI_QI_INT,
+- IX86_BUILTIN_GATHER3DIV8DI);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatherdiv8di",
++ V8DI_FTYPE_V8DI_PCVOID_V8DI_QI_INT,
++ IX86_BUILTIN_GATHER3DIV8DI);
+
+- def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatheraltsiv8df ",
+- V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
+- IX86_BUILTIN_GATHER3ALTSIV8DF);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatheraltsiv8df ",
++ V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
++ IX86_BUILTIN_GATHER3ALTSIV8DF);
+
+- def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatheraltdiv8sf ",
+- V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
+- IX86_BUILTIN_GATHER3ALTDIV16SF);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatheraltdiv8sf ",
++ V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
++ IX86_BUILTIN_GATHER3ALTDIV16SF);
+
+- def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatheraltsiv8di ",
+- V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
+- IX86_BUILTIN_GATHER3ALTSIV8DI);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatheraltsiv8di ",
++ V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
++ IX86_BUILTIN_GATHER3ALTSIV8DI);
+
+- def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatheraltdiv8si ",
+- V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
+- IX86_BUILTIN_GATHER3ALTDIV16SI);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatheraltdiv8si ",
++ V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
++ IX86_BUILTIN_GATHER3ALTDIV16SI);
+
+ def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_scattersiv16sf",
+ VOID_FTYPE_PVOID_HI_V16SI_V16SF_INT,
+@@ -31825,85 +31866,85 @@
+ IX86_BUILTIN_SCATTERDIV8DI);
+
+ /* AVX512VL */
+- def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv2df",
+- V2DF_FTYPE_V2DF_PCVOID_V4SI_QI_INT,
+- IX86_BUILTIN_GATHER3SIV2DF);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv2df",
++ V2DF_FTYPE_V2DF_PCVOID_V4SI_QI_INT,
++ IX86_BUILTIN_GATHER3SIV2DF);
+
+- def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv4df",
+- V4DF_FTYPE_V4DF_PCVOID_V4SI_QI_INT,
+- IX86_BUILTIN_GATHER3SIV4DF);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv4df",
++ V4DF_FTYPE_V4DF_PCVOID_V4SI_QI_INT,
++ IX86_BUILTIN_GATHER3SIV4DF);
+
+- def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div2df",
+- V2DF_FTYPE_V2DF_PCVOID_V2DI_QI_INT,
+- IX86_BUILTIN_GATHER3DIV2DF);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div2df",
++ V2DF_FTYPE_V2DF_PCVOID_V2DI_QI_INT,
++ IX86_BUILTIN_GATHER3DIV2DF);
+
+- def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div4df",
+- V4DF_FTYPE_V4DF_PCVOID_V4DI_QI_INT,
+- IX86_BUILTIN_GATHER3DIV4DF);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div4df",
++ V4DF_FTYPE_V4DF_PCVOID_V4DI_QI_INT,
++ IX86_BUILTIN_GATHER3DIV4DF);
+
+- def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv4sf",
+- V4SF_FTYPE_V4SF_PCVOID_V4SI_QI_INT,
+- IX86_BUILTIN_GATHER3SIV4SF);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv4sf",
++ V4SF_FTYPE_V4SF_PCVOID_V4SI_QI_INT,
++ IX86_BUILTIN_GATHER3SIV4SF);
+
+- def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv8sf",
+- V8SF_FTYPE_V8SF_PCVOID_V8SI_QI_INT,
+- IX86_BUILTIN_GATHER3SIV8SF);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv8sf",
++ V8SF_FTYPE_V8SF_PCVOID_V8SI_QI_INT,
++ IX86_BUILTIN_GATHER3SIV8SF);
+
+- def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div4sf",
+- V4SF_FTYPE_V4SF_PCVOID_V2DI_QI_INT,
+- IX86_BUILTIN_GATHER3DIV4SF);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div4sf",
++ V4SF_FTYPE_V4SF_PCVOID_V2DI_QI_INT,
++ IX86_BUILTIN_GATHER3DIV4SF);
+
+- def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div8sf",
+- V4SF_FTYPE_V4SF_PCVOID_V4DI_QI_INT,
+- IX86_BUILTIN_GATHER3DIV8SF);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div8sf",
++ V4SF_FTYPE_V4SF_PCVOID_V4DI_QI_INT,
++ IX86_BUILTIN_GATHER3DIV8SF);
+
+- def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv2di",
+- V2DI_FTYPE_V2DI_PCVOID_V4SI_QI_INT,
+- IX86_BUILTIN_GATHER3SIV2DI);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv2di",
++ V2DI_FTYPE_V2DI_PCVOID_V4SI_QI_INT,
++ IX86_BUILTIN_GATHER3SIV2DI);
+
+- def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv4di",
+- V4DI_FTYPE_V4DI_PCVOID_V4SI_QI_INT,
+- IX86_BUILTIN_GATHER3SIV4DI);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv4di",
++ V4DI_FTYPE_V4DI_PCVOID_V4SI_QI_INT,
++ IX86_BUILTIN_GATHER3SIV4DI);
+
+- def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div2di",
+- V2DI_FTYPE_V2DI_PCVOID_V2DI_QI_INT,
+- IX86_BUILTIN_GATHER3DIV2DI);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div2di",
++ V2DI_FTYPE_V2DI_PCVOID_V2DI_QI_INT,
++ IX86_BUILTIN_GATHER3DIV2DI);
+
+- def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div4di",
+- V4DI_FTYPE_V4DI_PCVOID_V4DI_QI_INT,
+- IX86_BUILTIN_GATHER3DIV4DI);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div4di",
++ V4DI_FTYPE_V4DI_PCVOID_V4DI_QI_INT,
++ IX86_BUILTIN_GATHER3DIV4DI);
+
+- def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv4si",
+- V4SI_FTYPE_V4SI_PCVOID_V4SI_QI_INT,
+- IX86_BUILTIN_GATHER3SIV4SI);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv4si",
++ V4SI_FTYPE_V4SI_PCVOID_V4SI_QI_INT,
++ IX86_BUILTIN_GATHER3SIV4SI);
+
+- def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv8si",
+- V8SI_FTYPE_V8SI_PCVOID_V8SI_QI_INT,
+- IX86_BUILTIN_GATHER3SIV8SI);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv8si",
++ V8SI_FTYPE_V8SI_PCVOID_V8SI_QI_INT,
++ IX86_BUILTIN_GATHER3SIV8SI);
+
+- def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div4si",
+- V4SI_FTYPE_V4SI_PCVOID_V2DI_QI_INT,
+- IX86_BUILTIN_GATHER3DIV4SI);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div4si",
++ V4SI_FTYPE_V4SI_PCVOID_V2DI_QI_INT,
++ IX86_BUILTIN_GATHER3DIV4SI);
+
+- def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div8si",
+- V4SI_FTYPE_V4SI_PCVOID_V4DI_QI_INT,
+- IX86_BUILTIN_GATHER3DIV8SI);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div8si",
++ V4SI_FTYPE_V4SI_PCVOID_V4DI_QI_INT,
++ IX86_BUILTIN_GATHER3DIV8SI);
+
+- def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3altsiv4df ",
+- V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_QI_INT,
+- IX86_BUILTIN_GATHER3ALTSIV4DF);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3altsiv4df ",
++ V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_QI_INT,
++ IX86_BUILTIN_GATHER3ALTSIV4DF);
+
+- def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3altdiv8sf ",
+- V8SF_FTYPE_V8SF_PCFLOAT_V4DI_QI_INT,
+- IX86_BUILTIN_GATHER3ALTDIV8SF);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3altdiv8sf ",
++ V8SF_FTYPE_V8SF_PCFLOAT_V4DI_QI_INT,
++ IX86_BUILTIN_GATHER3ALTDIV8SF);
+
+- def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3altsiv4di ",
+- V4DI_FTYPE_V4DI_PCINT64_V8SI_QI_INT,
+- IX86_BUILTIN_GATHER3ALTSIV4DI);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3altsiv4di ",
++ V4DI_FTYPE_V4DI_PCINT64_V8SI_QI_INT,
++ IX86_BUILTIN_GATHER3ALTSIV4DI);
+
+- def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3altdiv8si ",
+- V8SI_FTYPE_V8SI_PCINT_V4DI_QI_INT,
+- IX86_BUILTIN_GATHER3ALTDIV8SI);
++ def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3altdiv8si ",
++ V8SI_FTYPE_V8SI_PCINT_V4DI_QI_INT,
++ IX86_BUILTIN_GATHER3ALTDIV8SI);
+
+ def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scattersiv8sf",
+ VOID_FTYPE_PVOID_QI_V8SI_V8SF_INT,
+Index: gcc/config/sh/rtems.h
+===================================================================
+--- a/src/gcc/config/sh/rtems.h (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/sh/rtems.h (.../branches/gcc-7-branch)
+@@ -2,22 +2,27 @@
+ Copyright (C) 1997-2017 Free Software Foundation, Inc.
+ Contributed by Joel Sherrill (joel at OARcorp.com).
+
+-This file is part of GCC.
++ This file is part of GCC.
+
+-GCC is free software; you can redistribute it and/or modify
+-it under the terms of the GNU General Public License as published by
+-the Free Software Foundation; either version 3, or (at your option)
+-any later version.
++ GCC is free software; you can redistribute it and/or modify it
++ under the terms of the GNU General Public License as published
++ by the Free Software Foundation; either version 3, or (at your
++ option) any later version.
+
+-GCC is distributed in the hope that it will be useful,
+-but WITHOUT ANY WARRANTY; without even the implied warranty of
+-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-GNU General Public License for more details.
++ GCC is distributed in the hope that it will be useful, but WITHOUT
++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
++ License for more details.
+
+-You should have received a copy of the GNU General Public License
+-along with GCC; see the file COPYING3. If not see
+-<http://www.gnu.org/licenses/>. */
++ Under Section 7 of GPL version 3, you are granted additional
++ permissions described in the GCC Runtime Library Exception, version
++ 3.1, as published by the Free Software Foundation.
+
++ You should have received a copy of the GNU General Public License and
++ a copy of the GCC Runtime Library Exception along with this program;
++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
++ <http://www.gnu.org/licenses/>. */
++
+ /* Specify predefined symbols in preprocessor. */
+
+ #define TARGET_OS_CPP_BUILTINS() do { \
+Index: gcc/config/sh/rtemself.h
+===================================================================
+--- a/src/gcc/config/sh/rtemself.h (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/sh/rtemself.h (.../branches/gcc-7-branch)
+@@ -2,22 +2,27 @@
+ Copyright (C) 1997-2017 Free Software Foundation, Inc.
+ Contributed by Joel Sherrill (joel at OARcorp.com).
+
+-This file is part of GCC.
++ This file is part of GCC.
+
+-GCC is free software; you can redistribute it and/or modify
+-it under the terms of the GNU General Public License as published by
+-the Free Software Foundation; either version 3, or (at your option)
+-any later version.
++ GCC is free software; you can redistribute it and/or modify it
++ under the terms of the GNU General Public License as published
++ by the Free Software Foundation; either version 3, or (at your
++ option) any later version.
+
+-GCC is distributed in the hope that it will be useful,
+-but WITHOUT ANY WARRANTY; without even the implied warranty of
+-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-GNU General Public License for more details.
++ GCC is distributed in the hope that it will be useful, but WITHOUT
++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
++ License for more details.
+
+-You should have received a copy of the GNU General Public License
+-along with GCC; see the file COPYING3. If not see
+-<http://www.gnu.org/licenses/>. */
++ Under Section 7 of GPL version 3, you are granted additional
++ permissions described in the GCC Runtime Library Exception, version
++ 3.1, as published by the Free Software Foundation.
+
++ You should have received a copy of the GNU General Public License and
++ a copy of the GCC Runtime Library Exception along with this program;
++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
++ <http://www.gnu.org/licenses/>. */
++
+ /* Specify predefined symbols in preprocessor. */
+
+ #define TARGET_OS_CPP_BUILTINS() do { \
+Index: gcc/config/microblaze/rtems.h
+===================================================================
+--- a/src/gcc/config/microblaze/rtems.h (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/microblaze/rtems.h (.../branches/gcc-7-branch)
+@@ -1,22 +1,27 @@
+ /* Definitions for rtems targeting a microblaze using ELF.
+ Copyright (C) 2012-2017 Free Software Foundation, Inc.
+
+-This file is part of GCC.
++ This file is part of GCC.
+
+-GCC is free software; you can redistribute it and/or modify
+-it under the terms of the GNU General Public License as published by
+-the Free Software Foundation; either version 3, or (at your option)
+-any later version.
++ GCC is free software; you can redistribute it and/or modify it
++ under the terms of the GNU General Public License as published
++ by the Free Software Foundation; either version 3, or (at your
++ option) any later version.
+
+-GCC is distributed in the hope that it will be useful,
+-but WITHOUT ANY WARRANTY; without even the implied warranty of
+-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-GNU General Public License for more details.
++ GCC is distributed in the hope that it will be useful, but WITHOUT
++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
++ License for more details.
+
+-You should have received a copy of the GNU General Public License
+-along with GCC; see the file COPYING3. If not see
+-<http://www.gnu.org/licenses/>. */
++ Under Section 7 of GPL version 3, you are granted additional
++ permissions described in the GCC Runtime Library Exception, version
++ 3.1, as published by the Free Software Foundation.
+
++ You should have received a copy of the GNU General Public License and
++ a copy of the GCC Runtime Library Exception along with this program;
++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
++ <http://www.gnu.org/licenses/>. */
++
+ /* Specify predefined symbols in preprocessor. */
+
+ #define TARGET_OS_CPP_BUILTINS() do { \
+Index: gcc/config/avr/avr.c
+===================================================================
+--- a/src/gcc/config/avr/avr.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/avr/avr.c (.../branches/gcc-7-branch)
+@@ -553,9 +553,9 @@
+ HOST_WIDE_INT hig_idx = low_idx + num_idx;
+
+ // Maximum ranges of (un)signed QImode resp. HImode.
+- int imin = QImode == mode ? INT8_MIN : INT16_MIN;
+- int imax = QImode == mode ? INT8_MAX : INT16_MAX;
+- unsigned umax = QImode == mode ? UINT8_MAX : UINT16_MAX;
++ unsigned umax = QImode == mode ? 0xff : 0xffff;
++ int imax = QImode == mode ? 0x7f : 0x7fff;
++ int imin = -imax - 1;
+
+ // Testing the case range and whether it fits into the range of the
+ // (un)signed mode. This test should actually always pass because it
+@@ -1062,12 +1062,6 @@
+
+ name = default_strip_name_encoding (name);
+
+- /* Silently ignore 'signal' if 'interrupt' is present. AVR-LibC startet
+- using this when it switched from SIGNAL and INTERRUPT to ISR. */
+-
+- if (cfun->machine->is_interrupt)
+- cfun->machine->is_signal = 0;
+-
+ /* Interrupt handlers must be void __vector (void) functions. */
+
+ if (args && TREE_CODE (TREE_VALUE (args)) != VOID_TYPE)
+@@ -1076,6 +1070,13 @@
+ if (TREE_CODE (ret) != VOID_TYPE)
+ error_at (loc, "%qs function cannot return a value", isr);
+
++#if defined WITH_AVRLIBC
++ /* Silently ignore 'signal' if 'interrupt' is present. AVR-LibC startet
++ using this when it switched from SIGNAL and INTERRUPT to ISR. */
++
++ if (cfun->machine->is_interrupt)
++ cfun->machine->is_signal = 0;
++
+ /* If the function has the 'signal' or 'interrupt' attribute, ensure
+ that the name of the function is "__vector_NN" so as to catch
+ when the user misspells the vector name. */
+@@ -1082,9 +1083,24 @@
+
+ if (!STR_PREFIX_P (name, "__vector"))
+ warning_at (loc, OPT_Wmisspelled_isr, "%qs appears to be a misspelled "
+- "%s handler, missing __vector prefix", name, isr);
++ "%qs handler, missing %<__vector%> prefix", name, isr);
++#endif // AVR-LibC naming conventions
+ }
+
++#if defined WITH_AVRLIBC
++ // Common problem is using "ISR" without first including avr/interrupt.h.
++ const char *name = IDENTIFIER_POINTER (DECL_NAME (decl));
++ name = default_strip_name_encoding (name);
++ if (0 == strcmp ("ISR", name)
++ || 0 == strcmp ("INTERRUPT", name)
++ || 0 == strcmp ("SIGNAL", name))
++ {
++ warning_at (loc, OPT_Wmisspelled_isr, "%qs is a reserved indentifier"
++ " in AVR-LibC. Consider %<#include <avr/interrupt.h>%>"
++ " before using the %qs macro", name, name);
++ }
++#endif // AVR-LibC naming conventions
++
+ /* Don't print the above diagnostics more than once. */
+
+ cfun->machine->attributes_checked_p = 1;
+@@ -3820,7 +3836,7 @@
+ if (CONSTANT_ADDRESS_P (x))
+ {
+ int n_words = AVR_TINY ? 1 : 2;
+- return optimize > 0 && io_address_operand (x, QImode)
++ return io_address_operand (x, QImode)
+ ? avr_asm_len ("in %0,%i1", op, plen, -1)
+ : avr_asm_len ("lds %0,%m1", op, plen, -n_words);
+ }
+@@ -4088,7 +4104,7 @@
+ else if (CONSTANT_ADDRESS_P (base))
+ {
+ int n_words = AVR_TINY ? 2 : 4;
+- return optimize > 0 && io_address_operand (base, HImode)
++ return io_address_operand (base, HImode)
+ ? avr_asm_len ("in %A0,%i1" CR_TAB
+ "in %B0,%i1+1", op, plen, -2)
+
+@@ -5215,7 +5231,7 @@
+ if (CONSTANT_ADDRESS_P (x))
+ {
+ int n_words = AVR_TINY ? 1 : 2;
+- return optimize > 0 && io_address_operand (x, QImode)
++ return io_address_operand (x, QImode)
+ ? avr_asm_len ("out %i0,%1", op, plen, -1)
+ : avr_asm_len ("sts %m0,%1", op, plen, -n_words);
+ }
+@@ -5291,13 +5307,12 @@
+
+ if (CONSTANT_ADDRESS_P (base))
+ {
+- int n_words = AVR_TINY ? 2 : 4;
+- return optimize > 0 && io_address_operand (base, HImode)
++ return io_address_operand (base, HImode)
+ ? avr_asm_len ("out %i0,%A1" CR_TAB
+ "out %i0+1,%B1", op, plen, -2)
+
+ : avr_asm_len ("sts %m0,%A1" CR_TAB
+- "sts %m0+1,%B1", op, plen, -n_words);
++ "sts %m0+1,%B1", op, plen, -4);
+ }
+
+ if (reg_base > 0)
+@@ -5477,7 +5492,7 @@
+ if (CONSTANT_ADDRESS_P (base))
+ {
+ int n_words = AVR_TINY ? 2 : 4;
+- return optimize > 0 && io_address_operand (base, HImode)
++ return io_address_operand (base, HImode)
+ ? avr_asm_len ("out %i0+1,%B1" CR_TAB
+ "out %i0,%A1", op, plen, -2)
+
+@@ -10125,18 +10140,26 @@
+
+ if (new_decl_p
+ && decl && DECL_P (decl)
+- && NULL_TREE == DECL_INITIAL (decl)
+ && !DECL_EXTERNAL (decl)
+ && avr_progmem_p (decl, DECL_ATTRIBUTES (decl)))
+ {
+- // Don't warn for (implicit) aliases like in PR80462.
+- tree asmname = DECL_ASSEMBLER_NAME (decl);
+- varpool_node *node = varpool_node::get_for_asmname (asmname);
+- bool alias_p = node && node->alias;
++ if (!TREE_READONLY (decl))
++ {
++ // This might happen with C++ if stuff needs constructing.
++ error ("variable %q+D with dynamic initialization put "
++ "into program memory area", decl);
++ }
++ else if (NULL_TREE == DECL_INITIAL (decl))
++ {
++ // Don't warn for (implicit) aliases like in PR80462.
++ tree asmname = DECL_ASSEMBLER_NAME (decl);
++ varpool_node *node = varpool_node::get_for_asmname (asmname);
++ bool alias_p = node && node->alias;
+
+- if (!alias_p)
+- warning (OPT_Wuninitialized, "uninitialized variable %q+D put into "
+- "program memory area", decl);
++ if (!alias_p)
++ warning (OPT_Wuninitialized, "uninitialized variable %q+D put "
++ "into program memory area", decl);
++ }
+ }
+
+ default_encode_section_info (decl, rtl, new_decl_p);
+@@ -10434,6 +10457,33 @@
+ }
+
+
++/* Cost for mul highpart. X is a LSHIFTRT, i.e. the outer TRUNCATE is
++ already stripped off. */
++
++static int
++avr_mul_highpart_cost (rtx x, int)
++{
++ if (AVR_HAVE_MUL
++ && LSHIFTRT == GET_CODE (x)
++ && MULT == GET_CODE (XEXP (x, 0))
++ && CONST_INT_P (XEXP (x, 1)))
++ {
++ // This is the wider mode.
++ machine_mode mode = GET_MODE (x);
++
++ // The middle-end might still have PR81444, i.e. it is calling the cost
++ // functions with strange modes. Fix this now by also considering
++ // PSImode (should actually be SImode instead).
++ if (HImode == mode || PSImode == mode || SImode == mode)
++ {
++ return COSTS_N_INSNS (2);
++ }
++ }
++
++ return 10000;
++}
++
++
+ /* Mutually recursive subroutine of avr_rtx_cost for calculating the
+ cost of an RTX operand given its context. X is the rtx of the
+ operand, MODE is its mode, and OUTER is the rtx_code of this
+@@ -10473,7 +10523,7 @@
+ In either case, *TOTAL contains the cost result. */
+
+ static bool
+-avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
++avr_rtx_costs_1 (rtx x, machine_mode mode, int outer_code,
+ int opno ATTRIBUTE_UNUSED, int *total, bool speed)
+ {
+ enum rtx_code code = GET_CODE (x);
+@@ -11127,6 +11177,12 @@
+ return true;
+
+ case LSHIFTRT:
++ if (outer_code == TRUNCATE)
++ {
++ *total = avr_mul_highpart_cost (x, speed);
++ return true;
++ }
++
+ switch (mode)
+ {
+ case QImode:
+@@ -11304,16 +11360,10 @@
+ return true;
+
+ case TRUNCATE:
+- if (AVR_HAVE_MUL
+- && LSHIFTRT == GET_CODE (XEXP (x, 0))
+- && MULT == GET_CODE (XEXP (XEXP (x, 0), 0))
+- && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
++ if (LSHIFTRT == GET_CODE (XEXP (x, 0)))
+ {
+- if (QImode == mode || HImode == mode)
+- {
+- *total = COSTS_N_INSNS (2);
+- return true;
+- }
++ *total = avr_mul_highpart_cost (XEXP (x, 0), speed);
++ return true;
+ }
+ break;
+
+@@ -11361,8 +11411,7 @@
+ }
+ else if (CONSTANT_ADDRESS_P (x))
+ {
+- if (optimize > 0
+- && io_address_operand (x, QImode))
++ if (io_address_operand (x, QImode))
+ cost = 2;
+
+ if (AVR_TINY
Index: gcc/config/xtensa/xtensa.c
===================================================================
--- a/src/gcc/config/xtensa/xtensa.c (.../tags/gcc_7_1_0_release)
@@ -61557,6 +75424,185 @@ Index: gcc/config/xtensa/xtensa.c
else
output_addr_const (file, x);
}
+Index: gcc/config/lm32/rtems.h
+===================================================================
+--- a/src/gcc/config/lm32/rtems.h (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/lm32/rtems.h (.../branches/gcc-7-branch)
+@@ -1,22 +1,27 @@
+ /* Definitions for rtems targeting a lm32 using ELF.
+ Copyright (C) 2009-2017 Free Software Foundation, Inc.
+
+-This file is part of GCC.
++ This file is part of GCC.
+
+-GCC is free software; you can redistribute it and/or modify
+-it under the terms of the GNU General Public License as published by
+-the Free Software Foundation; either version 3, or (at your option)
+-any later version.
++ GCC is free software; you can redistribute it and/or modify it
++ under the terms of the GNU General Public License as published
++ by the Free Software Foundation; either version 3, or (at your
++ option) any later version.
+
+-GCC is distributed in the hope that it will be useful,
+-but WITHOUT ANY WARRANTY; without even the implied warranty of
+-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-GNU General Public License for more details.
++ GCC is distributed in the hope that it will be useful, but WITHOUT
++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
++ License for more details.
+
+-You should have received a copy of the GNU General Public License
+-along with GCC; see the file COPYING3. If not see
+-<http://www.gnu.org/licenses/>. */
++ Under Section 7 of GPL version 3, you are granted additional
++ permissions described in the GCC Runtime Library Exception, version
++ 3.1, as published by the Free Software Foundation.
+
++ You should have received a copy of the GNU General Public License and
++ a copy of the GCC Runtime Library Exception along with this program;
++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
++ <http://www.gnu.org/licenses/>. */
++
+ /* Target OS builtins. */
+ #undef TARGET_OS_CPP_BUILTINS
+ #define TARGET_OS_CPP_BUILTINS() \
+Index: gcc/config/moxie/rtems.h
+===================================================================
+--- a/src/gcc/config/moxie/rtems.h (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/moxie/rtems.h (.../branches/gcc-7-branch)
+@@ -2,22 +2,27 @@
+ Copyright (C) 2010-2017 Free Software Foundation, Inc.
+ Contributed by Anthony Green (green at moxielogic.com)
+
+-This file is part of GCC.
++ This file is part of GCC.
+
+-GCC is free software; you can redistribute it and/or modify
+-it under the terms of the GNU General Public License as published by
+-the Free Software Foundation; either version 3, or (at your option)
+-any later version.
++ GCC is free software; you can redistribute it and/or modify it
++ under the terms of the GNU General Public License as published
++ by the Free Software Foundation; either version 3, or (at your
++ option) any later version.
+
+-GCC is distributed in the hope that it will be useful,
+-but WITHOUT ANY WARRANTY; without even the implied warranty of
+-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-GNU General Public License for more details.
++ GCC is distributed in the hope that it will be useful, but WITHOUT
++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
++ License for more details.
+
+-You should have received a copy of the GNU General Public License
+-along with GCC; see the file COPYING3. If not see
+-<http://www.gnu.org/licenses/>. */
++ Under Section 7 of GPL version 3, you are granted additional
++ permissions described in the GCC Runtime Library Exception, version
++ 3.1, as published by the Free Software Foundation.
+
++ You should have received a copy of the GNU General Public License and
++ a copy of the GCC Runtime Library Exception along with this program;
++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
++ <http://www.gnu.org/licenses/>. */
++
+ /* Target OS preprocessor built-ins. */
+ #define TARGET_OS_CPP_BUILTINS() \
+ do \
+Index: gcc/config/nios2/rtems.h
+===================================================================
+--- a/src/gcc/config/nios2/rtems.h (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/nios2/rtems.h (.../branches/gcc-7-branch)
+@@ -3,22 +3,27 @@
+
+ Contributed by Chris Johns (chrisj at rtems.org).
+
+-This file is part of GCC.
++ This file is part of GCC.
+
+-GCC is free software; you can redistribute it and/or modify
+-it under the terms of the GNU General Public License as published by
+-the Free Software Foundation; either version 3, or (at your option)
+-any later version.
++ GCC is free software; you can redistribute it and/or modify it
++ under the terms of the GNU General Public License as published
++ by the Free Software Foundation; either version 3, or (at your
++ option) any later version.
+
+-GCC is distributed in the hope that it will be useful,
+-but WITHOUT ANY WARRANTY; without even the implied warranty of
+-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-GNU General Public License for more details.
++ GCC is distributed in the hope that it will be useful, but WITHOUT
++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
++ License for more details.
+
+-You should have received a copy of the GNU General Public License
+-along with GCC; see the file COPYING3. If not see
+-<http://www.gnu.org/licenses/>. */
++ Under Section 7 of GPL version 3, you are granted additional
++ permissions described in the GCC Runtime Library Exception, version
++ 3.1, as published by the Free Software Foundation.
+
++ You should have received a copy of the GNU General Public License and
++ a copy of the GCC Runtime Library Exception along with this program;
++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
++ <http://www.gnu.org/licenses/>. */
++
+ /* Specify predefined symbols in preprocessor. */
+ #define TARGET_OS_CPP_BUILTINS() \
+ do { \
+Index: gcc/config/rtems.h
+===================================================================
+--- a/src/gcc/config/rtems.h (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/rtems.h (.../branches/gcc-7-branch)
+@@ -1,26 +1,26 @@
+ /* Configuration common to all targets running RTEMS.
+ Copyright (C) 2000-2017 Free Software Foundation, Inc.
+
+-This file is part of GCC.
++ This file is part of GCC.
+
+-GCC is free software; you can redistribute it and/or modify
+-it under the terms of the GNU General Public License as published by
+-the Free Software Foundation; either version 3, or (at your option)
+-any later version.
++ GCC is free software; you can redistribute it and/or modify it
++ under the terms of the GNU General Public License as published
++ by the Free Software Foundation; either version 3, or (at your
++ option) any later version.
+
+-GCC is distributed in the hope that it will be useful,
+-but WITHOUT ANY WARRANTY; without even the implied warranty of
+-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-GNU General Public License for more details.
++ GCC is distributed in the hope that it will be useful, but WITHOUT
++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
++ License for more details.
+
+-Under Section 7 of GPL version 3, you are granted additional
+-permissions described in the GCC Runtime Library Exception, version
+-3.1, as published by the Free Software Foundation.
++ Under Section 7 of GPL version 3, you are granted additional
++ permissions described in the GCC Runtime Library Exception, version
++ 3.1, as published by the Free Software Foundation.
+
+-You should have received a copy of the GNU General Public License and
+-a copy of the GCC Runtime Library Exception along with this program;
+-see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+-<http://www.gnu.org/licenses/>. */
++ You should have received a copy of the GNU General Public License and
++ a copy of the GCC Runtime Library Exception along with this program;
++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
++ <http://www.gnu.org/licenses/>. */
+
+ /* The system headers under RTEMS are C++-aware. */
+ #undef NO_IMPLICIT_EXTERN_C
Index: gcc/config/m68k/m68k.md
===================================================================
--- a/src/gcc/config/m68k/m68k.md (.../tags/gcc_7_1_0_release)
@@ -61588,6 +75634,51 @@ Index: gcc/config/m68k/m68k.md
(and:SI (rotate:SI (const_int -2)
(and:SI (match_operand:SI 1 "register_operand" "d")
(const_int 31)))
+Index: gcc/config/m68k/rtemself.h
+===================================================================
+--- a/src/gcc/config/m68k/rtemself.h (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/m68k/rtemself.h (.../branches/gcc-7-branch)
+@@ -3,23 +3,28 @@
+ Copyright (C) 2007-2017 Free Software Foundation, Inc.
+ Contributed by Charles-Antoine Gauthier (charles.gauthier at nrc.ca).
+
+-This file is part of GCC.
++ This file is part of GCC.
+
+-GCC is free software; you can redistribute it and/or modify
+-it under the terms of the GNU General Public License as published by
+-the Free Software Foundation; either version 3, or (at your option)
+-any later version.
++ GCC is free software; you can redistribute it and/or modify it
++ under the terms of the GNU General Public License as published
++ by the Free Software Foundation; either version 3, or (at your
++ option) any later version.
+
+-GCC is distributed in the hope that it will be useful,
+-but WITHOUT ANY WARRANTY; without even the implied warranty of
+-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-GNU General Public License for more details.
++ GCC is distributed in the hope that it will be useful, but WITHOUT
++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
++ License for more details.
+
+-You should have received a copy of the GNU General Public License
+-along with GCC; see the file COPYING3. If not see
+-<http://www.gnu.org/licenses/>. */
++ Under Section 7 of GPL version 3, you are granted additional
++ permissions described in the GCC Runtime Library Exception, version
++ 3.1, as published by the Free Software Foundation.
+
++ You should have received a copy of the GNU General Public License and
++ a copy of the GCC Runtime Library Exception along with this program;
++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
++ <http://www.gnu.org/licenses/>. */
+
++
+ /* Target OS builtins. */
+ #undef TARGET_OS_CPP_BUILTINS /* Defined in m68kemb.h. */
+ #define TARGET_OS_CPP_BUILTINS() \
Index: gcc/config/aarch64/cortex-a57-fma-steering.c
===================================================================
--- a/src/gcc/config/aarch64/cortex-a57-fma-steering.c (.../tags/gcc_7_1_0_release)
@@ -61604,6 +75695,64 @@ Index: gcc/config/aarch64/cortex-a57-fma-steering.c
}
/* Dump information about the forest FOREST. */
+@@ -973,10 +973,17 @@
+ break;
+ }
+
+- /* We didn't find a chain with a def for this instruction. */
+- gcc_assert (i < dest_op_info->n_chains);
+-
+- this->analyze_fma_fmul_insn (forest, chain, head);
++ /* Due to implementation of regrename, dest register can slip away
++ from regrename's analysis. As a result, there is no chain for
++ the destination register of insn. We simply skip the insn even
++ it is a fmul/fmac instruction. This can happen when the dest
++ register is also a source register of insn and one of the below
++ conditions is satisfied:
++ 1) the source reg is setup in larger mode than this insn;
++ 2) the source reg is uninitialized;
++ 3) the source reg is passed in as parameter. */
++ if (i < dest_op_info->n_chains)
++ this->analyze_fma_fmul_insn (forest, chain, head);
+ }
+ }
+ free (bb_dfs_preorder);
+Index: gcc/config/aarch64/rtems.h
+===================================================================
+--- a/src/gcc/config/aarch64/rtems.h (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/aarch64/rtems.h (.../branches/gcc-7-branch)
+@@ -1,20 +1,25 @@
+ /* Definitions for RTEMS based AARCH64 system.
+ Copyright (C) 2016-2017 Free Software Foundation, Inc.
+-
++
+ This file is part of GCC.
+-
++
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 3, or (at your
+ option) any later version.
+-
++
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+-
+- You should have received a copy of the GNU General Public License
+- along with GCC; see the file COPYING3. If not see
++
++ Under Section 7 of GPL version 3, you are granted additional
++ permissions described in the GCC Runtime Library Exception, version
++ 3.1, as published by the Free Software Foundation.
++
++ You should have received a copy of the GNU General Public License and
++ a copy of the GCC Runtime Library Exception along with this program;
++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+ #define HAS_INIT_SECTION
Index: gcc/config/aarch64/aarch64-option-extensions.def
===================================================================
--- a/src/gcc/config/aarch64/aarch64-option-extensions.def (.../tags/gcc_7_1_0_release)
@@ -61740,6 +75889,19 @@ Index: gcc/config/aarch64/aarch64-cost-tables.h
-
#endif
-
+Index: gcc/config/aarch64/aarch64.c
+===================================================================
+--- a/src/gcc/config/aarch64/aarch64.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/aarch64/aarch64.c (.../branches/gcc-7-branch)
+@@ -9935,7 +9935,7 @@
+ /* This is alright even in PIC code as the constant
+ pool reference is always PC relative and within
+ the same translation unit. */
+- if (CONSTANT_POOL_ADDRESS_P (x))
++ if (!aarch64_pcrelative_literal_loads && CONSTANT_POOL_ADDRESS_P (x))
+ return SYMBOL_SMALL_ABSOLUTE;
+ else
+ return SYMBOL_FORCE_TO_MEM;
Index: gcc/config/rs6000/vector.md
===================================================================
--- a/src/gcc/config/rs6000/vector.md (.../tags/gcc_7_1_0_release)
@@ -61788,11 +75950,303 @@ Index: gcc/config/rs6000/predicates.md
;; Return 1 if the operand is suitable for load/store quad memory.
;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx).
(define_predicate "quad_memory_operand"
+Index: gcc/config/rs6000/t-rtems
+===================================================================
+--- a/src/gcc/config/rs6000/t-rtems (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/rs6000/t-rtems (.../branches/gcc-7-branch)
+@@ -27,8 +27,8 @@
+ MULTILIB_OPTIONS += mcpu=403/mcpu=505/mcpu=603e/mcpu=604/mcpu=860/mcpu=7400/mcpu=8540/mcpu=e6500
+ MULTILIB_DIRNAMES += m403 m505 m603e m604 m860 m7400 m8540 me6500
+
+-MULTILIB_OPTIONS += m32
+-MULTILIB_DIRNAMES += m32
++MULTILIB_OPTIONS += m32/m64
++MULTILIB_DIRNAMES += m32 m64
+
+ MULTILIB_OPTIONS += msoft-float/mfloat-gprs=double
+ MULTILIB_DIRNAMES += nof gprsdouble
+@@ -77,3 +77,5 @@
+ MULTILIB_REQUIRED += mcpu=860
+ MULTILIB_REQUIRED += mcpu=e6500/m32
+ MULTILIB_REQUIRED += mcpu=e6500/m32/msoft-float/mno-altivec
++MULTILIB_REQUIRED += mcpu=e6500/m64
++MULTILIB_REQUIRED += mcpu=e6500/m64/msoft-float/mno-altivec
+Index: gcc/config/rs6000/ppc-auxv.h
+===================================================================
+--- a/src/gcc/config/rs6000/ppc-auxv.h (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/rs6000/ppc-auxv.h (.../branches/gcc-7-branch)
+@@ -89,6 +89,8 @@
+ #define PPC_FEATURE2_HTM_NOSC 0x01000000
+ #define PPC_FEATURE2_ARCH_3_00 0x00800000
+ #define PPC_FEATURE2_HAS_IEEE128 0x00400000
++#define PPC_FEATURE2_DARN 0x00200000
++#define PPC_FEATURE2_SCV 0x00100000
+
+
+ /* Thread Control Block (TCB) offsets of the AT_PLATFORM, AT_HWCAP and
+Index: gcc/config/rs6000/rtems.h
+===================================================================
+--- a/src/gcc/config/rs6000/rtems.h (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/rs6000/rtems.h (.../branches/gcc-7-branch)
+@@ -14,33 +14,172 @@
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+- You should have received a copy of the GNU General Public License
+- along with GCC; see the file COPYING3. If not see
++ Under Section 7 of GPL version 3, you are granted additional
++ permissions described in the GCC Runtime Library Exception, version
++ 3.1, as published by the Free Software Foundation.
++
++ You should have received a copy of the GNU General Public License and
++ a copy of the GCC Runtime Library Exception along with this program;
++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+-/* Specify predefined symbols in preprocessor. */
++/* Copy and paste from linux64.h and freebsd64.h */
++#ifdef IN_LIBGCC2
++#undef TARGET_64BIT
++#ifdef __powerpc64__
++#define TARGET_64BIT 1
++#else
++#define TARGET_64BIT 0
++#endif
++#endif
+
++/* Copy and paste from linux64.h and freebsd64.h */
++#undef TARGET_AIX
++#define TARGET_AIX TARGET_64BIT
++
+ #undef TARGET_OS_CPP_BUILTINS
+-#define TARGET_OS_CPP_BUILTINS() \
+- do \
+- { \
+- builtin_define_std ("PPC"); \
+- builtin_define ("__rtems__"); \
+- builtin_define ("__USE_INIT_FINI__"); \
+- builtin_assert ("system=rtems"); \
+- builtin_assert ("cpu=powerpc"); \
+- builtin_assert ("machine=powerpc"); \
+- TARGET_OS_SYSV_CPP_BUILTINS (); \
+- } \
++#define TARGET_OS_CPP_BUILTINS() \
++ do \
++ { \
++ builtin_define ("__rtems__"); \
++ builtin_define ("__USE_INIT_FINI__"); \
++ builtin_assert ("system=rtems"); \
++ if (TARGET_64BIT) \
++ { \
++ builtin_define ("__PPC__"); \
++ builtin_define ("__PPC64__"); \
++ builtin_define ("__powerpc64__"); \
++ builtin_assert ("cpu=powerpc64"); \
++ builtin_assert ("machine=powerpc64"); \
++ } \
++ else \
++ { \
++ builtin_define_std ("PPC"); \
++ builtin_define_std ("powerpc"); \
++ builtin_assert ("cpu=powerpc"); \
++ builtin_assert ("machine=powerpc"); \
++ TARGET_OS_SYSV_CPP_BUILTINS (); \
++ } \
++ } \
+ while (0)
+
++/* Copy and paste from linux64.h and freebsd64.h */
++#define INVALID_64BIT "-m%s not supported in this configuration"
++
++/* A lot of copy and paste from linux64.h and freebsd64.h */
++#undef SUBSUBTARGET_OVERRIDE_OPTIONS
++#define SUBSUBTARGET_OVERRIDE_OPTIONS \
++ do \
++ { \
++ if (rs6000_isa_flags & OPTION_MASK_64BIT) \
++ { \
++ rs6000_elf_abi = 2; \
++ rs6000_current_abi = ABI_ELFv2; \
++ if (rs6000_isa_flags & OPTION_MASK_RELOCATABLE) \
++ { \
++ rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \
++ error (INVALID_64BIT, "relocatable"); \
++ } \
++ if (rs6000_isa_flags & OPTION_MASK_EABI) \
++ { \
++ rs6000_isa_flags &= ~OPTION_MASK_EABI; \
++ error (INVALID_64BIT, "eabi"); \
++ } \
++ if (TARGET_PROTOTYPE) \
++ { \
++ target_prototype = 0; \
++ error (INVALID_64BIT, "prototype"); \
++ } \
++ if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) == 0) \
++ { \
++ rs6000_isa_flags |= OPTION_MASK_POWERPC64; \
++ error ("-m64 requires a PowerPC64 cpu"); \
++ } \
++ } \
++ } \
++ while (0)
++
+ #undef TARGET_LIBGCC_SDATA_SECTION
+ #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
+
++/* Copy and paste from linux64.h and freebsd64.h */
++#undef SIZE_TYPE
++#define SIZE_TYPE (TARGET_64BIT ? "long unsigned int" : "unsigned int")
++
++/* Copy and paste from linux64.h and freebsd64.h */
++#undef PTRDIFF_TYPE
++#define PTRDIFF_TYPE (TARGET_64BIT ? "long int" : "int")
++
++/* Copy and paste from freebsd64.h */
++#undef WCHAR_TYPE
++
++/* Copy and paste from freebsd64.h */
++#undef WCHAR_TYPE_SIZE
++#define WCHAR_TYPE_SIZE 32
++
++/* Copy and paste from linux64.h and freebsd64.h */
++#ifdef __powerpc64__
++#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
++ asm (SECTION_OP "\n" \
++" bl " #FUNC "\n" \
++" nop\n" \
++" .previous");
++#endif
++
++/* This could be also POWERPC_FREEBSD. It is related to the save/restore
++ defines below. */
++#define POWERPC_LINUX
++
++/* Copy and paste from linux64.h and freebsd64.h */
++#undef SAVE_FP_PREFIX
++#define SAVE_FP_PREFIX (TARGET_64BIT ? "._savef" : "_savefpr_")
++#undef SAVE_FP_SUFFIX
++#define SAVE_FP_SUFFIX ""
++#undef RESTORE_FP_PREFIX
++#define RESTORE_FP_PREFIX (TARGET_64BIT ? "._restf" : "_restfpr_")
++#undef RESTORE_FP_SUFFIX
++#define RESTORE_FP_SUFFIX ""
++
++/* Copy and paste from linux64.h and freebsd64.h */
++#undef ASM_DECLARE_FUNCTION_SIZE
++#define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \
++ do \
++ { \
++ if (!flag_inhibit_size_directive) \
++ { \
++ fputs ("\t.size\t", (FILE)); \
++ if (TARGET_64BIT && DOT_SYMBOLS) \
++ putc ('.', (FILE)); \
++ assemble_name ((FILE), (FNAME)); \
++ fputs (",.-", (FILE)); \
++ rs6000_output_function_entry (FILE, FNAME); \
++ putc ('\n', (FILE)); \
++ } \
++ } \
++ while (0)
++
++/* Copy and paste from linux64.h and freebsd64.h */
++#undef ASM_OUTPUT_SPECIAL_POOL_ENTRY_P
++#define ASM_OUTPUT_SPECIAL_POOL_ENTRY_P(X, MODE) \
++ (TARGET_TOC \
++ && (GET_CODE (X) == SYMBOL_REF \
++ || (GET_CODE (X) == CONST && GET_CODE (XEXP (X, 0)) == PLUS \
++ && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF) \
++ || GET_CODE (X) == LABEL_REF \
++ || (GET_CODE (X) == CONST_INT \
++ && GET_MODE_BITSIZE (MODE) <= GET_MODE_BITSIZE (Pmode)) \
++ || (GET_CODE (X) == CONST_DOUBLE \
++ && ((TARGET_64BIT \
++ && (TARGET_MINIMAL_TOC \
++ || (SCALAR_FLOAT_MODE_P (GET_MODE (X)) \
++ && ! TARGET_NO_FP_IN_TOC))) \
++ || (!TARGET_64BIT \
++ && !TARGET_NO_FP_IN_TOC \
++ && SCALAR_FLOAT_MODE_P (GET_MODE (X)) \
++ && BITS_PER_WORD == HOST_BITS_PER_INT)))))
++
+ #undef CPP_OS_DEFAULT_SPEC
+-#define CPP_OS_DEFAULT_SPEC "%(cpp_os_rtems)"
+-
+-#define CPP_OS_RTEMS_SPEC "\
++#define CPP_OS_DEFAULT_SPEC "\
+ %{!mcpu*: %{!Dppc*: %{!Dmpc*: -Dmpc750} } }\
+ %{mcpu=403: %{!Dppc*: %{!Dmpc*: -Dppc403} } } \
+ %{mcpu=505: %{!Dppc*: %{!Dmpc*: -Dmpc505} } } \
+@@ -55,6 +194,37 @@
+ %{mcpu=8540: %{!Dppc*: %{!Dmpc*: -Dppc8540} } } \
+ %{mcpu=e6500: -D__PPC_CPU_E6500__}"
+
++#undef ASM_DEFAULT_SPEC
++#define ASM_DEFAULT_SPEC "-mppc%{m64:64}"
++
++#undef ASM_SPEC
++#define ASM_SPEC "%{!m64:%(asm_spec32)}%{m64:%(asm_spec64)} %(asm_spec_common)"
++
++#define ASM_SPEC32 "-a32 \
++%{mrelocatable} %{mrelocatable-lib} %{" FPIE_OR_FPIC_SPEC ":-K PIC} \
++%{memb|msdata=eabi: -memb}"
++
++#define ASM_SPEC64 "-a64"
++
++#define ASM_SPEC_COMMON "%(asm_cpu) \
++%{,assembler|,assembler-with-cpp: %{mregnames} %{mno-regnames}}" \
++ ENDIAN_SELECT(" -mbig", " -mlittle", DEFAULT_ASM_ENDIAN)
++
++#undef LINK_OS_DEFAULT_SPEC
++#define LINK_OS_DEFAULT_SPEC \
++"%{!m64:%(link_os_spec32)}%{m64:%(link_os_spec64)}"
++
++#define LINK_OS_SPEC32 ENDIAN_SELECT(" -m elf32ppc", \
++ " -m elf32lppc", \
++ " -m elf32ppc")
++#define LINK_OS_SPEC64 ENDIAN_SELECT(" -m elf64ppc", \
++ " -m elf64lppc", \
++ " -m elf64ppc")
++
+ #undef SUBSUBTARGET_EXTRA_SPECS
+ #define SUBSUBTARGET_EXTRA_SPECS \
+- { "cpp_os_rtems", CPP_OS_RTEMS_SPEC }
++ { "asm_spec_common", ASM_SPEC_COMMON }, \
++ { "asm_spec32", ASM_SPEC32 }, \
++ { "asm_spec64", ASM_SPEC64 }, \
++ { "link_os_spec32", LINK_OS_SPEC32 }, \
++ { "link_os_spec64", LINK_OS_SPEC64 },
+Index: gcc/config/rs6000/rs6000-c.c
+===================================================================
+--- a/src/gcc/config/rs6000/rs6000-c.c (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/rs6000/rs6000-c.c (.../branches/gcc-7-branch)
+@@ -648,6 +648,9 @@
+ builtin_define ("__FLOAT128_HARDWARE__");
+ if (TARGET_LONG_DOUBLE_128 && FLOAT128_IBM_P (TFmode))
+ builtin_define ("__ibm128=long double");
++#ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
++ builtin_define ("__BUILTIN_CPU_SUPPORTS__");
++#endif
+
+ /* We needed to create a keyword if -mfloat128-type was used but not -mfloat,
+ so we used __ieee128. If -mfloat128 was used, create a #define back to
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- a/src/gcc/config/rs6000/rs6000.c (.../tags/gcc_7_1_0_release)
+++ b/src/gcc/config/rs6000/rs6000.c (.../branches/gcc-7-branch)
-@@ -5873,6 +5873,10 @@
+@@ -379,7 +379,9 @@
+ { "tar", PPC_FEATURE2_HAS_TAR, 1 },
+ { "vcrypto", PPC_FEATURE2_HAS_VEC_CRYPTO, 1 },
+ { "arch_3_00", PPC_FEATURE2_ARCH_3_00, 1 },
+- { "ieee128", PPC_FEATURE2_HAS_IEEE128, 1 }
++ { "ieee128", PPC_FEATURE2_HAS_IEEE128, 1 },
++ { "darn", PPC_FEATURE2_DARN, 1 },
++ { "scv", PPC_FEATURE2_SCV, 1 }
+ };
+
+ /* Newer LIBCs explicitly export this symbol to declare that they provide
+@@ -5873,6 +5875,10 @@
/* Implement targetm.vectorize.init_cost. */
@@ -61803,7 +76257,7 @@ Index: gcc/config/rs6000/rs6000.c
static void *
rs6000_init_cost (struct loop *loop_info)
{
-@@ -5881,6 +5885,7 @@
+@@ -5881,6 +5887,7 @@
data->cost[vect_prologue] = 0;
data->cost[vect_body] = 0;
data->cost[vect_epilogue] = 0;
@@ -61811,7 +76265,7 @@ Index: gcc/config/rs6000/rs6000.c
return data;
}
-@@ -5907,6 +5912,15 @@
+@@ -5907,6 +5914,15 @@
retval = (unsigned) (count * stmt_cost);
cost_data->cost[where] += retval;
@@ -61827,7 +76281,7 @@ Index: gcc/config/rs6000/rs6000.c
}
return retval;
-@@ -5923,6 +5937,19 @@
+@@ -5923,6 +5939,19 @@
if (cost_data->loop_info)
rs6000_density_test (cost_data);
@@ -61847,7 +76301,35 @@ Index: gcc/config/rs6000/rs6000.c
*prologue_cost = cost_data->cost[vect_prologue];
*body_cost = cost_data->cost[vect_body];
*epilogue_cost = cost_data->cost[vect_epilogue];
-@@ -18183,6 +18210,17 @@
+@@ -7454,6 +7483,8 @@
+ insn = gen_vsx_set_v8hi_p9 (target, target, val, elt_rtx);
+ else if (mode == V16QImode)
+ insn = gen_vsx_set_v16qi_p9 (target, target, val, elt_rtx);
++ else if (mode == V4SFmode)
++ insn = gen_vsx_set_v4sf_p9 (target, target, val, elt_rtx);
+ }
+
+ if (insn)
+@@ -15555,6 +15586,8 @@
+ emit_insn (gen_eqsi3 (scratch2, scratch1, const0_rtx));
+ emit_insn (gen_rtx_SET (target, gen_rtx_XOR (SImode, scratch2, const1_rtx)));
+ }
++ else
++ gcc_unreachable ();
+
+ /* Record that we have expanded a CPU builtin, so that we can later
+ emit a reference to the special symbol exported by LIBC to ensure we
+@@ -15562,6 +15595,9 @@
+ cpu_builtin_p = true;
+
+ #else
++ warning (0, "%s needs GLIBC (2.23 and newer) that exports hardware "
++ "capability bits", rs6000_builtin_info[(size_t) fcode].name);
++
+ /* For old LIBCs, always return FALSE. */
+ emit_move_insn (target, GEN_INT (0));
+ #endif /* TARGET_LIBC_PROVIDES_HWCAP_IN_TCB */
+@@ -18183,6 +18219,17 @@
def_builtin ("__builtin_vsx_st_elemrev_v16qi",
void_ftype_v16qi_long_pvoid, VSX_BUILTIN_ST_ELEMREV_V16QI);
}
@@ -61865,7 +76347,7 @@ Index: gcc/config/rs6000/rs6000.c
def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
VSX_BUILTIN_VEC_LD);
-@@ -28096,9 +28134,11 @@
+@@ -28096,9 +28143,11 @@
&& REGNO (stack_limit_rtx) > 1
&& REGNO (stack_limit_rtx) <= 31)
{
@@ -61884,7 +76366,142 @@ Index: gcc/config/rs6000/vsx.md
===================================================================
--- a/src/gcc/config/rs6000/vsx.md (.../tags/gcc_7_1_0_release)
+++ b/src/gcc/config/rs6000/vsx.md (.../branches/gcc-7-branch)
-@@ -3068,10 +3068,11 @@
+@@ -3012,6 +3012,134 @@
+ }
+ [(set_attr "type" "vecperm")])
+
++(define_insn_and_split "vsx_set_v4sf_p9"
++ [(set (match_operand:V4SF 0 "gpc_reg_operand" "=wa")
++ (unspec:V4SF
++ [(match_operand:V4SF 1 "gpc_reg_operand" "0")
++ (match_operand:SF 2 "gpc_reg_operand" "ww")
++ (match_operand:QI 3 "const_0_to_3_operand" "n")]
++ UNSPEC_VSX_SET))
++ (clobber (match_scratch:SI 4 "=&wJwK"))]
++ "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
++ && TARGET_UPPER_REGS_DI && TARGET_POWERPC64"
++ "#"
++ "&& reload_completed"
++ [(set (match_dup 5)
++ (unspec:V4SF [(match_dup 2)]
++ UNSPEC_VSX_CVDPSPN))
++ (parallel [(set (match_dup 4)
++ (vec_select:SI (match_dup 6)
++ (parallel [(match_dup 7)])))
++ (clobber (scratch:SI))])
++ (set (match_dup 8)
++ (unspec:V4SI [(match_dup 8)
++ (match_dup 4)
++ (match_dup 3)]
++ UNSPEC_VSX_SET))]
++{
++ unsigned int tmp_regno = reg_or_subregno (operands[4]);
++
++ operands[5] = gen_rtx_REG (V4SFmode, tmp_regno);
++ operands[6] = gen_rtx_REG (V4SImode, tmp_regno);
++ operands[7] = GEN_INT (VECTOR_ELT_ORDER_BIG ? 1 : 2);
++ operands[8] = gen_rtx_REG (V4SImode, reg_or_subregno (operands[0]));
++}
++ [(set_attr "type" "vecperm")
++ (set_attr "length" "12")])
++
++;; Special case setting 0.0f to a V4SF element
++(define_insn_and_split "*vsx_set_v4sf_p9_zero"
++ [(set (match_operand:V4SF 0 "gpc_reg_operand" "=wa")
++ (unspec:V4SF
++ [(match_operand:V4SF 1 "gpc_reg_operand" "0")
++ (match_operand:SF 2 "zero_fp_constant" "j")
++ (match_operand:QI 3 "const_0_to_3_operand" "n")]
++ UNSPEC_VSX_SET))
++ (clobber (match_scratch:SI 4 "=&wJwK"))]
++ "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
++ && TARGET_UPPER_REGS_DI && TARGET_POWERPC64"
++ "#"
++ "&& reload_completed"
++ [(set (match_dup 4)
++ (const_int 0))
++ (set (match_dup 5)
++ (unspec:V4SI [(match_dup 5)
++ (match_dup 4)
++ (match_dup 3)]
++ UNSPEC_VSX_SET))]
++{
++ operands[5] = gen_rtx_REG (V4SImode, reg_or_subregno (operands[0]));
++}
++ [(set_attr "type" "vecperm")
++ (set_attr "length" "8")])
++
++;; Optimize x = vec_insert (vec_extract (v2, n), v1, m) if n is the element
++;; that is in the default scalar position (1 for big endian, 2 for little
++;; endian). We just need to do an xxinsertw since the element is in the
++;; correct location.
++
++(define_insn "*vsx_insert_extract_v4sf_p9"
++ [(set (match_operand:V4SF 0 "gpc_reg_operand" "=wa")
++ (unspec:V4SF
++ [(match_operand:V4SF 1 "gpc_reg_operand" "0")
++ (vec_select:SF (match_operand:V4SF 2 "gpc_reg_operand" "wa")
++ (parallel
++ [(match_operand:QI 3 "const_0_to_3_operand" "n")]))
++ (match_operand:QI 4 "const_0_to_3_operand" "n")]
++ UNSPEC_VSX_SET))]
++ "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
++ && TARGET_UPPER_REGS_DI && TARGET_POWERPC64
++ && (INTVAL (operands[3]) == (VECTOR_ELT_ORDER_BIG ? 1 : 2))"
++{
++ int ele = INTVAL (operands[4]);
++
++ if (!VECTOR_ELT_ORDER_BIG)
++ ele = GET_MODE_NUNITS (V4SFmode) - 1 - ele;
++
++ operands[4] = GEN_INT (GET_MODE_SIZE (SFmode) * ele);
++ return "xxinsertw %x0,%x2,%4";
++}
++ [(set_attr "type" "vecperm")])
++
++;; Optimize x = vec_insert (vec_extract (v2, n), v1, m) if n is not the element
++;; that is in the default scalar position (1 for big endian, 2 for little
++;; endian). Convert the insert/extract to int and avoid doing the conversion.
++
++(define_insn_and_split "*vsx_insert_extract_v4sf_p9_2"
++ [(set (match_operand:V4SF 0 "gpc_reg_operand" "=wa")
++ (unspec:V4SF
++ [(match_operand:V4SF 1 "gpc_reg_operand" "0")
++ (vec_select:SF (match_operand:V4SF 2 "gpc_reg_operand" "wa")
++ (parallel
++ [(match_operand:QI 3 "const_0_to_3_operand" "n")]))
++ (match_operand:QI 4 "const_0_to_3_operand" "n")]
++ UNSPEC_VSX_SET))
++ (clobber (match_scratch:SI 5 "=&wJwK"))]
++ "VECTOR_MEM_VSX_P (V4SFmode) && VECTOR_MEM_VSX_P (V4SImode)
++ && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
++ && TARGET_UPPER_REGS_DI && TARGET_POWERPC64
++ && (INTVAL (operands[3]) != (VECTOR_ELT_ORDER_BIG ? 1 : 2))"
++ "#"
++ "&& 1"
++ [(parallel [(set (match_dup 5)
++ (vec_select:SI (match_dup 6)
++ (parallel [(match_dup 3)])))
++ (clobber (scratch:SI))])
++ (set (match_dup 7)
++ (unspec:V4SI [(match_dup 8)
++ (match_dup 5)
++ (match_dup 4)]
++ UNSPEC_VSX_SET))]
++{
++ if (GET_CODE (operands[5]) == SCRATCH)
++ operands[5] = gen_reg_rtx (SImode);
++
++ operands[6] = gen_lowpart (V4SImode, operands[2]);
++ operands[7] = gen_lowpart (V4SImode, operands[0]);
++ operands[8] = gen_lowpart (V4SImode, operands[1]);
++}
++ [(set_attr "type" "vecperm")])
++
+ ;; Expanders for builtins
+ (define_expand "vsx_mergel_<mode>"
+ [(use (match_operand:VSX_D 0 "vsx_register_operand" ""))
+@@ -3068,10 +3196,11 @@
;; V2DF/V2DI splat
(define_insn_and_split "vsx_splat_<mode>"
[(set (match_operand:VSX_D 0 "vsx_register_operand"
@@ -61898,7 +76515,7 @@ Index: gcc/config/rs6000/vsx.md
"VECTOR_MEM_VSX_P (<MODE>mode)"
"@
xxpermdi %x0,%x1,%x1,0
-@@ -3078,8 +3079,12 @@
+@@ -3078,8 +3207,12 @@
lxvdsx %x0,%y1
mtvsrdd %x0,%1,%1
#"
@@ -61964,19 +76581,30 @@ Index: gcc/config/rs6000/rs6000.md
(define_code_attr su [(sign_extend "s")
(zero_extend "u")
-@@ -728,6 +701,11 @@
+@@ -728,6 +701,13 @@
(define_code_attr SMINMAX [(smin "SMIN")
(smax "SMAX")])
+;; Iterator to optimize the following cases:
+;; D-form load to FPR register & move to Altivec register
+;; Move Altivec register to FPR register and store
-+(define_mode_iterator ALTIVEC_DFORM [DI DF SF])
++(define_mode_iterator ALTIVEC_DFORM [DF
++ SF
++ (DI "TARGET_POWERPC64")])
+
;; Start with fixed-point load and store insns. Here we put only the more
;; complex forms. Basic data transfer is done later.
-@@ -1027,8 +1005,8 @@
+@@ -974,7 +954,7 @@
+ (set (match_dup 0)
+ (sign_extend:EXTHI (match_dup 2)))]
+ {
+- operands[2] = gen_rtx_REG (HImode, REGNO (operands[1]));
++ operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));
+ })
+
+ (define_insn "*extendhi<mode>2_noload"
+@@ -1027,8 +1007,8 @@
(define_insn "extendsi<mode>2"
@@ -61987,7 +76615,7 @@ Index: gcc/config/rs6000/rs6000.md
""
"@
lwa%U1%X1 %0,%1
-@@ -1036,10 +1014,39 @@
+@@ -1036,10 +1016,39 @@
lfiwax %0,%y1
lxsiwax %x0,%y1
mtvsrwa %x0,%1
@@ -62030,13 +76658,13 @@ Index: gcc/config/rs6000/rs6000.md
(define_insn_and_split "*extendsi<mode>2_dot"
[(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
(compare:CC (sign_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
-@@ -1643,6 +1650,17 @@
+@@ -1643,6 +1652,17 @@
|| rtx_equal_p (operands[0], operands[1]))
? operands[0] : gen_reg_rtx (<MODE>mode));
+ /* Adding a constant to r0 is not a valid insn, so use a different
+ strategy in that case. */
-+ if (REGNO (operands[1]) == 0 || REGNO (tmp) == 0)
++ if (reg_or_subregno (operands[1]) == 0 || reg_or_subregno (tmp) == 0)
+ {
+ if (operands[0] == operands[1])
+ FAIL;
@@ -62048,7 +76676,7 @@ Index: gcc/config/rs6000/rs6000.md
HOST_WIDE_INT val = INTVAL (operands[2]);
HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
-@@ -5570,7 +5588,7 @@
+@@ -5570,7 +5590,7 @@
"TARGET_HARD_FLOAT && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
"
{
@@ -62057,7 +76685,7 @@ Index: gcc/config/rs6000/rs6000.md
{
rtx src = force_reg (<MODE>mode, operands[1]);
-@@ -5596,7 +5614,8 @@
+@@ -5596,7 +5616,8 @@
(clobber (match_scratch:DI 2 "=d"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
@@ -62067,7 +76695,7 @@ Index: gcc/config/rs6000/rs6000.md
"#"
""
[(pc)]
-@@ -5637,7 +5656,8 @@
+@@ -5637,7 +5658,8 @@
(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
(clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
(clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
@@ -62077,7 +76705,7 @@ Index: gcc/config/rs6000/rs6000.md
"#"
""
[(pc)]
-@@ -5721,7 +5741,7 @@
+@@ -5721,7 +5743,7 @@
|| <E500_CONVERT>)"
"
{
@@ -62086,7 +76714,7 @@ Index: gcc/config/rs6000/rs6000.md
{
emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
DONE;
-@@ -5733,7 +5753,8 @@
+@@ -5733,7 +5755,8 @@
(unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
(clobber (match_scratch:DI 2 "=d"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
@@ -62096,7 +76724,7 @@ Index: gcc/config/rs6000/rs6000.md
"#"
""
[(pc)]
-@@ -5818,13 +5839,43 @@
+@@ -5818,13 +5841,43 @@
}
DONE;
})
@@ -62145,7 +76773,7 @@ Index: gcc/config/rs6000/rs6000.md
UNSPEC_FCTIWZ))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
"@
-@@ -7168,40 +7219,82 @@
+@@ -7168,40 +7221,82 @@
operands[3] = gen_int_mode (l, SImode);
}")
@@ -62248,7 +76876,31 @@ Index: gcc/config/rs6000/rs6000.md
(define_insn "*mov<mode>_softfloat"
[(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
-@@ -13999,6 +14092,74 @@
+@@ -7385,8 +7480,8 @@
+ ;; except for 0.0 which can be created on VSX with an xor instruction.
+
+ (define_insn "*mov<mode>_hardfloat32"
+- [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_p9>,wY,<f64_vsx>,<f64_vsx>,!r,Y,r,!r")
+- (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,wY,<f64_p9>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r"))]
++ [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_p9>,wY,<f64_av>,Z,<f64_vsx>,<f64_vsx>,!r,Y,r,!r")
++ (match_operand:FMOVE64 1 "input_operand" "d,m,d,wY,<f64_p9>,Z,<f64_av>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r"))]
+ "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
+ && (gpc_reg_operand (operands[0], <MODE>mode)
+ || gpc_reg_operand (operands[1], <MODE>mode))"
+@@ -7394,10 +7489,10 @@
+ stfd%U0%X0 %1,%0
+ lfd%U1%X1 %0,%1
+ fmr %0,%1
++ lxsd %0,%1
++ stxsd %1,%0
+ lxsd%U1x %x0,%y1
+ stxsd%U0x %x1,%y0
+- lxsd %0,%1
+- stxsd %1,%0
+ xxlor %x0,%x1,%x1
+ xxlxor %x0,%x0,%x0
+ #
+@@ -13999,6 +14094,74 @@
(set_attr "length" "8")])
@@ -62259,13 +76911,13 @@ Index: gcc/config/rs6000/rs6000.md
+;; move fpr->altivec
+
+(define_peephole2
-+ [(match_scratch:DI 0 "b")
++ [(match_scratch:P 0 "b")
+ (set (match_operand:ALTIVEC_DFORM 1 "fpr_reg_operand")
+ (match_operand:ALTIVEC_DFORM 2 "simple_offsettable_mem_operand"))
+ (set (match_operand:ALTIVEC_DFORM 3 "altivec_register_operand")
+ (match_dup 1))]
-+ "TARGET_VSX && TARGET_POWERPC64 && TARGET_UPPER_REGS_<MODE>
-+ && !TARGET_P9_DFORM_SCALAR && peep2_reg_dead_p (2, operands[1])"
++ "TARGET_VSX && TARGET_UPPER_REGS_<MODE> && !TARGET_P9_DFORM_SCALAR
++ && peep2_reg_dead_p (2, operands[1])"
+ [(set (match_dup 0)
+ (match_dup 4))
+ (set (match_dup 3)
@@ -62280,7 +76932,7 @@ Index: gcc/config/rs6000/rs6000.md
+ add_op0 = XEXP (addr, 0);
+ add_op1 = XEXP (addr, 1);
+ gcc_assert (REG_P (add_op0));
-+ new_addr = gen_rtx_PLUS (DImode, add_op0, tmp_reg);
++ new_addr = gen_rtx_PLUS (Pmode, add_op0, tmp_reg);
+
+ operands[4] = add_op1;
+ operands[5] = change_address (mem, <MODE>mode, new_addr);
@@ -62292,13 +76944,13 @@ Index: gcc/config/rs6000/rs6000.md
+;; store fpr
+
+(define_peephole2
-+ [(match_scratch:DI 0 "b")
++ [(match_scratch:P 0 "b")
+ (set (match_operand:ALTIVEC_DFORM 1 "fpr_reg_operand")
+ (match_operand:ALTIVEC_DFORM 2 "altivec_register_operand"))
+ (set (match_operand:ALTIVEC_DFORM 3 "simple_offsettable_mem_operand")
+ (match_dup 1))]
-+ "TARGET_VSX && TARGET_POWERPC64 && TARGET_UPPER_REGS_<MODE>
-+ && !TARGET_P9_DFORM_SCALAR && peep2_reg_dead_p (2, operands[1])"
++ "TARGET_VSX && TARGET_UPPER_REGS_<MODE> && !TARGET_P9_DFORM_SCALAR
++ && peep2_reg_dead_p (2, operands[1])"
+ [(set (match_dup 0)
+ (match_dup 4))
+ (set (match_dup 5)
@@ -62313,7 +76965,7 @@ Index: gcc/config/rs6000/rs6000.md
+ add_op0 = XEXP (addr, 0);
+ add_op1 = XEXP (addr, 1);
+ gcc_assert (REG_P (add_op0));
-+ new_addr = gen_rtx_PLUS (DImode, add_op0, tmp_reg);
++ new_addr = gen_rtx_PLUS (Pmode, add_op0, tmp_reg);
+
+ operands[4] = add_op1;
+ operands[5] = change_address (mem, <MODE>mode, new_addr);
@@ -62604,6 +77256,42 @@ Index: gcc/config/arm/t-aprofile
MULTILIB_MATCHES += march?armv8-a=mcpu?xgene1
# Arch Matches
+Index: gcc/config/arm/rtems.h
+===================================================================
+--- a/src/gcc/config/arm/rtems.h (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/arm/rtems.h (.../branches/gcc-7-branch)
+@@ -1,20 +1,25 @@
+ /* Definitions for RTEMS based ARM systems using EABI.
+ Copyright (C) 2011-2017 Free Software Foundation, Inc.
+-
++
+ This file is part of GCC.
+-
++
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 3, or (at your
+ option) any later version.
+-
++
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+-
+- You should have received a copy of the GNU General Public License
+- along with GCC; see the file COPYING3. If not see
++
++ Under Section 7 of GPL version 3, you are granted additional
++ permissions described in the GCC Runtime Library Exception, version
++ 3.1, as published by the Free Software Foundation.
++
++ You should have received a copy of the GNU General Public License and
++ a copy of the GCC Runtime Library Exception along with this program;
++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+ #define HAS_INIT_SECTION
Index: gcc/config/arm/arm-tune.md
===================================================================
--- a/src/gcc/config/arm/arm-tune.md (.../tags/gcc_7_1_0_release)
@@ -62876,6 +77564,122 @@ Index: gcc/config/pa/pa.c
if (MAYBE_FP_REG_CLASS_P (rclass))
return true;
+Index: gcc/config/mips/rtems.h
+===================================================================
+--- a/src/gcc/config/mips/rtems.h (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/mips/rtems.h (.../branches/gcc-7-branch)
+@@ -2,22 +2,27 @@
+ Copyright (C) 1996-2017 Free Software Foundation, Inc.
+ Contributed by Joel Sherrill (joel at OARcorp.com).
+
+-This file is part of GCC.
++ This file is part of GCC.
+
+-GCC is free software; you can redistribute it and/or modify
+-it under the terms of the GNU General Public License as published by
+-the Free Software Foundation; either version 3, or (at your option)
+-any later version.
++ GCC is free software; you can redistribute it and/or modify it
++ under the terms of the GNU General Public License as published
++ by the Free Software Foundation; either version 3, or (at your
++ option) any later version.
+
+-GCC is distributed in the hope that it will be useful,
+-but WITHOUT ANY WARRANTY; without even the implied warranty of
+-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-GNU General Public License for more details.
++ GCC is distributed in the hope that it will be useful, but WITHOUT
++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
++ License for more details.
+
+-You should have received a copy of the GNU General Public License
+-along with GCC; see the file COPYING3. If not see
+-<http://www.gnu.org/licenses/>. */
++ Under Section 7 of GPL version 3, you are granted additional
++ permissions described in the GCC Runtime Library Exception, version
++ 3.1, as published by the Free Software Foundation.
+
++ You should have received a copy of the GNU General Public License and
++ a copy of the GCC Runtime Library Exception along with this program;
++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
++ <http://www.gnu.org/licenses/>. */
++
+ /* Specify predefined symbols in preprocessor. */
+
+ #define TARGET_OS_CPP_BUILTINS() \
+Index: gcc/config/v850/rtems.h
+===================================================================
+--- a/src/gcc/config/v850/rtems.h (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/v850/rtems.h (.../branches/gcc-7-branch)
+@@ -3,15 +3,15 @@
+
+ This file is part of GCC.
+
+- GCC is free software; you can redistribute it and/or modify
+- it under the terms of the GNU General Public License as published by
+- the Free Software Foundation; either version 3, or (at your option)
+- any later version.
++ GCC is free software; you can redistribute it and/or modify it
++ under the terms of the GNU General Public License as published
++ by the Free Software Foundation; either version 3, or (at your
++ option) any later version.
+
+- GCC is distributed in the hope that it will be useful,
+- but WITHOUT ANY WARRANTY; without even the implied warranty of
+- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+- GNU General Public License for more details.
++ GCC is distributed in the hope that it will be useful, but WITHOUT
++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
++ License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+Index: gcc/config/bfin/rtems.h
+===================================================================
+--- a/src/gcc/config/bfin/rtems.h (.../tags/gcc_7_1_0_release)
++++ b/src/gcc/config/bfin/rtems.h (.../branches/gcc-7-branch)
+@@ -2,22 +2,27 @@
+ Copyright (C) 2006-2017 Free Software Foundation, Inc.
+ Contributed by Ralf Corsépius (ralf.corsepius at rtems.org).
+
+-This file is part of GCC.
++ This file is part of GCC.
+
+-GCC is free software; you can redistribute it and/or modify
+-it under the terms of the GNU General Public License as published by
+-the Free Software Foundation; either version 3, or (at your option)
+-any later version.
++ GCC is free software; you can redistribute it and/or modify it
++ under the terms of the GNU General Public License as published
++ by the Free Software Foundation; either version 3, or (at your
++ option) any later version.
+
+-GCC is distributed in the hope that it will be useful,
+-but WITHOUT ANY WARRANTY; without even the implied warranty of
+-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-GNU General Public License for more details.
++ GCC is distributed in the hope that it will be useful, but WITHOUT
++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
++ License for more details.
+
+-You should have received a copy of the GNU General Public License
+-along with GCC; see the file COPYING3. If not see
+-<http://www.gnu.org/licenses/>. */
++ Under Section 7 of GPL version 3, you are granted additional
++ permissions described in the GCC Runtime Library Exception, version
++ 3.1, as published by the Free Software Foundation.
+
++ You should have received a copy of the GNU General Public License and
++ a copy of the GCC Runtime Library Exception along with this program;
++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
++ <http://www.gnu.org/licenses/>. */
++
+ /* Target OS preprocessor built-ins. */
+ #define TARGET_OS_CPP_BUILTINS() \
+ do \
Index: gcc/params.def
===================================================================
--- a/src/gcc/params.def (.../tags/gcc_7_1_0_release)
@@ -62930,6 +77734,80 @@ Index: libgo/go/os/wait_waitid.go
psig := &siginfo[0]
_, _, e := syscall.Syscall6(syscall.SYS_WAITID, _P_PID, uintptr(p.Pid), uintptr(unsafe.Pointer(psig)), syscall.WEXITED|syscall.WNOWAIT, 0, 0)
runtime.KeepAlive(p)
+Index: libgo/go/syscall/syscall_linux_s390x.go
+===================================================================
+--- a/src/libgo/go/syscall/syscall_linux_s390x.go (.../tags/gcc_7_1_0_release)
++++ b/src/libgo/go/syscall/syscall_linux_s390x.go (.../branches/gcc-7-branch)
+@@ -12,10 +12,29 @@
+
+ func (r *PtraceRegs) SetPC(pc uint64) { r.Psw.Addr = pc }
+
+-func PtraceGetRegs(pid int, regsout *PtraceRegs) (err error) {
+- return ptrace(PTRACE_GETREGS, pid, 0, uintptr(unsafe.Pointer(regsout)))
++const syscall_PTRACE_PEEKUSR_AREA = 0x5000
++const syscall_PTRACE_POKEUSR_AREA = 0x5001
++
++type syscall_ptrace_area struct {
++ len uint32
++ kernel_addr uint64
++ process_addr uint64
+ }
+
++func PtraceGetRegs(pid int, regs *PtraceRegs) (err error) {
++ parea := syscall_ptrace_area{
++ 24,
++ 0,
++ uint64(uintptr(unsafe.Pointer(regs))),
++ }
++ return ptrace(syscall_PTRACE_PEEKUSR_AREA, pid, uintptr(unsafe.Pointer(&parea)), 0)
++}
++
+ func PtraceSetRegs(pid int, regs *PtraceRegs) (err error) {
+- return ptrace(PTRACE_SETREGS, pid, 0, uintptr(unsafe.Pointer(regs)))
++ parea := syscall_ptrace_area{
++ 24,
++ 0,
++ uint64(uintptr(unsafe.Pointer(regs))),
++ }
++ return ptrace(syscall_PTRACE_POKEUSR_AREA, pid, uintptr(unsafe.Pointer(&parea)), 0)
+ }
+Index: libgo/go/syscall/syscall_linux_s390.go
+===================================================================
+--- a/src/libgo/go/syscall/syscall_linux_s390.go (.../tags/gcc_7_1_0_release)
++++ b/src/libgo/go/syscall/syscall_linux_s390.go (.../branches/gcc-7-branch)
+@@ -12,10 +12,29 @@
+
+ func (r *PtraceRegs) SetPC(pc uint64) { r.Psw.Addr = uint32(pc) }
+
+-func PtraceGetRegs(pid int, regsout *PtraceRegs) (err error) {
+- return ptrace(PTRACE_GETREGS, pid, 0, uintptr(unsafe.Pointer(regsout)))
++const syscall_PTRACE_PEEKUSR_AREA = 0x5000
++const syscall_PTRACE_POKEUSR_AREA = 0x5001
++
++type syscall_ptrace_area struct {
++ len uint32
++ kernel_addr uint32
++ process_addr uint32
+ }
+
++func PtraceGetRegs(pid int, regs *PtraceRegs) (err error) {
++ parea := syscall_ptrace_area{
++ 12,
++ 0,
++ uint32(uintptr(unsafe.Pointer(regs))),
++ }
++ return ptrace(syscall_PTRACE_PEEKUSR_AREA, pid, uintptr(unsafe.Pointer(&parea)), 0)
++}
++
+ func PtraceSetRegs(pid int, regs *PtraceRegs) (err error) {
+- return ptrace(PTRACE_SETREGS, pid, 0, uintptr(unsafe.Pointer(regs)))
++ parea := syscall_ptrace_area{
++ 12,
++ 0,
++ uint32(uintptr(unsafe.Pointer(regs))),
++ }
++ return ptrace(syscall_PTRACE_POKEUSR_AREA, pid, uintptr(unsafe.Pointer(&parea)), 0)
+ }
Index: libgo/Makefile.am
===================================================================
--- a/src/libgo/Makefile.am (.../tags/gcc_7_1_0_release)
@@ -64808,3 +79686,13 @@ Index: libcilkrts/ChangeLog
2017-05-02 Release Manager
* GCC 7.1.0 released.
+Index: .
+===================================================================
+--- a/src/. (.../tags/gcc_7_1_0_release)
++++ b/src/. (.../branches/gcc-7-branch)
+
+Property changes on: .
+___________________________________________________________________
+Added: svn:mergeinfo
+## -0,0 +0,1 ##
+ Merged /trunk:r249272,249411
diff --git a/debian/rules.defs b/debian/rules.defs
index b77eeae..7c681a6 100644
--- a/debian/rules.defs
+++ b/debian/rules.defs
@@ -1404,7 +1404,7 @@ ifneq (,$(filter $(DEB_HOST_ARCH), hppa mips))
with_check := disabled for $(DEB_HOST_ARCH), testsuite timeouts with expect
endif
endif
-#with_check := disabled for this upload
+with_check := disabled for this upload
# not a dependency on all archs, but if available, use it for the testsuite
ifneq (,$(wildcard /usr/bin/localedef))
--
Alioth's /usr/local/bin/git-commit-notice on /srv/git.debian.org/git/reproducible/gcc-7.git
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