[gcc-7] 281/354: * Update to SVN 20170901 (r251583) from the gcc-7-branch.
Ximin Luo
infinity0 at debian.org
Thu Nov 23 15:51:16 UTC 2017
This is an automated email from the git hooks/post-receive script.
infinity0 pushed a commit to branch master
in repository gcc-7.
commit 0bc35ed3d378ab1e0c212ef3385b1b644f6b0e60
Author: doko <doko at 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca>
Date: Fri Sep 1 11:35:40 2017 +0000
* Update to SVN 20170901 (r251583) from the gcc-7-branch.
git-svn-id: svn+ssh://svn.debian.org/svn/gcccvs/branches/sid/gcc-7@9648 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca
---
debian/changelog | 13 +++-
debian/patches/svn-updates.diff | 153 ++++++++++++++++++++++++++++++++++++++--
2 files changed, 156 insertions(+), 10 deletions(-)
diff --git a/debian/changelog b/debian/changelog
index 043c64d..19c7db2 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,4 +1,11 @@
-gcc-7 (7.2.0-2) UNRELEASED; urgency=medium
+gcc-7 (7.2.0-3) unstable; urgency=medium
+
+ * Update to SVN 20170901 (r251583) from the gcc-7-branch.
+ - Fix PR target/81504 (PPC), PR c++/82040.
+
+ -- Matthias Klose <doko at debian.org> Fri, 01 Sep 2017 13:22:28 +0200
+
+gcc-7 (7.2.0-2) unstable; urgency=medium
* Update to SVN 20170830 (r251446) from the gcc-7-branch.
- Fix PR target/72804 (PPC), PR target/80210 (PPC), PR target/81910 (AVR),
@@ -9,11 +16,11 @@ gcc-7 (7.2.0-2) UNRELEASED; urgency=medium
PR middle-end/81884, PR tree-optimization/81181,
PR tree-optimization/81723, PR target/81921 (x86), PR c++/81607.
* Update the Linaro support to the 7-2017.08 snapshot.
- * Restore configuring with on armhf. Closes: #873584.
+ * Restore configuring with --with-mode=thumb on armhf. Closes: #873584.
* Default to PIE on powerpc again, now that PR target/81170 and
PR target/81295 are fixed. Closes: #856224.
- -- Matthias Klose <doko at debian.org> Wed, 30 Aug 2017 07:02:51 +0200
+ -- Matthias Klose <doko at debian.org> Wed, 30 Aug 2017 11:47:42 +0200
gcc-7 (7.2.0-1) unstable; urgency=medium
diff --git a/debian/patches/svn-updates.diff b/debian/patches/svn-updates.diff
index adbc1d9..e6e78f1 100644
--- a/debian/patches/svn-updates.diff
+++ b/debian/patches/svn-updates.diff
@@ -1,10 +1,10 @@
-# DP: updates from the 7 branch upto 20170830 (r251446).
+# DP: updates from the 7 branch upto 20170901 (r251583).
last_update()
{
cat > ${dir}LAST_UPDATED <EOF
-Wed Aug 30 08:55:14 CEST 2017
-Wed Aug 30 06:55:14 UTC 2017 (revision 251446)
+Fri Sep 1 13:21:58 CEST 2017
+Fri Sep 1 11:21:58 UTC 2017 (revision 251583)
EOF
}
@@ -426,7 +426,7 @@ Index: gcc/DATESTAMP
+++ b/src/gcc/DATESTAMP (.../branches/gcc-7-branch)
@@ -1 +1 @@
-20170814
-+20170830
++20170901
Index: gcc/tree.c
===================================================================
--- a/src/gcc/tree.c (.../tags/gcc_7_2_0_release)
@@ -679,7 +679,20 @@ Index: gcc/ChangeLog
===================================================================
--- a/src/gcc/ChangeLog (.../tags/gcc_7_2_0_release)
+++ b/src/gcc/ChangeLog (.../branches/gcc-7-branch)
-@@ -1,3 +1,216 @@
+@@ -1,3 +1,229 @@
++2017-08-31 Bill Schmidt <wschmidt at linux.vnet.ibm.com>
++
++ Backport from mainline
++ 2017-08-25 Bill Schmidt <wschmidt at linux.vnet.ibm.com>
++
++ PR target/81504
++ * config/rs6000/rs6000.c (find_alignment_op): Add reference
++ parameter and_insn and return it.
++ (recombine_lvx_pattern): Insert a copy to ensure availability of
++ the base register of the copied masking operation at the point of
++ the instruction replacement.
++ (recombine_stvx_pattern): Likewise.
++
+2017-08-29 Michael Meissner <meissner at linux.vnet.ibm.com>
+
+ Back port from trunk
@@ -2085,6 +2098,22 @@ Index: gcc/testsuite/g++.dg/other/bitfield6.C
+} d;
+
+char f = (903092 ? int(d.c) : 0) << a;
+Index: gcc/testsuite/g++.dg/warn/Wbool-operation-1.C
+===================================================================
+--- a/src/gcc/testsuite/g++.dg/warn/Wbool-operation-1.C (.../tags/gcc_7_2_0_release)
++++ b/src/gcc/testsuite/g++.dg/warn/Wbool-operation-1.C (.../branches/gcc-7-branch)
+@@ -0,0 +1,11 @@
++// PR c++/82040
++// { dg-do compile { target c++11 } }
++// { dg-options "-Wbool-operation" }
++
++template <class c>
++decltype (~c{})
++call ()
++{
++ return ~false; // { dg-warning "on an expression of type bool" }
++}
++template int call<bool>();
Index: gcc/testsuite/c-c++-common/ubsan/pr81065.c
===================================================================
--- a/src/gcc/testsuite/c-c++-common/ubsan/pr81065.c (.../tags/gcc_7_2_0_release)
@@ -2141,11 +2170,31 @@ Index: gcc/testsuite/c-c++-common/ubsan/pr81088.c
+ i = -(s + (int)(~(unsigned)(0 / y))) + 0x7fffffff;
+ return 0;
+}
+Index: gcc/cp/typeck.c
+===================================================================
+--- a/src/gcc/cp/typeck.c (.../tags/gcc_7_2_0_release)
++++ b/src/gcc/cp/typeck.c (.../branches/gcc-7-branch)
+@@ -5927,6 +5927,7 @@
+ {
+ /* Warn if the expression has boolean value. */
+ if (TREE_CODE (TREE_TYPE (arg)) == BOOLEAN_TYPE
++ && (complain & tf_warning)
+ && warning_at (location, OPT_Wbool_operation,
+ "%<~%> on an expression of type bool"))
+ inform (location, "did you mean to use logical not (%<!%>)?");
Index: gcc/cp/ChangeLog
===================================================================
--- a/src/gcc/cp/ChangeLog (.../tags/gcc_7_2_0_release)
+++ b/src/gcc/cp/ChangeLog (.../branches/gcc-7-branch)
-@@ -1,3 +1,13 @@
+@@ -1,3 +1,21 @@
++2017-09-01 Marek Polacek <polacek at redhat.com>
++
++ Backported from mainline
++ 2017-09-01 Marek Polacek <polacek at redhat.com>
++
++ PR c++/82040
++ * typeck.c (cp_build_unary_op): Avoid re-entering reporting routines.
++
+2017-08-25 Marek Polacek <polacek at redhat.com>
+
+ Backported from mainline
@@ -2159,7 +2208,7 @@ Index: gcc/cp/ChangeLog
2017-08-14 Release Manager
* GCC 7.2.0 released.
-@@ -4,8 +14,8 @@
+@@ -4,8 +22,8 @@
2017-08-09 Leonid Koppel <lkoppel at uwaterloo.ca>
@@ -305096,6 +305145,96 @@ Index: gcc/config/rs6000/rs6000.c
}
+@@ -42693,9 +42702,10 @@
+ }
+
+ /* Given INSN that's a load or store based at BASE_REG, look for a
+- feeding computation that aligns its address on a 16-byte boundary. */
++ feeding computation that aligns its address on a 16-byte boundary.
++ Return the rtx and its containing AND_INSN. */
+ static rtx
+-find_alignment_op (rtx_insn *insn, rtx base_reg)
++find_alignment_op (rtx_insn *insn, rtx base_reg, rtx_insn **and_insn)
+ {
+ df_ref base_use;
+ struct df_insn_info *insn_info = DF_INSN_INFO_GET (insn);
+@@ -42716,8 +42726,8 @@
+ if (DF_REF_IS_ARTIFICIAL (base_def_link->ref))
+ break;
+
+- rtx_insn *and_insn = DF_REF_INSN (base_def_link->ref);
+- and_operation = alignment_mask (and_insn);
++ *and_insn = DF_REF_INSN (base_def_link->ref);
++ and_operation = alignment_mask (*and_insn);
+ if (and_operation != 0)
+ break;
+ }
+@@ -42739,7 +42749,8 @@
+ rtx mem = XEXP (SET_SRC (body), 0);
+ rtx base_reg = XEXP (mem, 0);
+
+- rtx and_operation = find_alignment_op (insn, base_reg);
++ rtx_insn *and_insn;
++ rtx and_operation = find_alignment_op (insn, base_reg, &and_insn);
+
+ if (and_operation != 0)
+ {
+@@ -42763,7 +42774,21 @@
+ to_delete[INSN_UID (swap_insn)].replace = true;
+ to_delete[INSN_UID (swap_insn)].replace_insn = swap_insn;
+
+- XEXP (mem, 0) = and_operation;
++ /* However, first we must be sure that we make the
++ base register from the AND operation available
++ in case the register has been overwritten. Copy
++ the base register to a new pseudo and use that
++ as the base register of the AND operation in
++ the new LVX instruction. */
++ rtx and_base = XEXP (and_operation, 0);
++ rtx new_reg = gen_reg_rtx (GET_MODE (and_base));
++ rtx copy = gen_rtx_SET (new_reg, and_base);
++ rtx_insn *new_insn = emit_insn_after (copy, and_insn);
++ set_block_for_insn (new_insn, BLOCK_FOR_INSN (and_insn));
++ df_insn_rescan (new_insn);
++
++ XEXP (mem, 0) = gen_rtx_AND (GET_MODE (and_base), new_reg,
++ XEXP (and_operation, 1));
+ SET_SRC (body) = mem;
+ INSN_CODE (insn) = -1; /* Force re-recognition. */
+ df_insn_rescan (insn);
+@@ -42786,7 +42811,8 @@
+ rtx mem = SET_DEST (body);
+ rtx base_reg = XEXP (mem, 0);
+
+- rtx and_operation = find_alignment_op (insn, base_reg);
++ rtx_insn *and_insn;
++ rtx and_operation = find_alignment_op (insn, base_reg, &and_insn);
+
+ if (and_operation != 0)
+ {
+@@ -42814,7 +42840,21 @@
+ to_delete[INSN_UID (swap_insn)].replace = true;
+ to_delete[INSN_UID (swap_insn)].replace_insn = swap_insn;
+
+- XEXP (mem, 0) = and_operation;
++ /* However, first we must be sure that we make the
++ base register from the AND operation available
++ in case the register has been overwritten. Copy
++ the base register to a new pseudo and use that
++ as the base register of the AND operation in
++ the new STVX instruction. */
++ rtx and_base = XEXP (and_operation, 0);
++ rtx new_reg = gen_reg_rtx (GET_MODE (and_base));
++ rtx copy = gen_rtx_SET (new_reg, and_base);
++ rtx_insn *new_insn = emit_insn_after (copy, and_insn);
++ set_block_for_insn (new_insn, BLOCK_FOR_INSN (and_insn));
++ df_insn_rescan (new_insn);
++
++ XEXP (mem, 0) = gen_rtx_AND (GET_MODE (and_base), new_reg,
++ XEXP (and_operation, 1));
+ SET_SRC (body) = src_reg;
+ INSN_CODE (insn) = -1; /* Force re-recognition. */
+ df_insn_rescan (insn);
Index: gcc/config/rs6000/vsx.md
===================================================================
--- a/src/gcc/config/rs6000/vsx.md (.../tags/gcc_7_2_0_release)
--
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