[yosys] 41/57: Extended the description in d/control

[Ruben Undheim]

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rubund-guest pushed a commit to branch master
in repository yosys.

commit 7177324393140277afe665d26d729e1589433454
Author: Ruben Undheim <ruben.undheim at gmail.com>
Date:   Wed Sep 10 20:22:05 2014 +0200

    Extended the description in d/control
---
 debian/control | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/debian/control b/debian/control
index 4ec6f57..6f5129f 100644
--- a/debian/control
+++ b/debian/control
@@ -13,5 +13,11 @@ Package: yosys
 Architecture: any
 Depends: ${shlibs:Depends}, ${misc:Depends}, iverilog, graphviz, xdot
 Recommends: abc
-Description: Open source synthesis of digital circuits
- yosys is a complete package for the synthesis from RTL to gate-level logic.
+Description: Yosys Open SYnthesis Suite
+ Yosys is a framework for Verilog RTL synthesis. It currently has extensive
+ Verilog-2005 support and provides a basic set of synthesis algorithms for
+ various application domains.
+ .
+ Yosys can be adapted to perform any synthesis job by combining the existing
+ passes (algorithms) using synthesis scripts and adding additional passes as
+ needed by extending the yosys C++ code base.

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