[yosys] 22/38: Fixed a bug with autowire bit size (removed leftover from when we tried to auto-size the wires)

[Ruben Undheim]

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rubund-guest pushed a commit to tag upstream/0.5.0
in repository yosys.

commit c8305e3a6d1e195391eb6962aac5bf7e1c548b5d
Author: Clifford Wolf <clifford at clifford.at>
Date:   Sun Feb 8 00:48:23 2015 +0100

    Fixed a bug with autowire bit size
    (removed leftover from when we tried to auto-size the wires)
---
 frontends/ast/genrtlil.cc | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 17d62d4..f481019 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1294,15 +1294,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 	// add entries to current_module->connections for assignments (outside of always blocks)
 	case AST_ASSIGN:
 		{
-			if (children[0]->type == AST_IDENTIFIER && children[0]->id2ast && children[0]->id2ast->type == AST_AUTOWIRE) {
-				RTLIL::SigSpec right = children[1]->genRTLIL();
-				RTLIL::SigSpec left = children[0]->genWidthRTLIL(right.size());
-				current_module->connect(RTLIL::SigSig(left, right));
-			} else {
-				RTLIL::SigSpec left = children[0]->genRTLIL();
-				RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.size());
-				current_module->connect(RTLIL::SigSig(left, right));
-			}
+			RTLIL::SigSpec left = children[0]->genRTLIL();
+			RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.size());
+			current_module->connect(RTLIL::SigSig(left, right));
 		}
 		break;
 

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