[yosys] 23/38: Ignore explicit assignments to constants in HDL code

[Ruben Undheim]

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rubund-guest pushed a commit to tag upstream/0.5.0
in repository yosys.

commit 234a45a3d5d4b36e12d40033d58ac2ac3250fa27
Author: Clifford Wolf <clifford at clifford.at>
Date:   Sun Feb 8 00:58:03 2015 +0100

    Ignore explicit assignments to constants in HDL code
---
 frontends/ast/genrtlil.cc | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index f481019..7124866 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1296,6 +1296,20 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 		{
 			RTLIL::SigSpec left = children[0]->genRTLIL();
 			RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.size());
+			if (left.has_const()) {
+				RTLIL::SigSpec new_left, new_right;
+				for (int i = 0; i < GetSize(left); i++)
+					if (left[i].wire) {
+						new_left.append(left[i]);
+						new_right.append(right[i]);
+					}
+				log_warning("Ignoring assignment to constant bits at %s:%d:\n"
+						"    old assignment: %s = %s\n    new assignment: %s = %s.\n",
+						filename.c_str(), linenum, log_signal(left), log_signal(right),
+						log_signal(new_left), log_signal(new_right));
+				left = new_left;
+				right = new_right;
+			}
 			current_module->connect(RTLIL::SigSig(left, right));
 		}
 		break;

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