[yosys] 34/38: Fixed iterator invalidation bug in "rename" command

[Ruben Undheim]

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rubund-guest pushed a commit to tag upstream/0.5.0
in repository yosys.

commit f889e3d38524bb3cb6a10ccd33f788e987c6e14e
Author: Clifford Wolf <clifford at clifford.at>
Date:   Mon Feb 9 00:18:36 2015 +0100

    Fixed iterator invalidation bug in "rename" command
---
 passes/cmds/rename.cc | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index 8f24af2..17d803e 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -34,9 +34,10 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
 
 	for (auto &it : module->wires_)
 		if (it.first == from_name) {
-			log("Renaming wire %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module));
-			module->rename(it.second, to_name);
-			if (it.second->port_id)
+			Wire *w = it.second;
+			log("Renaming wire %s to %s in module %s.\n", log_id(w), log_id(to_name), log_id(module));
+			module->rename(w, to_name);
+			if (w->port_id)
 				module->fixup_ports();
 			return;
 		}

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