[yosys] 35/38: Various presentation fixes

[Ruben Undheim]

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rubund-guest pushed a commit to tag upstream/0.5.0
in repository yosys.

commit 85887de547fa557f00ebaa5b29091bc420794c22
Author: Clifford Wolf <clifford at clifford.at>
Date:   Mon Feb 9 12:02:21 2015 +0100

    Various presentation fixes
---
 manual/PRESENTATION_ExSyn.tex |  2 +-
 manual/PRESENTATION_Prog.tex  | 21 ++++++++++++++-------
 2 files changed, 15 insertions(+), 8 deletions(-)

diff --git a/manual/PRESENTATION_ExSyn.tex b/manual/PRESENTATION_ExSyn.tex
index f0dd96e..b7d6b8a 100644
--- a/manual/PRESENTATION_ExSyn.tex
+++ b/manual/PRESENTATION_ExSyn.tex
@@ -268,7 +268,7 @@ memory -nomap; techmap -map my_memory_map.v; memory_map
 \end{frame}
 
 \begin{frame}[t, fragile]{\subsecname{} -- Example 1/2}
-\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -6cm]{PRESENTATION_ExSyn/memory_01.pdf}\vss}
+\vbox to 0cm{\includegraphics[width=0.7\linewidth,trim=0cm 0cm 0cm -10cm]{PRESENTATION_ExSyn/memory_01.pdf}\vss}
 \vskip-1cm
 \begin{columns}
 \column[t]{5cm}
diff --git a/manual/PRESENTATION_Prog.tex b/manual/PRESENTATION_Prog.tex
index d400245..96189e5 100644
--- a/manual/PRESENTATION_Prog.tex
+++ b/manual/PRESENTATION_Prog.tex
@@ -123,8 +123,9 @@ has been executed.
 \subsection{The RTLIL Data Structures}
 
 \begin{frame}{\subsecname}
-The RTLIL data structures are simple structs utilizing C++ {\tt std::}
-containers.
+The RTLIL data structures are simple structs utilizing {\tt pool<>} and
+{\tt dict<>} containers (drop-in replacementments for {\tt
+std::unordered\_set<>} and {\tt std::unordered\_map<>}).
 
 \bigskip
 \begin{itemize}
@@ -176,14 +177,14 @@ data structures. Yosys always operates on one active design, but can hold many d
 \bigskip
 \begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
 struct RTLIL::Design {
-    std::map<RTLIL::IdString, RTLIL::Module*> modules_;
+    dict<RTLIL::IdString, RTLIL::Module*> modules_;
     ...
 };
 
 struct RTLIL::Module {
     RTLIL::IdString name;
-    std::map<RTLIL::IdString, RTLIL::Wire*> wires_;
-    std::map<RTLIL::IdString, RTLIL::Cell*> cells_;
+    dict<RTLIL::IdString, RTLIL::Wire*> wires_;
+    dict<RTLIL::IdString, RTLIL::Cell*> cells_;
     std::vector<RTLIL::SigSig> connections_;
     ...
 };
@@ -293,8 +294,8 @@ instances:
 \begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=C++]
 struct RTLIL::Cell {
     RTLIL::IdString name, type;
-    std::map<RTLIL::IdString, RTLIL::SigSpec> connections_;
-    std::map<RTLIL::IdString, RTLIL::Const> parameters;
+    dict<RTLIL::IdString, RTLIL::SigSpec> connections_;
+    dict<RTLIL::IdString, RTLIL::Const> parameters;
     ...
 };
 \end{lstlisting}
@@ -555,6 +556,12 @@ yosys-config --exec --cxx --cxxflags --ldflags \
 \end{lstlisting}
 
 \bigskip
+Or shorter:
+\begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont]
+yosys-config --build my_cmd.so my_cmd.cc
+\end{lstlisting}
+
+\bigskip
 Load the plugin using the yosys {\tt -m} option:
 \begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont]
 yosys -m ./my_cmd.so -p 'my_cmd foo bar'

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