[yosys] branch master updated (f2a2faf -> 022827a)
Ruben Undheim
rubund-guest at moszumanska.debian.org
Fri Jul 24 10:18:52 UTC 2015
This is an automated email from the git hooks/post-receive script.
rubund-guest pushed a change to branch master
in repository yosys.
from f2a2faf Refreshed patch again
adds 7ad1791 appnote for verilog to btor
adds 6c6cdf7 appnote added
adds 3dd316b corrections in appnote
adds 6460d09 removed unused bib
adds d944487 corrected abstract of appnote
adds 8acdd90 Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys into btor
adds e0ff4d1 We are now in 0.5+ development
adds a779a09 Fixed creation of command reference in manual
adds 68979d1 Various changes to release checklist
adds adf4ecb Some hashlib improvements
adds 510deb3 Added "scc -expect <N> -nofeedback"
adds 4f68a77 Improved read_verilog support for empty behavioral statements
adds 87819c6 Less aggressive "share" defaults
adds 554a8df Added "proc_dlatch"
adds d58c3ec Some test related fixes
adds 2f0edff Added EMCCFLAGS
adds cd919ab Added AstNode::simplify() recursion counter
adds 04cb947 Added "check" command
adds a0a0594 hotfix in "check" command
adds 756b406 Fixed "write_verilog -attr2comment" handling of "*/" in strings
adds ef151b0 Fixed handling of "//" in filenames in verilog pre-processor
adds 9105565 Added $meminit cell type
adds a8e9d37 Creating $meminit cells in verilog front-end
adds 7f1a175 Added "read_verilog -nomeminit" and "nomeminit" attribute
adds 913c304 Added $meminit test case
adds dcf2e24 Added $meminit support to "memory" command
adds e9368a1 Various fixes for memories with offsets
adds c6ae9eb Fixed "stat" handling of blackbox modules
adds ec05242 Smaller default parameters in $mem simlib model
adds 86819cc Fixed default EMCCFLAGS
adds 3216f94 More emscripten stuff, Added example app
adds a54c994 Cosmetic fixes in "hierarchy" for blackbox modules
adds 40f021e Added "check -noinit"
adds 881dcd8 Added final checks to "synth" and "synth_xilinx"
adds 4d34d03 Added "stat" to "synth" and "synth_xilinx"
adds c2cc342 Improved yosys.js example
adds 8d45f81 More emcc stuff
adds 549d56b Added yosys.js FS support
adds 0283703 Added Viz to yosys.js
adds 162432a More yosys.js improvements
adds 0748ef6 Bugfix in wreduce
adds 33e80b9 Added YosysJS wrapper
adds 3e5e9a3 More YosysJS stuff
adds 4c22195 YosysJS fixes for firefox
adds 5f54be5 Added "select %xe %cie %coe"
adds 138547f CodingReadme
adds 024aa55 wreduce help typo fix
adds e4cf604 Merge branch 'master' of github.com:cliffordwolf/yosys
adds f41378a Fixed clang (svn trunk) warnings
adds c2ba4fb Convert floating point cell parameters to strings
adds 20eb5ca Changed "show" defaults for Win32
adds 1ecee6c Added "sat -dump_json" (WaveJSON format)
adds 08c0fe1 format fixes in "sat -dump_json"
adds e0e6d13 YosysJS stuff
adds 78b991d YosysJS firefox fixes
adds dc1a0f0 Parser support for complex delay expressions
adds d5ce9a3 Added deep recursion warning to AST simplify
adds f778a40 Catch constants assigned to cell outputs in "flatten"
adds 4e6ca77 Replaced ezDefaultSAT with ezSatPtr
adds 1fe15a5 YosysJS: Wait for Viz to load
adds 1f6737f Hotfix for yosysjs/demo03.html
adds 49dd9c7 Fixed "flatten" for non-pre-derived modules
adds dcbd00c Fixed basecase init for "sat -tempinduct"
adds 1688b9b Added "sat -tempinduct-baseonly -tempinduct-inductonly"
adds 9237fb9 When "sat -tempinduct-baseonly -maxsteps N" reaches maxsteps it is a good thing.
adds b19c926 sat docu change
adds fae0e75 Added "sat -stepsize" and "sat -tempinduct-step"
adds 39d25b2 Fixed "sat -initsteps" off-by-one bug
adds e8307ce Added "check -assert"
adds d361d31 Added "check -assert" doc
adds 4b89dd9 Added "<mod>_a" and "<mod>_i" to write_smt2 output
adds c4f383e Fixed "check -assert"
adds ff3f244 Minor "write_smt2" help msg change
adds 81fa4e8 Fixed compilation problems with gcc 4.6.3; use enum instead of const ints. (original patch by Andrew Becker <andrew.becker at epfl.ch>)
adds 9ae2126 Some cleanups in "clean"
adds 331f8b8 Bugfix in iopadmap
adds 3fe18c2 Added "keep_hierarchy" attribute
adds 27a918e Merge branch 'master' of github.com:cliffordwolf/yosys
adds b005eed Added $assume cell type
adds 1f1deda Added non-std verilog assume() statement
adds 5d4f513 Added $assume support to write_smt2
adds 422794c Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker()
adds 8b48898 Added JSON backend
adds 795a6e1 Added write_blif -attr
adds 4fc63f2 Json backend improvements
adds adc12ce Json bugfix
adds ed15400 Fixed bug in "hierarchy" for parametric designs
adds 42d5d94 Added very first version of "synth_ice40"
adds 6c8fdb1 Documentation for JSON format, added attributes
adds 67e6dcd Added Verilog backend $dffsr support
adds aed4d76 Added hierarchy -auto-top
adds 604c097 fix for python 2.6.6
adds 8b1e0bd Fixed handling of quotes in liberty parser
adds 6f8547b Merge branch 'master' of github.com:cliffordwolf/yosys
adds 611cd01 Added blif reference to appnote 010
adds 68bbb15 Fixed detection of absolute paths in ABC for win32
adds e468d4c Fixes in cmos_cells.v
adds a923a63 Ignore celldefine directive in verilog front-end
adds 4b44907 documentation improvements
adds bdf6b2b Merge branch 'master' of https://github.com/cliffordwolf/yosys
adds ea2e029 separated memory next from write cell
adds e82e4f7 Update README
adds ed750f0 Delete btor.ys
adds 13e2e71 Update README
adds 3b6ebb6 Merge pull request #55 from ahmedirfan1983/master
adds 082550f Updated ABC to 51705b168d7a
adds 1d5d1f7 Appnote 012
adds 0737bf5 appnote 012 fix
adds b0c0ede Added "init" attribute support to verilog backend
adds c52a4cd Added "dffinit", Support for initialized Xilinx DFF
adds 7066312 Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types
adds 95944eb make all vector-size related integer params in $mem sim model signed
adds a1c62b7 Avoid parameter values with size 0 ($mem cells)
adds c0e2b3e Added "port_directions" to write_json output
adds 4389d93 Added Xilinx bram black-box modules
adds d198666 Added Xilinx test case for initialized brams
adds 169d1c4 Added support for initialized brams
adds 8520b7f Added support for initialized xilinx brams
adds 329b841 Added "chparam" command
adds c1af590 typo fix
adds b31e77f Added pool<K>::pop()
adds f7fb21f Added "muxcover" command
adds aae5f2c Added hashlib support for std::tuple<>
adds 590f74d Added decoder generation to "muxcover"
adds 1f33b2a Added "chparam -list"
adds 724cead Added "pmuxtree" command
adds 8eadd8f Added %M and %C select operators
adds aa0ab97 Removed "techmap -share_map" (use "-map +/filename" instead)
adds 21a1cc1 Added support for "file names with blanks"
adds b00cad8 Towards DRAM support in Xilinx flow
adds be7b9b3 techmap code cleanup
adds 25781e3 Fixed const2big performance bug
adds 229825e Xilinx DRAMS: RAM64X1D, RAM128X1D
adds d176e61 Minor fixes in handling of "init" attribute
adds 44519d4 Added back-end auto-detect for .edif and .json
adds 7319951 Added memory_bram "make_outreg" feature
adds 3481f46 Improved xilinx "bram1" test
adds e305d85 Added handling of bool-output cells to "wreduce"
adds 2fc2f8f Added "splice -wires"
adds 06ce496 more cells in ice40 cell library
adds 4529c56 use "hierarchy -auto-top" in synth_ice40
adds f80d020 Added "dff2dffe -direct-match"
adds 0d344a2 improved ice40 dff cell mapping
adds 3e9e6e1 Added simple ice40 dff tests
adds dc30b03 Fixed "dff2dffe -direct-match"
adds 31755ed Changed ice40 ICESTORM_CARRYCONST port name
adds cfdc9fc A "#" does start a comment, not a label.
adds e050467 Improved "maccmap" help message
adds 661b647 Added mapping of synchronous set/reset to iCE40 flow
adds 8cdbcf6 Bugfix for $_DFF_?_ in "dff2dffe -direct-match"
adds 9041f34 Improved handling of init values in opt_rmdff
adds faa95dd don't consider blackbox modules in "sat" command
adds f78fa71 Added ice40 SB_CARRY support
adds f564a65 Added ice40 test_arith
adds 49ef830 added sync reset to ice40 test_ffs.sh
adds 7ff802e Verilog front-end: define `BLACKBOX in -lib mode
adds 1277d1b iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* models
adds 11f7720 Fixed memory_share for unconditional write with part select to memory
adds d6f7698 Added ice40 bram support
adds 308a59a iCE40 bram tests and fixes
adds 687f5a5 iCE40 bram progress
adds 4985939 Improved attributes API and handling of "src" attributes
adds 82a4722 More iCE40 bram improvements
adds bd05971 Updated ABC to hg rev 779de2de1481
adds 4cc4400 improved iCE40 SB_RAM40_4K simulation model
adds b4d7a59 initialized iCE40 brams (mode 0)
adds 7528519 Initialization support for all iCE40 bram modes
adds 8d4a675 Added iCE40 const folding support for SB_CARRY
adds 794d229 Added simplemap $lut support
adds 310fde1 iCE40: SB_CARRY const fold -> unmap SB_LUT
adds 9d067fe ice40_opt bugfix
adds f483dce Added $eq/$neq -> $logic_not/$reduce_bool optimization
adds 96be31d Preserve important attributes in splitnets
adds 7462618 Fixed memory_unpack for initialized memories
adds c0b68f4 Added support for $mem cells in the verilog backend.
adds 2c1e150 Verilog backend for $mem cells should now be able to handle different write-enable bits and RD_TRANSPARENT parameter settings.
adds 6de8fea Made changes recommended by Clifford Wolf ...
adds e47218e Merge pull request #62 from wluker/verilog-backend-mem
adds 9e56739 Disabled broken $mem support in verilog backend
adds 3bb5f06 Fixed bug in $mem cell verilog code generation.
adds 42348cd Merge pull request #63 from wluker/verilog-backend-mem
adds dae00e1 changed file() to open() in python scripts
adds c2f30e0 Added .barbuf support to abc BLIF parser
adds 61512b6 Verific build fixes
adds 7dad017 abc/blifparse files reorganization
adds e5116ee Generalized blifparse API
adds 2cc4e75 Added read_blif command
adds 3ecb2bf Improved .latch support in BLIF front-end
adds 83499dc added vloghtb test_febe.sh
adds 6061b7b bugfix in blif front-end
adds e122c26 preserve used $-wires with init attribute in opt_clean
adds 4744bb9 Some fixes for $mem in verilog back-end
adds 98bceed Merge branch 'master' of github.com:cliffordwolf/yosys
adds 264eb8e Added ice40 SB_IO sim model
adds 4b62214 Added simple $dlatch support to opt_rmdff
adds 9f772eb Improved "flatten" handlings of inout ports
adds 313f570 improved ice40 SB_IO sim model
adds 08a4af3 Improvements in BLIF front-end
adds c329233 Added output args to synth_ice40
adds 99b8746 Fixed signedness of genvar expressions
adds 522705c Added liberty dont_use support to dfflibmap
adds 09ef279 Added iCE40 PLL cells
adds 08f9b38 Added opt_share -share_all
adds 13983e8 Fixed handling of parameters with reversed range
adds 98650a0 Added log_dump() support for IdStrings
adds de4f4da Fixed "avail_parameters" handling in module clone/copy
adds a8fe040 Bug fix in $mem verilog backend + changed tests/bram flow of make test.
adds 2f90499 $mem cell in verilog backend : grouped writes by clock
adds c88be7b Merge branch 'verilog-backend-memV2' of github.com:wluker/yosys
adds b57cb4a Merge clock inverters in memory_dff
adds e49e266 Added cellaigs API
adds 9500b56 synth_ice40 now flattens by default
adds 66f9ee4 Added "aig" pass
adds 8528729 Fixed cellaigs port extending
adds 56d4822 Renamed "aig" to "aigmap"
adds e534881 Added "json -aig"
adds 1ae360c AigMaker refactoring
adds 3a6abc9 Improvements in cellaigs.cc and "json -aig"
adds 4c73330 Fixed cstr_buf for std::string with small string optimization
adds 285f140 Makefile fix for YosysJS build
adds 255dcb2 Added write_smt2 -mem
adds f6eca50 Added "memory -nordff"
adds 66910e1 Modernized memory_dff (and fixed a bug)
adds 93685a7 Removed debug code from write_smt2
adds ea23bb8 Added "write_smv" skeleton
adds 0f01ef6 Progress in SMV back-end
adds 5231503 Progress in SMV back-end
adds ed128b8 Added "synth -nordff -noalumacc"
adds b8c5e27 Progress in SMV back-end
adds 9f7a5b4 Progress in SMV back-end
adds 99100f3 Added "rename -top new_name"
adds 8e84418 Progress in SMV back-end
adds 8a86162 Progress in SMV back-end
adds 8c79765 Progress in SMV back-end
adds 6c6bf49 Progress in SMV back-end
adds 3123c45 Added init support to SMV back-end
adds 94fbaff Using static mem size of 128 MB in emcc build
adds df0163c iCE40: set min bram efficiency to 2%
adds caa274a Added design->rename(module, new_name)
adds 77e8939 Bugfix in chparam
adds 358e415 Added YosysJS.create_worker()
adds 7987f23 Merge branch 'master' of github.com:cliffordwolf/yosys
adds ee9188a Added logic-loop error handling to freduce
adds 053058d Added opt_const -clkinv
adds 6c84341 Fixed trailing whitespaces
adds f0c9a09 Added "synth -nofsm"
adds 766dd51 Bugfix in fsm_extract
adds c4dde71 Improved YosysJS WebWorker API
adds d2ff5d9 Do not collect disabled $memwr cells
adds 3049a08 Updated ABC
adds 85aaf08 Improved liberty file test case
adds 55acc51 Fixed YosysJS.create_worker() usage of this.url_prefix
adds 8393f70 Some fixes in "select" command
adds 54588a2 Avoid tristate warning for blackbox ice40/cells_sim.v
adds ad919ae Fixed techmap processes error msg
adds c6ca478 iCE40 DFF sim models: init Q regs to 0
new 96fc55d Merge branch 'upstream'
new 022827a Refreshed patches for new version
The 2 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
.gitignore | 6 +-
CodingReadme | 99 ++-
Makefile | 46 +-
README | 17 +-
backends/blif/blif.cc | 58 +-
backends/btor/README | 6 +-
backends/btor/btor.cc | 220 ++++--
backends/btor/btor.ys | 18 -
backends/btor/verilog2btor.sh | 14 +-
backends/edif/edif.cc | 4 +-
backends/ilang/ilang_backend.cc | 6 +-
backends/ilang/ilang_backend.h | 4 +-
backends/intersynth/intersynth.cc | 6 +-
backends/json/Makefile.inc | 3 +
backends/json/json.cc | 538 +++++++++++++
backends/smt2/smt2.cc | 398 +++++++---
backends/smv/Makefile.inc | 3 +
backends/smv/smv.cc | 755 ++++++++++++++++++
backends/spice/spice.cc | 6 +-
backends/verilog/verilog_backend.cc | 305 +++++++-
debian/changelog | 6 +
debian/patches/01_gitrevision.patch | 8 +-
debian/patches/02_removeabc.patch | 6 +-
debian/patches/03_notruntests.patch | 8 +-
debian/patches/04_installpath.patch | 6 +-
debian/patches/05_abc_executable.patch | 8 +-
debian/patches/06_cflags_ldflags.patch | 8 +-
frontends/ast/ast.cc | 18 +-
frontends/ast/ast.h | 14 +-
frontends/ast/dpicall.cc | 4 +-
frontends/ast/genrtlil.cc | 67 +-
frontends/ast/simplify.cc | 115 ++-
frontends/blif/Makefile.inc | 3 +
{passes/abc => frontends/blif}/blifparse.cc | 181 ++++-
{passes/abc => frontends/blif}/blifparse.h | 6 +-
frontends/ilang/ilang_frontend.cc | 4 +-
frontends/ilang/ilang_frontend.h | 4 +-
frontends/ilang/ilang_lexer.l | 4 +-
frontends/ilang/ilang_parser.y | 4 +-
frontends/liberty/liberty.cc | 6 +-
frontends/verific/build_amd64.txt | 2 +-
frontends/verific/verific.cc | 8 +-
frontends/verilog/const2ast.cc | 4 +-
frontends/verilog/preproc.cc | 8 +-
frontends/verilog/verilog_frontend.cc | 35 +-
frontends/verilog/verilog_frontend.h | 7 +-
frontends/verilog/verilog_lexer.l | 16 +-
frontends/verilog/verilog_parser.y | 56 +-
frontends/vhdl2verilog/vhdl2verilog.cc | 6 +-
kernel/bitpattern.h | 6 +-
kernel/calc.cc | 39 +-
kernel/cellaigs.cc | 481 ++++++++++++
passes/abc/blifparse.h => kernel/cellaigs.h | 31 +-
kernel/celltypes.h | 18 +-
kernel/consteval.h | 4 +-
kernel/cost.h | 4 +-
kernel/driver.cc | 53 +-
kernel/hashlib.h | 73 +-
kernel/log.cc | 31 +-
kernel/log.h | 6 +-
kernel/macc.h | 4 +-
kernel/modtools.h | 4 +-
kernel/register.cc | 36 +-
kernel/register.h | 8 +-
kernel/rtlil.cc | 122 ++-
kernel/rtlil.h | 84 +-
kernel/satgen.h | 66 +-
kernel/sigtools.h | 4 +-
kernel/utils.h | 6 +-
kernel/yosys.cc | 75 +-
kernel/yosys.h | 23 +-
libs/ezsat/demo_bit.cc | 4 +-
libs/ezsat/demo_cmp.cc | 4 +-
libs/ezsat/demo_vec.cc | 4 +-
libs/ezsat/ezminisat.cc | 4 +-
libs/ezsat/ezminisat.h | 4 +-
libs/ezsat/ezsat.cc | 6 +-
libs/ezsat/ezsat.h | 4 +-
libs/ezsat/puzzle3d.cc | 6 +-
libs/ezsat/testbench.cc | 8 +-
libs/subcircuit/README | 4 +-
libs/subcircuit/subcircuit.cc | 4 +-
libs/subcircuit/subcircuit.h | 6 +-
libs/subcircuit/test_large.spl | 2 +-
manual/APPNOTE_010_Verilog_to_BLIF.tex | 12 +-
manual/APPNOTE_011_Design_Investigation.tex | 40 +-
manual/APPNOTE_012_Verilog_to_BTOR.tex | 435 +++++++++++
manual/CHAPTER_Appnotes.tex | 2 +-
manual/CHAPTER_Basics.tex | 8 +-
manual/CHAPTER_CellLib.tex | 2 +-
manual/CHAPTER_Eval/grep-it.sh | 2 +-
manual/CHAPTER_Intro.tex | 6 +-
manual/CHAPTER_Optimize.tex | 2 +-
manual/CHAPTER_Overview.tex | 10 +-
manual/CHAPTER_Prog/stubnets.cc | 2 +-
manual/CHAPTER_StateOfTheArt/simlib_hana.v | 204 ++---
manual/CHAPTER_StateOfTheArt/simlib_yosys.v | 4 +-
manual/CHAPTER_Verilog.tex | 8 +-
manual/PRESENTATION_ExAdv.tex | 6 +-
manual/PRESENTATION_ExAdv/addshift_map.v | 8 +-
manual/PRESENTATION_ExAdv/red_or3x1_map.v | 6 +-
manual/PRESENTATION_ExAdv/sym_mul_map.v | 6 +-
manual/PRESENTATION_ExOth.tex | 4 +-
manual/PRESENTATION_ExSyn.tex | 2 +-
manual/PRESENTATION_Intro/counter.ys | 2 +-
manual/PRESENTATION_Prog.tex | 2 +-
manual/appnotes.sh | 2 +-
manual/command-reference-manual.tex | 12 +-
misc/yosysjs/demo01.html | 197 +++++
misc/yosysjs/demo02.html | 103 +++
misc/yosysjs/demo03.html | 103 +++
misc/yosysjs/yosysjs.js | 312 ++++++++
misc/yosysjs/yosyswrk.js | 63 ++
passes/abc/Makefile.inc | 6 -
passes/cmds/Makefile.inc | 1 +
passes/cmds/add.cc | 6 +-
passes/cmds/check.cc | 154 ++++
passes/cmds/connect.cc | 6 +-
passes/cmds/connwrappers.cc | 6 +-
passes/cmds/copy.cc | 6 +-
passes/cmds/delete.cc | 6 +-
passes/cmds/design.cc | 4 +-
passes/cmds/rename.cc | 31 +-
passes/cmds/scatter.cc | 6 +-
passes/cmds/scc.cc | 61 +-
passes/cmds/select.cc | 90 ++-
passes/cmds/setattr.cc | 113 ++-
passes/cmds/setundef.cc | 6 +-
passes/cmds/show.cc | 22 +-
passes/cmds/splice.cc | 35 +-
passes/cmds/splitnets.cc | 19 +-
passes/cmds/stat.cc | 21 +-
passes/equiv/equiv_add.cc | 4 +-
passes/equiv/equiv_induct.cc | 39 +-
passes/equiv/equiv_make.cc | 4 +-
passes/equiv/equiv_miter.cc | 4 +-
passes/equiv/equiv_remove.cc | 4 +-
passes/equiv/equiv_simple.cc | 26 +-
passes/equiv/equiv_status.cc | 4 +-
passes/fsm/fsm.cc | 6 +-
passes/fsm/fsm_detect.cc | 6 +-
passes/fsm/fsm_expand.cc | 6 +-
passes/fsm/fsm_export.cc | 4 +-
passes/fsm/fsm_extract.cc | 31 +-
passes/fsm/fsm_info.cc | 6 +-
passes/fsm/fsm_map.cc | 6 +-
passes/fsm/fsm_opt.cc | 10 +-
passes/fsm/fsm_recode.cc | 10 +-
passes/fsm/fsmdata.h | 4 +-
passes/hierarchy/hierarchy.cc | 85 +-
passes/hierarchy/submod.cc | 6 +-
passes/memory/memory.cc | 17 +-
passes/memory/memory_bram.cc | 75 +-
passes/memory/memory_collect.cc | 135 ++--
passes/memory/memory_dff.cc | 302 +++----
passes/memory/memory_map.cc | 33 +-
passes/memory/memory_share.cc | 23 +-
passes/memory/memory_unpack.cc | 23 +-
passes/opt/Makefile.inc | 4 +-
passes/opt/opt.cc | 37 +-
passes/opt/opt_clean.cc | 35 +-
passes/opt/opt_const.cc | 114 ++-
passes/opt/opt_muxtree.cc | 6 +-
passes/opt/opt_reduce.cc | 6 +-
passes/opt/opt_rmdff.cc | 61 +-
passes/opt/opt_share.cc | 37 +-
passes/opt/share.cc | 40 +-
passes/opt/wreduce.cc | 38 +-
passes/proc/Makefile.inc | 1 +
passes/proc/proc.cc | 11 +-
passes/proc/proc_arst.cc | 11 +-
passes/proc/proc_clean.cc | 6 +-
passes/proc/proc_dff.cc | 6 +-
passes/proc/proc_dlatch.cc | 308 ++++++++
passes/proc/proc_init.cc | 6 +-
passes/proc/proc_mux.cc | 6 +-
passes/proc/proc_rmdead.cc | 6 +-
passes/sat/eval.cc | 28 +-
passes/sat/expose.cc | 6 +-
passes/sat/freduce.cc | 71 +-
passes/sat/miter.cc | 8 +-
passes/sat/sat.cc | 406 +++++++---
passes/techmap/Makefile.inc | 10 +
passes/{abc => techmap}/abc.cc | 112 ++-
passes/techmap/aigmap.cc | 149 ++++
passes/techmap/alumacc.cc | 6 +-
passes/techmap/dff2dffe.cc | 72 +-
passes/techmap/dffinit.cc | 121 +++
passes/techmap/dfflibmap.cc | 14 +-
passes/techmap/extract.cc | 10 +-
passes/techmap/hilomap.cc | 6 +-
passes/techmap/iopadmap.cc | 19 +-
passes/techmap/libparse.cc | 12 +-
passes/techmap/libparse.h | 4 +-
passes/techmap/maccmap.cc | 10 +-
passes/techmap/muxcover.cc | 632 +++++++++++++++
passes/techmap/pmuxtree.cc | 112 +++
passes/techmap/simplemap.cc | 62 +-
passes/techmap/simplemap.h | 5 +-
passes/techmap/techmap.cc | 156 ++--
passes/tests/test_abcloop.cc | 24 +-
passes/tests/test_autotb.cc | 8 +-
passes/tests/test_cell.cc | 17 +-
techlibs/cmos/cmos_cells.lib | 3 +-
techlibs/cmos/cmos_cells.v | 15 +-
techlibs/cmos/counter.v | 2 +-
techlibs/common/simcells.v | 33 +-
techlibs/common/simlib.v | 81 +-
techlibs/common/synth.cc | 67 +-
techlibs/common/techmap.v | 16 +-
techlibs/ice40/.gitignore | 4 +
techlibs/ice40/Makefile.inc | 29 +
techlibs/{xilinx => ice40}/arith_map.v | 59 +-
techlibs/ice40/brams.txt | 40 +
techlibs/ice40/brams_init.py | 17 +
techlibs/ice40/brams_map.v | 309 ++++++++
techlibs/ice40/cells_map.v | 57 ++
techlibs/ice40/cells_sim.v | 867 +++++++++++++++++++++
techlibs/ice40/ice40_ffssr.cc | 123 +++
techlibs/ice40/ice40_opt.cc | 170 ++++
.../synth_xilinx.cc => ice40/synth_ice40.cc} | 154 +++-
techlibs/ice40/tests/.gitignore | 2 +
techlibs/ice40/tests/test_arith.v | 3 +
techlibs/ice40/tests/test_arith.ys | 10 +
techlibs/ice40/tests/test_bram.sh | 19 +
techlibs/ice40/tests/test_bram.v | 24 +
.../bram1_tb.v => ice40/tests/test_bram_tb.v} | 48 +-
techlibs/ice40/tests/test_ffs.sh | 20 +
techlibs/ice40/tests/test_ffs.v | 42 +
techlibs/xilinx/.gitignore | 2 +
techlibs/xilinx/Makefile.inc | 25 +
techlibs/xilinx/arith_map.v | 4 +-
techlibs/xilinx/brams.txt | 6 +-
techlibs/xilinx/brams_bb.v | 319 ++++++++
techlibs/xilinx/brams_init.py | 37 +
techlibs/xilinx/brams_map.v | 232 ++++--
techlibs/xilinx/drams.txt | 36 +
techlibs/xilinx/drams_bb.v | 20 +
techlibs/xilinx/drams_map.v | 63 ++
techlibs/xilinx/synth_xilinx.cc | 47 +-
techlibs/xilinx/tests/.gitignore | 3 +
techlibs/xilinx/tests/bram1.sh | 3 +-
techlibs/xilinx/tests/bram1.v | 17 +
techlibs/xilinx/tests/bram1_tb.v | 52 +-
techlibs/xilinx/tests/bram2.sh | 8 +
techlibs/xilinx/tests/bram2.v | 35 +
techlibs/xilinx/tests/bram2_tb.v | 56 ++
tests/asicworld/code_hdl_models_dlatch_reset.v | 30 -
tests/asicworld/code_hdl_models_ram_sp_ar_sw.v | 58 --
tests/asicworld/code_hdl_models_ram_sp_sr_sw.v | 62 --
tests/bram/generate.py | 8 +-
tests/fsm/generate.py | 148 ++--
tests/realmath/generate.py | 103 +--
tests/share/generate.py | 94 +--
tests/simple/loops.v | 6 +-
tests/simple/mem2reg.v | 2 +-
tests/simple/memory.v | 23 +
tests/simple/omsp_dbg_uart.v | 4 +-
tests/{bram => smv}/.gitignore | 0
tests/smv/run-single.sh | 33 +
tests/smv/run-test.sh | 19 +
tests/techmap/mem_simple_4x1_map.v | 5 +
tests/tools/autotest.sh | 2 +-
tests/various/muxcover.ys | 51 ++
tests/vloghtb/common.sh | 36 +
tests/vloghtb/test_febe.sh | 13 +
266 files changed, 11824 insertions(+), 2280 deletions(-)
delete mode 100644 backends/btor/btor.ys
create mode 100644 backends/json/Makefile.inc
create mode 100644 backends/json/json.cc
create mode 100644 backends/smv/Makefile.inc
create mode 100644 backends/smv/smv.cc
create mode 100644 frontends/blif/Makefile.inc
rename {passes/abc => frontends/blif}/blifparse.cc (54%)
copy {passes/abc => frontends/blif}/blifparse.h (91%)
create mode 100644 kernel/cellaigs.cc
rename passes/abc/blifparse.h => kernel/cellaigs.h (69%)
create mode 100644 manual/APPNOTE_012_Verilog_to_BTOR.tex
create mode 100644 misc/yosysjs/demo01.html
create mode 100644 misc/yosysjs/demo02.html
create mode 100644 misc/yosysjs/demo03.html
create mode 100644 misc/yosysjs/yosysjs.js
create mode 100644 misc/yosysjs/yosyswrk.js
delete mode 100644 passes/abc/Makefile.inc
create mode 100644 passes/cmds/check.cc
create mode 100644 passes/proc/proc_dlatch.cc
rename passes/{abc => techmap}/abc.cc (87%)
create mode 100644 passes/techmap/aigmap.cc
create mode 100644 passes/techmap/dffinit.cc
create mode 100644 passes/techmap/muxcover.cc
create mode 100644 passes/techmap/pmuxtree.cc
create mode 100644 techlibs/ice40/.gitignore
create mode 100644 techlibs/ice40/Makefile.inc
copy techlibs/{xilinx => ice40}/arith_map.v (70%)
create mode 100644 techlibs/ice40/brams.txt
create mode 100644 techlibs/ice40/brams_init.py
create mode 100644 techlibs/ice40/brams_map.v
create mode 100644 techlibs/ice40/cells_map.v
create mode 100644 techlibs/ice40/cells_sim.v
create mode 100644 techlibs/ice40/ice40_ffssr.cc
create mode 100644 techlibs/ice40/ice40_opt.cc
copy techlibs/{xilinx/synth_xilinx.cc => ice40/synth_ice40.cc} (53%)
create mode 100644 techlibs/ice40/tests/.gitignore
create mode 100644 techlibs/ice40/tests/test_arith.v
create mode 100644 techlibs/ice40/tests/test_arith.ys
create mode 100644 techlibs/ice40/tests/test_bram.sh
create mode 100644 techlibs/ice40/tests/test_bram.v
copy techlibs/{xilinx/tests/bram1_tb.v => ice40/tests/test_bram_tb.v} (68%)
create mode 100644 techlibs/ice40/tests/test_ffs.sh
create mode 100644 techlibs/ice40/tests/test_ffs.v
create mode 100644 techlibs/xilinx/.gitignore
create mode 100644 techlibs/xilinx/brams_bb.v
create mode 100644 techlibs/xilinx/brams_init.py
create mode 100644 techlibs/xilinx/drams.txt
create mode 100644 techlibs/xilinx/drams_bb.v
create mode 100644 techlibs/xilinx/drams_map.v
create mode 100644 techlibs/xilinx/tests/bram2.sh
create mode 100644 techlibs/xilinx/tests/bram2.v
create mode 100644 techlibs/xilinx/tests/bram2_tb.v
delete mode 100644 tests/asicworld/code_hdl_models_dlatch_reset.v
delete mode 100644 tests/asicworld/code_hdl_models_ram_sp_ar_sw.v
delete mode 100644 tests/asicworld/code_hdl_models_ram_sp_sr_sw.v
copy tests/{bram => smv}/.gitignore (100%)
create mode 100644 tests/smv/run-single.sh
create mode 100755 tests/smv/run-test.sh
create mode 100644 tests/various/muxcover.ys
create mode 100644 tests/vloghtb/test_febe.sh
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