[yosys] branch master updated (d8d096a -> c6b473a)
Ruben Undheim
rubund-guest at moszumanska.debian.org
Wed Oct 7 20:09:37 UTC 2015
This is an automated email from the git hooks/post-receive script.
rubund-guest pushed a change to branch master
in repository yosys.
from d8d096a Python is now a build dependency
adds 914ae34 Improved $adff simplification
adds 2397078 Keep modules with $assume (like $assert)
adds badc5f7 Added "miter -assert"
adds 2a613b1 Some cleanups in opt_rmdff
adds 4d0ba9b Fixed "check" command for inout ports
adds 516e882 Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)
adds 4513ff1 Fixed nested mem2reg
adds eac0bcd Improvements in BLIF back-end
adds 3860c9a Fixed flatten $meminit handling
adds 8d6d5c3 Added WORDS parameter to $meminit
adds c836faa Add -noautowire option to verilog frontend
adds c63e5ed Merge pull request #68 from zeldin/master
adds 31b555a Added libyosys.so build
adds c7fd3fb Added $assert support to SMV back-end
adds 4e4b156 Added ENABLE_LIBYOSYS Makefile option
adds 5dc2397 Bugfix in SMV back-end for partially unassigned wires
adds 6834461 Remove some very strange whitespace in btor.cc (by Larry Doolittle)
adds c9e56bc Added iCE40 WARMBOOT cell
adds 3565e89 Merge pull request #69 from zeldin/master
adds 883e09d Use MEMID as name for $mem cell
adds 2185125 Added missing ct_all setup to opt_clean
adds 45ee2ba Fixed handling of [a-fxz?] in decimal constants
adds 8c4c62f Bugfix for cell hash cache option in opt_share.
adds 021b4a2 Bugfix for cell hash cache option in opt_share.
adds cbda56d Remove unused blackbox modules in opt_clean.
adds 667b015 Merge pull request #70 from gaomy3832/bugfix
adds 08ad540 Some ASCII encoding fixes (comments and docs) by Larry Doolittle
adds ad8efeb Fixed CRLF line endings
adds c699d7c More ASCII encoding fixes
adds f81bf9b Added SMV back-end 'test_cells.sh' script
adds bc468cb Fixed hashlib for 64 bit int keys
adds c43f38c Improved handling of "keep" attributes in hierarchical designs in opt_clean
adds e4ef000 Adjust makefiles to work with out-of-tree builds
adds fc20b1c Fixed "make clean" for out-of-tree builds
adds 698357d Added "write_smt2 -regs"
adds 80910d1 Merge branch 'master' of github.com:cliffordwolf/yosys
adds 84bf862 Spell check (by Larry Doolittle)
adds 0350074 Re-created command-reference-manual.tex, copied some doc fixes to online help
adds 022f570 Keep gcc from complaining about uninitialized variables
adds 6c00704 Another block of spelling fixes
adds 1e67b29 Fix version strings for out-of-tree builds
adds b659ffb Fixed generation of smt2 concat statements
adds ae09c89 Fixed opt_clean handling of inout ports
adds ff50bc2 Added $tribuf and $_TBUF_ cell types
adds 9c33172 Added tribuf command
adds d5b1a90 Added $tribuf and $_TBUF_ sim models
adds aedcfd6 Fixed Makefile rules for generated share files
adds 9596fe7 Another bugfix for ice40 and xilinx brams_init make rules
adds 8eebb67 Added .travis.yml.
adds b7cb5e2 Merge pull request #72 from cseed/master
adds 64ccbf8 Warn on literals exceeding the specified bit width
adds 0491042 Check base-n literals only contain valid digits
adds a7ab917 Small corrections to const2ast warning messages
adds f438150 Properly clean up unused "init" attributes
adds 246e362 Bugfix in fsm_detect for complex muxtrees
adds f40d1b7 Added sat -show-regs, -show-public, -show-all
adds c475dee Switched to Python 3
adds eb38722 Fixed handling of memory read without address
adds 09b51cb Added "yosys-smt2-wire" tag support to smt2 back-end
adds 92dce21 Using dict<> and pool<> in alumacc pass
adds ee8f6f3 Added SigMap::allbits()
adds 24e7cf8 Fixed iopadmap help message
adds 744a533 Microsoft Visual C++ fix for log.h.
adds 09176bc Microsoft Visual C++ fixes in hashlib; template specializations on int32_t and int64_t.
adds 522176c Removed unnecessary cast.
adds b10ea05 gcc-4.6 build fixes
adds 6f9a6fd Fixed port ordering in "splitnets" cmd
adds 99ccb31 Fixed ice40 handling of negclk RAM40
adds e7c018e Fixed sharing of $memrd cells
adds c5352f4 Added GreenPAK4 skeleton
adds d9cecab Fixed copy&paste typo in synth_greenpak4
adds e446e65 Initial implementation of $finish()
adds 7141f65 Initial implementation of $display()
adds 9db05d1 Added AST_INITIAL checks for $finish and $display
adds 7a230d3 Merge branch 'feat-finish-disp'
adds c89ceee Added $finish and $display to README
adds b7535a6 Added $logic_not handling to fsm_detect
adds 51e1295 Added detection of "mux inverter" chains in opt_const
adds 452d4bf Added support for "dfflibmap -liberty +/..."
adds 745d561 Renamed GreenPAK4 cells, improved GP4 DFF mapping
adds db54880 Added buffer detection to "abc -lut"
adds d212d4d Cosmetic fix in Module::addLut()
adds c851f51 Added lut2mux pass
adds 598a475 Added nlutmap
adds c469f22 Improvements to $display system task
adds 539c5ee Added "qwp" command
adds 6329bea Added "qwp -dump"
adds 80898dc Improvements and fixes in "qwp" pass
adds 11c27b5 Bugfix in "qwp" pass
adds b66bf8b Do not detect fsm state registers with init attribute
adds 405cf67 Fixed emcc build
adds 4b8200e Fixed segfault on invalid verilog constant 1'b_
adds 6176f4d Fixed multi-level prefix resolving
adds a3a13cc Fixed detection of "task foo(bar);" syntax error
adds b845b77 Fixed support for $write system task
adds 559929e Warning for $display/$write outside initial block
adds 089c1e1 Bugfix in handling of multi-dimensional memories
adds e2e092b Added read_verilog -nodpi
adds 1b8cb99 Fixed AstNode::mkconst_bits() segfault on zero-sized constant
adds 3501f8e Fixed memory_bram for ROMs in BRAMs with write-enable inputs
adds b1e9cb3 Added statistics summary to "qwp"
adds 69071bb Improved qwp performance
adds ec92c89 Added pivoting to qwp solver
adds 924d9d6 Added read-enable to memory model
adds b2544cf Fixed segfault in AstNode::asReal
adds 4ac202e Bugfixes in writing of memories as Verilog
adds f9d7df0 Bugfixes in $readmem[hb]
adds 4864736 Bugfix in bram read-enable code
adds 82028c4 Added wreduce $mul support and fixed signed $mul opt_const bug
adds ddcfc99 Added "test_cell -noeval"
adds 281c1f4 Some cleanups in qwp
adds c58bd5d Added edgetypes command
adds 9caeadf Fixed detection of unconditional $readmem[hb]
adds e51dcc8 Fixed complexity of assigning to vectors in constant functions
adds ba4cce9 Added support for "parameter" and "localparam" in global context
new f24a3d2 Merge tag 'upstream/0.5.0+20151007gitba4cce9'
new 4c30c5f New version name
new c6b473a Refreshed patches
The 3 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
.gitignore | 1 +
.travis.yml | 34 +
CHANGELOG | 12 +-
CodingReadme | 8 +-
Makefile | 52 +-
README | 26 +-
backends/blif/blif.cc | 89 ++-
backends/btor/btor.cc | 18 +-
backends/btor/verilog2btor.sh | 2 +-
backends/json/json.cc | 2 +-
backends/smt2/smt2.cc | 60 +-
backends/smv/smv.cc | 45 +-
backends/smv/test_cells.sh | 33 +
backends/verilog/verilog_backend.cc | 27 +-
debian/changelog | 2 +-
debian/patches/01_gitrevision.patch | 12 +-
debian/patches/02_removeabc.patch | 6 +-
debian/patches/03_notruntests.patch | 8 +-
debian/patches/04_installpath.patch | 24 +-
debian/patches/05_abc_executable.patch | 6 +-
debian/patches/06_cflags_ldflags.patch | 34 +-
frontends/ast/ast.cc | 12 +-
frontends/ast/ast.h | 6 +-
frontends/ast/genrtlil.cc | 25 +-
frontends/ast/simplify.cc | 230 +++++-
frontends/blif/blifparse.cc | 2 +-
frontends/ilang/Makefile.inc | 6 +-
frontends/ilang/ilang_lexer.l | 2 +-
frontends/ilang/ilang_parser.y | 2 +-
frontends/verific/verific.cc | 5 +-
frontends/verilog/Makefile.inc | 6 +-
frontends/verilog/const2ast.cc | 89 ++-
frontends/verilog/verilog_frontend.cc | 42 +-
frontends/verilog/verilog_lexer.l | 8 +-
frontends/verilog/verilog_parser.y | 6 +-
kernel/bitpattern.h | 4 +-
kernel/celltypes.h | 9 +-
kernel/driver.cc | 2 +-
kernel/hashlib.h | 18 +-
kernel/log.h | 7 +-
kernel/rtlil.cc | 36 +-
kernel/rtlil.h | 5 +-
kernel/sigtools.h | 8 +
kernel/yosys.cc | 2 +-
libs/ezsat/ezsat.h | 2 +-
manual/APPNOTE_010_Verilog_to_BLIF.tex | 6 +-
manual/APPNOTE_011_Design_Investigation.tex | 8 +-
manual/APPNOTE_012_Verilog_to_BTOR.tex | 2 +-
manual/CHAPTER_Appnotes.tex | 2 +-
manual/CHAPTER_Approach.tex | 4 +-
manual/CHAPTER_Auxlibs.tex | 4 +-
manual/CHAPTER_Auxprogs.tex | 2 +-
manual/CHAPTER_Basics.tex | 18 +-
manual/CHAPTER_CellLib.tex | 12 +-
manual/CHAPTER_Eval.tex | 4 +-
manual/CHAPTER_Optimize.tex | 4 +-
manual/CHAPTER_Overview.tex | 4 +-
manual/CHAPTER_Prog/stubnets.cc | 2 +-
manual/CHAPTER_StateOfTheArt.tex | 2 +-
manual/CHAPTER_StateOfTheArt/simlib_yosys.v | 2 +-
manual/CHAPTER_Techmap.tex | 2 +-
manual/CHAPTER_Verilog.tex | 24 +-
manual/PRESENTATION_ExAdv.tex | 10 +-
manual/PRESENTATION_ExOth.tex | 8 +-
manual/PRESENTATION_ExOth/equiv.ys | 4 +-
manual/PRESENTATION_ExSyn.tex | 4 +-
manual/PRESENTATION_Intro.tex | 42 +-
manual/PRESENTATION_Prog.tex | 4 +-
manual/command-reference-manual.tex | 806 +++++++++++++++++---
manual/literature.bib | 326 ++++----
manual/manual.tex | 2 +-
manual/presentation.tex | 4 +-
manual/weblinks.bib | 268 +++----
misc/example.cc | 5 +-
passes/cmds/Makefile.inc | 2 +
passes/cmds/check.cc | 16 +-
passes/cmds/connect.cc | 4 +-
passes/cmds/connwrappers.cc | 4 +-
passes/cmds/design.cc | 2 +-
passes/cmds/edgetypes.cc | 106 +++
passes/cmds/qwp.cc | 840 +++++++++++++++++++++
passes/cmds/scc.cc | 2 +-
passes/cmds/select.cc | 12 +-
passes/cmds/show.cc | 14 +-
passes/cmds/splice.cc | 2 +-
passes/cmds/splitnets.cc | 25 +-
passes/cmds/write_file.cc | 2 +-
passes/equiv/equiv_make.cc | 2 +-
passes/fsm/fsm.cc | 4 +-
passes/fsm/fsm_detect.cc | 42 +-
passes/fsm/fsm_expand.cc | 2 +-
passes/hierarchy/hierarchy.cc | 4 +-
passes/memory/memory_bram.cc | 39 +-
passes/memory/memory_collect.cc | 126 ++--
passes/memory/memory_dff.cc | 52 +-
passes/memory/memory_map.cc | 33 +-
passes/memory/memory_unpack.cc | 33 +-
passes/opt/opt_clean.cc | 75 +-
passes/opt/opt_const.cc | 42 +-
passes/opt/opt_reduce.cc | 2 +-
passes/opt/opt_rmdff.cc | 45 +-
passes/opt/opt_share.cc | 2 +
passes/opt/share.cc | 6 +-
passes/opt/wreduce.cc | 6 +-
passes/proc/proc_init.cc | 2 +-
passes/sat/eval.cc | 6 +-
passes/sat/expose.cc | 4 +-
passes/sat/freduce.cc | 10 +-
passes/sat/miter.cc | 96 ++-
passes/sat/sat.cc | 43 +-
passes/techmap/Makefile.inc | 5 +
passes/techmap/abc.cc | 12 +-
passes/techmap/alumacc.cc | 10 +-
passes/techmap/dff2dffe.cc | 2 +-
passes/techmap/dffinit.cc | 22 +-
passes/techmap/dfflibmap.cc | 1 +
passes/techmap/extract.cc | 8 +-
passes/techmap/iopadmap.cc | 6 +-
passes/techmap/lut2mux.cc | 93 +++
passes/techmap/nlutmap.cc | 173 +++++
passes/techmap/simplemap.cc | 18 +-
passes/techmap/techmap.cc | 20 +-
passes/techmap/tribuf.cc | 186 +++++
passes/tests/test_autotb.cc | 4 +-
passes/tests/test_cell.cc | 13 +-
techlibs/common/Makefile.inc | 7 -
techlibs/common/blackbox.sed | 5 -
techlibs/common/simcells.v | 8 +-
techlibs/common/simlib.v | 30 +-
techlibs/common/techmap.v | 4 +-
techlibs/greenpak4/Makefile.inc | 6 +
techlibs/greenpak4/cells_map.v | 48 ++
techlibs/greenpak4/cells_sim.v | 25 +
techlibs/greenpak4/gp_dff.lib | 26 +
.../synth_greenpak4.cc} | 83 +-
techlibs/ice40/Makefile.inc | 10 +-
techlibs/ice40/brams.txt | 4 +-
techlibs/ice40/brams_init.py | 11 +-
techlibs/ice40/brams_map.v | 18 +-
techlibs/ice40/cells_sim.v | 26 +-
techlibs/ice40/synth_ice40.cc | 2 +
techlibs/xilinx/Makefile.inc | 14 +-
techlibs/xilinx/brams.txt | 14 +-
techlibs/xilinx/brams_init.py | 13 +-
techlibs/xilinx/brams_map.v | 24 +-
techlibs/xilinx/synth_xilinx.cc | 4 +-
tests/asicworld/README | 2 +-
tests/asicworld/code_hdl_models_arbiter.v | 246 +++---
tests/asicworld/code_hdl_models_t_gate_switch.v | 22 +-
tests/asicworld/code_hdl_models_up_counter.v | 2 +-
tests/asicworld/code_verilog_tutorial_counter.v | 38 +-
tests/asicworld/code_verilog_tutorial_counter_tb.v | 226 +++---
tests/bram/generate.py | 5 +-
tests/bram/run-test.sh | 2 +-
tests/fsm/generate.py | 5 +-
tests/fsm/run-test.sh | 2 +-
tests/hana/README | 2 +-
tests/realmath/generate.py | 5 +-
tests/realmath/run-test.sh | 4 +-
tests/share/generate.py | 5 +-
tests/share/run-test.sh | 2 +-
tests/simple/dff_different_styles.v | 2 +-
tests/simple/hierarchy.v | 4 +-
tests/simple/rotate.v | 2 +-
tests/simple/vloghammer.v | 4 +-
tests/techmap/mem_simple_4x1_map.v | 9 +-
tests/tools/autotest.sh | 2 +-
tests/tools/txt2tikztiming.py | 5 +-
tests/tools/vcdcd.pl | 2 +-
169 files changed, 4448 insertions(+), 1432 deletions(-)
create mode 100644 .travis.yml
create mode 100644 backends/smv/test_cells.sh
create mode 100644 passes/cmds/edgetypes.cc
create mode 100644 passes/cmds/qwp.cc
create mode 100644 passes/techmap/lut2mux.cc
create mode 100644 passes/techmap/nlutmap.cc
create mode 100644 passes/techmap/tribuf.cc
delete mode 100644 techlibs/common/blackbox.sed
create mode 100644 techlibs/greenpak4/Makefile.inc
create mode 100644 techlibs/greenpak4/cells_map.v
create mode 100644 techlibs/greenpak4/cells_sim.v
create mode 100644 techlibs/greenpak4/gp_dff.lib
copy techlibs/{ice40/synth_ice40.cc => greenpak4/synth_greenpak4.cc} (72%)
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