[yosys] 01/03: Merge tag 'upstream/0.5.0+20151007gitba4cce9'
Ruben Undheim
rubund-guest at moszumanska.debian.org
Wed Oct 7 20:09:37 UTC 2015
This is an automated email from the git hooks/post-receive script.
rubund-guest pushed a commit to branch master
in repository yosys.
commit f24a3d275e468964f313978990777f7fa21c75de
Merge: d8d096a ba4cce9
Author: Ruben Undheim <ruben.undheim at gmail.com>
Date: Wed Oct 7 23:52:29 2015 +0400
Merge tag 'upstream/0.5.0+20151007gitba4cce9'
.gitignore | 1 +
.travis.yml | 34 +
CHANGELOG | 12 +-
CodingReadme | 8 +-
Makefile | 52 +-
README | 26 +-
backends/blif/blif.cc | 89 ++-
backends/btor/btor.cc | 18 +-
backends/btor/verilog2btor.sh | 2 +-
backends/json/json.cc | 2 +-
backends/smt2/smt2.cc | 60 +-
backends/smv/smv.cc | 45 +-
backends/smv/test_cells.sh | 33 +
backends/verilog/verilog_backend.cc | 27 +-
frontends/ast/ast.cc | 12 +-
frontends/ast/ast.h | 6 +-
frontends/ast/genrtlil.cc | 25 +-
frontends/ast/simplify.cc | 230 +++++-
frontends/blif/blifparse.cc | 2 +-
frontends/ilang/Makefile.inc | 6 +-
frontends/ilang/ilang_lexer.l | 2 +-
frontends/ilang/ilang_parser.y | 2 +-
frontends/verific/verific.cc | 5 +-
frontends/verilog/Makefile.inc | 6 +-
frontends/verilog/const2ast.cc | 89 ++-
frontends/verilog/verilog_frontend.cc | 42 +-
frontends/verilog/verilog_lexer.l | 8 +-
frontends/verilog/verilog_parser.y | 6 +-
kernel/bitpattern.h | 4 +-
kernel/celltypes.h | 9 +-
kernel/driver.cc | 2 +-
kernel/hashlib.h | 18 +-
kernel/log.h | 7 +-
kernel/rtlil.cc | 36 +-
kernel/rtlil.h | 5 +-
kernel/sigtools.h | 8 +
kernel/yosys.cc | 2 +-
libs/ezsat/ezsat.h | 2 +-
manual/APPNOTE_010_Verilog_to_BLIF.tex | 6 +-
manual/APPNOTE_011_Design_Investigation.tex | 8 +-
manual/APPNOTE_012_Verilog_to_BTOR.tex | 2 +-
manual/CHAPTER_Appnotes.tex | 2 +-
manual/CHAPTER_Approach.tex | 4 +-
manual/CHAPTER_Auxlibs.tex | 4 +-
manual/CHAPTER_Auxprogs.tex | 2 +-
manual/CHAPTER_Basics.tex | 18 +-
manual/CHAPTER_CellLib.tex | 12 +-
manual/CHAPTER_Eval.tex | 4 +-
manual/CHAPTER_Optimize.tex | 4 +-
manual/CHAPTER_Overview.tex | 4 +-
manual/CHAPTER_Prog/stubnets.cc | 2 +-
manual/CHAPTER_StateOfTheArt.tex | 2 +-
manual/CHAPTER_StateOfTheArt/simlib_yosys.v | 2 +-
manual/CHAPTER_Techmap.tex | 2 +-
manual/CHAPTER_Verilog.tex | 24 +-
manual/PRESENTATION_ExAdv.tex | 10 +-
manual/PRESENTATION_ExOth.tex | 8 +-
manual/PRESENTATION_ExOth/equiv.ys | 4 +-
manual/PRESENTATION_ExSyn.tex | 4 +-
manual/PRESENTATION_Intro.tex | 42 +-
manual/PRESENTATION_Prog.tex | 4 +-
manual/command-reference-manual.tex | 806 +++++++++++++++++---
manual/literature.bib | 326 ++++----
manual/manual.tex | 2 +-
manual/presentation.tex | 4 +-
manual/weblinks.bib | 268 +++----
misc/example.cc | 5 +-
passes/cmds/Makefile.inc | 2 +
passes/cmds/check.cc | 16 +-
passes/cmds/connect.cc | 4 +-
passes/cmds/connwrappers.cc | 4 +-
passes/cmds/design.cc | 2 +-
passes/cmds/edgetypes.cc | 106 +++
passes/cmds/qwp.cc | 840 +++++++++++++++++++++
passes/cmds/scc.cc | 2 +-
passes/cmds/select.cc | 12 +-
passes/cmds/show.cc | 14 +-
passes/cmds/splice.cc | 2 +-
passes/cmds/splitnets.cc | 25 +-
passes/cmds/write_file.cc | 2 +-
passes/equiv/equiv_make.cc | 2 +-
passes/fsm/fsm.cc | 4 +-
passes/fsm/fsm_detect.cc | 42 +-
passes/fsm/fsm_expand.cc | 2 +-
passes/hierarchy/hierarchy.cc | 4 +-
passes/memory/memory_bram.cc | 39 +-
passes/memory/memory_collect.cc | 126 ++--
passes/memory/memory_dff.cc | 52 +-
passes/memory/memory_map.cc | 33 +-
passes/memory/memory_unpack.cc | 33 +-
passes/opt/opt_clean.cc | 75 +-
passes/opt/opt_const.cc | 42 +-
passes/opt/opt_reduce.cc | 2 +-
passes/opt/opt_rmdff.cc | 45 +-
passes/opt/opt_share.cc | 2 +
passes/opt/share.cc | 6 +-
passes/opt/wreduce.cc | 6 +-
passes/proc/proc_init.cc | 2 +-
passes/sat/eval.cc | 6 +-
passes/sat/expose.cc | 4 +-
passes/sat/freduce.cc | 10 +-
passes/sat/miter.cc | 96 ++-
passes/sat/sat.cc | 43 +-
passes/techmap/Makefile.inc | 5 +
passes/techmap/abc.cc | 12 +-
passes/techmap/alumacc.cc | 10 +-
passes/techmap/dff2dffe.cc | 2 +-
passes/techmap/dffinit.cc | 22 +-
passes/techmap/dfflibmap.cc | 1 +
passes/techmap/extract.cc | 8 +-
passes/techmap/iopadmap.cc | 6 +-
passes/techmap/lut2mux.cc | 93 +++
passes/techmap/nlutmap.cc | 173 +++++
passes/techmap/simplemap.cc | 18 +-
passes/techmap/techmap.cc | 20 +-
passes/techmap/tribuf.cc | 186 +++++
passes/tests/test_autotb.cc | 4 +-
passes/tests/test_cell.cc | 13 +-
techlibs/common/Makefile.inc | 7 -
techlibs/common/blackbox.sed | 5 -
techlibs/common/simcells.v | 8 +-
techlibs/common/simlib.v | 30 +-
techlibs/common/techmap.v | 4 +-
techlibs/greenpak4/Makefile.inc | 6 +
techlibs/greenpak4/cells_map.v | 48 ++
techlibs/greenpak4/cells_sim.v | 25 +
techlibs/greenpak4/gp_dff.lib | 26 +
.../synth_greenpak4.cc} | 83 +-
techlibs/ice40/Makefile.inc | 10 +-
techlibs/ice40/brams.txt | 4 +-
techlibs/ice40/brams_init.py | 11 +-
techlibs/ice40/brams_map.v | 18 +-
techlibs/ice40/cells_sim.v | 26 +-
techlibs/ice40/synth_ice40.cc | 2 +
techlibs/xilinx/Makefile.inc | 14 +-
techlibs/xilinx/brams.txt | 14 +-
techlibs/xilinx/brams_init.py | 13 +-
techlibs/xilinx/brams_map.v | 24 +-
techlibs/xilinx/synth_xilinx.cc | 4 +-
tests/asicworld/README | 2 +-
tests/asicworld/code_hdl_models_arbiter.v | 246 +++---
tests/asicworld/code_hdl_models_t_gate_switch.v | 22 +-
tests/asicworld/code_hdl_models_up_counter.v | 2 +-
tests/asicworld/code_verilog_tutorial_counter.v | 38 +-
tests/asicworld/code_verilog_tutorial_counter_tb.v | 226 +++---
tests/bram/generate.py | 5 +-
tests/bram/run-test.sh | 2 +-
tests/fsm/generate.py | 5 +-
tests/fsm/run-test.sh | 2 +-
tests/hana/README | 2 +-
tests/realmath/generate.py | 5 +-
tests/realmath/run-test.sh | 4 +-
tests/share/generate.py | 5 +-
tests/share/run-test.sh | 2 +-
tests/simple/dff_different_styles.v | 2 +-
tests/simple/hierarchy.v | 4 +-
tests/simple/rotate.v | 2 +-
tests/simple/vloghammer.v | 4 +-
tests/techmap/mem_simple_4x1_map.v | 9 +-
tests/tools/autotest.sh | 2 +-
tests/tools/txt2tikztiming.py | 5 +-
tests/tools/vcdcd.pl | 2 +-
162 files changed, 4408 insertions(+), 1380 deletions(-)
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