[tbb] 38/64: Imported Debian patch 4.1~20130613-1.1
Graham Inggs
ginggs at moszumanska.debian.org
Mon Jul 3 12:28:01 UTC 2017
This is an automated email from the git hooks/post-receive script.
ginggs pushed a commit to branch master
in repository tbb.
commit 7da2d4122e6c6d82f28ebffd2c0934c03f04e90e
Author: Mathieu Malaterre <malat at debian.org>
Date: Mon Aug 26 13:00:26 2013 +0200
Imported Debian patch 4.1~20130613-1.1
---
debian/changelog | 9 +
debian/patches/series | 2 -
.../tbb40_20120613oss-0001-Endianness.patch | 42 ----
.../tbb40_20120613oss-0002-ARM-support.patch | 240 ---------------------
...s-0003-Add-machine_fetchadd-48-intrinsics.patch | 157 --------------
debian/patches/toto | 11 -
6 files changed, 9 insertions(+), 452 deletions(-)
diff --git a/debian/changelog b/debian/changelog
index f644654..4150395 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,12 @@
+tbb (4.1~20130613-1.1) unstable; urgency=low
+
+ * Non-maintainer upload.
+ * Remove patches from bug #692033, since integrated upstream now
+ * Upload to sid
+ - Closes: #714986, #715162, #713347, #715425, #705495
+
+ -- Mathieu Malaterre <malat at debian.org> Mon, 26 Aug 2013 13:00:26 +0200
+
tbb (4.1~20130613-1.1~exp1) experimental; urgency=low
* Non-maintainer upload.
diff --git a/debian/patches/series b/debian/patches/series
deleted file mode 100644
index 03ca13b..0000000
--- a/debian/patches/series
+++ /dev/null
@@ -1,2 +0,0 @@
-tbb40_20120613oss-0002-ARM-support.patch
-tbb40_20120613oss-0003-Add-machine_fetchadd-48-intrinsics.patch
diff --git a/debian/patches/tbb40_20120613oss-0001-Endianness.patch b/debian/patches/tbb40_20120613oss-0001-Endianness.patch
deleted file mode 100644
index 71fc039..0000000
--- a/debian/patches/tbb40_20120613oss-0001-Endianness.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From 2abd332fee526be68a0c30d1175599056a79f917 Mon Sep 17 00:00:00 2001
-From: Steve Capper <steve.capper at linaro.org>
-Date: Tue, 28 Aug 2012 04:11:16 -0400
-Subject: [PATCH 1/3] Endianness
-
-Fix the __TBB_BIG_ENDIAN preprocessor logic to correctly identify
-the unknown (at compile time) endianess check.
-
-Signed-off-by: Steve Capper <steve.capper at linaro.org>
----
- include/tbb/tbb_machine.h | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
-diff --git a/include/tbb/tbb_machine.h b/include/tbb/tbb_machine.h
-index 6c83942..803fcda 100644
---- a/include/tbb/tbb_machine.h
-+++ b/include/tbb/tbb_machine.h
-@@ -378,10 +378,12 @@ void spin_wait_until_eq( const volatile T& location, const U value ) {
- // - The operation assumes that the architecture consistently uses either little-endian or big-endian:
- // it does not support mixed-endian or page-specific bi-endian architectures.
- // This function is the only use of __TBB_BIG_ENDIAN.
--#if (__TBB_BIG_ENDIAN!=-1)
-+#if (__TBB_BIG_ENDIAN==-1)
- #if ( __TBB_USE_GENERIC_PART_WORD_CAS)
- #error generic implementation of part-word CAS was explicitly disabled for this configuration
- #endif
-+#endif
-+
- template<typename T>
- inline T __TBB_MaskedCompareAndSwap (volatile T * const ptr, const T value, const T comparand ) {
- struct endianness{ static bool is_big_endian(){
-@@ -419,7 +421,6 @@ inline T __TBB_MaskedCompareAndSwap (volatile T * const ptr, const T value, cons
- else continue; // CAS failed but the bits of interest left unchanged
- }
- }
--#endif
- template<size_t S, typename T>
- inline T __TBB_CompareAndSwapGeneric (volatile void *ptr, T value, T comparand );
-
---
-1.7.11.4
-
diff --git a/debian/patches/tbb40_20120613oss-0002-ARM-support.patch b/debian/patches/tbb40_20120613oss-0002-ARM-support.patch
deleted file mode 100644
index 58c4cc7..0000000
--- a/debian/patches/tbb40_20120613oss-0002-ARM-support.patch
+++ /dev/null
@@ -1,240 +0,0 @@
-From 5690a53639758f6a15c0d2a60acea4aa86ae9209 Mon Sep 17 00:00:00 2001
-From: Steve Capper <steve.capper at linaro.org>
-Date: Tue, 28 Aug 2012 07:11:51 -0400
-Subject: [PATCH 2/3] ARM support.
-
-Add ARMv7 support to libTBB.
-
-Signed-off-by: Steve Capper <steve.capper at linaro.org>
----
- build/linux.gcc.inc | 5 ++
- build/linux.inc | 6 ++
- include/tbb/machine/linux_armv7.h | 177 ++++++++++++++++++++++++++++++++++++++
- include/tbb/tbb_machine.h | 2 +
- src/tbbmalloc/frontend.cpp | 8 +-
- src/test/harness.h | 2 +-
- 6 files changed, 198 insertions(+), 2 deletions(-)
- create mode 100644 include/tbb/machine/linux_armv7.h
-
-Index: tbb41_20130613oss/build/linux.gcc.inc
-===================================================================
---- tbb41_20130613oss.orig/build/linux.gcc.inc 2013-06-19 16:53:57.000000000 +0200
-+++ tbb41_20130613oss/build/linux.gcc.inc 2013-07-06 15:04:59.000000000 +0200
-@@ -120,6 +120,11 @@
- CPLUS_FLAGS += -Wa,-mimplicit-it=thumb
- endif
-
-+# automatically generate "IT" instructions when compiling for Thumb ISA
-+ifeq (armv7,$(arch))
-+ CPLUS_FLAGS += -Wa,-mimplicit-it=thumb
-+endif
-+
- #------------------------------------------------------------------------------
- # Setting assembler data.
- #------------------------------------------------------------------------------
-Index: tbb41_20130613oss/build/linux.inc
-===================================================================
---- tbb41_20130613oss.orig/build/linux.inc 2013-06-19 16:53:56.000000000 +0200
-+++ tbb41_20130613oss/build/linux.inc 2013-07-06 15:04:59.000000000 +0200
-@@ -59,6 +59,9 @@
- ifeq ($(uname_m),armv71)
- export arch :=armv7
- endif
-+ ifeq ($(uname_m),armv7l)
-+ export arch:=armv7
-+ endif
- ifndef arch
- export arch:=$(uname_m)
- endif
-@@ -109,6 +112,9 @@
- endif
- ifeq ($(arch),armv7)
- def_prefix = lin32
-+endif
-+ifeq ($(arch),armv7)
-+ def_prefix = lin32
- endif
- ifeq (,$(def_prefix))
- ifeq (64,$(findstring 64,$(arch)))
-Index: tbb41_20130613oss/include/tbb/machine/linux_armv7.h
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ tbb41_20130613oss/include/tbb/machine/linux_armv7.h 2013-07-06 15:04:59.000000000 +0200
-@@ -0,0 +1,177 @@
-+/*
-+ Copyright 2012 ARM Limited All Rights Reserved.
-+
-+ This file is part of Threading Building Blocks.
-+
-+ Threading Building Blocks is free software; you can redistribute it
-+ and/or modify it under the terms of the GNU General Public License
-+ version 2 as published by the Free Software Foundation.
-+
-+ Threading Building Blocks is distributed in the hope that it will be
-+ useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-+ of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ GNU General Public License for more details.
-+
-+ You should have received a copy of the GNU General Public License
-+ along with Threading Building Blocks; if not, write to the Free Software
-+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-+
-+ As a special exception, you may use this file as part of a free software
-+ library without restriction. Specifically, if other files instantiate
-+ templates or use macros or inline functions from this file, or you compile
-+ this file and link it with other files to produce an executable, this
-+ file does not by itself cause the resulting executable to be covered by
-+ the GNU General Public License. This exception does not however
-+ invalidate any other reasons why the executable file might be covered by
-+ the GNU General Public License.
-+*/
-+
-+/*
-+ This is the TBB implementation for the ARMv7-a architecture.
-+*/
-+
-+#ifndef __TBB_machine_H
-+#error Do not include this file directly; include tbb_machine.h instead
-+#endif
-+
-+#if !(__ARM_ARCH_7A__)
-+#error Threading Building Blocks ARM port requires an ARMv7-a architecture.
-+#endif
-+
-+#include <sys/param.h>
-+#include <unistd.h>
-+
-+#define __TBB_WORDSIZE 4
-+
-+#ifndef __BYTE_ORDER__
-+ // Hopefully endianness can be validly determined at runtime.
-+ // This may silently fail in some embedded systems with page-specific endianness.
-+#elif __BYTE_ORDER__==__ORDER_BIG_ENDIAN__
-+ #define __TBB_BIG_ENDIAN 1
-+#elif __BYTE_ORDER__==__ORDER_LITTLE_ENDIAN__
-+ #define __TBB_BIG_ENDIAN 0
-+#else
-+ #define __TBB_BIG_ENDIAN -1 // not currently supported
-+#endif
-+
-+
-+#define __TBB_compiler_fence() __asm__ __volatile__("": : :"memory")
-+#define __TBB_control_consistency_helper() __TBB_compiler_fence()
-+
-+#define __TBB_armv7_inner_shareable_barrier() __asm__ __volatile__("dmb ish": : :"memory")
-+#define __TBB_acquire_consistency_helper() __TBB_armv7_inner_shareable_barrier()
-+#define __TBB_release_consistency_helper() __TBB_armv7_inner_shareable_barrier()
-+#define __TBB_full_memory_fence() __TBB_armv7_inner_shareable_barrier()
-+
-+
-+//--------------------------------------------------
-+// Compare and swap
-+//--------------------------------------------------
-+
-+/**
-+ * Atomic CAS for 32 bit values, if *ptr==comparand, then *ptr=value, returns *ptr
-+ * @param ptr pointer to value in memory to be swapped with value if *ptr==comparand
-+ * @param value value to assign *ptr to if *ptr==comparand
-+ * @param comparand value to compare with *ptr
-+ * @return value originally in memory at ptr, regardless of success
-+*/
-+static inline int32_t __TBB_machine_cmpswp4(volatile void *ptr, int32_t value, int32_t comparand )
-+{
-+ int32_t oldval, res;
-+
-+ __TBB_full_memory_fence();
-+
-+ do {
-+ __asm__ __volatile__(
-+ "ldrex %1, [%3]\n"
-+ "mov %0, #0\n"
-+ "cmp %1, %4\n"
-+ "strexeq %0, %5, [%3]\n"
-+ : "=&r" (res), "=&r" (oldval), "+Qo" (*(volatile int32_t*)ptr)
-+ : "r" ((int32_t *)ptr), "Ir" (comparand), "r" (value)
-+ : "cc");
-+ } while (res);
-+
-+ __TBB_full_memory_fence();
-+
-+ return oldval;
-+}
-+
-+/**
-+ * Atomic CAS for 64 bit values, if *ptr==comparand, then *ptr=value, returns *ptr
-+ * @param ptr pointer to value in memory to be swapped with value if *ptr==comparand
-+ * @param value value to assign *ptr to if *ptr==comparand
-+ * @param comparand value to compare with *ptr
-+ * @return value originally in memory at ptr, regardless of success
-+ */
-+static inline int64_t __TBB_machine_cmpswp8(volatile void *ptr, int64_t value, int64_t comparand )
-+{
-+ int64_t oldval;
-+ int32_t res;
-+
-+ __TBB_full_memory_fence();
-+
-+ do {
-+ __asm__ __volatile__(
-+ "mov %0, #0\n"
-+ "ldrexd %1, %H1, [%3]\n"
-+ "cmp %1, %4\n"
-+ "cmpeq %H1, %H4\n"
-+ "strexdeq %0, %5, %H5, [%3]"
-+ : "=&r" (res), "=&r" (oldval), "+Qo" (*(volatile int64_t*)ptr)
-+ : "r" ((int64_t *)ptr), "r" (comparand), "r" (value)
-+ : "cc");
-+ } while (res);
-+
-+ __TBB_full_memory_fence();
-+
-+ return oldval;
-+}
-+
-+inline void __TBB_machine_pause (int32_t delay )
-+{
-+ while(delay>0)
-+ {
-+ __TBB_compiler_fence();
-+ delay--;
-+ }
-+}
-+
-+namespace tbb {
-+namespace internal {
-+ template <typename T, size_t S>
-+ struct machine_load_store_relaxed {
-+ static inline T load ( const volatile T& location ) {
-+ const T value = location;
-+
-+ /*
-+ * An extra memory barrier is required for errata #761319
-+ * Please see http://infocenter.arm.com/help/topic/com.arm.doc.uan0004a
-+ */
-+ __TBB_armv7_inner_shareable_barrier();
-+ return value;
-+ }
-+
-+ static inline void store ( volatile T& location, T value ) {
-+ location = value;
-+ }
-+ };
-+}} // namespaces internal, tbb
-+
-+// Machine specific atomic operations
-+
-+#define __TBB_CompareAndSwap4(P,V,C) __TBB_machine_cmpswp4(P,V,C)
-+#define __TBB_CompareAndSwap8(P,V,C) __TBB_machine_cmpswp8(P,V,C)
-+#define __TBB_CompareAndSwapW(P,V,C) __TBB_machine_cmpswp4(P,V,C)
-+#define __TBB_Pause(V) __TBB_machine_pause(V)
-+
-+// Use generics for some things
-+#define __TBB_USE_GENERIC_PART_WORD_CAS 1
-+#define __TBB_USE_GENERIC_PART_WORD_FETCH_ADD 1
-+#define __TBB_USE_GENERIC_PART_WORD_FETCH_STORE 1
-+#define __TBB_USE_GENERIC_FETCH_ADD 1
-+#define __TBB_USE_GENERIC_FETCH_STORE 1
-+#define __TBB_USE_GENERIC_HALF_FENCED_LOAD_STORE 1
-+#define __TBB_USE_GENERIC_DWORD_LOAD_STORE 1
-+#define __TBB_USE_GENERIC_SEQUENTIAL_CONSISTENCY_LOAD_STORE 1
-+
diff --git a/debian/patches/tbb40_20120613oss-0003-Add-machine_fetchadd-48-intrinsics.patch b/debian/patches/tbb40_20120613oss-0003-Add-machine_fetchadd-48-intrinsics.patch
deleted file mode 100644
index 6e9ede0..0000000
--- a/debian/patches/tbb40_20120613oss-0003-Add-machine_fetchadd-48-intrinsics.patch
+++ /dev/null
@@ -1,157 +0,0 @@
-From 327bde31309e8ce049f427f538c30af567d3783e Mon Sep 17 00:00:00 2001
-From: Steve Capper <steve.capper at linaro.org>
-Date: Tue, 28 Aug 2012 07:20:08 -0400
-Subject: [PATCH 3/3] Add machine_fetchadd[48] intrinsics.
-
-Unfortunately ittnotify also requires its own copy of fetchadd4.
-
-Signed-off-by: Steve Capper <steve.capper at linaro.org>
----
- include/tbb/machine/linux_armv7.h | 49 ++++++++++++++++++++++++++++++++++--
- src/tbb/tools_api/ittnotify.h | 2 +-
- src/tbb/tools_api/ittnotify_config.h | 32 ++++++++++++++++++++++-
- 3 files changed, 79 insertions(+), 4 deletions(-)
-
-Index: tbb41_20130613oss/include/tbb/machine/linux_armv7.h
-===================================================================
---- tbb41_20130613oss.orig/include/tbb/machine/linux_armv7.h 2013-07-06 15:04:59.000000000 +0200
-+++ tbb41_20130613oss/include/tbb/machine/linux_armv7.h 2013-07-06 15:05:05.000000000 +0200
-@@ -128,6 +128,53 @@
- return oldval;
- }
-
-+static inline int32_t __TBB_machine_fetchadd4(volatile void* ptr, int32_t addend)
-+{
-+ unsigned long tmp;
-+ int32_t result, tmp2;
-+
-+ __TBB_full_memory_fence();
-+
-+ __asm__ __volatile__(
-+"1: ldrex %0, [%4]\n"
-+" add %3, %0, %5\n"
-+" strex %1, %3, [%4]\n"
-+" cmp %1, #0\n"
-+" bne 1b\n"
-+ : "=&r" (result), "=&r" (tmp), "+Qo" (*(volatile int32_t*)ptr), "=&r"(tmp2)
-+ : "r" ((int32_t *)ptr), "Ir" (addend)
-+ : "cc");
-+
-+ __TBB_full_memory_fence();
-+
-+ return result;
-+}
-+
-+static inline int64_t __TBB_machine_fetchadd8(volatile void *ptr, int64_t addend)
-+{
-+ unsigned long tmp;
-+ int64_t result, tmp2;
-+
-+ __TBB_full_memory_fence();
-+
-+ __asm__ __volatile__(
-+"1: ldrexd %0, %H0, [%4]\n"
-+" adds %3, %0, %5\n"
-+" adc %H3, %H0, %H5\n"
-+" strexd %1, %3, %H3, [%4]\n"
-+" cmp %1, #0\n"
-+" bne 1b"
-+ : "=&r" (result), "=&r" (tmp), "+Qo" (*(volatile int64_t*)ptr), "=&r"(tmp2)
-+ : "r" ((int64_t *)ptr), "r" (addend)
-+ : "cc");
-+
-+
-+ __TBB_full_memory_fence();
-+
-+ return result;
-+}
-+
-+
- inline void __TBB_machine_pause (int32_t delay )
- {
- while(delay>0)
-@@ -169,9 +216,7 @@
- #define __TBB_USE_GENERIC_PART_WORD_CAS 1
- #define __TBB_USE_GENERIC_PART_WORD_FETCH_ADD 1
- #define __TBB_USE_GENERIC_PART_WORD_FETCH_STORE 1
--#define __TBB_USE_GENERIC_FETCH_ADD 1
- #define __TBB_USE_GENERIC_FETCH_STORE 1
- #define __TBB_USE_GENERIC_HALF_FENCED_LOAD_STORE 1
- #define __TBB_USE_GENERIC_DWORD_LOAD_STORE 1
- #define __TBB_USE_GENERIC_SEQUENTIAL_CONSISTENCY_LOAD_STORE 1
--
-Index: tbb41_20130613oss/src/tbb/tools_api/ittnotify.h
-===================================================================
---- tbb41_20130613oss.orig/src/tbb/tools_api/ittnotify.h 2013-06-19 16:53:52.000000000 +0200
-+++ tbb41_20130613oss/src/tbb/tools_api/ittnotify.h 2013-07-06 15:05:05.000000000 +0200
-@@ -153,7 +153,7 @@
- # if ITT_PLATFORM==ITT_PLATFORM_WIN
- # define CDECL __cdecl
- # else /* ITT_PLATFORM==ITT_PLATFORM_WIN */
--# if defined _M_X64 || defined _M_AMD64 || defined __x86_64__
-+# if defined _M_X64 || defined _M_AMD64 || defined __x86_64__ || defined __arm__
- # define CDECL /* not actual on x86_64 platform */
- # else /* _M_X64 || _M_AMD64 || __x86_64__ */
- # define CDECL __attribute__ ((cdecl))
-Index: tbb41_20130613oss/src/tbb/tools_api/ittnotify_config.h
-===================================================================
---- tbb41_20130613oss.orig/src/tbb/tools_api/ittnotify_config.h 2013-06-19 16:53:52.000000000 +0200
-+++ tbb41_20130613oss/src/tbb/tools_api/ittnotify_config.h 2013-07-06 15:05:05.000000000 +0200
-@@ -86,7 +86,7 @@
- # if ITT_PLATFORM==ITT_PLATFORM_WIN
- # define CDECL __cdecl
- # else /* ITT_PLATFORM==ITT_PLATFORM_WIN */
--# if defined _M_X64 || defined _M_AMD64 || defined __x86_64__
-+# if defined _M_X64 || defined _M_AMD64 || defined __x86_64__ || defined __arm__
- # define CDECL /* not actual on x86_64 platform */
- # else /* _M_X64 || _M_AMD64 || __x86_64__ */
- # define CDECL __attribute__ ((cdecl))
-@@ -144,11 +144,17 @@
- # define ITT_ARCH_IA64 3
- #endif /* ITT_ARCH_IA64 */
-
-+#ifndef ITT_ARCH_ARM
-+# define ITT_ARCH_ARM 4
-+#endif /* ITT_ARCH_ARM */
-+
- #ifndef ITT_ARCH
- # if defined _M_X64 || defined _M_AMD64 || defined __x86_64__
- # define ITT_ARCH ITT_ARCH_IA32E
- # elif defined _M_IA64 || defined __ia64
- # define ITT_ARCH ITT_ARCH_IA64
-+# elif defined __arm__
-+# define ITT_ARCH ITT_ARCH_ARM
- # else
- # define ITT_ARCH ITT_ARCH_IA32
- # endif
-@@ -258,6 +264,30 @@
- #else /* __INTEL_COMPILER */
- /* TODO: Add Support for not Intel compilers for IA-64 architecture*/
- #endif /* __INTEL_COMPILER */
-+#elif ITT_ARCH==ITT_ARCH_ARM
-+#define __TBB_armv7_inner_shareable_barrier() __asm__ __volatile__("dmb ish": : :"memory")
-+#define __TBB_full_memory_fence() __TBB_armv7_inner_shareable_barrier()
-+INLINE int32_t __TBB_machine_fetchadd4(volatile void* ptr, int32_t addend)
-+{
-+ unsigned long tmp;
-+ int32_t result, tmp2;
-+
-+ __TBB_full_memory_fence();
-+
-+ __asm__ __volatile__(
-+"1: ldrex %0, [%4]\n"
-+" add %3, %0, %5\n"
-+" strex %1, %3, [%4]\n"
-+" cmp %1, #0\n"
-+" bne 1b\n"
-+ : "=&r" (result), "=&r" (tmp), "+Qo" (*(volatile int32_t*)ptr), "=&r"(tmp2)
-+ : "r" ((int32_t *)ptr), "Ir" (addend)
-+ : "cc");
-+
-+ __TBB_full_memory_fence();
-+
-+ return result;
-+}
- #else /* ITT_ARCH!=ITT_ARCH_IA64 */
- INLINE int __TBB_machine_fetchadd4(volatile void* ptr, long addend)
- {
diff --git a/debian/patches/toto b/debian/patches/toto
deleted file mode 100644
index 48b1a78..0000000
--- a/debian/patches/toto
+++ /dev/null
@@ -1,11 +0,0 @@
-Index: tbb41_20130613oss/README
-===================================================================
---- tbb41_20130613oss.orig/README 2013-07-06 15:04:22.000000000 +0200
-+++ tbb41_20130613oss/README 2013-07-06 15:04:24.000000000 +0200
-@@ -1,5 +1,6 @@
- Intel(R) Threading Building Blocks - README
-
-+
- See index.html for directions and documentation.
-
- If source is present (./Makefile and src/ directories),
--
Alioth's /usr/local/bin/git-commit-notice on /srv/git.debian.org/git/debian-science/packages/tbb.git
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