[qflow] annotated tag upstream/1.1.44 created (now f0a0917)
Ruben Undheim
rubund-guest at moszumanska.debian.org
Fri Mar 17 12:55:23 UTC 2017
This is an automated email from the git hooks/post-receive script.
rubund-guest pushed a change to annotated tag upstream/1.1.44
in repository qflow.
at f0a0917 (tag)
tagging 548aa8a30317aade2d08d55499cf8860513bd081 (commit)
tagged by Ruben Undheim
on Fri Mar 17 12:49:24 2017 +0000
- Log -----------------------------------------------------------------
Upstream version 1.1.44
Ruben Undheim (13):
Merge remote-tracking branch 'upstream/master' into upstream
Merge remote-tracking branch 'upstream/master' into upstream
Merge remote-tracking branch 'upstream/master' into upstream
Merge remote-tracking branch 'upstream/master' into upstream
Merge remote-tracking branch 'upstream/master' into upstream
Merge remote-tracking branch 'upstream/master' into upstream
Merge remote-tracking branch 'upstream/master' into upstream
Fixed VERSION
Merge remote-tracking branch 'upstream/master' into upstream
Merge remote-tracking branch 'upstream/master' into upstream
Merge tag '1.1.31' into upstream
Squashed commit of the following:
New upstream version 1.1.44
Tim Edwards (443):
Initial commit at Tue Apr 9 17:00:19 EDT 2013 by tim on stravinsky.tim.linglan.net
Trivial update to check the remote updates on opencircuitdesign.
Trivial change, once more, 2nd check. . .
Third time's the charm.
Update at Tue Apr 9 17:08:54 EDT 2013 by tim
Merge branch 'master' into work
Various updates, corrections to make the example circuit complete the
Update at Tue Apr 9 19:58:56 EDT 2013 by tim
Merge branch 'master' into work
Added a few scripts for file conversion. These are not yet part
Update at Wed Apr 10 11:44:01 EDT 2013 by tim
Merge branch 'master' into work
Trivial changes. . .
Update at Thu Apr 11 10:39:20 EDT 2013 by tim
Merge branch 'master' into work
Implemented a technology-independent spacer (filler cell) adding
Update at Fri Apr 12 14:04:55 EDT 2013 by tim
Merge branch 'master' into work
Forgot to map the output of addspacers back to the original filename
Small modification to add output to the log file instead of dumping
Changed sis input from "rlib" to "read_library", as "rlib" became
Update at Sun Apr 14 19:20:53 EDT 2013 by tim
Merge branch 'master' into work
Corrected an error in the configure script that would prevent setting
Update at Tue Apr 30 17:52:27 EDT 2013 by tim
Merge branch 'master' into work
A number of changes. Most changes involve support of power and ground
Update at Wed May 8 19:48:28 EDT 2013 by tim
Merge branch 'master' into work
Corrected a minor error preventing BDnetFanout from running.
Update at Thu May 9 14:08:19 EDT 2013 by tim
Merge branch 'master' into work
Corrected the BDnetFanout source as well so that a missing "ignore"
Put the call to BDnet2BSpice back in the synthesis and resynthesis
Made modifications to BDnet2BSpice to take as an input argument the
Update at Fri May 10 13:33:32 EDT 2013 by tim
Merge branch 'master' into work
Corrected an error in the core bounding box position calculated
Corrected the unused input to a DFFSR when used as a set-only
Update at Sat May 11 09:22:40 EDT 2013 by tim
Merge branch 'master' into work
Expanded the verilog preprocessor to handle "parameter" statements,
Small modification to vpreproc (nonfunctional)
Update at Mon May 13 11:26:32 EDT 2013 by tim
Merge branch 'master' into work
Modified qflow to add the magic startup script to the layout directory,
Update at Thu May 16 10:34:43 EDT 2013 by tim
Merge branch 'master' into work
Accidental commit of object files and other temporary build files.
Update at Sun Jul 14 15:34:16 EDT 2013 by tim
Merge branch 'master' into work
Removed temporary build files from the distribution.
Corrected an error which was setting the current working directory
Update at Mon Jul 15 15:12:58 EDT 2013 by tim
Merge branch 'master' into work
Changed the flow so that "placement.sh" is always run with the "-d"
Update at Wed Jul 17 09:05:24 EDT 2013 by tim
Merge branch 'master' into work
Made changes to "vpreproc.c" to ignore "always" blocks that either
Quick correction to the last commit.
Added preliminary support for the Odin-II verilog parser.
Corrections to the preprocessor for VIS, to remove ending semicolon
Update at Thu Jul 18 11:16:04 EDT 2013 by tim
Merge branch 'master' into work
Some extensions to the preprocessor, restoring the ability of the
Correction to vpreproc.c, which was closing the input file before
Update at Sun Jul 21 13:42:37 EDT 2013 by tim
Merge branch 'master' into work
This is a major update to qflow, replacing the tools "VIS" and "SIS"
Update at Thu Jul 25 13:24:13 EDT 2013 by tim
Merge branch 'master' into work
Update to vpreproc, still trying to accomodate a whole bunch of
Update at Fri Jul 26 14:47:22 EDT 2013 by tim
Merge branch 'master' into work
Added the OSU 0.5um standard cell set, with a lot of help from
Update at Mon Jul 29 18:33:01 EDT 2013 by tim
Merge branch 'master' into work
Modifications to the OSU 0.5um technology files to correct errors
Update at Tue Jul 30 10:12:11 EDT 2013 by tim
Merge branch 'master' into work
One additional modification moves one of the VDD fingers in
Additional correction to the IRSIM parameter file for OSU050
Update to the configure script and makefiles to correctly support the
Modified the synthesis script to make use of newest Odin-II code,
Update at Fri Aug 2 20:05:40 EDT 2013 by tim
Merge branch 'master' into work
Update to vpreproc tool to (1) correctly handle parameters with
Update at Thu Aug 15 08:41:01 EDT 2013 by tim
Merge branch 'master' into work
Correction to a major error that cropped up with the last update to
Update at Fri Aug 16 09:53:46 EDT 2013 by tim
Merge branch 'master' into work
Corrected an error in vpreproc that would overwrite the reset
Corrected the so-called "resynthesis" script (clock tree generator),
Update at Sat Aug 17 11:15:19 EDT 2013 by tim
Merge branch 'master' into work
Rewrote the clocktree algorithm to limit the number of branches in
Update at Tue Aug 20 17:50:01 EDT 2013 by tim
Merge branch 'master' into work
Added handling of LOGIC0 and LOGIC1 generic gates for technologies
Corrected an error in the cleanup script that was still referring
Update at Wed Aug 21 11:43:57 EDT 2013 by tim
Merge branch 'master' into work
Corrected a minor typo in place2def2.tcl, which was calling itself
Implemented what are hopefully some halfway rational ways to deal
Additional work to capture errors. Within a specific qflow master
Update at Thu Aug 22 09:06:28 EDT 2013 by tim
Merge branch 'master' into work
Added options "build" and "all" to "qflow", so that qflow can be
Corrected an error preventing use of a locally defined tech directory.
Update at Sun Aug 25 09:48:02 EDT 2013 by tim
Merge branch 'master' into work
Corrected the synthesis script to avoid an undefined variable error
Corrected an error in clocktree where an empty cluster can cause a
Update at Fri Aug 30 20:16:49 EDT 2013 by tim
Merge branch 'master' into work
Created a new tool called "liberty2tech", that is useful for
Update at Sun Sep 1 19:55:46 EDT 2013 by tim
Merge branch 'master' into work
Added liberty2tech compile/install to Makefile.in
Update at Mon Sep 2 08:27:12 EDT 2013 by tim
Merge branch 'master' into work
Modified liberty2tech to use a simple pattern matching to determing
Made some changes to avoid having scripts hard-code the DFF clock
Corrected an error preventing the use of set and reset flops.
Corrected an error allowing long input/output lists to overrun
Modified the techfiles distributed with the OSU035 and OSU050
Added features to liberty2tech to deal with local overrides of
Update at Tue Sep 3 11:42:17 EDT 2013 by tim
Merge branch 'master' into work
Expanded liberty2tech to handle templates in either orientation, and
Updated the genlib and gate.cfg files for osu035 and osu050 from the
And additional expansion of the function strings handled by
Qflow corrections: postproc.tcl will not skip parsing a file if
Update at Fri Sep 6 20:22:01 EDT 2013 by tim
Merge branch 'master' into work
Replaced the vpreproc tool with the new verilogpp tool. This
Update at Sat Sep 7 14:06:39 EDT 2013 by tim
Merge branch 'master' into work
One additional correction to send stderr output from abc to the
Using the new "-k" switch on qrouter; some changes to the osu050 tech
Correction to BDnetFanout, to avoid overwriting the string-terminating
Slight change to the last modification, nothing important. . .
Removed error message reporting from "qrouter -i", because it appears
Corrected a fairly major error (only off by a factor of 1000!) in
Update at Sun Sep 8 08:49:15 EDT 2013 by tim
Merge branch 'master' into work
Added to qflow the ability to add padding area to the layout with
Corrected an unbalanced parenthesis introduced into the osu050.genlib
Changed the handling of fill cells completely. To get a better
Update at Mon Sep 9 09:29:26 EDT 2013 by tim
Merge branch 'master' into work
Correction to the ".par" parameter files used by TimberWolf for
One further small correction to a comment line with incorrect
And a few more small things. . . added 'random.seed' to the .par
Correction to the last update to place2def.
Found that TimberWolf can violate track pitch when placing pins,
Update at Wed Sep 11 12:19:30 EDT 2013 by tim
Merge branch 'master' into work
Modified clocktree to pick up the random seed number (if any)
Corrected liberty2tech (once again), where a correction to the slope
Allows the technology script to set variable "resolution", which is
Update at Thu Sep 12 13:54:20 EDT 2013 by tim
Merge branch 'master' into work
Corrected two fprintf lines in verilogpp error messages. Fixed
Modified the qflow "configure" script to allow the use of the much
Update at Fri Sep 13 10:42:08 EDT 2013 by tim
Merge branch 'master' into work
Added some option handling. The "project_vars.sh" file is now a
Update at Sat Sep 14 17:11:58 EDT 2013 by tim
Merge branch 'master' into work
Another change: technology is now picked up from the existing
Removed the hard-coded via stack specifier, and made it settable from
Update at Sun Sep 15 10:22:17 EDT 2013 by tim
Merge branch 'master' into work
Correction to qflow.sh.in to avoid printing messages about values
Corrected a typo. . .
Another slight change, to move some manipulations of the .cfg file
One last correction to syntax. . .
A vague attempt to parse and modify verilog statements of the
Update at Mon Sep 23 22:18:33 EDT 2013 by tim
Modified .gitignore for project
Merge branch 'master' into work
Added an important initialization to the state stack pointer
Update at Mon Sep 30 11:47:18 EDT 2013 by tim
Merge branch 'master' into work
Preprocessor correction when popping out of the last "end" statement
Update at Wed Oct 2 10:12:31 EDT 2013 by tim
Merge branch 'master' into work
Corrected the verilogpp source in the correct way, this time.
Correction to verilogpp.c covering a case where a negative edge
Update at Thu Oct 3 11:30:57 EDT 2013 by tim
Merge branch 'master' into work
Added code needed to handle resets that are declared to be internal
Update at Fri Oct 4 17:38:59 EDT 2013 by tim
Merge branch 'master' into work
Some modifications to avoid redundant handling of clocks and reset
Update at Tue Oct 8 11:28:23 EDT 2013 by tim
Merge branch 'master' into work
Overhaul of qflow to eliminate all uses of the "BDNET" format in favor
Update at Wed Oct 9 12:02:14 EDT 2013 by tim
Merge branch 'master' into work
Rewrote the verilog preprocessing and postprocessing routines to
Update at Thu Oct 10 10:28:15 EDT 2013 by tim
Merge branch 'master' into work
Some more modifications to the new routines, and a correction to
Update at Fri Oct 11 09:41:14 EDT 2013 by tim
Merge branch 'master' into work
Found that the substitutions previously done by blifrtl2bdnet
Further refinement of XML file generation for Odin-II to avoid repeating
A few corrections to (1) verilogpp.c for parsing "always @(*)" syntax,
Update at Sat Oct 19 10:49:15 EDT 2013 by tim
Merge branch 'master' into work
Major update to support yosys, following changes made to yosys by
Update at Thu Oct 24 19:47:28 EDT 2013 by tim
Merge branch 'master' into work
Added script "ybuffer" to add buffers between internal signals
Update at Fri Oct 25 13:35:25 EDT 2013 by tim
Merge branch 'master' into work
Update with a reasonably good, working version of the vesta
Update at Tue Oct 29 20:16:05 EDT 2013 by tim
Merge branch 'master' into work
Added setup time calculation at path termination on a flop input.
Update at Wed Oct 30 17:51:18 EDT 2013 by tim
Merge branch 'master' into work
Modifed the STA to use a "--fastmode" that does not attempt to
Update at Thu Oct 31 20:41:33 EDT 2013 by tim
Merge branch 'master' into work
A few more minor optimizations. Inverted "fast mode" so that
Update at Fri Nov 1 20:08:35 EDT 2013 by tim
Merge branch 'master' into work
Removed temporary copies of the vesta source.
Added the remainder of the standard analysis types to vesta,
Update at Mon Nov 4 13:34:58 EST 2013 by tim
Merge branch 'master' into work
Important update to the clock tree insertion tool, which now
Update at Tue Nov 26 19:27:07 EST 2013 by tim
Merge branch 'master' into work
A number of changes to the flow: Mainly, incorporated the
Update at Wed Nov 27 16:21:48 EST 2013 by tim
Merge branch 'master' into work
Modified router script to track qrouter's new output messages
HAAAAAAAAAAAANDS (xkcd 1296)
Reworked the decongestion script both to match the normalized
Update at Thu Nov 28 12:02:49 EST 2013 by tim
Merge branch 'master' into work
Twiddled with the decongestent parameters again. It is clear that
Update at Sun Dec 1 17:17:26 EST 2013 by tim
Merge branch 'master' into work
Changes to deal with problems arising from use of lower case
Update at Fri Dec 20 13:05:12 EST 2013 by tim
Merge branch 'master' into work
Corrected an error where yosys' use of a backslash before module
Update at Thu Jan 16 09:14:35 EST 2014 by tim
Merge branch 'master' into work
Modified blif2Verilog so that it changes characters ":" and "." to
Update at Fri Jan 17 17:05:31 EST 2014 by tim
Merge branch 'master' into work
Modified the yosys synthesis script to make use of the new
Update at Wed Jan 22 09:56:20 EST 2014 by tim
Merge branch 'master' into work
Added the "tiehipin_out" and "tielopin_out" variables to the
Update at Thu Jan 23 21:23:12 EST 2014 by tim
Merge branch 'master' into work
Made changes to the flow scripts so that (1) the flow properly
Update at Sat Jan 25 12:26:24 EST 2014 by tim
Merge branch 'master' into work
Made a change to the placement script to check if "qrouter -i"
Update at Thu Feb 6 12:06:04 EST 2014 by tim
Merge branch 'master' into work
Corrected an error pertaining to the order in which qrouter is
Update at Fri Feb 7 12:38:22 EST 2014 by tim
Merge branch 'master' into work
Corrected an error in vesta that would invert the tables, swapping
Update at Sat Feb 8 11:29:24 EST 2014 by tim
Merge branch 'master' into work
A very quick fix to ybuffer.tcl to correct an error that could
Update at Sat Feb 15 15:58:44 EST 2014 by tim
Merge branch 'master' into work
Updated synthesize_yosys to make use of the "-bits" option to
Corrected Vesta for lookup tables that are 1-dimensional.
Update at Sun Feb 16 17:15:48 EST 2014 by tim
Merge branch 'master' into work
Added routine "getfillcell.tcl" that searches a LEF file for fill
Update at Tue Apr 8 17:42:20 EDT 2014 by tim
Merge branch 'master' into work
Update at Mon May 26 09:55:12 EDT 2014 by tim
Update at Tue May 27 19:10:21 EDT 2014 by tim
Update at Thu May 29 10:52:52 EDT 2014 by tim
Update at Fri May 30 14:41:25 EDT 2014 by tim
Update at Sat May 31 14:50:58 EDT 2014 by tim
Correction to the clocktree script to handle cells such as tiehi/
Update at Wed Jul 9 12:00:47 EDT 2014 by tim
Merge branch 'master' into work
Additional diagnostic statements printed in the STA tool.
Update at Sat Jul 12 14:18:44 EDT 2014 by tim
Merge branch 'master' into work
Fixed an error that causes vesta to crash if it has bad input and
Corrected an error in blifFanout that causes a crash if the gate
Added support for structural verilog in-line, pending update of
Update at Thu Jul 17 08:34:09 EDT 2014 by tim
Merge branch 'master' into work
Updated synthesis checks on yosys version to capture the newest
Update at Thu Sep 18 09:34:36 EDT 2014 by tim
Merge branch 'master' into work
Corrected an error that prevents qflow from working with qrouter
Update at Mon Sep 29 21:05:35 EDT 2014 by tim
Merge branch 'master' into work
Removed references to TimberWolf in favor of Ruben Undheim's update
Update at Tue Oct 14 20:42:31 EDT 2014 by tim
Merge branch 'master' into work
Corrected an error that causes synthesize_yosys.sh to fail due to
Update at Wed Nov 19 15:52:34 EST 2014 by tim
Merge branch 'master' into work
Applied patch from green AT moxielogic.com from Bugzilla bug ID 44,
Update at Mon Feb 2 08:10:25 EST 2015 by tim
Merge branch 'master' into work
Added qflow option "-v" or "--version" to print qflow version
Update at Wed Feb 25 19:39:23 EST 2015 by tim
Merge branch 'master' into work
Corrected a bad error in the ypostproc.tcl script that was
Update at Thu Feb 26 20:13:15 EST 2015 by tim
Merge branch 'master' into work
Made a couple of corrections that allows the use of a null string
Update at Mon Mar 30 16:42:31 EDT 2015 by tim
Merge branch 'master' into work
Corrected place2def.tcl, which would greedily take the first
Thought better of it and added a $ to the regexp to make sure that
Modified the blif2Verilog script so that the ".nopwr.v" file
Update at Mon Apr 20 09:31:37 EDT 2015 by tim
Merge branch 'master' into work
Changed all tcl scripts to use /bin/tclsh; however, this needs
Update at Thu May 7 15:48:59 EDT 2015 by tim
Merge branch 'master' into work
Implemented a variation of "decongest.tcl" that will take a .cel
Corrected calculation for number of fill cells to add, to get the
Update at Fri May 8 20:08:42 EDT 2015 by tim
Merge branch 'master' into work
Additional correction to clocktree to correctly parse a cellname
Another correction to prevent the clock tree insertion tool from
Initial commit at Sun May 17 21:16:12 EDT 2015 by tim on stravinsky
Added a comment, mostly just to jog the system into updating all
Corrected code so that it does not segfault on a diagnostic
Update at Tue May 26 12:16:13 EDT 2015 by tim
Merge branch 'master' into work
Corrected an error in back-annotation of permuted buffer tree nets.
Update at Fri May 29 09:36:47 EDT 2015 by tim
Merge branch 'master' into work
Finally got around to updating the yosys script to use the default
Added a new option to "project_vars.sh" called "yosys_nodebug".
Corrected the liberty file reading of scalar values instead of
Update at Sun May 31 19:36:05 EDT 2015 by tim
Merge branch 'master' into work
Removed an unused backup file.
Modified readliberty.c to ignore cells marked "dont_use".
Update at Tue Jun 2 10:08:55 EDT 2015 by tim
Merge branch 'master' into work
Corrected missing tagging of flop and latch output with an appropriate
Corrected Makefile.in in the src directory, or else vesta won't
Modified scripts such that all TCL scripts are annotated with the
Update at Wed Jun 3 17:34:02 EDT 2015 by tim
Merge branch 'master' into work
Added files for support of OSU018 (for TSMC). Also: Corrected
Update at Tue Jun 9 11:30:38 EDT 2015 by tim
Merge branch 'master' into work
Added OFFSET lines back into the OSU standard cell LEF files.
Corrected src makefile to clean up hash.o and readliberty.o on a
Update at Fri Jul 24 10:41:34 EDT 2015 by tim
Merge branch 'master' into work
Oops, last change defined hash.o and readliberty.o in such a way
Update at Sat Jul 25 09:27:08 EDT 2015 by tim
Merge branch 'master' into work
Once again. . .
Noted that graywolf produces redundant net entries where it thinks
Update at Mon Aug 3 10:01:25 EDT 2015 by tim
Merge branch 'master' into work
Corrected density planning of "decongest" for situations where
Update at Sun Sep 6 12:41:16 EDT 2015 by tim
Merge branch 'master' into work
Corrected POLYGON handling of blif2cel.
Update at Mon Sep 14 08:50:39 EDT 2015 by tim
Merge branch 'master' into work
Added patch by Staf Verhaegen that passes a default script argument
Update at Sun Oct 4 11:43:37 EDT 2015 by tim
Merge branch 'master' into work
Modified synthesis script to provide immediate output on the
Corrected two errors with the decongestion routine. One error
Update at Sun Oct 11 11:27:31 EDT 2015 by tim
Merge branch 'master' into work
Updated readliberty.c to match a change previously made to the
Update at Fri Oct 16 11:02:32 EDT 2015 by tim
Merge branch 'master' into work
Modified the synthesis script so that the various files (lef,
Update at Wed Oct 28 09:43:21 EDT 2015 by tim
Merge branch 'master' into work
Extended the absolute path handling capability to all the major
Corrected one remaining error in the "decongest" density planning
Update at Thu Oct 29 08:33:10 EDT 2015 by tim
Merge branch 'master' into work
Modified scripts so that the .cel file is generated as part of
Update at Fri Oct 30 09:22:54 EDT 2015 by tim
Merge branch 'master' into work
Corrected synthesis script, which had added the line necessary to
Update at Wed Nov 11 11:31:46 EST 2015 by tim
Merge branch 'master' into work
Corrected a problem in the place2def.tcl script that was not
Update at Thu Nov 12 20:02:55 EST 2015 by tim
Merge branch 'master' into work
Changed qflow behavior so that option "yosys_nodebug" is now
Update at Fri Nov 13 13:11:19 EST 2015 by tim
Merge branch 'master' into work
Added graywolf_options to list of variables defined in
Update at Fri Nov 20 13:40:40 EST 2015 by tim
Merge branch 'master' into work
Revised the way that the placement and router scripts handle
Update at Sun Nov 22 09:41:25 EST 2015 by tim
Merge branch 'master' into work
Slight modification, as the unroute copy was being made before
Rootname, not project. . .
Corrected installation and execution for local installations of
Update at Sat Jan 9 10:44:42 EST 2016 by tim
Merge branch 'master' into work
Corrected handling of place2def so that it does not exit with an
Update at Fri Feb 12 22:08:27 EST 2016 by tim
Merge branch 'master' into work
Corrected a number of errors in blifFanout that failed to properly
Update at Mon Feb 15 21:53:50 EST 2016 by tim
Merge branch 'master' into work
Corrected an error in vesta that would segfault on attempting to
Update at Tue Feb 16 20:24:17 EST 2016 by tim
Merge branch 'master' into work
Corrected a round-off error in the generation of .cel files by
Update at Thu Feb 18 22:34:47 EST 2016 by tim
Merge branch 'master' into work
Added "touch $synthlog" to the top of all the scripts after
Update at Fri Feb 26 19:03:44 EST 2016 by tim
Merge branch 'master' into work
Fixed an incorrect parsing of one of the various possible version
Update at Tue Mar 15 16:36:03 EDT 2016 by tim
Merge branch 'master' into work
Added back parsing of option "buffer" for backwards-comptibility
Update at Wed Mar 16 09:21:40 EDT 2016 by tim
Merge branch 'master' into work
-----------------------------------------------------------------------
No new revisions were added by this update.
--
Alioth's /usr/local/bin/git-commit-notice on /srv/git.debian.org/git/debian-science/packages/qflow.git
More information about the debian-science-commits
mailing list