r2641 - trunk/kernel/source/kernel-source-2.6.11-2.6.11/debian/patches
Sven Luther
luther@costa.debian.org
Tue, 08 Mar 2005 10:05:58 +0100
Author: luther
Date: 2005-03-08 10:05:56 +0100 (Tue, 08 Mar 2005)
New Revision: 2641
Modified:
trunk/kernel/source/kernel-source-2.6.11-2.6.11/debian/patches/powerpc-pegasos-marvell.dpatch
Log:
powerpc-pegasos-marvell patch was missing two header diffs :/
Modified: trunk/kernel/source/kernel-source-2.6.11-2.6.11/debian/patches/powerpc-pegasos-marvell.dpatch
===================================================================
--- trunk/kernel/source/kernel-source-2.6.11-2.6.11/debian/patches/powerpc-pegasos-marvell.dpatch 2005-03-08 07:40:13 UTC (rev 2640)
+++ trunk/kernel/source/kernel-source-2.6.11-2.6.11/debian/patches/powerpc-pegasos-marvell.dpatch 2005-03-08 09:05:56 UTC (rev 2641)
@@ -4150,3 +4150,1258 @@
config MV643XX_ETH_0
bool "MV-643XX Port 0"
+--- kernel-source-2.6.11/drivers/net/mv643xx_eth.h 2005-03-02 08:38:09.000000000 +0100
++++ linux-2.5-mv643xx-enet/drivers/net/mv643xx_eth.h 2005-03-07 14:15:29.000000000 +0100
+@@ -1,5 +1,5 @@
+-#ifndef __MV64340_ETH_H__
+-#define __MV64340_ETH_H__
++#ifndef __MV643XX_ETH_H__
++#define __MV643XX_ETH_H__
+
+ #include <linux/version.h>
+ #include <linux/module.h>
+@@ -46,17 +46,16 @@
+ * The first part is the high level driver of the gigE ethernet ports.
+ */
+
+-#define ETH_PORT0_IRQ_NUM 48 /* main high register, bit0 */
+-#define ETH_PORT1_IRQ_NUM ETH_PORT0_IRQ_NUM+1 /* main high register, bit1 */
+-#define ETH_PORT2_IRQ_NUM ETH_PORT0_IRQ_NUM+2 /* main high register, bit1 */
+-
+-/* Checksum offload for Tx works */
+-#define MV64340_CHECKSUM_OFFLOAD_TX
+-#define MV64340_NAPI
+-#define MV64340_TX_FAST_REFILL
+-#undef MV64340_COAL
++/* Checksum offload for Tx works for most packets, but
++ * fails if previous packet sent did not use hw csum
++ */
++#undef MV643XX_CHECKSUM_OFFLOAD_TX
++#define MV643XX_NAPI
++#define MV643XX_TX_FAST_REFILL
++#undef MV643XX_RX_QUEUE_FILL_ON_TASK /* Does not work, yet */
++#undef MV643XX_COAL
+
+-/*
++/*
+ * Number of RX / TX descriptors on RX / TX rings.
+ * Note that allocating RX descriptors is done by allocating the RX
+ * ring AND a preallocated RX buffers (skb's) for each descriptor.
+@@ -65,89 +64,35 @@
+ */
+
+ /* Default TX ring size is 1000 descriptors */
+-#define MV64340_TX_QUEUE_SIZE 1000
++#define MV643XX_DEFAULT_TX_QUEUE_SIZE 1000
+
+ /* Default RX ring size is 400 descriptors */
+-#define MV64340_RX_QUEUE_SIZE 400
++#define MV643XX_DEFAULT_RX_QUEUE_SIZE 400
+
+-#define MV64340_TX_COAL 100
+-#ifdef MV64340_COAL
+-#define MV64340_RX_COAL 100
++#define MV643XX_TX_COAL 100
++#ifdef MV643XX_COAL
++#define MV643XX_RX_COAL 100
+ #endif
+
+-
+ /*
+- * The second part is the low level driver of the gigE ethernet ports. *
++ * The second part is the low level driver of the gigE ethernet ports.
+ */
+
+-
+ /*
+- * Header File for : MV-643xx network interface header
++ * Header File for : MV-643xx network interface header
+ *
+ * DESCRIPTION:
+- * This header file contains macros typedefs and function declaration for
+- * the Marvell Gig Bit Ethernet Controller.
++ * This header file contains macros typedefs and function declaration for
++ * the Marvell Gig Bit Ethernet Controller.
+ *
+ * DEPENDENCIES:
+- * None.
++ * None.
+ *
+ */
+
+-/* Default port configuration value */
+-#define PORT_CONFIG_VALUE \
+- ETH_UNICAST_NORMAL_MODE | \
+- ETH_DEFAULT_RX_QUEUE_0 | \
+- ETH_DEFAULT_RX_ARP_QUEUE_0 | \
+- ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
+- ETH_RECEIVE_BC_IF_IP | \
+- ETH_RECEIVE_BC_IF_ARP | \
+- ETH_CAPTURE_TCP_FRAMES_DIS | \
+- ETH_CAPTURE_UDP_FRAMES_DIS | \
+- ETH_DEFAULT_RX_TCP_QUEUE_0 | \
+- ETH_DEFAULT_RX_UDP_QUEUE_0 | \
+- ETH_DEFAULT_RX_BPDU_QUEUE_0
+-
+-/* Default port extend configuration value */
+-#define PORT_CONFIG_EXTEND_VALUE \
+- ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
+- ETH_PARTITION_DISABLE
+-
+-
+-/* Default sdma control value */
+-#define PORT_SDMA_CONFIG_VALUE \
+- ETH_RX_BURST_SIZE_16_64BIT | \
+- GT_ETH_IPG_INT_RX(0) | \
+- ETH_TX_BURST_SIZE_16_64BIT;
+-
+-#define GT_ETH_IPG_INT_RX(value) \
+- ((value & 0x3fff) << 8)
+-
+-/* Default port serial control value */
+-#define PORT_SERIAL_CONTROL_VALUE \
+- ETH_FORCE_LINK_PASS | \
+- ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
+- ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
+- ETH_ADV_SYMMETRIC_FLOW_CTRL | \
+- ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
+- ETH_FORCE_BP_MODE_NO_JAM | \
+- BIT9 | \
+- ETH_DO_NOT_FORCE_LINK_FAIL | \
+- ETH_RETRANSMIT_16_ATTEMPTS | \
+- ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
+- ETH_DTE_ADV_0 | \
+- ETH_DISABLE_AUTO_NEG_BYPASS | \
+- ETH_AUTO_NEG_NO_CHANGE | \
+- ETH_MAX_RX_PACKET_9700BYTE | \
+- ETH_CLR_EXT_LOOPBACK | \
+- ETH_SET_FULL_DUPLEX_MODE | \
+- ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
+-
+-#define RX_BUFFER_MAX_SIZE 0x4000000
+-#define TX_BUFFER_MAX_SIZE 0x4000000
+-
+ /* MAC accepet/reject macros */
+-#define ACCEPT_MAC_ADDR 0
+-#define REJECT_MAC_ADDR 1
++#define ACCEPT_MAC_ADDR 0
++#define REJECT_MAC_ADDR 1
+
+ /* Buffer offset from buffer pointer */
+ #define RX_BUF_OFFSET 0x2
+@@ -155,277 +100,132 @@
+ /* Gigabit Ethernet Unit Global Registers */
+
+ /* MIB Counters register definitions */
+-#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
+-#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
+-#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
+-#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
+-#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
+-#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
+-#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
+-#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
+-#define ETH_MIB_FRAMES_64_OCTETS 0x20
+-#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
+-#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
+-#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
+-#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
+-#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
+-#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
+-#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
+-#define ETH_MIB_GOOD_FRAMES_SENT 0x40
+-#define ETH_MIB_EXCESSIVE_COLLISION 0x44
+-#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
+-#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
+-#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
+-#define ETH_MIB_FC_SENT 0x54
+-#define ETH_MIB_GOOD_FC_RECEIVED 0x58
+-#define ETH_MIB_BAD_FC_RECEIVED 0x5c
+-#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
+-#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
+-#define ETH_MIB_OVERSIZE_RECEIVED 0x68
+-#define ETH_MIB_JABBER_RECEIVED 0x6c
+-#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
+-#define ETH_MIB_BAD_CRC_EVENT 0x74
+-#define ETH_MIB_COLLISION 0x78
+-#define ETH_MIB_LATE_COLLISION 0x7c
++#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
++#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
++#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
++#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
++#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
++#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
++#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
++#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
++#define ETH_MIB_FRAMES_64_OCTETS 0x20
++#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
++#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
++#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
++#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
++#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
++#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
++#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
++#define ETH_MIB_GOOD_FRAMES_SENT 0x40
++#define ETH_MIB_EXCESSIVE_COLLISION 0x44
++#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
++#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
++#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
++#define ETH_MIB_FC_SENT 0x54
++#define ETH_MIB_GOOD_FC_RECEIVED 0x58
++#define ETH_MIB_BAD_FC_RECEIVED 0x5c
++#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
++#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
++#define ETH_MIB_OVERSIZE_RECEIVED 0x68
++#define ETH_MIB_JABBER_RECEIVED 0x6c
++#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
++#define ETH_MIB_BAD_CRC_EVENT 0x74
++#define ETH_MIB_COLLISION 0x78
++#define ETH_MIB_LATE_COLLISION 0x7c
+
+ /* Port serial status reg (PSR) */
+-#define ETH_INTERFACE_GMII_MII 0
+-#define ETH_INTERFACE_PCM BIT0
+-#define ETH_LINK_IS_DOWN 0
+-#define ETH_LINK_IS_UP BIT1
+-#define ETH_PORT_AT_HALF_DUPLEX 0
+-#define ETH_PORT_AT_FULL_DUPLEX BIT2
+-#define ETH_RX_FLOW_CTRL_DISABLED 0
+-#define ETH_RX_FLOW_CTRL_ENBALED BIT3
+-#define ETH_GMII_SPEED_100_10 0
+-#define ETH_GMII_SPEED_1000 BIT4
+-#define ETH_MII_SPEED_10 0
+-#define ETH_MII_SPEED_100 BIT5
+-#define ETH_NO_TX 0
+-#define ETH_TX_IN_PROGRESS BIT7
+-#define ETH_BYPASS_NO_ACTIVE 0
+-#define ETH_BYPASS_ACTIVE BIT8
+-#define ETH_PORT_NOT_AT_PARTITION_STATE 0
+-#define ETH_PORT_AT_PARTITION_STATE BIT9
+-#define ETH_PORT_TX_FIFO_NOT_EMPTY 0
+-#define ETH_PORT_TX_FIFO_EMPTY BIT10
+-
+-
+-/* These macros describes the Port configuration reg (Px_cR) bits */
+-#define ETH_UNICAST_NORMAL_MODE 0
+-#define ETH_UNICAST_PROMISCUOUS_MODE BIT0
+-#define ETH_DEFAULT_RX_QUEUE_0 0
+-#define ETH_DEFAULT_RX_QUEUE_1 BIT1
+-#define ETH_DEFAULT_RX_QUEUE_2 BIT2
+-#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1)
+-#define ETH_DEFAULT_RX_QUEUE_4 BIT3
+-#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1)
+-#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2)
+-#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1)
+-#define ETH_DEFAULT_RX_ARP_QUEUE_0 0
+-#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4
+-#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5
+-#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4)
+-#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6
+-#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4)
+-#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5)
+-#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4)
+-#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
+-#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7
+-#define ETH_RECEIVE_BC_IF_IP 0
+-#define ETH_REJECT_BC_IF_IP BIT8
+-#define ETH_RECEIVE_BC_IF_ARP 0
+-#define ETH_REJECT_BC_IF_ARP BIT9
+-#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12
+-#define ETH_CAPTURE_TCP_FRAMES_DIS 0
+-#define ETH_CAPTURE_TCP_FRAMES_EN BIT14
+-#define ETH_CAPTURE_UDP_FRAMES_DIS 0
+-#define ETH_CAPTURE_UDP_FRAMES_EN BIT15
+-#define ETH_DEFAULT_RX_TCP_QUEUE_0 0
+-#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16
+-#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17
+-#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16)
+-#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18
+-#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16)
+-#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17)
+-#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16)
+-#define ETH_DEFAULT_RX_UDP_QUEUE_0 0
+-#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19
+-#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20
+-#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19)
+-#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21
+-#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19)
+-#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20)
+-#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19)
+-#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0
+-#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22
+-#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23
+-#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22)
+-#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24
+-#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22)
+-#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23)
+-#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22)
+-
+-
+-/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
+-#define ETH_CLASSIFY_EN BIT0
+-#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
+-#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1
+-#define ETH_PARTITION_DISABLE 0
+-#define ETH_PARTITION_ENABLE BIT2
+-
+-
+-/* Tx/Rx queue command reg (RQCR/TQCR)*/
+-#define ETH_QUEUE_0_ENABLE BIT0
+-#define ETH_QUEUE_1_ENABLE BIT1
+-#define ETH_QUEUE_2_ENABLE BIT2
+-#define ETH_QUEUE_3_ENABLE BIT3
+-#define ETH_QUEUE_4_ENABLE BIT4
+-#define ETH_QUEUE_5_ENABLE BIT5
+-#define ETH_QUEUE_6_ENABLE BIT6
+-#define ETH_QUEUE_7_ENABLE BIT7
+-#define ETH_QUEUE_0_DISABLE BIT8
+-#define ETH_QUEUE_1_DISABLE BIT9
+-#define ETH_QUEUE_2_DISABLE BIT10
+-#define ETH_QUEUE_3_DISABLE BIT11
+-#define ETH_QUEUE_4_DISABLE BIT12
+-#define ETH_QUEUE_5_DISABLE BIT13
+-#define ETH_QUEUE_6_DISABLE BIT14
+-#define ETH_QUEUE_7_DISABLE BIT15
+-
+-
+-/* These macros describes the Port Sdma configuration reg (SDCR) bits */
+-#define ETH_RIFB BIT0
+-#define ETH_RX_BURST_SIZE_1_64BIT 0
+-#define ETH_RX_BURST_SIZE_2_64BIT BIT1
+-#define ETH_RX_BURST_SIZE_4_64BIT BIT2
+-#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1)
+-#define ETH_RX_BURST_SIZE_16_64BIT BIT3
+-#define ETH_BLM_RX_NO_SWAP BIT4
+-#define ETH_BLM_RX_BYTE_SWAP 0
+-#define ETH_BLM_TX_NO_SWAP BIT5
+-#define ETH_BLM_TX_BYTE_SWAP 0
+-#define ETH_DESCRIPTORS_BYTE_SWAP BIT6
+-#define ETH_DESCRIPTORS_NO_SWAP 0
+-#define ETH_TX_BURST_SIZE_1_64BIT 0
+-#define ETH_TX_BURST_SIZE_2_64BIT BIT22
+-#define ETH_TX_BURST_SIZE_4_64BIT BIT23
+-#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22)
+-#define ETH_TX_BURST_SIZE_16_64BIT BIT24
+-
+-
+-
+-/* These macros describes the Port serial control reg (PSCR) bits */
+-#define ETH_SERIAL_PORT_DISABLE 0
+-#define ETH_SERIAL_PORT_ENABLE BIT0
+-#define ETH_FORCE_LINK_PASS BIT1
+-#define ETH_DO_NOT_FORCE_LINK_PASS 0
+-#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
+-#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2
+-#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
+-#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3
+-#define ETH_ADV_NO_FLOW_CTRL 0
+-#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4
+-#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
+-#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5
+-#define ETH_FORCE_BP_MODE_NO_JAM 0
+-#define ETH_FORCE_BP_MODE_JAM_TX BIT7
+-#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8
+-#define ETH_FORCE_LINK_FAIL 0
+-#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10
+-#define ETH_RETRANSMIT_16_ATTEMPTS 0
+-#define ETH_RETRANSMIT_FOREVER BIT11
+-#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13
+-#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
+-#define ETH_DTE_ADV_0 0
+-#define ETH_DTE_ADV_1 BIT14
+-#define ETH_DISABLE_AUTO_NEG_BYPASS 0
+-#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15
+-#define ETH_AUTO_NEG_NO_CHANGE 0
+-#define ETH_RESTART_AUTO_NEG BIT16
+-#define ETH_MAX_RX_PACKET_1518BYTE 0
+-#define ETH_MAX_RX_PACKET_1522BYTE BIT17
+-#define ETH_MAX_RX_PACKET_1552BYTE BIT18
+-#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17)
+-#define ETH_MAX_RX_PACKET_9192BYTE BIT19
+-#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17)
+-#define ETH_SET_EXT_LOOPBACK BIT20
+-#define ETH_CLR_EXT_LOOPBACK 0
+-#define ETH_SET_FULL_DUPLEX_MODE BIT21
+-#define ETH_SET_HALF_DUPLEX_MODE 0
+-#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22
+-#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
+-#define ETH_SET_GMII_SPEED_TO_10_100 0
+-#define ETH_SET_GMII_SPEED_TO_1000 BIT23
+-#define ETH_SET_MII_SPEED_TO_10 0
+-#define ETH_SET_MII_SPEED_TO_100 BIT24
+-
++#define ETH_INTERFACE_GMII_MII 0
++#define ETH_INTERFACE_PCM BIT0
++#define ETH_LINK_IS_DOWN 0
++#define ETH_LINK_IS_UP BIT1
++#define ETH_PORT_AT_HALF_DUPLEX 0
++#define ETH_PORT_AT_FULL_DUPLEX BIT2
++#define ETH_RX_FLOW_CTRL_DISABLED 0
++#define ETH_RX_FLOW_CTRL_ENBALED BIT3
++#define ETH_GMII_SPEED_100_10 0
++#define ETH_GMII_SPEED_1000 BIT4
++#define ETH_MII_SPEED_10 0
++#define ETH_MII_SPEED_100 BIT5
++#define ETH_NO_TX 0
++#define ETH_TX_IN_PROGRESS BIT7
++#define ETH_BYPASS_NO_ACTIVE 0
++#define ETH_BYPASS_ACTIVE BIT8
++#define ETH_PORT_NOT_AT_PARTITION_STATE 0
++#define ETH_PORT_AT_PARTITION_STATE BIT9
++#define ETH_PORT_TX_FIFO_NOT_EMPTY 0
++#define ETH_PORT_TX_FIFO_EMPTY BIT10
++
++#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22)
++#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24
++#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22)
++#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23)
++#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22)
+
+ /* SMI reg */
+-#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */
+-#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */
++#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */
++#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */
+ #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */
+-#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */
++#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */
+
+ /* SDMA command status fields macros */
+
+ /* Tx & Rx descriptors status */
+-#define ETH_ERROR_SUMMARY (BIT0)
++#define ETH_ERROR_SUMMARY (BIT0)
+
+ /* Tx & Rx descriptors command */
+-#define ETH_BUFFER_OWNED_BY_DMA (BIT31)
++#define ETH_BUFFER_OWNED_BY_DMA (BIT31)
+
+ /* Tx descriptors status */
+-#define ETH_LC_ERROR (0 )
+-#define ETH_UR_ERROR (BIT1 )
+-#define ETH_RL_ERROR (BIT2 )
+-#define ETH_LLC_SNAP_FORMAT (BIT9 )
++#define ETH_LC_ERROR (0 )
++#define ETH_UR_ERROR (BIT1 )
++#define ETH_RL_ERROR (BIT2 )
++#define ETH_LLC_SNAP_FORMAT (BIT9 )
+
+ /* Rx descriptors status */
+-#define ETH_CRC_ERROR (0 )
+-#define ETH_OVERRUN_ERROR (BIT1 )
+-#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 )
+-#define ETH_RESOURCE_ERROR ((BIT2 | BIT1))
+-#define ETH_VLAN_TAGGED (BIT19)
+-#define ETH_BPDU_FRAME (BIT20)
+-#define ETH_TCP_FRAME_OVER_IP_V_4 (0 )
+-#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21)
+-#define ETH_OTHER_FRAME_TYPE (BIT22)
+-#define ETH_LAYER_2_IS_ETH_V_2 (BIT23)
+-#define ETH_FRAME_TYPE_IP_V_4 (BIT24)
+-#define ETH_FRAME_HEADER_OK (BIT25)
+-#define ETH_RX_LAST_DESC (BIT26)
+-#define ETH_RX_FIRST_DESC (BIT27)
+-#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28)
+-#define ETH_RX_ENABLE_INTERRUPT (BIT29)
+-#define ETH_LAYER_4_CHECKSUM_OK (BIT30)
++#define ETH_CRC_ERROR (0 )
++#define ETH_OVERRUN_ERROR (BIT1 )
++#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 )
++#define ETH_RESOURCE_ERROR ((BIT2 | BIT1))
++#define ETH_VLAN_TAGGED (BIT19)
++#define ETH_BPDU_FRAME (BIT20)
++#define ETH_TCP_FRAME_OVER_IP_V_4 (0 )
++#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21)
++#define ETH_OTHER_FRAME_TYPE (BIT22)
++#define ETH_LAYER_2_IS_ETH_V_2 (BIT23)
++#define ETH_FRAME_TYPE_IP_V_4 (BIT24)
++#define ETH_FRAME_HEADER_OK (BIT25)
++#define ETH_RX_LAST_DESC (BIT26)
++#define ETH_RX_FIRST_DESC (BIT27)
++#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28)
++#define ETH_RX_ENABLE_INTERRUPT (BIT29)
++#define ETH_LAYER_4_CHECKSUM_OK (BIT30)
+
+ /* Rx descriptors byte count */
+-#define ETH_FRAME_FRAGMENTED (BIT2)
++#define ETH_FRAME_FRAGMENTED (BIT2)
+
+ /* Tx descriptors command */
+ #define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10)
+-#define ETH_FRAME_SET_TO_VLAN (BIT15)
+-#define ETH_TCP_FRAME (0 )
+-#define ETH_UDP_FRAME (BIT16)
+-#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17)
+-#define ETH_GEN_IP_V_4_CHECKSUM (BIT18)
+-#define ETH_ZERO_PADDING (BIT19)
+-#define ETH_TX_LAST_DESC (BIT20)
+-#define ETH_TX_FIRST_DESC (BIT21)
+-#define ETH_GEN_CRC (BIT22)
+-#define ETH_TX_ENABLE_INTERRUPT (BIT23)
+-#define ETH_AUTO_MODE (BIT30)
++#define ETH_FRAME_SET_TO_VLAN (BIT15)
++#define ETH_TCP_FRAME (0 )
++#define ETH_UDP_FRAME (BIT16)
++#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17)
++#define ETH_GEN_IP_V_4_CHECKSUM (BIT18)
++#define ETH_ZERO_PADDING (BIT19)
++#define ETH_TX_LAST_DESC (BIT20)
++#define ETH_TX_FIRST_DESC (BIT21)
++#define ETH_GEN_CRC (BIT22)
++#define ETH_TX_ENABLE_INTERRUPT (BIT23)
++#define ETH_AUTO_MODE (BIT30)
+
+ /* typedefs */
+
+ typedef enum _eth_func_ret_status {
+- ETH_OK, /* Returned as expected. */
+- ETH_ERROR, /* Fundamental error. */
+- ETH_RETRY, /* Could not process request. Try later. */
+- ETH_END_OF_JOB, /* Ring has nothing to process. */
+- ETH_QUEUE_FULL, /* Ring resource error. */
+- ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
++ ETH_OK, /* Returned as expected. */
++ ETH_ERROR, /* Fundamental error. */
++ ETH_RETRY, /* Could not process request. Try later.*/
++ ETH_END_OF_JOB, /* Ring has nothing to process. */
++ ETH_QUEUE_FULL, /* Ring resource error. */
++ ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
+ } ETH_FUNC_RET_STATUS;
+
+ typedef enum _eth_target {
+@@ -441,66 +241,103 @@
+ */
+ #if defined(__BIG_ENDIAN)
+ struct eth_rx_desc {
+- u16 byte_cnt; /* Descriptor buffer byte count */
+- u16 buf_size; /* Buffer size */
+- u32 cmd_sts; /* Descriptor command status */
+- u32 next_desc_ptr; /* Next descriptor pointer */
+- u32 buf_ptr; /* Descriptor buffer pointer */
++ u16 byte_cnt; /* Descriptor buffer byte count */
++ u16 buf_size; /* Buffer size */
++ u32 cmd_sts; /* Descriptor command status */
++ u32 next_desc_ptr; /* Next descriptor pointer */
++ u32 buf_ptr; /* Descriptor buffer pointer */
+ };
+
+ struct eth_tx_desc {
+- u16 byte_cnt; /* buffer byte count */
+- u16 l4i_chk; /* CPU provided TCP checksum */
+- u32 cmd_sts; /* Command/status field */
+- u32 next_desc_ptr; /* Pointer to next descriptor */
+- u32 buf_ptr; /* pointer to buffer for this descriptor */
++ u16 byte_cnt; /* buffer byte count */
++ u16 l4i_chk; /* CPU provided TCP checksum */
++ u32 cmd_sts; /* Command/status field */
++ u32 next_desc_ptr; /* Pointer to next descriptor */
++ u32 buf_ptr; /* pointer to buffer for this descriptor*/
+ };
+
+ #elif defined(__LITTLE_ENDIAN)
+ struct eth_rx_desc {
+- u32 cmd_sts; /* Descriptor command status */
+- u16 buf_size; /* Buffer size */
+- u16 byte_cnt; /* Descriptor buffer byte count */
+- u32 buf_ptr; /* Descriptor buffer pointer */
+- u32 next_desc_ptr; /* Next descriptor pointer */
++ u32 cmd_sts; /* Descriptor command status */
++ u16 buf_size; /* Buffer size */
++ u16 byte_cnt; /* Descriptor buffer byte count */
++ u32 buf_ptr; /* Descriptor buffer pointer */
++ u32 next_desc_ptr; /* Next descriptor pointer */
+ };
+
+ struct eth_tx_desc {
+- u32 cmd_sts; /* Command/status field */
+- u16 l4i_chk; /* CPU provided TCP checksum */
+- u16 byte_cnt; /* buffer byte count */
+- u32 buf_ptr; /* pointer to buffer for this descriptor */
+- u32 next_desc_ptr; /* Pointer to next descriptor */
++ u32 cmd_sts; /* Command/status field */
++ u16 l4i_chk; /* CPU provided TCP checksum */
++ u16 byte_cnt; /* buffer byte count */
++ u32 buf_ptr; /* pointer to buffer for this descriptor*/
++ u32 next_desc_ptr; /* Pointer to next descriptor */
+ };
+ #else
+ #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
+ #endif
+
+-/* Unified struct for Rx and Tx operations. The user is not required to */
+-/* be familier with neither Tx nor Rx descriptors. */
++/* Unified struct for Rx and Tx operations. The user is not required to */
++/* be familier with neither Tx nor Rx descriptors. */
+ struct pkt_info {
+- unsigned short byte_cnt; /* Descriptor buffer byte count */
+- unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */
+- unsigned int cmd_sts; /* Descriptor command status */
+- dma_addr_t buf_ptr; /* Descriptor buffer pointer */
+- struct sk_buff * return_info; /* User resource return information */
++ unsigned short byte_cnt; /* Descriptor buffer byte count */
++ unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */
++ unsigned int cmd_sts; /* Descriptor command status */
++ dma_addr_t buf_ptr; /* Descriptor buffer pointer */
++ struct sk_buff *return_info; /* User resource return information */
+ };
+
+-
+ /* Ethernet port specific infomation */
+
+-struct mv64340_private {
+- int port_num; /* User Ethernet port number */
+- u8 port_mac_addr[6]; /* User defined port MAC address. */
+- u32 port_config; /* User port configuration value */
+- u32 port_config_extend; /* User port config extend value */
+- u32 port_sdma_config; /* User port SDMA config value */
+- u32 port_serial_control; /* User port serial control value */
+- u32 port_tx_queue_command; /* Port active Tx queues summary */
+- u32 port_rx_queue_command; /* Port active Rx queues summary */
++struct mv643xx_mib_counters {
++ u64 good_octets_received;
++ u32 bad_octets_received;
++ u32 internal_mac_transmit_err;
++ u32 good_frames_received;
++ u32 bad_frames_received;
++ u32 broadcast_frames_received;
++ u32 multicast_frames_received;
++ u32 frames_64_octets;
++ u32 frames_65_to_127_octets;
++ u32 frames_128_to_255_octets;
++ u32 frames_256_to_511_octets;
++ u32 frames_512_to_1023_octets;
++ u32 frames_1024_to_max_octets;
++ u64 good_octets_sent;
++ u32 good_frames_sent;
++ u32 excessive_collision;
++ u32 multicast_frames_sent;
++ u32 broadcast_frames_sent;
++ u32 unrec_mac_control_received;
++ u32 fc_sent;
++ u32 good_fc_received;
++ u32 bad_fc_received;
++ u32 undersize_received;
++ u32 fragments_received;
++ u32 oversize_received;
++ u32 jabber_received;
++ u32 mac_receive_error;
++ u32 bad_crc_event;
++ u32 collision;
++ u32 late_collision;
++};
++
++struct mv643xx_private {
++ int port_num; /* User Ethernet port number */
++ u8 port_mac_addr[6]; /* User defined port MAC address.*/
++ u32 port_config; /* User port configuration value*/
++ u32 port_config_extend; /* User port config extend value*/
++ u32 port_sdma_config; /* User port SDMA config value */
++ u32 port_serial_control; /* User port serial control value */
++ u32 port_tx_queue_command; /* Port active Tx queues summary*/
++ u32 port_rx_queue_command; /* Port active Rx queues summary*/
++
++ u32 rx_sram_addr; /* Base address of rx sram area */
++ u32 rx_sram_size; /* Size of rx sram area */
++ u32 tx_sram_addr; /* Base address of tx sram area */
++ u32 tx_sram_size; /* Size of tx sram area */
+
+- int rx_resource_err; /* Rx ring resource error flag */
+- int tx_resource_err; /* Tx ring resource error flag */
++ int rx_resource_err; /* Rx ring resource error flag */
++ int tx_resource_err; /* Tx ring resource error flag */
+
+ /* Tx/Rx rings managment indexes fields. For driver use */
+
+@@ -509,30 +346,32 @@
+
+ /* Next available and first returning Tx resource */
+ int tx_curr_desc_q, tx_used_desc_q;
+-#ifdef MV64340_CHECKSUM_OFFLOAD_TX
+- int tx_first_desc_q;
++#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
++ int tx_first_desc_q;
++ u32 tx_first_command;
+ #endif
+
+-#ifdef MV64340_TX_FAST_REFILL
+- u32 tx_clean_threshold;
++#ifdef MV643XX_TX_FAST_REFILL
++ u32 tx_clean_threshold;
+ #endif
+
+- volatile struct eth_rx_desc * p_rx_desc_area;
+- dma_addr_t rx_desc_dma;
+- unsigned int rx_desc_area_size;
+- struct sk_buff * rx_skb[MV64340_RX_QUEUE_SIZE];
+-
+- volatile struct eth_tx_desc * p_tx_desc_area;
+- dma_addr_t tx_desc_dma;
+- unsigned int tx_desc_area_size;
+- struct sk_buff * tx_skb[MV64340_TX_QUEUE_SIZE];
++ struct eth_rx_desc *p_rx_desc_area;
++ dma_addr_t rx_desc_dma;
++ unsigned int rx_desc_area_size;
++ struct sk_buff **rx_skb;
++
++ struct eth_tx_desc *p_tx_desc_area;
++ dma_addr_t tx_desc_dma;
++ unsigned int tx_desc_area_size;
++ struct sk_buff **tx_skb;
+
+- struct work_struct tx_timeout_task;
++ struct work_struct tx_timeout_task;
+
+ /*
+- * Former struct mv64340_eth_priv members start here
++ * Former struct mv643xx_eth_priv members start here
+ */
+ struct net_device_stats stats;
++ struct mv643xx_mib_counters mib_counters;
+ spinlock_t lock;
+ /* Size of Tx Ring per queue */
+ unsigned int tx_ring_size;
+@@ -544,13 +383,13 @@
+ unsigned int rx_ring_skbs;
+
+ /*
+- * rx_task used to fill RX ring out of bottom half context
++ * rx_task used to fill RX ring out of bottom half context
+ */
+ struct work_struct rx_task;
+
+- /*
+- * Used in case RX Ring is empty, which can be caused when
+- * system does not have resources (skb's)
++ /*
++ * Used in case RX Ring is empty, which can be caused when
++ * system does not have resources (skb's)
+ */
+ struct timer_list timeout;
+ long rx_task_busy __attribute__ ((aligned(SMP_CACHE_BYTES)));
+@@ -563,9 +402,9 @@
+ /* ethernet.h API list */
+
+ /* Port operation control routines */
+-static void eth_port_init(struct mv64340_private *mp);
++static void eth_port_init(struct mv643xx_private *mp);
+ static void eth_port_reset(unsigned int eth_port_num);
+-static int eth_port_start(struct mv64340_private *mp);
++static void eth_port_start(struct mv643xx_private *mp);
+
+ static void ethernet_set_config_reg(unsigned int eth_port_num,
+ unsigned int value);
+@@ -576,26 +415,24 @@
+ unsigned char *p_addr);
+
+ /* PHY and MIB routines */
+-static int ethernet_phy_reset(unsigned int eth_port_num);
++static void ethernet_phy_reset(unsigned int eth_port_num);
++
++static void eth_port_write_smi_reg(unsigned int eth_port_num,
++ unsigned int phy_reg, unsigned int value);
+
+-static int eth_port_write_smi_reg(unsigned int eth_port_num,
+- unsigned int phy_reg,
+- unsigned int value);
+-
+-static int eth_port_read_smi_reg(unsigned int eth_port_num,
+- unsigned int phy_reg,
+- unsigned int *value);
++static void eth_port_read_smi_reg(unsigned int eth_port_num,
++ unsigned int phy_reg, unsigned int *value);
+
+ static void eth_clear_mib_counters(unsigned int eth_port_num);
+
+ /* Port data flow control routines */
+-static ETH_FUNC_RET_STATUS eth_port_send(struct mv64340_private *mp,
+- struct pkt_info * p_pkt_info);
+-static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv64340_private *mp,
+- struct pkt_info * p_pkt_info);
+-static ETH_FUNC_RET_STATUS eth_port_receive(struct mv64340_private *mp,
+- struct pkt_info * p_pkt_info);
+-static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv64340_private *mp,
+- struct pkt_info * p_pkt_info);
++static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
++ struct pkt_info *p_pkt_info);
++static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv643xx_private *mp,
++ struct pkt_info *p_pkt_info);
++static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
++ struct pkt_info *p_pkt_info);
++static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
++ struct pkt_info *p_pkt_info);
+
+-#endif /* __MV64340_ETH_H__ */
++#endif /* __MV643XX_ETH_H__ */
+--- kernel-source-2.6.11/include/linux/mv643xx.h 2005-03-02 08:38:18.000000000 +0100
++++ linux-dale/include/linux/mv643xx.h 2005-03-08 09:51:00.000000000 +0100
+@@ -1,5 +1,5 @@
+ /*
+- * mv64340.h - MV-64340 Internal registers definition file.
++ * mv643xx.h - MV-643XX Internal registers definition file.
+ *
+ * Copyright 2002 Momentum Computer, Inc.
+ * Author: Matthew Dharm <mdharm@momenco.com>
+@@ -10,8 +10,8 @@
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+-#ifndef __ASM_MV64340_H
+-#define __ASM_MV64340_H
++#ifndef __ASM_MV643XX_H
++#define __ASM_MV643XX_H
+
+ #ifdef __MIPS__
+ #include <asm/addrspace.h>
+@@ -662,116 +662,119 @@
+ /* Ethernet Unit Registers */
+ /****************************************/
+
+-#define MV64340_ETH_PHY_ADDR_REG 0x2000
+-#define MV64340_ETH_SMI_REG 0x2004
+-#define MV64340_ETH_UNIT_DEFAULT_ADDR_REG 0x2008
+-#define MV64340_ETH_UNIT_DEFAULTID_REG 0x200c
+-#define MV64340_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080
+-#define MV64340_ETH_UNIT_INTERRUPT_MASK_REG 0x2084
+-#define MV64340_ETH_UNIT_INTERNAL_USE_REG 0x24fc
+-#define MV64340_ETH_UNIT_ERROR_ADDR_REG 0x2094
+-#define MV64340_ETH_BAR_0 0x2200
+-#define MV64340_ETH_BAR_1 0x2208
+-#define MV64340_ETH_BAR_2 0x2210
+-#define MV64340_ETH_BAR_3 0x2218
+-#define MV64340_ETH_BAR_4 0x2220
+-#define MV64340_ETH_BAR_5 0x2228
+-#define MV64340_ETH_SIZE_REG_0 0x2204
+-#define MV64340_ETH_SIZE_REG_1 0x220c
+-#define MV64340_ETH_SIZE_REG_2 0x2214
+-#define MV64340_ETH_SIZE_REG_3 0x221c
+-#define MV64340_ETH_SIZE_REG_4 0x2224
+-#define MV64340_ETH_SIZE_REG_5 0x222c
+-#define MV64340_ETH_HEADERS_RETARGET_BASE_REG 0x2230
+-#define MV64340_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234
+-#define MV64340_ETH_HIGH_ADDR_REMAP_REG_0 0x2280
+-#define MV64340_ETH_HIGH_ADDR_REMAP_REG_1 0x2284
+-#define MV64340_ETH_HIGH_ADDR_REMAP_REG_2 0x2288
+-#define MV64340_ETH_HIGH_ADDR_REMAP_REG_3 0x228c
+-#define MV64340_ETH_BASE_ADDR_ENABLE_REG 0x2290
+-#define MV64340_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2))
+-#define MV64340_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7))
+-#define MV64340_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10))
+-#define MV64340_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10))
+-#define MV64340_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10))
+-#define MV64340_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10))
+-#define MV64340_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10))
+-#define MV64340_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10))
+-#define MV64340_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10))
+-#define MV64340_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10))
+-#define MV64340_ETH_DSCP_0(port) (0x2420 + (port<<10))
+-#define MV64340_ETH_DSCP_1(port) (0x2424 + (port<<10))
+-#define MV64340_ETH_DSCP_2(port) (0x2428 + (port<<10))
+-#define MV64340_ETH_DSCP_3(port) (0x242c + (port<<10))
+-#define MV64340_ETH_DSCP_4(port) (0x2430 + (port<<10))
+-#define MV64340_ETH_DSCP_5(port) (0x2434 + (port<<10))
+-#define MV64340_ETH_DSCP_6(port) (0x2438 + (port<<10))
+-#define MV64340_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10))
+-#define MV64340_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10))
+-#define MV64340_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10))
+-#define MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10))
+-#define MV64340_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10))
+-#define MV64340_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10))
+-#define MV64340_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10))
+-#define MV64340_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10))
+-#define MV64340_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10))
+-#define MV64340_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10))
+-#define MV64340_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10))
+-#define MV64340_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10))
+-#define MV64340_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10))
+-#define MV64340_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10))
+-#define MV64340_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10)
+-#define MV64340_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10))
+-#define MV64340_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10))
+-#define MV64340_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10))
+-#define MV64340_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10))
+-#define MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10))
+-#define MV64340_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10))
+-#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10))
+-#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10))
+-#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10))
+-#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10))
+-#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10))
+-#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10))
+-#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10))
+-#define MV64340_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10))
+-#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10))
+-#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10))
+-#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10))
+-#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10))
+-#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10))
+-#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10))
+-#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10))
+-#define MV64340_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10))
+-#define MV64340_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10))
+-#define MV64340_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10))
+-#define MV64340_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10))
+-#define MV64340_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10))
+-#define MV64340_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10))
++#define MV643XX_ETH_SHARED_REGS 0x2000
++#define MV643XX_ETH_SHARED_REGS_SIZE 0x2000
++
++#define MV643XX_ETH_PHY_ADDR_REG 0x2000
++#define MV643XX_ETH_SMI_REG 0x2004
++#define MV643XX_ETH_UNIT_DEFAULT_ADDR_REG 0x2008
++#define MV643XX_ETH_UNIT_DEFAULTID_REG 0x200c
++#define MV643XX_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080
++#define MV643XX_ETH_UNIT_INTERRUPT_MASK_REG 0x2084
++#define MV643XX_ETH_UNIT_INTERNAL_USE_REG 0x24fc
++#define MV643XX_ETH_UNIT_ERROR_ADDR_REG 0x2094
++#define MV643XX_ETH_BAR_0 0x2200
++#define MV643XX_ETH_BAR_1 0x2208
++#define MV643XX_ETH_BAR_2 0x2210
++#define MV643XX_ETH_BAR_3 0x2218
++#define MV643XX_ETH_BAR_4 0x2220
++#define MV643XX_ETH_BAR_5 0x2228
++#define MV643XX_ETH_SIZE_REG_0 0x2204
++#define MV643XX_ETH_SIZE_REG_1 0x220c
++#define MV643XX_ETH_SIZE_REG_2 0x2214
++#define MV643XX_ETH_SIZE_REG_3 0x221c
++#define MV643XX_ETH_SIZE_REG_4 0x2224
++#define MV643XX_ETH_SIZE_REG_5 0x222c
++#define MV643XX_ETH_HEADERS_RETARGET_BASE_REG 0x2230
++#define MV643XX_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234
++#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_0 0x2280
++#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_1 0x2284
++#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_2 0x2288
++#define MV643XX_ETH_HIGH_ADDR_REMAP_REG_3 0x228c
++#define MV643XX_ETH_BASE_ADDR_ENABLE_REG 0x2290
++#define MV643XX_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2))
++#define MV643XX_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7))
++#define MV643XX_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10))
++#define MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10))
++#define MV643XX_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10))
++#define MV643XX_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10))
++#define MV643XX_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10))
++#define MV643XX_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10))
++#define MV643XX_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10))
++#define MV643XX_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10))
++#define MV643XX_ETH_DSCP_0(port) (0x2420 + (port<<10))
++#define MV643XX_ETH_DSCP_1(port) (0x2424 + (port<<10))
++#define MV643XX_ETH_DSCP_2(port) (0x2428 + (port<<10))
++#define MV643XX_ETH_DSCP_3(port) (0x242c + (port<<10))
++#define MV643XX_ETH_DSCP_4(port) (0x2430 + (port<<10))
++#define MV643XX_ETH_DSCP_5(port) (0x2434 + (port<<10))
++#define MV643XX_ETH_DSCP_6(port) (0x2438 + (port<<10))
++#define MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10))
++#define MV643XX_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10))
++#define MV643XX_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10))
++#define MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10))
++#define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10))
++#define MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10))
++#define MV643XX_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10))
++#define MV643XX_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10))
++#define MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10))
++#define MV643XX_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10))
++#define MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10))
++#define MV643XX_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10))
++#define MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10))
++#define MV643XX_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10))
++#define MV643XX_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10)
++#define MV643XX_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10))
++#define MV643XX_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10))
++#define MV643XX_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10))
++#define MV643XX_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10))
++#define MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10))
++#define MV643XX_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10))
++#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10))
++#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10))
++#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10))
++#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10))
++#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10))
++#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10))
++#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10))
++#define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10))
++#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10))
++#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10))
++#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10))
++#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10))
++#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10))
++#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10))
++#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10))
++#define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10))
++#define MV643XX_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10))
++#define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10))
++#define MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10))
++#define MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10))
++#define MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10))
+
+ /*******************************************/
+ /* CUNIT Registers */
+@@ -1085,4 +1088,221 @@
+ u32 brg_clk_freq;
+ };
+
+-#endif /* __ASM_MV64340_H */
++/* These macros describe Ethernet Port configuration reg (Px_cR) bits */
++#define MV643XX_ETH_UNICAST_NORMAL_MODE 0
++#define MV643XX_ETH_UNICAST_PROMISCUOUS_MODE (1<<0)
++#define MV643XX_ETH_DEFAULT_RX_QUEUE_0 0
++#define MV643XX_ETH_DEFAULT_RX_QUEUE_1 (1<<1)
++#define MV643XX_ETH_DEFAULT_RX_QUEUE_2 (1<<2)
++#define MV643XX_ETH_DEFAULT_RX_QUEUE_3 ((1<<2) | (1<<1))
++#define MV643XX_ETH_DEFAULT_RX_QUEUE_4 (1<<3)
++#define MV643XX_ETH_DEFAULT_RX_QUEUE_5 ((1<<3) | (1<<1))
++#define MV643XX_ETH_DEFAULT_RX_QUEUE_6 ((1<<3) | (1<<2))
++#define MV643XX_ETH_DEFAULT_RX_QUEUE_7 ((1<<3) | (1<<2) | (1<<1))
++#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_0 0
++#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_1 (1<<4)
++#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_2 (1<<5)
++#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_3 ((1<<5) | (1<<4))
++#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_4 (1<<6)
++#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_5 ((1<<6) | (1<<4))
++#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_6 ((1<<6) | (1<<5))
++#define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_7 ((1<<6) | (1<<5) | (1<<4))
++#define MV643XX_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
++#define MV643XX_ETH_REJECT_BC_IF_NOT_IP_OR_ARP (1<<7)
++#define MV643XX_ETH_RECEIVE_BC_IF_IP 0
++#define MV643XX_ETH_REJECT_BC_IF_IP (1<<8)
++#define MV643XX_ETH_RECEIVE_BC_IF_ARP 0
++#define MV643XX_ETH_REJECT_BC_IF_ARP (1<<9)
++#define MV643XX_ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY (1<<12)
++#define MV643XX_ETH_CAPTURE_TCP_FRAMES_DIS 0
++#define MV643XX_ETH_CAPTURE_TCP_FRAMES_EN (1<<14)
++#define MV643XX_ETH_CAPTURE_UDP_FRAMES_DIS 0
++#define MV643XX_ETH_CAPTURE_UDP_FRAMES_EN (1<<15)
++#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_0 0
++#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_1 (1<<16)
++#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_2 (1<<17)
++#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_3 ((1<<17) | (1<<16))
++#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_4 (1<<18)
++#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_5 ((1<<18) | (1<<16))
++#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_6 ((1<<18) | (1<<17))
++#define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_7 ((1<<18) | (1<<17) | (1<<16))
++#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_0 0
++#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_1 (1<<19)
++#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_2 (1<<20)
++#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_3 ((1<<20) | (1<<19))
++#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_4 ((1<<21)
++#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_5 ((1<<21) | (1<<19))
++#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_6 ((1<<21) | (1<<20))
++#define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_7 ((1<<21) | (1<<20) | (1<<19))
++#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_0 0
++#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_1 (1<<22)
++#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_2 (1<<23)
++#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_3 ((1<<23) | (1<<22))
++#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_4 (1<<24)
++#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_5 ((1<<24) | (1<<22))
++#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_6 ((1<<24) | (1<<23))
++#define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_7 ((1<<24) | (1<<23) | (1<<22))
++
++#define MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE \
++ MV643XX_ETH_UNICAST_NORMAL_MODE | \
++ MV643XX_ETH_DEFAULT_RX_QUEUE_0 | \
++ MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_0 | \
++ MV643XX_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
++ MV643XX_ETH_RECEIVE_BC_IF_IP | \
++ MV643XX_ETH_RECEIVE_BC_IF_ARP | \
++ MV643XX_ETH_CAPTURE_TCP_FRAMES_DIS | \
++ MV643XX_ETH_CAPTURE_UDP_FRAMES_DIS | \
++ MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_0 | \
++ MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_0 | \
++ MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_0
++
++/* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/
++#define MV643XX_ETH_CLASSIFY_EN (1<<0)
++#define MV643XX_ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
++#define MV643XX_ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1<<1)
++#define MV643XX_ETH_PARTITION_DISABLE 0
++#define MV643XX_ETH_PARTITION_ENABLE (1<<2)
++
++#define MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE \
++ MV643XX_ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
++ MV643XX_ETH_PARTITION_DISABLE
++
++/* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */
++#define MV643XX_ETH_RIFB (1<<0)
++#define MV643XX_ETH_RX_BURST_SIZE_1_64BIT 0
++#define MV643XX_ETH_RX_BURST_SIZE_2_64BIT (1<<1)
++#define MV643XX_ETH_RX_BURST_SIZE_4_64BIT (1<<2)
++#define MV643XX_ETH_RX_BURST_SIZE_8_64BIT ((1<<2) | (1<<1))
++#define MV643XX_ETH_RX_BURST_SIZE_16_64BIT (1<<3)
++#define MV643XX_ETH_BLM_RX_NO_SWAP (1<<4)
++#define MV643XX_ETH_BLM_RX_BYTE_SWAP 0
++#define MV643XX_ETH_BLM_TX_NO_SWAP (1<<5)
++#define MV643XX_ETH_BLM_TX_BYTE_SWAP 0
++#define MV643XX_ETH_DESCRIPTORS_BYTE_SWAP (1<<6)
++#define MV643XX_ETH_DESCRIPTORS_NO_SWAP 0
++#define MV643XX_ETH_TX_BURST_SIZE_1_64BIT 0
++#define MV643XX_ETH_TX_BURST_SIZE_2_64BIT (1<<22)
++#define MV643XX_ETH_TX_BURST_SIZE_4_64BIT (1<<23)
++#define MV643XX_ETH_TX_BURST_SIZE_8_64BIT ((1<<23) | (1<<22))
++#define MV643XX_ETH_TX_BURST_SIZE_16_64BIT (1<<24)
++
++#define MV643XX_ETH_IPG_INT_RX(value) ((value & 0x3fff) << 8)
++
++#define MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE \
++ MV643XX_ETH_RX_BURST_SIZE_4_64BIT | \
++ MV643XX_ETH_IPG_INT_RX(0) | \
++ MV643XX_ETH_TX_BURST_SIZE_4_64BIT
++
++/* These macros describe Ethernet Port serial control reg (PSCR) bits */
++#define MV643XX_ETH_SERIAL_PORT_DISABLE 0
++#define MV643XX_ETH_SERIAL_PORT_ENABLE (1<<0)
++#define MV643XX_ETH_FORCE_LINK_PASS (1<<1)
++#define MV643XX_ETH_DO_NOT_FORCE_LINK_PASS 0
++#define MV643XX_ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
++#define MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX (1<<2)
++#define MV643XX_ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
++#define MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1<<3)
++#define MV643XX_ETH_ADV_NO_FLOW_CTRL 0
++#define MV643XX_ETH_ADV_SYMMETRIC_FLOW_CTRL (1<<4)
++#define MV643XX_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
++#define MV643XX_ETH_FORCE_FC_MODE_TX_PAUSE_DIS (1<<5)
++#define MV643XX_ETH_FORCE_BP_MODE_NO_JAM 0
++#define MV643XX_ETH_FORCE_BP_MODE_JAM_TX (1<<7)
++#define MV643XX_ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1<<8)
++#define MV643XX_ETH_FORCE_LINK_FAIL 0
++#define MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL (1<<10)
++#define MV643XX_ETH_RETRANSMIT_16_ATTEMPTS 0
++#define MV643XX_ETH_RETRANSMIT_FOREVER (1<<11)
++#define MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII (1<<13)
++#define MV643XX_ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
++#define MV643XX_ETH_DTE_ADV_0 0
++#define MV643XX_ETH_DTE_ADV_1 (1<<14)
++#define MV643XX_ETH_DISABLE_AUTO_NEG_BYPASS 0
++#define MV643XX_ETH_ENABLE_AUTO_NEG_BYPASS (1<<15)
++#define MV643XX_ETH_AUTO_NEG_NO_CHANGE 0
++#define MV643XX_ETH_RESTART_AUTO_NEG (1<<16)
++#define MV643XX_ETH_MAX_RX_PACKET_1518BYTE 0
++#define MV643XX_ETH_MAX_RX_PACKET_1522BYTE (1<<17)
++#define MV643XX_ETH_MAX_RX_PACKET_1552BYTE (1<<18)
++#define MV643XX_ETH_MAX_RX_PACKET_9022BYTE ((1<<18) | (1<<17))
++#define MV643XX_ETH_MAX_RX_PACKET_9192BYTE (1<<19)
++#define MV643XX_ETH_MAX_RX_PACKET_9700BYTE ((1<<19) | (1<<17))
++#define MV643XX_ETH_SET_EXT_LOOPBACK (1<<20)
++#define MV643XX_ETH_CLR_EXT_LOOPBACK 0
++#define MV643XX_ETH_SET_FULL_DUPLEX_MODE (1<<21)
++#define MV643XX_ETH_SET_HALF_DUPLEX_MODE 0
++#define MV643XX_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1<<22)
++#define MV643XX_ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
++#define MV643XX_ETH_SET_GMII_SPEED_TO_10_100 0
++#define MV643XX_ETH_SET_GMII_SPEED_TO_1000 (1<<23)
++#define MV643XX_ETH_SET_MII_SPEED_TO_10 0
++#define MV643XX_ETH_SET_MII_SPEED_TO_100 (1<<24)
++
++#define MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE \
++ MV643XX_ETH_DO_NOT_FORCE_LINK_PASS | \
++ MV643XX_ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
++ MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
++ MV643XX_ETH_ADV_SYMMETRIC_FLOW_CTRL | \
++ MV643XX_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
++ MV643XX_ETH_FORCE_BP_MODE_NO_JAM | \
++ (1<<9) /* reserved */ | \
++ MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL | \
++ MV643XX_ETH_RETRANSMIT_16_ATTEMPTS | \
++ MV643XX_ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
++ MV643XX_ETH_DTE_ADV_0 | \
++ MV643XX_ETH_DISABLE_AUTO_NEG_BYPASS | \
++ MV643XX_ETH_AUTO_NEG_NO_CHANGE | \
++ MV643XX_ETH_MAX_RX_PACKET_9700BYTE | \
++ MV643XX_ETH_CLR_EXT_LOOPBACK | \
++ MV643XX_ETH_SET_FULL_DUPLEX_MODE | \
++ MV643XX_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
++
++/* These macros describe Ethernet Serial Status reg (PSR) bits */
++#define MV643XX_ETH_PORT_STATUS_MODE_10_BIT (1<<0)
++#define MV643XX_ETH_PORT_STATUS_LINK_UP (1<<1)
++#define MV643XX_ETH_PORT_STATUS_FULL_DUPLEX (1<<2)
++#define MV643XX_ETH_PORT_STATUS_FLOW_CONTROL (1<<3)
++#define MV643XX_ETH_PORT_STATUS_GMII_1000 (1<<4)
++#define MV643XX_ETH_PORT_STATUS_MII_100 (1<<5)
++/* PSR bit 6 is undocumented */
++#define MV643XX_ETH_PORT_STATUS_TX_IN_PROGRESS (1<<7)
++#define MV643XX_ETH_PORT_STATUS_AUTONEG_BYPASSED (1<<8)
++#define MV643XX_ETH_PORT_STATUS_PARTITION (1<<9)
++#define MV643XX_ETH_PORT_STATUS_TX_FIFO_EMPTY (1<<10)
++/* PSR bits 11-31 are reserved */
++
++#define MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
++#define MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
++
++#define MV643XX_ETH_DESC_SIZE 64
++
++#define MV643XX_ETH_SHARED_NAME "mv643xx_eth_shared"
++#define MV643XX_ETH_NAME "mv643xx_eth"
++
++struct mv643xx_eth_platform_data {
++ /*
++ * Non-values for mac_addr, phy_addr, port_config, etc.
++ * override the default value. Setting the corresponding
++ * force_* field, causes the default value to be overridden
++ * even when zero.
++ */
++ unsigned int force_phy_addr:1;
++ unsigned int force_port_config:1;
++ unsigned int force_port_config_extend:1;
++ unsigned int force_port_sdma_config:1;
++ unsigned int force_port_serial_control:1;
++ int phy_addr;
++ char *mac_addr; /* pointer to mac address */
++ u32 port_config;
++ u32 port_config_extend;
++ u32 port_sdma_config;
++ u32 port_serial_control;
++ u32 tx_queue_size;
++ u32 rx_queue_size;
++ u32 tx_sram_addr;
++ u32 tx_sram_size;
++ u32 rx_sram_addr;
++ u32 rx_sram_size;
++};
++
++#endif /* __ASM_MV643XX_H */