[SCM] Qt 4 packaging branch, experimental-snapshots, updated. debian/4.7.3-1-7-g0470728
Fathi Boudra
fabo at alioth.debian.org
Sat Jun 11 11:42:51 UTC 2011
The following commit has been merged in the experimental-snapshots branch:
commit 0cc201bdabe7559ed210ec8789f18daa59dda662
Author: Sune Vuorela <sune at vuorela.dk>
Date: Sat Mar 19 17:53:15 2011 +0100
armhf support, thanks markos
---
debian/changelog | 4 +
debian/patches/94_armv6_uname_entry.diff | 15 ++
debian/patches/95_neon_flags.patch | 18 ++
debian/patches/series | 3 +
...CC-intrinsics-for-armv6-atomic-operations.patch | 200 ++++++++++++++++++++
debian/rules | 4 +
6 files changed, 244 insertions(+), 0 deletions(-)
diff --git a/debian/changelog b/debian/changelog
index 3aaced7..b452c98 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,5 +1,9 @@
qt4-x11 (4:4.7.2-2) unstable; urgency=low
+ [ Konstantinos Margaritis ]
+ * armhf support. (Closes: #618670)
+ backport from Ubuntu:
+ * http://launchpadlibrarian.net/66374974/x-0003-Use-GCC-intrinsics-for-armv6-atomic-operations.patch
-- Sune Vuorela <sune at debian.org> Sat, 19 Mar 2011 13:12:51 +0100
diff --git a/debian/patches/94_armv6_uname_entry.diff b/debian/patches/94_armv6_uname_entry.diff
new file mode 100644
index 0000000..f8f215b
--- /dev/null
+++ b/debian/patches/94_armv6_uname_entry.diff
@@ -0,0 +1,15 @@
+Description: Add armv6 uname entry for armhf
+---
+
+--- a/configure 2011-03-10 15:25:58.000000000 +0200
++++ b/configure 2011-03-11 10:40:13.837312856 +0200
+@@ -182,6 +182,9 @@
+ armel)
+ UNAME_MACHINE="armv5tel"
+ ;;
++ armhf)
++ UNAME_MACHINE="armv6"
++ ;;
+ hppa)
+ UNAME_MACHINE="parisc64"
+ ;;
diff --git a/debian/patches/95_neon_flags.patch b/debian/patches/95_neon_flags.patch
new file mode 100644
index 0000000..882ac22
--- /dev/null
+++ b/debian/patches/95_neon_flags.patch
@@ -0,0 +1,18 @@
+## Description: add some description
+## Origin/Author: add some origin or author
+## Bug: bug URL
+Index: qt4-x11-4.7.2/src/gui/gui.pro
+===================================================================
+--- qt4-x11-4.7.2.orig/src/gui/gui.pro 2011-03-06 21:41:47.058276259 +0200
++++ qt4-x11-4.7.2/src/gui/gui.pro 2011-03-06 21:38:16.569232507 +0200
+@@ -65,9 +65,9 @@
+ neon:*-g++* {
+ DEFINES += QT_HAVE_NEON
+ HEADERS += $$NEON_HEADERS
+- SOURCES += $$NEON_SOURCES
+
+ DRAWHELPER_NEON_ASM_FILES = $$NEON_ASM
++ DRAWHELPER_NEON_ASM_FILES += $$NEON_SOURCES
+
+ neon_compiler.commands = $$QMAKE_CXX -c -mfpu=neon
+ neon_compiler.commands += $(CXXFLAGS) $(INCPATH) ${QMAKE_FILE_IN} -o ${QMAKE_FILE_OUT}
diff --git a/debian/patches/series b/debian/patches/series
index 1b6310d..5861215 100644
--- a/debian/patches/series
+++ b/debian/patches/series
@@ -31,5 +31,8 @@ buildable_appchooser_states_demos.patch
89_powerpc_opts.diff
91_s390_use_gstabs.diff
92_armel_gcc43_valist_compat.diff
+x-0003-Use-GCC-intrinsics-for-armv6-atomic-operations.patch
+94_armv6_uname_entry.diff
+95_neon_flags.patch
96_webkit_no_gc_sections.diff
99_hppa_bug561203_decrease_failure_rate.diff
diff --git a/debian/patches/x-0003-Use-GCC-intrinsics-for-armv6-atomic-operations.patch b/debian/patches/x-0003-Use-GCC-intrinsics-for-armv6-atomic-operations.patch
new file mode 100644
index 0000000..e7f7597
--- /dev/null
+++ b/debian/patches/x-0003-Use-GCC-intrinsics-for-armv6-atomic-operations.patch
@@ -0,0 +1,200 @@
+From 7aaf387cdb578327017169a9c97bcf6c0581a780 Mon Sep 17 00:00:00 2001
+From: michaedw in build chroot <build at ctbu-bld5.cisco.com>
+Date: Mon, 14 Mar 2011 01:52:46 +0000
+Subject: [PATCH] Use GCC intrinsics for armv6 atomic operations
+
+---
+ src/corelib/arch/qatomic_armv6.h | 146 +++++++------------------------------
+ 1 files changed, 28 insertions(+), 118 deletions(-)
+
+diff --git a/src/corelib/arch/qatomic_armv6.h b/src/corelib/arch/qatomic_armv6.h
+index 53f7907..7dfc002 100644
+--- a/src/corelib/arch/qatomic_armv6.h
++++ b/src/corelib/arch/qatomic_armv6.h
+@@ -104,155 +104,65 @@ Q_INLINE_TEMPLATE bool QBasicAtomicPointer<T>::isFetchAndAddWaitFree()
+
+ inline bool QBasicAtomicInt::ref()
+ {
+- register int newValue;
+- register int result;
+- asm volatile("0:
"
+- "ldrex %[newValue], [%[_q_value]]
"
+- "add %[newValue], %[newValue], #1
"
+- "strex %[result], %[newValue], [%[_q_value]]
"
+- "teq %[result], #0
"
+- "bne 0b
"
+- : [newValue] "=&r" (newValue),
+- [result] "=&r" (result),
+- "+m" (_q_value)
+- : [_q_value] "r" (&_q_value)
+- : "cc", "memory");
+- return newValue != 0;
++ return __sync_add_and_fetch(&_q_value, 1) != 0;
+ }
+
+ inline bool QBasicAtomicInt::deref()
+ {
+- register int newValue;
+- register int result;
+- asm volatile("0:
"
+- "ldrex %[newValue], [%[_q_value]]
"
+- "sub %[newValue], %[newValue], #1
"
+- "strex %[result], %[newValue], [%[_q_value]]
"
+- "teq %[result], #0
"
+- "bne 0b
"
+- : [newValue] "=&r" (newValue),
+- [result] "=&r" (result),
+- "+m" (_q_value)
+- : [_q_value] "r" (&_q_value)
+- : "cc", "memory");
+- return newValue != 0;
++ return __sync_sub_and_fetch(&_q_value, 1) != 0;
+ }
+
+ inline bool QBasicAtomicInt::testAndSetOrdered(int expectedValue, int newValue)
+ {
+- register int result;
+- asm volatile("0:
"
+- "ldrex %[result], [%[_q_value]]
"
+- "eors %[result], %[result], %[expectedValue]
"
+- "strexeq %[result], %[newValue], [%[_q_value]]
"
+- "teqeq %[result], #1
"
+- "beq 0b
"
+- : [result] "=&r" (result),
+- "+m" (_q_value)
+- : [expectedValue] "r" (expectedValue),
+- [newValue] "r" (newValue),
+- [_q_value] "r" (&_q_value)
+- : "cc", "memory");
+- return result == 0;
++ return __sync_bool_compare_and_swap(&_q_value, expectedValue, newValue);
+ }
+
+ inline int QBasicAtomicInt::fetchAndStoreOrdered(int newValue)
+ {
+- register int originalValue;
+- register int result;
+- asm volatile("0:
"
+- "ldrex %[originalValue], [%[_q_value]]
"
+- "strex %[result], %[newValue], [%[_q_value]]
"
+- "teq %[result], #0
"
+- "bne 0b
"
+- : [originalValue] "=&r" (originalValue),
+- [result] "=&r" (result),
+- "+m" (_q_value)
+- : [newValue] "r" (newValue),
+- [_q_value] "r" (&_q_value)
+- : "cc", "memory");
+- return originalValue;
++ if (!newValue)
++ return __sync_fetch_and_and(&_q_value, 0);
++ else
++ {
++ int expectedValue = 0;
++ int oldValue;
++ do {
++ oldValue = __sync_val_compare_and_swap(&_q_value, expectedValue, newValue);
++ } while (oldValue != expectedValue);
++ return oldValue;
++ }
+ }
+
+ inline int QBasicAtomicInt::fetchAndAddOrdered(int valueToAdd)
+ {
+- register int originalValue;
+- register int newValue;
+- register int result;
+- asm volatile("0:
"
+- "ldrex %[originalValue], [%[_q_value]]
"
+- "add %[newValue], %[originalValue], %[valueToAdd]
"
+- "strex %[result], %[newValue], [%[_q_value]]
"
+- "teq %[result], #0
"
+- "bne 0b
"
+- : [originalValue] "=&r" (originalValue),
+- [newValue] "=&r" (newValue),
+- [result] "=&r" (result),
+- "+m" (_q_value)
+- : [valueToAdd] "r" (valueToAdd),
+- [_q_value] "r" (&_q_value)
+- : "cc", "memory");
+- return originalValue;
++ return __sync_fetch_and_add(&_q_value, valueToAdd);
+ }
+
+ template <typename T>
+ Q_INLINE_TEMPLATE bool QBasicAtomicPointer<T>::testAndSetOrdered(T *expectedValue, T *newValue)
+ {
+- register T *result;
+- asm volatile("0:
"
+- "ldrex %[result], [%[_q_value]]
"
+- "eors %[result], %[result], %[expectedValue]
"
+- "strexeq %[result], %[newValue], [%[_q_value]]
"
+- "teqeq %[result], #1
"
+- "beq 0b
"
+- : [result] "=&r" (result),
+- "+m" (_q_value)
+- : [expectedValue] "r" (expectedValue),
+- [newValue] "r" (newValue),
+- [_q_value] "r" (&_q_value)
+- : "cc", "memory");
+- return result == 0;
++ return __sync_bool_compare_and_swap(&_q_value, expectedValue, newValue);
+ }
+
+ template <typename T>
+ Q_INLINE_TEMPLATE T *QBasicAtomicPointer<T>::fetchAndStoreOrdered(T *newValue)
+ {
+- register T *originalValue;
+- register int result;
+- asm volatile("0:
"
+- "ldrex %[originalValue], [%[_q_value]]
"
+- "strex %[result], %[newValue], [%[_q_value]]
"
+- "teq %[result], #0
"
+- "bne 0b
"
+- : [originalValue] "=&r" (originalValue),
+- [result] "=&r" (result),
+- "+m" (_q_value)
+- : [newValue] "r" (newValue),
+- [_q_value] "r" (&_q_value)
+- : "cc", "memory");
+- return originalValue;
++ if (!newValue)
++ return __sync_fetch_and_and(&_q_value, 0);
++ else
++ {
++ T* expectedValue = 0;
++ T* oldValue;
++ do {
++ oldValue = __sync_val_compare_and_swap(&_q_value, expectedValue, newValue);
++ } while (oldValue != expectedValue);
++ return oldValue;
++ }
+ }
+
+ template <typename T>
+ Q_INLINE_TEMPLATE T *QBasicAtomicPointer<T>::fetchAndAddOrdered(qptrdiff valueToAdd)
+ {
+- register T *originalValue;
+- register T *newValue;
+- register int result;
+- asm volatile("0:
"
+- "ldrex %[originalValue], [%[_q_value]]
"
+- "add %[newValue], %[originalValue], %[valueToAdd]
"
+- "strex %[result], %[newValue], [%[_q_value]]
"
+- "teq %[result], #0
"
+- "bne 0b
"
+- : [originalValue] "=&r" (originalValue),
+- [newValue] "=&r" (newValue),
+- [result] "=&r" (result),
+- "+m" (_q_value)
+- : [valueToAdd] "r" (valueToAdd * sizeof(T)),
+- [_q_value] "r" (&_q_value)
+- : "cc", "memory");
+- return originalValue;
++ return (T*) __sync_fetch_and_add((volatile int*) &_q_value, valueToAdd);
+ }
+
+ #else
+--
+1.7.0.4
+
diff --git a/debian/rules b/debian/rules
index 6a1c721..c0e58c4 100755
--- a/debian/rules
+++ b/debian/rules
@@ -35,6 +35,10 @@ ifeq ($(DEB_HOST_ARCH),arm)
extra_configure_opts += -DQT_QLOCALE_USES_FCVT
endif
+ifeq ($(DEB_HOST_ARCH),armhf)
+ extra_configure_opts += -arch armv6
+endif
+
ifeq ($(DEB_HOST_ARCH_OS),linux)
ifeq ($(DEB_HOST_ARCH),amd64)
platform_arg = linux-g++-64
--
Qt 4 packaging
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