[gcc-6] 337/401: * Update to SVN 20170109 (r244224) from the gcc-6-branch.

Ximin Luo infinity0 at debian.org
Wed Apr 5 15:50:35 UTC 2017


This is an automated email from the git hooks/post-receive script.

infinity0 pushed a commit to branch pu/reproducible_builds
in repository gcc-6.

commit 77ccab41e8edfd02602b219ac6b7a2de776a0abd
Author: doko <doko at 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca>
Date:   Mon Jan 9 12:40:25 2017 +0000

      * Update to SVN 20170109 (r244224) from the gcc-6-branch.
    
    
    git-svn-id: svn://anonscm.debian.org/gcccvs/branches/sid/gcc-6@9216 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca
---
 debian/changelog                |   6 +-
 debian/patches/svn-updates.diff | 662 +++++++++++++++++++++++++++++++++++++++-
 2 files changed, 660 insertions(+), 8 deletions(-)

diff --git a/debian/changelog b/debian/changelog
index f8d8af4..679a17d 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,12 +1,14 @@
 gcc-6 (6.3.0-3) UNRELEASED; urgency=medium
 
-  * Update to SVN 20170105 (r244102) from the gcc-6-branch.
+  * Update to SVN 20170109 (r244224) from the gcc-6-branch.
     - Fix PR tree-optimization/71055, PR driver/78863, PR translation/78745,
       PR tree-optimization/78886, PR tree-optimization/78428,
+      PR libstdc++/78956, PR libstdc++/78991, PR rtl-optimization/78255,
+      PR target/78041 (ARM).
   * Always configure sparc builds --with-cpu-32=ultrasparc (James Clark).
     Closes: #850250.
 
- -- Matthias Klose <doko at debian.org>  Thu, 05 Jan 2017 14:15:08 +0100
+ -- Matthias Klose <doko at debian.org>  Mon, 09 Jan 2017 13:38:04 +0100
 
 gcc-6 (6.3.0-2) unstable; urgency=medium
 
diff --git a/debian/patches/svn-updates.diff b/debian/patches/svn-updates.diff
index eed9ab9..345e489 100644
--- a/debian/patches/svn-updates.diff
+++ b/debian/patches/svn-updates.diff
@@ -1,10 +1,10 @@
-# DP: updates from the 6 branch upto 20170105 (r244102).
+# DP: updates from the 6 branch upto 20170109 (r244224).
 
 last_update()
 {
 	cat > ${dir}LAST_UPDATED <EOF
-Thu Jan  5 15:12:04 CET 2017
-Thu Jan  5 14:12:04 UTC 2017 (revision 244102)
+Mon Jan  9 13:27:17 CET 2017
+Mon Jan  9 12:27:17 UTC 2017 (revision 244224)
 EOF
 }
 
@@ -12,6 +12,229 @@ LANG=C svn diff svn://gcc.gnu.org/svn/gcc/tags/gcc_6_3_0_release svn://gcc.gnu.o
 	| sed -r 's,^--- (\S+)\t(\S+)(.*)$,--- a/src/\1\t\2,;s,^\+\+\+ (\S+)\t(\S+)(.*)$,+++ b/src/\1\t\2,' \
 	| awk '/^Index:.*\.(class|texi)/ {skip=1; next} /^Index:/ { skip=0 } skip==0'
 
+Index: libstdc++-v3/include/std/thread
+===================================================================
+--- a/src/libstdc++-v3/include/std/thread	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/include/std/thread	(.../branches/gcc-6-branch)
+@@ -119,6 +119,7 @@
+     // 2097.  packaged_task constructors should be constrained
+     thread(thread&) = delete;
+     thread(const thread&) = delete;
++    thread(const thread&&) = delete;
+ 
+     thread(thread&& __t) noexcept
+     { swap(__t); }
+Index: libstdc++-v3/include/bits/predefined_ops.h
+===================================================================
+--- a/src/libstdc++-v3/include/bits/predefined_ops.h	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/include/bits/predefined_ops.h	(.../branches/gcc-6-branch)
+@@ -42,6 +42,7 @@
+       operator()(_Iterator1 __it1, _Iterator2 __it2) const
+       { return *__it1 < *__it2; }
+   };
++
+   _GLIBCXX14_CONSTEXPR
+   inline _Iter_less_iter
+   __iter_less_iter()
+@@ -53,7 +54,7 @@
+       bool
+       operator()(_Iterator __it, _Value& __val) const
+       { return *__it < __val; }
+-    };
++  };
+ 
+   inline _Iter_less_val
+   __iter_less_val()
+@@ -69,7 +70,7 @@
+       bool
+       operator()(_Value& __val, _Iterator __it) const
+       { return __val < *__it; }
+-    };
++  };
+ 
+   inline _Val_less_iter
+   __val_less_iter()
+@@ -85,7 +86,7 @@
+       bool
+       operator()(_Iterator1 __it1, _Iterator2 __it2) const
+       { return *__it1 == *__it2; }
+-    };
++  };
+ 
+   inline _Iter_equal_to_iter
+   __iter_equal_to_iter()
+@@ -97,7 +98,7 @@
+       bool
+       operator()(_Iterator __it, _Value& __val) const
+       { return *__it == __val; }
+-    };
++  };
+ 
+   inline _Iter_equal_to_val
+   __iter_equal_to_val()
+@@ -111,7 +112,8 @@
+     struct _Iter_comp_iter
+     {
+       _Compare _M_comp;
+-      _GLIBCXX14_CONSTEXPR
++
++      explicit _GLIBCXX14_CONSTEXPR
+       _Iter_comp_iter(_Compare __comp)
+ 	: _M_comp(__comp)
+       { }
+@@ -134,6 +136,7 @@
+     {
+       _Compare _M_comp;
+ 
++      explicit
+       _Iter_comp_val(_Compare __comp)
+ 	: _M_comp(__comp)
+       { }
+@@ -159,6 +162,7 @@
+     {
+       _Compare _M_comp;
+ 
++      explicit
+       _Val_comp_iter(_Compare __comp)
+ 	: _M_comp(__comp)
+       { }
+@@ -184,6 +188,7 @@
+     {
+       _Value& _M_value;
+ 
++      explicit
+       _Iter_equals_val(_Value& __value)
+ 	: _M_value(__value)
+       { }
+@@ -204,6 +209,7 @@
+     {
+       typename std::iterator_traits<_Iterator1>::reference _M_ref;
+ 
++      explicit
+       _Iter_equals_iter(_Iterator1 __it1)
+ 	: _M_ref(*__it1)
+       { }
+@@ -224,6 +230,7 @@
+     {
+       _Predicate _M_pred;
+ 
++      explicit
+       _Iter_pred(_Predicate __pred)
+ 	: _M_pred(__pred)
+       { }
+@@ -286,6 +293,7 @@
+     {
+       _Predicate _M_pred;
+ 
++      explicit
+       _Iter_negate(_Predicate __pred)
+ 	: _M_pred(__pred)
+       { }
+Index: libstdc++-v3/ChangeLog
+===================================================================
+--- a/src/libstdc++-v3/ChangeLog	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/ChangeLog	(.../branches/gcc-6-branch)
+@@ -1,3 +1,21 @@
++2017-01-06  Jonathan Wakely  <jwakely at redhat.com>
++
++	Backport from mainline
++	2017-01-03  Jonathan Wakely  <jwakely at redhat.com>
++
++	PR libstdc++/78956
++	* include/std/thread (thread(const thread&&)): Add deleted
++	constructor.
++	* testsuite/30_threads/thread/cons/lwg2097.cc: New test.
++
++2017-01-06  Jonathan Wakely  <jwakely at redhat.com>
++
++	PR libstdc++/78991
++	* include/bits/predefined_ops.h (_Iter_comp_iter, _Iter_comp_val)
++	(_Val_comp_iter, _Iter_equals_val, _Iter_pred, _Iter_comp_to_val)
++	(_Iter_comp_to_iter, _Iter_negate): Make constructors explicit.
++	* testsuite/25_algorithms/sort/78991.cc: New test.
++
+ 2016-12-21  Release Manager
+ 
+ 	* GCC 6.3.0 released.
+Index: libstdc++-v3/testsuite/25_algorithms/sort/78991.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/25_algorithms/sort/78991.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/testsuite/25_algorithms/sort/78991.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,40 @@
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++// { dg-do compile { target c++14 } }
++
++// PR 78991
++// This failed to compile with Clang because the result_of expression causes
++// instantiation of _Iter_comp_iter::operator() outside the immediate context.
++
++#include <algorithm>
++
++struct function
++{
++  function() = default;
++
++  template<typename F, typename = std::result_of_t<F&(int, int)>>
++    function(F) { }
++
++  bool operator()(int x, int y) const { return x < y; }
++};
++
++int main()
++{
++  int a[2]{ 2, 1 };
++  std::sort(a, a+2, function{});
++}
+Index: libstdc++-v3/testsuite/30_threads/thread/cons/lwg2097.cc
+===================================================================
+--- a/src/libstdc++-v3/testsuite/30_threads/thread/cons/lwg2097.cc	(.../tags/gcc_6_3_0_release)
++++ b/src/libstdc++-v3/testsuite/30_threads/thread/cons/lwg2097.cc	(.../branches/gcc-6-branch)
+@@ -0,0 +1,29 @@
++// { dg-do compile { target c++11 } }
++// { dg-require-cstdint "" }
++// { dg-require-gthreads "" }
++
++// Copyright (C) 2017 Free Software Foundation, Inc.
++//
++// This file is part of the GNU ISO C++ Library.  This library is free
++// software; you can redistribute it and/or modify it under the
++// terms of the GNU General Public License as published by the
++// Free Software Foundation; either version 3, or (at your option)
++// any later version.
++
++// This library is distributed in the hope that it will be useful,
++// but WITHOUT ANY WARRANTY; without even the implied warranty of
++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++// GNU General Public License for more details.
++
++// You should have received a copy of the GNU General Public License along
++// with this library; see the file COPYING3.  If not see
++// <http://www.gnu.org/licenses/>.
++
++#include <thread>
++
++using std::thread;
++using std::is_constructible;
++
++static_assert( !is_constructible<thread, thread&>::value, "" );
++static_assert( !is_constructible<thread, const thread&>::value, "" );
++static_assert( !is_constructible<thread, const thread>::value, "" );
 Index: gcc/c/ChangeLog
 ===================================================================
 --- a/src/gcc/c/ChangeLog	(.../tags/gcc_6_3_0_release)
@@ -60,7 +283,23 @@ Index: gcc/DATESTAMP
 +++ b/src/gcc/DATESTAMP	(.../branches/gcc-6-branch)
 @@ -1 +1 @@
 -20161221
-+20170105
++20170109
+Index: gcc/postreload.c
+===================================================================
+--- a/src/gcc/postreload.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/postreload.c	(.../branches/gcc-6-branch)
+@@ -93,6 +93,11 @@
+   basic_block insn_bb = BLOCK_FOR_INSN (insn);
+   unsigned insn_bb_succs = EDGE_COUNT (insn_bb->succs);
+ 
++  /* If NO_FUNCTION_CSE has been set by the target, then we should not try
++     to cse function calls.  */
++  if (NO_FUNCTION_CSE && CALL_P (insn))
++    return false;
++
+   if (GET_CODE (body) == SET)
+     {
+       int count = 0;
 Index: gcc/tree-ssa-strlen.c
 ===================================================================
 --- a/src/gcc/tree-ssa-strlen.c	(.../tags/gcc_6_3_0_release)
@@ -142,7 +381,51 @@ Index: gcc/ChangeLog
 ===================================================================
 --- a/src/gcc/ChangeLog	(.../tags/gcc_6_3_0_release)
 +++ b/src/gcc/ChangeLog	(.../branches/gcc-6-branch)
-@@ -1,3 +1,67 @@
+@@ -1,3 +1,111 @@
++2017-01-09  Andre Vieira <andre.simoesdiasvieira at arm.com>
++
++	Backport from mainline
++	2016-12-09  Andre Vieira <andre.simoesdiasvieira at arm.com>
++
++	PR rtl-optimization/78255
++	* gcc/postreload.c (reload_cse_simplify): Do not CSE a function if
++	NO_FUNCTION_CSE is true.
++
++2017-01-06  Wilco Dijkstra  <wdijkstr at arm.com>
++
++	Backport from mainline
++	2016-10-25  Wilco Dijkstra  <wdijkstr at arm.com>
++
++	PR target/78041
++	* config/arm/neon.md (ashldi3_neon): Add "r 0 i" and "&r r i" variants.
++	Remove partial overlap check for shift by 1.
++	(ashldi3_neon): Likewise.
++
++2017-01-05  Kelvin Nilsen  <kelvin at gcc.gnu.org>
++
++	Backport from mainline
++	2016-07-22  Kelvin Nilsen  <kelvin at gcc.gnu.org>
++
++	* config/rs6000/rs6000.c (rs6000_option_override_internal): Add
++	comments to explain why certain error messages make mention of
++	undocumented options.
++	(rs6000_invalid_builtin): Change error messages to replace mention
++	of undocumented options with mention of the -mcpu=power9 option
++	that enables those undocumented options.
++	* config/rs6000/rs6000.h: Add macro definition of MASK_FLOAT128
++	and change the macro definition of RS6000_BTM_FLOAT128 to correct
++	an error that was discovered during the development of this patch.
++	* config/rs6000/rs6000.opt: Add the Undocumented qualifier to the
++	mpower9-fusion, mpower9-vector, mpower9-dform, and mmodulo entries.
++	* doc/extend.texi (PowerPC AltiVec Built-in Functions): Modify
++	descriptions of built-in functions so that they depend on
++	-mcpu=power9 instead of on the corresponding undocumented flags.
++	* doc/invoke.texi (Option Summary):  Remove all mention of newly
++	undocumented flags.
++	(IBM RS/6000 and PowerPC Options): Likewise.
++	* doc/md.texi (Constraints for Particuliar Machines): Remove all
++	mention of newly undocumented flags.
++
 +2017-01-05  Andreas Krebbel  <krebbel at linux.vnet.ibm.com>
 +
 +	Backport from mainline
@@ -210,6 +493,110 @@ Index: gcc/ChangeLog
  2016-12-21  Release Manager
  
  	* GCC 6.3.0 released.
+Index: gcc/testsuite/gcc.target/arm/pr78255-1.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/arm/pr78255-1.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/arm/pr78255-1.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,57 @@
++/* { dg-do run } */
++/* { dg-options "-O2" }  */
++
++#include <string.h>
++
++struct table_s
++    {
++    void (*fun0)
++        ( void );
++    void (*fun1)
++        ( void );
++    void (*fun2)
++        ( void );
++    void (*fun3)
++        ( void );
++    void (*fun4)
++        ( void );
++    void (*fun5)
++        ( void );
++    void (*fun6)
++        ( void );
++    void (*fun7)
++        ( void );
++    } table;
++
++void callback0(){__asm("mov r0, r0 \n\t");}
++void callback1(){__asm("mov r0, r0 \n\t");}
++void callback2(){__asm("mov r0, r0 \n\t");}
++void callback3(){__asm("mov r0, r0 \n\t");}
++void callback4(){__asm("mov r0, r0 \n\t");}
++
++void test (void) {
++    memset(&table, 0, sizeof table);
++
++    asm volatile ("" : : : "r3");
++
++    table.fun0 = callback0;
++    table.fun1 = callback1;
++    table.fun2 = callback2;
++    table.fun3 = callback3;
++    table.fun4 = callback4;
++    table.fun0();
++}
++
++void foo (void)
++{
++  __builtin_abort ();
++}
++
++int main (void)
++{
++  unsigned long p = (unsigned long) &foo;
++  asm volatile ("mov r3, %0" : : "r" (p));
++  test ();
++
++  return 0;
++}
+Index: gcc/testsuite/gcc.target/arm/pr78255-2.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/arm/pr78255-2.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/arm/pr78255-2.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,12 @@
++/* { dg-do compile } */
++/* { dg-options "-O2" }  */
++
++extern int bar (void *);
++
++int
++foo (void)
++{
++  return bar ((void*)bar);
++}
++
++/* { dg-final { scan-assembler "bl?\\s+bar" } } */
+Index: gcc/testsuite/gcc.target/arm/pr78041.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/arm/pr78041.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/arm/pr78041.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,20 @@
++/* { dg-require-effective-target arm_thumb2_ok } */
++/* { dg-require-effective-target arm_neon_ok } */
++/* { dg-options "-fno-inline -mthumb -O1 -mfpu=neon -w" } */
++
++extern void abort (void);
++
++register long long x asm ("r1");
++
++long long f (void)
++{
++  return x << 5;
++}
++
++int main ()
++{
++  x = 0x0100000001;
++  if (f () != 0x2000000020)
++    abort ();
++  return 0;
++}
 Index: gcc/testsuite/gcc.target/s390/litpool-str-1.c
 ===================================================================
 --- a/src/gcc/testsuite/gcc.target/s390/litpool-str-1.c	(.../tags/gcc_6_3_0_release)
@@ -237,6 +624,23 @@ Index: gcc/testsuite/gcc.target/s390/litpool-str-1.c
 +}
 +
 +/* { dg-final { scan-assembler-not "GOTOFF" } } */
+Index: gcc/testsuite/gcc.target/aarch64/pr78255.c
+===================================================================
+--- a/src/gcc/testsuite/gcc.target/aarch64/pr78255.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/testsuite/gcc.target/aarch64/pr78255.c	(.../branches/gcc-6-branch)
+@@ -0,0 +1,12 @@
++/* { dg-do compile } */
++/* { dg-options "-O2 -mcmodel=tiny" } */
++
++extern int bar (void *);
++
++int
++foo (void)
++{
++  return bar ((void *)bar);
++}
++
++/* { dg-final { scan-assembler "b\\s+bar" } } */
 Index: gcc/testsuite/gfortran.dg/fimplicit_none_2.f90
 ===================================================================
 --- a/src/gcc/testsuite/gfortran.dg/fimplicit_none_2.f90	(.../tags/gcc_6_3_0_release)
@@ -364,7 +768,33 @@ Index: gcc/testsuite/ChangeLog
 ===================================================================
 --- a/src/gcc/testsuite/ChangeLog	(.../tags/gcc_6_3_0_release)
 +++ b/src/gcc/testsuite/ChangeLog	(.../branches/gcc-6-branch)
-@@ -1,3 +1,60 @@
+@@ -1,3 +1,86 @@
++2017-01-09  Andre Vieira <andre.simoesdiasvieira at arm.com>
++
++	Backport from mainline
++	2016-12-20  Andre Vieira  <andre.simoesdiasvieira at arm.com>
++
++	* gcc.target/arm/pr78255-2.c: Fix to work for targets
++	that do not optimize for tailcall.
++
++2017-01-09  Andre Vieira <andre.simoesdiasvieira at arm.com>
++
++	Backport from mainline
++	2016-12-09  Andre Vieira <andre.simoesdiasvieira at arm.com>
++
++	PR rtl-optimization/78255
++	* gcc.target/aarch64/pr78255.c: New.
++	* gcc.target/arm/pr78255-1.c: New.
++	* gcc.target/arm/pr78255-2.c: New.
++
++2017-01-06  Wilco Dijkstra  <wdijkstr at arm.com>
++
++	Backport from mainline
++	2016-10-25  Wilco Dijkstra  <wdijkstr at arm.com>
++
++	PR target/78041
++	* gcc.target/arm/pr78041.c: New test.
++
 +2017-01-05  Andreas Krebbel  <krebbel at linux.vnet.ibm.com>
 +
 +	Backport from mainline
@@ -42081,3 +42511,223 @@ Index: gcc/config/i386/stringop.opt
 -
 -#undef DEF_ENUM
 -#undef DEF_ALG
+Index: gcc/config/rs6000/rs6000.opt
+===================================================================
+--- a/src/gcc/config/rs6000/rs6000.opt	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/rs6000/rs6000.opt	(.../branches/gcc-6-branch)
+@@ -602,7 +602,7 @@
+ Analyze and remove doubleword swaps from VSX computations.
+ 
+ mpower9-fusion
+-Target Report Mask(P9_FUSION) Var(rs6000_isa_flags)
++Target Undocumented Report Mask(P9_FUSION) Var(rs6000_isa_flags)
+ Fuse certain operations together for better performance on power9.
+ 
+ mpower9-misc
+@@ -610,7 +610,7 @@
+ Use/do not use certain scalar instructions added in ISA 3.0.
+ 
+ mpower9-vector
+-Target Report Mask(P9_VECTOR) Var(rs6000_isa_flags)
++Target Undocumented Report Mask(P9_VECTOR) Var(rs6000_isa_flags)
+ Use/do not use vector instructions added in ISA 3.0.
+ 
+ mpower9-dform-scalar
+@@ -622,7 +622,7 @@
+ Use/do not use vector register+offset memory instructions added in ISA 3.0.
+ 
+ mpower9-dform
+-Target Report Var(TARGET_P9_DFORM_BOTH) Init(-1) Save
++Target Undocumented Report Var(TARGET_P9_DFORM_BOTH) Init(-1) Save
+ Use/do not use register+offset memory instructions added in ISA 3.0.
+ 
+ mpower9-minmax
+@@ -634,7 +634,7 @@
+ Fuse medium/large code model toc references with the memory instruction.
+ 
+ mmodulo
+-Target Report Mask(MODULO) Var(rs6000_isa_flags)
++Target Undocumented Report Mask(MODULO) Var(rs6000_isa_flags)
+ Generate the integer modulo instructions.
+ 
+ mfloat128
+Index: gcc/config/rs6000/rs6000.c
+===================================================================
+--- a/src/gcc/config/rs6000/rs6000.c	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/rs6000/rs6000.c	(.../branches/gcc-6-branch)
+@@ -4190,6 +4190,10 @@
+     {
+       if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
+ 	{
++	  /* We prefer to not mention undocumented options in
++	     error messages.  However, if users have managed to select
++	     power9-fusion without selecting power8-fusion, they
++	     already know about undocumented flags.  */
+ 	  error ("-mpower9-fusion requires -mpower8-fusion");
+ 	  rs6000_isa_flags &= ~OPTION_MASK_P9_FUSION;
+ 	}
+@@ -4237,6 +4241,10 @@
+   /* ISA 3.0 vector instructions include ISA 2.07.  */
+   if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR)
+     {
++      /* We prefer to not mention undocumented options in
++	 error messages.  However, if users have managed to select
++	 power9-vector without selecting power8-vector, they
++	 already know about undocumented flags.  */
+       if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
+ 	error ("-mpower9-vector requires -mpower8-vector");
+       rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR;
+@@ -4264,6 +4272,10 @@
+   /* ISA 3.0 D-form instructions require p9-vector and upper-regs.  */
+   if ((TARGET_P9_DFORM_SCALAR || TARGET_P9_DFORM_VECTOR) && !TARGET_P9_VECTOR)
+     {
++      /* We prefer to not mention undocumented options in
++	 error messages.  However, if users have managed to select
++	 power9-dform without selecting power9-vector, they
++	 already know about undocumented flags.  */
+       if (rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR)
+ 	error ("-mpower9-dform requires -mpower9-vector");
+       rs6000_isa_flags &= ~(OPTION_MASK_P9_DFORM_SCALAR
+@@ -4272,6 +4284,10 @@
+ 
+   if (TARGET_P9_DFORM_SCALAR && !TARGET_UPPER_REGS_DF)
+     {
++      /* We prefer to not mention undocumented options in
++	 error messages.  However, if users have managed to select
++	 power9-dform without selecting upper-regs-df, they
++	 already know about undocumented flags.  */
+       if (rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_DF)
+ 	error ("-mpower9-dform requires -mupper-regs-df");
+       rs6000_isa_flags &= ~OPTION_MASK_P9_DFORM_SCALAR;
+@@ -15412,13 +15428,13 @@
+   else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0)
+     error ("Builtin function %s requires the -mpower8-vector option", name);
+   else if ((fnmask & RS6000_BTM_P9_VECTOR) != 0)
+-    error ("Builtin function %s requires the -mpower9-vector option", name);
++    error ("Builtin function %s requires the -mcpu=power9 option", name);
+   else if ((fnmask & (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
+ 	   == (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
+-    error ("Builtin function %s requires the -mpower9-misc and"
++    error ("Builtin function %s requires the -mcpu=power9 and"
+ 	   " -m64 options", name);
+   else if ((fnmask & RS6000_BTM_P9_MISC) == RS6000_BTM_P9_MISC)
+-    error ("Builtin function %s requires the -mpower9-misc option", name);
++    error ("Builtin function %s requires the -mcpu=power9 option", name);
+   else if ((fnmask & (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
+ 	   == (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
+     error ("Builtin function %s requires the -mhard-float and"
+Index: gcc/config/rs6000/rs6000.h
+===================================================================
+--- a/src/gcc/config/rs6000/rs6000.h	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/rs6000/rs6000.h	(.../branches/gcc-6-branch)
+@@ -635,6 +635,7 @@
+ #define MASK_DIRECT_MOVE		OPTION_MASK_DIRECT_MOVE
+ #define MASK_DLMZB			OPTION_MASK_DLMZB
+ #define MASK_EABI			OPTION_MASK_EABI
++#define MASK_FLOAT128			OPTION_MASK_FLOAT128
+ #define MASK_FPRND			OPTION_MASK_FPRND
+ #define MASK_P8_FUSION			OPTION_MASK_P8_FUSION
+ #define MASK_HARD_FLOAT			OPTION_MASK_HARD_FLOAT
+@@ -2718,7 +2719,7 @@
+ #define RS6000_BTM_HARD_FLOAT	MASK_SOFT_FLOAT	/* Hardware floating point.  */
+ #define RS6000_BTM_LDBL128	MASK_MULTIPLE	/* 128-bit long double.  */
+ #define RS6000_BTM_64BIT	MASK_64BIT	/* 64-bit addressing.  */
+-#define RS6000_BTM_FLOAT128	MASK_P9_VECTOR	/* IEEE 128-bit float.  */
++#define RS6000_BTM_FLOAT128	MASK_FLOAT128	/* IEEE 128-bit float.  */
+ 
+ #define RS6000_BTM_COMMON	(RS6000_BTM_ALTIVEC			\
+ 				 | RS6000_BTM_VSX			\
+Index: gcc/config/arm/neon.md
+===================================================================
+--- a/src/gcc/config/arm/neon.md	(.../tags/gcc_6_3_0_release)
++++ b/src/gcc/config/arm/neon.md	(.../branches/gcc-6-branch)
+@@ -1045,12 +1045,12 @@
+ )
+ 
+ (define_insn_and_split "ashldi3_neon"
+-  [(set (match_operand:DI 0 "s_register_operand"	    "= w, w,?&r,?r, ?w,w")
+-	(ashift:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, r, 0w,w")
+-		   (match_operand:SI 2 "general_operand"    "rUm, i,  r, i,rUm,i")))
+-   (clobber (match_scratch:SI 3				    "= X, X,?&r, X,  X,X"))
+-   (clobber (match_scratch:SI 4				    "= X, X,?&r, X,  X,X"))
+-   (clobber (match_scratch:DI 5				    "=&w, X,  X, X, &w,X"))
++  [(set (match_operand:DI 0 "s_register_operand"	    "= w, w,?&r,?r,?&r, ?w,w")
++	(ashift:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, 0,  r, 0w,w")
++		   (match_operand:SI 2 "general_operand"    "rUm, i,  r, i,  i,rUm,i")))
++   (clobber (match_scratch:SI 3				    "= X, X,?&r, X,  X,  X,X"))
++   (clobber (match_scratch:SI 4				    "= X, X,?&r, X,  X,  X,X"))
++   (clobber (match_scratch:DI 5				    "=&w, X,  X, X,  X, &w,X"))
+    (clobber (reg:CC_C CC_REGNUM))]
+   "TARGET_NEON"
+   "#"
+@@ -1082,9 +1082,11 @@
+       }
+     else
+       {
+-	if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1
+-	    && (!reg_overlap_mentioned_p (operands[0], operands[1])
+-		|| REGNO (operands[0]) == REGNO (operands[1])))
++	/* The shift expanders support either full overlap or no overlap.  */
++	gcc_assert (!reg_overlap_mentioned_p (operands[0], operands[1])
++		    || REGNO (operands[0]) == REGNO (operands[1]));
++
++	if (operands[2] == CONST1_RTX (SImode))
+ 	  /* This clobbers CC.  */
+ 	  emit_insn (gen_arm_ashldi3_1bit (operands[0], operands[1]));
+ 	else
+@@ -1093,8 +1095,8 @@
+       }
+     DONE;
+   }"
+-  [(set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")
+-   (set_attr "opt" "*,*,speed,speed,*,*")
++  [(set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")
++   (set_attr "opt" "*,*,speed,speed,speed,*,*")
+    (set_attr "type" "multiple")]
+ )
+ 
+@@ -1143,12 +1145,12 @@
+ ;; ashrdi3_neon
+ ;; lshrdi3_neon
+ (define_insn_and_split "<shift>di3_neon"
+-  [(set (match_operand:DI 0 "s_register_operand"	     "= w, w,?&r,?r,?w,?w")
+-	(RSHIFTS:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, r,0w, w")
+-		    (match_operand:SI 2 "reg_or_int_operand" "  r, i,  r, i, r, i")))
+-   (clobber (match_scratch:SI 3				     "=2r, X, &r, X,2r, X"))
+-   (clobber (match_scratch:SI 4				     "= X, X, &r, X, X, X"))
+-   (clobber (match_scratch:DI 5				     "=&w, X,  X, X,&w, X"))
++  [(set (match_operand:DI 0 "s_register_operand"	     "= w, w,?&r,?r,?&r,?w,?w")
++	(RSHIFTS:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, 0,  r,0w, w")
++		    (match_operand:SI 2 "reg_or_int_operand" "  r, i,  r, i,  i, r, i")))
++   (clobber (match_scratch:SI 3				     "=2r, X, &r, X,  X,2r, X"))
++   (clobber (match_scratch:SI 4				     "= X, X, &r, X,  X, X, X"))
++   (clobber (match_scratch:DI 5				     "=&w, X,  X, X, X,&w, X"))
+    (clobber (reg:CC CC_REGNUM))]
+   "TARGET_NEON"
+   "#"
+@@ -1184,9 +1186,11 @@
+       }
+     else
+       {
+-	if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1
+-	    && (!reg_overlap_mentioned_p (operands[0], operands[1])
+-		|| REGNO (operands[0]) == REGNO (operands[1])))
++	/* The shift expanders support either full overlap or no overlap.  */
++	gcc_assert (!reg_overlap_mentioned_p (operands[0], operands[1])
++		    || REGNO (operands[0]) == REGNO (operands[1]));
++
++	if (operands[2] == CONST1_RTX (SImode))
+ 	  /* This clobbers CC.  */
+ 	  emit_insn (gen_arm_<shift>di3_1bit (operands[0], operands[1]));
+ 	else
+@@ -1197,8 +1201,8 @@
+ 
+     DONE;
+   }"
+-  [(set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")
+-   (set_attr "opt" "*,*,speed,speed,*,*")
++  [(set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")
++   (set_attr "opt" "*,*,speed,speed,speed,*,*")
+    (set_attr "type" "multiple")]
+ )
+ 

-- 
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