[gcc-6] 338/401: - Fix build from Linaro branch with branch update
Ximin Luo
infinity0 at debian.org
Wed Apr 5 15:50:35 UTC 2017
This is an automated email from the git hooks/post-receive script.
infinity0 pushed a commit to branch pu/reproducible_builds
in repository gcc-6.
commit 51faf1c122f03a988cd9727e919ade801aa0c6ea
Author: doko <doko at 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca>
Date: Mon Jan 9 12:49:47 2017 +0000
- Fix build from Linaro branch with branch update
git-svn-id: svn://anonscm.debian.org/gcccvs/branches/sid/gcc-6@9217 6ca36cf4-e1d1-0310-8c6f-e303bb2178ca
---
debian/patches/gcc-linaro-r244161-revert.diff | 117 ++++++++++++++++++++++++++
debian/rules.patch | 1 +
2 files changed, 118 insertions(+)
diff --git a/debian/patches/gcc-linaro-r244161-revert.diff b/debian/patches/gcc-linaro-r244161-revert.diff
new file mode 100644
index 0000000..3a73a5d
--- /dev/null
+++ b/debian/patches/gcc-linaro-r244161-revert.diff
@@ -0,0 +1,117 @@
+# DP: Revert r244161, already backported to Linaro
+
+--- a/src/gcc/testsuite/gcc.target/arm/pr78041.c
++++ a/src/gcc/testsuite/gcc.target/arm/pr78041.c
+@@ -1,20 +0,0 @@
+-/* { dg-require-effective-target arm_thumb2_ok } */
+-/* { dg-require-effective-target arm_neon_ok } */
+-/* { dg-options "-fno-inline -mthumb -O1 -mfpu=neon -w" } */
+-
+-extern void abort (void);
+-
+-register long long x asm ("r1");
+-
+-long long f (void)
+-{
+- return x << 5;
+-}
+-
+-int main ()
+-{
+- x = 0x0100000001;
+- if (f () != 0x2000000020)
+- abort ();
+- return 0;
+-}
+--- a/src/gcc/config/arm/neon.md
++++ a/src/gcc/config/arm/neon.md
+@@ -1045,12 +1045,12 @@
+ )
+
+ (define_insn_and_split "ashldi3_neon"
+- [(set (match_operand:DI 0 "s_register_operand" "= w, w,?&r,?r,?&r, ?w,w")
+- (ashift:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, 0, r, 0w,w")
+- (match_operand:SI 2 "general_operand" "rUm, i, r, i, i,rUm,i")))
+- (clobber (match_scratch:SI 3 "= X, X,?&r, X, X, X,X"))
+- (clobber (match_scratch:SI 4 "= X, X,?&r, X, X, X,X"))
+- (clobber (match_scratch:DI 5 "=&w, X, X, X, X, &w,X"))
++ [(set (match_operand:DI 0 "s_register_operand" "= w, w,?&r,?r, ?w,w")
++ (ashift:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, r, 0w,w")
++ (match_operand:SI 2 "general_operand" "rUm, i, r, i,rUm,i")))
++ (clobber (match_scratch:SI 3 "= X, X,?&r, X, X,X"))
++ (clobber (match_scratch:SI 4 "= X, X,?&r, X, X,X"))
++ (clobber (match_scratch:DI 5 "=&w, X, X, X, &w,X"))
+ (clobber (reg:CC_C CC_REGNUM))]
+ "TARGET_NEON"
+ "#"
+@@ -1082,11 +1082,9 @@
+ }
+ else
+ {
+- /* The shift expanders support either full overlap or no overlap. */
+- gcc_assert (!reg_overlap_mentioned_p (operands[0], operands[1])
+- || REGNO (operands[0]) == REGNO (operands[1]));
+-
+- if (operands[2] == CONST1_RTX (SImode))
++ if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1
++ && (!reg_overlap_mentioned_p (operands[0], operands[1])
++ || REGNO (operands[0]) == REGNO (operands[1])))
+ /* This clobbers CC. */
+ emit_insn (gen_arm_ashldi3_1bit (operands[0], operands[1]));
+ else
+@@ -1095,8 +1093,8 @@
+ }
+ DONE;
+ }"
+- [(set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")
+- (set_attr "opt" "*,*,speed,speed,speed,*,*")
++ [(set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")
++ (set_attr "opt" "*,*,speed,speed,*,*")
+ (set_attr "type" "multiple")]
+ )
+
+@@ -1145,12 +1143,12 @@
+ ;; ashrdi3_neon
+ ;; lshrdi3_neon
+ (define_insn_and_split "<shift>di3_neon"
+- [(set (match_operand:DI 0 "s_register_operand" "= w, w,?&r,?r,?&r,?w,?w")
+- (RSHIFTS:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, 0, r,0w, w")
+- (match_operand:SI 2 "reg_or_int_operand" " r, i, r, i, i, r, i")))
+- (clobber (match_scratch:SI 3 "=2r, X, &r, X, X,2r, X"))
+- (clobber (match_scratch:SI 4 "= X, X, &r, X, X, X, X"))
+- (clobber (match_scratch:DI 5 "=&w, X, X, X, X,&w, X"))
++ [(set (match_operand:DI 0 "s_register_operand" "= w, w,?&r,?r,?w,?w")
++ (RSHIFTS:DI (match_operand:DI 1 "s_register_operand" " 0w, w, 0r, r,0w, w")
++ (match_operand:SI 2 "reg_or_int_operand" " r, i, r, i, r, i")))
++ (clobber (match_scratch:SI 3 "=2r, X, &r, X,2r, X"))
++ (clobber (match_scratch:SI 4 "= X, X, &r, X, X, X"))
++ (clobber (match_scratch:DI 5 "=&w, X, X, X,&w, X"))
+ (clobber (reg:CC CC_REGNUM))]
+ "TARGET_NEON"
+ "#"
+@@ -1186,11 +1184,9 @@
+ }
+ else
+ {
+- /* The shift expanders support either full overlap or no overlap. */
+- gcc_assert (!reg_overlap_mentioned_p (operands[0], operands[1])
+- || REGNO (operands[0]) == REGNO (operands[1]));
+-
+- if (operands[2] == CONST1_RTX (SImode))
++ if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1
++ && (!reg_overlap_mentioned_p (operands[0], operands[1])
++ || REGNO (operands[0]) == REGNO (operands[1])))
+ /* This clobbers CC. */
+ emit_insn (gen_arm_<shift>di3_1bit (operands[0], operands[1]));
+ else
+@@ -1201,8 +1197,8 @@
+
+ DONE;
+ }"
+- [(set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")
+- (set_attr "opt" "*,*,speed,speed,speed,*,*")
++ [(set_attr "arch" "neon_for_64bits,neon_for_64bits,*,*,avoid_neon_for_64bits,avoid_neon_for_64bits")
++ (set_attr "opt" "*,*,speed,speed,*,*")
+ (set_attr "type" "multiple")]
+ )
+
diff --git a/debian/rules.patch b/debian/rules.patch
index 23c98e7..b24a157 100644
--- a/debian/rules.patch
+++ b/debian/rules.patch
@@ -15,6 +15,7 @@ series_file ?= $(patchdir)/series
debian_patches = \
svn-updates \
libiberty-updates \
+ $(if $(with_linaro_branch),gcc-linaro-r244161-revert) \
$(if $(with_linaro_branch),gcc-linaro-r243646-revert) \
$(if $(with_linaro_branch),gcc-linaro) \
$(if $(with_linaro_branch),gcc-linaro-no-macros) \
--
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